diff --git a/CMakeLists.txt b/CMakeLists.txt deleted file mode 100644 index 481def8..0000000 --- a/CMakeLists.txt +++ /dev/null @@ -1,56 +0,0 @@ -#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE! -SET(CMAKE_SYSTEM_NAME Generic) -SET(CMAKE_SYSTEM_VERSION 1) -cmake_minimum_required(VERSION 3.7) - -# specify cross compilers and tools -SET(CMAKE_C_COMPILER_WORKS 1) -SET(CMAKE_C_COMPILER arm-none-eabi-gcc) -SET(CMAKE_CXX_COMPILER_WORKS 1) -SET(CMAKE_CXX_COMPILER arm-none-eabi-g++) -set(CMAKE_ASM_COMPILER arm-none-eabi-gcc) -set(CMAKE_AR arm-none-eabi-ar) -set(CMAKE_OBJCOPY arm-none-eabi-objcopy) -set(CMAKE_OBJDUMP arm-none-eabi-objdump) -set(SIZE arm-none-eabi-size) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32H750VBTx_FLASH.ld) - -#Uncomment for hardware floating point -SET(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv5-d16") -add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1) - -#Uncomment for software floating point -#SET(FPU_FLAGS "-mfloat-abi=soft") - -SET(COMMON_FLAGS - "-mcpu=cortex-m7 ${FPU_FLAGS} -mthumb -mthumb-interwork -ffunction-sections -fdata-sections \ - -g -fno-common -fmessage-length=0 -specs=nosys.specs -specs=nano.specs") - -SET(CMAKE_CXX_FLAGS_INIT "${COMMON_FLAGS} -std=c++11") -SET(CMAKE_C_FLAGS_INIT "${COMMON_FLAGS} -std=gnu99") -SET(CMAKE_EXE_LINKER_FLAGS_INIT "-Wl,-gc-sections,--print-memory-usage -T ${LINKER_SCRIPT}") - -PROJECT(STM32H750VB_Bootloader C CXX ASM) -set(CMAKE_CXX_STANDARD 11) - -#add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1) -add_definitions(-D__weak=__attribute__\(\(weak\)\) -D__packed=__attribute__\(\(__packed__\)\) -DUSE_HAL_DRIVER -DSTM32H750xx) - -file(GLOB_RECURSE SOURCES "USB_DEVICE/*.*" "Middlewares/*.*" "startup/*.*" "Drivers/*.*" "Core/*.*") - -include_directories(Core/Inc Drivers/STM32H7xx_HAL_Driver/Inc Drivers/STM32H7xx_HAL_Driver/Inc/Legacy Drivers/CMSIS/Device/ST/STM32H7xx/Include Drivers/CMSIS/Include USB_DEVICE/App USB_DEVICE/Target Middlewares/ST/STM32_USB_Device_Library/Core/Inc Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc) - -add_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT}) - -set(CMAKE_EXE_LINKER_FLAGS - "${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map") - -set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex) -set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin) - -add_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD - COMMAND ${CMAKE_OBJCOPY} -Oihex $ ${HEX_FILE} - COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${BIN_FILE} - COMMENT "Building ${HEX_FILE} -Building ${BIN_FILE}") diff --git a/CMakeLists_template.txt b/CMakeLists_template.txt deleted file mode 100644 index 954e98f..0000000 --- a/CMakeLists_template.txt +++ /dev/null @@ -1,56 +0,0 @@ -#${templateWarning} -SET(CMAKE_SYSTEM_NAME Generic) -SET(CMAKE_SYSTEM_VERSION 1) -cmake_minimum_required(VERSION 3.7) - -# specify cross compilers and tools -SET(CMAKE_C_COMPILER_WORKS 1) -SET(CMAKE_C_COMPILER arm-none-eabi-gcc) -SET(CMAKE_CXX_COMPILER_WORKS 1) -SET(CMAKE_CXX_COMPILER arm-none-eabi-g++) -set(CMAKE_ASM_COMPILER arm-none-eabi-gcc) -set(CMAKE_AR arm-none-eabi-ar) -set(CMAKE_OBJCOPY arm-none-eabi-objcopy) -set(CMAKE_OBJDUMP arm-none-eabi-objdump) -set(SIZE arm-none-eabi-size) - -SET(LINKER_SCRIPT $${CMAKE_SOURCE_DIR}/${linkerScript}) - -#Uncomment for hardware floating point -SET(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv5-d16") -add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1) - -#Uncomment for software floating point -#SET(FPU_FLAGS "-mfloat-abi=soft") - -SET(COMMON_FLAGS - "-mcpu=${mcpu} $${FPU_FLAGS} -mthumb -mthumb-interwork -ffunction-sections -fdata-sections \ - -g -fno-common -fmessage-length=0 ${linkerFlags}") - -SET(CMAKE_CXX_FLAGS_INIT "$${COMMON_FLAGS} -std=c++11") -SET(CMAKE_C_FLAGS_INIT "$${COMMON_FLAGS} -std=gnu99") -SET(CMAKE_EXE_LINKER_FLAGS_INIT "-Wl,-gc-sections,--print-memory-usage -T $${LINKER_SCRIPT}") - -PROJECT(${projectName} C CXX ASM) -set(CMAKE_CXX_STANDARD 11) - -#add_definitions(-DARM_MATH_CM4 -DARM_MATH_MATRIX_CHECK -DARM_MATH_ROUNDING -D__FPU_PRESENT=1) -add_definitions(${defines}) - -file(GLOB_RECURSE SOURCES ${sources}) - -include_directories(${includes}) - -add_executable($${PROJECT_NAME}.elf $${SOURCES} $${LINKER_SCRIPT}) - -set(CMAKE_EXE_LINKER_FLAGS - "$${CMAKE_EXE_LINKER_FLAGS} -Wl,-Map=$${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.map") - -set(HEX_FILE $${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.hex) -set(BIN_FILE $${PROJECT_BINARY_DIR}/$${PROJECT_NAME}.bin) - -add_custom_command(TARGET $${PROJECT_NAME}.elf POST_BUILD - COMMAND $${CMAKE_OBJCOPY} -Oihex $ $${HEX_FILE} - COMMAND $${CMAKE_OBJCOPY} -Obinary $ $${BIN_FILE} - COMMENT "Building $${HEX_FILE} -Building $${BIN_FILE}") diff --git a/Core/Inc/flash_config.h b/Core/Inc/flash_config.h new file mode 100644 index 0000000..6b06411 --- /dev/null +++ b/Core/Inc/flash_config.h @@ -0,0 +1,7 @@ +#ifndef __FLASH_CONFIG_H +#define __FLASH_CONFIG_H + +#define USE_QPI_MODE 1 +#define QPI_HIGH_SPEED 0 + +#endif \ No newline at end of file diff --git a/Core/Inc/main.h b/Core/Inc/main.h index 8c3800e..74773d9 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -33,6 +33,9 @@ extern "C" { /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "pin_config.h" +#include "flash_config.h" + /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ diff --git a/Core/Inc/pin_config.h b/Core/Inc/pin_config.h new file mode 100644 index 0000000..3e1c4d3 --- /dev/null +++ b/Core/Inc/pin_config.h @@ -0,0 +1,12 @@ +#ifndef __PIN_CONFIG_H +#define __PIN_CONFIG_H + +#define LED_PORT GPIOA +#define LED_PIN GPIO_PIN_1 + +#define BTN_PORT GPIOE +#define BTN_PIN GPIO_PIN_3 + +#define BTN_INACTIVE_STATE GPIO_PIN_SET + +#endif \ No newline at end of file diff --git a/Core/Inc/stm32h7xx_hal_conf.h b/Core/Inc/stm32h7xx_hal_conf.h index 3800a87..497d5bd 100644 --- a/Core/Inc/stm32h7xx_hal_conf.h +++ b/Core/Inc/stm32h7xx_hal_conf.h @@ -15,11 +15,11 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32H7xx_HAL_CONF_H -#define __STM32H7xx_HAL_CONF_H +#ifndef STM32H7xx_HAL_CONF_H +#define STM32H7xx_HAL_CONF_H #ifdef __cplusplus extern "C" { @@ -30,14 +30,16 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED +#define HAL_MODULE_ENABLED /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_FMAC_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ @@ -46,12 +48,17 @@ /* #define HAL_ETH_MODULE_ENABLED */ /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ /* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ /* #define HAL_JPEG_MODULE_ENABLED */ /* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ @@ -78,6 +85,8 @@ /* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_JPEG_MODULE_ENABLED */ /* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_MDMA_MODULE_ENABLED @@ -93,14 +102,14 @@ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)1000U) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -110,11 +119,11 @@ #if !defined (CSI_VALUE) #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* CSI_VALUE */ - + /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ @@ -132,10 +141,16 @@ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ @@ -147,47 +162,60 @@ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section - */ + */ #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ #define USE_RTOS 0U -#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */ +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 0U /*!< use CRC in SPI */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ #define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ #define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ #define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ /* ########################### Ethernet Configuration ######################### */ @@ -203,14 +231,14 @@ /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ -/* #define USE_FULL_ASSERT 1U */ +/* #define USE_FULL_ASSERT 1U */ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -277,6 +305,10 @@ #include "stm32h7xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32h7xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ @@ -293,6 +325,14 @@ #include "stm32h7xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32h7xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + #ifdef HAL_HRTIM_MODULE_ENABLED #include "stm32h7xx_hal_hrtim.h" #endif /* HAL_HRTIM_MODULE_ENABLED */ @@ -349,6 +389,14 @@ #include "stm32h7xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED #include "stm32h7xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ @@ -428,22 +476,30 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32h7xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else - #define assert_param(expr) ((void)0) + #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus @@ -451,6 +507,5 @@ #endif #endif /* __STM32H7xx_HAL_CONF_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32h7xx_it.h b/Core/Inc/stm32h7xx_it.h index 81e7fbe..84d261c 100644 --- a/Core/Inc/stm32h7xx_it.h +++ b/Core/Inc/stm32h7xx_it.h @@ -24,7 +24,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/Core/Inc/w25_qspi.h b/Core/Inc/w25_qspi.h index 9d2b5bc..b711c8d 100644 --- a/Core/Inc/w25_qspi.h +++ b/Core/Inc/w25_qspi.h @@ -11,12 +11,17 @@ #define W25_CMD_WRITE_VOLATILE_ENABLE 0x50 #define W25_CMD_PAGE_PROGRAM 0x02 #define W25_CMD_PAGE_PROGRAM_QUAD 0x32 +#define W25_CMD_QPI_ENABLE 0x38 +#define W25_CMD_QPI_DISABLE 0xFF #define W25_CMD_READ 0x03 #define W25_CMD_READ_QUAD 0x6B #define W25_CMD_SECTOR_ERASE 0x20 #define W25_CMD_READ_STATUS_1 0x05 +#define W25_CMD_READ_STATUS_2 0x35 +#define W25_CMD_WRITE_STATUS_2 0x31 #define W25_CMD_READ_JEDEC_ID 0x9F #define W25_CMD_READ_MFG_DEV_ID 0x90 +#define W25_CMD_QPI_READ_PARAMS 0xC0 typedef enum { W25_MODE_SINGLE, @@ -29,6 +34,20 @@ typedef enum { W25_ADDRESS_32BITS } w25_address_size_t; +typedef enum { + W25_QPI_DUMMY_2 = 0, + W25_QPI_DUMMY_4, + W25_QPI_DUMMY_6, + W25_QPI_DUMMY_8 +} w25_qpi_dummy_t; + +typedef enum { + W25_QPI_WRAP_LENGTH_8 = 0, + W25_QPI_WRAP_LENGTH_16, + W25_QPI_WRAP_LENGTH_32, + W25_QPI_WRAP_LENGTH_64 +} w25_qpi_wrap_t; + typedef struct { QSPI_HandleTypeDef *interface; w25_mode_t mode; @@ -42,5 +61,8 @@ HAL_StatusTypeDef W25_QSPI_Init(w25_qspi_t *flash); HAL_StatusTypeDef W25_QSPI_Erase_Sector(w25_qspi_t *flash, uint32_t address); HAL_StatusTypeDef W25_QSPI_Program_Page(w25_qspi_t *flash, uint32_t address, uint8_t *data); HAL_StatusTypeDef W25_QSPI_Read(w25_qspi_t *flash, uint32_t address, uint8_t *data, uint32_t length); +HAL_StatusTypeDef W25_QSPI_QuadEnable(w25_qspi_t *flash, uint8_t permanent); +HAL_StatusTypeDef W25_QPI_Mode(w25_qspi_t *flash, uint8_t enable); +HAL_StatusTypeDef W25_QPI_ReadParams(w25_qspi_t *flash, w25_qpi_dummy_t dummy_clocks, w25_qpi_wrap_t wrap_length); #endif //STM32H750VB_BOOTLOADER_W25_QSPI_H diff --git a/Core/Src/bootloader_control.c b/Core/Src/bootloader_control.c index fa2e129..cf4d578 100644 --- a/Core/Src/bootloader_control.c +++ b/Core/Src/bootloader_control.c @@ -22,7 +22,6 @@ uint32_t BL_GetEntryPoint(uint32_t base_address) { void BL_JumpToXIPStart(uint32_t entry_point, uint32_t vector_base) { __disable_irq(); - SCB->VTOR = vector_base; SysTick->CTRL = 0; SysTick->LOAD = 0; SysTick->VAL = 0; diff --git a/Core/Src/main.c b/Core/Src/main.c index a4744f1..db1dc9c 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -17,7 +17,6 @@ ****************************************************************************** */ /* USER CODE END Header */ - /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "usb_device.h" @@ -28,6 +27,7 @@ #include "printf.h" #include "bootloader_control.h" #include "w25_qspi.h" + /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -79,10 +79,6 @@ int main(void) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - - - /* Enable I-Cache---------------------------------------------------------*/ - SCB_EnableICache(); /* MCU Configuration--------------------------------------------------------*/ @@ -111,18 +107,46 @@ int main(void) QSPI_CommandTypeDef sCommand; QSPI_MemoryMappedTypeDef sMemMappedCfg; sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; - sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + sCommand.AddressMode = QSPI_ADDRESS_4_LINES; sCommand.AddressSize = QSPI_ADDRESS_24_BITS; sCommand.DataMode = QSPI_DATA_4_LINES; - sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; + sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; + sCommand.AlternateBytes = 0xFF; sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; - sCommand.Instruction = 0x6B; - sCommand.DummyCycles = 8; + sCommand.Instruction = 0xEB; + sCommand.DummyCycles = 4; sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; sMemMappedCfg.TimeOutPeriod = 0; + w25_qspi_t w25_flash; + w25_flash.interface = &hqspi; + w25_flash.mode = W25_MODE_QUAD; + w25_flash.address_size = W25_ADDRESS_24BITS; + +#if(USE_QPI_MODE == 1) + W25_QPI_Mode(&w25_flash, 0); // Special use case!! +#endif // USE_QPI_MODE + + W25_QSPI_Init(&w25_flash); + printf("Main: Mfg: 0x%x\r\n", w25_flash.manufacturer); + + W25_QSPI_QuadEnable(&w25_flash, 0); + +#if(USE_QPI_MODE == 1) + sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + W25_QPI_Mode(&w25_flash, 1); +#if(QPI_HIGH_SPEED == 1) // For 80MHz HIGHHHHHH speed QPI mode(33-80MHz), additional 4 dummy cycles are required. + sCommand.DummyCycles = 4; // In QPI mode, M7-0 are used as dummy clocks. + W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_6, W25_QPI_WRAP_LENGTH_8); +#else + sCommand.DummyCycles = 0; // In QPI mode, M7-0 are used as dummy clocks. + W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); +#endif // QPI_HIGH_SPEED +#endif // USE_QPI_MODE + if(HAL_QSPI_MemoryMapped(&hqspi, &sCommand, &sMemMappedCfg) == HAL_OK) { printf("QSPI mapped ok!\r\n"); if(BL_CheckValidImage(0x90000000) == HAL_OK) { @@ -158,33 +182,38 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /** Supply configuration update enable + /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); - /** Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI + |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 240; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 40; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 5; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLQ = 1; + RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 @@ -192,28 +221,26 @@ void SystemClock_Config(void) RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { Error_Handler(); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USB - |RCC_PERIPHCLK_QSPI; - PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_CLKP; + PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } - /** Enables the Clock Security System - */ - HAL_RCC_EnableCSS(); - /** Enable USB Voltage detector + /** Enable USB Voltage detector */ HAL_PWREx_EnableUSBVoltageDetector(); } @@ -235,12 +262,12 @@ static void MX_QUADSPI_Init(void) /* USER CODE END QUADSPI_Init 1 */ /* QUADSPI parameter configuration*/ hqspi.Instance = QUADSPI; - hqspi.Init.ClockPrescaler = 16; + hqspi.Init.ClockPrescaler = 2; hqspi.Init.FifoThreshold = 4; hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; - hqspi.Init.FlashSize = 23; - hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE; - hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; + hqspi.Init.FlashSize = 24; + hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; + hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; hqspi.Init.FlashID = QSPI_FLASH_ID_1; hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; if (HAL_QSPI_Init(&hqspi) != HAL_OK) @@ -314,9 +341,12 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); /*Configure GPIO pin : PE3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; @@ -324,6 +354,13 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + /*Configure GPIO pin : PA1 */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ @@ -351,7 +388,7 @@ void Error_Handler(void) * @retval None */ void assert_failed(uint8_t *file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c index b148257..f590041 100644 --- a/Core/Src/stm32h7xx_hal_msp.c +++ b/Core/Src/stm32h7xx_hal_msp.c @@ -109,17 +109,17 @@ void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_QSPI_CLK_ENABLE(); - + __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); - /**QUADSPI GPIO Configuration + /**QUADSPI GPIO Configuration PE2 ------> QUADSPI_BK1_IO2 PB2 ------> QUADSPI_CLK PD11 ------> QUADSPI_BK1_IO0 PD12 ------> QUADSPI_BK1_IO1 PD13 ------> QUADSPI_BK1_IO3 - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -174,14 +174,14 @@ void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) /* USER CODE END QUADSPI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration + + /**QUADSPI GPIO Configuration PE2 ------> QUADSPI_BK1_IO2 PB2 ------> QUADSPI_CLK PD11 ------> QUADSPI_BK1_IO0 PD12 ------> QUADSPI_BK1_IO1 PD13 ------> QUADSPI_BK1_IO3 - PB6 ------> QUADSPI_BK1_NCS + PB6 ------> QUADSPI_BK1_NCS */ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2); @@ -214,11 +214,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -252,10 +252,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END USART1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration + + /**USART1 GPIO Configuration PA9 ------> USART1_TX - PA10 ------> USART1_RX + PA10 ------> USART1_RX */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c index f7da376..d13f5dd 100644 --- a/Core/Src/stm32h7xx_it.c +++ b/Core/Src/stm32h7xx_it.c @@ -64,7 +64,7 @@ extern UART_HandleTypeDef huart1; /* USER CODE END EV */ /******************************************************************************/ -/* Cortex Processor Interruption and Exception Handlers */ +/* Cortex Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. @@ -74,7 +74,6 @@ void NMI_Handler(void) /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ - HAL_RCC_NMI_IRQHandler(); /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ diff --git a/Core/Src/w25_qspi.c b/Core/Src/w25_qspi.c index abfa73b..14849c0 100644 --- a/Core/Src/w25_qspi.c +++ b/Core/Src/w25_qspi.c @@ -8,6 +8,7 @@ #include "w25_qspi.h" HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash); +HAL_StatusTypeDef _W25_Write_Volatile_Enable(w25_qspi_t *flash); HAL_StatusTypeDef _W25_Wait_Ready(w25_qspi_t *flash); HAL_StatusTypeDef _W25_GetDefaultCommand(w25_qspi_t *flash, QSPI_CommandTypeDef *sCommand); HAL_StatusTypeDef _W25_QSPI_Identify(w25_qspi_t *flash); @@ -74,17 +75,77 @@ HAL_StatusTypeDef W25_QSPI_Read(w25_qspi_t *flash, uint32_t address, uint8_t *da return HAL_OK; } -HAL_StatusTypeDef _W25_Set_Mode(w25_qspi_t *flash) { +HAL_StatusTypeDef W25_QSPI_QuadEnable(w25_qspi_t *flash, uint8_t permanent) { QSPI_CommandTypeDef sCommand; _W25_GetDefaultCommand(flash, &sCommand); - sCommand.Instruction = W25_CMD_WRITE_VOLATILE_ENABLE; + sCommand.Instruction = W25_CMD_READ_STATUS_2; + sCommand.AddressMode = QSPI_ADDRESS_NONE; + sCommand.DataMode = QSPI_DATA_1_LINE; + sCommand.NbData = 1; + sCommand.DummyCycles = 0; + + uint8_t status_2; + + if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + return HAL_ERROR; + } + if(HAL_QSPI_Receive(flash->interface, &status_2, 1000) != HAL_OK) { + return HAL_ERROR; + } + + if(permanent) { + _W25_Write_Enable(flash); + } + else _W25_Write_Volatile_Enable(flash); + + sCommand.Instruction = W25_CMD_WRITE_STATUS_2; + status_2 |= 0x02; // BIT 1 QE + + if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + return HAL_ERROR; + } + if(HAL_QSPI_Transmit(flash->interface, &status_2, 1000) != HAL_OK) { + return HAL_ERROR; + } + + return HAL_OK; + +} + +HAL_StatusTypeDef W25_QPI_Mode(w25_qspi_t *flash, uint8_t enable) { + QSPI_CommandTypeDef sCommand; + _W25_GetDefaultCommand(flash, &sCommand); + if(enable) { + sCommand.Instruction = W25_CMD_QPI_ENABLE; + } + else { + sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + sCommand.Instruction = W25_CMD_QPI_DISABLE; + } sCommand.AddressMode = QSPI_ADDRESS_NONE; sCommand.DataMode = QSPI_DATA_NONE; sCommand.NbData = 0; sCommand.DummyCycles = 0; - HAL_QSPI_Command(flash->interface, &sCommand, 1000); - return HAL_OK; + return HAL_QSPI_Command(flash->interface, &sCommand, 1000); +} + +HAL_StatusTypeDef W25_QPI_ReadParams(w25_qspi_t *flash, w25_qpi_dummy_t dummy_clocks, w25_qpi_wrap_t wrap_length) { + uint8_t rd_params = (dummy_clocks & 0x03) << 4 | (wrap_length & 0x03); // BIT 5-4: DUMMY, BIT 1-0 WRAP + QSPI_CommandTypeDef sCommand; + _W25_GetDefaultCommand(flash, &sCommand); + sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + sCommand.Instruction = W25_CMD_QPI_READ_PARAMS; + sCommand.AddressMode = QSPI_ADDRESS_NONE; + sCommand.DataMode = QSPI_DATA_4_LINES; + sCommand.NbData = 1; + sCommand.DummyCycles = 0; + + if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + return HAL_ERROR; + } + + return HAL_QSPI_Transmit(flash->interface, &rd_params, 1000); } HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash) { @@ -101,6 +162,20 @@ HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash) { return HAL_OK; } +HAL_StatusTypeDef _W25_Write_Volatile_Enable(w25_qspi_t *flash) { + QSPI_CommandTypeDef sCommand; + _W25_GetDefaultCommand(flash, &sCommand); + sCommand.Instruction = W25_CMD_WRITE_VOLATILE_ENABLE; + sCommand.AddressMode = QSPI_ADDRESS_NONE; + sCommand.DataMode = QSPI_DATA_NONE; + sCommand.NbData = 0; + sCommand.DummyCycles = 0; + + HAL_QSPI_Command(flash->interface, &sCommand, 1000); + + return HAL_OK; +} + HAL_StatusTypeDef _W25_Wait_Ready(w25_qspi_t *flash) { QSPI_AutoPollingTypeDef sConfig; sConfig.Match = 0x00; diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h b/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h index aa0de3a..f9aed6a 100644 --- a/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h @@ -244,48 +244,48 @@ typedef enum typedef struct { - __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ - __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ - __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< Reserved, 0x028 */ - uint32_t RESERVED2; /*!< Reserved, 0x02C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - uint32_t RESERVED3; /*!< Reserved, 0x044 */ - uint32_t RESERVED4; /*!< Reserved, 0x048 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ - uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ - uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ - __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ - uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ - uint32_t RESERVED9; /*!< Reserved, 0x0AC */ - __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ - __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ - __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ - __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ - __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ - __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ - __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ } ADC_TypeDef; @@ -3151,6 +3151,7 @@ typedef struct #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ @@ -3315,64 +3316,64 @@ typedef struct #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ -#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ -#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ -#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ -#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ********************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ -#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ @@ -3401,8 +3402,8 @@ typedef struct #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ @@ -3410,13 +3411,14 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_SSATE_Pos (31U) -#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ -#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + /******************** Bit definition for ADC_OFR2 register ********************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ -#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ @@ -3445,8 +3447,8 @@ typedef struct #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ @@ -3454,13 +3456,14 @@ typedef struct #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_SSATE_Pos (31U) -#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + /******************** Bit definition for ADC_OFR3 register ********************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ -#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ @@ -3489,8 +3492,8 @@ typedef struct #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ @@ -3498,13 +3501,14 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_SSATE_Pos (31U) -#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ -#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + /******************** Bit definition for ADC_OFR4 register ********************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ -#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ @@ -3533,8 +3537,8 @@ typedef struct #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ @@ -3542,13 +3546,14 @@ typedef struct #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_SSATE_Pos (31U) -#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ -#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ @@ -3584,8 +3589,8 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ @@ -3621,8 +3626,8 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ @@ -3658,8 +3663,8 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ @@ -3695,8 +3700,8 @@ typedef struct /******************** Bit definition for ADC_AWD2CR register ********************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ @@ -3720,8 +3725,8 @@ typedef struct /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ @@ -3745,8 +3750,8 @@ typedef struct /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ @@ -3771,7 +3776,7 @@ typedef struct /******************** Bit definition for ADC_CALFACT register ********************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ -#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ @@ -3785,7 +3790,7 @@ typedef struct #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ -#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ @@ -3801,7 +3806,7 @@ typedef struct /******************** Bit definition for ADC_CALFACT2 register ********************/ #define ADC_CALFACT2_LINCALFACT_Pos (0U) #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ -#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ @@ -3904,8 +3909,8 @@ typedef struct /******************** Bit definition for ADC_CCR register ********************/ #define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ -#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ @@ -3913,8 +3918,8 @@ typedef struct #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ -#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ @@ -3922,48 +3927,48 @@ typedef struct #define ADC_CCR_DAMDF_Pos (14U) -#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ -#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ -#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ #define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ -#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ -#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************** Bit definition for ADC_CDR2 register ******************/ #define ADC_CDR2_RDATA_ALT_Pos (0U) #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ -#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ /******************************************************************************/ @@ -4157,7 +4162,7 @@ typedef struct /***************** Bit definition for FDCAN_ECR register *********************/ #define FDCAN_ECR_TEC_Pos (0U) -#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */ +#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */ #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL)) -#endif /* DUAL_CORE */ /** * @} */ +#endif /* DUAL_CORE */ /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros * @{ @@ -739,6 +815,23 @@ typedef enum #define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L) #endif /* DUAL_CORE */ +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#endif /* !SYSCFG_PMCR_BOOSTEN */ /** * @} */ @@ -760,8 +853,19 @@ typedef enum #define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1)) #define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2)) #define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) #define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ +#if defined(TIM23) +#define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1)) #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8)) @@ -794,8 +898,19 @@ typedef enum #define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1)) #define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2)) #define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) #define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ +#if defined(TIM23) +#define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ #define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1)) #define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8)) @@ -935,11 +1050,19 @@ uint32_t HAL_GetDEVID(void); uint32_t HAL_GetUIDw0(void); uint32_t HAL_GetUIDw1(void); uint32_t HAL_GetUIDw2(void); +#if defined(SYSCFG_PMCR_EPIS_SEL) void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); +#endif /* SYSCFG_PMCR_EPIS_SEL */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); +#if defined(SYSCFG_PMCR_BOOSTEN) void HAL_SYSCFG_EnableBOOST(void); void HAL_SYSCFG_DisableBOOST(void); +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/ + #if defined(DUAL_CORE) void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); void HAL_SYSCFG_EnableCM7BOOT(void); @@ -953,6 +1076,9 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void); void HAL_SYSCFG_DisableIOSpeedOptimize(void); void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode); void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#if defined(SYSCFG_CCCR_NCC_MMC) +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#endif /* SYSCFG_CCCR_NCC_MMC */ void HAL_EnableDBGSleepMode(void); void HAL_DisableDBGSleepMode(void); void HAL_EnableDBGStopMode(void); @@ -989,6 +1115,12 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void); +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ /** * @} diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h index 54d24de..1ac7f5a 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -308,7 +308,12 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ -#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ +#if defined (PSSI) +#define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */ +#else +#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ #define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ #define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ @@ -327,8 +332,11 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ #define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ + +#if defined(SAI2) #define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ #define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ #define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ #define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ @@ -336,12 +344,14 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ +#if defined(HRTIM1) #define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ #define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */ #define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */ #define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */ #define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */ #define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */ +#endif /* HRTIM1 */ #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ @@ -359,11 +369,57 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ +#if defined(SAI3) #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ +#if defined(ADC3) #define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ +#if defined(UART9) +#define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */ +#define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */ +#endif /* UART9 */ + +#if defined(USART10) +#define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */ +#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */ +#endif /* USART10 */ + +#if defined(FMAC) +#define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ + +#if defined(CORDIC) +#define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ + +#if defined(I2C5) +#define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ + +#if defined(TIM23) +#define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ + +#if defined(TIM24) +#define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ /* DMAMUX2 requests */ #define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ @@ -381,9 +437,19 @@ typedef struct __DMA_HandleTypeDef #define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ #define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ #define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined(SAI4) #define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ #define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined(ADC3) #define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined(DAC2) +#define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined(DFSDM2_Channel0) +#define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */ +#endif /* DFSDM1_Channel0 */ /** * @} @@ -649,6 +715,42 @@ typedef struct __DMA_HandleTypeDef * @param __HANDLE__: DMA handle * @retval The specified transfer complete flag index. */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#else #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ @@ -675,12 +777,49 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\ (uint32_t)0x00000000) +#endif /* BDMA1 */ /** * @brief Return the current DMA Stream half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. */ +#if defined(BDMA1) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#else #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ @@ -707,12 +846,49 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\ (uint32_t)0x00000000) +#endif /* BDMA1 */ /** * @brief Return the current DMA Stream transfer error flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#else #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ @@ -739,6 +915,7 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\ (uint32_t)0x00000000) +#endif /* BDMA1 */ /** * @brief Return the current DMA Stream FIFO error flag. @@ -793,6 +970,26 @@ typedef struct __DMA_HandleTypeDef * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ +#if defined(BDMA1) +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#else #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\ @@ -803,6 +1000,7 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\ (uint32_t)0x00000000) +#endif /* BDMA1 */ /** * @brief Get the DMA Stream pending flags. @@ -817,11 +1015,20 @@ typedef struct __DMA_HandleTypeDef * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. * @retval The state of FLAG (SET or RESET). */ +#if defined(BDMA1) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#else #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#endif /* BDMA1 */ /** * @brief Clear the DMA Stream pending flags. @@ -836,11 +1043,20 @@ typedef struct __DMA_HandleTypeDef * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. * @retval None */ +#if defined(BDMA1) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#else #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#endif /* BDMA1 */ #define DMA_TO_BDMA_IT(__DMA_IT__) \ ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ @@ -1019,9 +1235,19 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @{ */ +#if defined(TIM24) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG)) +#elif defined(ADC3) #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX)) +#endif /* TIM24 */ +#if defined(ADC3) #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) +#else +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0)) +#endif /* ADC3 */ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h index 7790e15..4125ae7 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h @@ -177,8 +177,12 @@ typedef struct #define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ #define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ #define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined(LPTIM4) #define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) #define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ #define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ #define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ #define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ @@ -190,8 +194,10 @@ typedef struct #define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ #define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ #define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined(ADC3) #define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ #define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ #define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ #define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h index 6f0ec0e..e47db13 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h @@ -134,22 +134,46 @@ typedef struct #define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#if !defined(USB2_OTG_FS) +#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU) +#else #define EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#endif /* USB2_OTG_FS */ #define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU) +#if defined(DSI) #define EXTI_LINE_46 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU) +#else +#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU) +#endif /* DSI */ #define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU) #define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U) #define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U) #define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U) #define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U) +#if defined(LPTIM4) #define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U) +#else +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U) +#else +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#endif /*LPTIM5*/ #define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) #define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) #define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#if defined(EXTI_IMR2_IM57) #define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#else +#define EXTI_LINE_57 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x19U) +#endif /*EXTI_IMR2_IM57*/ #define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#if defined(EXTI_IMR2_IM59) #define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#else +#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x1BU) +#endif /*EXTI_IMR2_IM59*/ #define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) #define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) #define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) @@ -165,37 +189,58 @@ typedef struct #define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) #define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U) #define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#if defined(ADC3) #define EXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) -#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) -#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU) - -#if defined (DUAL_CORE) -#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU) #else -#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU) -#endif /* DUAL_CORE */ - -#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU) - +#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU) +#endif /* ADC3 */ +#if defined(SAI4) +#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#else +#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU) +#endif /* SAI4 */ #if defined (DUAL_CORE) +#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU) +#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU) +#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU) #define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U) #else +#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU) +#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU) +#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU) #define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U) #endif /* DUAL_CORE */ - #define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U) - #if defined (DUAL_CORE) #define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U) #else #define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U) #endif /* DUAL_CORE */ - #define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U) +#if defined (DUAL_CORE) #define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U) +#else +#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U) +#endif /* DUAL_CORE */ #define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#if defined(ETH) #define EXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#else +#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U) +#endif /* ETH */ #define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#if defined(DTS) +#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U) +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define EXTI_LINE_89 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#endif /*EXTI_IMR3_IM89*/ +#if defined(EXTI_IMR3_IM90) +#define EXTI_LINE_90 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#endif /*EXTI_IMR3_IM90*/ +#if defined(I2C5) +#define EXTI_LINE_91 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#endif /*I2C5*/ /** * @} @@ -240,7 +285,9 @@ typedef struct #define EXTI_GPIOF 0x00000005U #define EXTI_GPIOG 0x00000006U #define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) #define EXTI_GPIOI 0x00000008U +#endif /*GPIOI*/ #define EXTI_GPIOJ 0x00000009U #define EXTI_GPIOK 0x0000000AU @@ -255,8 +302,16 @@ typedef struct #define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero */ #define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */ #define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/ +#if defined (LPTIM4) #define EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ -#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +#if defined (LPTIM5) +#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif /** * @} */ @@ -339,7 +394,13 @@ typedef struct /** * @brief EXTI Line number */ +#if (STM32H7_DEV_ID == 0x483UL) +#define EXTI_LINE_NB 92UL +#elif (STM32H7_DEV_ID == 0x480UL) +#define EXTI_LINE_NB 89UL +#else #define EXTI_LINE_NB 88UL +#endif /* EXTI_LINE_91 */ /** * @} @@ -377,6 +438,7 @@ typedef struct #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00UL) +#if defined(GPIOI) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ @@ -388,14 +450,33 @@ typedef struct ((__PORT__) == EXTI_GPIOI) || \ ((__PORT__) == EXTI_GPIOJ) || \ ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /*GPIOI*/ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL) - +#if defined (LPTIM4) && defined (LPTIM5) #define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \ ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5)) +#else +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3)) +#endif /* LPTIM4 && LPTIM5 */ /** * @} diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h index 66ebcad..9da1470 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h @@ -91,24 +91,28 @@ typedef struct * @brief FLASH Error Code * @{ */ -#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ -#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ -#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */ -#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */ -#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */ -#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */ -#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */ -#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */ -#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */ -#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */ +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ +#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */ +#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */ +#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */ +#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */ +#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */ +#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */ #define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */ #define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */ #define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */ #define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */ +#if defined (FLASH_SR_OPERR) #define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */ +#endif /* FLASH_SR_OPERR */ #define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */ #define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */ #define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */ @@ -119,7 +123,9 @@ typedef struct #define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */ #define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */ #define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */ +#if defined (FLASH_SR_OPERR) #define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */ +#endif /* FLASH_SR_OPERR */ #define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */ #define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */ #define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */ @@ -134,7 +140,10 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word (256-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word at a specified address */ +#if defined (FLASH_OPTCR_PG_OTP) +#define FLASH_TYPEPROGRAM_OTPWORD 0x02U /*!< Program an OTP word at a specified address */ +#endif /* FLASH_OPTCR_PG_OTP */ /** * @} */ @@ -144,77 +153,99 @@ typedef struct * @{ */ #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */ -#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */ -#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */ +#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write Buffer Not Empty flag */ +#define FLASH_FLAG_QW FLASH_SR_QW /*!< Wait Queue on flag */ +#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC Busy flag */ #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */ #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */ #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */ -#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */ +#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe Error flag */ #define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */ +#if defined (FLASH_SR_OPERR) #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */ +#endif /* FLASH_SR_OPERR */ #define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */ #define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */ #define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */ #define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */ -#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */ +#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC End of Calculation flag */ #define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */ #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */ -#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */ -#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */ -#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */ +#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Write Buffer Not Empty on Bank 1 flag */ +#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Wait Queue on Bank 1 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC Busy on Bank 1 flag */ #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */ #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */ #define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */ -#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */ +#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< Strobe Error on Bank 1 flag */ #define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */ +#if defined (FLASH_SR_OPERR) #define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */ +#endif /* FLASH_SR_OPERR */ #define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */ #define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */ #define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */ #define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */ -#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */ +#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC End of Calculation on Bank 1 flag */ #define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */ +#if defined (FLASH_SR_OPERR) #define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \ FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \ - FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) + FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | \ + FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \ + FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#endif /* FLASH_SR_OPERR */ #define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \ FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \ FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \ - FLASH_FLAG_ALL_ERRORS_BANK1) + FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */ #define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */ -#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */ -#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */ -#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */ +#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Write Buffer Not Empty on Bank 2 flag */ +#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Wait Queue on Bank 2 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC Busy on Bank 2 flag */ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */ #define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */ #define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */ #define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */ +#if defined (FLASH_SR_OPERR) #define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */ +#endif /* FLASH_SR_OPERR */ #define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */ #define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */ #define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */ #define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */ -#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */ +#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC End of Calculation on Bank 2 flag */ #define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */ +#if defined (FLASH_SR_OPERR) #define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \ FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \ - FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) + FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | \ + FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \ + FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#endif /* FLASH_SR_OPERR */ #define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \ FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \ FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \ - FLASH_FLAG_ALL_ERRORS_BANK2) + FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */ /** * @} */ @@ -228,7 +259,9 @@ typedef struct #define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */ #define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */ #define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) #define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ #define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */ #define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */ #define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */ @@ -236,19 +269,30 @@ typedef struct #define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */ #define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) #define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \ FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \ FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \ - FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) + FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_RDPERR_BANK1 | \ + FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | \ + FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | \ + FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ #define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */ #define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */ #define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */ #define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */ #define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) #define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ #define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */ #define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */ #define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */ @@ -256,16 +300,26 @@ typedef struct #define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */ #define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) #define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \ FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \ FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \ - FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) + FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_RDPERR_BANK2 | \ + FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | \ + FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | \ + FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ /** * @} */ +#if defined (FLASH_CR_PSIZE) /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism * @{ */ @@ -276,6 +330,7 @@ typedef struct /** * @} */ +#endif /* FLASH_CR_PSIZE */ /** @defgroup FLASH_Keys FLASH Keys @@ -300,6 +355,128 @@ typedef struct #define FLASH_SECTOR_5 5U /*!< Sector Number 5 */ #define FLASH_SECTOR_6 6U /*!< Sector Number 6 */ #define FLASH_SECTOR_7 7U /*!< Sector Number 7 */ +#if (FLASH_SECTOR_TOTAL == 128) +#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */ +#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */ +#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */ +#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */ +#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */ +#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */ +#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */ +#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */ +#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */ +#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */ +#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */ +#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */ +#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */ +#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */ +#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */ +#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */ +#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */ +#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */ +#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */ +#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */ +#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */ +#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */ +#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */ +#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */ +#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */ +#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */ +#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */ +#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */ +#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */ +#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */ +#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */ +#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */ +#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */ +#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */ +#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */ +#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */ +#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */ +#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */ +#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */ +#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */ +#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */ +#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */ +#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */ +#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */ +#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */ +#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */ +#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */ +#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */ +#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */ +#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */ +#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */ +#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */ +#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */ +#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */ +#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */ +#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */ +#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */ +#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */ +#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */ +#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */ +#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */ +#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */ +#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */ +#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */ +#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */ +#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */ +#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */ +#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */ +#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */ +#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */ +#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */ +#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */ +#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */ +#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */ +#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */ +#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */ +#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */ +#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */ +#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */ +#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */ +#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */ +#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */ +#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */ +#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */ +#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */ +#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */ +#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */ +#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */ +#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */ +#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */ +#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */ +#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */ +#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */ +#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */ +#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */ +#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */ +#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */ +#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */ +#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */ +#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */ +#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */ +#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */ +#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */ +#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */ +#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ /** * @} */ @@ -344,8 +521,9 @@ typedef struct * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source - - * In case of Bank 2, this parameter can be any combination of the following values: * + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source @@ -358,6 +536,7 @@ typedef struct * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources * @retval none */ @@ -365,9 +544,13 @@ typedef struct #define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU)) +#if defined (DUAL_BANK) #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \ __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ /** @@ -386,8 +569,9 @@ typedef struct * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source - - * In case of Bank 2, this parameter can be any combination of the following values: * + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source @@ -400,6 +584,7 @@ typedef struct * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources * @retval none */ @@ -407,18 +592,22 @@ typedef struct #define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU)) +#if defined (DUAL_BANK) #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \ __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ /** * @brief Checks whether the specified FLASH flag is set or not. * @param __FLAG__: specifies the FLASH flag to check. - * In case of Bank 1 This parameter can be any combination of the following values : + * In case of Bank 1 This parameter can be one of the following values : * @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag - * @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag - * @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag + * @arg FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag + * @arg FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag * @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag @@ -433,10 +622,10 @@ typedef struct * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag * - * In case of Bank 2 This parameter can be any combination of the following values : + * In case of Bank 2 This parameter can be one of the following values : * @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag - * @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag - * @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag + * @arg FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag + * @arg FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag * @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag @@ -456,40 +645,48 @@ typedef struct #define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU))) +#if defined (DUAL_BANK) #define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \ __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ /** * @brief Clear the specified FLASH flag. * @param __FLAG__: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag - * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag - * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag - * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag - * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag - * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag - * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag - * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag - * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag - * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag - * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag - * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * In case of Bank 1, this parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags + * @arg FLASH_FLAG_ALL_BANK1 : All Bank 1 flags * - * In case of Bank 2 This parameter can be any combination of the following values : - * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag - * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag - * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag - * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag - * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag - * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag - * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag - * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag - * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag - * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag - * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag - * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * In case of Bank 2, this parameter can be any combination of the following values : + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags + * @arg FLASH_FLAG_ALL_BANK2 : All Bank 2 flags * @retval none */ @@ -497,8 +694,12 @@ typedef struct #define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU)) +#if defined (DUAL_BANK) #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \ - __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)) + __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ /** * @} @@ -575,49 +776,62 @@ extern FLASH_ProcessTypeDef pFlash; * @{ */ -/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions - * @{ - */ -#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) -/** - * @} - */ -/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions - * @{ - */ +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) +#endif /* FLASH_OPTCR_PG_OTP */ -#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT)) +#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT)) +#if defined (DUAL_BANK) +#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT)) +#endif /* DUAL_BANK */ -#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT)) - -/** - * @} - */ - -#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG)) - -#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG)) - -/** @defgroup FLASH_Address FLASH Address - * @{ - */ +#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG)) +#if defined (DUAL_BANK) +#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG)) +#endif /* DUAL_BANK */ +#if defined (DUAL_BANK) #define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE)) #define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) <= FLASH_END)) +#endif /* DUAL_BANK */ -#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U)) +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#else +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#endif /* DUAL_BANK */ -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) +#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U)) -#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2)) - -/** - * @} - */ +#if defined (DUAL_BANK) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) +#else +#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) +#endif /* DUAL_BANK */ /** * @} diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h index 6fa6ab6..a84e503 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h @@ -69,26 +69,26 @@ typedef struct */ typedef struct { - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ - uint32_t WRPState; /*!< Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ - uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. - The value of this parameter depend on device used within the same series */ + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ - uint32_t RDPLevel; /*!< Set the read protection level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - uint32_t BORLevel; /*!< Set the BOR Level. - This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ - uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / - IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . This parameter must be a value of @ref FLASHEx_Banks */ @@ -103,13 +103,13 @@ typedef struct uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of a bank */ - uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 + uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ - uint32_t BootAddr0; /*!< Boot Address 0. + uint32_t BootAddr0; /*!< Boot Address 0. This parameter must be a value between begin and end of a bank */ - uint32_t BootAddr1; /*!< Boot Address 1. + uint32_t BootAddr1; /*!< Boot Address 1. This parameter must be a value between begin and end of a bank */ #if defined(DUAL_CORE) uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 @@ -123,9 +123,9 @@ typedef struct This parameter must be a value between begin and end of a bank */ #endif /*DUAL_CORE*/ - uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not - when RDP level decreased from Level 1 to Level 0 or during a mass erase. - This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ + uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. This parameter must be a value between begin address and end address of bank1 */ @@ -133,6 +133,21 @@ typedef struct uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. This parameter must be a value between Secure Area Start address and end address of a bank1 */ +#if defined (FLASH_OTPBL_LOCKBL) + uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. + This parameter must be a value of @ref FLASHEx_OTP_Blocks */ +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM. + This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost. + This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + } FLASH_OBProgramInitTypeDef; /** @@ -140,20 +155,20 @@ typedef struct */ typedef struct { - uint32_t TypeCRC; /*!< CRC Selection Type. - This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ + uint32_t TypeCRC; /*!< CRC Selection Type. + This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ - uint32_t BurstSize; /*!< CRC Burst Size. - This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ + uint32_t BurstSize; /*!< CRC Burst Size. + This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ - uint32_t Bank; /*!< Select bank where CRC computation is enabled. - This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ + uint32_t Bank; /*!< Select bank where CRC computation is enabled. + This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ - uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation - This parameter must be a value of @ref FLASH_Sectors */ + uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation + This parameter must be a value of @ref FLASH_Sectors */ - uint32_t NbSectors; /*!< Number of sectors to be computed. - This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + uint32_t NbSectors; /*!< Number of sectors to be computed. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ uint32_t CRCStartAddr; /*!< CRC Start address. This parameter must be a value between begin address and end address of a bank */ @@ -181,6 +196,7 @@ typedef struct * @} */ +#if defined (FLASH_CR_PSIZE) /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range * @{ */ @@ -191,6 +207,7 @@ typedef struct /** * @} */ +#endif /* FLASH_CR_PSIZE */ /** @defgroup FLASHEx_WRP_State FLASH WRP State * @{ @@ -210,13 +227,40 @@ typedef struct #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ #define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ #define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) #define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ #define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ #define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ -#else /* Single core*/ +#else /* Single core */ #define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ #endif /*DUAL_CORE*/ +#if defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */ +#endif /* FLASH_OTPBL_LOCKBL */ +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (DUAL_CORE) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */ +#elif defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD) /*!< All option byte configuration */ +#endif /* DUAL_CORE */ /** * @} */ @@ -245,8 +289,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog * @{ */ -#define OB_IWDG_SW 0x20U /*!< Software IWDG selected */ -#define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */ +#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */ +#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */ /** * @} */ @@ -272,8 +316,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP * @{ */ -#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ -#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ /** * @} */ @@ -281,8 +325,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY * @{ */ -#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ -#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ /** * @} */ @@ -290,10 +334,10 @@ typedef struct /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level * @{ */ -#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ -#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ -#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ -#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ +#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ +#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ +#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ +#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ /** * @} */ @@ -303,13 +347,13 @@ typedef struct /** @defgroup FLASHEx_Boot_Address FLASH Boot Address * @{ */ -#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ -#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ -#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ -#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ -#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ -#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ -#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ +#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ +#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ /** * @} */ @@ -340,9 +384,11 @@ typedef struct /** @defgroup FLASHEx_Banks FLASH Banks * @{ */ -#define FLASH_BANK_1 0x01U /*!< Bank 1 */ -#define FLASH_BANK_2 0x02U /*!< Bank 2 */ -#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +#define FLASH_BANK_1 0x01U /*!< Bank 1 */ +#if defined (DUAL_BANK) +#define FLASH_BANK_2 0x02U /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +#endif /* DUAL_BANK */ /** * @} */ @@ -350,10 +396,10 @@ typedef struct /** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP * @{ */ -#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level - is decreased from Level 1 to Level 0 or during a mass erase */ -#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is - decreased from Level 1 to Level 0 (full mass erase) */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ /** * @} @@ -362,15 +408,51 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection * @{ */ -#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ -#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ -#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ -#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ -#define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */ +#if (FLASH_SECTOR_TOTAL == 128) +#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ +#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ +#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ +#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ +#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ +#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ +#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ +#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ +#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ +#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ +#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ +#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ +#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ +#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ +#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ +#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ +#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ +#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ +#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ +#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ +#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ +#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ +#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ +#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ +#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ +#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ +#else +#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ /** * @} */ @@ -387,10 +469,10 @@ typedef struct /** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE * @{ */ -#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ -#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ -#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ -#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ /** * @} */ @@ -414,7 +496,7 @@ typedef struct /** * @} */ -#endif /*DUAL_CORE*/ +#endif /* DUAL_CORE */ /** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW * @{ @@ -454,7 +536,7 @@ typedef struct * @} */ -#if defined(DUAL_CORE) +#if defined (FLASH_OPTSR_NRST_STOP_D2) /** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 * @{ */ @@ -472,7 +554,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ /** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK * @{ @@ -486,21 +568,46 @@ typedef struct /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV * @{ */ -#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ -#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ +#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ +#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ /** * @} */ -/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV * @{ */ -#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ -#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ -#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ +#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */ +#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */ /** * @} */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST + * @{ + */ +#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */ +#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED + * @{ + */ +#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type * @{ @@ -513,15 +620,53 @@ typedef struct #define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ #define OB_USER_SECURITY 0x0040U /*!< security selection */ #define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ +#if defined (DUAL_BANK) #define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ +#endif /* DUAL_BANK */ +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ #if defined (DUAL_CORE) #define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ #define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ #define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ -#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/ -#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/ #endif /*DUAL_CORE*/ +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */ +#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ +#if defined (DUAL_CORE) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#elif defined (FLASH_OPTSR_VDDMMC_HSLV) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_VDDMMC_HSLV) +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION + * @{ + */ +#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ +#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ +#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ /** * @} */ @@ -533,7 +678,6 @@ typedef struct is decreased from Level 1 to Level 0 or during a mass erase */ #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase) */ - /** * @} */ @@ -570,6 +714,32 @@ typedef struct * @} */ +#if defined (FLASH_OTPBL_LOCKBL) +/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks + * @{ + */ +#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ +#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ +#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ +#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ +#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ +#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ +#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ +#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ +#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ +#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ +#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ +#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ +#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ +#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ +#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ +#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ +#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */ +/** + * @} + */ +#endif /* FLASH_OTPBL_LOCKBL */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros * @{ @@ -585,6 +755,7 @@ typedef struct * @} */ +#if defined (FLASH_CR_PSIZE) /** * @brief Set the FLASH Program/Erase parallelism. * @param __PSIZE__ FLASH Program/Erase parallelism @@ -592,9 +763,13 @@ typedef struct * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) * @retval none */ +#if defined (DUAL_BANK) #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) +#else +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) +#endif /* DUAL_BANK */ /** * @brief Get the FLASH Program/Erase parallelism. @@ -602,9 +777,15 @@ typedef struct * @retval FLASH Program/Erase parallelism * This return value can be a value of @ref FLASH_Program_Parallelism */ +#if defined (DUAL_BANK) #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) +#else +#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) +#endif /* DUAL_BANK */ + +#endif /* FLASH_CR_PSIZE */ /** * @brief Set the FLASH Programming Delay. @@ -637,8 +818,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); +#if defined (DUAL_BANK) HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); +#endif /* DUAL_BANK */ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); @@ -661,66 +844,70 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ * @{ */ -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) -#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_4)) +#if defined (FLASH_CR_PSIZE) +#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) +#endif /* FLASH_CR_PSIZE */ -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) -#if defined(DUAL_CORE) -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U)) +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ + (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ + ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) + +#if (FLASH_SECTOR_TOTAL == 8U) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) #else -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U)) -#endif /*DUAL_CORE*/ +#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U) +#endif /* FLASH_SECTOR_TOTAL == 8U */ -#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1) ||\ - ((LEVEL) == OB_RDP_LEVEL_2)) - -#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) - -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) - -#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) - -#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) - -#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ - ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ - ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || \ - ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4) || \ - ((LATENCY) == FLASH_LATENCY_5) || \ - ((LATENCY) == FLASH_LATENCY_6) || \ - ((LATENCY) == FLASH_LATENCY_7) || \ - ((LATENCY) == FLASH_LATENCY_8) || \ - ((LATENCY) == FLASH_LATENCY_9) || \ - ((LATENCY) == FLASH_LATENCY_10) || \ - ((LATENCY) == FLASH_LATENCY_11) || \ - ((LATENCY) == FLASH_LATENCY_12) || \ - ((LATENCY) == FLASH_LATENCY_13) || \ - ((LATENCY) == FLASH_LATENCY_14) || \ - ((LATENCY) == FLASH_LATENCY_15)) - -#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) - -#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ - ((CONFIG) == OB_PCROP_RDP_ERASE)) +#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_PCROP_RDP_ERASE)) #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ ((CONFIG) == OB_SECURE_RDP_ERASE)) @@ -729,10 +916,14 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE)) +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) #define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) -#endif /*DUAL_CORE*/ +#endif /* DUAL_CORE */ #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) @@ -746,20 +937,29 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) #define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) #define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) +#endif /* DUAL_CORE */ +#if defined (FLASH_OPTSR_NRST_STOP_D2) #define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) #define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) -#endif /*DUAL_CORE*/ -#if defined(DUAL_CORE) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U)) -#else -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U)) -#endif +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \ + ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB)) +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE)) +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ + (((TYPE) & ~OB_USER_ALL) == 0U)) #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ ((VALUE) == OB_BOOT_ADD1) || \ @@ -768,6 +968,10 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ ((VALUE) == FLASH_CRC_SECTORS) || \ ((VALUE) == FLASH_CRC_BANK)) + +#if defined (FLASH_OTPBL_LOCKBL) +#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U)) +#endif /* FLASH_OTPBL_LOCKBL */ /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h index bbea888..c185566 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -173,7 +173,7 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__)) +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending flags. @@ -181,7 +181,7 @@ typedef enum * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__)) +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) /** * @brief Checks whether the specified EXTI line is asserted or not. @@ -189,7 +189,7 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__)) +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending bits. @@ -197,7 +197,7 @@ typedef enum * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__)) +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) #if defined(DUAL_CORE) /** @@ -206,7 +206,7 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__)) +#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending flags. @@ -214,7 +214,7 @@ typedef enum * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ -#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__)) +#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) /** * @brief Checks whether the specified EXTI line is asserted or not. @@ -222,7 +222,7 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__)) +#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) /** * @brief Clears the EXTI's line pending bits. @@ -230,9 +230,9 @@ typedef enum * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ -#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) #endif + /** * @brief Generates a Software interrupt on selected EXTI line. * @param __EXTI_LINE__: specifies the EXTI line to check. @@ -296,8 +296,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h index 21bba63..14f576a 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h @@ -46,14 +46,16 @@ extern "C" { /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection * @{ */ + /** * @brief AF 0 selection */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */ #define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ #define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ #define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ @@ -62,26 +64,40 @@ extern "C" { #define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ #define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ #endif /* DUAL_CORE */ +#endif /* PWR_CPUCR_PDDS_D2 */ /** * @brief AF 1 selection */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ -#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#if defined(HRTIM1) #define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#if defined(SAI4) +#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* SAI4 */ +#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + /** * @brief AF 2 selection */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ -#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */ -#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(FDCAN3) +#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ /** * @brief AF 3 selection @@ -89,11 +105,18 @@ extern "C" { #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */ #define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */ -#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */ #define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */ #define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */ #define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */ #define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#if defined(HRTIM1) +#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ /** * @brief AF 4 selection @@ -102,11 +125,27 @@ extern "C" { #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ #define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ #define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ #define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ #define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ #define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */ +#if defined(USART10) +#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /*USART10*/ +#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(PSSI) +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#if defined(OCTOSPIM) +#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* OCTOSPIM */ /** * @brief AF 5 selection @@ -118,18 +157,31 @@ extern "C" { #define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ #define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ #define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ - +#if defined(FDCAN3) +#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ /** * @brief AF 6 selection */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ -#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */ -#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */ -#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(SAI3) +#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */ +#endif /* SAI3 */ +#if defined(OCTOSPIM) +#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ /** * @brief AF 7 selection @@ -142,90 +194,159 @@ extern "C" { #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ #define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */ -#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */ #define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */ /** * @brief AF 8 selection */ -#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ -#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ -#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */ -#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ +#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(SAI4) +#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ /** * @brief AF 9 selection */ -#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ -#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ -#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */ -#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */ -#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */ +#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */ +#if defined(QUADSPI) +#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if defined(OCTOSPIM) +#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ /** * @brief AF 10 selection */ -#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */ -#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */ -#define GPIO_AF10_SDMMC2 ((uint8_t)0xA) /* SDMMC2 Alternate Function mapping */ -#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */ -#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */ -#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */ -#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */ -#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */ -#define GPIO_AF10_CRS_SYNC ((uint8_t)0xA) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */ - +#if defined(SAI2) +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ +#if defined(USB2_OTG_FS) +#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */ +#endif /*USB2_OTG_FS*/ +#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */ +#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(QUADSPI) +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if !defined(USB2_OTG_FS) +#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /* !USB2_OTG_FS */ +#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ /** * @brief AF 11 selection */ -#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */ -#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */ -#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */ -#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */ -#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ -#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */ -#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */ -#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */ -#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */ +#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */ +#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */ +#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */ +#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(USART10) +#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */ +#endif /* USART10 */ +#if defined(UART9) +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#endif /* UART9 */ +#if defined(ETH) +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(LTDC) +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /*LTDC*/ +#if defined(OCTOSPIM) +#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ /** * @brief AF 12 selection */ -#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */ -#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(USB2_OTG_FS) +#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */ +#endif /* USB2_OTG_FS */ +#if defined(OCTOSPIM) +#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ /** * @brief AF 13 selection */ -#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ #define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */ #define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */ -#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(DSI) +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(PSSI) +#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */ +#if defined(TIM23) +#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */ +#endif /*TIM23*/ /** * @brief AF 14 selection */ -#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ #define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ +#if defined(TIM24) +#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */ +#endif /*TIM24*/ /** * @brief AF 15 selection @@ -277,11 +398,21 @@ extern "C" { #define GPIOE_PIN_AVAILABLE GPIO_PIN_All #define GPIOF_PIN_AVAILABLE GPIO_PIN_All #define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) #define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#endif /*GPIOI*/ +#if defined(GPIOI) #define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#else +#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 ) +#endif /* GPIOI */ #define GPIOH_PIN_AVAILABLE GPIO_PIN_All -#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \ +#if defined(GPIOI) +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) +#else +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 ) +#endif /* GPIOI */ /** * @} @@ -294,6 +425,7 @@ extern "C" { /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index * @{ */ +#if defined(GPIOI) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ ((__GPIOx__) == (GPIOB))? 1UL :\ ((__GPIOx__) == (GPIOC))? 2UL :\ @@ -304,6 +436,18 @@ extern "C" { ((__GPIOx__) == (GPIOH))? 7UL :\ ((__GPIOx__) == (GPIOI))? 8UL :\ ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#endif /* GPIOI */ + /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h index bf89420..46fc375 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h @@ -55,6 +55,7 @@ extern "C" { /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ #define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ #define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ #define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ @@ -63,6 +64,11 @@ extern "C" { #define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ #define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ #define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#if defined(SYSCFG_PMCR_I2C5_FMP) +#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ +#else +#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ +#endif /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h index 56cc59e..356eee4 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -292,20 +292,43 @@ typedef struct __MDMA_HandleTypeDef #define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */ #define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */ #define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */ +#if defined (LTDC) #define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */ +#endif /* LTDC */ +#if defined (JPEG) #define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */ #define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */ #define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */ #define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */ #define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */ +#endif /* JPEG */ +#if defined (OCTOSPI1) +#define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */ +#endif /* OCTOSPI1 */ +#if defined (QUADSPI) #define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */ #define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */ +#endif /* QUADSPI */ #define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */ #define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */ #define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */ +#if defined (DSI) +#define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */ +#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */ +#endif /* DSI */ + #define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */ +#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */ +#define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */ + +#if defined (OCTOSPI2) +#define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */ +#endif /* OCTOSPI2 */ + #define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ /** @@ -316,9 +339,9 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Transfer Trigger Mode * @{ */ -#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ -#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ -#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ +#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ +#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ +#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ #define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ /** @@ -343,10 +366,10 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Endianness * @{ */ -#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ -#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ -#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD*/ -#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ +#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ +#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ +#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ +#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ /** * @} @@ -356,14 +379,14 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Source increment mode * @{ */ -#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ -#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/ -#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ -#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/ +#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ #define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ -#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/ -#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ -#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/ +#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ #define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ /** @@ -374,14 +397,14 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Destination increment mode * @{ */ -#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ -#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/ -#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ -#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/ +#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ #define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ -#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/ -#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ -#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/ +#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ #define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ /** @@ -392,9 +415,9 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Source data size * @{ */ -#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ -#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ -#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ +#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ +#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ +#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ #define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ /** @@ -405,9 +428,9 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Destination data size * @{ */ -#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ -#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ -#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ +#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ +#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ +#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ #define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ /** @@ -419,11 +442,11 @@ typedef struct __MDMA_HandleTypeDef * @{ */ #define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size - All data are right aligned, in Little Endien mode. */ -#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ + All data are right aligned, in Little Endien mode. */ +#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ #define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , Note : this mode is allowed only if the Source data size is smaller than Destination data size */ -#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ +#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ /** * @} @@ -434,12 +457,12 @@ typedef struct __MDMA_HandleTypeDef * @{ */ #define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ -#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ -#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ -#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ -#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ -#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ -#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ +#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ +#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ +#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ +#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ +#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ +#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ #define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ /** @@ -451,12 +474,12 @@ typedef struct __MDMA_HandleTypeDef * @{ */ #define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ -#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ -#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ -#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ -#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ -#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ -#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ +#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ +#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ +#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ +#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ +#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ +#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ #define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ /** @@ -467,11 +490,11 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA interrupt enable definitions * @{ */ -#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ +#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ #define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ -#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ -#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ -#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ +#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ +#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ +#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ /** * @} @@ -481,12 +504,12 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA flag definitions * @{ */ -#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ -#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ +#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ +#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ #define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ -#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ -#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ -#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */ +#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ +#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ +#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */ /** * @} @@ -575,8 +598,8 @@ typedef struct __MDMA_HandleTypeDef /** * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt source to check. * @arg MDMA_IT_TE : Transfer Error interrupt mask * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask @@ -586,6 +609,21 @@ typedef struct __MDMA_HandleTypeDef */ #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) +/** + * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. + * @param __HANDLE__ : MDMA handle + * @param __COUNTER__: Number of data in bytes to be transferred. + * @retval None + */ +#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) + +/** + * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. + * @param __HANDLE__ : MDMA handle + * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. + */ +#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) + /** * @} */ @@ -708,18 +746,22 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) -#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ - ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ - ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ - ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) +#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ + ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ + ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ + ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) -#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ - ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ - ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ - ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) +#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) -#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA)) +#if defined (OCTOSPI2) +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC)) +#else +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END)) +#endif /* OCTOSPI2 */ #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \ ((__INC__) == MDMA_SRC_INC_BYTE ) || \ @@ -752,9 +794,9 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ - ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ - ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ - ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ @@ -777,9 +819,9 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); ((__BURST__) == MDMA_DEST_BURST_128BEATS)) #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ - ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ - ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ - ((__MODE__) == MDMA_FULL_TRANSFER)) + ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_FULL_TRANSFER)) #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h index a47aaae..109d89a 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h @@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef typedef struct #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; @@ -244,7 +244,7 @@ typedef enum HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ @@ -363,14 +363,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @{ */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U - -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U - #define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12) /*!< USB FS EXTI Line WakeUp Interrupt */ #define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11) /*!< USB HS EXTI Line WakeUp Interrupt */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h index 72850e2..3b3b5bd 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -23,7 +23,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" @@ -47,11 +47,15 @@ */ typedef struct { - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This + parameter can be a value of @ref + PWR_PVD_detection_level. + */ - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ + uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD + event. This parameter can be a value of @ref + PWR_PVD_Mode. + */ }PWR_PVDTypeDef; /** @@ -66,14 +70,22 @@ typedef struct /** @defgroup PWR_PVD_detection_level PWR PVD detection level * @{ */ -#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector level 0 selection : 1V95 */ -#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector level 1 selection : 2V1 */ -#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector level 2 selection : 2V25 */ -#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector level 3 selection : 2V4 */ -#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector level 4 selection : 2V55 */ -#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector level 5 selection : 2V7 */ -#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector level 6 selection : 2V85 */ -#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage (Compare internally to VREFINT) */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector + level 0 selection : 1V95 */ +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector + level 1 selection : 2V1 */ +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector + level 2 selection : 2V25 */ +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector + level 3 selection : 2V4 */ +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector + level 4 selection : 2V55 */ +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector + level 5 selection : 2V7 */ +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector + level 6 selection : 2V85 */ +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage + (Compare internally to VREF) */ /** * @} */ @@ -81,13 +93,13 @@ typedef struct /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -95,7 +107,7 @@ typedef struct /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) +#define PWR_MAINREGULATOR_ON (0U) #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS /** * @} @@ -104,8 +116,8 @@ typedef struct /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +#define PWR_SLEEPENTRY_WFI (0x01U) +#define PWR_SLEEPENTRY_WFE (0x02U) /** * @} */ @@ -113,8 +125,8 @@ typedef struct /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +#define PWR_STOPENTRY_WFI (0x01U) +#define PWR_STOPENTRY_WFE (0x02U) /** * @} */ @@ -122,10 +134,17 @@ typedef struct /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale * @{ */ -#define PWR_REGULATOR_VOLTAGE_SCALE0 ((uint32_t)0x00000000) +#if defined(PWR_SRDCR_VOS) +#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) +#else +#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) #define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) +#endif /* PWR_SRDCR_VOS */ /** * @} */ @@ -133,29 +152,48 @@ typedef struct /** @defgroup PWR_Flag PWR Flag * @{ */ -#define PWR_FLAG_STOP ((uint8_t)0x01U) -#define PWR_FLAG_SB_D1 ((uint8_t)0x02U) -#define PWR_FLAG_SB_D2 ((uint8_t)0x03U) -#define PWR_FLAG_SB ((uint8_t)0x04U) -#if defined(DUAL_CORE) -#define PWR_FLAG_CPU_HOLD ((uint8_t)0x05U) -#define PWR_FLAG_CPU2_HOLD ((uint8_t)0x06U) -#define PWR_FLAG2_STOP ((uint8_t)0x07U) -#define PWR_FLAG2_SB_D1 ((uint8_t)0x08U) -#define PWR_FLAG2_SB_D2 ((uint8_t)0x09U) -#define PWR_FLAG2_SB ((uint8_t)0x0AU) -#endif /*DUAL_CORE*/ -#define PWR_FLAG_PVDO ((uint8_t)0x0BU) -#define PWR_FLAG_AVDO ((uint8_t)0x0CU) -#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU) -#define PWR_FLAG_ACTVOS ((uint8_t)0x0EU) -#define PWR_FLAG_BRR ((uint8_t)0x0FU) -#define PWR_FLAG_VOSRDY ((uint8_t)0x10U) -#if defined(SMPS) -#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U) +/* PWR CPU flag */ +#define PWR_FLAG_STOP (0x01U) +#if defined (PWR_CPUCR_SBF_D2) +#define PWR_FLAG_SB_D1 (0x02U) +#define PWR_FLAG_SB_D2 (0x03U) +#endif /* defined (PWR_CPUCR_SBF_D2) */ +#define PWR_FLAG_SB (0x04U) +#if defined (DUAL_CORE) +#define PWR_FLAG_CPU_HOLD (0x05U) +#define PWR_FLAG_CPU2_HOLD (0x06U) +#define PWR_FLAG2_STOP (0x07U) +#define PWR_FLAG2_SB_D1 (0x08U) +#define PWR_FLAG2_SB_D2 (0x09U) +#define PWR_FLAG2_SB (0x0AU) +#endif /* defined (DUAL_CORE) */ +#define PWR_FLAG_PVDO (0x0BU) +#define PWR_FLAG_AVDO (0x0CU) +#define PWR_FLAG_ACTVOSRDY (0x0DU) +#define PWR_FLAG_ACTVOS (0x0EU) +#define PWR_FLAG_BRR (0x0FU) +#define PWR_FLAG_VOSRDY (0x10U) +#if defined (SMPS) +#define PWR_FLAG_SMPSEXTRDY (0x11U) #else -#define PWR_FLAG_SCUEN ((uint8_t)0x11U) -#endif /* SMPS */ +#define PWR_FLAG_SCUEN (0x11U) +#endif /* defined (SMPS) */ +#if defined (PWR_CSR1_MMCVDO) +#define PWR_FLAG_MMCVDO (0x12U) +#endif /* defined (PWR_CSR1_MMCVDO) */ +#define PWR_FLAG_USB33RDY (0x13U) +#define PWR_FLAG_TEMPH (0x14U) +#define PWR_FLAG_TEMPL (0x15U) +#define PWR_FLAG_VBATH (0x16U) +#define PWR_FLAG_VBATL (0x17U) + +/* PWR Wake up flag */ +#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 +#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 +#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 +#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 +#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 +#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 /** * @} */ @@ -163,7 +201,7 @@ typedef struct /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask * @{ */ -#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU) +#define PWR_EWUP_MASK (0x0FFF3F3FU) /** * @} */ @@ -176,141 +214,288 @@ typedef struct * @{ */ -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). +/** @brief Configure the main internal regulator output voltage. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * trade-off between performance and power consumption + * when the device does not operate at the maximum + * frequency (refer to the datasheet for more details). * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - * @note PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO. - * the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0 - * using macro __HAL_RCC_SYSCFG_CLK_ENABLE(). - * Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in - * PWR_REGULATOR_VOLTAGE_SCALE1. - * transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1 - * then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale. - * After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG - * To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first - * switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode. - * - * @retval None + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * Scale 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * Scale 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * Scale 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0 using + * __HAL_PWR_VOLTAGESCALING_CONFIG(). + * Transition to Voltage Scale 0 is only possible when the system is + * already in Voltage Scale 1. + * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 + * then once in Voltage Scale 1 it is possible to switch to another + * voltage scale. + * After each regulator voltage setting, wait on VOSRDY flag to be set + * using macro __HAL_PWR_GET_FLAG(). + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval None. */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ -do { \ - __IO uint32_t tmpreg = 0x00; \ - if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ - { \ - MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ - /* Delay after setting the voltage scaling */ \ - tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ - MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \ - /* Delay after setting the syscfg boost setting */ \ - tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ - } \ - else \ - { \ - CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ - /* Delay after setting the syscfg boost setting */ \ - tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ - MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ - tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ - } \ - UNUSED(tmpreg); \ +#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ + UNUSED(tmpreg); \ } while(0) +#else /* 3 power domains devices */ +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Check the voltage scaling to be configured */ \ + if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ + { \ + /* Configure the Voltage Scaling 1 */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + /* Enable the PWR overdrive */ \ + SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + } \ + else \ + { \ + /* Disable the PWR overdrive */ \ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Configure the Voltage Scaling x */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + } \ + UNUSED(tmpreg); \ +} while(0) +#else /* STM32H72xxx and STM32H73xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#endif /* defined(SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ -#if defined(DUAL_CORE) -/** @brief Check PWR PVD/AVD and VOSflags are set or not. - * @param __FLAG__: specifies the flag to check. +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. * This parameter can be one of the following values: - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled - * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode. - * For this reason, this bit is equal to 0 after Standby or reset - * until the AVDE bit is set. - * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_STOP: STOP flag - * @arg PWR_FLAG_SB_D1: StandBy D1 flag - * @arg PWR_FLAG_SB_D2: StandBy D2 flag - * @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold - * @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD + * is enabled by the HAL_PWR_EnablePVD() + * function. + * The PVD is stopped by STANDBY mode. For this + * reason, this bit is equal to 0 after STANDBY + * or reset until the PVDE bit is set. + * @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD + * is enabled by the HAL_PWREx_EnableAVD() + * function. The AVD is stopped by STANDBY mode. + * For this reason, this bit is equal to 0 + * after STANDBY or reset until the AVDE bit + * is set. + * @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is + * ready. + * @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not + * reset when the device wakes up from STANDBY + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is ready. + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply + * from regulator is ready. + * @arg PWR_FLAG_TEMPH : This flag indicates that the temperature + * equal or above high threshold level. + * @arg PWR_FLAG_TEMPL : This flag indicates that the temperature + * equal or below low threshold level. + * @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal + * or above high threshold level. + * @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal + * or below low threshold level. + * @arg PWR_FLAG_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG_SB : This flag indicates that the system entered in + * STANDBY mode. + * @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG2_SB : This flag indicates that the system entered + * in STANDBY mode. + * @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes + * up with hold. + * @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes + * up with hold. + * @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS + * External supply is sready. + * @arg PWR_FLAG_SCUEN : This flag indicates that the supply + * configuration update is enabled. + * @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is + * above or equal to 1.2 V. + * @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, + * PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, + * PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags + * are used for all H7 family lines. + * The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, + * PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 + * dual core lines. + * The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 + * family except STM32H7Axxx and STM32H7Bxxx lines. + * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and + * STM32H7Bxxx lines. + * The PWR_FLAG_SCUEN flag is used for devices that support only LDO + * regulator. + * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO + * and SMPS regulators. + * @retval The (__FLAG__) state (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ( \ -((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \ -((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \ -((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \ -((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \ -((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \ -((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \ -((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \ -((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \ -((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \ -((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \ -((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \ -((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \ -((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \ -((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \ -((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \ -(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)) -#else -/** @brief Check PWR PVD/AVD and VOSflags are set or not. - * @param __FLAG__: specifies the flag to check. +#if defined (DUAL_CORE) /* Dual core lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\ + ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* Single core lines */ +#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ +#if defined (SMPS) /* STM32H725 and STM32H735 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* defined (SMPS) */ +#else /* STM32H7Axxx and STM32H7Bxxx lines */ +#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H7Axx and STM32H7Bxx lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* SMPS */ +#endif /* PWR_CPUCR_SBF_D2 */ +#endif /* DUAL_CORE */ + +/** @brief Check PWR wake up flags are set or not. + * @param __FLAG__: specifies the wake up flag to check. * This parameter can be one of the following values: - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled - * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode. - * For this reason, this bit is equal to 0 after Standby or reset - * until the AVDE bit is set. - * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_STOP: STOP flag - * @arg PWR_FLAG_SB_D1: StandBy D1 flag - * @arg PWR_FLAG_SB_D2: StandBy D2 flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval The (__FLAG__) state (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ( \ -((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \ -((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \ -((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \ -((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \ -((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \ -((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \ -((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \ -((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \ -((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \ -((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2)) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) - -#if defined(DUAL_CORE) -/** @brief Clear PWR flags. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_SB: Standby flag. - * @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags. +#if defined (DUAL_CORE) +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2. + * This parameter can be one of the following values : + * @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 + * CPU flags. * @retval None. */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ @@ -319,157 +504,171 @@ do { \ SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \ } while(0) #else -/** @brief Clear PWR flags. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_SB: Standby flag. - * @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags. +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags. + * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU + * flags are STOPF, SBF, SBF_D1 and SBF_D2. + * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. * @retval None. */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) +#endif /* defined (DUAL_CORE) */ + +/** @brief Clear PWR wake up flags. + * @param __FLAG__ : Specifies the wake up flag to be cleared. + * This parameter can be one of the following values : + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval None. + */ +#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) /** * @brief Enable the PVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** * @brief Enable the PVD EXTI D2 Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ /** * @brief Disable the PVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** * @brief Disable the PVD EXTI D2 Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ /** * @brief Enable event on PVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief Enable event on PVD EXTI D2 Line. + * @brief Enable event on PVD EXTI D2 Line. * @retval None. */ -#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ /** * @brief Disable event on PVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief Disable event on PVD EXTI D2 Line. + * @brief Disable event on PVD EXTI D2 Line. * @retval None. */ -#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ /** - * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @brief Enable the PVD Rising Interrupt Trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) /** - * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @brief Disable the PVD Rising Interrupt Trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) /** - * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @brief Enable the PVD Falling Interrupt Trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) /** - * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @brief Disable the PVD Falling Interrupt Trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) /** - * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @brief Enable the PVD Rising & Falling Interrupt Trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ -do { \ - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ +do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ } while(0); /** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @brief Disable the PVD Rising & Falling Interrupt Trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ -do { \ - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ +do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ } while(0); /** - * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @retval EXTI PVD Line Status. */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET) +#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) - -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @brief Checks whether the specified PVD EXTI interrupt flag is set or not. * @retval EXTI D2 PVD Line Status. */ -#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ /** * @brief Clear the PVD EXTI flag. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** * @brief Clear the PVD EXTI D2 flag. * @retval None. */ -#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ /** * @brief Generates a Software interrupt on PVD EXTI line. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) /** * @} */ - /* Include PWR HAL Extension module */ #include "stm32h7xx_hal_pwr_ex.h" @@ -478,44 +677,44 @@ do { \ * @{ */ -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions * @{ */ /* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); +void HAL_PWR_DeInit (void); +void HAL_PWR_EnableBkUpAccess (void); +void HAL_PWR_DisableBkUpAccess (void); /** * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions * @{ */ /* Peripheral Control functions **********************************************/ /* PVD configuration */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD (void); +void HAL_PWR_DisablePVD (void); /* WakeUp pins configuration */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); /* Low Power modes entry */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode (void); /* Power PVD IRQ Handler */ -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); +void HAL_PWR_PVD_IRQHandler (void); +void HAL_PWR_PVDCallback (void); /* Cortex System Control functions *******************************************/ -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); +void HAL_PWR_EnableSleepOnExit (void); +void HAL_PWR_DisableSleepOnExit (void); +void HAL_PWR_EnableSEVOnPend (void); +void HAL_PWR_DisableSEVOnPend (void); /** * @} */ @@ -534,8 +733,8 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line * @{ */ -/*!< External interrupt line 16 Connected to the PVD EXTI Line */ -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16) +#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the PVD EXTI Line */ /** * @} */ @@ -551,26 +750,42 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters * @{ */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +/* Check PVD level parameter */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\ + ((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) ||\ + ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) ||\ + ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) ||\ + ((LEVEL) == PWR_PVDLEVEL_7)) -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) +/* Check PVD mode parameter */ +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_NORMAL)) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ +/* Check low power regulator parameter */ +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +/* Check low power mode entry parameter */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ +/* Check low power mode entry parameter */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE)) + +/* Check voltage scale level parameter */ +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) - /** * @} */ @@ -589,8 +804,7 @@ void HAL_PWR_DisableSEVOnPend(void); #ifdef __cplusplus } -#endif - +#endif /* __cplusplus */ #endif /* STM32H7xx_HAL_PWR_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h index cd13961..9e87e12 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -23,7 +23,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" @@ -45,11 +45,15 @@ */ typedef struct { - uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level. - This parameter can be a value of @ref PWREx_AVD_detection_level */ + uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This + parameter can be a value of @ref + PWREx_AVD_detection_level + */ - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWREx_AVD_Mode */ + uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD + event. This parameter can be a value of @ref + PWREx_AVD_Mode. + */ }PWREx_AVDTypeDef; /** @@ -57,19 +61,37 @@ typedef struct */ typedef struct { - uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. - This parameter can be a value of @ref PWREx_WakeUp_Pins */ + uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref + PWREx_WakeUp_Pins + */ - uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. - This parameter can be a value of @ref PWREx_PIN_Polarity */ + uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref + PWREx_PIN_Polarity + */ - uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. - This parameter can be a value of @ref PWREx_PIN_Pull */ + uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This + parameter can be a value of @ref + PWREx_PIN_Pull + */ }PWREx_WakeupPinTypeDef; +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief PWR VDDMMC voltage level enum definition + */ +typedef enum +{ + PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ + PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ +} PWREx_MMC_VoltageLevel; +#endif /* defined (PWR_CSR1_MMCVDO) */ + /** * @} */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Constants PWREx Exported Constants @@ -78,26 +100,41 @@ typedef struct /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins * @{ */ -#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 -#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 -#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 -#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 -#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 -#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 + /* High level and No pull */ -#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 -#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 -#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 -#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 -#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 -#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 +#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 + /* Low level and No pull */ -#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) -#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) -#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) -#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) -#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) -#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) +#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) +#if defined (PWR_WKUPEPR_WKUPP5) +#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) +#endif /* defined (PWR_WKUPEPR_WKUPP5) */ +#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) +#if defined (PWR_WKUPEPR_WKUPP3) +#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) +#endif /* defined (PWR_WKUPEPR_WKUPP3) */ +#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) +#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) /** * @} */ @@ -105,8 +142,8 @@ typedef struct /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration * @{ */ -#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U) -#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U) +#define PWR_PIN_POLARITY_HIGH (0x00000000U) +#define PWR_PIN_POLARITY_LOW (0x00000001U) /** * @} */ @@ -114,44 +151,57 @@ typedef struct /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration * @{ */ -#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U) -#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U) -#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U) +#define PWR_PIN_NO_PULL (0x00000000U) +#define PWR_PIN_PULL_UP (0x00000001U) +#define PWR_PIN_PULL_DOWN (0x00000002U) /** * @} */ - /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. * @{ */ -#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */ -#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */ -#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */ -#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */ -#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */ -#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */ +#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ + PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) +#else +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) +#endif /* defined (PWR_WKUPFR_WKUPF3) */ /** * @} */ -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** @defgroup PWREx_Core_Select PWREx Core definition * @{ */ -#define PWR_CORE_CPU1 ((uint32_t)0x00000000U) -#define PWR_CORE_CPU2 ((uint32_t)0x00000001U) +#define PWR_CORE_CPU1 (0x00000000U) +#define PWR_CORE_CPU2 (0x00000001U) /** * @} */ -#endif /*DUAL_CORE*/ +#endif /* defined (DUAL_CORE) */ /** @defgroup PWREx_Domains PWREx Domains definition * @{ */ -#define PWR_D1_DOMAIN ((uint32_t)0x00000000U) -#define PWR_D2_DOMAIN ((uint32_t)0x00000001U) -#define PWR_D3_DOMAIN ((uint32_t)0x00000002U) +#define PWR_D1_DOMAIN (0x00000000U) +#if defined (PWR_CPUCR_PDDS_D2) +#define PWR_D2_DOMAIN (0x00000001U) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ +#define PWR_D3_DOMAIN (0x00000002U) /** * @} */ @@ -159,12 +209,13 @@ typedef struct /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition * @{ */ -#if defined(DUAL_CORE) -#define PWR_D1_DOMAIN_FLAGS ((uint32_t)0x00000000U) -#define PWR_D2_DOMAIN_FLAGS ((uint32_t)0x00000001U) +#if defined (DUAL_CORE) +#define PWR_D1_DOMAIN_FLAGS (0x00000000U) +#define PWR_D2_DOMAIN_FLAGS (0x00000001U) +#define PWR_ALL_DOMAIN_FLAGS (0x00000002U) #else -#define PWR_CPU_FLAGS ((uint32_t)0x00000000U) -#endif /*DUAL_CORE*/ +#define PWR_CPU_FLAGS (0x00000000U) +#endif /* defined (DUAL_CORE) */ /** * @} */ @@ -172,8 +223,8 @@ typedef struct /** @defgroup PWREx_D3_State PWREx D3 Domain State * @{ */ -#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U) -#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U) +#define PWR_D3_DOMAIN_STOP (0x00000000U) +#define PWR_D3_DOMAIN_RUN (0x00000800U) /** * @} @@ -183,23 +234,23 @@ typedef struct * @{ */ #define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */ -#if defined(SMPS) +#if defined (SMPS) #define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */ -#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ -#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */ #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */ #define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ #define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ -#endif /* SMPS */ +#endif /* defined (SMPS) */ #define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ -#if defined(SMPS) -#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ - PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#if defined (SMPS) +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ + PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) #else -#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) -#endif /* SMPS */ +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#endif /* defined (SMPS) */ /** * @} */ @@ -208,10 +259,14 @@ typedef struct /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level * @{ */ -#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 -#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 -#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 -#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 +#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 + selection : 1V7 */ +#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 + selection : 2V1 */ +#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 + selection : 2V5 */ +#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 + selection : 2V8 */ /** * @} */ @@ -219,13 +274,13 @@ typedef struct /** @defgroup PWREx_AVD_Mode PWREx AVD Mode * @{ */ -#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */ -#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -233,9 +288,9 @@ typedef struct /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale * @{ */ -#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) -#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) -#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) +#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) +#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) +#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /** * @} */ @@ -243,8 +298,8 @@ typedef struct /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection * @{ */ -#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ -#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ /** * @} */ @@ -252,7 +307,7 @@ typedef struct /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds * @{ */ -#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U) +#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) #define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL #define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH /** @@ -262,7 +317,7 @@ typedef struct /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds * @{ */ -#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U) +#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) #define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL #define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH /** @@ -271,14 +326,37 @@ typedef struct /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 * @{ */ -#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */ +#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the AVD EXTI Line */ /** * @} */ + +#if defined (PWR_CR1_SRDRAMSO) +/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection + * @{ + */ +#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ +#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ +#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ +#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ +#define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ +#define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ /** * @} */ +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ + /** @defgroup PWREx_Exported_Macro PWREx Exported Macro * @{ */ @@ -287,192 +365,202 @@ typedef struct * @brief Enable the AVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** * @brief Enable the AVD EXTI D2 Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ /** * @brief Disable the AVD EXTI Line 16 * @retval None. */ -#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** * @brief Disable the AVD EXTI D2 Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ /** - * @brief Enable event on AVD EXTI Line 16. + * @brief Enable event on AVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief Enable event on AVD EXTI D2 Line 16. + * @brief Enable event on AVD EXTI D2 Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ /** - * @brief Disable event on AVD EXTI Line 16. + * @brief Disable event on AVD EXTI Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief Disable event on AVD EXTI D2 Line 16. + * @brief Disable event on AVD EXTI D2 Line 16. * @retval None. */ -#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ /** - * @brief Enable the AVD Extended Interrupt Rising Trigger. + * @brief Enable the AVD Extended Interrupt Rising Trigger. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) /** - * @brief Disable the AVD Extended Interrupt Rising Trigger. + * @brief Disable the AVD Extended Interrupt Rising Trigger. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) /** - * @brief Enable the AVD Extended Interrupt Falling Trigger. + * @brief Enable the AVD Extended Interrupt Falling Trigger. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) - +#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) /** - * @brief Disable the AVD Extended Interrupt Falling Trigger. + * @brief Disable the AVD Extended Interrupt Falling Trigger. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) - +#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) /** - * @brief AVD EXTI line configuration: set rising & falling edge trigger. + * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ } while(0); /** - * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. + * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ -do { \ - __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ } while(0); /** - * @brief Check whether the specified AVD EXTI interrupt flag is set or not. + * @brief Check whether the specified AVD EXTI interrupt flag is set or not. * @retval EXTI AVD Line Status. */ -#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET) +#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. + * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. * @retval EXTI D2 AVD Line Status. */ -#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ /** * @brief Clear the AVD EXTI flag. * @retval None. */ -#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) +#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** * @brief Clear the AVD EXTI D2 flag. * @retval None. */ -#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) -#endif /*DUAL_CORE*/ +#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ +/** + * @brief Generates a Software interrupt on AVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) /** * @} */ /* Exported functions --------------------------------------------------------*/ + /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions * @{ */ -/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions * @{ */ -/* Power supply control functions */ -HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); -uint32_t HAL_PWREx_GetSupplyConfig(void); -/* Power volatge scaling functions */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling); -uint32_t HAL_PWREx_GetStopModeVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig (void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange (void); +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange (void); /** * @} */ -/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions * @{ */ /* System low power control functions */ -void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); -void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain); -void HAL_PWREx_ConfigD3Domain(uint32_t D3State); - -#if defined(DUAL_CORE) -void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags); - -/* Power core holding functions */ -HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU); -void HAL_PWREx_ReleaseCore(uint32_t CPU); - -#endif /*DUAL_CORE*/ - -/* Clear pending event function */ -void HAL_PWREx_ClearPendingEvent(void); - +#if defined (PWR_CPUCR_RETDS_CD) +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); +#endif /* defined (PWR_CPUCR_RETDS_CD) */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); +void HAL_PWREx_ConfigD3Domain (uint32_t D3State); +/* Clear Cortex-Mx pending flag */ +void HAL_PWREx_ClearPendingEvent (void); +#if defined (DUAL_CORE) +/* Clear domain flags */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); +/* Core Hold/Release functions */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); +void HAL_PWREx_ReleaseCore (uint32_t CPU); +#endif /* defined (DUAL_CORE) */ /* Flash low power control functions */ -void HAL_PWREx_EnableFlashPowerDown(void); -void HAL_PWREx_DisableFlashPowerDown(void); +void HAL_PWREx_EnableFlashPowerDown (void); +void HAL_PWREx_DisableFlashPowerDown (void); +#if defined (PWR_CR1_SRDRAMSO) +/* Memory shut-off functions */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); +#endif /* defined(PWR_CR1_SRDRAMSO) */ /* Wakeup Pins control functions */ -void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams); -void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin); -uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag); -HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag); - +void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); /* Power Wakeup PIN IRQ Handler */ -void HAL_PWREx_WAKEUP_PIN_IRQHandler(void); -void HAL_PWREx_WKUP1_Callback(void); -void HAL_PWREx_WKUP2_Callback(void); -void HAL_PWREx_WKUP3_Callback(void); -void HAL_PWREx_WKUP4_Callback(void); -void HAL_PWREx_WKUP5_Callback(void); -void HAL_PWREx_WKUP6_Callback(void); +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); +void HAL_PWREx_WKUP1_Callback (void); +void HAL_PWREx_WKUP2_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN3) +void HAL_PWREx_WKUP3_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +void HAL_PWREx_WKUP4_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN5) +void HAL_PWREx_WKUP5_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +void HAL_PWREx_WKUP6_Callback (void); /** * @} */ @@ -481,18 +569,21 @@ void HAL_PWREx_WKUP6_Callback(void); * @{ */ /* Backup regulator control functions */ -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); - +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); /* USB regulator control functions */ -HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void); -HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void); -void HAL_PWREx_EnableUSBVoltageDetector(void); -void HAL_PWREx_DisableUSBVoltageDetector(void); - +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); +void HAL_PWREx_EnableUSBVoltageDetector (void); +void HAL_PWREx_DisableUSBVoltageDetector (void); /* Battery control functions */ -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); -void HAL_PWREx_DisableBatteryCharging(void); +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging (void); +#if defined (PWR_CR1_BOOSTE) +/* Analog Booster functions */ +void HAL_PWREx_EnableAnalogBooster (void); +void HAL_PWREx_DisableAnalogBooster (void); +#endif /* PWR_CR1_BOOSTE */ /** * @} */ @@ -501,20 +592,20 @@ void HAL_PWREx_DisableBatteryCharging(void); * @{ */ /* Power VBAT/Temperature monitoring functions */ -void HAL_PWREx_EnableMonitoring(void); -void HAL_PWREx_DisableMonitoring(void); -uint32_t HAL_PWREx_GetTemperatureLevel(void); -uint32_t HAL_PWREx_GetVBATLevel(void); - +void HAL_PWREx_EnableMonitoring (void); +void HAL_PWREx_DisableMonitoring (void); +uint32_t HAL_PWREx_GetTemperatureLevel (void); +uint32_t HAL_PWREx_GetVBATLevel (void); +#if defined (PWR_CSR1_MMCVDO) +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); +#endif /* PWR_CSR1_MMCVDO */ /* Power AVD configuration functions */ -void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD); -void HAL_PWREx_EnableAVD(void); -void HAL_PWREx_DisableAVD(void); - +void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_EnableAVD (void); +void HAL_PWREx_DisableAVD (void); /* Power PVD/AVD IRQ Handler */ -void HAL_PWREx_PVD_AVD_IRQHandler(void); -void HAL_PWREx_AVDCallback(void); - +void HAL_PWREx_PVD_AVD_IRQHandler (void); +void HAL_PWREx_AVDCallback (void); /** * @} */ @@ -533,87 +624,149 @@ void HAL_PWREx_AVDCallback(void); /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters * @{ */ -#if defined(SMPS) -#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \ - ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \ - ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \ - ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \ - ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \ - ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \ - ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \ - ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \ - ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) +/* Check PWR regulator configuration parameter */ +#if defined (SMPS) +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) #else -#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \ - ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) -#endif /*SMPS*/ +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) +#endif /* defined (SMPS) */ -#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \ - ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \ - ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) -#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \ - ((DOMAIN) == PWR_D2_DOMAIN) || \ - ((DOMAIN) == PWR_D3_DOMAIN)) +/* Check PWR domain parameter */ +#if defined (PWR_CPUCR_PDDS_D2) +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D2_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#else +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ -#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN)) +/* Check D3/SRD domain state parameter */ +#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ + ((STATE) == PWR_D3_DOMAIN_RUN)) -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN6) || \ - ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN6_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN5_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN6_LOW)) +/* Check wake up pin parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ -#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ - ((POLARITY) == PWR_PIN_POLARITY_LOW)) +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ + ((POLARITY) == PWR_PIN_POLARITY_LOW)) -#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \ - ((PULL) == PWR_PIN_PULL_UP) || \ - ((PULL) == PWR_PIN_PULL_DOWN)) +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ + ((PULL) == PWR_PIN_PULL_UP) ||\ + ((PULL) == PWR_PIN_PULL_DOWN)) -#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \ - ((FLAG) == PWR_WAKEUP_FLAG2) || \ - ((FLAG) == PWR_WAKEUP_FLAG3) || \ - ((FLAG) == PWR_WAKEUP_FLAG4) || \ - ((FLAG) == PWR_WAKEUP_FLAG5) || \ - ((FLAG) == PWR_WAKEUP_FLAG6)) +/* Check wake up flag parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG3) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG5) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#else +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ -#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \ - ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3)) +/* Check wake up flag parameter */ +#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ + ((LEVEL) == PWR_AVDLEVEL_1) ||\ + ((LEVEL) == PWR_AVDLEVEL_2) ||\ + ((LEVEL) == PWR_AVDLEVEL_3)) -#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_AVD_MODE_NORMAL)) - -#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) +/* Check AVD mode parameter */ +#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_NORMAL) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) +/* Check resistor battery parameter */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) +/* Check D1/CD CPU ID parameter */ #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) +/* Check CPU parameter */ #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) +/* Check D2 CPU ID parameter */ #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) +/* Check PWR domain flag parameter */ #define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ - ((FLAG) == PWR_D2_DOMAIN_FLAGS)) -#endif /*DUAL_CORE*/ + ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) +#endif /* defined (DUAL_CORE) */ +#if defined (PWR_CR1_SRDRAMSO) +/* Check memory block parameter */ +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) +#endif /* defined (PWR_CR1_SRDRAMSO) */ /** * @} */ @@ -630,7 +783,7 @@ void HAL_PWREx_AVDCallback(void); */ #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32H7xx_HAL_PWR_EX_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h index 4d2cdf0..d7d955c 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h @@ -12,7 +12,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -28,6 +28,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined(QUADSPI) + /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -44,35 +46,27 @@ /** * @brief QSPI Init structure definition */ - typedef struct { uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. This parameter can be a number between 0 and 255 */ - uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) This parameter can be a value between 1 and 32 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits required to address the flash memory. The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number of clock cycles which the chip select must remain high between commands. This parameter can be a value of @ref QSPI_ChipSelectHighTime */ - uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ - uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ - uint32_t DualFlash; /* Specifies the Dual Flash Mode State This parameter can be a value of @ref QSPI_DualFlash_Mode */ }QSPI_InitTypeDef; @@ -100,7 +94,7 @@ typedef enum typedef struct __QSPI_HandleTypeDef #else typedef struct -#endif/* USE_HAL_QSPI_REGISTER_CALLBACKS */ +#endif { QUADSPI_TypeDef *Instance; /* QSPI registers base address */ QSPI_InitTypeDef Init; /* QSPI communication parameters */ @@ -110,7 +104,7 @@ typedef struct uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ - MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ + MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ __IO HAL_LockTypeDef Lock; /* Locking object */ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ __IO uint32_t ErrorCode; /* QSPI Error code */ @@ -155,13 +149,13 @@ typedef struct This parameter can be a value of @ref QSPI_AlternateBytesMode */ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) This parameter can be a value of @ref QSPI_DataMode */ - uint32_t NbData; /* Specifies the number of data to transfer. + uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length until end of memory)*/ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of - system clock in DDR mode. + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ uint32_t SIOOMode; /* Specifies the send instruction only once mode This parameter can be a value of @ref QSPI_SIOOMode */ @@ -193,7 +187,7 @@ typedef struct { uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ - uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref QSPI_TimeOutActivation */ }QSPI_MemoryMappedTypeDef; @@ -233,11 +227,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ #endif @@ -248,7 +242,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -499,8 +493,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -512,8 +506,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -526,8 +520,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -540,8 +534,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -558,12 +552,22 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @addtogroup QSPI_Exported_Functions * @{ */ + +/** @addtogroup QSPI_Exported_Functions_Group1 + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); +/** + * @} + */ +/** @addtogroup QSPI_Exported_Functions_Group2 + * @{ + */ /* IO operation functions *****************************************************/ /* QSPI IRQ handler method */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); @@ -626,12 +630,15 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ +/** + * @} + */ /* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Macros QSPI Private Macros -* @{ -*/ + * @{ + */ #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) @@ -653,7 +660,6 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ ((CLKMODE) == QSPI_CLOCK_MODE_3)) - #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ ((FLASH_ID) == QSPI_FLASH_ID_2)) @@ -730,9 +736,8 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ -/** - * @} - */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + #ifdef __cplusplus } #endif diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h index 9268474..a705190 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -57,7 +57,9 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ uint32_t PLLP; /*!< PLLP: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 @@ -78,7 +80,6 @@ typedef struct }RCC_PLLInitTypeDef; - /** * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition */ @@ -176,6 +177,9 @@ typedef struct #define RCC_HSE_OFF (0x00000000U) #define RCC_HSE_ON RCC_CR_HSEON #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +#if defined(RCC_CR_HSEEXT) +#define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) +#endif /* RCC_CR_HSEEXT */ /** * @} @@ -187,6 +191,9 @@ typedef struct #define RCC_LSE_OFF (0x00000000U) #define RCC_LSE_ON RCC_BDCR_LSEON #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +#if defined(RCC_BDCR_LSEEXT) +#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +#endif /* RCC_BDCR_LSEEXT */ /** * @} @@ -204,8 +211,7 @@ typedef struct #define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION) /*!< HSI_DIV8 clock activation */ - -#define RCC_HSICALIBRATION_DEFAULT (0x20U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */ /** * @} */ @@ -236,8 +242,7 @@ typedef struct #define RCC_CSI_OFF (0x00000000U) #define RCC_CSI_ON RCC_CR_CSION -#define RCC_CSICALIBRATION_DEFAULT (0x10U) /* Default CSI calibration trimming value */ - +#define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */ /** * @} */ @@ -281,10 +286,10 @@ typedef struct /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range * @{ */ -#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 -#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 -#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 -#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 +#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ /** @@ -343,6 +348,7 @@ typedef struct /** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source * @{ */ +#if defined(RCC_D1CFGR_D1CPRE_DIV1) #define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1 #define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2 #define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4 @@ -352,7 +358,17 @@ typedef struct #define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128 #define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256 #define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512 - +#else +#define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512 +#endif /** * @} */ @@ -361,6 +377,7 @@ typedef struct /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source * @{ */ +#if defined(RCC_D1CFGR_HPRE_DIV1) #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1 #define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2 #define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4 @@ -370,7 +387,17 @@ typedef struct #define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128 #define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256 #define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512 - +#else +#define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1 +#define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2 +#define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4 +#define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8 +#define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16 +#define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64 +#define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128 +#define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256 +#define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512 +#endif /** * @} */ @@ -378,12 +405,19 @@ typedef struct /** @defgroup RCC_APB3_Clock_Source RCC APB3 Clock Source * @{ */ +#if defined (RCC_D1CFGR_D1PPRE_DIV1) #define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1 #define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2 #define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4 #define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8 #define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16 - +#else +#define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1 +#define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2 +#define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4 +#define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8 +#define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16 +#endif /** * @} */ @@ -391,11 +425,19 @@ typedef struct /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source * @{ */ +#if defined (RCC_D2CFGR_D2PPRE1_DIV1) #define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1 #define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2 #define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4 #define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8 #define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16 +#else +#define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1 +#define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2 +#define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4 +#define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8 +#define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16 +#endif /** * @} @@ -404,12 +446,19 @@ typedef struct /** @defgroup RCC_APB2_Clock_Source RCC APB2 Clock Source * @{ */ +#if defined (RCC_D2CFGR_D2PPRE2_DIV1) #define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1 #define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2 #define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4 #define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8 #define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16 - +#else +#define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1 +#define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2 +#define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4 +#define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8 +#define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16 +#endif /** * @} */ @@ -417,12 +466,19 @@ typedef struct /** @defgroup RCC_APB4_Clock_Source RCC APB4 Clock Source * @{ */ +#if defined(RCC_D3CFGR_D3PPRE_DIV1) #define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1 #define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2 #define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4 #define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8 #define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16 - +#else +#define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1 +#define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2 +#define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4 +#define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8 +#define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16 +#endif /** * @} */ @@ -430,6 +486,7 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) #define RCC_RTCCLKSOURCE_LSE (0x00000100U) #define RCC_RTCCLKSOURCE_LSI (0x00000200U) #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) @@ -595,8 +652,18 @@ typedef struct #define RCC_FLAG_HSIDIV ((uint8_t)0x25) #define RCC_FLAG_CSIRDY ((uint8_t)0x28) #define RCC_FLAG_HSI48RDY ((uint8_t)0x2D) +#if defined(RCC_CR_D1CKRDY) #define RCC_FLAG_D1CKRDY ((uint8_t)0x2E) +#else +#define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E) +#define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */ +#endif /* RCC_CR_D1CKRDY */ +#if defined(RCC_CR_D2CKRDY) #define RCC_FLAG_D2CKRDY ((uint8_t)0x2F) +#else +#define RCC_FLAG_CDCKRDY ((uint8_t)0x2F) +#define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */ +#endif /* RCC_CR_D2CKRDY */ #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) @@ -608,10 +675,18 @@ typedef struct #define RCC_FLAG_LSIRDY ((uint8_t)0x61) /* Flags in the RSR register */ +#if defined(RCC_RSR_CPURSTF) #define RCC_FLAG_CPURST ((uint8_t)0x91) +#endif /* RCC_RSR_CPURSTF */ +#if defined(RCC_RSR_D1RSTF) #define RCC_FLAG_D1RST ((uint8_t)0x93) +#else +#define RCC_FLAG_CDRST ((uint8_t)0x93) +#endif /* RCC_RSR_D1RSTF */ +#if defined(RCC_RSR_D2RSTF) #define RCC_FLAG_D2RST ((uint8_t)0x94) +#endif /* RCC_RSR_D2RSTF */ #define RCC_FLAG_BORRST ((uint8_t)0x95) #define RCC_FLAG_PINRST ((uint8_t)0x96) #define RCC_FLAG_PORRST ((uint8_t)0x97) @@ -666,6 +741,14 @@ typedef struct /** * @} */ + +#if defined(RCC_VER_X) +#define HAL_RCC_REV_Y_HSITRIM_Pos (12U) +#define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U) +#define HAL_RCC_REV_Y_CSITRIM_Pos (26U) +#define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U) +#endif /* RCC_VER_X */ + /** * @} */ @@ -696,6 +779,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ UNUSED(tmpreg); \ } while(0) + #if defined(JPEG) #define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -706,7 +790,6 @@ typedef struct } while(0) #endif /* JPEG */ - #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ @@ -715,6 +798,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ @@ -722,7 +806,61 @@ typedef struct tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ UNUSED(tmpreg); \ } while(0) - +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ @@ -734,15 +872,33 @@ typedef struct #define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) - #if defined(JPEG) #define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) #endif /* JPEG */ - #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN)) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN)) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN)) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN)) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN)) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN)) +#endif /* GFXMMU */ /** @brief Get the enable or disable status of the AHB3 peripheral clock * @note After reset, the peripheral clock (used for registers read/write access) @@ -752,27 +908,61 @@ typedef struct #define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) - #if defined(JPEG) #define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) #endif /* JPEG */ - #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) +#if defined (QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U) +#endif /* OCTOSPI2 */ #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ #define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) - #if defined(JPEG) #define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) #endif /* JPEG */ - #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) +#if defined (QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) +#endif /* QUADSPI */ #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) - - +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U) +#endif +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U) +#endif +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U) +#endif +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U) +#endif +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U) +#endif +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U) +#endif /** @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before @@ -813,6 +1003,17 @@ typedef struct } while(0) #endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ETH) #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ @@ -836,6 +1037,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ UNUSED(tmpreg); \ } while(0) +#endif #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -853,6 +1055,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ @@ -868,6 +1071,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ UNUSED(tmpreg); \ } while(0) +#endif #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) @@ -875,14 +1079,20 @@ typedef struct #if defined(DUAL_CORE) #define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) #endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN)) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) #define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) #define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#endif #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) - +#endif /* USB2_OTG_FS */ /** @brief Get the enable or disable status of the AHB1 peripheral clock * @note After reset, the peripheral clock (used for registers read/write access) @@ -896,13 +1106,20 @@ typedef struct #if defined(DUAL_CORE) #define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U) #endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) +#endif #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) +#endif /* USB2_OTG_FS */ #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) @@ -910,13 +1127,20 @@ typedef struct #if defined(DUAL_CORE) #define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U) #endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) #define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) #define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) +#endif #define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) +#endif /* USB2_OTG_FS */ /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -924,6 +1148,17 @@ typedef struct * using it. */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ @@ -931,7 +1166,9 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -939,7 +1176,9 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ @@ -947,6 +1186,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -964,6 +1204,27 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMAC */ + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CORDIC */ + +#if defined(RCC_AHB2ENR_D2SRAM1EN) #define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ @@ -971,7 +1232,17 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ UNUSED(tmpreg); \ } while(0) +#else +#define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) #define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ @@ -979,7 +1250,17 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ UNUSED(tmpreg); \ } while(0) +#else +#define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) #define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ @@ -987,16 +1268,67 @@ typedef struct tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ UNUSED(tmpreg); \ } while(0) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_HSEMEN */ + +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* BDMA1 */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN)) +#define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) #define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN)) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) #define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN)) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) #define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) - +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN)) +#endif /** @brief Get the enable or disable status of the AHB2 peripheral clock * @note After reset, the peripheral clock (used for registers read/write access) @@ -1004,23 +1336,85 @@ typedef struct * using it. */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) #define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) #define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) #define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U) +#endif +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) #define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) #define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) #define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U) +#endif /** @brief Enable or disable the AHB4 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1092,6 +1486,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ @@ -1099,6 +1494,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1116,6 +1512,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(RCC_AHB4ENR_CRCEN) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ @@ -1123,7 +1520,19 @@ typedef struct tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ UNUSED(tmpreg); \ } while(0) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ @@ -1131,7 +1540,9 @@ typedef struct tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ UNUSED(tmpreg); \ } while(0) +#endif +#if defined(ADC3) #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ @@ -1139,7 +1550,9 @@ typedef struct tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ UNUSED(tmpreg); \ } while(0) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) #define __HAL_RCC_HSEM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ @@ -1147,6 +1560,17 @@ typedef struct tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ UNUSED(tmpreg); \ } while(0) +#endif + +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1165,13 +1589,29 @@ typedef struct #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#if defined(RCC_AHB4ENR_CRCEN) #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN) +#define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#endif +#if defined(ADC3) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) #define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN) +#endif #define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) @@ -1189,13 +1629,29 @@ typedef struct #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) +#if defined(RCC_AHB4ENR_CRCEN) #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) +#endif +#if defined(ADC3) #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) #define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U) +#endif #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) @@ -1206,13 +1662,30 @@ typedef struct #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) + +#if defined(RCC_AHB4ENR_CRCEN) #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) +#endif +#if defined(ADC3) #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) #define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U) +#endif #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) @@ -1253,38 +1726,33 @@ typedef struct #if defined(LTDC) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) #endif /*DSI*/ #define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) - /** @brief Get the enable or disable status of the APB3 peripheral clock * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ + #if defined(LTDC) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U) #endif /*DSI*/ #define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) - #if defined(LTDC) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U) #endif /*DSI*/ #define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) - /** @brief Enable or disable the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before @@ -1461,6 +1929,16 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + #define __HAL_RCC_CEC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ @@ -1533,6 +2011,25 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM23 */ + +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM24 */ #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) @@ -1559,6 +2056,9 @@ typedef struct #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN) +#endif /* I2C5 */ #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) #define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) @@ -1568,6 +2068,12 @@ typedef struct #define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) #define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) #define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN) +#endif /* TIM24 */ /** @brief Get the enable or disable status of the APB1 peripheral clock @@ -1599,6 +2105,9 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U) +#endif /* I2C5 */ #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) #define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) @@ -1608,6 +2117,12 @@ typedef struct #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U) +#endif /* TIM24 */ #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) @@ -1632,6 +2147,9 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U) +#endif /* I2C5 */ #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) #define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) @@ -1641,6 +2159,12 @@ typedef struct #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) #define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U) +#endif /* TIM24 */ /** @brief Enable or disable the APB2 peripheral clock. @@ -1681,6 +2205,26 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*UART9*/ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*USART10*/ + #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ @@ -1737,6 +2281,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ @@ -1744,7 +2289,9 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ UNUSED(tmpreg); \ } while(0) +#endif /*SAI2*/ +#if defined(SAI3) #define __HAL_RCC_SAI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ @@ -1752,6 +2299,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ UNUSED(tmpreg); \ } while(0) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1761,6 +2309,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ @@ -1768,11 +2317,18 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ UNUSED(tmpreg); \ } while(0) +#endif /*HRTIM1*/ #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN) +#endif /*USART10*/ #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) @@ -1780,11 +2336,16 @@ typedef struct #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#endif /*SAI2*/ +#if defined(SAI3) #define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) - +#endif /*HRTIM*/ /** @brief Get the enable or disable status of the APB2 peripheral clock * @note After reset, the peripheral clock (used for registers read/write access) @@ -1796,6 +2357,12 @@ typedef struct #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U) +#endif /*USART10*/ #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) @@ -1803,15 +2370,27 @@ typedef struct #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) +#if defined(SAI2) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) +#endif /*SAI2*/ +#if defined(SAI3) #define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) +#endif /* SAI3 */ #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) +#endif /*HRTIM1*/ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U) +#endif /*USART10*/ #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) @@ -1819,11 +2398,16 @@ typedef struct #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) +#if defined(SAI2) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) +#endif /*SAI2*/ +#if defined(SAI3) #define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) - +#endif /*HRTIM1*/ /** @brief Enable or disable the APB4 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -1879,6 +2463,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ @@ -1886,7 +2471,9 @@ typedef struct tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ UNUSED(tmpreg); \ } while(0) +#endif /* LPTIM4 */ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ @@ -1894,6 +2481,17 @@ typedef struct tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ UNUSED(tmpreg); \ } while(0) +#endif /* LPTIM5 */ + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DAC2 */ #define __HAL_RCC_COMP12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1911,6 +2509,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(SAI4) #define __HAL_RCC_SAI4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ @@ -1918,6 +2517,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ UNUSED(tmpreg); \ } while(0) +#endif /* SAI4 */ #define __HAL_RCC_RTC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1927,18 +2527,53 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DTS*/ + +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DFSDM2*/ + #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) #define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#if defined(SAI4) #define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN) +#endif /*DFSDM2*/ /** @brief Get the enable or disable status of the APB4 peripheral clock * @note After reset, the peripheral clock (used for registers read/write access) @@ -1952,12 +2587,27 @@ typedef struct #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) #define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) +#if defined(SAI4) #define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U) +#endif /*DFSDM2*/ #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) @@ -1965,13 +2615,27 @@ typedef struct #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) #define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) +#if defined(SAI4) #define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) - +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U) +#endif /*DFSDM2*/ #if defined(DUAL_CORE) @@ -2165,7 +2829,7 @@ typedef struct tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ UNUSED(tmpreg); \ } while(0) - +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -2173,7 +2837,9 @@ typedef struct tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ @@ -2181,6 +2847,7 @@ typedef struct tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -2223,8 +2890,12 @@ typedef struct } while(0) #define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) #define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) @@ -3153,7 +3824,6 @@ typedef struct UNUSED(tmpreg); \ } while(0) - #define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ @@ -3162,6 +3832,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) + #define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) #define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) #define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) @@ -3188,6 +3859,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -3195,7 +3867,9 @@ typedef struct tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ @@ -3203,6 +3877,7 @@ typedef struct tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -3245,8 +3920,12 @@ typedef struct } while(0) #define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) #define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) #define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) @@ -3982,45 +4661,99 @@ typedef struct /** @brief Enable or disable the AHB3 peripheral reset. */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */ +#else +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) - #if defined(JPEG) #define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) #endif /* JPEG */ - #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) - +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) #define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) - #if defined(JPEG) #define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) #endif /* JPEG */ - #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ /** @brief Force or release the AHB1 peripheral reset. */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */ +#else +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) #if defined(DUAL_CORE) #define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST)) #endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) @@ -4029,32 +4762,92 @@ typedef struct #if defined(DUAL_CORE) #define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST)) #endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) - +#endif /*USB2_OTG_FS*/ /** @brief Force or release the AHB2 peripheral reset. */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */ +#else +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ /** @brief Force or release the AHB4 peripheral reset. */ -#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */ +#else +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) @@ -4063,13 +4856,26 @@ typedef struct #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) #define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) +#endif #define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) @@ -4080,41 +4886,61 @@ typedef struct #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) #define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) - +#endif /** @brief Force or release the APB3 peripheral reset. */ -#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0xFFFFFFFFU) - +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */ +#else +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #if defined(LTDC) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST) #endif /*DSI*/ #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) - #if defined(LTDC) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST) #endif /*DSI*/ /** @brief Force or release the APB1 peripheral reset. */ -#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xFFFFFFFFU) -#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */ +#else +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */ +#else +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) @@ -4135,6 +4961,9 @@ typedef struct #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) #define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) @@ -4144,6 +4973,12 @@ typedef struct #define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) #define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) #define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ #define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) #define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) @@ -4167,6 +5002,9 @@ typedef struct #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) #define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) @@ -4176,14 +5014,32 @@ typedef struct #define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) #define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) #define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ /** @brief Force or release the APB2 peripheral reset. */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */ +#else +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) @@ -4191,16 +5047,28 @@ typedef struct #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) #define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) @@ -4208,26 +5076,53 @@ typedef struct #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) #define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ /** @brief Force or release the APB4 peripheral reset. */ -#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0xFFFFFFFFU) +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */ +#else +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */ +#endif /* STM32H7_DEV_ID == 0x450UL */ #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) #define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) #define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) #define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ #define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) @@ -4236,11 +5131,26 @@ typedef struct #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) #define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(RCC_APB4RSTR_DAC2RST) +#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST) +#endif #define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) #define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -4252,37 +5162,95 @@ typedef struct #define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) - #if defined(JPEG) #define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) #endif /* JPEG */ - #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) #define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) - +#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ #define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) - #if defined(JPEG) #define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) #endif /* JPEG */ - #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) #define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) - +#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -4293,36 +5261,91 @@ typedef struct #define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) - #if defined(JPEG) #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) #endif /* JPEG */ - #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) +#endif /*QUADSPI*/ #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U) +#endif #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U) +#endif #define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) - #if defined(JPEG) #define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) #endif /* JPEG */ - #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) +#if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) +#endif /*QUADSPI*/ #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U) +#endif #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) #define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) #define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) - +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U) +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ /** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -4334,31 +5357,48 @@ typedef struct #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ #if defined(DUAL_CORE) #define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN)) #endif /*DUAL_CORE*/ +#if defined(ETH) #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ #if defined(DUAL_CORE) #define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN)) #endif /*DUAL_CORE*/ +#if defined(ETH) #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) #define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) #define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) - +#endif /* USB2_OTG_FS */ /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -4370,30 +5410,48 @@ typedef struct #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) +#endif /*ETH*/ #if defined(DUAL_CORE) #define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U) #endif /*DUAL_CORE*/ +#if defined(ETH) #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) +#endif /*ETH*/ #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) +#endif /* USB2_OTG_FS */ #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U) +#endif +#if defined(ETH) #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) +#endif /* ETH */ #if defined(DUAL_CORE) #define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U) #endif /*DUAL_CORE*/ +#if defined(ETH) #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) +#endif /* ETH */ #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) #define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) +#if defined(USB2_OTG_FS) #define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) #define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) +#endif /* USB2_OTG_FS */ /** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. @@ -4403,24 +5461,79 @@ typedef struct * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) #define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) #define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) #define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) #define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) #define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) #define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) - +#endif /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -4429,23 +5542,79 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/ +#else #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) +#endif /* HASH */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) +#endif #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) #define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) #define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) #define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/ /** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. @@ -4463,14 +5632,30 @@ typedef struct #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else #define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#endif /* BDMA2 */ +#if defined(ADC3) #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#endif /* ADC3 */ #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else #define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */ #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) @@ -4480,14 +5665,30 @@ typedef struct #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/ +#else #define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#endif /*BDMA2*/ +#if defined(ADC3) #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#endif /*ADC3*/ #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE +#else #define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif /** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. @@ -4505,14 +5706,30 @@ typedef struct #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else #define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) +#endif /*BDMA2*/ +#if defined(ADC3) #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) +#endif /*ADC3*/ #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) +#endif #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) @@ -4522,14 +5739,30 @@ typedef struct #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) +#if defined(GPIOI) #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) +#endif /* GPIOI */ #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else #define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) +#endif /*BDMA2*/ +#if defined(ADC3) #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) +#endif /*ADC3*/ #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else #define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) +#endif /** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. @@ -4542,7 +5775,6 @@ typedef struct #if defined(LTDC) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) #endif /*DSI*/ @@ -4551,7 +5783,6 @@ typedef struct #if defined(LTDC) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) #endif /*DSI*/ @@ -4568,7 +5799,6 @@ typedef struct #if defined(LTDC) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U) #endif /*DSI*/ @@ -4577,7 +5807,6 @@ typedef struct #if defined(LTDC) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) #endif /* LTDC */ - #if defined(DSI) #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U) #endif /*DSI*/ @@ -4616,6 +5845,9 @@ typedef struct #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) #define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) @@ -4625,6 +5857,12 @@ typedef struct #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) @@ -4652,6 +5890,9 @@ typedef struct #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) #define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) @@ -4661,6 +5902,12 @@ typedef struct #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. @@ -4693,6 +5940,9 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U) +#endif /* I2C5 */ #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) #define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) @@ -4702,6 +5952,12 @@ typedef struct #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U) +#endif /* TIM24 */ #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) @@ -4726,6 +5982,9 @@ typedef struct #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U) +#endif /* I2C5 */ #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) #define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) @@ -4735,6 +5994,12 @@ typedef struct #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U) +#endif /* TIM24 */ /** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. @@ -4748,6 +6013,12 @@ typedef struct #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) @@ -4755,15 +6026,27 @@ typedef struct #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) #define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) @@ -4771,10 +6054,16 @@ typedef struct #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) #define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. @@ -4788,6 +6077,12 @@ typedef struct #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U) +#endif /*USART10*/ #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) @@ -4795,15 +6090,27 @@ typedef struct #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) +#if defined(SAI2) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) +#endif /* SAI2 */ +#if defined(SAI3) #define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) +#endif /*HRTIM1*/ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) +#if defined(UART9) +#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U) +#endif /*USART10*/ #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) @@ -4811,11 +6118,16 @@ typedef struct #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) +#if defined(SAI2) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) +#endif /* SAI2 */ +#if defined(SAI3) #define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) +#endif /*SAI3*/ #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) +#if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) - +#endif /*HRTIM1*/ /** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -4830,12 +6142,27 @@ typedef struct #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) #define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) @@ -4843,13 +6170,27 @@ typedef struct #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) #define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) - +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ /** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. @@ -4865,12 +6206,27 @@ typedef struct #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) +#if defined(SAI4) #define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U) +#endif /*DFSDM2*/ #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) @@ -4878,12 +6234,27 @@ typedef struct #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U) +#endif /*DAC2*/ #define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) #define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) +#if defined(SAI4) #define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U) +#endif /*DFSDM2*/ #if defined(DUAL_CORE) @@ -4958,8 +6329,12 @@ typedef struct */ #define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -4967,8 +6342,12 @@ typedef struct #define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) #define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -5246,8 +6625,12 @@ typedef struct */ #define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -5255,8 +6638,12 @@ typedef struct #define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) #define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) #define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) #define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ #define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) #define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) #define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) @@ -5473,41 +6860,255 @@ typedef struct */ #endif /*DUAL_CORE*/ +#if defined(RCC_D3AMR_BDMAAMEN) #define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) #define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) #define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) #define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) #define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) #define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) #define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) #define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) #define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) #define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) #define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) - +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) #define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) #define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN) +#endif + +#if defined(RCC_D3AMR_BDMAAMEN) #define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) #define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) #define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) #define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) #define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) #define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) #define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) #define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) -#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_RTCAMEN) -#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_CRCAMEN) -#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_SAI4AMEN) -#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~(RCC_D3AMR_ADC3AMEN) - +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) #define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) #define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(RCC_SRDAMR_DAC2AMEN) +#define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN) +#endif + + +#if defined(RCC_CKGAENR_AXICKG) +/** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register). + */ + +#define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG) + + +#define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG) + +#endif /* RCC_CKGAENR_AXICKG */ + + /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). @@ -5568,18 +7169,30 @@ typedef struct * @param __HSICalibrationValue__: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x7F (3F for Rev Y device). */ +#if defined(RCC_VER_X) #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ do { \ if(HAL_GetREVID() <= REV_ID_Y) \ { \ - MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);\ + if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \ } \ + } \ else \ { \ MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \ } \ } while(0) +#else +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ /** * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) * in STOP mode to be quickly available as kernel clock for some peripherals. @@ -5629,11 +7242,19 @@ typedef struct * @param __CSICalibrationValue__: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x1F. */ +#if defined(RCC_VER_X) #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ do { \ if(HAL_GetREVID() <= REV_ID_Y) \ { \ - MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ } \ else \ { \ @@ -5641,6 +7262,13 @@ typedef struct } \ } while(0) +#else +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } while(0) + +#endif /*RCC_VER_X*/ /** * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. @@ -5684,6 +7312,39 @@ typedef struct * @arg RCC_HSE_ON: turn ON the HSE oscillator. * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. */ +#if defined(RCC_CR_HSEEXT) +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) +#else #define __HAL_RCC_HSE_CONFIG(__STATE__) \ do { \ if ((__STATE__) == RCC_HSE_ON) \ @@ -5706,6 +7367,7 @@ typedef struct CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ } while(0) +#endif /* RCC_CR_HSEEXT */ /** @defgroup RCC_LSE_Configuration LSE Configuration * @{ @@ -5715,20 +7377,60 @@ typedef struct * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). + A duty cycle close to 50% is recommended. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. + * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) * @param __STATE__: specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg RCC_LSE_ON: turn ON the LSE oscillator. * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + * @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*) + * + * (*) Available on some STM32H7 lines only. */ +#if defined(RCC_BDCR_LSEEXT) +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + } \ + } while(0) +#else + #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ if((__STATE__) == RCC_LSE_ON) \ @@ -5751,6 +7453,8 @@ typedef struct CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) + +#endif /* RCC_BDCR_LSEEXT */ /** * @} */ @@ -5794,7 +7498,7 @@ typedef struct /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. + * and the RTC clock source selection in RCC_BDCR register. * @note The BKPSRAM is not affected by this reset. */ #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) @@ -5817,9 +7521,14 @@ typedef struct * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted * This parameter can be one of the following values: - * @arg RCC_PLL1_DIVP: This clock is used to generate system clock (up to 400MHZ) - * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ) - * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock (up to 400MHZ) + * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * * @retval None */ #define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) @@ -5854,13 +7563,13 @@ typedef struct * frequency ranges from 1 to 16 MHz. * * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 4 and 512. + * This parameter must be a number between 4 and 512 or between 8 and 420(*). * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 150 and 420 MHz (when in medium VCO range) or - * between 192 and 836 MHZ (when in wide VCO range) + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) * * @param __PLLP1__: specifies the division factor for system clock. - * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) * * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks * This parameter must be a number between 1 and 128 @@ -5868,7 +7577,13 @@ typedef struct * @param __PLLR1__: specifies the division factor for peripheral kernel clocks * This parameter must be a number between 1 and 128 * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters. * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. */ @@ -5900,9 +7615,10 @@ typedef struct * It should be a value between 0 and 8191 * @note Warning: The software has to set correctly these bits to insure that the VCO * output frequency is between its valid frequency range, which is: - * 192 to 836 MHz if PLL1VCOSEL = 0 + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 * 150 to 420 MHz if PLL1VCOSEL = 1. * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ @@ -5925,8 +7641,11 @@ typedef struct /** @brief Macro to select the PLL1 reference frequency range. * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range * This parameter can be one of the following values: - * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz + * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * * @retval None */ #define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ @@ -6020,6 +7739,7 @@ typedef struct * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. * @retval None */ +#if defined(RCC_VER_X) #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ do{ \ if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \ @@ -6031,6 +7751,10 @@ typedef struct MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \ } \ } while(0) +#else +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); +#endif /*RCC_VER_X*/ /** * @brief Macro to configure the wake up from stop clock. * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop @@ -6188,16 +7912,19 @@ typedef struct * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready - * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready (*) + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready (*) + * @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*) + * @arg RCC_FLAG_CDCKRDY: CPU Domain clock ready (*) * @arg RCC_FLAG_PLLRDY: PLL1 clock ready * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready * @arg RCC_FLAG_CPURST: CPU reset flag - * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag - * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag (*) + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag (*) + * @arg RCC_FLAG_CDRST: CD domain power switch reset flag (*) * @arg RCC_FLAG_BORRST: BOR reset flag * @arg RCC_FLAG_PINRST: Pin reset * @arg RCC_FLAG_PORRST: POR/PDR reset @@ -6208,11 +7935,12 @@ typedef struct * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag * @retval The new state of __FLAG__ (TRUE or FALSE). + * + * (*) Available on some STM32H7 lines only. */ #define RCC_FLAG_MASK ((uint8_t)0x1F) #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) - #endif /*DUAL_CORE*/ /** @@ -6301,11 +8029,6 @@ void HAL_RCC_CCSCallback(void); * @{ */ -#define HAL_RCC_REV_Y_HSITRIM_Pos (12U) -#define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U) -#define HAL_RCC_REV_Y_CSITRIM_Pos (26U) -#define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U) - #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ @@ -6314,11 +8037,21 @@ void HAL_RCC_CCSCallback(void); (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) +#if defined(RCC_CR_HSEEXT) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL)) +#else #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_BYPASS)) +#endif /* RCC_CR_HSEEXT */ +#if defined(RCC_BDCR_LSEEXT) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL)) +#else #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_BYPASS)) +#endif /* RCC_BDCR_LSEEXT */ #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ @@ -6338,7 +8071,11 @@ void HAL_RCC_CCSCallback(void); ((SOURCE) == RCC_PLLSOURCE_NONE) || \ ((SOURCE) == RCC_PLLSOURCE_HSE)) #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#if !defined(RCC_VER_2_0) #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#else +#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U)) +#endif /* !RCC_VER_2_0 */ #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) @@ -6367,9 +8104,11 @@ void HAL_RCC_CCSCallback(void); ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ ((HCLK) == RCC_HCLK_DIV512)) -#define IS_RCC_D1PCLK1(D1PCLK1) (((D1PCLK1) == RCC_APB3_DIV1) || ((D1PCLK1) == RCC_APB3_DIV2) || \ - ((D1PCLK1) == RCC_APB3_DIV4) || ((D1PCLK1) == RCC_APB3_DIV8) || \ - ((D1PCLK1) == RCC_APB3_DIV16)) +#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \ + ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \ + ((CDPCLK1) == RCC_APB3_DIV16)) + +#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */ #define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ @@ -6379,9 +8118,11 @@ void HAL_RCC_CCSCallback(void); ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ ((PCLK2) == RCC_APB2_DIV16)) -#define IS_RCC_D3PCLK1(D3PCLK1) (((D3PCLK1) == RCC_APB4_DIV1) || ((D3PCLK1) == RCC_APB4_DIV2) || \ - ((D3PCLK1) == RCC_APB4_DIV4) || ((D3PCLK1) == RCC_APB4_DIV8) || \ - ((D3PCLK1) == RCC_APB4_DIV16)) +#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \ + ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \ + ((SRDPCLK1) == RCC_APB4_DIV16)) + +#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/ #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ @@ -6453,6 +8194,7 @@ void HAL_RCC_CCSCallback(void); #else +#if defined(RCC_CR_D2CKRDY) #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ @@ -6465,11 +8207,24 @@ void HAL_RCC_CCSCallback(void); ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#else +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#endif /* RCC_CR_D2CKRDY */ #endif /*DUAL_CORE*/ #define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) -#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) +#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) #define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h index 6103287..07102a6 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. + *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -51,7 +51,9 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. - This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 @@ -71,7 +73,6 @@ typedef struct PLL2 VCO It should be a value between 0 and 8191 */ }RCC_PLL2InitTypeDef; - /** * @brief PLL3 Clock structure definition */ @@ -82,7 +83,9 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. - This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 @@ -150,12 +153,21 @@ typedef struct uint32_t FmcClockSelection; /*!< Specifies FMC clock source This parameter can be a value of @ref RCCEx_FMC_Clock_Source */ +#if defined(QUADSPI) uint32_t QspiClockSelection; /*!< Specifies QSPI clock source This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + uint32_t OspiClockSelection; /*!< Specifies OSPI clock source + This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ +#endif /*(OCTOSPI1) || (OCTOSPI2)*/ + + #if defined(DSI) uint32_t DsiClockSelection; /*!< Specifies DSI clock source This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ -#endif /*DSI*/ +#endif /* DSI */ uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ @@ -166,8 +178,20 @@ typedef struct uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ +#if defined(SAI3) uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source - This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */ + This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */ +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + uint32_t Sai2AClockSelection; /*!< Specifies SAI2A clock source + This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source */ +#endif /* RCC_CDCCIP1R_SAI2ASEL */ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) + uint32_t Sai2BClockSelection; /*!< Specifies SAI2B clock source + This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source */ +#endif /* RCC_CDCCIP1R_SAI2BSEL */ uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */ @@ -180,6 +204,12 @@ typedef struct uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ + +#if defined(DFSDM2_BASE) + uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock clock source + This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source */ +#endif /* DFSDM2_BASE */ + #if defined(FDCAN1) || defined(FDCAN2) uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ @@ -197,8 +227,13 @@ typedef struct uint32_t RngClockSelection; /*!< Specifies RNG clock source This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ - uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source - This parameter can be a value of @ref RCCEx_I2C123_Clock_Source */ +#if defined(I2C5) + uint32_t I2c1235ClockSelection; /*!< Specifies I2C1/2/3/5 clock source + This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ +#else + uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source + This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source */ +#endif /*I2C5*/ uint32_t UsbClockSelection; /*!< Specifies USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ @@ -223,12 +258,13 @@ typedef struct uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ - +#if defined(SAI4) uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */ uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */ +#endif /* SAI4 */ uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */ @@ -236,12 +272,22 @@ typedef struct uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined(HRTIM1) uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ +#endif /* HRTIM1 */ + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ }RCC_PeriphCLKInitTypeDef; +/*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only */ +#if defined(I2C5) +#define I2c123ClockSelection I2c1235ClockSelection +#else +#define I2c1235ClockSelection I2c123ClockSelection +#endif /*I2C5*/ + /** * @brief RCC_CRS Init structure definition @@ -305,9 +351,21 @@ typedef struct * @{ */ +#if defined(UART9) && defined(USART10) +#define RCC_PERIPHCLK_USART16910 (0x00000001U) +#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16910 +#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16910 +#define RCC_PERIPHCLK_UART9 RCC_PERIPHCLK_USART16910 +#define RCC_PERIPHCLK_USART10 RCC_PERIPHCLK_USART16910 +/*alias*/ +#define RCC_PERIPHCLK_USART16 RCC_PERIPHCLK_USART16910 +#else #define RCC_PERIPHCLK_USART16 (0x00000001U) #define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16 #define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16 +/* alias */ +#define RCC_PERIPHCLK_USART16910 RCC_PERIPHCLK_USART16 +#endif /* UART9 && USART10*/ #define RCC_PERIPHCLK_USART234578 (0x00000002U) #define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578 #define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578 @@ -316,23 +374,49 @@ typedef struct #define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578 #define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578 #define RCC_PERIPHCLK_LPUART1 (0x00000004U) +#if defined(I2C5) +#define RCC_PERIPHCLK_I2C1235 (0x00000008U) +#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C1235 +#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C1235 +#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C1235 +/* alias */ +#define RCC_PERIPHCLK_I2C123 RCC_PERIPHCLK_I2C1235 +#else #define RCC_PERIPHCLK_I2C123 (0x00000008U) #define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123 #define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123 #define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123 +#endif /*I2C5*/ #define RCC_PERIPHCLK_I2C4 (0x00000010U) +#if defined(I2C5) +#define RCC_PERIPHCLK_I2C5 RCC_PERIPHCLK_I2C1235 +#endif /*I2C5*/ #define RCC_PERIPHCLK_LPTIM1 (0x00000020U) #define RCC_PERIPHCLK_LPTIM2 (0x00000040U) #define RCC_PERIPHCLK_LPTIM345 (0x00000080U) #define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345 +#if defined(LPTIM4) #define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345 +#endif /*LPTIM4*/ +#if defined(LPTIM5) #define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345 +#endif /*LPTIM5*/ #define RCC_PERIPHCLK_SAI1 (0x00000100U) +#if defined(SAI3) #define RCC_PERIPHCLK_SAI23 (0x00000200U) #define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23 #define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23 +#endif /* SAI3 */ +#if defined(RCC_CDCCIP1R_SAI2ASEL_0) +#define RCC_PERIPHCLK_SAI2A (0x00000200U) +#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */ +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) +#define RCC_PERIPHCLK_SAI2B (0x00000400U) +#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */ +#if defined(SAI4) #define RCC_PERIPHCLK_SAI4A (0x00000400U) #define RCC_PERIPHCLK_SAI4B (0x00000800U) +#endif /* SAI4 */ #define RCC_PERIPHCLK_SPI123 (0x00001000U) #define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123 #define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123 @@ -348,18 +432,26 @@ typedef struct #define RCC_PERIPHCLK_ADC (0x00080000U) #define RCC_PERIPHCLK_SWPMI1 (0x00100000U) #define RCC_PERIPHCLK_DFSDM1 (0x00200000U) +#if defined(DFSDM2_BASE) +#define RCC_PERIPHCLK_DFSDM2 (0x00000800U) +#endif /* DFSDM2 */ #define RCC_PERIPHCLK_RTC (0x00400000U) #define RCC_PERIPHCLK_CEC (0x00800000U) #define RCC_PERIPHCLK_FMC (0x01000000U) +#if defined(QUADSPI) #define RCC_PERIPHCLK_QSPI (0x02000000U) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +#define RCC_PERIPHCLK_OSPI (0x02000000U) +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ #define RCC_PERIPHCLK_DSI (0x04000000U) #define RCC_PERIPHCLK_SPDIFRX (0x08000000U) +#if defined(HRTIM1) #define RCC_PERIPHCLK_HRTIM1 (0x10000000U) - +#endif /* HRTIM1 */ #if defined(LTDC) #define RCC_PERIPHCLK_LTDC (0x20000000U) #endif /* LTDC */ - #define RCC_PERIPHCLK_TIM (0x40000000U) #define RCC_PERIPHCLK_CKPER (0x80000000U) @@ -393,10 +485,10 @@ typedef struct /** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range * @{ */ -#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 -#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 -#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 -#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 +#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ /** * @} @@ -416,10 +508,10 @@ typedef struct /** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range * @{ */ -#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 -#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 -#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 -#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 +#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0 /*!< Clock range frequency between 1 and 2 MHz */ +#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1 /*!< Clock range frequency between 2 and 4 MHz */ +#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2 /*!< Clock range frequency between 4 and 8 MHz */ +#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3 /*!< Clock range frequency between 8 and 16 MHz */ /** * @} @@ -439,12 +531,53 @@ typedef struct /** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source * @{ */ +#if defined(RCC_D2CCIP2R_USART16SEL) #define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U) -#define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 -#define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 -#define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) -#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 -#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) +/* alias */ +#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 +#define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0 +#define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1 +#define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) +#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2 +#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) + +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define RCC_USART16910CLKSOURCE_CDPCLK2 (0x00000000U) +/* alias */ +#define RCC_USART16910CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 +#define RCC_USART16910CLKSOURCE_PLL2 RCC_CDCCIP2R_USART16910SEL_0 +#define RCC_USART16910CLKSOURCE_PLL3 RCC_CDCCIP2R_USART16910SEL_1 +#define RCC_USART16910CLKSOURCE_HSI (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) +#define RCC_USART16910CLKSOURCE_CSI RCC_CDCCIP2R_USART16910SEL_2 +#define RCC_USART16910CLKSOURCE_LSE (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) + +/* Aliases */ +#define RCC_USART16CLKSOURCE_CDPCLK2 RCC_USART16910CLKSOURCE_CDPCLK2 +#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 +#define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_CDPCLK2 +#define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 +#define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 +#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI +#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI +#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE + +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define RCC_USART16910CLKSOURCE_D2PCLK2 (0x00000000U) +#define RCC_USART16910CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16910SEL_0 +#define RCC_USART16910CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16910SEL_1 +#define RCC_USART16910CLKSOURCE_HSI (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) +#define RCC_USART16910CLKSOURCE_CSI RCC_D2CCIP2R_USART16910SEL_2 +#define RCC_USART16910CLKSOURCE_LSE (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) + +/* Aliases */ +#define RCC_USART16CLKSOURCE_D2PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 +#define RCC_USART16CLKSOURCE_PCLK2 RCC_USART16910CLKSOURCE_D2PCLK2 +#define RCC_USART16CLKSOURCE_PLL2 RCC_USART16910CLKSOURCE_PLL2 +#define RCC_USART16CLKSOURCE_PLL3 RCC_USART16910CLKSOURCE_PLL3 +#define RCC_USART16CLKSOURCE_HSI RCC_USART16910CLKSOURCE_HSI +#define RCC_USART16CLKSOURCE_CSI RCC_USART16910CLKSOURCE_CSI +#define RCC_USART16CLKSOURCE_LSE RCC_USART16910CLKSOURCE_LSE +#endif /* RCC_D2CCIP2R_USART16SEL */ /** * @} */ @@ -476,16 +609,59 @@ typedef struct * @} */ +#if defined(UART9) +/** @defgroup RCCEx_UART9_Clock_Source RCCEx UART9 Clock Source + * @{ + */ +#define RCC_UART9CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 +#define RCC_UART9CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 +#define RCC_UART9CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 +#define RCC_UART9CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI +#define RCC_UART9CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI +#define RCC_UART9CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE +/** + * @} + */ +#endif /* UART9 */ + +#if defined(USART10) +/** @defgroup RCCEx_USART10_Clock_Source RCCEx USART10 Clock Source + * @{ + */ +#define RCC_USART10CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2 +#define RCC_USART10CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2 +#define RCC_USART10CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3 +#define RCC_USART10CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI +#define RCC_USART10CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI +#define RCC_USART10CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE +/** + * @} + */ +#endif /* USART10 */ + /** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source * @{ */ +#if defined(RCC_D2CCIP2R_USART28SEL) #define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U) -#define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 -#define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 -#define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) +/* alias */ +#define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1 +#define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0 +#define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1 +#define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) #define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2 -#define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) - +#define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) +#else +#define RCC_USART234578CLKSOURCE_CDPCLK1 (0x00000000U) +/* alias */ +#define RCC_USART234578CLKSOURCE_PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 +#define RCC_USART234578CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_CDPCLK1 +#define RCC_USART234578CLKSOURCE_PLL2 RCC_CDCCIP2R_USART234578SEL_0 +#define RCC_USART234578CLKSOURCE_PLL3 RCC_CDCCIP2R_USART234578SEL_1 +#define RCC_USART234578CLKSOURCE_HSI (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) +#define RCC_USART234578CLKSOURCE_CSI RCC_CDCCIP2R_USART234578SEL_2 +#define RCC_USART234578CLKSOURCE_LSE (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) +#endif /* RCC_D2CCIP2R_USART28SEL */ /** * @} */ @@ -577,25 +753,66 @@ typedef struct /** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source * @{ */ +#if defined(RCC_D3CCIPR_LPUART1SEL) #define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U) +/* alias */ +#define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_D3PCLK1 #define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) #define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2 #define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0) - +#else +#define RCC_LPUART1CLKSOURCE_SRDPCLK4 (0x00000000U) +/* alias*/ +#define RCC_LPUART1CLKSOURCE_PCLK4 RCC_LPUART1CLKSOURCE_SRDPCLK4 +#define RCC_LPUART1CLKSOURCE_D3PCLK1 RCC_LPUART1CLKSOURCE_SRDPCLK4 +#define RCC_LPUART1CLKSOURCE_PLL2 RCC_SRDCCIPR_LPUART1SEL_0 +#define RCC_LPUART1CLKSOURCE_PLL3 RCC_SRDCCIPR_LPUART1SEL_1 +#define RCC_LPUART1CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) +#define RCC_LPUART1CLKSOURCE_CSI RCC_SRDCCIPR_LPUART1SEL_2 +#define RCC_LPUART1CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0) +#endif /* RCC_D3CCIPR_LPUART1SEL */ /** * @} */ -/** @defgroup RCCEx_I2C123_Clock_Source RCCEx I2C1/2/3 Clock Source +/** @defgroup RCCEx_I2C1235_Clock_Source RCCEx I2C1/2/3/5 Clock Source * @{ */ +#if defined (RCC_D2CCIP2R_I2C123SEL) #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) #define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0 #define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1 #define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) - +/* aliases */ +#define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 +#define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 +#define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI +#define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define RCC_I2C123CLKSOURCE_CDPCLK1 (0x00000000U) +/* alias */ +#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_CDPCLK1 +#define RCC_I2C123CLKSOURCE_PLL3 RCC_CDCCIP2R_I2C123SEL_0 +#define RCC_I2C123CLKSOURCE_HSI RCC_CDCCIP2R_I2C123SEL_1 +#define RCC_I2C123CLKSOURCE_CSI (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) +/* aliases */ +#define RCC_I2C1235CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 +#define RCC_I2C1235CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 +#define RCC_I2C1235CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI +#define RCC_I2C1235CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI +#elif defined(I2C5) +#define RCC_I2C1235CLKSOURCE_D2PCLK1 (0x00000000U) +#define RCC_I2C1235CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C1235SEL_0 +#define RCC_I2C1235CLKSOURCE_HSI RCC_D2CCIP2R_I2C1235SEL_1 +#define RCC_I2C1235CLKSOURCE_CSI (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) +/* aliases */ +#define RCC_I2C123CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 +#define RCC_I2C123CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 +#define RCC_I2C123CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI +#define RCC_I2C123CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI +#endif /* RCC_D2CCIP2R_I2C123SEL */ /** * @} */ @@ -603,11 +820,17 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source * @{ */ +#if defined(I2C5) +#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 +#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 +#define RCC_I2C1CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI +#define RCC_I2C1CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI +#else #define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 #define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 #define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI #define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI - +#endif /*I2C5*/ /** * @} @@ -616,10 +839,17 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source * @{ */ +#if defined(I2C5) +#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 +#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 +#define RCC_I2C2CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI +#define RCC_I2C2CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI +#else #define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 #define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 #define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI #define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI +#endif /*I2C5*/ /** * @} @@ -628,10 +858,17 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source * @{ */ +#if defined(I2C5) +#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 +#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 +#define RCC_I2C3CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI +#define RCC_I2C3CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI +#else #define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1 #define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3 #define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI #define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI +#endif /*I2C5*/ /** * @} @@ -640,28 +877,56 @@ typedef struct /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source * @{ */ +#if defined(RCC_D3CCIPR_I2C4SEL) #define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U) #define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1 #define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) - +#else +#define RCC_I2C4CLKSOURCE_SRDPCLK4 (0x00000000U) +/* alias */ +#define RCC_I2C4CLKSOURCE_D3PCLK1 RCC_I2C4CLKSOURCE_SRDPCLK4 +#define RCC_I2C4CLKSOURCE_PLL3 RCC_SRDCCIPR_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_SRDCCIPR_I2C4SEL_1 +#define RCC_I2C4CLKSOURCE_CSI (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) +#endif /* RCC_D3CCIPR_I2C4SEL */ /** * @} */ +#if defined(I2C5) +/** @defgroup RCCEx_I2C5_Clock_Source RCCEx I2C5 Clock Source + * @{ + */ +#define RCC_I2C5CLKSOURCE_D2PCLK1 RCC_I2C1235CLKSOURCE_D2PCLK1 +#define RCC_I2C5CLKSOURCE_PLL3 RCC_I2C1235CLKSOURCE_PLL3 +#define RCC_I2C5CLKSOURCE_HSI RCC_I2C1235CLKSOURCE_HSI +#define RCC_I2C5CLKSOURCE_CSI RCC_I2C1235CLKSOURCE_CSI + +/** + * @} + */ +#endif /*I2C5*/ /** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source * @{ */ +#if defined(RCC_D2CCIP2R_RNGSEL) #define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) #define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0 #define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1 #define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL - +#else +#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U) +#define RCC_RNGCLKSOURCE_PLL RCC_CDCCIP2R_RNGSEL_0 +#define RCC_RNGCLKSOURCE_LSE RCC_CDCCIP2R_RNGSEL_1 +#define RCC_RNGCLKSOURCE_LSI RCC_CDCCIP2R_RNGSEL +#endif /* RCC_D2CCIP2R_RNGSEL */ /** * @} */ +#if defined(HRTIM1) /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source * @{ @@ -672,13 +937,20 @@ typedef struct /** * @} */ +#endif /*HRTIM1*/ /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source * @{ */ +#if defined(RCC_D2CCIP2R_USBSEL) #define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0 #define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1 #define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL +#else +#define RCC_USBCLKSOURCE_PLL RCC_CDCCIP2R_USBSEL_0 +#define RCC_USBCLKSOURCE_PLL3 RCC_CDCCIP2R_USBSEL_1 +#define RCC_USBCLKSOURCE_HSI48 RCC_CDCCIP2R_USBSEL +#endif /* RCC_D2CCIP2R_USBSEL */ /** * @} @@ -687,18 +959,24 @@ typedef struct /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ +#if defined(RCC_D2CCIP1R_SAI1SEL) #define RCC_SAI1CLKSOURCE_PLL (0x00000000U) #define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1 #define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) #define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2 - +#else +#define RCC_SAI1CLKSOURCE_PLL (0x00000000U) +#define RCC_SAI1CLKSOURCE_PLL2 RCC_CDCCIP1R_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_PLL3 RCC_CDCCIP1R_SAI1SEL_1 +#define RCC_SAI1CLKSOURCE_PIN (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) +#define RCC_SAI1CLKSOURCE_CLKP RCC_CDCCIP1R_SAI1SEL_2 +#endif /* RCC_D2CCIP1R_SAI1SEL */ /** * @} */ - - +#if defined(SAI3) /** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source * @{ */ @@ -707,7 +985,6 @@ typedef struct #define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1 #define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) #define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2 - /** * @} */ @@ -733,20 +1010,58 @@ typedef struct #define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3 #define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN #define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP - /** * @} */ +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +/** @defgroup RCCEx_SAI2A_Clock_Source SAI2A Clock Source + * @{ + */ +#define RCC_SAI2ACLKSOURCE_PLL (0x00000000U) +#define RCC_SAI2ACLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2ASEL_0 +#define RCC_SAI2ACLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2ASEL_1 +#define RCC_SAI2ACLKSOURCE_PIN (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) +#define RCC_SAI2ACLKSOURCE_CLKP RCC_CDCCIP1R_SAI2ASEL_2 +#define RCC_SAI2ACLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) + /** + * @} + */ +#endif /* RCC_CDCCIP1R_SAI2ASEL */ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +/** @defgroup RCCEx_SAI2B_Clock_Source SAI2B Clock Source + * @{ + */ +#define RCC_SAI2BCLKSOURCE_PLL (0x00000000U) +#define RCC_SAI2BCLKSOURCE_PLL2 RCC_CDCCIP1R_SAI2BSEL_0 +#define RCC_SAI2BCLKSOURCE_PLL3 RCC_CDCCIP1R_SAI2BSEL_1 +#define RCC_SAI2BCLKSOURCE_PIN (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) +#define RCC_SAI2BCLKSOURCE_CLKP RCC_CDCCIP1R_SAI2BSEL_2 +#define RCC_SAI2BCLKSOURCE_SPDIF (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) +/** + * @} + */ +#endif /* RCC_CDCCIP1R_SAI2BSEL */ + /** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source * @{ */ +#if defined(RCC_D2CCIP1R_SPI123SEL) #define RCC_SPI123CLKSOURCE_PLL (0x00000000U) #define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0 #define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1 #define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) #define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2 - +#else +#define RCC_SPI123CLKSOURCE_PLL (0x00000000U) +#define RCC_SPI123CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI123SEL_0 +#define RCC_SPI123CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI123SEL_1 +#define RCC_SPI123CLKSOURCE_PIN (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) +#define RCC_SPI123CLKSOURCE_CLKP RCC_CDCCIP1R_SPI123SEL_2 +#endif /* RCC_D2CCIP1R_SPI123SEL */ /** * @} */ @@ -793,13 +1108,25 @@ typedef struct /** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source * @{ */ +#if defined(RCC_D2CCIP1R_SPI45SEL) #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U) +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1 #define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0 #define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1 #define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) #define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2 #define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) - +#else +#define RCC_SPI45CLKSOURCE_CDPCLK1 (0x00000000U) +/* aliases */ +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_CDPCLK1 +#define RCC_SPI45CLKSOURCE_PLL2 RCC_CDCCIP1R_SPI45SEL_0 +#define RCC_SPI45CLKSOURCE_PLL3 RCC_CDCCIP1R_SPI45SEL_1 +#define RCC_SPI45CLKSOURCE_HSI (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) +#define RCC_SPI45CLKSOURCE_CSI RCC_CDCCIP1R_SPI45SEL_2 +#define RCC_SPI45CLKSOURCE_HSE (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) +#endif /* RCC_D2CCIP1R_SPI45SEL */ /** * @} */ @@ -835,19 +1162,33 @@ typedef struct /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source * @{ */ +#if defined(RCC_D3CCIPR_SPI6SEL) #define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U) +#define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_D3PCLK1 #define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0 #define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1 #define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) #define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2 #define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) - +#else +#define RCC_SPI6CLKSOURCE_SRDPCLK4 (0x00000000U) +/* alias */ +#define RCC_SPI6CLKSOURCE_D3PCLK1 RCC_SPI6CLKSOURCE_SRDPCLK4 /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */ +#define RCC_SPI6CLKSOURCE_PCLK4 RCC_SPI6CLKSOURCE_SRDPCLK4 +#define RCC_SPI6CLKSOURCE_PLL2 RCC_SRDCCIPR_SPI6SEL_0 +#define RCC_SPI6CLKSOURCE_PLL3 RCC_SRDCCIPR_SPI6SEL_1 +#define RCC_SPI6CLKSOURCE_HSI (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) +#define RCC_SPI6CLKSOURCE_CSI RCC_SRDCCIPR_SPI6SEL_2 +#define RCC_SPI6CLKSOURCE_HSE (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) +#define RCC_SPI6CLKSOURCE_PIN (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) +#endif /* RCC_D3CCIPR_SPI6SEL */ /** * @} */ +#if defined(SAI4_Block_A) /** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source * @{ */ @@ -856,13 +1197,18 @@ typedef struct #define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1 #define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) #define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2 - +#if defined(RCC_VER_3_0) +#define RCC_SAI4ACLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) +#endif /*RCC_VER_3_0*/ /** * @} */ +#endif /* SAI4_Block_A */ + +#if defined(SAI4_Block_B) /** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source * @{ */ @@ -871,22 +1217,39 @@ typedef struct #define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1 #define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) #define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2 +#if defined(RCC_VER_3_0) +#define RCC_SAI4BCLKSOURCE_SPDIF (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) +#endif /* RCC_VER_3_0 */ /** * @} */ +#endif /* SAI4_Block_B */ /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source * @{ */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) #define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U) +/* alias */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_D2PCLK1 #define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1 -#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) -#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 -#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) - +#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2 +#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) +#else +#define RCC_LPTIM1CLKSOURCE_CDPCLK1 (0x00000000U) +/* alias */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 +#define RCC_LPTIM1CLKSOURCE_D2PCLK1 RCC_LPTIM1CLKSOURCE_CDPCLK1 +#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_CDCCIP2R_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_CDCCIP2R_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CDCCIP2R_LPTIM1SEL_2 +#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ /** * @} @@ -895,13 +1258,26 @@ typedef struct /** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source * @{ */ -#define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U) +/* alias */ +#define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_D3PCLK1 #define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0 #define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1 -#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) -#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 -#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) - +#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) +#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2 +#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) +#else +#define RCC_LPTIM2CLKSOURCE_SRDPCLK4 (0x00000000U) +/*alias*/ +#define RCC_LPTIM2CLKSOURCE_PCLK4 RCC_LPTIM2CLKSOURCE_SRDPCLK4 +#define RCC_LPTIM2CLKSOURCE_D3PCLK1 RCC_LPTIM2CLKSOURCE_SRDPCLK4 +#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM2SEL_0 +#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM2SEL_1 +#define RCC_LPTIM2CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) +#define RCC_LPTIM2CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM2SEL_2 +#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ /** * @} */ @@ -909,13 +1285,26 @@ typedef struct /** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source * @{ */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) #define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U) +/* alias*/ +#define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_D3PCLK1 #define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0 #define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1 -#define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) -#define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2 -#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) - +#define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) +#define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2 +#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) +#else +#define RCC_LPTIM345CLKSOURCE_SRDPCLK4 (0x00000000U) +/* alias */ +#define RCC_LPTIM345CLKSOURCE_PCLK4 RCC_LPTIM345CLKSOURCE_SRDPCLK4 +#define RCC_LPTIM345CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_SRDPCLK4 +#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_SRDCCIPR_LPTIM3SEL_0 +#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_SRDCCIPR_LPTIM3SEL_1 +#define RCC_LPTIM345CLKSOURCE_LSE (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) +#define RCC_LPTIM345CLKSOURCE_LSI RCC_SRDCCIPR_LPTIM3SEL_2 +#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ /** * @} */ @@ -933,7 +1322,7 @@ typedef struct /** * @} */ - +#if defined(LPTIM4) /** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source * @{ */ @@ -943,11 +1332,12 @@ typedef struct #define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE #define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI #define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP - /** * @} */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) /** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source * @{ */ @@ -961,7 +1351,9 @@ typedef struct /** * @} */ +#endif /* LPTIM5 */ +#if defined(QUADSPI) /** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source * @{ */ @@ -970,11 +1362,39 @@ typedef struct #define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1 #define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL +/** + * @} + */ +#endif /* QUADSPI */ + + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCCEx_OSPI_Clock_Source RCCEx OSPI Clock Source + * @{ + */ + +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define RCC_OSPICLKSOURCE_CDHCLK (0x00000000U) +/*aliases*/ +#define RCC_OSPICLKSOURCE_D1HCLK RCC_OSPICLKSOURCE_CDHCLK +#define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_CDHCLK +#define RCC_OSPICLKSOURCE_PLL RCC_CDCCIPR_OCTOSPISEL_0 +#define RCC_OSPICLKSOURCE_PLL2 RCC_CDCCIPR_OCTOSPISEL_1 +#define RCC_OSPICLKSOURCE_CLKP RCC_CDCCIPR_OCTOSPISEL +#else +#define RCC_OSPICLKSOURCE_D1HCLK (0x00000000U) +#define RCC_OSPICLKSOURCE_HCLK RCC_OSPICLKSOURCE_D1HCLK +#define RCC_OSPICLKSOURCE_PLL RCC_D1CCIPR_OCTOSPISEL_0 +#define RCC_OSPICLKSOURCE_PLL2 RCC_D1CCIPR_OCTOSPISEL_1 +#define RCC_OSPICLKSOURCE_CLKP RCC_D1CCIPR_OCTOSPISEL +#endif /* RCC_CDCCIPR_OCTOSPISEL */ /** * @} */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + #if defined(DSI) /** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source * @{ @@ -985,16 +1405,26 @@ typedef struct /** * @} */ -#endif /*DSI*/ +#endif /* DSI */ /** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source * @{ */ +#if defined(RCC_D1CCIPR_FMCSEL) #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) +#define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_D1HCLK #define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0 #define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1 #define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL - +#else +#define RCC_FMCCLKSOURCE_CDHCLK (0x00000000U) +#define RCC_FMCCLKSOURCE_HCLK RCC_FMCCLKSOURCE_CDHCLK +/*alias*/ +#define RCC_FMCCLKSOURCE_D1HCLK RCC_FMCCLKSOURCE_CDHCLK +#define RCC_FMCCLKSOURCE_PLL RCC_CDCCIPR_FMCSEL_0 +#define RCC_FMCCLKSOURCE_PLL2 RCC_CDCCIPR_FMCSEL_1 +#define RCC_FMCCLKSOURCE_CLKP RCC_CDCCIPR_FMCSEL +#endif /* RCC_D1CCIPR_FMCSEL */ /** * @} */ @@ -1003,11 +1433,15 @@ typedef struct /** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source * @{ */ - +#if defined(RCC_D2CCIP1R_FDCANSEL) #define RCC_FDCANCLKSOURCE_HSE (0x00000000U) #define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0 #define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1 - +#else +#define RCC_FDCANCLKSOURCE_HSE (0x00000000U) +#define RCC_FDCANCLKSOURCE_PLL RCC_CDCCIP1R_FDCANSEL_0 +#define RCC_FDCANCLKSOURCE_PLL2 RCC_CDCCIP1R_FDCANSEL_1 +#endif /* D3_SRAM_BASE */ /** * @} */ @@ -1017,10 +1451,13 @@ typedef struct /** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source * @{ */ - +#if defined(RCC_D1CCIPR_SDMMCSEL) #define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) #define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL - +#else +#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U) +#define RCC_SDMMCCLKSOURCE_PLL2 RCC_CDCCIPR_SDMMCSEL +#endif /* RCC_D1CCIPR_SDMMCSEL */ /** * @} */ @@ -1029,24 +1466,31 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source * @{ */ +#if defined(RCC_D3CCIPR_ADCSEL_0) #define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) #define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0 #define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1 - +#else +#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U) +#define RCC_ADCCLKSOURCE_PLL3 RCC_SRDCCIPR_ADCSEL_0 +#define RCC_ADCCLKSOURCE_CLKP RCC_SRDCCIPR_ADCSEL_1 +#endif /* RCC_D3CCIPR_ADCSEL_0 */ /** * @} */ - - - - /** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source * @{ */ +#if defined(RCC_D2CCIP1R_SWPSEL) #define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U) #define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL - +#else +#define RCC_SWPMI1CLKSOURCE_CDPCLK1 (0x00000000U) +/* alias */ +#define RCC_SWPMI1CLKSOURCE_D2PCLK1 RCC_SWPMI1CLKSOURCE_CDPCLK1 +#define RCC_SWPMI1CLKSOURCE_HSI RCC_CDCCIP1R_SWPSEL +#endif /* RCC_D2CCIP1R_SWPSEL */ /** * @} */ @@ -1054,22 +1498,46 @@ typedef struct /** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source * @{ */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) #define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U) #define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL - - +#else +#define RCC_DFSDM1CLKSOURCE_CDPCLK1 (0x00000000U) +/* alias */ +#define RCC_DFSDM1CLKSOURCE_D2PCLK1 RCC_DFSDM1CLKSOURCE_CDPCLK1 +#define RCC_DFSDM1CLKSOURCE_SYS RCC_CDCCIP1R_DFSDM1SEL +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ /** * @} */ +#if defined(DFSDM2_BASE) +/** @defgroup RCCEx_DFSDM2_Clock_Source RCCEx DFSDM2 Clock Source + * @{ + */ +#define RCC_DFSDM2CLKSOURCE_SRDPCLK4 (0x00000000U) +/* alias */ +#define RCC_DFSDM2CLKSOURCE_SRDPCLK1 RCC_DFSDM2CLKSOURCE_SRDPCLK4 +#define RCC_DFSDM2CLKSOURCE_SYS RCC_SRDCCIPR_DFSDM2SEL +/** + * @} + */ +#endif /* DFSDM2 */ + /** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source * @{ */ +#if defined(RCC_D2CCIP1R_SPDIFSEL_0) #define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) #define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL - +#else +#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U) +#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_CDCCIP1R_SPDIFSEL_0 +#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_CDCCIP1R_SPDIFSEL_1 +#define RCC_SPDIFRXCLKSOURCE_HSI RCC_CDCCIP1R_SPDIFSEL +#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */ /** * @} */ @@ -1077,10 +1545,15 @@ typedef struct /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ */ +#if defined(RCC_D2CCIP2R_CECSEL_0) #define RCC_CECCLKSOURCE_LSE (0x00000000U) #define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0 #define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1 - +#else +#define RCC_CECCLKSOURCE_LSE (0x00000000U) +#define RCC_CECCLKSOURCE_LSI RCC_CDCCIP2R_CECSEL_0 +#define RCC_CECCLKSOURCE_CSI RCC_CDCCIP2R_CECSEL_1 +#endif /* RCC_D2CCIP2R_CECSEL_0 */ /** * @} */ @@ -1089,10 +1562,15 @@ typedef struct /** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source * @{ */ +#if defined(RCC_D1CCIPR_CKPERSEL_0) #define RCC_CLKPSOURCE_HSI (0x00000000U) #define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0 #define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1 - +#else +#define RCC_CLKPSOURCE_HSI (0x00000000U) +#define RCC_CLKPSOURCE_CSI RCC_CDCCIPR_CKPERSEL_0 +#define RCC_CLKPSOURCE_HSE RCC_CDCCIPR_CKPERSEL_1 +#endif /* RCC_D1CCIPR_CKPERSEL_0 */ /** * @} */ @@ -1144,6 +1622,14 @@ typedef struct #endif /*DUAL_CORE*/ +/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM18 /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */ +/** + * @} + */ + /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ @@ -1161,7 +1647,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ -#define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and abobe devices only */ +#define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */ #define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */ @@ -1287,9 +1773,14 @@ typedef struct * This is mainly used to save Power. * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted * This parameter can be one of the following values: - * @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ) - * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ) - * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ) + * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * * @retval None */ #define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) @@ -1315,29 +1806,35 @@ typedef struct * frequency ranges from 1 to 16 MHz. * * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock - * This parameter must be a number between 4 and 512. + * This parameter must be a number between 4 and 512 or between 8 and 420(*). * @note You have to set the PLL2N parameter correctly to ensure that the VCO * output frequency is between 150 and 420 MHz (when in medium VCO range) or - * between 192 and 836 MHZ (when in wide VCO range) + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) * * @param __PLL2P__ specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * This parameter must be a number between 1 and 128. * * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 + * This parameter must be a number between 1 and 128. * * @param __PLL2R__ specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 + * This parameter must be a number between 1 and 128. * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ - #define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ - do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ - WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ - ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ - } while(0) + do{ \ + MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ + WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ + ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ + } while(0) + /** * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor * @@ -1347,13 +1844,15 @@ typedef struct * It should be a value between 0 and 8191 * @note Warning: the software has to set correctly these bits to insure that the VCO * output frequency is between its valid frequency range, which is: - * 192 to 836 MHz if PLL2VCOSEL = 0 + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 * 150 to 420 MHz if PLL2VCOSEL = 1. * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ - #define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos) +#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) /** @brief Macro to select the PLL2 reference frequency range. * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range @@ -1371,8 +1870,11 @@ typedef struct /** @brief Macro to select the PLL2 reference frequency range. * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range * This parameter can be one of the following values: - * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz + * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * * @retval None */ #define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ @@ -1402,9 +1904,14 @@ typedef struct * This is mainly used to save Power. * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted * This parameter can be one of the following values: - * @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ) - * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ) - * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ) + * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * * @retval None */ #define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) @@ -1424,7 +1931,7 @@ typedef struct * This parameter must be a number between 4 and 512. * @note You have to set the PLL3N parameter correctly to ensure that the VCO * output frequency is between 150 and 420 MHz (when in medium VCO range) or - * between 192 and 836 MHZ (when in wide VCO range) + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) * * @param __PLL3P__ specifies the division factor for peripheral kernel clocks * This parameter must be a number between 2 and 128 (where odd numbers not allowed) @@ -1435,7 +1942,12 @@ typedef struct * @param __PLL3R__ specifies the division factor for peripheral kernel clocks * This parameter must be a number between 1 and 128 * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ #define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ @@ -1455,9 +1967,10 @@ typedef struct * It should be a value between 0 and 8191 * @note Warning: the software has to set correctly these bits to insure that the VCO * output frequency is between its valid frequency range, which is: - * 192 to 836 MHz if PLL3VCOSEL = 0 + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 * 150 to 420 MHz if PLL3VCOSEL = 1. * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. * * @retval None */ @@ -1479,8 +1992,11 @@ typedef struct /** @brief Macro to select the PLL3 reference frequency range. * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range * This parameter can be one of the following values: - * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz + * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * * @retval None */ #define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ @@ -1497,8 +2013,13 @@ typedef struct * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock * @retval None */ +#if defined(RCC_D2CCIP1R_SAI1SEL) #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#else +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SAI1SEL */ /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: @@ -1508,7 +2029,11 @@ typedef struct * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock */ +#if defined(RCC_D2CCIP1R_SAI1SEL) #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) +#else +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) +#endif /* RCC_D2CCIP1R_SAI1SEL */ /** * @brief Macro to Configure the SPDIFRX clock source. @@ -1521,14 +2046,25 @@ typedef struct * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI * @retval None */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) #define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#else +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + /** * @brief Macro to get the SPDIFRX clock source. * @retval None */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) +#else +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +#if defined(SAI3) /** * @brief Macro to Configure the SAI2/3 clock source. * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived @@ -1566,8 +2102,7 @@ typedef struct * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock * @retval None */ -#define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__)) +#define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG /** @brief Macro to get the SAI2 clock source. * @retval The clock source can be one of the following values: @@ -1577,7 +2112,7 @@ typedef struct * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock */ -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) +#define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE /** * @brief Macro to Configure the SAI3 clock source. @@ -1591,8 +2126,7 @@ typedef struct * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock * @retval None */ -#define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__)) +#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG /** @brief Macro to get the SAI3 clock source. * @retval The clock source can be one of the following values: @@ -1602,8 +2136,69 @@ typedef struct * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock */ -#define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) +#define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE +#endif /* SAI3 */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +/** + * @brief Macro to Configure the SAI2A clock source. + * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) + +/** @brief Macro to get the SAI2A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +/** + * @brief Macro to Configure the SAI2B clock source. + * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) + +/** @brief Macro to get the SAI2B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ + + +#if defined(SAI4_Block_A) /** * @brief Macro to Configure the SAI4A clock source. * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived @@ -1628,7 +2223,9 @@ typedef struct * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock */ #define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) +#endif /* SAI4_Block_A */ +#if defined(SAI4_Block_B) /** * @brief Macro to Configure the SAI4B clock source. * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived @@ -1653,27 +2250,50 @@ typedef struct * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock */ #define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) +#endif /* SAI4_Block_B */ -/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK). +/** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). * - * @param __I2C123CLKSource__ specifies the I2C1/2/3 clock source. + * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. * This parameter can be one of the following values: - * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock - * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock - * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock - * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. */ -#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__)) +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) +/* alias */ +#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* RCC_D2CCIP2R_I2C123SEL */ -/** @brief macro to get the I2C1/2/3 clock source. +/** @brief macro to get the I2C1/2/3/5* clock source. * @retval The clock source can be one of the following values: - * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock - * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock - * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock - * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. */ +#if defined(RCC_D2CCIP2R_I2C123SEL) #define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) +/* alias */ +#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ /** @brief macro to configure the I2C1 clock (I2C1CLK). * @@ -1684,17 +2304,24 @@ typedef struct * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__)) +#if defined(I2C5) +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ /** @brief macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: -* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#if defined(I2C5) +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ /** @brief macro to configure the I2C2 clock (I2C2CLK). * @@ -1705,8 +2332,11 @@ typedef struct * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock */ -#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__)) +#if defined(I2C5) +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ /** @brief macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: @@ -1715,7 +2345,11 @@ typedef struct * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#if defined(I2C5) +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ /** @brief macro to configure the I2C3 clock (I2C3CLK). * @@ -1726,8 +2360,11 @@ typedef struct * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock */ -#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__)) +#if defined(I2C5) +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ /** @brief macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: @@ -1736,7 +2373,11 @@ typedef struct * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#if defined(I2C5) +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ /** @brief macro to configure the I2C4 clock (I2C4CLK). * @@ -1747,8 +2388,13 @@ typedef struct * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock */ +#if defined(RCC_D3CCIPR_I2C4SEL) #define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#else +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#endif /* RCC_D3CCIPR_I2C4SEL */ /** @brief macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: @@ -1759,30 +2405,80 @@ typedef struct */ #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) -/** @brief macro to configure the USART1/6 clock (USART16CLK). +#if defined(I2C5) +/** @brief macro to configure the I2C5 clock (I2C5CLK). * - * @param __USART16CLKSource__ specifies the USART1/6 clock source. + * @param __I2C5CLKSource__ specifies the I2C5 clock source. * This parameter can be one of the following values: - * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock */ -#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__)) +#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* I2C5 */ -/** @brief macro to get the USART1/6 clock source. +#if defined(I2C5) +/** @brief macro to get the I2C5 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock - * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock */ +#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* I2C5 */ + +/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). + * + * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. + * This parameter can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to get the USART1/6/9* /10* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) #define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) +/* alias*/ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) +/* alias */ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ /** @brief macro to configure the USART234578 clock (USART234578CLK). * @@ -1795,8 +2491,13 @@ typedef struct * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock */ +#if defined(RCC_D2CCIP2R_USART28SEL) #define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) +#else +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) +#endif /* RCC_D2CCIP2R_USART28SEL */ /** @brief macro to get the USART2/3/4/5/7/8 clock source. * @retval The clock source can be one of the following values: @@ -1807,7 +2508,11 @@ typedef struct * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock */ +#if defined(RCC_D2CCIP2R_USART28SEL) #define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#else +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) +#endif /* RCC_D2CCIP2R_USART28SEL */ /** @brief macro to configure the USART1 clock (USART1CLK). * @@ -1820,8 +2525,7 @@ typedef struct * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock */ -#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__)) +#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG /** @brief macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @@ -1832,7 +2536,7 @@ typedef struct * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) +#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE /** @brief macro to configure the USART2 clock (USART2CLK). * @@ -1845,8 +2549,7 @@ typedef struct * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock */ -#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__)) +#define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG /** @brief macro to get the USART2 clock source. * @retval The clock source can be one of the following values: @@ -1857,7 +2560,7 @@ typedef struct * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE /** @brief macro to configure the USART3 clock (USART3CLK). * @@ -1870,8 +2573,7 @@ typedef struct * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock */ -#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__)) +#define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG /** @brief macro to get the USART3 clock source. * @retval The clock source can be one of the following values: @@ -1882,7 +2584,7 @@ typedef struct * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE /** @brief macro to configure the UART4 clock (UART4CLK). * @@ -1895,8 +2597,7 @@ typedef struct * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock */ -#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__)) +#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG /** @brief macro to get the UART4 clock source. * @retval The clock source can be one of the following values: @@ -1907,7 +2608,7 @@ typedef struct * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE /** @brief macro to configure the UART5 clock (UART5CLK). * @@ -1920,8 +2621,7 @@ typedef struct * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock */ -#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__)) +#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG /** @brief macro to get the UART5 clock source. * @retval The clock source can be one of the following values: @@ -1932,7 +2632,7 @@ typedef struct * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE /** @brief macro to configure the USART6 clock (USART6CLK). * @@ -1945,8 +2645,7 @@ typedef struct * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock */ -#define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__)) +#define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG /** @brief macro to get the USART6 clock source. * @retval The clock source can be one of the following values: @@ -1957,7 +2656,7 @@ typedef struct * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock */ -#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) +#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE /** @brief macro to configure the UART5 clock (UART7CLK). * @@ -1970,8 +2669,7 @@ typedef struct * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock */ -#define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__)) +#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG /** @brief macro to get the UART7 clock source. * @retval The clock source can be one of the following values: @@ -1982,7 +2680,7 @@ typedef struct * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock */ -#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE /** @brief macro to configure the UART8 clock (UART8CLK). * @@ -1995,8 +2693,7 @@ typedef struct * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock */ -#define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__)) +#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG /** @brief macro to get the UART8 clock source. * @retval The clock source can be one of the following values: @@ -2007,7 +2704,59 @@ typedef struct * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock */ -#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +#if defined(UART9) +/** @brief macro to configure the UART9 clock (UART9CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the UART9 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* UART9 */ + +#if defined(USART10) +/** @brief macro to configure the USART10 clock (USART10CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART10 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* USART10 */ /** @brief macro to configure the LPUART1 clock (LPUART1CLK). * @@ -2020,8 +2769,13 @@ typedef struct * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock */ +#if defined (RCC_D3CCIPR_LPUART1SEL) #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#else +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#endif /* RCC_D3CCIPR_LPUART1SEL */ /** @brief macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: @@ -2032,7 +2786,11 @@ typedef struct * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock */ +#if defined (RCC_D3CCIPR_LPUART1SEL) #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) +#else +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) +#endif /* RCC_D3CCIPR_LPUART1SEL */ /** @brief macro to configure the LPTIM1 clock source. * @@ -2045,9 +2803,13 @@ typedef struct * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) - +#else +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ /** @brief macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: @@ -2058,7 +2820,11 @@ typedef struct * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) +#else +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ /** @brief macro to configure the LPTIM2 clock source. * @@ -2071,9 +2837,13 @@ typedef struct * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) - +#else +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ /** @brief macro to get the LPTIM2 clock source. * @retval The clock source can be one of the following values: @@ -2084,7 +2854,11 @@ typedef struct * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) +#else +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ /** @brief macro to configure the LPTIM3/4/5 clock source. * @@ -2096,9 +2870,13 @@ typedef struct * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) #define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) - +#else +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ /** @brief macro to get the LPTIM3/4/5 clock source. * @retval The clock source can be one of the following values: @@ -2109,7 +2887,11 @@ typedef struct * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) #define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#else +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ /** @brief macro to configure the LPTIM3 clock source. * @@ -2121,9 +2903,7 @@ typedef struct * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock */ -#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \ - MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__)) - +#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG /** @brief macro to get the LPTIM3 clock source. * @retval The clock source can be one of the following values: @@ -2134,8 +2914,9 @@ typedef struct * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock */ -#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#if defined(LPTIM4) /** @brief macro to configure the LPTIM4 clock source. * * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. @@ -2146,8 +2927,7 @@ typedef struct * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock */ -#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \ - MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__)) +#define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG /** @brief macro to get the LPTIM4 clock source. @@ -2159,8 +2939,10 @@ typedef struct * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock */ -#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM4 */ +#if defined(LPTIM5) /** @brief macro to configure the LPTIM5 clock source. * * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. @@ -2171,8 +2953,7 @@ typedef struct * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock */ -#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \ - MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__)) +#define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG /** @brief macro to get the LPTIM5 clock source. @@ -2184,8 +2965,10 @@ typedef struct * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock */ -#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM5 */ +#if defined(QUADSPI) /** @brief macro to configure the QSPI clock source. * * @param __QSPICLKSource__ specifies the QSPI clock source. @@ -2206,6 +2989,39 @@ typedef struct * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock */ #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @brief macro to configure the OSPI clock source. + * + * @param __OSPICLKSource__ specifies the OSPI clock source. + * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#else +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ + +/** @brief macro to get the OSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) +#else +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + #if defined(DSI) /** @brief macro to configure the DSI clock source. @@ -2234,9 +3050,13 @@ typedef struct * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock */ +#if defined(RCC_D1CCIPR_FMCSEL) #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) - +#else +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#endif /* RCC_D1CCIPR_FMCSEL */ /** @brief macro to get the FMC clock source. * @retval The clock source can be one of the following values: @@ -2245,7 +3065,11 @@ typedef struct * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock */ +#if defined(RCC_D1CCIPR_FMCSEL) #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) +#else +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) +#endif /* RCC_D1CCIPR_FMCSEL */ /** @brief Macro to configure the USB clock (USBCLK). * @param __USBCLKSource__ specifies the USB clock source. @@ -2254,8 +3078,13 @@ typedef struct * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock */ +#if defined(RCC_D2CCIP2R_USBSEL) #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#else +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#endif /* RCC_D2CCIP2R_USBSEL */ /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: @@ -2263,8 +3092,11 @@ typedef struct * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock */ +#if defined(RCC_D2CCIP2R_USBSEL) #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) - +#else +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) +#endif /* RCC_D2CCIP2R_USBSEL */ /** @brief Macro to configure the ADC clock * @param __ADCCLKSource__ specifies the ADC digital interface clock source. @@ -2273,8 +3105,13 @@ typedef struct * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock */ +#if defined(RCC_D3CCIPR_ADCSEL) #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#else +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#endif /* RCC_D3CCIPR_ADCSEL */ /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: @@ -2282,7 +3119,11 @@ typedef struct * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock */ +#if defined(RCC_D3CCIPR_ADCSEL) #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) +#else +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) +#endif /* RCC_D3CCIPR_ADCSEL */ /** @brief Macro to configure the SWPMI1 clock * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. @@ -2290,15 +3131,24 @@ typedef struct * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock */ +#if defined(RCC_D2CCIP1R_SWPSEL) #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#else +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SWPSEL */ /** @brief Macro to get the SWPMI1 clock source. * @retval The clock source can be one of the following values: * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock */ +#if defined(RCC_D2CCIP1R_SWPSEL) #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) +#else +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) +#endif /* RCC_D2CCIP1R_SWPSEL */ /** @brief Macro to configure the DFSDM1 clock * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. @@ -2306,15 +3156,42 @@ typedef struct * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#else +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ /** @brief Macro to get the DFSDM1 clock source. * @retval The clock source can be one of the following values: * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock */ +#if defined (RCC_D2CCIP1R_DFSDM1SEL) #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) +#else +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +#if defined(DFSDM2_BASE) + /** @brief Macro to configure the DFSDM2 clock + * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) +#endif /* DFSDM2 */ /** @brief macro to configure the CEC clock (CECCLK). * @@ -2324,8 +3201,13 @@ typedef struct * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock */ +#if defined(RCC_D2CCIP2R_CECSEL) #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#else +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#endif /* RCC_D2CCIP2R_CECSEL */ /** @brief macro to get the CEC clock source. * @retval The clock source can be one of the following values: @@ -2333,8 +3215,11 @@ typedef struct * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock */ +#if defined(RCC_D2CCIP2R_CECSEL) #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) - +#else +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) +#endif /* RCC_D2CCIP2R_CECSEL */ /** @brief Macro to configure the CLKP : Oscillator clock for peripheral * @param __CLKPSource__ specifies Oscillator clock for peripheral @@ -2343,8 +3228,13 @@ typedef struct * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral */ +#if defined(RCC_D1CCIPR_CKPERSEL) #define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#else +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#endif /* RCC_D1CCIPR_CKPERSEL */ /** @brief Macro to get the Oscillator clock for peripheral source. * @retval The clock source can be one of the following values: @@ -2352,7 +3242,11 @@ typedef struct * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral */ +#if defined(RCC_D1CCIPR_CKPERSEL) #define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) +#else +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) +#endif /* RCC_D1CCIPR_CKPERSEL */ #if defined(FDCAN1) || defined(FDCAN2) /** @brief Macro to configure the FDCAN clock @@ -2362,8 +3256,13 @@ typedef struct * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock */ +#if defined(RCC_D2CCIP1R_FDCANSEL) #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#else +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#endif /* RCC_D2CCIP1R_FDCANSEL */ /** @brief Macro to get the FDCAN clock * @retval The clock source can be one of the following values: @@ -2371,8 +3270,14 @@ typedef struct * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock */ +#if defined(RCC_D2CCIP1R_FDCANSEL) #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) +#else +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + #endif /*FDCAN1 || FDCAN2*/ + /** * @brief Macro to Configure the SPI1/2/3 clock source. * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived @@ -2385,8 +3290,13 @@ typedef struct * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock * @retval None */ +#if defined(RCC_D2CCIP1R_SPI123SEL) #define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#else +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI123SEL */ /** @brief Macro to get the SPI1/2/3 clock source. * @retval The clock source can be one of the following values: @@ -2396,7 +3306,11 @@ typedef struct * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock */ +#if defined(RCC_D2CCIP1R_SPI123SEL) #define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#else +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) +#endif /* RCC_D2CCIP1R_SPI123SEL */ /** * @brief Macro to Configure the SPI1 clock source. @@ -2410,8 +3324,7 @@ typedef struct * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock * @retval None */ -#define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__)) +#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG /** @brief Macro to get the SPI1 clock source. * @retval The clock source can be one of the following values: @@ -2421,7 +3334,7 @@ typedef struct * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock */ -#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE /** * @brief Macro to Configure the SPI2 clock source. @@ -2435,8 +3348,7 @@ typedef struct * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock * @retval None */ -#define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__)) +#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG /** @brief Macro to get the SPI2 clock source. * @retval The clock source can be one of the following values: @@ -2446,7 +3358,7 @@ typedef struct * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock */ -#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE /** * @brief Macro to Configure the SPI3 clock source. @@ -2460,8 +3372,7 @@ typedef struct * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock * @retval None */ -#define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__)) +#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG /** @brief Macro to get the SPI3 clock source. * @retval The clock source can be one of the following values: @@ -2471,7 +3382,7 @@ typedef struct * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock */ -#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE /** * @brief Macro to Configure the SPI4/5 clock source. @@ -2486,8 +3397,13 @@ typedef struct * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE * @retval None */ +#if defined(RCC_D2CCIP1R_SPI45SEL) #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#else +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI45SEL */ /** @brief Macro to get the SPI4/5 clock source. * @retval The clock source can be one of the following values: @@ -2498,7 +3414,11 @@ typedef struct * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE */ +#if defined(RCC_D2CCIP1R_SPI45SEL) #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) +#else +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) +#endif /* RCC_D2CCIP1R_SPI45SEL */ /** * @brief Macro to Configure the SPI4 clock source. @@ -2513,8 +3433,7 @@ typedef struct * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE * @retval None */ -#define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__)) +#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG /** @brief Macro to get the SPI4 clock source. * @retval The clock source can be one of the following values: @@ -2525,7 +3444,7 @@ typedef struct * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE */ -#define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) +#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE /** * @brief Macro to Configure the SPI5 clock source. @@ -2540,8 +3459,7 @@ typedef struct * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE * @retval None */ -#define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\ - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__)) +#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG /** @brief Macro to get the SPI5 clock source. * @retval The clock source can be one of the following values: @@ -2552,7 +3470,7 @@ typedef struct * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE */ -#define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) +#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE /** * @brief Macro to Configure the SPI6 clock source. @@ -2565,10 +3483,20 @@ typedef struct * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) + * * @retval None + * + * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. + * */ +#if defined(RCC_D3CCIPR_SPI6SEL) #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#else +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#endif /* RCC_D3CCIPR_SPI6SEL */ /** @brief Macro to get the SPI6 clock source. * @retval The clock source can be one of the following values: @@ -2578,8 +3506,13 @@ typedef struct * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN */ +#if defined(RCC_D3CCIPR_SPI6SEL) #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) +#else +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) +#endif /* RCC_D3CCIPR_SPI6SEL */ /** @brief Macro to configure the SDMMC clock * @param __SDMMCCLKSource__ specifies clock source for SDMMC @@ -2587,12 +3520,21 @@ typedef struct * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock */ +#if defined(RCC_D1CCIPR_SDMMCSEL) #define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#else +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#endif /* RCC_D1CCIPR_SDMMCSEL */ /** @brief Macro to get the SDMMC clock */ +#if defined(RCC_D1CCIPR_SDMMCSEL) #define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) +#else +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) +#endif /* RCC_D1CCIPR_SDMMCSEL */ /** @brief macro to configure the RNG clock (RNGCLK). * @@ -2603,8 +3545,13 @@ typedef struct * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock */ +#if defined(RCC_D2CCIP2R_RNGSEL) #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#else +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#endif /* RCC_D2CCIP2R_RNGSEL */ /** @brief macro to get the RNG clock source. * @retval The clock source can be one of the following values: @@ -2613,12 +3560,13 @@ typedef struct * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock */ +#if defined(RCC_D2CCIP2R_RNGSEL) #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) +#else +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) +#endif /* RCC_D2CCIP2R_RNGSEL */ - -/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config - * @{ - */ +#if defined(HRTIM1) /** @brief Macro to configure the HRTIM1 prescaler clock source. * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. * This parameter can be one of the following values: @@ -2634,6 +3582,7 @@ typedef struct * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock */ #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) +#endif /* HRTIM1 */ /** @brief Macro to configure the Timers clocks prescalers * @param __PRESC__ specifies the Timers clocks prescalers selection @@ -2650,8 +3599,132 @@ typedef struct }while(0) /** - * @} + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + /** * @brief Enable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. @@ -2809,6 +3882,10 @@ typedef struct /* Exported functions --------------------------------------------------------*/ + /** @addtogroup RCCEx_Exported_Functions + * @{ + */ + /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ @@ -2832,10 +3909,15 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); #if defined(DUAL_CORE) void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); #endif /*DUAL_CORE*/ +#if defined(RCC_GCR_WW1RSC) void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); +#endif /*RCC_GCR_WW1RSC*/ /** * @} */ @@ -2855,6 +3937,10 @@ void HAL_RCCEx_CRS_SyncWarnCallback(void); void HAL_RCCEx_CRS_ExpectedSyncCallback(void); void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); +/** + * @} + */ + /** * @} */ @@ -2875,19 +3961,41 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((VALUE) == RCC_PLL3_DIVQ) || \ ((VALUE) == RCC_PLL3_DIVR)) +#if defined(RCC_D2CCIP2R_USART16SEL) #define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +#else +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +/* alias*/ +#define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined(RCC_D2CCIP2R_USART28SEL) #define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#else +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#endif /* RCC_D2CCIP2R_USART28SEL */ #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ @@ -2910,18 +4018,18 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) -#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ +#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) -#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ +#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) #define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ @@ -2931,31 +4039,58 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) -#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)|| \ - ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ +#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) -#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)|| \ - ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ +#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) -#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) +#if defined(UART9) +#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) +#endif +#if defined(USART10) +#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) +#endif + +#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) + +#if defined(I2C5) +#define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) + +#define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ +#else #define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) +#endif /*I2C5*/ #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ @@ -2977,13 +4112,22 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) +#endif /*I2C5*/ + #define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) +#if defined(HRTIM1) #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) +#endif #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ @@ -2996,6 +4140,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) +#if defined(SAI3) #define IS_RCC_SAI23CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ @@ -3010,12 +4155,34 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) + #define IS_RCC_SAI3CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define IS_RCC_SAI2ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define IS_RCC_SAI2BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) +#endif #define IS_RCC_SPI123CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ @@ -3069,6 +4236,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) +#if defined(RCC_D3CCIPR_SPI6SEL) #define IS_RCC_SPI6CLK(__SOURCE__) \ (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ @@ -3076,7 +4244,18 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) +#else +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) +#endif /* RCC_D3CCIPR_SPI6SEL */ +#if defined(SAI4) #define IS_RCC_SAI4ACLK(__SOURCE__) \ (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ @@ -3090,6 +4269,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) +#endif /*SAI4*/ #define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) #define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) @@ -3142,32 +4322,46 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) -#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)|| \ - ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ - ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ - ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ +#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) +#if defined(LPTIM4) #define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) +#endif /* LPTIM4*/ +#if defined(LPTIM5) #define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) +#endif /*LPTIM5*/ +#if defined(QUADSPI) #define IS_RCC_QSPICLK(__SOURCE__) \ (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI1) +#define IS_RCC_OSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) +#endif /*OCTOSPI1 || OCTOSPI1*/ #if defined(DSI) #define IS_RCC_DSICLK(__SOURCE__) \ @@ -3200,7 +4394,12 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ - ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) + +#if defined(DFSDM2_BASE) +#define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ + ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) +#endif /*DFSDM2*/ #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ @@ -3259,6 +4458,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); /** * @} */ + /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h index 0593603..bcf32cf 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h @@ -167,7 +167,7 @@ typedef struct This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -179,7 +179,7 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -304,6 +304,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -327,13 +347,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -460,7 +483,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_DMABASE_AF1 0x00000018U #define TIM_DMABASE_AF2 0x00000019U #endif /* TIM_BREAK_INPUT_SUPPORT */ -#define TIM_DMABASE_TISEL 0x00000020U +#define TIM_DMABASE_TISEL 0x0000001AU /** * @} */ @@ -523,6 +546,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -616,6 +648,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ @@ -980,6 +1021,11 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ +#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ +#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */ +#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} @@ -1093,25 +1139,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1313,6 +1383,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. @@ -1332,6 +1427,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1673,6 +1770,9 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) @@ -1695,6 +1795,9 @@ mode. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) @@ -1862,7 +1965,9 @@ mode. ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8)) + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ @@ -1873,6 +1978,8 @@ mode. ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ ((__SELECTION__) == TIM_TS_NONE)) #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ @@ -1891,15 +1998,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -1948,6 +2055,50 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + /** * @} */ @@ -2173,6 +2324,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -2192,7 +2348,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h index 38b3662..f3a7f01 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h @@ -93,9 +93,9 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */ #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */ -#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */ #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */ #define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */ @@ -123,6 +123,18 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */ #define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */ #define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */ +#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */ +#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */ + +#define TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */ +#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */ +#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */ + +#define TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */ +#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */ +#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */ +#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */ +#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */ /** * @} */ @@ -184,26 +196,22 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */ #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */ -#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */ +#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */ #define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */ #define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */ #define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */ -#if defined(TIM12_TI1_GPIO_SUPPORT) #define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */ -#endif /* TIM12_TI1_GPIO_SUPPORT */ -#if defined(TIM12_TI1_SPDIF_FS_SUPPORT) #define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */ -#endif /* TIM12_TI1_SPDIF_FS_SUPPORT */ #define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ #define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */ #define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */ #define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */ -#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_3) /* !< TIM15_TI1 is connected to RCC LSE */ -#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */ -#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */ +#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */ +#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */ +#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */ #define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */ #define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */ @@ -216,11 +224,19 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */ #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ -#if defined(TIM17_TI1_SPDIF_FS_SUPPORT) #define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */ -#endif /* TIM17_TI1_SPDIF_FS_SUPPORT */ #define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */ #define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */ + +#define TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */ +#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */ +#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */ +#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */ +#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */ +#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */ +#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */ /** * @} */ @@ -273,6 +289,8 @@ TIMEx_BreakInputConfigTypeDef; ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\ ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\ ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\ ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\ ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\ ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\ @@ -291,12 +309,20 @@ TIMEx_BreakInputConfigTypeDef; ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\ ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\ ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\ - ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)) + ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC)) #define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\ - ((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD1) ||\ - ((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD2) ||\ - ((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\ @@ -321,8 +347,15 @@ TIMEx_BreakInputConfigTypeDef; ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\ ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\ ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\ - ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)) - + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB)) /** * @} @@ -458,6 +491,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h index 48eb8db..7516a3f 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h @@ -1170,13 +1170,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. @@ -1185,7 +1186,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\ + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. @@ -1194,7 +1195,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\ + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check whether or not UART instance is Low Power UART. @@ -1514,6 +1515,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #include "stm32h7xx_hal_uart_ex.h" +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */ +extern const uint16_t UARTPrescTable[12]; + + /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h index 04fa406..86b81da 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h @@ -155,7 +155,7 @@ typedef struct typedef struct { - uint8_t dev_addr ; /*!< USB device address. + uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ uint8_t ch_num; /*!< Host channel number. @@ -199,10 +199,10 @@ typedef struct uint32_t ErrCnt; /*!< Host channel error count.*/ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ } USB_OTG_HCTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -237,11 +237,11 @@ typedef struct /** @defgroup USB_LL Device Speed * @{ */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FS_SPEED 1U +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U /** * @} */ @@ -269,11 +269,11 @@ typedef struct * @{ */ #ifndef USBD_HS_TRDT_VALUE -#define USBD_HS_TRDT_VALUE 9U +#define USBD_HS_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ #ifndef USBD_FS_TRDT_VALUE -#define USBD_FS_TRDT_VALUE 5U -#define USBD_DEFAULT_TRDT_VALUE 9U +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ /** * @} @@ -282,9 +282,9 @@ typedef struct /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ @@ -294,7 +294,6 @@ typedef struct */ #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) /** * @} @@ -403,7 +402,7 @@ typedef struct #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#define EP_ADDR_MSK 0xFU +#define EP_ADDR_MSK 0xFU /** * @} */ @@ -468,13 +467,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c index e41d5ec..159c3d9 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -47,10 +47,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32H7xx HAL Driver version number V1.6.0 + * @brief STM32H7xx HAL Driver version number V1.9.0 */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ -#define __STM32H7xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x09UL) /*!< [23:16] sub1 version */ #define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ @@ -134,6 +134,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ HAL_StatusTypeDef HAL_Init(void) { +uint32_t common_system_clock; + #if defined(DUAL_CORE) && defined(CORE_CM4) /* Configure Cortex-M4 Instruction cache through ART accelerator */ __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ @@ -145,10 +147,24 @@ HAL_StatusTypeDef HAL_Init(void) HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif /* Update the SystemD2Clock global variable */ - SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) @@ -251,32 +267,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) return HAL_ERROR; } -#if defined(DUAL_CORE) - if (HAL_GetCurrentCPUID() == CM7_CPUID) - { - /* Cortex-M7 detected */ /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) { return HAL_ERROR; } - } - else - { - /* Cortex-M4 detected */ - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U) - { - return HAL_ERROR; - } - } -#else - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) - { - return HAL_ERROR; - } -#endif /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) @@ -361,14 +356,26 @@ uint32_t HAL_GetTickPrio(void) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } } return status; @@ -581,6 +588,7 @@ void HAL_SYSCFG_DisableVREFBUF(void) CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); } +#if defined(SYSCFG_PMCR_EPIS_SEL) /** * @brief Ethernet PHY Interface Selection either MII or RMII * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface @@ -596,7 +604,7 @@ void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); } - +#endif /* SYSCFG_PMCR_EPIS_SEL */ /** * @brief Analog Switch control for dual analog pads. @@ -628,7 +636,7 @@ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCF MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); } - +#if defined(SYSCFG_PMCR_BOOSTEN) /** * @brief Enables the booster to reduce the total harmonic distortion of the analog * switch when the supply voltage is lower than 2.7 V. @@ -653,8 +661,9 @@ void HAL_SYSCFG_DisableBOOST(void) { CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; } +#endif /* SYSCFG_PMCR_BOOSTEN */ - +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) /** * @brief BootCM7 address 0 configuration * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) @@ -687,8 +696,8 @@ void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16)); #endif /*DUAL_CORE*/ } - } +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */ #if defined(DUAL_CORE) /** @@ -757,7 +766,6 @@ void HAL_SYSCFG_DisableCM4BOOT(void) CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); } #endif /*DUAL_CORE*/ - /** * @brief Enables the I/O Compensation Cell. * @note The I/O compensation cell can be used only when the device supply @@ -790,7 +798,11 @@ void HAL_DisableCompensationCell(void) */ void HAL_SYSCFG_EnableIOSpeedOptimize(void) { +#if defined(SYSCFG_CCCSR_HSLV) SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ } /** @@ -802,7 +814,11 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void) */ void HAL_SYSCFG_DisableIOSpeedOptimize(void) { +#if defined(SYSCFG_CCCSR_HSLV) CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ } /** @@ -838,9 +854,64 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); } +#if defined(SYSCFG_CCCR_NCC_MMC) +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} +#endif /* SYSCFG_CCCR_NCC_MMC */ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout0 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16] + * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16] + */ +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0); +} +/** + * @} + */ +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout1 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17] + * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17] + */ +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1); +} +/** + * @} + */ +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ /** - * @brief Enable the Debug Module during Domain1 SLEEP mode + * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode * @retval None */ void HAL_EnableDBGSleepMode(void) @@ -849,7 +920,7 @@ void HAL_EnableDBGSleepMode(void) } /** - * @brief Disable the Debug Module during Domain1 SLEEP mode + * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode * @retval None */ void HAL_DisableDBGSleepMode(void) @@ -857,8 +928,9 @@ void HAL_DisableDBGSleepMode(void) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); } + /** - * @brief Enable the Debug Module during Domain1 STOP mode + * @brief Enable the Debug Module during Domain1/CDomain STOP mode * @retval None */ void HAL_EnableDBGStopMode(void) @@ -867,7 +939,7 @@ void HAL_EnableDBGStopMode(void) } /** - * @brief Disable the Debug Module during Domain1 STOP mode + * @brief Disable the Debug Module during Domain1/CDomain STOP mode * @retval None */ void HAL_DisableDBGStopMode(void) @@ -876,7 +948,7 @@ void HAL_DisableDBGStopMode(void) } /** - * @brief Enable the Debug Module during Domain1 STANDBY mode + * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode * @retval None */ void HAL_EnableDBGStandbyMode(void) @@ -885,7 +957,7 @@ void HAL_EnableDBGStandbyMode(void) } /** - * @brief Disable the Debug Module during Domain1 STANDBY mode + * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode * @retval None */ void HAL_DisableDBGStandbyMode(void) @@ -949,18 +1021,16 @@ void HAL_DisableDomain2DBGStandbyMode(void) } #endif /*DUAL_CORE*/ - /** - * @brief Enable the Debug Module during Domain3 STOP mode + * @brief Enable the Debug Module during Domain3/SRDomain STOP mode * @retval None */ void HAL_EnableDomain3DBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); } - /** - * @brief Disable the Debug Module during Domain3 STOP mode + * @brief Disable the Debug Module during Domain3/SRDomain STOP mode * @retval None */ void HAL_DisableDomain3DBGStopMode(void) @@ -969,7 +1039,7 @@ void HAL_DisableDomain3DBGStopMode(void) } /** - * @brief Enable the Debug Module during Domain3 STANDBY mode + * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode * @retval None */ void HAL_EnableDomain3DBGStandbyMode(void) @@ -978,7 +1048,7 @@ void HAL_EnableDomain3DBGStandbyMode(void) } /** - * @brief Disable the Debug Module during Domain3 STANDBY mode + * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode * @retval None */ void HAL_DisableDomain3DBGStandbyMode(void) @@ -1066,7 +1136,7 @@ void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_D1_LINE(EXTI_Line)); - SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); } @@ -1081,7 +1151,7 @@ void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_D2_LINE(EXTI_Line)); - SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); } #endif /*DUAL_CORE*/ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c index 1f38c07..e3befad 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -146,6 +146,19 @@ typedef struct #define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) +#if defined(UART9) +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX ))) +#else +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) + +#endif /** * @} */ @@ -278,6 +291,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; } + /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + lock when transfering data to/from USART/UART */ +#if (STM32H7_DEV_ID == 0x450UL) + if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + { +#endif /* STM32H7_DEV_ID == 0x450UL */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } +#if (STM32H7_DEV_ID == 0x450UL) + } +#endif /* STM32H7_DEV_ID == 0x450UL */ + /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; @@ -325,8 +352,11 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ { - /* Check the request parameter */ - assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* Check the request parameter */ + assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + } /* Allocate lock resource */ __HAL_UNLOCK(hdma); @@ -344,12 +374,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ - registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | \ - DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | \ - DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | \ - DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | \ - DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | \ - DMA_TO_BDMA_MODE(hdma->Init.Mode) | \ + registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | + DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + DMA_TO_BDMA_MODE(hdma->Init.Mode) | DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); /* Write to DMA Channel CR register */ @@ -373,43 +403,46 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) return HAL_ERROR; } - /* Initialize parameters for DMAMUX channel : - DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask - */ - DMA_CalcDMAMUXChannelBaseAndMask(hdma); - - if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* if memory to memory force the request to 0*/ - hdma->Init.Request = DMA_REQUEST_MEM2MEM; - } + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); - /* Set peripheral request to DMAMUX channel */ - hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - /* Initialize parameters for DMAMUX request generator : - if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 - */ - if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) - { /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ - DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 + */ + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - /* Reset the DMAMUX request generator register */ - hdma->DMAmuxRequestGen->RGCR = 0U; + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - else - { - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; - hdma->DMAmuxRequestGenStatusMask = 0U; + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } } /* Initialize the error code */ @@ -496,35 +529,41 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) return HAL_ERROR; } - /* Initialize parameters for DMAMUX channel : - DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ - DMA_CalcDMAMUXChannelBaseAndMask(hdma); - - if(hdma->DMAmuxChannel != 0U) +#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */ + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ +#endif /* BDMA1 */ { - /* Resett he DMAMUX channel that corresponds to the DMA stream */ - hdma->DMAmuxChannel->CCR = 0U; + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + if(hdma->DMAmuxChannel != 0U) + { + /* Resett he DMAMUX channel that corresponds to the DMA stream */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + } + + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; } - if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) - { - /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ - DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - - /* Reset the DMAMUX request generator register */ - hdma->DMAmuxRequestGen->RGCR = 0U; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; - hdma->DMAmuxRequestGenStatusMask = 0U; /* Clean callbacks */ hdma->XferCpltCallback = NULL; @@ -687,18 +726,21 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, } } - /* Check if DMAMUX Synchronization is enabled */ - if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* Enable DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; - } + /* Check if DMAMUX Synchronization is enabled */ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ - /* enable the request gen overrun IT */ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } } /* Enable the Peripheral */ @@ -775,8 +817,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); } - /* disable the DMAMUX sync overrun IT */ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); @@ -812,17 +857,20 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); } - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ - /* disable the request gen overrun IT */ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } } /* Process Unlocked */ @@ -874,24 +922,27 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - /* disable the DMAMUX sync overrun IT */ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - - /* Clear all flags */ - regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; - regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ - /* disable the request gen overrun IT */ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + /* Clear all flags */ + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } } /* Process Unlocked */ @@ -1069,42 +1120,46 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* if timeout then abort the current transfer */ /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */ (void) HAL_DMA_Abort(hdma); - /* - Note that the Abort function will - - Clear the transfer error flags - - Unlock - - Set the State - */ + /* + Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ return HAL_ERROR; } } - /* Check for DMAMUX Request generator (if used) overrun status */ - if(hdma->DMAmuxRequestGen != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ - if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + /* Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) { - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; } } - - /* Check for DMAMUX Synchronization overrun */ - if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) - { - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; - } } + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { @@ -1715,13 +1770,16 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c index 982dfc7..6a48d94 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c @@ -175,16 +175,19 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); } - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } } /* Enable the peripheral */ @@ -271,13 +274,16 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ /* Configure the source, destination address and the data length */ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ @@ -304,18 +310,21 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ } } - /* Check if DMAMUX Synchronization is enabled*/ - if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ { - /* Enable DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; - } + /* Check if DMAMUX Synchronization is enabled*/ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ - /* enable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } } /* Enable the peripheral */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c index 449c527..be7c832 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c @@ -134,11 +134,11 @@ FLASH_ProcessTypeDef pFlash; */ /** - * @brief Program flash word of 256 bits at a specified address + * @brief Program flash word at a specified address * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param FlashAddress specifies the address to be programmed. - * @param DataAddress specifies the address of data (256 bits) to be programmed + * @param DataAddress specifies the address of data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -157,14 +157,24 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, /* Process Locked */ __HAL_LOCK(&pFlash); +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ { bank = FLASH_BANK_1; } - else +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) { bank = FLASH_BANK_2; } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; @@ -174,28 +184,63 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, if(status == HAL_OK) { +#if defined (DUAL_BANK) if(bank == FLASH_BANK_1) { - /* Set PG bit */ - SET_BIT(FLASH->CR1, FLASH_CR_PG); +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } } else { /* Set PG bit */ SET_BIT(FLASH->CR2, FLASH_CR_PG); } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ __ISB(); __DSB(); - /* Program the 256 bits flash word */ - do +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) { - *dest_addr = *src_addr; - dest_addr++; - src_addr++; - row_index--; - } while (row_index != 0U); + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } __ISB(); __DSB(); @@ -203,16 +248,41 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); - if(bank == FLASH_BANK_1) +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + if(bank == FLASH_BANK_1) + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } + else + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); + } + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ { /* If the program operation is completed, disable the PG */ CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); } - else - { - /* If the program operation is completed, disable the PG */ - CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); - } +#endif /* DUAL_BANK */ } /* Process Unlocked */ @@ -248,14 +318,24 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ { bank = FLASH_BANK_1; } - else +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) { bank = FLASH_BANK_2; } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); @@ -269,17 +349,33 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre { pFlash.Address = FlashAddress; +#if defined (DUAL_BANK) if(bank == FLASH_BANK_1) { /* Set internal variables used by the IRQ handler */ pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; - /* Set PG bit */ - SET_BIT(FLASH->CR1, FLASH_CR_PG); +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ } else { @@ -290,21 +386,62 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre SET_BIT(FLASH->CR2, FLASH_CR_PG); /* Enable End of Operation and Error interrupts for Bank2 */ +#if defined (FLASH_CR_OPERRIE) __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ } +#else /* Single Bank */ + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ +#endif /* DUAL_BANK */ __ISB(); __DSB(); - /* Program the 256 bits flash word */ - do +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) { - *dest_addr = *src_addr; - dest_addr++; - src_addr++; - row_index--; - } while (row_index != 0U); + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } __ISB(); __DSB(); @@ -391,6 +528,7 @@ void HAL_FLASH_IRQHandler(void) } } +#if defined (DUAL_BANK) /* Check FLASH Bank2 End of Operation flag */ if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET) { @@ -458,10 +596,16 @@ void HAL_FLASH_IRQHandler(void) } } } +#endif /* DUAL_BANK */ /* Check FLASH Bank1 operation error flags */ +#if defined (FLASH_SR_OPERR) errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); +#else + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1); +#endif /* FLASH_SR_OPERR */ if(errorflag != 0U) { @@ -497,11 +641,16 @@ void HAL_FLASH_IRQHandler(void) HAL_FLASH_OperationErrorCallback(temp); } +#if defined (DUAL_BANK) /* Check FLASH Bank2 operation error flags */ +#if defined (FLASH_SR_OPERR) errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU); +#else + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU); +#endif /* FLASH_SR_OPERR */ - /* Check FLASH Bank2 operation error flags */ if(errorflag != 0U) { /* Save the error code */ @@ -535,16 +684,31 @@ void HAL_FLASH_IRQHandler(void) /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(temp); } +#endif /* DUAL_BANK */ if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { +#if defined (FLASH_CR_OPERRIE) /* Disable Bank1 Operation and Error source interrupt */ __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#if defined (DUAL_BANK) /* Disable Bank2 Operation and Error source interrupt */ __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#endif /* DUAL_BANK */ +#else + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* DUAL_BANK */ +#endif /* FLASH_CR_OPERRIE */ /* Process Unlocked */ __HAL_UNLOCK(&pFlash); @@ -626,6 +790,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) } } +#if defined (DUAL_BANK) if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) { /* Authorize the FLASH Bank2 Registers access */ @@ -638,6 +803,7 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) return HAL_ERROR; } } +#endif /* DUAL_BANK */ return HAL_OK; } @@ -657,6 +823,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) return HAL_ERROR; } +#if defined (DUAL_BANK) /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */ SET_BIT(FLASH->CR2, FLASH_CR_LOCK); @@ -665,6 +832,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) { return HAL_ERROR; } +#endif /* DUAL_BANK */ return HAL_OK; } @@ -722,10 +890,12 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { status = HAL_ERROR; } +#if defined (DUAL_BANK) else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) { status = HAL_ERROR; } +#endif /* DUAL_BANK */ else { status = HAL_OK; @@ -820,20 +990,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) Even if the FLASH operation fails, the QW flag will be reset and an error flag will be set */ - uint32_t bsyflag, errorflag; + uint32_t bsyflag = FLASH_FLAG_QW_BANK1; + uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; uint32_t tickstart = HAL_GetTick(); assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); - /* Select bsyflag depending on Bank */ - if(Bank == FLASH_BANK_1) - { - bsyflag = FLASH_FLAG_QW_BANK1; - } - else +#if defined (DUAL_BANK) + + if (Bank == FLASH_BANK_2) { + /* Get Error Flags */ + errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; + /* Select bsyflag depending on Bank */ bsyflag = FLASH_FLAG_QW_BANK2; } +#endif /* DUAL_BANK */ while(__HAL_FLASH_GET_FLAG(bsyflag)) { @@ -846,16 +1018,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) } } - /* Get Error Flags */ - if (Bank == FLASH_BANK_1) - { - errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; - } - else - { - errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; - } - /* In case of error reported in Flash SR1 or SR2 register */ if((errorflag & 0x7FFFFFFFU) != 0U) { @@ -877,6 +1039,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); } } +#if defined (DUAL_BANK) else { if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2)) @@ -885,6 +1048,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); } } +#endif /* DUAL_BANK */ return HAL_OK; } @@ -976,6 +1140,7 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank return HAL_ERROR; } } +#if defined (DUAL_BANK) else { if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2)) @@ -989,6 +1154,7 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank return HAL_ERROR; } } +#endif /* DUAL_BANK */ /* If there is no error flag set */ return HAL_OK; diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c index 2798cee..b2f8aae 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -45,6 +45,8 @@ (++) PCROP protection configuration and control per bank (++) Secure area configuration and control per bank (++) Core Boot address configuration + (++) TCM / AXI shared RAM configuration + (++) CPU Frequency Boost configuration (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(), HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions @@ -120,10 +122,25 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank); static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank); -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); #endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); +static uint32_t FLASH_OB_OTP_GetLock(void); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig); +static uint32_t FLASH_OB_SharedRAM_GetConfig(void); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost); +static uint32_t FLASH_OB_CPUFreq_GetBoost(void); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ /** * @} */ @@ -182,6 +199,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } } +#if defined (DUAL_BANK) /* Wait for last operation to be completed on Bank2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { @@ -190,6 +208,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t status = HAL_ERROR; } } +#endif /* DUAL_BANK */ if(status == HAL_OK) { @@ -198,7 +217,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Mass erase to be done */ FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed on Bank 1 */ if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) @@ -208,6 +227,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* if the erase operation is completed, disable the Bank1 BER Bit */ FLASH->CR1 &= (~FLASH_CR_BER); } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) @@ -217,6 +238,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* if the erase operation is completed, disable the Bank2 BER Bit */ FLASH->CR2 &= (~FLASH_CR_BER); } +#endif /* DUAL_BANK */ } else { @@ -236,6 +258,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* If the erase operation is completed, disable the SER Bit */ FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); } +#if defined (DUAL_BANK) if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Wait for last operation to be completed */ @@ -244,6 +267,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* If the erase operation is completed, disable the SER Bit */ FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); } +#endif /* DUAL_BANK */ if(status != HAL_OK) { @@ -282,7 +306,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed on Bank 1 */ if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) @@ -291,6 +315,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) } } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) @@ -298,6 +324,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) status = HAL_ERROR; } } +#endif /* DUAL_BANK */ if (status != HAL_OK) { @@ -309,15 +336,27 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) { /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ } +#if defined (DUAL_BANK) if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Enable End of Operation and Error interrupts for Bank 2 */ +#if defined (FLASH_CR_OPERRIE) __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ } +#endif /* DUAL_BANK */ if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { @@ -326,10 +365,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1; } +#if defined (DUAL_BANK) else if(pEraseInit->Banks == FLASH_BANK_2) { pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2; } +#endif /* DUAL_BANK */ else { pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE; @@ -340,6 +381,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) else { /* Erase by sector to be done */ +#if defined (DUAL_BANK) if(pEraseInit->Banks == FLASH_BANK_1) { pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; @@ -348,6 +390,9 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2; } +#else + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; +#endif /* DUAL_BANK */ pFlash.NbSectorsToErase = pEraseInit->NbSectors; pFlash.Sector = pEraseInit->Sector; @@ -386,10 +431,12 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { status = HAL_ERROR; } +#if defined (DUAL_BANK) else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) { status = HAL_ERROR; } +#endif /* DUAL_BANK */ else { status = HAL_OK; @@ -444,30 +491,54 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } #if defined(DUAL_CORE) - /*CM7 Boot Address configuration*/ + /* CM7 Boot Address configuration */ if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD) { FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); } - /*CM4 Boot Address configuration*/ + /* CM4 Boot Address configuration */ if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD) { FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1); } #else /* Single Core*/ - /*Boot Address configuration*/ + /* Boot Address configuration */ if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD) { FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); } #endif /*DUAL_CORE*/ - /*Bank1 secure area configuration*/ + /* Secure area configuration */ if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA) { FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks); } + +#if defined(FLASH_OTPBL_LOCKBL) + /* OTP Block Lock configuration */ + if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK) + { + FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); + } +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined(FLASH_OPTSR2_TCM_AXI_SHARED) + /* TCM / AXI Shared RAM configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM) + { + FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig); + } +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined(FLASH_OPTSR2_CPUFREQ_BOOST) + /* CPU Frequency Boost configuration */ + if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST) + { + FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState); + } +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ } /* Process Unlocked */ @@ -498,7 +569,11 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get BOR Level*/ pOBInit->BORLevel = FLASH_OB_GetBOR(); +#if defined (DUAL_BANK) if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) +#else + if (pOBInit->Banks == FLASH_BANK_1) +#endif /* DUAL_BANK */ { pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA); @@ -522,6 +597,27 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) #else pOBInit->OptionType |= OPTIONBYTE_BOOTADD; #endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) + pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK; + + /* Get OTP Block Lock */ + pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM; + + /* Get TCM / AXI Shared RAM */ + pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig(); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST; + + /* Get CPU Frequency Boost */ + pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost(); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ } /** @@ -557,6 +653,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void) return HAL_OK; } +#if defined (DUAL_BANK) /** * @brief Unlock the FLASH Bank2 control registers access * @retval HAL Status @@ -589,6 +686,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void) SET_BIT(FLASH->CR2, FLASH_CR_LOCK); return HAL_OK; } +#endif /* DUAL_BANK */ /* * @brief Perform a CRC computation on the specified FLASH memory area @@ -663,6 +761,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ /* Clear CRC flags */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1); } +#if defined (DUAL_BANK) else { /* Enable CRC feature */ @@ -711,6 +810,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ /* Clear CRC flags */ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2); } +#endif /* DUAL_BANK */ } return status; @@ -750,12 +850,18 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) { /* Check the parameters */ +#if defined (FLASH_CR_PSIZE) assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ assert_param(IS_FLASH_BANK(Banks)); +#if defined (DUAL_BANK) /* Flash Mass Erase */ if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) { +#if defined (FLASH_CR_PSIZE) /* Reset Program/erase VoltageRange for Bank1 and Bank2 */ FLASH->CR1 &= (~FLASH_CR_PSIZE); FLASH->CR2 &= (~FLASH_CR_PSIZE); @@ -763,31 +869,40 @@ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) /* Set voltage range */ FLASH->CR1 |= VoltageRange; FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ /* Set Mass Erase Bit */ FLASH->OPTCR |= FLASH_OPTCR_MER; } else +#endif /* DUAL_BANK */ { /* Proceed to erase Flash Bank */ if((Banks & FLASH_BANK_1) == FLASH_BANK_1) { - /* Reset Program/erase VoltageRange for Bank1 */ +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank1 */ FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR1 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ - /* Bank1 will be erased, and set voltage range */ - FLASH->CR1 |= FLASH_CR_BER | VoltageRange; - FLASH->CR1 |= FLASH_CR_START; + /* Erase Bank1 */ + FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); } + +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { - /* Reset Program/erase VoltageRange for Bank2 */ +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank2 */ FLASH->CR2 &= (~FLASH_CR_PSIZE); + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ - /* Bank2 will be erased, and set voltage range */ - FLASH->CR2 |= FLASH_CR_BER | VoltageRange; - FLASH->CR2 |= FLASH_CR_START; + /* Erase Bank2 */ + FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); } +#endif /* DUAL_BANK */ } } @@ -813,27 +928,43 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) { assert_param(IS_FLASH_SECTOR(Sector)); assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); +#if defined (FLASH_CR_PSIZE) assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ if((Banks & FLASH_BANK_1) == FLASH_BANK_1) { - /* reset Program/erase VoltageRange for Bank1 */ +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank1 */ FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); - FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos)); + FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_SNB); - FLASH->CR1 |= FLASH_CR_START; + FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { - /* reset Program/erase VoltageRange for Bank2 */ +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank2 */ FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); - FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos)); + FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_SNB); - FLASH->CR2 |= FLASH_CR_START; + FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ } +#endif /* DUAL_BANK */ } /** @@ -862,11 +993,13 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN)); } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Enable Write Protection for bank 2 */ FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN)); } +#endif /* DUAL_BANK */ } /** @@ -895,11 +1028,13 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN); } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Disable Write Protection for bank 2 */ FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN); } +#endif /* DUAL_BANK */ } /** @@ -924,15 +1059,17 @@ static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Ba { uint32_t regvalue = 0U; - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1) + if(Bank == FLASH_BANK_1) { regvalue = FLASH->WPSN_CUR1; } - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2) +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) { regvalue = FLASH->WPSN_CUR2; } +#endif /* DUAL_BANK */ (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN; @@ -1145,7 +1282,9 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7); optr_reg_mask |= FLASH_OPTSR_BCM7; } +#endif /* DUAL_CORE */ +#if defined (FLASH_OPTSR_NRST_STOP_D2) if((UserType & OB_USER_NRST_STOP_D2) != 0U) { /* NRST_STOP option byte should be modified */ @@ -1165,7 +1304,9 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2); optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2; } -#endif /*DUAL_CORE*/ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) if((UserType & OB_USER_SWAP_BANK) != 0U) { /* SWAP_BANK_OPT option byte should be modified */ @@ -1175,6 +1316,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT); optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT; } +#endif /* DUAL_BANK */ if((UserType & OB_USER_IOHSLV) != 0U) { @@ -1186,6 +1328,18 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) optr_reg_mask |= FLASH_OPTSR_IO_HSLV; } +#if defined (FLASH_OPTSR_VDDMMC_HSLV) + if((UserType & OB_USER_VDDMMC_HSLV) != 0U) + { + /* VDDMMC_HSLV option byte should be modified */ + assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV)); + + /* Set value and mask for VDDMMC_HSLV option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV); + optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV; + } +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + /* Configure the option bytes register */ MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val); } @@ -1259,6 +1413,7 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, PCROPConfig; } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr)); @@ -1269,6 +1424,7 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ PCROPConfig; } +#endif /* DUAL_BANK */ } /** @@ -1294,17 +1450,19 @@ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, u uint32_t regvalue = 0; uint32_t bankBase = 0; - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1) + if(Bank == FLASH_BANK_1) { regvalue = FLASH->PRAR_CUR1; bankBase = FLASH_BANK1_BASE; } - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2) +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) { regvalue = FLASH->PRAR_CUR2; bankBase = FLASH_BANK2_BASE; } +#endif /* DUAL_BANK */ (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP); @@ -1495,6 +1653,7 @@ static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t Secure (SecureAreaConfig & FLASH_SCAR_DMES); } +#if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) { /* Check the parameters */ @@ -1506,6 +1665,7 @@ static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t Secure (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ (SecureAreaConfig & FLASH_SCAR_DMES); } +#endif /* DUAL_BANK */ } /** @@ -1523,17 +1683,19 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA uint32_t bankBase = 0; /* Check Bank parameter value */ - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1) + if(Bank == FLASH_BANK_1) { regvalue = FLASH->SCAR_CUR1; bankBase = FLASH_BANK1_BASE; } - if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2) +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) { regvalue = FLASH->SCAR_CUR2; bankBase = FLASH_BANK2_BASE; } +#endif /* DUAL_BANK */ /* Get the secure area settings */ (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES); @@ -1561,6 +1723,7 @@ static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) /* Select CRC Sector and activate ADD_SECT bit */ FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT; } +#if defined (DUAL_BANK) else { /* Clear CRC sector */ @@ -1569,6 +1732,7 @@ static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) /* Select CRC Sector and activate ADD_SECT bit */ FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT; } +#endif /* DUAL_BANK */ } /** @@ -1589,6 +1753,7 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, FLASH->CRCSADD1 = CRCStartAddr; FLASH->CRCEADD1 = CRCEndAddr; } +#if defined (DUAL_BANK) else { assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr)); @@ -1598,11 +1763,93 @@ static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, FLASH->CRCSADD2 = CRCStartAddr; FLASH->CRCEADD2 = CRCEndAddr; } +#endif /* DUAL_BANK */ } /** * @} */ +#if defined (FLASH_OTPBL_LOCKBL) +/** + * @brief Configure the OTP Block Lock. + * @param OTP_Block specifies the OTP Block to lock. + * This parameter can be a value of @ref FLASHEx_OTP_Blocks + * @retval None + */ +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block) +{ + /* Check the parameters */ + assert_param(IS_OTP_BLOCK(OTP_Block)); + + /* Configure the OTP Block lock in the option bytes register */ + FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL); +} + +/** + * @brief Get the OTP Block Lock. + * @retval OTP_Block specifies the OTP Block to lock. + * This return value can be a value of @ref FLASHEx_OTP_Blocks + */ +static uint32_t FLASH_OB_OTP_GetLock(void) +{ + return (FLASH->OTPBL_CUR); +} +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** + * @brief Configure the TCM / AXI Shared RAM. + * @param SharedRamConfig specifies the Shared RAM configuration. + * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + * @retval None + */ +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig)); + + /* Configure the TCM / AXI Shared RAM in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig); +} + +/** + * @brief Get the TCM / AXI Shared RAM configurtion. + * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration. + * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + */ +static uint32_t FLASH_OB_SharedRAM_GetConfig(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);; +} +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** + * @brief Configure the CPU Frequency Boost. + * @param FreqBoost specifies the CPU Frequency Boost state. + * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + * @retval None + */ +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost)); + + /* Configure the CPU Frequency Boost in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost); +} + +/** + * @brief Get the CPU Frequency Boost state. + * @retval FreqBoost returns the CPU Frequency Boost state. + * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + */ +static uint32_t FLASH_OB_CPUFreq_GetBoost(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);; +} +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + #endif /* HAL_FLASH_MODULE_ENABLED */ /** diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c index ac9fc3d..13dcc40 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -198,26 +198,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00U) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3U]; - temp &= ~(0xFU << ((position & 0x07U) * 4U)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); - GPIOx->AFR[position >> 3U] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -243,6 +223,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -333,9 +333,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (0x0FUL << (4U * (position & 0x03U))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = 0x0FUL << (4U * (position & 0x03U)); - SYSCFG->EXTICR[position >> 2U] &= ~tmp; - /* Clear EXTI line configuration for Current CPU */ EXTI_CurrentCPU->IMR1 &= ~(iocurrent); EXTI_CurrentCPU->EMR1 &= ~(iocurrent); @@ -343,6 +340,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear Rising Falling edge configuration */ EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ @@ -352,14 +352,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); } position++; diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c index 1fab0ce..9fae472 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c @@ -101,6 +101,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #if defined(DUAL_CORE) +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + #ifndef HSEM_R_MASTERID #define HSEM_R_MASTERID HSEM_R_COREID #endif @@ -112,6 +116,10 @@ #ifndef HSEM_CR_MASTERID #define HSEM_CR_MASTERID HSEM_CR_COREID #endif + +/** + * @} + */ #endif /* DUAL_CORE */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c index a243923..635b01c 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -3200,7 +3203,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3285,7 +3288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3446,7 +3449,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3531,7 +3534,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -4737,6 +4752,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Process locked */ __HAL_LOCK(hi2c); + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ @@ -4788,9 +4810,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { if (hi2c->XferCount > 0U) { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -4844,13 +4863,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Nothing to do */ } - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5004,10 +5016,18 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ @@ -5075,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5092,11 +5128,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { I2C_ITAddrCplt(hi2c, ITFlags); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } else { /* Nothing to do */ @@ -5370,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5427,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5448,12 +5514,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5467,6 +5538,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5501,6 +5573,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5547,12 +5620,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5566,6 +5653,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5573,6 +5663,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5609,7 +5702,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5632,6 +5724,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5647,6 +5740,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5661,6 +5755,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5734,6 +5829,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5753,7 +5849,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5768,16 +5863,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5793,13 +5891,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5815,10 +5920,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5832,6 +5955,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6063,30 +6188,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6363,19 +6474,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6401,7 +6512,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6455,19 +6566,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c index ea50ce3..db8682d 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c @@ -276,6 +276,8 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) * only by using I2C_FASTMODEPLUS_I2C3 parameter. * @note For all I2C4 pins fast mode plus driving capability can be enabled * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) @@ -305,6 +307,8 @@ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) * only by using I2C_FASTMODEPLUS_I2C3 parameter. * @note For all I2C4 pins fast mode plus driving capability can be disabled * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. * @retval None */ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c index 2217070..08498c4 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -7,127 +7,127 @@ * + Initialization/de-initialization functions * + I/O operation functions * + Peripheral State and errors functions - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the MDMA Channel - (except for internal SRAM/FLASH memories: no initialization is + (except for internal SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between peripherals - and MDMA requests. - - (#) - For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters: - transfer request , channel priority, data endianness, Source increment, destination increment , - source data size, destination data size, data alignment, source Burst, destination Burst , - buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer + and MDMA requests. + + (#) + For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters: + transfer request , channel priority, data endianness, Source increment, destination increment , + source data size, destination data size, data alignment, source Burst, destination Burst , + buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer or full transfer) source and destination block address offset, mask address and data. - + If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node. Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero. Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position. - User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the + User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the last node of the list to the first one in order to make the list circular. In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init - + -@- The initial transfer itself (node 0 corresponding to the Init). - User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove + User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove the connection between last node and first one. Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list. - When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops), + When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops), the linked list remains circular and node 2 becomes the first one. Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user). [..] (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be transfer upon a request : - (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data + (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data with BufferTransferLength defined within the HAL_MDMA_Init. - (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block - with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block + with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT or within the current linked list node parameters. (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks - with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT or within the current linked list node parameters. - (++) MDMA_FULL_TRANSFER : each request triggers a full transfer + (++) MDMA_FULL_TRANSFER : each request triggers a full transfer all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode). *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source + ================================= + [..] + (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level - In this case a fixed Timeout can be configured by User depending from his application. - (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns + In this case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns when the abort ends or timeout (should not be called from an interrupt service routine). - - *** Interrupt mode IO operation *** - =================================== - [..] + + *** Interrupt mode IO operation *** + =================================== + [..] (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the MDMA interrupt is configured. + (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the MDMA interrupt is configured. (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of MDMA handle structure). - + (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of MDMA handle structure). + (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel has effectively aborted. (could be called from an interrupt service routine). - + (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks from the following list : (++) XferCpltCallback : transfer complete callback. (++) XferBufferCpltCallback : buffer transfer complete callback. (++) XferBlockCpltCallback : block transfer complete callback. - (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback. - (++) XferErrorCallback : transfer error callback. - (++) XferAbortCallback : transfer abort complete callback. - + (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + [..] (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions: (++) This function returns an error if used while the Transfer has ended or not started. (++) If used while the current request has not been served yet (current request transfer on going) this function returns an error and the new request is ignored. - - Generally this function should be used in conjunctions with the MDMA callbacks: - (++) example 1: + + Generally this function should be used in conjunctions with the MDMA callbacks: + (++) example 1: (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER - (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID) + (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID) (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data. - (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer - request using HAL_MDMA_GenerateSWRequest. - - (++) example 2: + (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer + request using HAL_MDMA_GenerateSWRequest. + + (++) example 2: (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER - (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID) + (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID) (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data. - (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask - for a new block transfer request using HAL_MDMA_GenerateSWRequest. + (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask + for a new block transfer request using HAL_MDMA_GenerateSWRequest. [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection. *** MDMA HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in MDMA HAL driver. - + (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel. (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel. (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags. (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags. (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts. (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts. - (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not. - - [..] + (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not. + + [..] (@) You can refer to the header file of the MDMA HAL driver for more useful macros. [..] @@ -167,7 +167,7 @@ * @{ */ #define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */ -#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */ +#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */ /** * @} */ @@ -190,42 +190,42 @@ static void MDMA_Init(MDMA_HandleTypeDef *hmdma); /** @addtogroup MDMA_Exported_Functions_Group1 * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to : Initialize and de-initialize the MDMA channel. - Register and Unregister MDMA callbacks + Register and Unregister MDMA callbacks [..] The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in - reference manual. + reference manual. The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel. - HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows + HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows respectevely to register/unregister an MDMA callback function. @endverbatim * @{ */ - + /** * @brief Initializes the MDMA according to the specified * parameters in the MDMA_InitTypeDef and create the associated handle. * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains - * the configuration information for the specified MDMA Channel. + * the configuration information for the specified MDMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) { uint32_t tickstart = HAL_GetTick(); - + /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance)); assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority)); @@ -241,18 +241,18 @@ HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength)); assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode)); assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); - assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); - - + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); + + /* Allocate lock resource */ __HAL_UNLOCK(hmdma); - + /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_BUSY; - + /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); - + /* Check if the MDMA channel is effectively disabled */ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) { @@ -261,85 +261,78 @@ HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) { /* Update error code */ hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT; - + /* Change the MDMA state */ hmdma->State = HAL_MDMA_STATE_ERROR; - + return HAL_ERROR; } } - + /* Initialize the MDMA channel registers */ MDMA_Init(hmdma); - + /* Reset the MDMA first/last linkedlist node addresses and node counter */ - hmdma->FirstLinkedListNodeAddress = 0; - hmdma->LastLinkedListNodeAddress = 0; - hmdma->LinkedListNodeCounter = 0; - + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + /* Initialize the error code */ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; - + /* Initialize the MDMA state */ hmdma->State = HAL_MDMA_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitializes the MDMA peripheral + * @brief DeInitializes the MDMA peripheral * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains - * the configuration information for the specified MDMA Channel. + * the configuration information for the specified MDMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma) -{ - +{ + /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; } - - /* Check the MDMA peripheral state */ - if(hmdma->State == HAL_MDMA_STATE_BUSY) - { - hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; - return HAL_ERROR; - } - + /* Disable the selected MDMA Channelx */ __HAL_MDMA_DISABLE(hmdma); - + /* Reset MDMA Channel control register */ hmdma->Instance->CCR = 0; hmdma->Instance->CTCR = 0; hmdma->Instance->CBNDTR = 0; hmdma->Instance->CSAR = 0; - hmdma->Instance->CDAR = 0; + hmdma->Instance->CDAR = 0; hmdma->Instance->CBRUR = 0; hmdma->Instance->CLAR = 0; hmdma->Instance->CTBR = 0; hmdma->Instance->CMAR = 0; hmdma->Instance->CMDR = 0; - + /* Clear all flags */ __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC)); - + /* Reset the MDMA first/last linkedlist node addresses and node counter */ - hmdma->FirstLinkedListNodeAddress = 0; - hmdma->LastLinkedListNodeAddress = 0; - hmdma->LinkedListNodeCounter = 0; - + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + /* Initialize the error code */ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; - + /* Initialize the MDMA state */ hmdma->State = HAL_MDMA_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hmdma); - + return HAL_OK; } @@ -351,7 +344,7 @@ HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma) * @param MaskData: specifies the value to be written to MaskAddress after a request is served. * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData) { HAL_StatusTypeDef status = HAL_OK; @@ -361,10 +354,10 @@ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint { return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* if HW request set Post Request MaskAddress and MaskData, */ @@ -374,7 +367,7 @@ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint hmdma->Instance->CMAR = MaskAddress; hmdma->Instance->CMDR = MaskData; - /* + /* -If the request is done by SW : BWM could be set to 1 or 0. -If the request is done by a peripheral : If mask address not set (0) => BWM must be set to 0 @@ -392,7 +385,7 @@ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } } else @@ -402,8 +395,8 @@ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint } /* Release Lock */ __HAL_UNLOCK(hmdma); - - return status; + + return status; } /** @@ -413,20 +406,20 @@ HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint * @param CallbackID: User Callback identifier * @param pCallback: pointer to callbacsk function. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)) -{ +{ HAL_StatusTypeDef status = HAL_OK; /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; - } - + } + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { switch (CallbackID) @@ -434,27 +427,27 @@ HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_ case HAL_MDMA_XFER_CPLT_CB_ID: hmdma->XferCpltCallback = pCallback; break; - + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: hmdma->XferBufferCpltCallback = pCallback; break; - + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: hmdma->XferBlockCpltCallback = pCallback; break; - + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: hmdma->XferRepeatBlockCpltCallback = pCallback; break; - + case HAL_MDMA_XFER_ERROR_CB_ID: hmdma->XferErrorCallback = pCallback; break; - + case HAL_MDMA_XFER_ABORT_CB_ID: hmdma->XferAbortCallback = pCallback; break; - + default: break; } @@ -464,10 +457,10 @@ HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_ /* Return error status */ status = HAL_ERROR; } - + /* Release Lock */ __HAL_UNLOCK(hmdma); - + return status; } @@ -488,10 +481,10 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM { return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { switch (CallbackID) @@ -499,27 +492,27 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM case HAL_MDMA_XFER_CPLT_CB_ID: hmdma->XferCpltCallback = NULL; break; - + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: hmdma->XferBufferCpltCallback = NULL; break; - + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: hmdma->XferBlockCpltCallback = NULL; break; - + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: hmdma->XferRepeatBlockCpltCallback = NULL; break; - + case HAL_MDMA_XFER_ERROR_CB_ID: hmdma->XferErrorCallback = NULL; break; - + case HAL_MDMA_XFER_ABORT_CB_ID: hmdma->XferAbortCallback = NULL; - break; - + break; + case HAL_MDMA_XFER_ALL_CB_ID: hmdma->XferCpltCallback = NULL; hmdma->XferBufferCpltCallback = NULL; @@ -527,8 +520,8 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM hmdma->XferRepeatBlockCpltCallback = NULL; hmdma->XferErrorCallback = NULL; hmdma->XferAbortCallback = NULL; - break; - + break; + default: status = HAL_ERROR; break; @@ -538,10 +531,10 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM { status = HAL_ERROR; } - + /* Release Lock */ __HAL_UNLOCK(hmdma); - + return status; } @@ -551,15 +544,15 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM /** @addtogroup MDMA_Exported_Functions_Group2 * -@verbatim +@verbatim =============================================================================== ##### Linked list operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Create a linked list node (+) Add a node to the MDMA linked list (+) Remove a node from the MDMA linked list - (+) Enable/Disable linked list circular mode + (+) Enable/Disable linked list circular mode @endverbatim * @{ */ @@ -567,23 +560,23 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM /** * @brief Initializes an MDMA Link Node according to the specified * parameters in the pMDMA_LinkedListNodeConfig . - * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node - * registers configurations. + * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * registers configurations. * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains - * the configuration information for the specified MDMA Linked List Node. + * the configuration information for the specified MDMA Linked List Node. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig) { uint32_t addressMask; uint32_t blockoffset; - + /* Check the MDMA peripheral state */ if((pNode == NULL) || (pNodeConfig == NULL)) { return HAL_ERROR; - } - + } + /* Check the parameters */ assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority)); assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness)); @@ -599,20 +592,20 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode)); assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset)); assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset)); - + assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength)); - assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); - - + assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); + + /* Configure next Link node Address Register to zero */ pNode->CLAR = 0; - + /* Configure the Link Node registers*/ pNode->CTBR = 0; - pNode->CMAR = 0; + pNode->CMAR = 0; pNode->CMDR = 0; pNode->Reserved = 0; - + /* Write new CTCR Register value */ pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \ pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ @@ -620,14 +613,14 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD pNodeConfig->Init.DestBurst | \ ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ pNodeConfig->Init.TransferTriggerMode; - + /* If SW request set the CTCR register to SW Request Mode*/ if(pNodeConfig->Init.Request == MDMA_REQUEST_SW) { pNode->CTCR |= MDMA_CTCR_SWRM; } - - /* + + /* -If the request is done by SW : BWM could be set to 1 or 0. -If the request is done by a peripheral : If mask address not set (0) => BWM must be set to 0 @@ -637,10 +630,10 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD { pNode->CTCR |= MDMA_CTCR_BWM; } - - /* Set the new CBNDTR Register value */ + + /* Set the new CBNDTR Register value */ pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC; - + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ if(pNodeConfig->Init.SourceBlockAddressOffset < 0) { @@ -651,10 +644,10 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD } else { - /*write new CBRUR Register value : source repeat block offset */ - pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU); - } - + /*write new CBRUR Register value : source repeat block offset */ + pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ if(pNodeConfig->Init.DestBlockAddressOffset < 0) { @@ -665,19 +658,19 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD } else { - /*write new CBRUR Register value : destination repeat block offset */ - pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); - } - + /*write new CBRUR Register value : destination repeat block offset */ + pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + /* Configure MDMA Link Node data length */ pNode->CBNDTR |= pNodeConfig->BlockDataLength; - + /* Configure MDMA Link Node destination address */ - pNode->CDAR = pNodeConfig->DstAddress; - + pNode->CDAR = pNodeConfig->DstAddress; + /* Configure MDMA Link Node Source address */ pNode->CSAR = pNodeConfig->SrcAddress; - + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ if(pNodeConfig->Init.Request != MDMA_REQUEST_SW) { @@ -685,23 +678,23 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL; /* Set the HW request clear Mask and Data */ pNode->CMAR = pNodeConfig->PostRequestMaskAddress; - pNode->CMDR = pNodeConfig->PostRequestMaskData; + pNode->CMDR = pNodeConfig->PostRequestMaskData; } - + addressMask = pNodeConfig->SrcAddress & 0xFF000000U; if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) { /*The AHBSbus is used as source (read operation) on channel x */ - pNode->CTBR |= MDMA_CTBR_SBUS; + pNode->CTBR |= MDMA_CTBR_SBUS; } - + addressMask = pNodeConfig->DstAddress & 0xFF000000U; if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) { /*The AHB bus is used as destination (write operation) on channel x */ pNode->CTBR |= MDMA_CTBR_DBUS; } - + return HAL_OK; } @@ -709,10 +702,10 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD * @brief Connect a node to the linked list. * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. - * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node * to be add to the list. * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node - * at the end of the list + * at the end of the list * * @retval HAL status */ @@ -720,40 +713,40 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_Li { MDMA_LinkNodeTypeDef *pNode; uint32_t counter = 0, nodeInserted = 0; - HAL_StatusTypeDef hal_status = HAL_OK; - + HAL_StatusTypeDef hal_status = HAL_OK; + /* Check the MDMA peripheral handle */ if((hmdma == NULL) || (pNewNode == NULL)) { return HAL_ERROR; - } - + } + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_BUSY; - + /* Check if this is the first node (after the Inititlization node) */ if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) { if(pPrevNode == NULL) { - /* if this is the first node after the initialization + /* if this is the first node after the initialization connect this node to the node 0 by updating the MDMA channel CLAR register to this node address */ hmdma->Instance->CLAR = (uint32_t)pNewNode; /* Set the MDMA handle First linked List node*/ hmdma->FirstLinkedListNodeAddress = pNewNode; - + /*reset New node link */ pNewNode->CLAR = 0; - - /* Update the Handle last node address */ + + /* Update the Handle last node address */ hmdma->LastLinkedListNodeAddress = pNewNode; - + hmdma->LinkedListNodeCounter = 1; } else @@ -761,9 +754,9 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_Li hal_status = HAL_ERROR; } } - else if(hmdma->FirstLinkedListNodeAddress != pNewNode) + else if(hmdma->FirstLinkedListNodeAddress != pNewNode) { - /* Check if the node to insert already exists*/ + /* Check if the node to insert already exists*/ pNode = hmdma->FirstLinkedListNodeAddress; while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK)) { @@ -774,14 +767,14 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_Li pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; counter++; } - + if(hal_status == HAL_OK) { - /* Check if the previous node is the last one in the current list or zero */ + /* Check if the previous node is the last one in the current list or zero */ if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL)) { /* insert the new node at the end of the list */ - pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR; + pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR; hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; /* Update the Handle last node address */ hmdma->LastLinkedListNodeAddress = pNewNode; @@ -790,7 +783,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_Li } else { - /*insert the new node after the pPreviousNode node */ + /*insert the new node after the pPreviousNode node */ pNode = hmdma->FirstLinkedListNodeAddress; counter = 0; while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U)) @@ -800,7 +793,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_Li { /*Insert the new node after the previous one */ pNewNode->CLAR = pNode->CLAR; - pNode->CLAR = (uint32_t)pNewNode; + pNode->CLAR = (uint32_t)pNewNode; /* Increment the linked list node counter */ hmdma->LinkedListNodeCounter++; nodeInserted = 1; @@ -810,41 +803,41 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_Li pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; } } - + if(nodeInserted == 0U) { hal_status = HAL_ERROR; } } - } + } } else { - hal_status = HAL_ERROR; + hal_status = HAL_ERROR; } - + /* Process unlocked */ - __HAL_UNLOCK(hmdma); - + __HAL_UNLOCK(hmdma); + hmdma->State = HAL_MDMA_STATE_READY; - - return hal_status; + + return hal_status; } else { /* Process unlocked */ __HAL_UNLOCK(hmdma); - + /* Return error status */ return HAL_BUSY; - } + } } /** * @brief Disconnect/Remove a node from the transfer linked list. * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. - * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node * to be removed from the list. * * @retval HAL status @@ -853,22 +846,22 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA { MDMA_LinkNodeTypeDef *ptmpNode; uint32_t counter = 0, nodeDeleted = 0; - HAL_StatusTypeDef hal_status = HAL_OK; - + HAL_StatusTypeDef hal_status = HAL_OK; + /* Check the MDMA peripheral handle */ if((hmdma == NULL) || (pNode == NULL)) { return HAL_ERROR; - } - + } + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_BUSY; - + /* If first and last node are null (no nodes in the list) : return error*/ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) { @@ -881,11 +874,11 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA { /*if the last node is at the same time the first one (1 single node after the init node 0) then update the last node too */ - + hmdma->FirstLinkedListNodeAddress = 0; hmdma->LastLinkedListNodeAddress = 0; hmdma->LinkedListNodeCounter = 0; - + hmdma->Instance->CLAR = 0; } else @@ -895,19 +888,19 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA /* if last node is looping to first (circular list) one update the last node connection */ hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR; } - - /* if deleting the first node after the initialization + + /* if deleting the first node after the initialization connect the next node to the node 0 by updating - the MDMA channel CLAR register to this node address */ + the MDMA channel CLAR register to this node address */ hmdma->Instance->CLAR = pNode->CLAR; hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; /* Update the Handle node counter */ - hmdma->LinkedListNodeCounter--; - } + hmdma->LinkedListNodeCounter--; + } } else /* Deleting any other node */ { - /*Deleted node is not the first one : find it */ + /*Deleted node is not the first one : find it */ ptmpNode = hmdma->FirstLinkedListNodeAddress; while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U)) { @@ -924,36 +917,36 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA ptmpNode->CLAR = pNode->CLAR; nodeDeleted = 1; /* Update the Handle node counter */ - hmdma->LinkedListNodeCounter--; + hmdma->LinkedListNodeCounter--; } else { ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR; } } - + if(nodeDeleted == 0U) { /* last node reashed without finding the node to delete : return error */ hal_status = HAL_ERROR; } } - + /* Process unlocked */ - __HAL_UNLOCK(hmdma); - + __HAL_UNLOCK(hmdma); + hmdma->State = HAL_MDMA_STATE_READY; - - return hal_status; + + return hal_status; } else { /* Process unlocked */ __HAL_UNLOCK(hmdma); - + /* Return error status */ return HAL_BUSY; - } + } } /** @@ -964,22 +957,22 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA */ HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma) { - HAL_StatusTypeDef hal_status = HAL_OK; - + HAL_StatusTypeDef hal_status = HAL_OK; + /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; - } - + } + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* Change MDMA peripheral state */ - hmdma->State = HAL_MDMA_STATE_BUSY; - + hmdma->State = HAL_MDMA_STATE_BUSY; + /* If first and last node are null (no nodes in the list) : return error*/ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) { @@ -990,14 +983,14 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmd /* to enable circular mode Last Node should be connected to first node */ hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; } - + } /* Process unlocked */ - __HAL_UNLOCK(hmdma); - + __HAL_UNLOCK(hmdma); + hmdma->State = HAL_MDMA_STATE_READY; - - return hal_status; + + return hal_status; } /** @@ -1008,22 +1001,22 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmd */ HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma) { - HAL_StatusTypeDef hal_status = HAL_OK; - + HAL_StatusTypeDef hal_status = HAL_OK; + /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; - } - + } + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* Change MDMA peripheral state */ - hmdma->State = HAL_MDMA_STATE_BUSY; - + hmdma->State = HAL_MDMA_STATE_BUSY; + /* If first and last node are null (no nodes in the list) : return error*/ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) { @@ -1034,14 +1027,14 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hm /* to disable circular mode Last Node should be connected to NULL */ hmdma->LastLinkedListNodeAddress->CLAR = 0; } - + } /* Process unlocked */ - __HAL_UNLOCK(hmdma); - + __HAL_UNLOCK(hmdma); + hmdma->State = HAL_MDMA_STATE_READY; - - return hal_status; + + return hal_status; } /** @@ -1050,18 +1043,18 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hm /** @addtogroup MDMA_Exported_Functions_Group3 * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start MDMA transfer - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start MDMA transfer with interrupt (+) Abort MDMA transfer (+) Poll for transfer complete (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW) - (+) Handle MDMA interrupt request + (+) Handle MDMA interrupt request @endverbatim * @{ @@ -1070,7 +1063,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hm /** * @brief Starts the MDMA Transfer. * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains - * the configuration information for the specified MDMA Channel. + * the configuration information for the specified MDMA Channel. * @param SrcAddress : The source memory Buffer address * @param DstAddress : The destination memory Buffer address * @param BlockDataLength : The length of a block transfer in bytes @@ -1081,56 +1074,56 @@ HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, { /* Check the parameters */ assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); - assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_BUSY; - + /* Initialize the error code */ - hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; - + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + /* Disable the peripheral */ __HAL_MDMA_DISABLE(hmdma); - + /* Configure the source, destination address and the data length */ MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); - + /* Enable the Peripheral */ __HAL_MDMA_ENABLE(hmdma); - + if(hmdma->Init.Request == MDMA_REQUEST_SW) { /* activate If SW request mode*/ hmdma->Instance->CCR |= MDMA_CCR_SWRQ; - } + } } else { /* Process unlocked */ __HAL_UNLOCK(hmdma); - + /* Return error status */ return HAL_BUSY; } - - return HAL_OK; + + return HAL_OK; } /** * @brief Starts the MDMA Transfer with interrupts enabled. * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains - * the configuration information for the specified MDMA Channel. + * the configuration information for the specified MDMA Channel. * @param SrcAddress : The source memory Buffer address * @param DstAddress : The destination memory Buffer address * @param BlockDataLength : The length of a block transfer in bytes @@ -1141,83 +1134,83 @@ HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddre { /* Check the parameters */ assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); - assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hmdma); - + if(HAL_MDMA_STATE_READY == hmdma->State) { /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_BUSY; - + /* Initialize the error code */ - hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; - + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + /* Disable the peripheral */ __HAL_MDMA_DISABLE(hmdma); - + /* Configure the source, destination address and the data length */ MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); - + /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/ __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC)); - + if(hmdma->XferBlockCpltCallback != NULL) { /* if Block transfer complete Callback is set enable the corresponding IT*/ - __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT); + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT); } - + if(hmdma->XferRepeatBlockCpltCallback != NULL) { - /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/ - __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT); - } - + /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT); + } + if(hmdma->XferBufferCpltCallback != NULL) { /* if buffer transfer complete Callback is set enable the corresponding IT*/ __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC); } - + /* Enable the Peripheral */ __HAL_MDMA_ENABLE(hmdma); - + if(hmdma->Init.Request == MDMA_REQUEST_SW) { /* activate If SW request mode*/ hmdma->Instance->CCR |= MDMA_CCR_SWRQ; - } + } } else { /* Process unlocked */ __HAL_UNLOCK(hmdma); - + /* Return error status */ return HAL_BUSY; } - + return HAL_OK; -} +} /** * @brief Aborts the MDMA Transfer. * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. - * - * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is - * effectively disabled is added. If a Channel is disabled + * + * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is + * effectively disabled is added. If a Channel is disabled * while a data transfer is ongoing, the current data will be transferred * and the Channel will be effectively disabled only after the transfer of - * this single data is finished. + * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) @@ -1228,25 +1221,25 @@ HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) if(hmdma == NULL) { return HAL_ERROR; - } - + } + if(HAL_MDMA_STATE_BUSY != hmdma->State) { hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; - + /* Process Unlocked */ __HAL_UNLOCK(hmdma); - + return HAL_ERROR; } else { /* Disable all the transfer interrupts */ __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); - + /* Disable the channel */ __HAL_MDMA_DISABLE(hmdma); - + /* Check if the MDMA Channel is effectively disabled */ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) { @@ -1255,28 +1248,28 @@ HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) { /* Update error code */ hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hmdma); - + /* Change the MDMA state */ hmdma->State = HAL_MDMA_STATE_ERROR; - + return HAL_ERROR; } } - + /* Clear all interrupt flags */ __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC)); - + /* Process Unlocked */ __HAL_UNLOCK(hmdma); - + /* Change the MDMA state*/ - hmdma->State = HAL_MDMA_STATE_READY; + hmdma->State = HAL_MDMA_STATE_READY; } - - return HAL_OK; + + return HAL_OK; } /** @@ -1292,23 +1285,23 @@ HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma) { return HAL_ERROR; } - + if(HAL_MDMA_STATE_BUSY != hmdma->State) { /* No transfer ongoing */ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; - + return HAL_ERROR; } else { /* Set Abort State */ hmdma->State = HAL_MDMA_STATE_ABORT; - + /* Disable the stream */ __HAL_MDMA_DISABLE(hmdma); } - + return HAL_OK; } @@ -1316,7 +1309,7 @@ HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma) * @brief Polling for transfer complete. * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains * the configuration information for the specified MDMA Channel. - * @param CompleteLevel: Specifies the MDMA level complete. + * @param CompleteLevel: Specifies the MDMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ @@ -1324,7 +1317,7 @@ HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_L { uint32_t levelFlag, errorFlag; uint32_t tickstart; - + /* Check the parameters */ assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel)); @@ -1332,33 +1325,33 @@ HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_L if(hmdma == NULL) { return HAL_ERROR; - } - + } + if(HAL_MDMA_STATE_BUSY != hmdma->State) { /* No transfer ongoing */ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; - + return HAL_ERROR; - } - + } + /* Get the level transfer complete flag */ levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \ (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ MDMA_FLAG_BRT); - - + + /* Get timeout */ tickstart = HAL_GetTick(); - + while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U) { if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) - { + { /* Get the transfer error source flag */ errorFlag = hmdma->Instance->CESR; - + if((errorFlag & MDMA_CESR_TED) == 0U) { /* Update error code : Read Transfer error */ @@ -1367,46 +1360,46 @@ HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_L else { /* Update error code : Write Transfer error */ - hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; } - + if((errorFlag & MDMA_CESR_TEMD) != 0U) { /* Update error code : Error Mask Data */ hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; } - + if((errorFlag & MDMA_CESR_TELD) != 0U) { /* Update error code : Error Linked list */ hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; } - + if((errorFlag & MDMA_CESR_ASE) != 0U) { /* Update error code : Address/Size alignment error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; } - + if((errorFlag & MDMA_CESR_BSE) != 0U) { /* Update error code : Block Size error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; - } - + } + (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */ - + /* - Note that the Abort function will + Note that the Abort function will - Clear all transfer flags - Unlock - - Set the State - */ - + - Set the State + */ + return HAL_ERROR; - + } - + /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { @@ -1418,122 +1411,122 @@ HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_L (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */ /* - Note that the Abort function will + Note that the Abort function will - Clear all transfer flags - Unlock - - Set the State + - Set the State */ - + return HAL_ERROR; } } } - + /* Clear the transfer level flag */ if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER) { __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); - + } else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) { __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT)); - + } else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER) { - __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT)); - } + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT)); + } else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER) { __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC)); - + /* Process unlocked */ - __HAL_UNLOCK(hmdma); - + __HAL_UNLOCK(hmdma); + hmdma->State = HAL_MDMA_STATE_READY; } else { return HAL_ERROR; } - + return HAL_OK; } /** * @brief Generate an MDMA SW request trigger to activate the request on the given Channel. * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains - * the configuration information for the specified MDMA Stream. + * the configuration information for the specified MDMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma) { uint32_t request_mode; - + /* Check the MDMA peripheral handle */ if(hmdma == NULL) { return HAL_ERROR; } - + /* Get the softawre request mode */ request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM; - + if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U) { /* if no Transfer on going (MDMA enable bit not set) retrun error */ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; - - return HAL_ERROR; + + return HAL_ERROR; } else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U)) { /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */ hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; - - return HAL_ERROR; + + return HAL_ERROR; } else { /* Set the SW request bit to activate the request on the Channel */ hmdma->Instance->CCR |= MDMA_CCR_SWRQ; - + return HAL_OK; } -} +} /** * @brief Handles MDMA interrupt request. * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains - * the configuration information for the specified MDMA Channel. + * the configuration information for the specified MDMA Channel. * @retval None */ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) { __IO uint32_t count = 0; uint32_t timeout = SystemCoreClock / 9600U; - + uint32_t generalIntFlag, errorFlag; - - /* General Interrupt Flag management ****************************************/ + + /* General Interrupt Flag management ****************************************/ generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU); if((MDMA->GISR0 & generalIntFlag) == 0U) { return; /* the General interrupt flag for the current channel is down , nothing to do */ - } - + } + /* Transfer Error Interrupt management ***************************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) { if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U) - { + { /* Disable the transfer error interrupt */ __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE); - + /* Get the transfer error source flag */ errorFlag = hmdma->Instance->CESR; - + if((errorFlag & MDMA_CESR_TED) == 0U) { /* Update error code : Read Transfer error */ @@ -1542,38 +1535,38 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) else { /* Update error code : Write Transfer error */ - hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; } - + if((errorFlag & MDMA_CESR_TEMD) != 0U) { /* Update error code : Error Mask Data */ hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; } - + if((errorFlag & MDMA_CESR_TELD) != 0U) { /* Update error code : Error Linked list */ hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; } - + if((errorFlag & MDMA_CESR_ASE) != 0U) { /* Update error code : Address/Size alignment error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; } - + if((errorFlag & MDMA_CESR_BSE) != 0U) { /* Update error code : Block Size error error */ hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; - } - + } + /* Clear the transfer error flags */ - __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); } } - + /* Buffer Transfer Complete Interrupt management ******************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U)) { @@ -1581,15 +1574,15 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) { /* Clear the buffer transfer complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); - + if(hmdma->XferBufferCpltCallback != NULL) { /* Buffer transfer callback */ hmdma->XferBufferCpltCallback(hmdma); - } + } } } - + /* Block Transfer Complete Interrupt management ******************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U)) { @@ -1597,15 +1590,15 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) { /* Clear the block transfer complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT); - + if(hmdma->XferBlockCpltCallback != NULL) { /* Block transfer callback */ hmdma->XferBlockCpltCallback(hmdma); - } + } } } - + /* Repeated Block Transfer Complete Interrupt management ******************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U)) { @@ -1613,15 +1606,15 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) { /* Clear the repeat block transfer complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT); - + if(hmdma->XferRepeatBlockCpltCallback != NULL) { /* Repeated Block transfer callback */ hmdma->XferRepeatBlockCpltCallback(hmdma); - } + } } - } - + } + /* Channel Transfer Complete Interrupt management ***********************************/ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U)) { @@ -1629,47 +1622,47 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) { /* Disable all the transfer interrupts */ __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); - + if(HAL_MDMA_STATE_ABORT == hmdma->State) { /* Process Unlocked */ __HAL_UNLOCK(hmdma); - + /* Change the DMA state */ hmdma->State = HAL_MDMA_STATE_READY; - + if(hmdma->XferAbortCallback != NULL) { hmdma->XferAbortCallback(hmdma); } return; } - + /* Clear the Channel Transfer Complete flag */ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC); - + /* Process Unlocked */ - __HAL_UNLOCK(hmdma); - + __HAL_UNLOCK(hmdma); + /* Change MDMA peripheral state */ hmdma->State = HAL_MDMA_STATE_READY; - + if(hmdma->XferCpltCallback != NULL) { /* Channel Transfer Complete callback */ hmdma->XferCpltCallback(hmdma); - } + } } } - + /* manage error case */ if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE) { hmdma->State = HAL_MDMA_STATE_ABORT; - + /* Disable the channel */ __HAL_MDMA_DISABLE(hmdma); - + do { if (++count > timeout) @@ -1678,10 +1671,10 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) } } while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U); - + /* Process Unlocked */ __HAL_UNLOCK(hmdma); - + if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) { /* Change the MDMA state to error if MDMA disable fails */ @@ -1690,10 +1683,10 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) else { /* Change the MDMA state to Ready if MDMA disable success */ - hmdma->State = HAL_MDMA_STATE_READY; + hmdma->State = HAL_MDMA_STATE_READY; } - + if (hmdma->XferErrorCallback != NULL) { /* Transfer error callback */ @@ -1768,34 +1761,34 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) { uint32_t addressMask; - + /* Configure the MDMA Channel data length */ MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT)); - + /* Configure the MDMA block repeat count */ MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC); - + /* Clear all interrupt flags */ - __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF); - + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF); + /* Configure MDMA Channel destination address */ - hmdma->Instance->CDAR = DstAddress; - + hmdma->Instance->CDAR = DstAddress; + /* Configure MDMA Channel Source address */ hmdma->Instance->CSAR = SrcAddress; - + addressMask = SrcAddress & 0xFF000000U; if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) { /*The AHBSbus is used as source (read operation) on channel x */ - hmdma->Instance->CTBR |= MDMA_CTBR_SBUS; + hmdma->Instance->CTBR |= MDMA_CTBR_SBUS; } else { /*The AXI bus is used as source (read operation) on channel x */ - hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS); + hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS); } - + addressMask = DstAddress & 0xFF000000U; if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) { @@ -1805,11 +1798,11 @@ static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint3 else { /*The AXI bus is used as destination (write operation) on channel x */ - hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS); + hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS); } - + /* Set the linked list register to the first node of the list */ - hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; + hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; } /** @@ -1825,7 +1818,7 @@ static void MDMA_Init(MDMA_HandleTypeDef *hmdma) /* Prepare the MDMA Channel configuration */ hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness; - + /* Write new CTCR Register value */ hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ @@ -1833,22 +1826,22 @@ static void MDMA_Init(MDMA_HandleTypeDef *hmdma) hmdma->Init.DestBurst | \ ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ hmdma->Init.TransferTriggerMode; - + /* If SW request set the CTCR register to SW Request Mode */ if(hmdma->Init.Request == MDMA_REQUEST_SW) { - /* + /* -If the request is done by SW : BWM could be set to 1 or 0. -If the request is done by a peripheral : If mask address not set (0) => BWM must be set to 0 If mask address set (different than 0) => BWM could be set to 1 or 0 - */ + */ hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM); - } - - /* Reset CBNDTR Register */ + } + + /* Reset CBNDTR Register */ hmdma->Instance->CBNDTR = 0; - + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ if(hmdma->Init.SourceBlockAddressOffset < 0) { @@ -1859,35 +1852,35 @@ static void MDMA_Init(MDMA_HandleTypeDef *hmdma) } else { - /* Write new CBRUR Register value : source repeat block offset */ - hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + /* Write new CBRUR Register value : source repeat block offset */ + hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); } - + /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ if(hmdma->Init.DestBlockAddressOffset < 0) { hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM; /* Write new CBRUR Register value : destination repeat block offset */ blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset); - hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); } else { - /*write new CBRUR Register value : destination repeat block offset */ - hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); - } - + /*write new CBRUR Register value : destination repeat block offset */ + hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ if(hmdma->Init.Request != MDMA_REQUEST_SW) { /* Set the HW request in CTRB register */ - hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; + hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; } else /* SW request : reset the CTBR register */ { hmdma->Instance->CTBR = 0; } - + /* Write Link Address Register */ hmdma->Instance->CLAR = 0; } diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c index 2b4b510..3a847e8 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c @@ -1058,6 +1058,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + temp = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { epnum = 0U; @@ -1079,9 +1111,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) @@ -1092,10 +1124,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { - if (hpcd->Init.dma_enable == 1U) - { - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } @@ -1133,16 +1161,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (hpcd->Init.dma_enable == 1U) { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - if (hpcd->Init.dma_enable == 1U) - { /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) { @@ -1150,6 +1169,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { @@ -1255,8 +1280,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; } USBx_DEVICE->DAINTMSK |= 0x10001U; @@ -1313,38 +1340,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - /* Handle RxQLevel Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - temp = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) - { - (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); - - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - else - { - /* ... */ - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { @@ -2071,16 +2066,6 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); } - - /* Inform the upper layer that a setup packet is available */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SetupStageCallback(hpcd); -#else - HAL_PCD_SetupStageCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ { @@ -2103,17 +2088,16 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else @@ -2146,6 +2130,12 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2171,22 +2161,10 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - if (hpcd->Init.dma_enable == 1U) + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) { - /* StupPktRcvd = 1 pending setup packet int */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - } - else - { - if ((gSNPSiD == USB_OTG_CORE_ID_310A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); } /* Inform the upper layer that a setup packet is available */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c index 31e8f3d..94c4acc 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -5,9 +5,130 @@ * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * + * + Initialization and de-initialization functions. + * + Peripheral Control functions. + * + Interrupt Handling functions. + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + In the H7 family, the number of power domains is different between + device lines. This difference is due to characteristics of each device. + + (#) Domain architecture overview for the different H7 lines: + (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757. + These devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals and a CPU + (Cortex-M4). The D3 domain contains the system control, I/O logic + and low-power peripherals. + (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753 + devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals. The D3 domains + contains the system control, I/O logic and low-power peripherals. + (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD). + The core domain (CD) contains a CPU (Cortex-M7), a Flash + memory and peripherals. The SmartRun domain contains the system + control, I/O logic and low-power peripherals. + + (#) Every entity have low power mode as decribed below : + (#) The CPU low power modes are : + (+) CPU CRUN. + (+) CPU CSLEEP. + (+) CPU CSTOP. + (#) The domain low power modes are : + (+) DRUN. + (+) DSTOP. + (+) DSTANDBY. + (#) The SYSTEM low power modes are : + (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from + Standby. In Run* mode, the performance is limited and the + system supply configuration shall be programmed. The system + enters Run mode only when the ACTVOSRDY bit in PWR control + status register 1 (PWR_CSR1) is set to 1. + (+) RUN. + (+) STOP. + (+) STANDBY. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Power management peripheral is active by default at startup level in + STM32h7xx lines. + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RTC registers, RTC backup + data registers and backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Power Voltage Detector, + then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start + and stop the PVD detection. + (+) PVD level could be one of the following values : + (++) 1V95 + (++) 2V1 + (++) 2V25 + (++) 2V4 + (++) 2V55 + (++) 2V7 + (++) 2V85 + (++) External voltage level + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High) and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP + mode. Wake-up from SLEEP mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in SLEEP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 + mode for single core devices. For dual core devices, this API will enter + the domain (containing Cortex-Mx that executing this function) in DSTOP + mode. According to the used parameter, user could select the regulator to + be kept actif in low power mode and wake-up event type. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in CSTOP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + STANDBY mode for single core devices. For dual core devices, this API + will enter the domain (containing Cortex-Mx that executing this function) + in DSTANDBY mode. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-Mx re-entring in SLEEP mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-Mx to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt + request. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal + regulator output voltage. + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim ****************************************************************************** * @attention * @@ -38,6 +159,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /** @addtogroup PWR_Private_Constants PWR Private Constants * @{ */ @@ -46,12 +168,13 @@ * @{ */ #if !defined (DUAL_CORE) -#define PVD_MODE_IT ((uint32_t)0x00010000U) -#define PVD_MODE_EVT ((uint32_t)0x00020000U) -#endif /* DUAL_CORE */ -#define PVD_RISING_EDGE ((uint32_t)0x00000001U) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) -#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U) +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#endif /* !defined (DUAL_CORE) */ + +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +#define PVD_RISING_FALLING_EDGE (0x00000003U) /** * @} */ @@ -59,6 +182,7 @@ /** * @} */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -68,550 +192,666 @@ * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions - * @brief Initialization and De-Initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization functions * @verbatim =============================================================================== - ##### Initialization and De-Initialization functions ##### + ##### Initialization and De-Initialization Functions ##### =============================================================================== [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. @endverbatim * @{ */ /** - * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. * @note This functionality is not available in this product. - * The prototype is kept just to maintain compatibility with other products. - * @retval None + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. */ -void HAL_PWR_DeInit(void) +void HAL_PWR_DeInit (void) { } /** - * @brief Enable access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). + * @brief Enable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. - * @retval None + * @retval None. */ -void HAL_PWR_EnableBkUpAccess(void) +void HAL_PWR_EnableBkUpAccess (void) { /* Enable access to RTC and backup registers */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); + SET_BIT (PWR->CR1, PWR_CR1_DBP); } /** - * @brief Disable access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). + * @brief Disable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. - * @retval None + * @retval None. */ -void HAL_PWR_DisableBkUpAccess(void) +void HAL_PWR_DisableBkUpAccess (void) { /* Disable access to RTC and backup registers */ - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); + CLEAR_BIT (PWR->CR1, PWR_CR1_DBP); } - /** * @} */ -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Power Control functions * @verbatim - =============================================================================== - ##### Peripheral Control functions ##### + ##### Peripheral Control Functions ##### =============================================================================== + [..] + This section provides functions allowing to control power peripheral. *** PVD configuration *** ========================= [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 register). + threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 + register). + (+) A PVDO flag is available to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line 16 to generate an interrupt if enabled. It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. + + (+) The PVD is stopped in STANDBY mode. *** Wake-up pin configuration *** - ================================ + ================================= [..] - (+) Wake-up pin is used to wake up the system from Standby mode. - The pin pull is configurable through the WKUPEPR register to be in No pull-up, Pull-up and Pull-down. - The pin polarity is configurable through the WKUPEPR register to be active on rising or falling edges. + (+) Wake-up pin is used to wake up the system from STANDBY mode. + The pin pull is configurable through the WKUPEPR register to be in + No-pull, Pull-up and Pull-down. + The pin polarity is configurable through the WKUPEPR register to be + active on rising or falling edges. + (+) There are up to six Wake-up pin in the STM32H7 devices family. *** Low Power modes configuration *** ===================================== [..] The device present 3 principles low-power modes features: - (+) SLEEP mode: Cortex-M7 core stopped and D1, D2 and D3 peripherals kept running. - (+) STOP mode: all clocks are stopped and the regulator is running in main or low power mode. - (+) STANDBY mode: D1, D2 and D3 domains enter DSTANDBY mode and the VCORE supply - regulator is powered off. + (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining + active (Powered and Clocked). + + (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the + regulator is running. The Main regulator or the LP + regulator could be selected. + + (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. *** SLEEP mode *** ================== [..] (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry) - function. + The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + SLEEPEntry) function. - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction. -@@- The Regulator parameter is not used for the STM32H7 family and is kept as parameter just to maintain compatibility with the lower power families (STM32L). + (+) Exit: Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. + controller (NVIC) can wake up the device from SLEEP mode. *** STOP mode *** ================= [..] - In system Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. + In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL, + the HSI, and the HSE RC oscillators are disabled. Internal SRAM and + register contents are preserved. The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. - It can be switched on again by software after exiting the Stop mode using + To minimize the consumption in STOP mode, FLASH can be powered off before + entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the STOP mode using the HAL_PWREx_DisableFlashPowerDown() function. (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) - function with: + The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + STOPEntry) function with: + (++) Regulator: (+++) PWR_MAINREGULATOR_ON: Main regulator ON. (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + (++) STOPEntry: - (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction - (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction. + (+) Exit: - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. *** STANDBY mode *** ==================== [..] (+) - The system Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. - The system is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. + The system STANDBY mode allows to achieve the lowest power consumption. + It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator + disabled. The system is consequently powered off. The PLL, the HSI + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the RTC registers, RTC backup registers, + backup SRAM and standby circuitry. + [..] The voltage regulator is OFF. + (++) Entry: - (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + (++) Exit: - (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC - wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + RTC wakeup, tamper event, time stamp event, external reset in NRST + pin, IWDG reset. *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event or a time-stamp event, without depending on - an external interrupt (Auto-wakeup mode). + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + RTC Wakeup event, a tamper event or a time-stamp event, without + depending on an external interrupt (Auto-wakeup mode). + (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + + (++) To wake up from the STOP mode with an RTC alarm event, it is + necessary to configure the RTC to generate the RTC alarm using the + HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + it is necessary to configure the RTC to detect the tamper or time + stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the STOP mode with an RTC WakeUp event, it is + necessary to configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() function. @endverbatim * @{ */ /** - * @brief Configure the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. + * @brief Configure the event mode and the voltage threshold detected by the + * Programmable Voltage Detector(PVD). + * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains + * the configuration information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. - * @retval None + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. + * @retval None. */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { + /* Check the PVD configuration parameter */ + if (sConfigPVD == NULL) + { + return; + } + /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); + assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); - /* Clear any previous config */ + /* Clear previous config */ #if !defined (DUAL_CORE) - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); -#endif /* DUAL_CORE */ - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_PVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); #if !defined (DUAL_CORE) - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + /* Interrupt mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); + __HAL_PWR_PVD_EXTI_ENABLE_IT (); } - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + /* Event mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); } -#endif /* DUAL_CORE */ +#endif /* !defined (DUAL_CORE) */ - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + /* Rising edge configuration */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); } - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + /* Falling edge configuration */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); } } /** - * @brief Enable the Power Voltage Detector(PVD). - * @retval None + * @brief Enable the Programmable Voltage Detector (PVD). + * @retval None. */ -void HAL_PWR_EnablePVD(void) +void HAL_PWR_EnablePVD (void) { /* Enable the power voltage detector */ - SET_BIT(PWR->CR1, PWR_CR1_PVDEN); + SET_BIT (PWR->CR1, PWR_CR1_PVDEN); } /** - * @brief Disable the Power Voltage Detector(PVD). - * @retval None + * @brief Disable the Programmable Voltage Detector (PVD). + * @retval None. */ -void HAL_PWR_DisablePVD(void) +void HAL_PWR_DisablePVD (void) { /* Disable the power voltage detector */ - CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); + CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN); } /** * @brief Enable the WakeUp PINx functionality. - * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values, which sets the default: - * polarity detection on high level (rising edge): - * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, - * PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 or one of the following values where - * the user can explicitly states the enabled pin and the chosen polarity. - * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW - * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. - * @retval None + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity) { - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity)); - /* Enable and Specify the Wake-Up pin polarity and the pull configuration - for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity); + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity); } /** * @brief Disable the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3 - * @arg PWR_WAKEUP_PIN4 - * @arg PWR_WAKEUP_PIN5 - * @arg PWR_WAKEUP_PIN6 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - CLEAR_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); -} - -/** - * @brief Enter the current core to Sleep mode. - * @param Regulator: Specifies the regulator state in SLEEP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON - * @note This parameter is not used for the STM32H7 family and is kept as parameter - * just to maintain compatibility with the lower power families. - * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry */ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } -} - -/** - * @brief Enter the system to STOP mode. - * @note This API must be used only for single core devices. - * @note In System Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting System Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as default system wakeup clock. - * @note In System STOP mode, when the voltage regulator operates in low power mode, - * an additional startup delay is incurred when the system is waking up. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in Stop mode */ - tmpreg = PWR->CR1; - /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR1_LPDS); - - /* Set LPDS bit according to Regulator value */ - tmpreg |= Regulator; - - /* Store the new value */ - PWR->CR1 = tmpreg; - -#if defined(DUAL_CORE) - /* Keep DSTOP mode when D1 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); - CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1); -#else - /* Keep DSTOP mode when D1 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); - - /* Keep DSTOP mode when D2 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2); - - /* Keep DSTOP mode when D3 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3); -#endif /*DUAL_CORE*/ - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Ensure that all instructions done before entering STOP mode */ - __DSB(); - __ISB(); - - /* Select Stop mode entry */ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enter the system to STANDBY mode. - * @note The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby. - * @note When the System exit STANDBY mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, + * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. * @retval None. */ -void HAL_PWR_EnterSTANDBYMode(void) +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx) { -#if defined(DUAL_CORE) - /* Keep DSTANDBY mode when D1 domain enters Deepsleep */ - SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); - SET_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1); -#else - /* Keep DSTANDBY mode when D1 domain enters Deepsleep */ - SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx)); - /* Keep DSTANDBY mode when D2 domain enters Deepsleep */ - SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2); + /* Disable the wake up pin selected */ + CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); +} - /* Keep DSTANDBY mode when D3 domain enters Deepsleep */ - SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3); -#endif /*DUAL_CORE*/ +/** + * @brief Enter the current core in SLEEP mode (CSLEEP). + * @param Regulator : Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power + * regulator ON. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with the lower power + * families. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction. + * @note Ensure to clear pending events before calling this API through + * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } +} + +/** + * @brief Enter STOP mode. + * @note For single core devices, this API will enter the system in STOP mode + * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is + * cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTOP mode. If all + * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is + * cleared, all the system will enter in STOP mode. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + * @note When exiting System STOP mode by issuing an interrupt or a wakeup + * event, the HSI RC oscillator is selected as default system wakeup + * clock. + * @note In System STOP mode, when the voltage regulator operates in low + * power mode, an additional startup delay is incurred when the system + * is waking up. By keeping the internal regulator ON during STOP mode, + * the consumption is higher although the startup time is reduced. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in STOP mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + } + else + { + /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + } +#else /* Single core devices */ + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select STOP mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter STANDBY mode. + * @note For single core devices, this API will enter the system in STANDBY + * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR + * regiter is cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTANDBY mode. If all + * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register + * is cleared, all the system will enter in STANDBY mode. + * @note The system enters Standby mode only when all domains are in DSTANDBY. + * @note When the System exit STANDBY mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock. + * @note It is recommended to disable all regulators before entring STANDBY + * mode for power consumption saving purpose. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode (void) +{ + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3)); + } + else + { + /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3)); + } +#else /* Single core devices */ + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) +#if defined (__CC_ARM) __force_stores(); -#endif +#endif /* defined (__CC_ARM) */ + /* Request Wait For Interrupt */ - __WFI(); + __WFI (); } /** - * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None + * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. */ -void HAL_PWR_EnableSleepOnExit(void) +void HAL_PWR_EnableSleepOnExit (void) { - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); } - /** - * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. * @retval None */ -void HAL_PWR_DisableSleepOnExit(void) +void HAL_PWR_DisableSleepOnExit (void) { - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); } /** - * @brief Enable CORTEX SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None + * @brief Enable CORTEX SEVONPEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-Mx. + * @retval None. */ -void HAL_PWR_EnableSEVOnPend(void) +void HAL_PWR_EnableSEVOnPend (void) { - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + /* Set SEVONPEND bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); } /** - * @brief Disable CORTEX SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-Mx. + * @retval None. */ -void HAL_PWR_DisableSEVOnPend(void) +void HAL_PWR_DisableSEVOnPend (void) { /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); } +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions + * @brief Interrupt Handling functions + * +@verbatim + =============================================================================== + ##### Interrupt Handling Functions ##### + =============================================================================== + [..] + This section provides functions allowing to handle the PVD pending + interrupts. + +@endverbatim + * @{ + */ /** * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None. */ -void HAL_PWR_PVD_IRQHandler(void) +void HAL_PWR_PVD_IRQHandler (void) { -#if defined(DUAL_CORE) - /* PVD EXTI line interrupt detected */ - if (HAL_GetCurrentCPUID() == CM7_CPUID) +#if defined (DUAL_CORE) + /* Check Cortex-Mx ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) { - /* Check PWR EXTI flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + /* Check PWR EXTI D1 flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); + /* Clear PWR EXTI D1 pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); - /* Clear PWR EXTI pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); } } else { /* Check PWR EXTI D2 flag */ - if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET) + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - /* Clear PWR EXTI D2 pending bit */ - __HAL_PWR_PVD_EXTID2_CLEAR_FLAG(); + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); } } -#else +#else /* Single core devices */ /* PVD EXTI line interrupt detected */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - /* Clear PWR EXTI pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); } -#endif /*DUAL_CORE*/ +#endif /* defined (DUAL_CORE) */ } /** - * @brief PWR PVD interrupt callback - * @retval None + * @brief PWR PVD interrupt callback. + * @retval None. */ -__weak void HAL_PWR_PVDCallback(void) +__weak void HAL_PWR_PVDCallback (void) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file */ } diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c index df10518..e756454 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -6,7 +6,136 @@ * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: * + Peripheral Extended features functions - * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + with the following different setups according to hardware (support SMPS): + (+) PWR_DIRECT_SMPS_SUPPLY + (+) PWR_SMPS_1V8_SUPPLIES_LDO + (+) PWR_SMPS_2V5_SUPPLIES_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT + (+) PWR_SMPS_2V5_SUPPLIES_EXT + (+) PWR_LDO_SUPPLY + (+) PWR_EXTERNAL_SOURCE_SUPPLY + + (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + + (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + internal regulator output voltage. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_VOLTAGE_SCALE0 + (+) PWR_REGULATOR_VOLTAGE_SCALE1 + (+) PWR_REGULATOR_VOLTAGE_SCALE2 + (+) PWR_REGULATOR_VOLTAGE_SCALE3 + + (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + voltage applied to the main regulator. + + (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the + main internal regulator output voltage in STOP mode. The voltage scaling + in STOP mode could be one of the following scales : + (+) PWR_REGULATOR_SVOS_SCALE3 + (+) PWR_REGULATOR_SVOS_SCALE4 + (+) PWR_REGULATOR_SVOS_SCALE5 + + (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current + output voltage applied to the main regulator in STOP mode. + + (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode + with core domain in D2STOP mode. This API is used only for STM32H7Axxx + and STM32H7Bxxx devices. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in + DSTOP mode. Call this API with all available power domains to enter the + system in STOP mode. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the + Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry. + + (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain + in DSTANDBY mode. Call this API with all available power domains to enter + the system in STANDBY mode. + + (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state + (RUN/STOP) when the system enter to low power mode. + + (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the + selected power domain. This API is used only for dual core devices. + + (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold + and release the selected CPU and and their domain peripherals when + exiting STOP mode. These APIs are used only for dual core devices. + + (#) Call HAL_PWREx_EnableFlashPowerDown() and + HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the + Flash Power Down in STOP mode. + + (#) Call HAL_PWREx_EnableMemoryShutOff() and + HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the + memory block shut-off in DStop or DStop2. These APIs are used only for + STM32H7Axxx and STM32H7Bxxx lines. + + (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin() + functions to enable and disable the Wake-up pin functionality for + the selected pin. + + (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + functions to manage wake-up flag for the selected pin. + + (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions + to enable and disable the backup domain regulator. + + (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), + HAL_PWREx_EnableUSBVoltageDetector() and + HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power + regulation functionnalities. + + (#) Call HAL_PWREx_EnableBatteryCharging() and + HAL_PWREx_DisableBatteryCharging() functions to enable and disable the + battery charging feature with the selected resistor. + + (#) Call HAL_PWREx_EnableAnalogBooster() and + HAL_PWREx_DisableAnalogBooster() functions to enable and disable the + AVD boost feature when the VDD supply voltage is below 2V7. + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + functions to enable and disable the VBAT and Temperature monitoring. + When VBAT and Temperature monitoring feature is enables, use + HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + respectively the Temperature level and VBAT level. + + (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring() + function to get VDDMMC voltage level. This API is used only for + STM32H7Axxx and STM32H7Bxxx lines + + (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured + (event mode and voltage threshold) in order to set up the Analog Voltage + Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD() + functions to start and stop the AVD detection. + (+) AVD level could be one of the following values : + (++) 1V7 + (++) 2V1 + (++) 2V5 + (++) 2V8 + + (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and + AVD interrupt request. + + @endverbatim ****************************************************************************** * @attention * @@ -37,6 +166,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + /** @addtogroup PWREx_Private_Constants * @{ */ @@ -44,11 +174,11 @@ /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask * @{ */ -#define AVD_MODE_IT ((uint32_t)0x00010000U) -#define AVD_MODE_EVT ((uint32_t)0x00020000U) -#define AVD_RISING_EDGE ((uint32_t)0x00000001U) -#define AVD_FALLING_EDGE ((uint32_t)0x00000002U) -#define AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U) +#define AVD_MODE_IT (0x00010000U) +#define AVD_MODE_EVT (0x00020000U) +#define AVD_RISING_EDGE (0x00000001U) +#define AVD_FALLING_EDGE (0x00000002U) +#define AVD_RISING_FALLING_EDGE (0x00000003U) /** * @} */ @@ -56,7 +186,7 @@ /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value * @{ */ -#define PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U) +#define PWR_FLAG_SETTING_DELAY (1000U) /** * @} */ @@ -65,17 +195,21 @@ * @{ */ /* Wake-Up Pins EXTI register mask */ -#define PWR_EXTI_WAKEUP_PINS_MASK (uint32_t)(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 | \ - EXTI_IMR2_IM57 | EXTI_IMR2_IM58 | \ - EXTI_IMR2_IM59 | EXTI_IMR2_IM60) +#if defined (EXTI_IMR2_IM57) +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\ + EXTI_IMR2_IM59 | EXTI_IMR2_IM60) +#else +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM58 | EXTI_IMR2_IM60) +#endif /* defined (EXTI_IMR2_IM57) */ /* Wake-Up Pins PWR Pin Pull shift offsets */ -#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2U +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) /** * @} */ - /** * @} */ @@ -85,232 +219,286 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ - /* Exported functions --------------------------------------------------------*/ + /** @defgroup PWREx_Exported_Functions PWREx Exported Functions * @{ */ -/** @defgroup PWREx_Exported_Functions_Group1 Power supply control functions +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions * @brief Power supply control functions * @verbatim - =============================================================================== - ##### Power supply control functions ##### + ##### Power supply control functions ##### =============================================================================== - - *** Power supply configuration *** - ================================== [..] - When the system is powered on, the POR monitors VDD supply. Once VDD is above the - POR threshold level, the voltage regulator is enabled in the default supply - configuration: - (+) The Voltage converter output level is set at 1.0 V in accordance with the VOS3 - level configured in PWR D3 domain control register (PWR_D3CR). + (#) When the system is powered on, the POR monitors VDD supply. Once VDD is + above the POR threshold level, the voltage regulator is enabled in the + default supply configuration: + (+) The Voltage converter output level is set at 1V0 in accordance with + the VOS3 level configured in PWR (D3/SRD) domain control register + (PWR_D3CR/PWR_SRDCR). (+) The system is kept in reset mode as long as VCORE is not ok. - (+) Once VCORE is ok, the system is taken out of reset and the HSI oscillator is enabled. - (+) Once the oscillator is stable, the system is initialized: Flash memory and option - bytes are loaded and the CPU starts in Run* mode. - (+) The software shall then initialize the system including supply configuration - programming using the HAL_PWREx_ConfigSupply(SupplySource) with: - (++) SupplySource: - (+++) PWR_LDO_SUPPLY: VCORE Power Domains are supplied from the LDO according to - VOS. LDO power mode (Main, LP, Off) will follow system low-power - modes. - (+++) PWR_EXTERNAL_SOURCE_SUPPLY: VCORE supplied from external source and LDO bypassed, - voltage monitoring still active. - (+) Once the supply configuration has been configured, the HAL_PWREx_ConfigSupply - function checks the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) - to guarantee a valid voltage levels: - (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the system is in - limited Run* mode, write accesses to the RAMs are not permitted and VOS shall - not be changed. - (++) Once ACTVOSRDY indicates that voltage levels are valid, the system is in normal - Run mode, write accesses to RAMs are allowed and VOS can be changed. + (+) Once VCORE is ok, the system is taken out of reset and the HSI + oscillator is enabled. + (+) Once the oscillator is stable, the system is initialized: Flash memory + and option bytes are loaded and the CPU starts in Run* mode. + (+) The software shall then initialize the system including supply + configuration programming using the HAL_PWREx_ConfigSupply(). + (+) Once the supply configuration has been configured, the + HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR + control status register 1 (PWR_CSR1) to guarantee a valid voltage + levels: + (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the + system is in limited Run* mode, write accesses to the RAMs are not + permitted and VOS shall not be changed. + (++) Once ACTVOSRDY indicates that voltage levels are valid, the system + is in normal Run mode, write accesses to RAMs are allowed and VOS + can be changed. @endverbatim * @{ */ -#if defined(SMPS) /** - * @brief Configure the system Power Supply. - * @param SupplySource: Specifies the Power Supply source to set after a system startup. - * This parameter can be one of the following values: - * @arg PWR_LDO_SUPPLY The LDO regulator supplies the Vcore Power Domains. - * The SMPS regulator is Bypassed. - * - * @arg PWR_DIRECT_SMPS_SUPPLY The SMPS supplies the Vcore Power Domains. - * The LDO is Bypassed. - * - * @arg PWR_SMPS_1V8_SUPPLIES_LDO The SMPS 1.8V output supplies the LDO. - * The Vcore Power Domains are supplied from the LDO. - * - * @arg PWR_SMPS_2V5_SUPPLIES_LDO The SMPS 2.5V output supplies the LDO. - * The Vcore Power Domains are supplied from the LDO. - * - * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO The SMPS 1.8V output supplies external circuits and the LDO. - * The Vcore Power Domains are supplied from the LDO. - * - * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO The SMPS 2.5V output supplies external circuits and the LDO. - * The Vcore Power Domains are supplied from the LDO. - * - * @arg PWR_SMPS_1V8_SUPPLIES_EXT The SMPS 1.8V output supplies external circuits. - * The LDO is Bypassed. - * The Vcore Power Domains are supplied from external source. - * - * @arg PWR_SMPS_2V5_SUPPLIES_EXT The SMPS 2.5V output supplies external circuits. - * The LDO is Bypassed. - * The Vcore Power Domains are supplied from external source. - * - * @arg PWR_EXTERNAL_SOURCE_SUPPLY The SMPS and the LDO are Bypassed. - * The Vcore Power Domains are supplied from external source. + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power + * Domains. The LDO is Bypassed. + * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power + * Domains. The SMPS regulator is Bypassed. + * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all + * H7 lines. + * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, + * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, + * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and + * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS + * regulator. * @retval HAL status. */ -HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { uint32_t tickstart; /* Check the parameters */ - assert_param(IS_PWR_SUPPLY(SupplySource)); + assert_param (IS_PWR_SUPPLY (SupplySource)); - if((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) + /* Check if supply source was configured */ +#if defined (PWR_FLAG_SCUEN) + if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) +#else + if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) +#endif /* defined (PWR_FLAG_SCUEN) */ { - if((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + /* Check supply configuration */ + if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) { - /* Supply configuration update locked, can't apply a new regulator config */ + /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; } + else + { + /* Supply configuration update locked, but new supply configuration + matches with old supply configuration : nothing to do + */ + return HAL_OK; + } } /* Set the power supply configuration */ - MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); + MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick (); /* Wait till voltage level flag is set */ - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY)) + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } +#if defined (SMPS) /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ - if((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || - (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || - (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || - (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) + if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get the current tick number */ + tickstart = HAL_GetTick (); /* Wait till SMPS external supply ready flag is set */ - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_SMPSEXTRDY)) + while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } } +#endif /* defined (SMPS) */ return HAL_OK; } -#else -/** - * @brief Configure the system Power Supply. - * @param SupplySource: Specifies the Power Supply source to set after a system startup. - * This parameter can be one of the following values: - * @arg PWR_LDO_SUPPLY The LDO regulator supplies the Vcore Power Domains. - * - * @arg PWR_EXTERNAL_SOURCE_SUPPLY The LDO regulator is Bypassed. - * The Vcore Power Domains are supplied from external source. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_PWR_SUPPLY(SupplySource)); - - if(!__HAL_PWR_GET_FLAG(PWR_FLAG_SCUEN)) - { - if((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) - { - /* Supply configuration update locked, can't apply a new regulator config */ - return HAL_ERROR; - } - } - - /* Set the power supply configuration */ - MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till voltage level flag is set */ - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} -#endif /*SMPS*/ - /** - * @brief Get the power supply configuration. + * @brief Get the power supply configuration. * @retval The supply configuration. */ -uint32_t HAL_PWREx_GetSupplyConfig(void) +uint32_t HAL_PWREx_GetSupplyConfig (void) { return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK); } /** - * @brief Configure the main internal regulator output voltage. - * @param VoltageScaling: Specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode. - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode. - * @note When moving from Range 1 to Range 2, the system frequency must be decreased - * before calling HAL_PWREx_ControlVoltageScaling() API. - * When moving from Range 2 to Range 1, the system frequency can be increased - * after calling HAL_PWREx_ControlVoltageScaling() API. - * @note When moving from a Range to an other one, the API waits for VOSRDY flag to be - * set before returning the status. If the flag is not set within 1000 microseconds, - * HAL_TIMEOUT status is reported. + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * range 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * range 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * range 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0. + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. * @retval HAL Status */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling) { uint32_t tickstart; - assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling)); + /* Get the voltage scaling */ + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling) + { + /* Old and new voltage scaling configuration match : nothing to do */ + return HAL_OK; + } + +#if defined (PWR_SRDCR_VOS) + /* Set the voltage range */ + MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#else +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0) + { + if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN) + { + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + /* Enable the PWR overdrive */ + SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + } + else + { + /* The voltage scale 0 is only possible when LDO regulator is enabled */ + return HAL_ERROR; + } + } + else + { + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1) + { + if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U) + { + /* Disable the PWR overdrive */ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } + } + + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); + } +#else /* STM32H72xxx and STM32H73xxx lines */ /* Set the voltage range */ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick (); - /* Wait until the VOSRDY flag is set */ - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } @@ -318,494 +506,648 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) } /** - * @brief Get the main internal regulator output voltage. - * Reflecting the last VOS value applied to the PMU. - * @retval The actual applied VOS for VDD11 Voltage Scaling selection. + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. */ -uint32_t HAL_PWREx_GetVoltageRange(void) +uint32_t HAL_PWREx_GetVoltageRange (void) { + /* Get the active voltage scaling */ return (PWR->CSR1 & PWR_CSR1_ACTVOS); } /** - * @brief Configure the main internal regulator output voltage in STOP mode. - * @param VoltageScaling: Specifies the regulator output voltage when the system enters - * Stop mode to achieve a tradeoff between performance and power consumption. + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. * This parameter can be one of the following values: - * @arg PWR_REGULATOR_SVOS_SCALE3: Regulator voltage output range 3 mode. - * @arg PWR_REGULATOR_SVOS_SCALE4: Regulator voltage output range 4 mode. - * @arg PWR_REGULATOR_SVOS_SCALE5: Regulator voltage output range 5 mode. - * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage regulator - * in Low-power (LP) mode to further reduce power consumption. - * When preselecting SVOS3, the use of the voltage regulator low-power mode (LP) - * can be selected by LPDS register bit. - * @note The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting - * from system Stop mode. - * @retval HAL Status + * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range + * 3 mode. + * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range + * 4 mode. + * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range + * 5 mode. + * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage + * regulator in Low-power (LP) mode to further reduce power consumption. + * When preselecting SVOS3, the use of the voltage regulator low-power + * mode (LP) can be selected by LPDS register bit. + * @note The selected SVOS4 and SVOS5 levels add an additional startup delay + * when exiting from system Stop mode. + * @retval HAL Status. */ -HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling) +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling) { - assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling)); + /* Check the parameters */ + assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling)); - /* Set the stop mode voltage range */ - MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); + /* Return the stop mode voltage range */ + MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling); return HAL_OK; } /** - * @brief Get the main internal regulator output voltage in STOP mode. - * @retval The actual applied VOS for VDD11 Voltage Scaling selection. + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied VOS selection. */ -uint32_t HAL_PWREx_GetStopModeVoltageRange(void) +uint32_t HAL_PWREx_GetStopModeVoltageRange (void) { + /* Return the stop voltage scaling */ return (PWR->CR1 & PWR_CR1_SVOS); } - /** * @} */ -/** @defgroup PWREx_Exported_Functions_Group2 Low power control functions +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions * @brief Low power control functions * @verbatim - =============================================================================== - ##### Low power control functions ##### + ##### Low power control functions ##### =============================================================================== *** Domains Low Power modes configuration *** ============================================= [..] - The system present 3 principles domains (D1, D2 and D3) that can be operated - in low-power modes (DSTOP or DSTANDBY mode): + This section provides the extended low power mode control APIs. + The system presents 3 principles domains (D1, D2 and D3) that can be + operated in low-power modes (DSTOP or DSTANDBY mode): (+) DSTOP mode to enters a domain to STOP mode: (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU - subsystem is in CSTOP mode and has allocated peripheral in the domain. + subsystem is in CSTOP mode and has allocated peripheral in the + domain. In DSTOP mode the domain bus matrix clock is stopped. (++) The system enters STOP mode using one of the following scenarios: - (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains enter DSTOP mode. - (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains enter DSTOP mode. - (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains enter DSTOP mode. - (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain enters DSTOP mode. - (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain enters DSTOP mode. - (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain enters DSTOP mode. + (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains + enter DSTOP mode. + (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains + enter DSTOP mode. + (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains + enter DSTOP mode. + (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain + enters DSTOP mode. + (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain + enters DSTOP mode. + (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain + enters DSTOP mode. (+++) D1, D2 and D3 domains enter DSTOP mode. - (++) When the system enters STOP mode, the clocks are stopped and the regulator is running - in main or low power mode. - (++) D3 domain can be kept in Run mode regardless of the CPU status when enter - STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function. + (++) When the system enters STOP mode, the clocks are stopped and the + regulator is running in main or low power mode. + (++) D3 domain can be kept in Run mode regardless of the CPU status when + enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function. (+) DSTANDBY mode to enters a domain to STANDBY mode: - (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control register - (PWR_CPUCR) for the Dn domain selects Standby mode. - (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter DSTANDBY mode. - Consequently the VCORE supply regulator is powered off. + (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control + register (PWR_CPUCR) for the Dn domain selects Standby mode. + (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter + DSTANDBY mode. Consequently the VCORE supply regulator is powered + off. *** DSTOP mode *** ================== [..] In DStop mode the domain bus matrix clock is stopped. - The Flash memory can enter low-power Stop mode when it is enabled through FLPS in - PWR_CR1 register. This allows a trade-off between domain DStop restart time and low - power consumption. + The Flash memory can enter low-power Stop mode when it is enabled through + FLPS in PWR_CR1 register. This allows a trade-off between domain DStop + restart time and low power consumption. [..] - In DStop mode domain peripherals using the LSI or LSE clock and peripherals having a - kernel clock request are still able to operate. + In DStop mode domain peripherals using the LSI or LSE clock and + peripherals having a kernel clock request are still able to operate. [..] - Before entering DSTOP mode it is recommended to call SCB_CleanDCache function - in order to clean the D-Cache and guarantee the data integrity for the SRAM memories. + Before entering DSTOP mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. (+) Entry: - The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, STOPEntry, Domain) - function with: + The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, + STOPEntry, Domain) function with: (++) Regulator: - (+++) PWR_MAINREGULATOR_ON: Main regulator ON. - (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + (+++) PWR_MAINREGULATOR_ON : Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON. (++) STOPEntry: - (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction - (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction + (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction (++) Domain: - (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTOP mode. - (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTOP mode. - (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTOP mode. + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode. (+) Exit: Any EXTI Line (Internal or External) configured in Interrupt/Event mode. *** DSTANDBY mode *** - ==================== + ===================== [..] In DStandby mode: (+) The domain bus matrix clock is stopped. - (+) The domain is powered down and the domain RAM and register contents are lost. + (+) The domain is powered down and the domain RAM and register contents + are lost. [..] - Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function - in order to clean the D-Cache and guarantee the data integrity for the SRAM memories. + Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. (+) Entry: - The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode(Domain) function with: + The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode + (Domain) function with: (++) Domain: - (+++) PWR_D1_DOMAIN: Enters D1 domain to DSTANDBY mode. - (+++) PWR_D2_DOMAIN: Enters D2 domain to DSTANDBY mode. - (+++) PWR_D3_DOMAIN: Enters D3 domain to DSTANDBY mode. + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode. (+) Exit: WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC - wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. + wakeup, tamper event, time stamp event, external reset in NRST pin, + IWDG reset. - *** Keep D3 in RUN mode *** - =========================== + *** Keep D3/SRD in RUN mode *** + =============================== [..] - D3 domain can be kept in Run mode regardless of the CPU status when enter - STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function with: + D3/SRD domain can be kept in Run mode regardless of the CPU status when + entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function + with : (+) D3State: - (++) PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode. - (++) PWR_D3_DOMAIN_RUN: D3 domain remains in Run mode regardless of CPU subsystem mode. + (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system + mode. + (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless + of CPU subsystem mode. *** FLASH Power Down configuration **** ======================================= [..] - By setting the FLPS bit in the PWR_CR1 register using the HAL_PWREx_EnableFlashPowerDown() - function, the Flash memory also enters power down mode when the device enters Stop mode. - When the Flash memory is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. + By setting the FLPS bit in the PWR_CR1 register using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters + power down mode when the device enters STOP mode. When the Flash memory is + in power down mode, an additional startup delay is incurred when waking up + from STOP mode. *** Wakeup Pins configuration **** =================================== [..] - Wakeup pins allow the system to exit from Standby mode. The configuration of - wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) function with: + Wakeup pins allow the system to exit from Standby mode. The configuration + of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + function with: (+) sPinParams: structure to enable and configure a wakeup pin: (++) WakeUpPin: Wakeup pin to be enabled. (++) PinPolarity: Wakeup pin polarity (rising or falling edge). (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). [..] - The wakeup pins are internally connected to the EXTI lines [55-60] to generate an interrupt - if enabled. The EXTI lines configuration is done by the HAL_EXTI_Dx_EventInputConfig() functions - defined in the stm32h7xxhal.c file. + The wakeup pins are internally connected to the EXTI lines [55-60] to + generate an interrupt if enabled. The EXTI lines configuration is done by + the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c + file. [..] - When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is called - and the appropriate flag is set in the PWR_WKUPFR register. Then in the HAL_PWREx_WAKEUP_PIN_IRQHandler - function the wakeup pin flag will be cleared and the appropriate user callback will be called. - The user can add his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. + When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is + called and the appropriate flag is set in the PWR_WKUPFR register. Then in + the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + cleared and the appropriate user callback will be called. The user can add + his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. @endverbatim * @{ */ +#if defined (PWR_CPUCR_RETDS_CD) /** - * @brief Enter a Domain to DSTOP mode. - * @note In DStop mode the domain bus matrix clock is stopped. - * @note The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode, - * the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU - * control register (PWR_CPUCR) for any domain request Stop. - * @note In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or - * DStandby mode. - * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache function - * in order to clean the D-Cache and guarantee the data integrity for the SRAM memories. - * @note In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the - * peripherals that have a kernel clock request to select HSI or CSI as source, - * are still able to operate. - * @param Regulator: Specifies the regulator state in Stop mode. + * @brief Enter the system to STOP mode with main domain in DSTOP2. + * @note In STOP mode, the domain bus matrix clock is stalled. + * @note In STOP mode, memories and registers are maintained and peripherals + * in CPU domain are no longer operational. + * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the + * HSE oscillators are disabled. Only Peripherals that have wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. In + * this case the HSI clock is propagated only to the peripheral + * requesting it. + * @note When exiting STOP mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in + * RCC_CFGR register is set. + * @param Regulator : Specifies the regulator state in STOP mode. * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction - * @param Domain: Specifies the Domain to enter STOP mode. - * This parameter can be one of the following values: - * @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode. - * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode. - * @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode. - * @retval None + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @retval None. */ -void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain) +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - assert_param(IS_PWR_DOMAIN(Domain)); + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); /* Select the regulator state in Stop mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, Regulator); + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); - /* Select the domain Power Down DeepSleep */ - if (Domain == PWR_D1_DOMAIN) + /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD); + + /* Keep DSTOP mode when SmartRun domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __ISB (); + __DSB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) { - /* Check Core */ - assert_param(IS_PWR_D1_CPU(HAL_GetCurrentCPUID())); - - /* Keep DSTOP mode when D1 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1); - -#if defined(DUAL_CORE) - CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1); -#endif /*DUAL_CORE*/ - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Ensure that all instructions done before entering STOP mode */ - __DSB(); - __ISB(); - - /* Select Stop mode entry */ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - } - else if (Domain == PWR_D2_DOMAIN) - { - /* Keep DSTOP mode when D2 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2); - -#if defined(DUAL_CORE) - /* Check Core */ - assert_param(IS_PWR_D2_CPU(HAL_GetCurrentCPUID())); - - CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Ensure that all instructions done before entering STOP mode */ - __DSB(); - __ISB(); - - /* Select Stop mode entry */ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -#endif /*DUAL_CORE*/ + /* Request Wait For Interrupt */ + __WFI (); } else { - /* Keep DSTOP mode when D3 domain enters Deepsleep */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3); - -#if defined(DUAL_CORE) - CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); -#endif /*DUAL_CORE*/ + /* Request Wait For Event */ + __WFE (); } -} + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} +#endif /* defined (PWR_CPUCR_RETDS_CD) */ /** - * @brief Clear pending event. - * @note This API clear the pending event in order to enter a given domain to DSTOP. It should - * be called just before enter low power mode APIs using Wait For Event request. - * @retval None - */ -void HAL_PWREx_ClearPendingEvent(void) -{ -#if defined(DUAL_CORE) - /* Check Core */ - if(HAL_GetCurrentCPUID() == CM7_CPUID) - { - __WFE(); - } - else - { - __SEV(); - __WFE(); - } -#else - __WFE(); -#endif /*DUAL_CORE*/ - -} - -/** - * @brief Enter a Domain to DSTANDBY mode. - * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain - * select Standby mode. When the system enters Standby mode, the voltage regulator - * is disabled. - * @note When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn - * bit to select Stop mode, the domain remains in DStandby mode. The domain will only - * exit DStandby when the CPU allocates a peripheral in the domain. - * @note The system D3 domain enters Standby mode only when the D1 and D2 domain are in - * DStandby. - * @note Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function - * in order to clean the D-Cache and guarantee the data integrity for the SRAM memories. - * @param Domain: Specifies the Domain to enter to STANDBY mode. + * @brief Enter a Domain to DSTOP mode. + * @note This API gives flexibility to manage independently each domain STOP + * mode. For dual core lines, this API should be executed with the + * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is + * executed by all available Cortex-Mx, the system enter to STOP mode. + * For single core lines, calling this API with domain parameter set to + * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode + * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the + * CPUCR_RUN_D3 is cleared. + * @note In DStop mode the domain bus matrix clock is stopped. + * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem + * is in CStop mode, the EXTI wakeup sources are inactive and at least + * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for + * any domain request Stop. + * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache + * function in order to clean the D-Cache and guarantee the data + * integrity for the SRAM memories. + * @note In System Stop mode, the domain peripherals that use the LSI or LSE + * clock, and the peripherals that have a kernel clock request to + * select HSI or CSI as source, are still able to operate. + * @param Regulator : Specifies the regulator state in STOP mode. * This parameter can be one of the following values: - * @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode. - * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode. - * @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode. - * @retval None + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @param Domain : Specifies the Domain to enter in DSTOP mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode. + * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode. + * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode. + * @retval None. */ -void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain) +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain) { /* Check the parameters */ - assert_param(IS_PWR_DOMAIN(Domain)); + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); /* Select the domain Power Down DeepSleep */ if (Domain == PWR_D1_DOMAIN) { - /* Check Core */ - assert_param(IS_PWR_D1_CPU(HAL_GetCurrentCPUID())); +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ - /* Allow DSTANDBY mode when D1 domain enters Deepsleep */ - SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1); + /* Keep DSTOP mode when D1/CD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1); -#if defined(DUAL_CORE) - SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } + + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +#else + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + } + else + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); + } +#else + /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Clear pending event. + * @note This API clears the pending event in order to enter a given CPU + * to CSLEEP or CSTOP. It should be called just before APIs performing + * enter low power mode using Wait For Event request. + * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ClearPendingEvent (void) +{ +#if defined (DUAL_CORE) + /* Check the current Core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + __WFE (); + } + else + { + __SEV (); + __WFE (); + } +#else + __WFE (); +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief Enter a Domain to DSTANDBY mode. + * @note This API gives flexibility to manage independently each domain + * STANDBY mode. For dual core lines, this API should be executed with + * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When + * it is executed by all available Cortex-Mx, the system enter STANDBY + * mode. + * For single core lines, calling this API with D1/SRD the selected + * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 + * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1. + * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for + * the Dn domain select Standby mode. When the system enters Standby + * mode, the voltage regulator is disabled. + * @note When D2 or D3 domain is in DStandby mode and the CPU sets the + * domain PDDS_Dn bit to select Stop mode, the domain remains in + * DStandby mode. The domain will only exit DStandby when the CPU + * allocates a peripheral in the domain. + * @note The system D3/SRD domain enters Standby mode only when the D1 and D2 + * domain are in DStandby. + * @note Before entering DSTANDBY mode it is recommended to call + * SCB_CleanDCache function in order to clean the D-Cache and guarantee + * the data integrity for the SRAM memories. + * @param Domain : Specifies the Domain to enter to STANDBY mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode. + * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode. + * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode. + * @retval None + */ +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); #endif /*DUAL_CORE*/ /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ /* Request Wait For Interrupt */ - __WFI(); + __WFI (); } +#if defined (PWR_CPUCR_PDDS_D2) else if (Domain == PWR_D2_DOMAIN) { /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ - SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D2); + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2); -#if defined(DUAL_CORE) - /* Check Core */ - assert_param(IS_PWR_D2_CPU(HAL_GetCurrentCPUID())); +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } - SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ /* Request Wait For Interrupt */ - __WFI(); -#endif /*DUAL_CORE*/ + __WFI (); +#endif /* defined (DUAL_CORE) */ } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ else { - /* Allow DSTANDBY mode when D3 domain enters Deepsleep */ - SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D3); + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); -#if defined(DUAL_CORE) - SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3); -#endif /*DUAL_CORE*/ +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ } } /** - * @brief Configure the D3 Domain state when the CPU is in low power mode. - * @param D3State: Specifies the D3 state. - * This parameter can be one of the following values: - * @arg PWR_D3_DOMAIN_STOP: D3 domain will follow the CPU sub-system mode. - * @arg PWR_D3_DOMAIN_RUN : D3 domain will stay in RUN mode regardless of the - * CPU sub-system mode. + * @brief Configure the D3/SRD Domain state when the System in low power mode. + * @param D3State : Specifies the D3/SRD state. + * This parameter can be one of the following values : + * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep + * CPU sub-system low power mode. + * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode + * regardless of the CPU sub-system low + * power mode. * @retval None */ -void HAL_PWREx_ConfigD3Domain(uint32_t D3State) +void HAL_PWREx_ConfigD3Domain (uint32_t D3State) { - /* Check the parameters */ - assert_param(IS_D3_STATE(D3State)); + /* Check the parameter */ + assert_param (IS_D3_STATE (D3State)); - /* Keep D3 in run mode */ - MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); -#if defined(DUAL_CORE) - MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_RUN_D3, D3State); -#endif /*DUAL_CORE*/ + /* Keep D3/SRD in run mode */ + MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); } -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) /** - * @brief Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a given domain. - * @param DomainFlags: Specifies the Domain flags to be cleared. + * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a + * given domain. + * @param DomainFlags : Specifies the Domain flags to be cleared. * This parameter can be one of the following values: - * @arg PWR_D1_DOMAIN_FLAGS: Clear D1 Domain flags. - * @arg PWR_D2_DOMAIN_FLAGS: Clear D2 Domain flags. + * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags. + * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags. + * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags. * @retval None. */ -void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags) +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags) { - /* Check the parameters */ - assert_param(IS_PWR_DOMAIN_FLAG(DomainFlags)); + /* Check the parameter */ + assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags)); + /* D1 CPU flags */ if (DomainFlags == PWR_D1_DOMAIN_FLAGS) { /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ - SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + } + /* D2 CPU flags */ + else if (DomainFlags == PWR_D2_DOMAIN_FLAGS) + { + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); } else { - /* Clear D2 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ - SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); } } -#endif /*DUAL_CORE*/ -#if defined(DUAL_CORE) /** - * @brief Hold the CPU and their allocated peripherals when exiting from STOP mode. - * @param CPU: Specifies the core to be held. - * This parameter can be one of the following values: + * @brief Hold the CPU and their domain peripherals when exiting STOP mode. + * @param CPU : Specifies the core to be held. + * This parameter can be one of the following values: * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master. * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master. * @retval HAL status */ -HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU) +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_PWR_CORE(CPU)); + assert_param (IS_PWR_CORE (CPU)); - if (PWR_CORE_CPU2 == CPU) + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) { /* If CPU1 is not held */ - if(PWR_CPU2CR_HOLD1 != (PWR->CPU2CR & PWR_CPU2CR_HOLD1)) + if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1) { /* Set HOLD2 bit */ - SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); - } - else - { - status = HAL_ERROR; - } - } - else if (PWR_CORE_CPU1 == CPU) - { - /* If CPU2 is not held */ - if(PWR_CPUCR_HOLD2 != (PWR->CPUCR & PWR_CPUCR_HOLD2)) - { - /* Set HOLD1 bit */ - SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); + SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); } else { @@ -814,77 +1156,160 @@ HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU) } else { - status = HAL_ERROR; + /* If CPU2 is not held */ + if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2) + { + /* Set HOLD1 bit */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } + else + { + status = HAL_ERROR; + } } return status; } -#endif /*DUAL_CORE*/ - -#if defined(DUAL_CORE) /** - * @brief Release the CPU and their allocated peripherals after a wake-up from STOP mode. + * @brief Release the CPU and their domain peripherals after a wake-up from + * STOP mode. * @param CPU: Specifies the core to be released. * This parameter can be one of the following values: - * @arg PWR_CORE_CPU1: Release the CPU1 and their allocated peripherals from holding. - * @arg PWR_CORE_CPU2: Release the CPU2 and their allocated peripherals from holding. + * @arg PWR_CORE_CPU1: Release the CPU1 and their domain + * peripherals from holding. + * @arg PWR_CORE_CPU2: Release the CPU2 and their domain + * peripherals from holding. * @retval None */ -void HAL_PWREx_ReleaseCore(uint32_t CPU) +void HAL_PWREx_ReleaseCore (uint32_t CPU) { /* Check the parameters */ - assert_param(IS_PWR_CORE(CPU)); + assert_param (IS_PWR_CORE (CPU)); - if (PWR_CORE_CPU2 == CPU) + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) { /* Reset HOLD2 bit */ - CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); } else { /* Reset HOLD1 bit */ - CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); } } -#endif /*DUAL_CORE*/ +#endif /* defined (DUAL_CORE) */ + /** - * @brief Enable the Flash Power Down in Stop mode. - * @retval None + * @brief Enable the Flash Power Down in Stop mode. + * @note When Flash Power Down is enabled the Flash memory enters low-power + * mode when D1/SRD domain is in DStop mode. This feature allows to + * obtain the best trade-off between low-power consumption and restart + * time when exiting from DStop mode. + * @retval None. */ -void HAL_PWREx_EnableFlashPowerDown(void) +void HAL_PWREx_EnableFlashPowerDown (void) { /* Enable the Flash Power Down */ - SET_BIT(PWR->CR1, PWR_CR1_FLPS); + SET_BIT (PWR->CR1, PWR_CR1_FLPS); } /** - * @brief Disable the Flash Power Down in Stop mode. - * @retval None + * @brief Disable the Flash Power Down in Stop mode. + * @note When Flash Power Down is disabled the Flash memory is kept on + * normal mode when D1/SRD domain is in DStop mode. This feature allows + * to obtain the best trade-off between low-power consumption and + * restart time when exiting from DStop mode. + * @retval None. */ -void HAL_PWREx_DisableFlashPowerDown(void) +void HAL_PWREx_DisableFlashPowerDown (void) { /* Disable the Flash Power Down */ - CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); + CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable memory block shut-off in DStop or DStop2 modes + * @note In DStop or DStop2 mode, the content of the memory blocks is + * maintained. Further power optimization can be obtained by switching + * off some memory blocks. This optimization implies loss of the memory + * content. The user can select which memory is discarded during STOP + * mode by means of xxSO bits. + * @param MemoryBlock : Specifies the memory block to shut-off during DStop or + * DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Enable memory block shut-off */ + SET_BIT (PWR->CR1, MemoryBlock); } /** - * @brief Enable the Wake-up PINx functionality. - * @param sPinParams: pointer to an PWREx_WakeupPinTypeDef structure that contains - * the configuration informations for the wake-up Pin. - * @retval None + * @brief Disable memory block shut-off in DStop or DStop2 modes + * @param MemoryBlock : Specifies the memory block to keep content during + * DStop or DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. */ -void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams) +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Disable memory block shut-off */ + CLEAR_BIT (PWR->CR1, MemoryBlock); +} +#endif /* defined (PWR_CR1_SRDRAMSO) */ + +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx. All combination are allowed: wake up only + * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and + * Cortex-M4. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) { uint32_t pinConfig; uint32_t regMask; const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin)); - assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity)); - assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull)); + assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin)); + assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity)); + assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull)); pinConfig = sPinParams->WakeUpPin | \ (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \ @@ -896,74 +1321,87 @@ void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams) /* Enable and Specify the Wake-Up pin polarity and the pull configuration for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig); + MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig); #ifndef DUAL_CORE /* Configure the Wakeup Pin EXTI Line */ - MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)); -#endif + MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)); +#endif /* !DUAL_CORE */ } /** * @brief Disable the Wake-up PINx functionality. - * @param WakeUpPin: Specifies the Wake-Up pin to be disabled. + * @param WakeUpPin : Specifies the Wake-Up pin to be disabled. * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1: Disable PA0 wake-up PIN. - * @arg PWR_WAKEUP_PIN2: Disable PA2 wake-up PIN.. - * @arg PWR_WAKEUP_PIN3: Disable PI8 wake-up PIN.. - * @arg PWR_WAKEUP_PIN4: Disable PC13 wake-up PIN.. - * @arg PWR_WAKEUP_PIN5: Disable PI11 wake-up PIN.. - * @arg PWR_WAKEUP_PIN6: Disable PC1 wake-up PIN.. + * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN. + * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN. + * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN. + * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN. + * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN. + * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN. + * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for + * devices that support GPIOI port. * @retval None */ -void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin) +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin) { - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin)); /* Disable the WakeUpPin */ - CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); + CLEAR_BIT (PWR->WKUPEPR, WakeUpPin); } /** - * @brief Get the Wake-Up Pin flag. - * @param WakeUpFlag: Specifies the Wake-Up PIN flag to check. + * @brief Get the Wake-Up Pin pending flags. + * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. * This parameter can be one of the following values: - * @arg PWR_WAKEUP_FLAG1: A wakeup event was received from PA0. - * @arg PWR_WAKEUP_FLAG2: A wakeup event was received from PA2. - * @arg PWR_WAKEUP_FLAG3: A wakeup event was received from PC1. - * @arg PWR_WAKEUP_FLAG4: A wakeup event was received from PC13. - * @arg PWR_WAKEUP_FLAG5: A wakeup event was received from PI8. - * @arg PWR_WAKEUP_FLAG6: A wakeup event was received from PI11. + * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all + * wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. * @retval The Wake-Up pin flag. */ -uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag) +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag) { /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag)); + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + /* Return the wake up pin flag */ return (PWR->WKUPFR & WakeUpFlag); } /** - * @brief Clear the Wake-Up pin flag. + * @brief Clear the Wake-Up pin pending flag. * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. * This parameter can be one of the following values: - * @arg PWR_WAKEUP_FLAG1: Clear the wakeup event received from PA0. - * @arg PWR_WAKEUP_FLAG2: Clear the wakeup event received from PA2. - * @arg PWR_WAKEUP_FLAG3: Clear the wakeup event received from PC1. - * @arg PWR_WAKEUP_FLAG4: Clear the wakeup event received from PC13. - * @arg PWR_WAKEUP_FLAG5: Clear the wakeup event received from PI8. - * @arg PWR_WAKEUP_FLAG6: Clear the wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from + * all wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. * @retval HAL status. */ -HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag) +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag) { - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_FLAG(WakeUpFlag)); + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); - SET_BIT(PWR->WKUPCR, WakeUpFlag); + /* Clear the wake up event received from wake up pin x */ + SET_BIT (PWR->WKUPCR, WakeUpFlag); - if((PWR->WKUPFR & WakeUpFlag) != 0U) + /* Check if the wake up event is well cleared */ + if ((PWR->WKUPFR & WakeUpFlag) != 0U) { return HAL_ERROR; } @@ -972,129 +1410,136 @@ HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag) } /** - * @brief This function handles the PWR WAKEUP PIN interrupt request. + * @brief This function handles the PWR WAKEUP PIN interrupt request. * @note This API should be called under the WAKEUP_PIN_IRQHandler(). - * @retval None + * @retval None. */ -void HAL_PWREx_WAKEUP_PIN_IRQHandler(void) +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void) { /* Wakeup pin EXTI line interrupt detected */ - if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) { /* Clear PWR WKUPF1 flag */ - SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1); /* PWR WKUP1 interrupt user callback */ - HAL_PWREx_WKUP1_Callback(); + HAL_PWREx_WKUP1_Callback (); } - else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) { /* Clear PWR WKUPF2 flag */ - SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2); /* PWR WKUP2 interrupt user callback */ - HAL_PWREx_WKUP2_Callback(); + HAL_PWREx_WKUP2_Callback (); } - else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) +#if defined (PWR_WKUPFR_WKUPF3) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) { /* Clear PWR WKUPF3 flag */ - SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3); /* PWR WKUP3 interrupt user callback */ - HAL_PWREx_WKUP3_Callback(); + HAL_PWREx_WKUP3_Callback (); } - else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) { /* Clear PWR WKUPF4 flag */ - SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4); /* PWR WKUP4 interrupt user callback */ - HAL_PWREx_WKUP4_Callback(); + HAL_PWREx_WKUP4_Callback (); } - else if(READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U) +#if defined (PWR_WKUPFR_WKUPF5) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U) { /* Clear PWR WKUPF5 flag */ - SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5); /* PWR WKUP5 interrupt user callback */ - HAL_PWREx_WKUP5_Callback(); + HAL_PWREx_WKUP5_Callback (); } +#endif /* defined (PWR_WKUPFR_WKUPF5) */ else { /* Clear PWR WKUPF6 flag */ - SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6); /* PWR WKUP6 interrupt user callback */ - HAL_PWREx_WKUP6_Callback(); + HAL_PWREx_WKUP6_Callback (); } } /** - * @brief PWR WKUP1 interrupt callback - * @retval None + * @brief PWR WKUP1 interrupt callback. + * @retval None. */ -__weak void HAL_PWREx_WKUP1_Callback(void) +__weak void HAL_PWREx_WKUP1_Callback (void) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_WKUP1Callback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP1Callback can be implemented in the user file */ } /** - * @brief PWR WKUP2 interrupt callback - * @retval None + * @brief PWR WKUP2 interrupt callback. + * @retval None. */ -__weak void HAL_PWREx_WKUP2_Callback(void) +__weak void HAL_PWREx_WKUP2_Callback (void) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_WKUP2Callback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP2Callback can be implemented in the user file */ } +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP3_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP3Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + /** - * @brief PWR WKUP3 interrupt callback - * @retval None + * @brief PWR WKUP4 interrupt callback. + * @retval None. */ -__weak void HAL_PWREx_WKUP3_Callback(void) +__weak void HAL_PWREx_WKUP4_Callback (void) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_WKUP3Callback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP4Callback can be implemented in the user file */ } +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief PWR WKUP5 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP5_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP5Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + /** - * @brief PWR WKUP4 interrupt callback - * @retval None + * @brief PWR WKUP6 interrupt callback. + * @retval None. */ -__weak void HAL_PWREx_WKUP4_Callback(void) +__weak void HAL_PWREx_WKUP6_Callback (void) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_WKUP4Callback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP6Callback can be implemented in the user file */ } - -/** - * @brief PWR WKUP5 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_WKUP5_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_WKUP5Callback could be implemented in the user file - */ -} - -/** - * @brief PWR WKUP6 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_WKUP6_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWREx_WKUP6Callback could be implemented in the user file - */ -} - /** * @} */ @@ -1103,7 +1548,6 @@ __weak void HAL_PWREx_WKUP6_Callback(void) * @brief Peripherals control functions * @verbatim - =============================================================================== ##### Peripherals control functions ##### =============================================================================== @@ -1111,15 +1555,16 @@ __weak void HAL_PWREx_WKUP6_Callback(void) *** Main and Backup Regulators configuration *** ================================================ [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the HAL_PWREx_EnableBkUpReg() function to - enable the low power backup regulator. - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only + from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its + content is retained even in Standby or VBAT mode when the low power + backup regulator is enabled. It can be considered as an internal + EEPROM when VBAT is always present. You can use the + HAL_PWREx_EnableBkUpReg() function to enable the low power backup + regulator. + (+) When the backup domain is supplied by VDD (analog switch connected to + VDD) the backup SRAM is powered from VDD which replaces the VBAT power + supply to save battery life. (+) The backup SRAM is not mass erased by a tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through @@ -1127,118 +1572,125 @@ __weak void HAL_PWREx_WKUP6_Callback(void) level 0 is requested. -@- Refer to the description of Read protection (RDP) in the Flash programming manual. - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through HAL_PWREx_ControlVoltageScaling(VOS) - function which configure the VOS bit in PWR_D3CR register. - (+) The main internal regulator can be configured to operate in Low Power mode - when the system enter STOP mode to further reduce power consumption. + (+) The main internal regulator can be configured to have a tradeoff + between performance and power consumption when the device does not + operate at the maximum frequency. This is done through + HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS + bit in PWR_D3CR register. + (+) The main internal regulator can be configured to operate in Low Power + mode when the system enters STOP mode to further reduce power + consumption. This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS) function which configure the SVOS bit in PWR_CR1 register. - The selected SVOS4 and SVOS5 levels add an additional startup delay when exiting from - system Stop mode. + The selected SVOS4 and SVOS5 levels add an additional startup delay + when exiting from system Stop mode. -@- Refer to the product datasheets for more details. *** USB Regulator configuration *** =================================== [..] - (+) The USB transceivers are supplied from a dedicated VDD33USB supply that can be - provided either by the integrated USB regulator, or by an external USB supply. - (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the VDD33USB - is then provided from the USB regulator. - (+) When the USB regulator is enabled, the VDD33USB supply level detector shall - be enabled through HAL_PWREx_EnableUSBVoltageDetector() function. - (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() function and VDD33USB - can be provided from an external supply. In this case VDD33USB and VDD50USB shall - be connected together + (+) The USB transceivers are supplied from a dedicated VDD33USB supply + that can be provided either by the integrated USB regulator, or by an + external USB supply. + (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the + VDD33USB is then provided from the USB regulator. + (+) When the USB regulator is enabled, the VDD33USB supply level detector + shall be enabled through HAL_PWREx_EnableUSBVoltageDetector() + function. + (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() + function and VDD33USB can be provided from an external supply. In this + case VDD33USB and VDD50USB shall be connected together. *** VBAT battery charging *** ============================= [..] - (+) When VDD is present, the external battery connected to VBAT can be charged through an - internal resistance. VBAT charging can be performed either through a 5 KOhm resistor - or through a 1.5 KOhm resistor. - (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging(ResistorValue) function - with: + (+) When VDD is present, the external battery connected to VBAT can be + charged through an internal resistance. VBAT charging can be performed + either through a 5 KOhm resistor or through a 1.5 KOhm resistor. + (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging + (ResistorValue) function with: (++) ResistorValue: (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. - (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() function. + (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() + function. @endverbatim * @{ */ /** - * @brief Enable the Backup Regulator. - * @retval HAL status + * @brief Enable the Backup Regulator. + * @retval HAL status. */ -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void) { uint32_t tickstart; /* Enable the Backup regulator */ - SET_BIT(PWR->CR2, PWR_CR2_BREN); + SET_BIT (PWR->CR2, PWR_CR2_BREN); /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick (); /* Wait till Backup regulator ready flag is set */ - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_BRR)) + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } + return HAL_OK; } /** - * @brief Disable the Backup Regulator. - * @retval HAL status + * @brief Disable the Backup Regulator. + * @retval HAL status. */ -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void) { uint32_t tickstart; /* Disable the Backup regulator */ - CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); + CLEAR_BIT (PWR->CR2, PWR_CR2_BREN); /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick (); /* Wait till Backup regulator ready flag is reset */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } + return HAL_OK; } /** - * @brief Enable the USB Regulator. - * @retval HAL status + * @brief Enable the USB Regulator. + * @retval HAL status. */ -HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void) +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void) { uint32_t tickstart; /* Enable the USB regulator */ - SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); + SET_BIT (PWR->CR3, PWR_CR3_USBREGEN); /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick (); /* Wait till the USB regulator ready flag is set */ - while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == 0U) + while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } @@ -1246,82 +1698,113 @@ HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void) } /** - * @brief Disable the USB Regulator. - * @retval HAL status + * @brief Disable the USB Regulator. + * @retval HAL status. */ -HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void) +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void) { uint32_t tickstart; /* Disable the USB regulator */ - CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); + CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN); /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick (); /* Wait till the USB regulator ready flag is reset */ - while(READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) != 0U) + while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U) { - if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US) + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) { - return HAL_TIMEOUT; + return HAL_ERROR; } } + return HAL_OK; } /** - * @brief Enable the USB voltage level detector. - * @retval None + * @brief Enable the USB voltage level detector. + * @retval None. */ -void HAL_PWREx_EnableUSBVoltageDetector(void) +void HAL_PWREx_EnableUSBVoltageDetector (void) { /* Enable the USB voltage detector */ - SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); + SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); } /** - * @brief Disable the USB voltage level detector. - * @retval None + * @brief Disable the USB voltage level detector. + * @retval None. */ -void HAL_PWREx_DisableUSBVoltageDetector(void) +void HAL_PWREx_DisableUSBVoltageDetector (void) { /* Disable the USB voltage detector */ - CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); + CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN); } - /** - * @brief Enable the Battery charging. - * When VDD is present, charge the external battery through an internal resistor. - * @param ResistorValue: Specifies the charging resistor. - * This parameter can be one of the following values: - * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. - * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. - * @retval None + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. */ -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue) +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue) { - assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue)); + /* Check the parameter */ + assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue)); /* Specify the charging resistor */ - MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, ResistorValue); + MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue); /* Enable the Battery charging */ - SET_BIT(PWR->CR3, PWR_CR3_VBE); + SET_BIT (PWR->CR3, PWR_CR3_VBE); } - /** - * @brief Disable the Battery charging. - * @retval None + * @brief Disable the Battery charging. + * @retval None. */ -void HAL_PWREx_DisableBatteryCharging(void) +void HAL_PWREx_DisableBatteryCharging (void) { /* Disable the Battery charging */ - CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); + CLEAR_BIT (PWR->CR3, PWR_CR3_VBE); } +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the booster to guarantee the analog switch AC performance when + * the VDD supply voltage is below 2V7. + * @note The VDD supply voltage can be monitored through the PVD and the PLS + * field bits. + * @retval None. + */ +void HAL_PWREx_EnableAnalogBooster (void) +{ + /* Enable the Analog voltage */ + SET_BIT (PWR->CR1, PWR_CR1_AVD_READY); + + /* Enable VDDA booster */ + SET_BIT (PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the analog booster. + * @retval None. + */ +void HAL_PWREx_DisableAnalogBooster (void) +{ + /* Disable VDDA booster */ + CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE); + + /* Disable the Analog voltage */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY); +} +#endif /* defined (PWR_CR1_BOOSTE) */ /** * @} */ @@ -1330,7 +1813,6 @@ void HAL_PWREx_DisableBatteryCharging(void) * @brief Power Monitoring functions * @verbatim - =============================================================================== ##### Power Monitoring functions ##### =============================================================================== @@ -1338,26 +1820,31 @@ void HAL_PWREx_DisableBatteryCharging(void) *** VBAT and Temperature supervision *** ======================================== [..] - (+) The VBAT battery voltage supply can be monitored by comparing it with two threshold - levels: VBAThigh and VBATlow. VBATH flag and VBATL flags in the PWR control register 2 - (PWR_CR2), indicate if VBAT is higher or lower than the threshold. - (+) The temperature can be monitored by comparing it with two threshold levels, TEMPhigh - and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2), - indicate whether the device temperature is higher or lower than the threshold. - (+) The VBAT and the temperature monitoring is enabled by HAL_PWREx_EnableMonitoring() - function and disabled by HAL_PWREx_DisableMonitoring() function. - (+) The HAL_PWREx_GetVBATLevel() function return the VBAT level which can be: - PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or + (+) The VBAT battery voltage supply can be monitored by comparing it with + two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags + in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or + lower than the threshold. + (+) The temperature can be monitored by comparing it with two threshold + levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR + control register 2 (PWR_CR2), indicate whether the device temperature + is higher or lower than the threshold. + (+) The VBAT and the temperature monitoring is enabled by + HAL_PWREx_EnableMonitoring() function and disabled by + HAL_PWREx_DisableMonitoring() function. + (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can + be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. - (+) The HAL_PWREx_GetTemperatureLevel() function return the Temperature level which - can be: PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or + (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature + level which can be : + PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. *** AVD configuration *** ========================= [..] (+) The AVD is used to monitor the VDDA power supply by comparing it to a - threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 register). + threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 + register). (+) A AVDO flag is available to indicate if VDDA is higher or lower than the AVD threshold. This event is internally connected to the EXTI line 16 to generate an interrupt if enabled. @@ -1369,46 +1856,48 @@ void HAL_PWREx_DisableBatteryCharging(void) */ /** - * @brief Enable the VBAT and temperature monitoring. - * @retval HAL status + * @brief Enable the VBAT and temperature monitoring. + * @retval HAL status. */ -void HAL_PWREx_EnableMonitoring(void) +void HAL_PWREx_EnableMonitoring (void) { /* Enable the VBAT and Temperature monitoring */ - SET_BIT(PWR->CR2, PWR_CR2_MONEN); + SET_BIT (PWR->CR2, PWR_CR2_MONEN); } /** - * @brief Disable the VBAT and temperature monitoring. - * @retval HAL status + * @brief Disable the VBAT and temperature monitoring. + * @retval HAL status. */ -void HAL_PWREx_DisableMonitoring(void) +void HAL_PWREx_DisableMonitoring (void) { /* Disable the VBAT and Temperature monitoring */ - CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); + CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN); } /** - * @brief Indicate whether the junction temperature is between, above or below the threshold. + * @brief Indicate whether the junction temperature is between, above or below + * the thresholds. * @retval Temperature level. */ -uint32_t HAL_PWREx_GetTemperatureLevel(void) +uint32_t HAL_PWREx_GetTemperatureLevel (void) { - uint32_t tempLevel; - uint32_t regValue; + uint32_t tempLevel, regValue; /* Read the temperature flags */ - regValue = PWR->CR2 & (PWR_CR2_TEMPH | PWR_CR2_TEMPL); + regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL)); - /* Compare the read value to the temperature threshold */ - if(regValue == PWR_CR2_TEMPL) + /* Check if the temperature is below the threshold */ + if (regValue == PWR_CR2_TEMPL) { tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; } - else if(regValue == PWR_CR2_TEMPH) + /* Check if the temperature is above the threshold */ + else if (regValue == PWR_CR2_TEMPH) { tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; } + /* The temperature is between the thresholds */ else { tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; @@ -1418,26 +1907,28 @@ uint32_t HAL_PWREx_GetTemperatureLevel(void) } /** - * @brief Indicate whether the Battery voltage level is between, above or below the threshold. + * @brief Indicate whether the Battery voltage level is between, above or below + * the thresholds. * @retval VBAT level. */ -uint32_t HAL_PWREx_GetVBATLevel(void) +uint32_t HAL_PWREx_GetVBATLevel (void) { - uint32_t VBATLevel; - uint32_t regValue; + uint32_t VBATLevel, regValue; /* Read the VBAT flags */ - regValue = PWR->CR2 & (PWR_CR2_VBATH | PWR_CR2_VBATL); + regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL)); - /* Compare the read value to the VBAT threshold */ - if(regValue == PWR_CR2_VBATL) + /* Check if the VBAT is below the threshold */ + if (regValue == PWR_CR2_VBATL) { VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; } - else if(regValue == PWR_CR2_VBATH) + /* Check if the VBAT is above the threshold */ + else if (regValue == PWR_CR2_VBATH) { VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; } + /* The VBAT is between the thresholds */ else { VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; @@ -1446,74 +1937,106 @@ uint32_t HAL_PWREx_GetVBATLevel(void) return VBATLevel; } +#if defined (PWR_CSR1_MMCVDO) /** - * @brief Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD). - * @param sConfigAVD: pointer to an PWR_AVDTypeDef structure that contains the configuration - * information for the AVD. - * @note Refer to the electrical characteristics of your device datasheet for more details - * about the voltage threshold corresponding to each detection level. - * @retval None + * @brief Get the VDDMMC voltage level. + * @retval The VDDMMC voltage level. */ -void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD) +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) +{ + PWREx_MMC_VoltageLevel mmc_voltage; + + /* Check voltage detector output on VDDMMC value */ + if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U) + { + mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2; + } + else + { + mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2; + } + + return mmc_voltage; +} +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Analog Voltage Detector (AVD). + * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains + * the configuration information for the AVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { /* Check the parameters */ - assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel)); - assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode)); + assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); + assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ - MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); + MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); /* Clear any previous config */ #if !defined (DUAL_CORE) - __HAL_PWR_AVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_AVD_EXTI_DISABLE_IT(); -#endif - __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_AVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); #if !defined (DUAL_CORE) /* Configure the interrupt mode */ - if(AVD_MODE_IT == (sConfigAVD->Mode & AVD_MODE_IT)) + if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) { - __HAL_PWR_AVD_EXTI_ENABLE_IT(); + __HAL_PWR_AVD_EXTI_ENABLE_IT (); } /* Configure the event mode */ - if(AVD_MODE_EVT == (sConfigAVD->Mode & AVD_MODE_EVT)) + if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) { - __HAL_PWR_AVD_EXTI_ENABLE_EVENT(); + __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); } -#endif - /* Configure the edge */ - if(AVD_RISING_EDGE == (sConfigAVD->Mode & AVD_RISING_EDGE)) +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) { - __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); } - if(AVD_FALLING_EDGE == (sConfigAVD->Mode & AVD_FALLING_EDGE)) + /* Falling edge configuration */ + if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) { - __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); } } /** - * @brief Enable the Analog Voltage Detector(AVD). - * @retval None + * @brief Enable the Analog Voltage Detector (AVD). + * @retval None. */ -void HAL_PWREx_EnableAVD(void) +void HAL_PWREx_EnableAVD (void) { /* Enable the Analog Voltage Detector */ - SET_BIT(PWR->CR1, PWR_CR1_AVDEN); + SET_BIT (PWR->CR1, PWR_CR1_AVDEN); } /** - * @brief Disable the Analog Voltage Detector(AVD). - * @retval None + * @brief Disable the Analog Voltage Detector(AVD). + * @retval None. */ -void HAL_PWREx_DisableAVD(void) +void HAL_PWREx_DisableAVD (void) { /* Disable the Analog Voltage Detector */ - CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); + CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN); } /** @@ -1521,108 +2044,85 @@ void HAL_PWREx_DisableAVD(void) * @note This API should be called under the PVD_AVD_IRQHandler(). * @retval None */ -void HAL_PWREx_PVD_AVD_IRQHandler(void) +void HAL_PWREx_PVD_AVD_IRQHandler (void) { -#if defined(DUAL_CORE) - /* PVD EXTI line interrupt detected */ - if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != 0U) + /* Check if the Programmable Voltage Detector is enabled (PVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U) { - if (HAL_GetCurrentCPUID() == CM7_CPUID) +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ { - /* Check PWR D1 EXTI flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + /* Check PWR D1/CD EXTI flag */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) { /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); + HAL_PWR_PVDCallback (); - /* Clear PWR EXTI D1 pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); } } +#if defined (DUAL_CORE) else { /* Check PWR EXTI D2 flag */ - if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET) + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) { /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); + HAL_PWR_PVDCallback (); /* Clear PWR EXTI D2 pending bit */ __HAL_PWR_PVD_EXTID2_CLEAR_FLAG(); } } +#endif /* defined (DUAL_CORE) */ } - /* AVD EXTI line interrupt detected */ - if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != 0U) + /* Check if the Analog Voltage Detector is enabled (AVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U) { - if (HAL_GetCurrentCPUID() == CM7_CPUID) +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ { - /* Check PWR EXTI D1 flag */ - if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET) + /* Check PWR EXTI D1/CD flag */ + if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U) { /* PWR AVD interrupt user callback */ - HAL_PWREx_AVDCallback(); + HAL_PWREx_AVDCallback (); - /* Clear PWR EXTI D1 pending bit */ - __HAL_PWR_AVD_EXTI_CLEAR_FLAG(); + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_AVD_EXTI_CLEAR_FLAG (); } } +#if defined (DUAL_CORE) else { /* Check PWR EXTI D2 flag */ - if(__HAL_PWR_AVD_EXTID2_GET_FLAG() != RESET) + if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U) { /* PWR AVD interrupt user callback */ - HAL_PWREx_AVDCallback(); + HAL_PWREx_AVDCallback (); /* Clear PWR EXTI D2 pending bit */ - __HAL_PWR_AVD_EXTID2_CLEAR_FLAG(); + __HAL_PWR_AVD_EXTID2_CLEAR_FLAG (); } } +#endif /* defined (DUAL_CORE) */ } -#else - /* PVD EXTI line interrupt detected */ - if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != 0U) - { - /* Check PWR EXTI flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR EXTI pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } - } - - /* AVD EXTI line interrupt detected */ - if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != 0U) - { - /* Check PWR EXTI flag */ - if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET) - { - /* PWR AVD interrupt user callback */ - HAL_PWREx_AVDCallback(); - - /* Clear PWR EXTI pending bit */ - __HAL_PWR_AVD_EXTI_CLEAR_FLAG(); - } - } -#endif /*DUAL_CORE*/ } /** - * @brief PWR AVD interrupt callback - * @retval None + * @brief PWR AVD interrupt callback. + * @retval None. */ -__weak void HAL_PWREx_AVDCallback(void) +__weak void HAL_PWREx_AVDCallback (void) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_AVDCallback could be implemented in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_AVDCallback can be implemented in the user file + */ } - /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c index 3c90ae8..b655c6e 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c @@ -24,7 +24,7 @@ [..] (#) As prerequisite, fill in the HAL_QSPI_MspInit() : (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). + (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt mode is used, enable and configure QuadSPI global @@ -64,7 +64,7 @@ (++) In polling mode, the output of the function is done when the transfer is complete. (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== @@ -91,23 +91,23 @@ ==================================== [..] (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function : - (++) MDMA settings for write operation : - (+) The DestinationInc should be MDMA_DEST_INC_DISABLE + (++) MDMA settings for write operation : + (+) The DestinationInc should be MDMA_DEST_INC_DISABLE (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) + (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) aligned with @ref MDMA_Source_increment_mode . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) - (++) MDMA settings for read operation : - (+) The SourceInc should be MDMA_SRC_INC_DISABLE + (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (++) MDMA settings for read operation : + (+) The SourceInc should be MDMA_SRC_INC_DISABLE (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) aligned with @ref MDMA_Destination_increment_mode. (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi. - (#)In case of wrong MDMA setting - (++) For write operation : + (#)In case of wrong MDMA setting + (++) For write operation : (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA(). - (++) For read operation : + (++) For read operation : (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA(). *** Memory-mapped functional mode *** @@ -137,7 +137,7 @@ (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. + the transfer complete bit is set. *** Control functions *** ========================= @@ -146,6 +146,7 @@ (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. *** Callback registration *** ============================================= @@ -218,7 +219,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -226,6 +227,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal.h" +#if defined(QUADSPI) + /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -242,7 +245,7 @@ /** @defgroup QSPI_Private_Constants QSPI Private Constants * @{ */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!Init.FlashID)); } - /* Process locked */ - __HAL_LOCK(hqspi); - if(hqspi->State == HAL_QSPI_STATE_RESET) { - /* Allocate lock resource and initialize it */ - hqspi->Lock = HAL_UNLOCKED; #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ @@ -356,8 +354,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /* Init the low level hardware : GPIO, CLOCK */ HAL_QSPI_MspInit(hqspi); #endif + /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); + HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); } /* Configure QSPI FIFO Threshold */ @@ -389,16 +388,13 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) hqspi->State = HAL_QSPI_STATE_READY; } - /* Release Lock */ - __HAL_UNLOCK(hqspi); - /* Return function status */ return status; } /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -409,9 +405,6 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hqspi); - /* Disable the QSPI Peripheral Clock */ __HAL_QSPI_DISABLE(hqspi); @@ -434,15 +427,12 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /* Initialize the QSPI state */ hqspi->State = HAL_QSPI_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hqspi); - return HAL_OK; } /** * @brief Initialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -457,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -496,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -506,7 +496,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT)) + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) { data_reg = &hqspi->Instance->DR; @@ -518,7 +508,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->TxXferCount > 0U) { /* Fill the FIFO until the threshold is reached */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -539,7 +529,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0U) { /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -556,6 +546,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { /* Nothing to do */ } + /* FIFO Threshold callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->FifoThresholdCallback(hqspi); @@ -565,7 +556,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC)) + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); @@ -576,7 +567,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -585,6 +576,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) __HAL_MDMA_DISABLE(hqspi->hmdma); } + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -597,7 +589,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -613,7 +605,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0U) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -625,6 +617,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -685,7 +678,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM)) + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); @@ -709,7 +702,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE)) + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); @@ -720,7 +713,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -758,7 +751,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO)) + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); @@ -770,6 +763,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) HAL_QSPI_TimeOutCallback(hqspi); #endif } + else { /* Nothing to do */ @@ -778,7 +772,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @param Timeout : Timeout duration * @note This function is used only in Indirect Read or Write Modes @@ -846,7 +840,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; } - } else { @@ -869,7 +862,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status @@ -968,10 +961,11 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode + * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) @@ -1010,7 +1004,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u break; } - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -1051,8 +1045,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status @@ -1097,7 +1091,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui break; } - *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -1111,6 +1105,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui { /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + } } @@ -1136,8 +1131,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1196,8 +1191,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1260,18 +1255,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode - * @note If MDMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If MDMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ __HAL_LOCK(hqspi); @@ -1283,64 +1275,75 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat if(pData != NULL ) { + /* Configure counters of the handle */ + hqspi->TxXferCount = data_size; - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pTxBuffPtr = pData; + /* Configure size and pointer of the handle */ + hqspi->TxXferSize = hqspi->TxXferCount; + hqspi->pTxBuffPtr = pData; - /* Configure QSPI: CCR register with functional mode as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Configure QSPI: CCR register with functional mode as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - /* Set the QSPI MDMA transfer complete callback */ - hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; + /* Set the QSPI MDMA transfer complete callback */ + hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; - /* Set the MDMA error callback */ - hqspi->hmdma->XferErrorCallback = QSPI_DMAError; + /* Set the MDMA error callback */ + hqspi->hmdma->XferErrorCallback = QSPI_DMAError; - /* Clear the MDMA abort callback */ - hqspi->hmdma->XferAbortCallback = NULL; - - /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */ - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE); - - /* Update MDMA configuration with the correct SourceInc field for Write operation */ - if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) - { - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE); - } - else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) - { - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD); - } - else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) - { - MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); - } - else - { - /* in case of incorrect source data size */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - status = HAL_ERROR; - } + /* Clear the MDMA abort callback */ + hqspi->hmdma->XferAbortCallback = NULL; - /* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC); - - /* Enable the QSPI transmit MDMA */ - if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */ + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE); - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ - } + /* Update MDMA configuration with the correct SourceInc field for Write operation */ + if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE); + } + else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD); + } + else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); + } + else + { + /* in case of incorrect source data size */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + status = HAL_ERROR; + } + + /* Enable the QSPI transmit MDMA */ + if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } else { @@ -1364,8 +1367,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1373,6 +1376,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData { HAL_StatusTypeDef status = HAL_OK; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ __HAL_LOCK(hqspi); @@ -1384,39 +1388,30 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData if(pData != NULL ) { + /* Configure counters of the handle */ + hqspi->RxXferCount = data_size; + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + /* Configure size and pointer of the handle */ + hqspi->RxXferSize = hqspi->RxXferCount; + hqspi->pRxBuffPtr = pData; - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pRxBuffPtr = pData; + /* Set the QSPI MDMA transfer complete callback */ + hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; - /* Set the QSPI DMA transfer complete callback */ - hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; + /* Set the MDMA error callback */ + hqspi->hmdma->XferErrorCallback = QSPI_DMAError; - /* Set the MDMA error callback */ - hqspi->hmdma->XferErrorCallback = QSPI_DMAError; + /* Clear the MDMA abort callback */ + hqspi->hmdma->XferAbortCallback = NULL; - /* Clear the MDMA abort callback */ - hqspi->hmdma->XferAbortCallback = NULL; - - - /* QSPI need to be configured to indirect mode before starting - the MDMA to avoid primatury triggering for the MDMA transfert */ - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - /* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE); - + /* Update MDMA configuration with the correct DestinationInc field for read operation */ if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE) { @@ -1430,27 +1425,43 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData { MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD); } - else + else { /* in case of incorrect destination data size */ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; status = HAL_ERROR; - } - - /* Enable the MDMA */ - if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ } + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Enable the MDMA */ + if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } else { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; /* Process unlocked */ @@ -1470,9 +1481,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @param Timeout : Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status @@ -1571,9 +1582,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1675,9 +1686,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1730,9 +1741,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT if (status == HAL_OK) { /* Configure QSPI: CR register with timeout counter enable */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) { assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); @@ -1764,7 +1775,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1779,7 +1790,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1794,7 +1805,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1809,7 +1820,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1824,10 +1835,10 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -1840,7 +1851,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1855,7 +1866,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1870,7 +1881,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -2112,7 +2123,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle + * @param hqspi : QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2123,7 +2134,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2133,7 +2144,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2147,7 +2158,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Process unlocked */ __HAL_UNLOCK(hqspi); - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2166,7 +2177,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if(status == HAL_OK) + if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -2176,6 +2187,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) if (status == HAL_OK) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2186,7 +2200,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2205,7 +2219,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2214,10 +2228,15 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) { - /* Set error code to DMA */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; - status = HAL_ERROR; + /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else + HAL_QSPI_AbortCpltCallback(hqspi); +#endif } } else @@ -2236,8 +2255,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout. - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. + * @param hqspi : QSPI handle. + * @param Timeout : Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2246,8 +2265,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @param hqspi : QSPI handle. + * @param Threshold : Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2279,7 +2298,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. + * @param hqspi : QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2328,14 +2347,22 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI * @} */ +/** + * @} + */ + +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ + /** * @brief DMA QSPI receive process complete callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); hqspi->RxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ @@ -2344,12 +2371,12 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); hqspi->TxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ @@ -2358,12 +2385,12 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI communication error callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); hqspi->RxXferCount = 0U; hqspi->TxXferCount = 0U; @@ -2379,12 +2406,12 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) /** * @brief MDMA QSPI abort complete callback. - * @param hmdma: MDMA handle + * @param hmdma : MDMA handle * @retval None */ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); hqspi->RxXferCount = 0U; hqspi->TxXferCount = 0U; @@ -2415,13 +2442,14 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) #endif } } + /** * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Tickstart: Tick start value - * @param Timeout: Duration of the timeout + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Tickstart : Tick start value + * @param Timeout : Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2447,9 +2475,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param FunctionalMode : functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2612,4 +2640,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ +#endif /* defined(QUADSPI) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c index cc34251..7d73fa5 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -161,13 +161,15 @@ HSE and PLL. The AHB clock (HCLK) is derived from System core clock through configurable pre-scaler and used to clock the CPU, memory and peripherals mapped - on AHB and APB bus of the 3 Domains (D1, D2, D3) through configurable pre-scalers + on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers and used to clock the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those with dual clock domain where kernel source clock could be selected through RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers. + + (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines. @endverbatim * @{ */ @@ -189,6 +191,22 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + /* Get Start Tick */ tickstart = HAL_GetTick(); @@ -210,8 +228,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - /* Update the SystemCoreClock global variable */ + /* Update the SystemCoreClock and SystemD2Clock global variables */ SystemCoreClock = HSI_VALUE; + SystemD2Clock = HSI_VALUE; /* Adapt Systick interrupt period */ if(HAL_InitTick(uwTickPrio) != HAL_OK) @@ -292,6 +311,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) } } +#if defined(RCC_D1CFGR_HPRE) /* Reset D1CFGR register */ CLEAR_REG(RCC->D1CFGR); @@ -300,6 +320,16 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Reset D3CFGR register */ CLEAR_REG(RCC->D3CFGR); +#else + /* Reset CDCFGR1 register */ + CLEAR_REG(RCC->CDCFGR1); + + /* Reset CDCFGR2 register */ + CLEAR_REG(RCC->CDCFGR2); + + /* Reset SRDCFGR register */ + CLEAR_REG(RCC->SRDCFGR); +#endif /* Reset PLLCKSELR register to default value */ RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5; @@ -337,6 +367,21 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Reset all RSR flags */ SET_BIT(RCC->RSR, RCC_RSR_RMVF); + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + +} + return HAL_OK; } @@ -357,6 +402,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; + uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) @@ -407,7 +453,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till HSE is bypassed or disabled */ + /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) @@ -425,12 +471,12 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - /* When the HSI is used as system clock it will not disabled */ + /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); const uint32_t temp_pllckselr = RCC->PLLCKSELR; if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) { - /* When HSI is used as system clock it will not disabled */ + /* When HSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) { return HAL_ERROR; @@ -438,20 +484,6 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Otherwise, just the calibration is allowed */ else { - /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ - __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - { - if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -488,7 +520,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) @@ -554,7 +586,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till CSI is ready */ + /* Wait till CSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) @@ -692,7 +724,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till LSE is ready */ + /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -727,7 +759,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -747,7 +779,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); - /* Configure PLL PLL1FRACN */ + /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); /* Select PLL1 input reference frequency range: VCI */ @@ -791,7 +823,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -803,7 +835,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } else { - return HAL_ERROR; + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLLCKSELR; + temp2_pllckcfg = RCC->PLL1DIVR; + if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } } } return HAL_OK; @@ -816,7 +860,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc * contains the configuration information for the RCC peripheral. * @param FLatency: FLASH Latency, this parameter depend on device selected * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency * and updated by HAL_InitTick() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after @@ -839,6 +883,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { HAL_StatusTypeDef halstatus; uint32_t tickstart; + uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) @@ -870,55 +915,95 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Increasing the BUS frequency divider */ - /*-------------------------- D1PCLK1 Configuration ---------------------------*/ + /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) { +#if defined (RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } +#else + if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { +#if defined (RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } +#else + if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } - +#endif + } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { +#if defined(RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } +#else + if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) { +#if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); } +#else + if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + } +#endif } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { +#if defined (RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } +#else + if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif } /*------------------------- SYSCLK Configuration -------------------------*/ @@ -926,7 +1011,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); +#if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); +#endif /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { @@ -982,12 +1071,21 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { +#if defined(RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } +#else + if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif } /* Decreasing the number of wait states because of lower CPU frequency */ @@ -1004,48 +1102,96 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } - /*-------------------------- D1PCLK1 Configuration ---------------------------*/ + /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) { +#if defined(RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } +#else + if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { +#if defined(RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } +#else + if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { +#if defined (RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } +#else + if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif } - /*-------------------------- D3PCLK1 Configuration ---------------------------*/ + /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) { +#if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); } +#else + if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + } +#endif } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); @@ -1298,7 +1444,26 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + return SystemD2Clock; } @@ -1311,8 +1476,13 @@ uint32_t HAL_RCC_GetHCLKFreq(void) */ uint32_t HAL_RCC_GetPCLK1Freq(void) { +#if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); +#else + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); +#endif } @@ -1325,7 +1495,11 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +#if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); +#else + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); +#endif } /** @@ -1342,6 +1516,24 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48; /* Get the HSE configuration -----------------------------------------------*/ +#if defined(RCC_CR_HSEEXT) + if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#else if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; @@ -1354,6 +1546,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } +#endif /* RCC_CR_HSEEXT */ /* Get the CSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION) @@ -1365,6 +1558,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->CSIState = RCC_CSI_OFF; } +#if defined(RCC_VER_X) if(HAL_GetREVID() <= REV_ID_Y) { RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos); @@ -1373,6 +1567,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); } +#else + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /*RCC_VER_X*/ /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) @@ -1384,6 +1581,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } +#if defined(RCC_VER_X) if(HAL_GetREVID() <= REV_ID_Y) { RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos); @@ -1392,8 +1590,29 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); } +#else + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ /* Get the LSE configuration -----------------------------------------------*/ +#if defined(RCC_BDCR_LSEEXT) + if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#else if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; @@ -1406,6 +1625,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } +#endif /* RCC_BDCR_LSEEXT */ /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) @@ -1464,6 +1684,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); +#if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); @@ -1481,7 +1702,25 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); +#else + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE); + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); +#endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c index 576b8b0..6af58a5 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -37,7 +37,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ -/** @defgroup RCCEx_Private_defines Private Defines +/** @defgroup RCCEx_Private_defines RCCEx Private Defines * @{ */ #define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ @@ -63,10 +63,8 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); - /* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions Exported Functions +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ @@ -94,14 +92,16 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals - * clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123, - * USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, - * SAI4A,SAI4B,SPI6,RTC). + * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, + * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, + * SAI4A*, SAI4B*, SPI6, RTC). * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source; in this case the Backup domain will be reset in * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) are set to their reset values. * + * (*) : Available on some STM32H7 lines only. + * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -119,23 +119,23 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk switch(PeriphClkInit->SpdifrxClockSelection) { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ - /* Enable SAI Clock output generated form System PLL . */ + /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI1 clock source configuration done later after clock selection check */ + /* SPDIFRX clock source configuration done later after clock selection check */ break; case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); - /* SAI1 clock source configuration done later after clock selection check */ + /* SPDIFRX clock source configuration done later after clock selection check */ break; case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); - /* SAI1 clock source configuration done later after clock selection check */ + /* SPDIFRX clock source configuration done later after clock selection check */ break; case RCC_SPDIFRXCLKSOURCE_HSI: @@ -212,6 +212,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } +#if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) { @@ -264,6 +265,128 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + /*---------------------------- SAI2A configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + { + switch(PeriphClkInit->Sai2AClockSelection) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + /* Enable SAI2A Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PIN: + /* External clock is used as source of SAI2A clock*/ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if(ret == HAL_OK) + { + /* Set the source of SAI2A clock*/ + __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2A*/ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) + + /*---------------------------- SAI2B configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + { + switch(PeriphClkInit->Sai2BClockSelection) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PIN: + /* External clock is used as source of SAI2B clock*/ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if(ret == HAL_OK) + { + /* Set the source of SAI2B clock*/ + __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2B*/ + +#if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) { @@ -298,6 +421,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4A clock */ + /* SAI4A clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; @@ -306,7 +436,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk if(ret == HAL_OK) { - /* Set the source of SAI2 clock*/ + /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); } else @@ -350,6 +480,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* SAI1 clock source configuration done later after clock selection check */ break; +#if defined(RCC_VER_3_0) + case RCC_SAI4BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4B clock */ + /* SAI4B clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + default: ret = HAL_ERROR; break; @@ -357,7 +494,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk if(ret == HAL_OK) { - /* Set the source of SAI2 clock*/ + /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); } else @@ -366,6 +503,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /*SAI4*/ + +#if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) { @@ -411,6 +551,55 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /*---------------------------- OCTOSPI configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + switch(PeriphClkInit->OspiClockSelection) + { + case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + /* Enable OSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_OSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_HCLK: + /* HCLK clock selected as OSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if(ret == HAL_OK) + { + /* Set the source of OSPI clock*/ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) @@ -468,7 +657,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Spi45ClockSelection) { - case RCC_SPI45CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for SPI4/5 */ + case RCC_SPI45CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for SPI4/5 */ /* SPI4/5 clock source configuration done later after clock selection check */ break; @@ -520,7 +709,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Spi6ClockSelection) { - case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for SPI6*/ + case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ /* SPI6 clock source configuration done later after clock selection check */ break; @@ -549,6 +738,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* HSE, oscillator is used as source of SPI6 clock */ /* SPI6 clock source configuration done later after clock selection check */ break; +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: + /* 2S_CKIN is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#endif default: ret = HAL_ERROR; @@ -645,8 +840,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk status = ret; } } - #endif /*FDCAN1 || FDCAN2*/ + /*---------------------------- FMC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) { @@ -672,8 +867,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* FMC clock source configuration done later after clock selection check */ break; - case RCC_FMCCLKSOURCE_D1HCLK: - /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + case RCC_FMCCLKSOURCE_HCLK: + /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: @@ -728,7 +923,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk RCC->BDCR = tmpreg; } - /* If LSE is selected as RTC clock source, wait for LSE reactivation */ + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) { /* Get Start Tick*/ @@ -768,7 +963,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Usart16ClockSelection) { - case RCC_USART16CLKSOURCE_D2PCLK2: /* D2PCLK2 as clock source for USART1/6 */ + case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; @@ -819,7 +1014,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Usart234578ClockSelection) { - case RCC_USART234578CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for USART2/3/4/5/7/8 */ + case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; @@ -870,7 +1065,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Lpuart1ClockSelection) { - case RCC_LPUART1CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPUART1 */ + case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; @@ -921,7 +1116,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Lptim1ClockSelection) { - case RCC_LPTIM1CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for LPTIM1*/ + case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ /* LPTIM1 clock source configuration done later after clock selection check */ break; @@ -974,7 +1169,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { switch(PeriphClkInit->Lptim2ClockSelection) { - case RCC_LPTIM2CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM2*/ + case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ /* LPTIM2 clock source configuration done later after clock selection check */ break; @@ -1028,7 +1223,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk switch(PeriphClkInit->Lptim345ClockSelection) { - case RCC_LPTIM345CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM3/4/5 */ + case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; @@ -1075,7 +1270,25 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } - /*------------------------------ I2C1/2/3 Configuration ------------------------*/ + /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ +#if defined(I2C5) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); + + if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 ) + { + if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); + + } +#else if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) { /* Check the parameters */ @@ -1089,12 +1302,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } - else - { __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); - } } +#endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) @@ -1110,10 +1321,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } - else - { __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - } + } /*---------------------------- ADC configuration -------------------------------*/ @@ -1304,7 +1513,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); } - +#if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) { @@ -1314,7 +1523,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } - +#endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) { @@ -1325,6 +1534,18 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); } +#if defined(DFSDM2_BASE) + /*------------------------------ DFSDM2 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM2 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } +#endif /* DFSDM2 */ + /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) { @@ -1355,28 +1576,62 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that -* returns the configuration information for the Extended Peripherals clocks : - * (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123, - * USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, -* SAI4A,SAI4B,SPI6,RTC,TIM). + * returns the configuration information for the Extended Peripherals clocks : + * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, + * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. + * SAI4A*, SAI4B*, SPI6, RTC, TIM). * @retval None + * + * (*) : Available on some STM32H7 lines only. */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = - RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C123 | + RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI23 | RCC_PERIPHCLK_SAI4A | RCC_PERIPHCLK_SAI4B | - RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_FDCAN | - RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC | - RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CEC | - RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_SPDIFRX | - RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_CKPER; + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | + RCC_PERIPHCLK_CKPER; +#if defined(I2C5) +PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; +#else +PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; +#endif /*I2C5*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI3) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; +#endif /* SAI3 */ +#if defined(SAI4) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; +#endif /* SAI4 */ +#if defined(DFSDM2_BASE) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; +#endif /* DFSDM2 */ +#if defined(QUADSPI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +#endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(HRTIM1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; +#endif /* HRTIM1 */ #if defined(LTDC) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; #endif /* LTDC */ +#if defined(DSI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; +#endif /* DSI */ /* Get the PLL3 Clock configuration -----------------------------------------------*/ PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos); @@ -1402,8 +1657,13 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(I2C5) + /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ + PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#else /* Get the I2C1/2/3 clock source -------------------------------------------*/ PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#endif /*I2C5*/ /* Get the LPTIM1 clock source ---------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); /* Get the LPTIM2 clock source ---------------------------------------------*/ @@ -1412,12 +1672,24 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); /* Get the SAI1 clock source -----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI3) /* Get the SAI2/3 clock source ---------------------------------------------*/ PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); +#endif /*SAI3*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL_0) + /* Get the SAI2A clock source ---------------------------------------------*/ + PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); +#endif /*SAI2A*/ +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + /* Get the SAI2B clock source ---------------------------------------------*/ + PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); +#endif /*SAI2B*/ +#if defined(SAI4) /* Get the SAI4A clock source ----------------------------------------------*/ PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); /* Get the SAI4B clock source ----------------------------------------------*/ PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); +#endif /*SAI4*/ /* Get the RTC clock source ------------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); /* Get the USB clock source ------------------------------------------------*/ @@ -1426,14 +1698,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if defined(HRTIM1) /* Get the HRTIM1 clock source ---------------------------------------------*/ PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); +#endif /* HRTIM1 */ /* Get the ADC clock source ------------------------------------------------*/ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); /* Get the SWPMI1 clock source ---------------------------------------------*/ PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); /* Get the DFSDM1 clock source ---------------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); +#if defined(DFSDM2_BASE) + /* Get the DFSDM2 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); +#endif /* DFSDM2 */ /* Get the SPDIFRX clock source --------------------------------------------*/ PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); /* Get the SPI1/2/3 clock source -------------------------------------------*/ @@ -1448,8 +1726,14 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); /* Get the FMC clock source ------------------------------------------------*/ PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); +#if defined(QUADSPI) /* Get the QSPI clock source -----------------------------------------------*/ PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OSPI clock source -----------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ #if defined(DSI) /* Get the DSI clock source ------------------------------------------------*/ @@ -1476,11 +1760,18 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @param PeriphClk: Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock - * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock - * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock - * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock + * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock * @retval Frequency in KHz + * + * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { @@ -1502,44 +1793,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (saiclocksource) { - case 0: /* PLL1 is the clock source for SAI1 */ + case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; break; } - case RCC_D2CCIP1R_SAI1SEL_0: /* PLLI2 is the clock source for SAI1 */ + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; break; } - case RCC_D2CCIP1R_SAI1SEL_1: /* PLLI3 is the clock source for SAI1 */ + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; break; } - case RCC_D2CCIP1R_SAI1SEL_2: /* CKPER is the clock source for SAI1*/ + case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== 0U) + if(ckpclocksource== RCC_CLKPSOURCE_HSI) { /* In Case the CKPER Source is HSI */ frequency = HSI_VALUE; } - else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0) + else if(ckpclocksource== RCC_CLKPSOURCE_CSI) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1) + else if (ckpclocksource== RCC_CLKPSOURCE_HSE) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -1554,7 +1845,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } - case (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1 ): /* External clock is the clock source for SAI1 */ + case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; break; @@ -1567,6 +1858,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } +#if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) { @@ -1580,38 +1872,38 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = pll1_clocks.PLL1_Q_Frequency; break; } - case RCC_D2CCIP1R_SAI23SEL_0: /* PLLI2 is the clock source for SAI2/3 */ + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; break; } - case RCC_D2CCIP1R_SAI23SEL_1: /* PLLI3 is the clock source for SAI2/3 */ + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; break; } - case RCC_D2CCIP1R_SAI23SEL_2: /* CKPER is the clock source for SAI2/3 */ + case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== 0U) + if(ckpclocksource== RCC_CLKPSOURCE_HSI) { /* In Case the CKPER Source is HSI */ frequency = HSI_VALUE; } - else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0) + else if(ckpclocksource== RCC_CLKPSOURCE_CSI) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1) + else if (ckpclocksource== RCC_CLKPSOURCE_HSE) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -1626,7 +1918,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } - case (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1 ): /* External clock is the clock source for SAI2/3 */ + case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; break; @@ -1638,7 +1930,159 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } } +#endif /* SAI3 */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) + + else if (PeriphClk == RCC_PERIPHCLK_SAI2A) + { + saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE(); + + switch (saiclocksource) + { + case 0: /* PLL1 is the clock source for SAI2A */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } + + case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + { + + ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); + + if(ckpclocksource== RCC_CLKPSOURCE_HSI) + { + /* In Case the CKPER Source is HSI */ + frequency = HSI_VALUE; + } + + else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + + } +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + else if (PeriphClk == RCC_PERIPHCLK_SAI2B) + { + + saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE(); + + switch (saiclocksource) + { + case 0: /* PLL1 is the clock source for SAI2B */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + break; + } + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + break; + } + + case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + { + + ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); + + if(ckpclocksource== RCC_CLKPSOURCE_HSI) + { + /* In Case the CKPER Source is HSI */ + frequency = HSI_VALUE; + } + + else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + break; + } + + case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif + +#if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) { @@ -1671,19 +2115,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== 0U) + if(ckpclocksource== RCC_CLKPSOURCE_HSI) { /* In Case the CKPER Source is HSI */ frequency = HSI_VALUE; } - else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0) + else if(ckpclocksource== RCC_CLKPSOURCE_CSI) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1) + else if (ckpclocksource== RCC_CLKPSOURCE_HSE) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -1744,19 +2188,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== 0U) + if(ckpclocksource== RCC_CLKPSOURCE_HSI) { /* In Case the CKPER Source is HSI */ frequency = HSI_VALUE; } - else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0) + else if(ckpclocksource== RCC_CLKPSOURCE_CSI) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1) + else if (ckpclocksource== RCC_CLKPSOURCE_HSE) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -1784,7 +2228,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } } - +#endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) { /* Get SPI1/2/3 clock source */ @@ -1792,27 +2236,27 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (srcclk) { - case 0: /* PLL1 is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */ { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; break; } - case RCC_D2CCIP1R_SPI123SEL_0: /* PLL2 is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */ { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; break; } - case RCC_D2CCIP1R_SPI123SEL_1: /* PLL3 is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */ { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; break; } - case RCC_D2CCIP1R_SPI123SEL_2: /* CKPER is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); @@ -1844,7 +2288,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } - case (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1): /* External clock is the clock source for I2S */ + case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; break; @@ -1935,6 +2379,59 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI6) + { + /* Get SPI6 clock source */ + srcclk= __HAL_RCC_GET_SPI6_SOURCE(); + + switch (srcclk) + { + case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ + { + frequency = HAL_RCCEx_GetD3PCLK1Freq(); + break; + } + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + break; + } + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + break; + } + case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + { + frequency = HSI_VALUE; + break; + } + case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + { + frequency = CSI_VALUE; + break; + } + case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + { + frequency = HSE_VALUE; + break; + } +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; @@ -1959,8 +2456,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) { +#if defined(RCC_D1CFGR_D1PPRE) /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); +#else +/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); +#endif } /** @@ -1971,8 +2473,13 @@ uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { +#if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); +#endif } /** * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency @@ -1997,8 +2504,8 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12) ; - pll2fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN; + pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); + pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); if (pll2m != 0U) @@ -2067,7 +2574,7 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; - pll3fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN; + pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); if (pll3m != 0U) @@ -2179,19 +2686,46 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) } /** - * @brief Returns the main Core frequency - * @note Each time core clock changes, this function must be called to update the - * right system core clock value. Otherwise, any configuration based on this function will be incorrect. - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @brief Returns the main System frequency + * @note Each time System clock changes, this function must be called to update the + * right core clock value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCCEx_GetD1SysClockFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); - return SystemCoreClock; -} +uint32_t common_system_clock; +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return common_system_clock; +} +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ /** * @brief Enables the LSE Clock Security System. * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled @@ -2216,6 +2750,28 @@ void HAL_RCCEx_DisableLSECSS(void) __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +#else + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +#endif /* DUAL_CORE && CORE_CM4 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + /** * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock * @param WakeUpClk: Wakeup clock @@ -2285,7 +2841,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) } #else - +#if defined(RCC_GCR_WW1RSC) /** * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs * @param RCC_WWDGx: WWDGx to be configured @@ -2300,9 +2856,12 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); SET_BIT(RCC->GCR, RCC_WWDGx) ; } - +#endif #endif /*DUAL_CORE*/ +/** + * @} + */ /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions @@ -2671,18 +3230,15 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) * @} */ -/** @defgroup RCCEx_Private_functions Private Functions +/** @defgroup RCCEx_Private_functions RCCEx Private Functions * @{ */ - - - /** * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that * contains the configuration parameters as well as VCI, VCO clock ranges. * @param Divider divider parameter to be updated - * @note PLL2 is temporary disable to apply new parameters + * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ @@ -2715,7 +3271,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) @@ -2787,7 +3343,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that * contains the configuration parameters as well as VCI, VCO clock ranges. * @param Divider divider parameter to be updated - * @note PLL3 is temporary disable to apply new parameters + * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ @@ -2884,12 +3440,37 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D return status; } +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + } +} /** - * @} + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + + /** * @} diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c index fff517e..0c68efe 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -199,7 +199,7 @@ all interrupt callbacks are set to the corresponding weak functions: /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions @@ -221,6 +221,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -306,6 +307,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -339,6 +347,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -391,6 +406,12 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; @@ -401,9 +422,6 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE(htim); } - /* Change the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -418,13 +436,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the TIM state*/ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -443,6 +458,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); @@ -466,12 +490,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -490,6 +518,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; @@ -507,7 +536,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else { - /* nothing to do */ + return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ @@ -555,7 +584,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -638,6 +667,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -671,6 +707,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -730,6 +773,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -780,6 +832,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -802,6 +857,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -918,6 +982,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -942,11 +1009,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -954,12 +1022,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1132,8 +1200,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1215,6 +1283,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1248,6 +1323,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1307,6 +1389,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1357,8 +1448,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1381,6 +1472,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1497,6 +1597,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1521,11 +1624,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1533,12 +1637,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1710,8 +1814,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1793,6 +1897,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1826,6 +1937,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1879,10 +1997,23 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1919,6 +2050,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1937,10 +2072,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -2044,6 +2192,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2064,16 +2216,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2081,12 +2238,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -2202,6 +2360,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2240,14 +2401,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2284,6 +2443,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2339,6 +2501,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2372,6 +2543,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2422,9 +2602,29 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2479,6 +2679,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2494,9 +2700,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2562,6 +2788,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2600,6 +2832,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status @@ -2617,15 +2852,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -2697,6 +2932,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2731,6 +2975,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2782,8 +3035,58 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ switch (Channel) @@ -2827,7 +3130,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2856,6 +3159,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + /* Return function status */ return HAL_OK; } @@ -2872,8 +3189,58 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2923,7 +3290,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2954,8 +3321,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -2977,27 +3355,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { - return HAL_ERROR; + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } } else { - htim->State = HAL_TIM_STATE_BUSY; + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; } } else { - /* nothing to do */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } switch (Channel) @@ -3095,6 +3541,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch default: break; } + /* Return function status */ return HAL_OK; } @@ -3112,7 +3559,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -3147,8 +3594,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -3417,8 +3875,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3485,8 +3941,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3517,8 +3971,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -3582,8 +4034,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3617,8 +4067,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3727,8 +4175,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3963,11 +4409,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -3975,7 +4421,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4112,8 +4558,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4178,6 +4622,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); } + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Return function status */ return status; } @@ -4291,11 +4738,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4303,7 +4750,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4441,8 +4888,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4507,6 +4952,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); } + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Return function status */ return status; } @@ -5796,6 +6244,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + /** * @} */ @@ -5817,13 +6313,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** @@ -5835,23 +6356,41 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5876,8 +6415,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5917,23 +6454,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5958,8 +6517,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5999,7 +6556,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -6017,8 +6577,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else @@ -6035,7 +6593,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); @@ -6053,8 +6614,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else @@ -6612,6 +7171,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR6: case TIM_TS_ITR7: case TIM_TS_ITR8: + case TIM_TS_ITR9: + case TIM_TS_ITR10: + case TIM_TS_ITR11: + case TIM_TS_ITR12: + case TIM_TS_ITR13: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -6906,11 +7470,19 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input - * @arg TIM_TS_ITR4: Internal Trigger 4 + * @arg TIM_TS_ITR4: Internal Trigger 4 (*) * @arg TIM_TS_ITR5: Internal Trigger 5 * @arg TIM_TS_ITR6: Internal Trigger 6 * @arg TIM_TS_ITR7: Internal Trigger 7 - * @arg TIM_TS_ITR8: Internal Trigger 8 + * @arg TIM_TS_ITR8: Internal Trigger 8 (*) + * @arg TIM_TS_ITR9: Internal Trigger 9 (*) + * @arg TIM_TS_ITR10: Internal Trigger 10 (*) + * @arg TIM_TS_ITR11: Internal Trigger 11 (*) + * @arg TIM_TS_ITR12: Internal Trigger 12 (*) + * @arg TIM_TS_ITR13: Internal Trigger 13 (*) + * + * (*) Value not defined in all devices. + * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c index c2610ba..2b5e0c0 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c @@ -55,7 +55,7 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @@ -91,9 +91,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ @@ -124,6 +126,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status @@ -209,6 +214,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -242,6 +256,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -289,12 +312,31 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -325,6 +367,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -337,10 +385,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -379,6 +446,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -393,29 +466,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -464,9 +544,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -513,6 +598,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -555,6 +649,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -577,6 +674,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -685,6 +791,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -709,24 +818,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -734,11 +844,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) @@ -753,11 +863,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) @@ -772,11 +882,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) @@ -864,8 +974,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -922,6 +1032,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -963,6 +1082,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -985,6 +1107,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1093,6 +1224,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1117,35 +1251,37 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) @@ -1160,11 +1296,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) @@ -1179,11 +1315,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) @@ -1271,8 +1407,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1312,11 +1448,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Enable the complementary One Pulse output */ + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1337,12 +1489,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1350,6 +1504,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1366,17 +1524,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - /* Enable the complementary One Pulse output */ + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1397,6 +1571,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1406,8 +1582,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1415,6 +1592,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1460,6 +1641,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR12: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR13: Internal trigger 13 selected (*) * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: @@ -1476,8 +1659,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t __HAL_LOCK(htim); - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; @@ -1516,6 +1700,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR2: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 13 selected (*) * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: @@ -1532,8 +1718,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 __HAL_LOCK(htim); - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; @@ -1573,7 +1760,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR2: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 13 selected (*) * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer @@ -1589,8 +1781,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 __HAL_LOCK(htim); - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; @@ -1636,7 +1829,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); @@ -1669,16 +1862,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; @@ -1893,9 +2089,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * @arg TIM_TIM1_ETR_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 - * @arg TIM_TIM1_ETR_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 - * @arg TIM_TIM1_ETR_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3 + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 @@ -1914,8 +2110,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * * For TIM5, the parameter is one of the following values: * @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO - * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A - * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B + * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * @arg TIM_TIM5_ETR_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) * * For TIM8, the parameter is one of the following values: * @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO @@ -1928,6 +2126,20 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 * + * For TIM23, the parameter is one of the following values: (*) + * @arg TIM_TIM23_ETR_GPIO TIM23_ETR is connected to GPIO + * @arg TIM_TIM23_ETR_COMP1 TIM23_ETR is connected to COMP1 output + * @arg TIM_TIM23_ETR_COMP2 TIM23_ETR is connected to COMP2 output + * + * For TIM24, the parameter is one of the following values: (*) + * @arg TIM_TIM24_ETR_GPIO TIM24_ETR is connected to GPIO + * @arg TIM_TIM24_ETR_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A + * @arg TIM_TIM24_ETR_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B + * @arg TIM_TIM24_ETR_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A + * @arg TIM_TIM24_ETR_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B + * + * (*) Value not defined in all devices. + * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) @@ -2009,6 +2221,18 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1 * + * For TIM23, the parameter can have the following values: (*) + * @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO + * @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output + * @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output + * @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output + * + * For TIM24, the parameter can have the following values: (*) + * @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO + * @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP + * @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP + * @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC + * * (*) Value not defined in all devices. \n * @retval HAL status */ @@ -2189,6 +2413,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} /** * @} */ @@ -2241,6 +2486,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) } +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c index 85a0b6e..684c0ce 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c @@ -191,6 +191,8 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -1065,6 +1067,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) @@ -1092,8 +1096,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1159,6 +1161,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } + __HAL_UNLOCK(huart); + /* as long as data have to be received */ while (huart->RxXferCount > 0U) { @@ -1182,8 +1186,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -2857,9 +2859,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv = 0x00000000U; + uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - uint32_t lpuart_ker_ck_pres = 0x00000000U; + uint32_t lpuart_ker_ck_pres; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; uint32_t pclk; @@ -2928,41 +2930,45 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_D3PCLK1: - lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCCEx_GetD3PCLK1Freq(); break; case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = pll2_clocks.PLL2_Q_Frequency; break; case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = pll3_clocks.PLL3_Q_Frequency; break; case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); } else { - lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; } break; case UART_CLOCKSOURCE_CSI: - lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) CSI_VALUE; break; case UART_CLOCKSOURCE_LSE: - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* if proper clock source reported */ - if (lpuart_ker_ck_pres != 0U) + /* If proper clock source reported */ + if (pclk != 0U) { - /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) { @@ -2970,42 +2976,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) } else { - switch (clocksource) - { - case UART_CLOCKSOURCE_D3PCLK1: - pclk = HAL_RCCEx_GetD3PCLK1Freq(); - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_PLL2: - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_PLL3: - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler)); - } - else - { - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - } - break; - case UART_CLOCKSOURCE_CSI: - usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - default: - ret = HAL_ERROR; - break; - } - - /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { huart->Instance->BRR = usartdiv; @@ -3014,8 +2987,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { ret = HAL_ERROR; } - } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ - } /* if (lpuart_ker_ck_pres != 0) */ + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) @@ -3024,51 +2997,54 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = pll2_clocks.PLL2_Q_Frequency; break; case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = pll3_clocks.PLL3_Q_Frequency; break; case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); } else { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; } break; case UART_CLOCKSOURCE_CSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) CSI_VALUE; break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } } else @@ -3077,49 +3053,52 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = pll2_clocks.PLL2_Q_Frequency; break; case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = pll3_clocks.PLL3_Q_Frequency; break; case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); } else { - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; } break; case UART_CLOCKSOURCE_CSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) CSI_VALUE; break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } } } @@ -3292,7 +3271,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3300,10 +3279,10 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_TIMEOUT; } } diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c index 9492085..822a2fb 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c @@ -60,10 +60,10 @@ * @{ */ /* UART RX FIFO depth */ -#define RX_FIFO_DEPTH 8U +#define RX_FIFO_DEPTH 16U /* UART TX FIFO depth */ -#define TX_FIFO_DEPTH 8U +#define TX_FIFO_DEPTH 16U /** * @} */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c index 5d931b8..2d92900 100644 --- a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c @@ -289,6 +289,8 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; @@ -389,17 +391,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - if (cfg.dma_enable == 1U) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 | - USB_OTG_DTHRCTL_RXTHRLEN_6; - - USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN | - USB_OTG_DTHRCTL_ISOTHREN | - USB_OTG_DTHRCTL_NONISOTHREN; - } - /* Disable all interrupts. */ USBx->GINTMSK = 0U; @@ -621,6 +612,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP /* Read DEPCTLn register */ if (ep->is_in == 1U) { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | @@ -631,6 +628,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP } else { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | @@ -656,11 +659,23 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U /* Read DEPCTLn register */ if (ep->is_in == 1U) { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); } else { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); } @@ -1227,13 +1242,9 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; - /* Set the MPS of the IN EP based on the enumeration speed */ + /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - USBx_INEP(0U)->DIEPCTL |= 3U; - } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; @@ -1337,7 +1348,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if ((USBx->CID & (0x1U << 8)) != 0U) { - if (cfg.speed == USB_OTG_SPEED_FULL) + if (cfg.speed == USBH_FSLS_SPEED) { /* Force Device Enumeration to FS/LS mode only */ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..2cb5655 --- /dev/null +++ b/Makefile @@ -0,0 +1,215 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Sun Dec 20 04:41:46 CST 2020] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = STM32H750VB_Bootloader + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +Core/Src/main.c \ +Core/Src/stm32h7xx_it.c \ +Core/Src/stm32h7xx_hal_msp.c \ +Core/Src/w25_qspi.c \ +Core/Src/port_printf.c \ +Core/Src/printf.c \ +Core/Src/bootloader_control.c \ +USB_DEVICE/App/usb_device.c \ +USB_DEVICE/App/usbd_desc.c \ +USB_DEVICE/App/usbd_dfu_if.c \ +USB_DEVICE/Target/usbd_conf.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \ +Core/Src/system_stm32h7xx.c \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ +Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c + +# ASM sources +ASM_SOURCES = \ +startup_stm32h750xx.s + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m7 + +# fpu +FPU = -mfpu=fpv5-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DUSE_HAL_DRIVER \ +-DSTM32H750xx + + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ +-IUSB_DEVICE/App \ +-IUSB_DEVICE/Target \ +-ICore/Inc \ +-IDrivers/STM32H7xx_HAL_Driver/Inc \ +-IDrivers/STM32H7xx_HAL_Driver/Inc/Legacy \ +-IMiddlewares/ST/STM32_USB_Device_Library/Core/Inc \ +-IMiddlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc \ +-IDrivers/CMSIS/Device/ST/STM32H7xx/Include \ +-IDrivers/CMSIS/Include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32H750VBTx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h b/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h index c0dfe95..f7a0d20 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h +++ b/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h @@ -115,7 +115,7 @@ extern "C" { /* Other defines */ /**************************************************/ /* Bit Detach capable = bit 3 in bmAttributes field */ -#define DFU_DETACH_MASK (uint8_t)(1 << 4) +#define DFU_DETACH_MASK (1U << 4) #define DFU_STATUS_DEPTH 6U typedef enum @@ -133,7 +133,7 @@ typedef void (*pFunction)(void); /********** Descriptor of DFU interface 0 Alternate setting n ****************/ -#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ +#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ \ 0x00, /* bInterfaceNumber: Number of Interface */ \ (n), /* bAlternateSetting: Alternate setting */ \ @@ -162,20 +162,19 @@ typedef struct union { uint32_t d32[USBD_DFU_XFER_SIZE / 4U]; - uint8_t d8[USBD_DFU_XFER_SIZE]; + uint8_t d8[USBD_DFU_XFER_SIZE]; } buffer; - uint32_t wblock_num; - uint32_t wlength; - uint32_t data_ptr; - uint32_t alt_setting; + uint32_t wblock_num; + uint32_t wlength; + uint32_t data_ptr; + uint32_t alt_setting; - uint8_t dev_status[DFU_STATUS_DEPTH]; - uint8_t ReservedForAlign[2]; - uint8_t dev_state; - uint8_t manif_state; -} -USBD_DFU_HandleTypeDef; + uint8_t dev_status[DFU_STATUS_DEPTH]; + uint8_t ReservedForAlign[2]; + uint8_t dev_state; + uint8_t manif_state; +} USBD_DFU_HandleTypeDef; typedef struct { @@ -186,8 +185,7 @@ typedef struct uint16_t (* Write)(uint8_t *src, uint8_t *dest, uint32_t Len); uint8_t *(* Read)(uint8_t *src, uint8_t *dest, uint32_t Len); uint16_t (* GetStatus)(uint32_t Add, uint8_t cmd, uint8_t *buff); -} -USBD_DFU_MediaTypeDef; +} USBD_DFU_MediaTypeDef; /** * @} */ @@ -206,8 +204,8 @@ USBD_DFU_MediaTypeDef; * @{ */ -extern USBD_ClassTypeDef USBD_DFU; -#define USBD_DFU_CLASS &USBD_DFU +extern USBD_ClassTypeDef USBD_DFU; +#define USBD_DFU_CLASS &USBD_DFU /** * @} */ @@ -215,8 +213,8 @@ extern USBD_ClassTypeDef USBD_DFU; /** @defgroup USB_CORE_Exported_Functions * @{ */ -uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, - USBD_DFU_MediaTypeDef *fops); +uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, + USBD_DFU_MediaTypeDef *fops); /** * @} */ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c b/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c index e41f240..b4f8f7d 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c +++ b/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c @@ -93,61 +93,34 @@ EndBSPDependencies */ */ - - /** @defgroup USBD_DFU_Private_FunctionPrototypes * @{ */ +static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev); -static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length); - -static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length); - -static uint8_t USBD_DFU_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_DFU_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_DFU_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_DFU_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length); +static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length); #if (USBD_SUPPORT_USER_STRING_DESC == 1U) -static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); +static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, + uint8_t index, uint16_t *length); #endif static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - static void DFU_GetStatus(USBD_HandleTypeDef *pdev); - static void DFU_ClearStatus(USBD_HandleTypeDef *pdev); - static void DFU_GetState(USBD_HandleTypeDef *pdev); - static void DFU_Abort(USBD_HandleTypeDef *pdev); - static void DFU_Leave(USBD_HandleTypeDef *pdev); - /** * @} */ @@ -156,18 +129,18 @@ static void DFU_Leave(USBD_HandleTypeDef *pdev); * @{ */ -USBD_ClassTypeDef USBD_DFU = +USBD_ClassTypeDef USBD_DFU = { USBD_DFU_Init, USBD_DFU_DeInit, USBD_DFU_Setup, USBD_DFU_EP0_TxReady, USBD_DFU_EP0_RxReady, - USBD_DFU_DataIn, - USBD_DFU_DataOut, + NULL, + NULL, USBD_DFU_SOF, - USBD_DFU_IsoINIncomplete, - USBD_DFU_IsoOutIncomplete, + NULL, + NULL, USBD_DFU_GetCfgDesc, USBD_DFU_GetCfgDesc, USBD_DFU_GetCfgDesc, @@ -180,20 +153,20 @@ USBD_ClassTypeDef USBD_DFU = /* USB DFU device Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_DFU_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ - 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x02, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and Supprts Remote Wakeup */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /* 09 */ /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ - USBD_DFU_IF_DESC(0U), /* This interface is mandatory for all devices */ + USBD_DFU_IF_DESC(0U), /* This interface is mandatory for all devices */ #if (USBD_DFU_MAX_ITF_NUM > 1U) /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ @@ -225,21 +198,21 @@ __ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_E #endif /* (USBD_DFU_MAX_ITF_NUM > 6) */ /******************** DFU Functional Descriptor********************/ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ + 0x09, /* blength = 9 Bytes */ + DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor */ + 0x0B, /* bmAttribute: + bitCanDnload = 1 (bit 0) + bitCanUpload = 1 (bit 1) + bitManifestationTolerant = 0 (bit 2) + bitWillDetach = 1 (bit 3) + Reserved (bit4-6) + bitAcceleratedST = 0 (bit 7) */ + 0xFF, /* DetachTimeOut= 255 ms*/ 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported + /* WARNING: In DMA mode the multiple MPS packets feature is still not supported ==> In this case, when using DMA USBD_DFU_XFER_SIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ + TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE), /* TransferSize = 1024 Byte */ + 0x1A, /* bcdDFUVersion */ 0x01 /***********************************************************/ /* 9*/ @@ -275,44 +248,45 @@ __ALIGN_BEGIN static uint8_t USBD_DFU_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_ * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - USBD_DFU_HandleTypeDef *hdfu; + UNUSED(cfgidx); + + USBD_DFU_HandleTypeDef *hdfu; /* Allocate Audio structure */ - pdev->pClassData = USBD_malloc(sizeof(USBD_DFU_HandleTypeDef)); + hdfu = USBD_malloc(sizeof(USBD_DFU_HandleTypeDef)); - if (pdev->pClassData == NULL) + if (hdfu == NULL) { - return USBD_FAIL; + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; } - else + + pdev->pClassData = (void *)hdfu; + + hdfu->alt_setting = 0U; + hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; + hdfu->wblock_num = 0U; + hdfu->wlength = 0U; + + hdfu->manif_state = DFU_MANIFEST_COMPLETE; + hdfu->dev_state = DFU_STATE_IDLE; + + hdfu->dev_status[0] = DFU_ERROR_NONE; + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = DFU_STATE_IDLE; + hdfu->dev_status[5] = 0U; + + /* Initialize Hardware layer */ + if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK) { - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - - hdfu->alt_setting = 0U; - hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; - hdfu->wblock_num = 0U; - hdfu->wlength = 0U; - - hdfu->manif_state = DFU_MANIFEST_COMPLETE; - hdfu->dev_state = DFU_STATE_IDLE; - - hdfu->dev_status[0] = DFU_ERROR_NONE; - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = DFU_STATE_IDLE; - hdfu->dev_status[5] = 0U; - - /* Initialize Hardware layer */ - if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK) - { - return USBD_FAIL; - } + return (uint8_t)USBD_FAIL; } - return USBD_OK; + + return (uint8_t)USBD_OK; } /** @@ -322,12 +296,17 @@ static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - USBD_DFU_HandleTypeDef *hdfu; - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + UNUSED(cfgidx); + USBD_DFU_HandleTypeDef *hdfu; + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_EMEM; + } + + hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; hdfu->wblock_num = 0U; hdfu->wlength = 0U; @@ -335,16 +314,12 @@ static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, hdfu->dev_status[0] = DFU_ERROR_NONE; hdfu->dev_status[4] = DFU_STATE_IDLE; - /* DeInit physical Interface components */ - if (pdev->pClassData != NULL) - { - /* De-Initialize Hardware layer */ - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); - pdev->pClassData = NULL; - } + /* DeInit physical Interface components and Hardware Layer */ + ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -354,129 +329,129 @@ static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, * @param req: usb requests * @retval status */ -static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; - uint8_t *pbuf = 0U; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_OK; + uint8_t *pbuf = NULL; uint16_t len = 0U; uint16_t status_info = 0U; - uint8_t ret = USBD_OK; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - switch (req->bRequest) - { - case DFU_DNLOAD: - DFU_Download(pdev, req); - break; - - case DFU_UPLOAD: - DFU_Upload(pdev, req); - break; - - case DFU_GETSTATUS: - DFU_GetStatus(pdev); - break; - - case DFU_CLRSTATUS: - DFU_ClearStatus(pdev); - break; - - case DFU_GETSTATE: - DFU_GetState(pdev); - break; - - case DFU_ABORT: - DFU_Abort(pdev); - break; - - case DFU_DETACH: - DFU_Detach(pdev, req); - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) + { + case DFU_DNLOAD: + DFU_Download(pdev, req); break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; + case DFU_UPLOAD: + DFU_Upload(pdev, req); + break; - case USB_REQ_GET_DESCRIPTOR: - if ((req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) - { - pbuf = USBD_DFU_CfgDesc + (9U * (USBD_DFU_MAX_ITF_NUM + 1U)); - len = MIN(USB_DFU_DESC_SIZ, req->wLength); - } + case DFU_GETSTATUS: + DFU_GetStatus(pdev); + break; - USBD_CtlSendData(pdev, pbuf, len); - break; + case DFU_CLRSTATUS: + DFU_ClearStatus(pdev); + break; - case USB_REQ_GET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hdfu->alt_setting, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; + case DFU_GETSTATE: + DFU_GetState(pdev); + break; - case USB_REQ_SET_INTERFACE: - if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM) - { - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - hdfu->alt_setting = (uint8_t)(req->wValue); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; + case DFU_ABORT: + DFU_Abort(pdev); + break; - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } + case DFU_DETACH: + DFU_Detach(pdev, req); break; default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) + { + pbuf = USBD_DFU_CfgDesc + (9U * (USBD_DFU_MAX_ITF_NUM + 1U)); + len = MIN(USB_DFU_DESC_SIZ, req->wLength); + } + + (void)USBD_CtlSendData(pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)hdfu->alt_setting, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM) + { + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + hdfu->alt_setting = (uint8_t)(req->wValue); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } @@ -487,25 +462,13 @@ static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length) +static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length) { - *length = sizeof(USBD_DFU_CfgDesc); + *length = (uint16_t)sizeof(USBD_DFU_CfgDesc); + return USBD_DFU_CfgDesc; } -/** - * @brief USBD_DFU_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) -{ - - return USBD_OK; -} /** * @brief USBD_DFU_EP0_RxReady @@ -513,10 +476,11 @@ static uint8_t USBD_DFU_DataIn(USBD_HandleTypeDef *pdev, * @param pdev: device instance * @retval status */ -static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_DFU_EP0_TxReady @@ -526,38 +490,47 @@ static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) */ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) { + USBD_SetupReqTypedef req; uint32_t addr; - USBD_SetupReqTypedef req; - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; if (hdfu->dev_state == DFU_STATE_DNLOAD_BUSY) { /* Decode the Special Command*/ if (hdfu->wblock_num == 0U) { - if ((hdfu->buffer.d8[0] == DFU_CMD_GETCOMMANDS) && (hdfu->wlength == 1U)) + if(hdfu->wlength == 1U) { - - } - else if ((hdfu->buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER) && (hdfu->wlength == 5U)) - { - hdfu->data_ptr = hdfu->buffer.d8[1]; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; - } - else if ((hdfu->buffer.d8[0] == DFU_CMD_ERASE) && (hdfu->wlength == 5U)) - { - hdfu->data_ptr = hdfu->buffer.d8[1]; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; - - if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Erase(hdfu->data_ptr) != USBD_OK) + if (hdfu->buffer.d8[0] == DFU_CMD_GETCOMMANDS) { - return USBD_FAIL; + /* nothink to do */ + } + } + else if (hdfu->wlength == 5U) + { + if (hdfu->buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER) + { + hdfu->data_ptr = hdfu->buffer.d8[1]; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + } + else if (hdfu->buffer.d8[0] == DFU_CMD_ERASE) + { + hdfu->data_ptr = hdfu->buffer.d8[1]; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + + if (DfuInterface->Erase(hdfu->data_ptr) != USBD_OK) + { + return (uint8_t)USBD_FAIL; + } + } + else + { + /* .. */ } } else @@ -580,10 +553,9 @@ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Preform the write operation */ - if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Write(hdfu->buffer.d8, - (uint8_t *)addr, hdfu->wlength) != USBD_OK) + if (DfuInterface->Write(hdfu->buffer.d8, (uint8_t *)addr, hdfu->wlength) != USBD_OK) { - return USBD_FAIL; + return (uint8_t)USBD_FAIL; } } } @@ -599,18 +571,18 @@ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; hdfu->dev_status[4] = hdfu->dev_state; - return USBD_OK; + } + else if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress */ + { + /* Start leaving DFU mode */ + DFU_Leave(pdev); } else { - if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress */ - { - /* Start leaving DFU mode */ - DFU_Leave(pdev); - } + /* .. */ } - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_DFU_SOF @@ -618,48 +590,13 @@ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev) +static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); - return USBD_OK; + return (uint8_t)USBD_OK; } -/** - * @brief USBD_DFU_IsoINIncomplete - * handle data ISO IN Incomplete event - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} -/** - * @brief USBD_DFU_IsoOutIncomplete - * handle data ISO OUT Incomplete event - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - - return USBD_OK; -} -/** - * @brief USBD_DFU_DataOut - * handle data OUT Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum) -{ - - return USBD_OK; -} /** * @brief DeviceQualifierDescriptor @@ -667,9 +604,10 @@ static uint8_t USBD_DFU_DataOut(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) +static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_DFU_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_DFU_DeviceQualifierDesc); + return USBD_DFU_DeviceQualifierDesc; } @@ -685,15 +623,17 @@ static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length) { static uint8_t USBD_StrDesc[255]; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + /* Check if the requested string interface is supported */ if (index <= (USBD_IDX_INTERFACE_STR + USBD_DFU_MAX_ITF_NUM)) { - USBD_GetString((uint8_t *)((USBD_DFU_MediaTypeDef *)pdev->pUserData)->pStrDesc, USBD_StrDesc, length); + USBD_GetString((uint8_t *)DfuInterface->pStrDesc, USBD_StrDesc, length); return USBD_StrDesc; } - /* Not supported Interface Descriptor index */ else { + /* Not supported Interface Descriptor index */ return NULL; } } @@ -704,14 +644,17 @@ static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t inde * @param fops: storage callback * @retval status */ -uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, - USBD_DFU_MediaTypeDef *fops) +uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, + USBD_DFU_MediaTypeDef *fops) { - if (fops != NULL) + if (fops == NULL) { - pdev->pUserData = fops; + return (uint8_t)USBD_FAIL; } - return 0U; + + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /****************************************************************************** @@ -726,13 +669,13 @@ uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, */ static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - - if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC - || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC - || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE) + if ((hdfu->dev_state == DFU_STATE_IDLE) || + (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) { /* Update the state machine */ hdfu->dev_state = DFU_STATE_IDLE; @@ -747,11 +690,11 @@ static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) } /* Check the detach capability in the DFU functional descriptor */ - if ((USBD_DFU_CfgDesc[12U + (9U * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK) + if (((USBD_DFU_CfgDesc[12U + (9U * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK) != 0U) { /* Perform an Attach-Detach operation on USB bus */ - USBD_Stop(pdev); - USBD_Start(pdev); + (void)USBD_Stop(pdev); + (void)USBD_Start(pdev); } else { @@ -769,9 +712,7 @@ static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) */ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; /* Data setup request */ if (req->wLength > 0U) @@ -787,8 +728,7 @@ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) hdfu->dev_status[4] = hdfu->dev_state; /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx(pdev, (uint8_t *)hdfu->buffer.d8, - (uint16_t)hdfu->wlength); + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hdfu->buffer.d8, hdfu->wlength); } /* Unsupported state */ else @@ -801,7 +741,7 @@ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) else { /* End of DNLOAD operation*/ - if (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_IDLE) + if ((hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || (hdfu->dev_state == DFU_STATE_IDLE)) { hdfu->manif_state = DFU_MANIFEST_IN_PROGRESS; hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; @@ -827,12 +767,10 @@ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) */ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - - uint8_t *phaddr = NULL; - uint32_t addr = 0U; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + uint8_t *phaddr; + uint32_t addr; /* Data setup request */ if (req->wLength > 0U) @@ -860,7 +798,7 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) hdfu->buffer.d8[2] = DFU_CMD_ERASE; /* Send the status data over EP0 */ - USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->buffer.d8[0])), 3U); + (void)USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->buffer.d8[0])), 3U); } else if (hdfu->wblock_num > 1U) { @@ -871,13 +809,13 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) hdfu->dev_status[3] = 0U; hdfu->dev_status[4] = hdfu->dev_state; - addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Change is Accelerated*/ + addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Return the physical address where data are stored */ - phaddr = ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength); + phaddr = DfuInterface->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength); /* Send the status data over EP0 */ - USBD_CtlSendData(pdev, phaddr, (uint16_t)hdfu->wlength); + (void)USBD_CtlSendData(pdev, phaddr, hdfu->wlength); } else /* unsupported hdfu->wblock_num */ { @@ -897,6 +835,7 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { hdfu->wlength = 0U; hdfu->wblock_num = 0U; + /* Call the error management function (command will be nacked */ USBD_CtlError(pdev, req); } @@ -921,73 +860,72 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) */ static void DFU_GetStatus(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; switch (hdfu->dev_state) { - case DFU_STATE_DNLOAD_SYNC: - if (hdfu->wlength != 0U) + case DFU_STATE_DNLOAD_SYNC: + if (hdfu->wlength != 0U) + { + hdfu->dev_state = DFU_STATE_DNLOAD_BUSY; + + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; + + if ((hdfu->wblock_num == 0U) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE)) { - hdfu->dev_state = DFU_STATE_DNLOAD_BUSY; - - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; - - if ((hdfu->wblock_num == 0U) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE)) - { - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status); - } - else - { - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status); - } - } - else /* (hdfu->wlength==0)*/ - { - hdfu->dev_state = DFU_STATE_DNLOAD_IDLE; - - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; - } - break; - - case DFU_STATE_MANIFEST_SYNC : - if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS) - { - hdfu->dev_state = DFU_STATE_MANIFEST; - - hdfu->dev_status[1] = 1U; /*bwPollTimeout = 1ms*/ - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; + DfuInterface->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status); } else { - if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && - ((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U)) - { - hdfu->dev_state = DFU_STATE_IDLE; - - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; - } + DfuInterface->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status); } - break; + } + else /* (hdfu->wlength==0)*/ + { + hdfu->dev_state = DFU_STATE_DNLOAD_IDLE; - default : - break; + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; + } + break; + + case DFU_STATE_MANIFEST_SYNC: + if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS) + { + hdfu->dev_state = DFU_STATE_MANIFEST; + + hdfu->dev_status[1] = 1U; /*bwPollTimeout = 1ms*/ + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; + } + else + { + if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && + (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U)) + { + hdfu->dev_state = DFU_STATE_IDLE; + + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; + } + } + break; + + default: + break; } /* Send the status data over EP0 */ - USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->dev_status[0])), 6U); + (void)USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->dev_status[0])), 6U); } /** @@ -998,30 +936,28 @@ static void DFU_GetStatus(USBD_HandleTypeDef *pdev) */ static void DFU_ClearStatus(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; if (hdfu->dev_state == DFU_STATE_ERROR) { hdfu->dev_state = DFU_STATE_IDLE; - hdfu->dev_status[0] = DFU_ERROR_NONE;/*bStatus*/ + hdfu->dev_status[0] = DFU_ERROR_NONE; /*bStatus*/ hdfu->dev_status[1] = 0U; hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ - hdfu->dev_status[4] = hdfu->dev_state;/*bState*/ - hdfu->dev_status[5] = 0U;/*iString*/ + hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + hdfu->dev_status[5] = 0U; /*iString*/ } else { /*State Error*/ hdfu->dev_state = DFU_STATE_ERROR; - hdfu->dev_status[0] = DFU_ERROR_UNKNOWN;/*bStatus*/ + hdfu->dev_status[0] = DFU_ERROR_UNKNOWN; /*bStatus*/ hdfu->dev_status[1] = 0U; hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ - hdfu->dev_status[4] = hdfu->dev_state;/*bState*/ - hdfu->dev_status[5] = 0U;/*iString*/ + hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + hdfu->dev_status[5] = 0U; /*iString*/ } } @@ -1033,12 +969,10 @@ static void DFU_ClearStatus(USBD_HandleTypeDef *pdev) */ static void DFU_GetState(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; /* Return the current state of the DFU interface */ - USBD_CtlSendData(pdev, &hdfu->dev_state, 1U); + (void)USBD_CtlSendData(pdev, &hdfu->dev_state, 1U); } /** @@ -1049,13 +983,14 @@ static void DFU_GetState(USBD_HandleTypeDef *pdev) */ static void DFU_Abort(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC - || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC - || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE) + if ((hdfu->dev_state == DFU_STATE_IDLE) || + (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) { hdfu->dev_state = DFU_STATE_IDLE; hdfu->dev_status[0] = DFU_ERROR_NONE; @@ -1078,13 +1013,11 @@ static void DFU_Abort(USBD_HandleTypeDef *pdev) */ static void DFU_Leave(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; hdfu->manif_state = DFU_MANIFEST_COMPLETE; - if ((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) + if (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U) { hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; @@ -1104,10 +1037,7 @@ static void DFU_Leave(USBD_HandleTypeDef *pdev) hdfu->dev_status[4] = hdfu->dev_state; /* Disconnect the USB device */ - USBD_Stop(pdev); - - /* DeInitilialize the MAL(Media Access Layer) */ - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); + (void)USBD_Stop(pdev); /* Generate system reset to allow jumping to the user code */ NVIC_SystemReset(); diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h index 030927b..988ba1f 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h @@ -88,53 +88,50 @@ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); -USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); /* USBD Low Level Driver */ -USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_mps); +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr); -USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t ep_type, uint16_t ep_mps); -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr); +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t *pbuf, uint32_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t *pbuf, uint32_t size); + +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr); + void USBD_LL_Delay(uint32_t Delay); /** diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h index 25a4758..a4bfc44 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h @@ -73,16 +73,14 @@ extern "C" { * @{ */ -USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - - -void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata); - void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); + /** * @} */ diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index 8d7502f..8219140 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -65,6 +65,10 @@ extern "C" { #define USBD_SUPPORT_USER_STRING_DESC 0U #endif /* USBD_SUPPORT_USER_STRING_DESC */ +#ifndef USBD_CLASS_USER_STRING_DESC +#define USBD_CLASS_USER_STRING_DESC 0U +#endif /* USBD_CLASS_USER_STRING_DESC */ + #define USB_LEN_DEV_QUALIFIER_DESC 0x0AU #define USB_LEN_DEV_DESC 0x12U #define USB_LEN_CFG_DESC 0x09U @@ -165,6 +169,28 @@ typedef struct usb_setup_req uint16_t wLength; } USBD_SetupReqTypedef; +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t wDescriptorLengthLow; + uint8_t wDescriptorLengthHigh; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} USBD_ConfigDescTypedef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} USBD_BosDescTypedef; + + struct _USBD_HandleTypeDef; typedef struct _Device_cb @@ -203,34 +229,39 @@ typedef enum /* Following USB Device status */ typedef enum { - USBD_OK = 0U, + USBD_OK = 0U, USBD_BUSY, + USBD_EMEM, USBD_FAIL, } USBD_StatusTypeDef; /* USB Device descriptors structure */ typedef struct { - uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); -#if (USBD_LPM_ENABLED == 1U) - uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); +#if (USBD_CLASS_USER_STRING_DESC == 1) + uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif +#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1)) + uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); #endif } USBD_DescriptorsTypeDef; /* USB Device handle structure */ typedef struct { - uint32_t status; - uint32_t is_used; - uint32_t total_length; - uint32_t rem_length; - uint32_t maxpacket; + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; + uint16_t is_used; + uint16_t bInterval; } USBD_EndpointTypeDef; /* USB Device handle structure */ @@ -251,6 +282,7 @@ typedef struct _USBD_HandleTypeDef uint8_t dev_connection_status; uint8_t dev_test_mode; uint32_t dev_remote_wakeup; + uint8_t ConfIdx; USBD_SetupReqTypedef request; USBD_DescriptorsTypeDef *pDesc; @@ -258,6 +290,8 @@ typedef struct _USBD_HandleTypeDef void *pClassData; void *pUserData; void *pData; + void *pBosDesc; + void *pConfDesc; } USBD_HandleTypeDef; /** @@ -269,8 +303,19 @@ typedef struct _USBD_HandleTypeDef /** @defgroup USBD_DEF_Exported_Macros * @{ */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) +__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) +{ + uint16_t _SwapVal, _Byte1, _Byte2; + uint8_t *_pbuff = addr; + + _Byte1 = *(uint8_t *)_pbuff; + _pbuff++; + _Byte2 = *(uint8_t *)_pbuff; + + _SwapVal = (_Byte2 << 8) | _Byte1; + + return _SwapVal; +} #define LOBYTE(x) ((uint8_t)((x) & 0x00FFU)) #define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h index 8a6dd5f..8f077c7 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h @@ -77,27 +77,22 @@ extern "C" { * @{ */ -USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev); - -uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr); /** * @} diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c index b1a60ae..e3db03f 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -89,6 +89,8 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { + USBD_StatusTypeDef ret; + /* Check whether the USB Host handle is valid */ if (pdev == NULL) { @@ -98,12 +100,17 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, return USBD_FAIL; } - /* Unlink previous class*/ + /* Unlink previous class */ if (pdev->pClass != NULL) { pdev->pClass = NULL; } + if (pdev->pConfDesc != NULL) + { + pdev->pConfDesc = NULL; + } + /* Assign USBD Descriptors */ if (pdesc != NULL) { @@ -113,10 +120,11 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; pdev->id = id; - /* Initialize low level driver */ - USBD_LL_Init(pdev); - return USBD_OK; + /* Initialize low level driver */ + ret = USBD_LL_Init(pdev); + + return ret; } /** @@ -127,19 +135,34 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, */ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) { + USBD_StatusTypeDef ret; + /* Set Default State */ pdev->dev_state = USBD_STATE_DEFAULT; /* Free Class Resources */ - pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } + + if (pdev->pConfDesc != NULL) + { + pdev->pConfDesc = NULL; + } /* Stop the low level driver */ - USBD_LL_Stop(pdev); + ret = USBD_LL_Stop(pdev); + + if (ret != USBD_OK) + { + return ret; + } /* Initialize low level driver */ - USBD_LL_DeInit(pdev); + ret = USBD_LL_DeInit(pdev); - return USBD_OK; + return ret; } /** @@ -149,24 +172,30 @@ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) * @param pclass: Class handle * @retval USBD Status */ -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { - USBD_StatusTypeDef status = USBD_OK; - if (pclass != NULL) - { - /* link the class to the USB Device handle */ - pdev->pClass = pclass; - status = USBD_OK; - } - else + uint16_t len = 0U; + + if (pclass == NULL) { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif - status = USBD_FAIL; + return USBD_FAIL; } - return status; + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + + /* Get Device Configuration Descriptor */ +#ifdef USE_USB_FS + pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len); +#else /* USE_USB_HS */ + pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len); +#endif /* USE_USB_FS */ + + + return USBD_OK; } /** @@ -175,12 +204,10 @@ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeD * @param pdev: Device Handle * @retval USBD Status */ -USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { /* Start the low level driver */ - USBD_LL_Start(pdev); - - return USBD_OK; + return USBD_LL_Start(pdev); } /** @@ -189,15 +216,25 @@ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) * @param pdev: Device Handle * @retval USBD Status */ -USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) { + USBD_StatusTypeDef ret; + /* Free Class Resources */ - pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } + + if (pdev->pConfDesc != NULL) + { + pdev->pConfDesc = NULL; + } /* Stop the low level driver */ - USBD_LL_Stop(pdev); + ret = USBD_LL_Stop(pdev); - return USBD_OK; + return ret; } /** @@ -206,7 +243,7 @@ USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { /* Prevent unused argument compilation warning */ UNUSED(pdev); @@ -222,17 +259,14 @@ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) * @retval status */ -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { USBD_StatusTypeDef ret = USBD_FAIL; if (pdev->pClass != NULL) { - /* Set configuration and Start the Class*/ - if (pdev->pClass->Init(pdev, cfgidx) == 0U) - { - ret = USBD_OK; - } + /* Set configuration and Start the Class */ + ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx); } return ret; @@ -245,10 +279,13 @@ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - /* Clear configuration and De-initialize the Class process*/ - pdev->pClass->DeInit(pdev, cfgidx); + /* Clear configuration and De-initialize the Class process */ + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, cfgidx); + } return USBD_OK; } @@ -262,6 +299,8 @@ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { + USBD_StatusTypeDef ret; + USBD_ParseSetupRequest(&pdev->request, psetup); pdev->ep0_state = USBD_EP0_SETUP; @@ -271,23 +310,23 @@ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) switch (pdev->request.bmRequest & 0x1FU) { case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq(pdev, &pdev->request); + ret = USBD_StdDevReq(pdev, &pdev->request); break; case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &pdev->request); + ret = USBD_StdItfReq(pdev, &pdev->request); break; case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &pdev->request); + ret = USBD_StdEPReq(pdev, &pdev->request); break; default: - USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); + ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); break; } - return USBD_OK; + return ret; } /** @@ -301,6 +340,7 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { USBD_EndpointTypeDef *pep; + USBD_StatusTypeDef ret; if (epnum == 0U) { @@ -312,8 +352,7 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, { pep->rem_length -= pep->maxpacket; - USBD_CtlContinueRx(pdev, pdata, - (uint16_t)MIN(pep->rem_length, pep->maxpacket)); + (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); } else { @@ -322,25 +361,32 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, { pdev->pClass->EP0_RxReady(pdev); } - USBD_CtlSendStatus(pdev); + (void)USBD_CtlSendStatus(pdev); } } else { +#if 0 if (pdev->ep0_state == USBD_EP0_STATUS_OUT) { /* * STATUS PHASE completed, update ep0_state to idle */ pdev->ep0_state = USBD_EP0_IDLE; - USBD_LL_StallEP(pdev, 0U); + (void)USBD_LL_StallEP(pdev, 0U); } +#endif } } else if ((pdev->pClass->DataOut != NULL) && (pdev->dev_state == USBD_STATE_CONFIGURED)) { - pdev->pClass->DataOut(pdev, epnum); + ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum); + + if (ret != USBD_OK) + { + return ret; + } } else { @@ -362,6 +408,7 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { USBD_EndpointTypeDef *pep; + USBD_StatusTypeDef ret; if (epnum == 0U) { @@ -373,23 +420,23 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, { pep->rem_length -= pep->maxpacket; - USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length); + (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); } else { /* last packet is MPS multiple, so send ZLP packet */ - if ((pep->total_length % pep->maxpacket == 0U) && + if ((pep->maxpacket == pep->rem_length) && (pep->total_length >= pep->maxpacket) && (pep->total_length < pdev->ep0_data_len)) { - USBD_CtlContinueSendData(pdev, NULL, 0U); + (void)USBD_CtlContinueSendData(pdev, NULL, 0U); pdev->ep0_data_len = 0U; /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); } else { @@ -398,30 +445,37 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, { pdev->pClass->EP0_TxSent(pdev); } - USBD_LL_StallEP(pdev, 0x80U); - USBD_CtlReceiveStatus(pdev); + (void)USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_CtlReceiveStatus(pdev); } } } else { +#if 0 if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || (pdev->ep0_state == USBD_EP0_IDLE)) { - USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_LL_StallEP(pdev, 0x80U); } +#endif } if (pdev->dev_test_mode == 1U) { - USBD_RunTestMode(pdev); + (void)USBD_RunTestMode(pdev); pdev->dev_test_mode = 0U; } } else if ((pdev->pClass->DataIn != NULL) && (pdev->dev_state == USBD_STATE_CONFIGURED)) { - pdev->pClass->DataIn(pdev, epnum); + ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum); + + if (ret != USBD_OK) + { + return ret; + } } else { @@ -441,29 +495,29 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { - /* Open EP0 OUT */ - USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); - pdev->ep_out[0x00U & 0xFU].is_used = 1U; - - pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; - - /* Open EP0 IN */ - USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); - pdev->ep_in[0x80U & 0xFU].is_used = 1U; - - pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; - /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; pdev->ep0_state = USBD_EP0_IDLE; pdev->dev_config = 0U; pdev->dev_remote_wakeup = 0U; - if (pdev->pClassData) + if (pdev->pClassData != NULL) { pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); } + /* Open EP0 OUT */ + (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_out[0x00U & 0xFU].is_used = 1U; + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_in[0x80U & 0xFU].is_used = 1U; + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + return USBD_OK; } @@ -490,8 +544,8 @@ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { - pdev->dev_old_state = pdev->dev_state; - pdev->dev_state = USBD_STATE_SUSPENDED; + pdev->dev_old_state = pdev->dev_state; + pdev->dev_state = USBD_STATE_SUSPENDED; return USBD_OK; } @@ -589,7 +643,11 @@ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; - pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } return USBD_OK; } diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c index e57c1bc..c51f349 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -71,27 +71,13 @@ /** @defgroup USBD_REQ_Private_FunctionPrototypes * @{ */ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_SetAddress(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_SetConfig(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_GetConfig(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_GetStatus(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_SetFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); static uint8_t USBD_GetLen(uint8_t *buf); /** @@ -111,58 +97,57 @@ static uint8_t USBD_GetLen(uint8_t *buf); * @param req: usb request * @retval status */ -USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - case USB_REQ_TYPE_VENDOR: - pdev->pClass->Setup(pdev, req); + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor(pdev, req); break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - USBD_GetDescriptor(pdev, req); - break; + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; + case USB_REQ_SET_CONFIGURATION: + ret = USBD_SetConfig(pdev, req); + break; - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig(pdev, req); - break; + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig(pdev, req); + break; - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig(pdev, req); - break; + case USB_REQ_GET_STATUS: + USBD_GetStatus(pdev, req); + break; - case USB_REQ_GET_STATUS: - USBD_GetStatus(pdev, req); - break; + case USB_REQ_SET_FEATURE: + USBD_SetFeature(pdev, req); + break; - case USB_REQ_SET_FEATURE: - USBD_SetFeature(pdev, req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature(pdev, req); - break; - - default: - USBD_CtlError(pdev, req); - break; - } + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature(pdev, req); break; default: USBD_CtlError(pdev, req); break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; } return ret; @@ -175,49 +160,48 @@ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - case USB_REQ_TYPE_VENDOR: - case USB_REQ_TYPE_STANDARD: - switch (pdev->dev_state) + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + case USB_REQ_TYPE_STANDARD: + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) { - case USBD_STATE_DEFAULT: - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); - if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) - { - ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); - - if ((req->wLength == 0U) && (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev, req); - } - break; - - default: - USBD_CtlError(pdev, req); - break; + if ((req->wLength == 0U) && (ret == USBD_OK)) + { + (void)USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev, req); } break; default: USBD_CtlError(pdev, req); break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; } - return USBD_OK; + return ret; } /** @@ -227,168 +211,159 @@ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { USBD_EndpointTypeDef *pep; - uint8_t ep_addr; + uint8_t ep_addr; USBD_StatusTypeDef ret = USBD_OK; - ep_addr = LOBYTE(req->wIndex); + ep_addr = LOBYTE(req->wIndex); switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - case USB_REQ_TYPE_VENDOR: - pdev->pClass->Setup(pdev, req); + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_SET_FEATURE: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + (void)USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + } + } + (void)USBD_CtlSendStatus(pdev); + + break; + + default: + USBD_CtlError(pdev, req); + break; + } break; - case USB_REQ_TYPE_STANDARD: - /* Check if it is a class request */ - if ((req->bmRequest & 0x60U) == 0x20U) - { - ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + case USB_REQ_CLEAR_FEATURE: - return ret; + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + (void)USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7FU) != 0x00U) + { + (void)USBD_LL_ClearStallEP(pdev, ep_addr); + } + (void)USBD_CtlSendStatus(pdev); + (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + } + break; + + default: + USBD_CtlError(pdev, req); + break; } + break; - switch (req->bRequest) + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) { - case USB_REQ_SET_FEATURE: - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - { - USBD_LL_StallEP(pdev, ep_addr); - USBD_LL_StallEP(pdev, 0x80U); - } - else - { - USBD_CtlError(pdev, req); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00U) && - (ep_addr != 0x80U) && (req->wLength == 0x00U)) - { - USBD_LL_StallEP(pdev, ep_addr); - } - } - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev, req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE: - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - { - USBD_LL_StallEP(pdev, ep_addr); - USBD_LL_StallEP(pdev, 0x80U); - } - else - { - USBD_CtlError(pdev, req); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr & 0x7FU) != 0x00U) - { - USBD_LL_ClearStallEP(pdev, ep_addr); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev, req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - { - USBD_CtlError(pdev, req); - break; - } - pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - &pdev->ep_out[ep_addr & 0x7FU]; - - pep->status = 0x0000U; - - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); - break; - - case USBD_STATE_CONFIGURED: - if ((ep_addr & 0x80U) == 0x80U) - { - if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) - { - USBD_CtlError(pdev, req); - break; - } - } - else - { - if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) - { - USBD_CtlError(pdev, req); - break; - } - } - - pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - &pdev->ep_out[ep_addr & 0x7FU]; - - if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) - { - pep->status = 0x0000U; - } - else if (USBD_LL_IsStallEP(pdev, ep_addr)) - { - pep->status = 0x0001U; - } - else - { - pep->status = 0x0000U; - } - - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); - break; - - default: - USBD_CtlError(pdev, req); - break; - } - break; - - default: + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { USBD_CtlError(pdev, req); break; + } + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; + + pep->status = 0x0000U; + + (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + break; + + case USBD_STATE_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) + { + if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + else + { + if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; + + if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) + { + pep->status = 0x0000U; + } + else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) + { + pep->status = 0x0001U; + } + else + { + pep->status = 0x0000U; + } + + (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + break; + + default: + USBD_CtlError(pdev, req); + break; } break; default: USBD_CtlError(pdev, req); break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; } return ret; @@ -402,8 +377,7 @@ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { uint16_t len = 0U; uint8_t *pbuf = NULL; @@ -411,134 +385,43 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, switch (req->wValue >> 8) { -#if (USBD_LPM_ENABLED == 1U) - case USB_DESC_TYPE_BOS: - if (pdev->pDesc->GetBOSDescriptor != NULL) - { - pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; +#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) + case USB_DESC_TYPE_BOS: + if (pdev->pDesc->GetBOSDescriptor != NULL) + { + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; #endif - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); - break; + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; - case USB_DESC_TYPE_CONFIGURATION: - if (pdev->dev_speed == USBD_SPEED_HIGH) + case USB_DESC_TYPE_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetHSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { + pbuf = pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + if (pdev->pDesc->GetLangIDStrDescriptor != NULL) { - pbuf = pdev->pClass->GetHSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - else - { - pbuf = pdev->pClass->GetFSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - if (pdev->pDesc->GetLangIDStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_MFC_STR: - if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_PRODUCT_STR: - if (pdev->pDesc->GetProductStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_SERIAL_STR: - if (pdev->pDesc->GetSerialStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_CONFIG_STR: - if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_INTERFACE_STR: - if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - default: -#if (USBD_SUPPORT_USER_STRING_DESC == 1U) - if (pdev->pClass->GetUsrStrDescriptor != NULL) - { - pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; -#else - USBD_CtlError(pdev, req); - err++; -#endif - } - break; - - case USB_DESC_TYPE_DEVICE_QUALIFIER: - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); } else { @@ -547,11 +430,58 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, } break; - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: - if (pdev->dev_speed == USBD_SPEED_HIGH) + case USBD_IDX_MFC_STR: + if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) { - pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_PRODUCT_STR: + if (pdev->pDesc->GetProductStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_SERIAL_STR: + if (pdev->pDesc->GetSerialStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_CONFIG_STR: + if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USBD_IDX_INTERFACE_STR: + if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); } else { @@ -561,9 +491,63 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, break; default: +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + if (pdev->pClass->GetUsrStrDescriptor != NULL) + { + pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } +#elif (USBD_CLASS_USER_STRING_DESC == 1U) + if (pdev->pDesc->GetUserStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetUserStrDescriptor(pdev->dev_speed, (req->wValue), &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } +#else USBD_CtlError(pdev, req); err++; +#endif break; + } + break; + + case USB_DESC_TYPE_DEVICE_QUALIFIER: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + default: + USBD_CtlError(pdev, req); + err++; + break; } if (err != 0U) @@ -572,13 +556,19 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, } else { - if ((len != 0U) && (req->wLength != 0U)) + if (req->wLength != 0U) { - len = MIN(len, req->wLength); - (void)USBD_CtlSendData(pdev, pbuf, len); + if (len != 0U) + { + len = MIN(len, req->wLength); + (void)USBD_CtlSendData(pdev, pbuf, len); + } + else + { + USBD_CtlError(pdev, req); + } } - - if (req->wLength == 0U) + else { (void)USBD_CtlSendStatus(pdev); } @@ -592,8 +582,7 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_SetAddress(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { uint8_t dev_addr; @@ -608,8 +597,8 @@ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, else { pdev->dev_address = dev_addr; - USBD_LL_SetUSBAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); + (void)USBD_LL_SetUSBAddress(pdev, dev_addr); + (void)USBD_CtlSendStatus(pdev); if (dev_addr != 0U) { @@ -634,8 +623,9 @@ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_StatusTypeDef ret = USBD_OK; static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); @@ -643,63 +633,77 @@ static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) if (cfgidx > USBD_MAX_NUM_CONFIGURATION) { USBD_CtlError(pdev, req); + return USBD_FAIL; } - else + + switch (pdev->dev_state) { - switch (pdev->dev_state) + case USBD_STATE_ADDRESSED: + if (cfgidx != 0U) { - case USBD_STATE_ADDRESSED: - if (cfgidx) - { - pdev->dev_config = cfgidx; - pdev->dev_state = USBD_STATE_CONFIGURED; - if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev, req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; + pdev->dev_config = cfgidx; - case USBD_STATE_CONFIGURED: - if (cfgidx == 0U) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - pdev->dev_config = cfgidx; - USBD_ClrClassConfig(pdev, cfgidx); - USBD_CtlSendStatus(pdev); - } - else if (cfgidx != pdev->dev_config) - { - /* Clear old configuration */ - USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + ret = USBD_SetClassConfig(pdev, cfgidx); - /* set new configuration */ - pdev->dev_config = cfgidx; - if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev, req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: + if (ret != USBD_OK) + { USBD_CtlError(pdev, req); - USBD_ClrClassConfig(pdev, cfgidx); - break; + } + else + { + (void)USBD_CtlSendStatus(pdev); + pdev->dev_state = USBD_STATE_CONFIGURED; + } } + else + { + (void)USBD_CtlSendStatus(pdev); + } + break; + + case USBD_STATE_CONFIGURED: + if (cfgidx == 0U) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + (void)USBD_ClrClassConfig(pdev, cfgidx); + (void)USBD_CtlSendStatus(pdev); + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + + ret = USBD_SetClassConfig(pdev, cfgidx); + + if (ret != USBD_OK) + { + USBD_CtlError(pdev, req); + (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + break; + + default: + USBD_CtlError(pdev, req); + (void)USBD_ClrClassConfig(pdev, cfgidx); + ret = USBD_FAIL; + break; } + + return ret; } /** @@ -719,19 +723,19 @@ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { switch (pdev->dev_state) { - case USBD_STATE_DEFAULT: - case USBD_STATE_ADDRESSED: - pdev->dev_default_config = 0U; - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U); - break; + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0U; + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + break; - case USBD_STATE_CONFIGURED: - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U); - break; + case USBD_STATE_CONFIGURED: + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); + break; - default: - USBD_CtlError(pdev, req); - break; + default: + USBD_CtlError(pdev, req); + break; } } } @@ -747,32 +751,32 @@ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { switch (pdev->dev_state) { - case USBD_STATE_DEFAULT: - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - if (req->wLength != 0x2U) - { - USBD_CtlError(pdev, req); - break; - } - -#if (USBD_SELF_POWERED == 1U) - pdev->dev_config_status = USB_CONFIG_SELF_POWERED; -#else - pdev->dev_config_status = 0U; -#endif - - if (pdev->dev_remote_wakeup) - { - pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; - } - - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U); - break; - - default: + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wLength != 0x2U) + { USBD_CtlError(pdev, req); break; + } + +#if (USBD_SELF_POWERED == 1U) + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; +#else + pdev->dev_config_status = 0U; +#endif + + if (pdev->dev_remote_wakeup != 0U) + { + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + } + + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); + break; + + default: + USBD_CtlError(pdev, req); + break; } } @@ -784,13 +788,12 @@ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) * @param req: usb request * @retval status */ -static void USBD_SetFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { pdev->dev_remote_wakeup = 1U; - USBD_CtlSendStatus(pdev); + (void)USBD_CtlSendStatus(pdev); } } @@ -802,8 +805,7 @@ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { switch (pdev->dev_state) { @@ -813,7 +815,7 @@ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { pdev->dev_remote_wakeup = 0U; - USBD_CtlSendStatus(pdev); + (void)USBD_CtlSendStatus(pdev); } break; @@ -833,12 +835,23 @@ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { - req->bmRequest = *(uint8_t *)(pdata); - req->bRequest = *(uint8_t *)(pdata + 1U); - req->wValue = SWAPBYTE(pdata + 2U); - req->wIndex = SWAPBYTE(pdata + 4U); - req->wLength = SWAPBYTE(pdata + 6U); + uint8_t *pbuff = pdata; + req->bmRequest = *(uint8_t *)(pbuff); + + pbuff++; + req->bRequest = *(uint8_t *)(pbuff); + + pbuff++; + req->wValue = SWAPBYTE(pbuff); + + pbuff++; + pbuff++; + req->wIndex = SWAPBYTE(pbuff); + + pbuff++; + pbuff++; + req->wLength = SWAPBYTE(pbuff); } /** @@ -849,11 +862,12 @@ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) * @retval None */ -void USBD_CtlError(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_LL_StallEP(pdev, 0x80U); - USBD_LL_StallEP(pdev, 0U); + UNUSED(req); + + (void)USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_LL_StallEP(pdev, 0U); } @@ -868,18 +882,29 @@ void USBD_CtlError(USBD_HandleTypeDef *pdev, void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { uint8_t idx = 0U; + uint8_t *pdesc; - if (desc != NULL) + if (desc == NULL) { - *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U; - unicode[idx++] = *(uint8_t *)(void *)len; - unicode[idx++] = USB_DESC_TYPE_STRING; + return; + } - while (*desc != '\0') - { - unicode[idx++] = *desc++; - unicode[idx++] = 0U; - } + pdesc = desc; + *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; + + unicode[idx] = *(uint8_t *)len; + idx++; + unicode[idx] = USB_DESC_TYPE_STRING; + idx++; + + while (*pdesc != (uint8_t)'\0') + { + unicode[idx] = *pdesc; + pdesc++; + idx++; + + unicode[idx] = 0U; + idx++; } } @@ -892,11 +917,12 @@ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) static uint8_t USBD_GetLen(uint8_t *buf) { uint8_t len = 0U; + uint8_t *pbuff = buf; - while (*buf != '\0') + while (*pbuff != (uint8_t)'\0') { len++; - buf++; + pbuff++; } return len; diff --git a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c index 3351972..4d5c8ef 100644 --- a/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c +++ b/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c @@ -85,15 +85,15 @@ * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; pdev->ep_in[0].total_length = len; - pdev->ep_in[0].rem_length = len; + pdev->ep_in[0].rem_length = len; /* Start the transfer */ - USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); return USBD_OK; } @@ -107,10 +107,10 @@ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { /* Start the next transfer */ - USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); return USBD_OK; } @@ -124,15 +124,15 @@ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; pdev->ep_out[0].total_length = len; - pdev->ep_out[0].rem_length = len; + pdev->ep_out[0].rem_length = len; /* Start the transfer */ - USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); return USBD_OK; } @@ -146,9 +146,9 @@ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { - USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); return USBD_OK; } @@ -165,7 +165,7 @@ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) pdev->ep0_state = USBD_EP0_STATUS_IN; /* Start the transfer */ - USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); + (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); return USBD_OK; } @@ -182,7 +182,7 @@ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) pdev->ep0_state = USBD_EP0_STATUS_OUT; /* Start the transfer */ - USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); return USBD_OK; } diff --git a/STM32H750VBTx_FLASH.ld b/STM32H750VBTx_FLASH.ld index e20e593..9dc7748 100644 --- a/STM32H750VBTx_FLASH.ld +++ b/STM32H750VBTx_FLASH.ld @@ -55,7 +55,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = 0x20020000; /* end of RAM */ /* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x1000; /* required amount of heap */ +_Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Specify the memory areas */ diff --git a/STM32H750VB_Bootloader.ioc b/STM32H750VB_Bootloader.ioc index 3f217e6..f63b3ea 100644 --- a/STM32H750VB_Bootloader.ioc +++ b/STM32H750VB_Bootloader.ioc @@ -1,253 +1,265 @@ #MicroXplorer Configuration settings - do not modify -CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS -CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS -CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0x0 -CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000 -CORTEX_M7.CPU_DCache=Disabled -CORTEX_M7.CPU_ICache=Enabled -CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE -CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE -CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE -CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings -CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_BUFFERABLE -CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE -CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE -CORTEX_M7.MPU_Control=__NULL -CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB -CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_8MB -File.Version=6 -KeepUserPlacement=false Mcu.Family=STM32H7 -Mcu.IP0=CORTEX_M7 -Mcu.IP1=DEBUG -Mcu.IP2=NVIC -Mcu.IP3=QUADSPI +NVIC.FLASH_IRQn=true\:0\:0\:false\:false\:true\:true\:true +QUADSPI.ClockMode=QSPI_CLOCK_MODE_3 +RCC.DIVQ2Freq_Value=16000000 +ProjectManager.MainLocation=Core/Src +USB_DEVICE.CLASS_NAME_FS=DFU +RCC.SAI1Freq_Value=160000000 +RCC.CortexFreq_Value=80000000 +ProjectManager.KeepUserCode=true +Mcu.UserName=STM32H750VBTx +QUADSPI.ClockPrescaler=2 +RCC.HPRE=RCC_HCLK_DIV2 +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +USART1.BaudRate=921600 +PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_QUADSPI_Init-QUADSPI-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +PA11.Mode=Device_Only +RCC.RTCFreq_Value=32000 +RCC.CpuClockFreq_Value=80000000 +RCC.VCO2OutputFreq_Value=32000000 +NVIC.OTG_FS_EP1_IN_IRQn=true\:1\:0\:true\:false\:true\:true\:true +USART1.IPParameters=VirtualMode-Asynchronous,BaudRate +VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Mode=DFU_FS +PinOutPanel.RotationAngle=0 +RCC.MCO1PinFreq_Value=64000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +ProjectManager.StackSize=0x400 +RCC.AHB4Freq_Value=40000000 +RCC.VCOInput3Freq_Value=320000 +RCC.LPTIM1Freq_Value=20000000 +PD13.Signal=QUADSPI_BK1_IO3 Mcu.IP4=RCC Mcu.IP5=SYS -Mcu.IP6=USART1 -Mcu.IP7=USB_DEVICE -Mcu.IP8=USB_OTG_FS +PD13.Locked=true +Mcu.IP2=NVIC +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.IP3=QUADSPI +Mcu.IP0=CORTEX_M7 +PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE +Mcu.IP1=DEBUG +PA12.Signal=USB_OTG_FS_DP +Mcu.UserConstants= +RCC.DIVP3Freq_Value=38400000 +RCC.SDMMCFreq_Value=160000000 +Mcu.ThirdPartyNb=0 +RCC.HCLKFreq_Value=40000000 +RCC.I2C4Freq_Value=20000000 +PE2.Mode=Single Bank 1 Mcu.IPNb=9 -Mcu.Name=STM32H750VBTx -Mcu.Package=LQFP100 +ProjectManager.PreviousToolchain=SW4STM32 +PB6.Signal=QUADSPI_BK1_NCS +RCC.SPDIFRXFreq_Value=160000000 +PB6.Mode=Single Bank 1 +RCC.DIVQ3Freq_Value=15360000 +Mcu.Pin6=PA1 +Mcu.Pin7=PB2 +Mcu.Pin8=PD11 +Mcu.Pin9=PD12 +QUADSPI.FlashSize=24 Mcu.Pin0=PE2 Mcu.Pin1=PE3 -Mcu.Pin10=PA9 -Mcu.Pin11=PA10 -Mcu.Pin12=PA11 -Mcu.Pin13=PA12 -Mcu.Pin14=PA13 (JTMS/SWDIO) -Mcu.Pin15=PA14 (JTCK/SWCLK) -Mcu.Pin16=PB6 -Mcu.Pin17=VP_SYS_VS_Systick -Mcu.Pin18=VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS +GPIO.groupedBy=Group By Peripherals Mcu.Pin2=PC14-OSC32_IN (OSC32_IN) +RCC.HRTIMFreq_Value=40000000 Mcu.Pin3=PC15-OSC32_OUT (OSC32_OUT) Mcu.Pin4=PH0-OSC_IN (PH0) Mcu.Pin5=PH1-OSC_OUT (PH1) -Mcu.Pin6=PB2 -Mcu.Pin7=PD11 -Mcu.Pin8=PD12 -Mcu.Pin9=PD13 -Mcu.PinsNb=19 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32H750VBTx -MxCube.Version=5.4.0 -MxDb.Version=DB.5.0.40 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.FLASH_IRQn=true\:0\:0\:false\:false\:true\:true\:true -NVIC.FPU_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.ForceEnableDMAVector=true -NVIC.HSEM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true -NVIC.OTG_FS_EP1_IN_IRQn=true\:1\:0\:true\:false\:true\:true\:true -NVIC.OTG_FS_EP1_OUT_IRQn=true\:1\:0\:true\:false\:true\:true\:true -NVIC.OTG_FS_IRQn=true\:2\:0\:true\:false\:true\:false\:true -NVIC.PVD_AVD_IRQn=true\:0\:0\:false\:false\:true\:true\:true -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.QUADSPI_IRQn=true\:1\:0\:true\:false\:true\:true\:true -NVIC.RCC_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -NVIC.USART1_IRQn=true\:1\:0\:true\:false\:true\:true\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.Mode=Device_Only -PA12.Signal=USB_OTG_FS_DP -PA13\ (JTMS/SWDIO).Mode=Serial_Wire -PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO -PA14\ (JTCK/SWCLK).Mode=Serial_Wire -PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB2.Mode=Single Bank 1 -PB2.Signal=QUADSPI_CLK -PB6.Locked=true -PB6.Mode=Single Bank 1 -PB6.Signal=QUADSPI_BK1_NCS -PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT -PCC.Checker=true -PCC.Line=STM32H750 Value line -PCC.MCU=STM32H750VBTx -PCC.PartNumber=STM32H750VBTx -PCC.Seq0=0 -PCC.Series=STM32H7 -PCC.Temperature=25 -PCC.Vdd=3.0 -PD11.Mode=Single Bank 1 -PD11.Signal=QUADSPI_BK1_IO0 -PD12.Mode=Single Bank 1 -PD12.Signal=QUADSPI_BK1_IO1 -PD13.Locked=true -PD13.Mode=Single Bank 1 -PD13.Signal=QUADSPI_BK1_IO3 -PE2.Mode=Single Bank 1 -PE2.Signal=QUADSPI_BK1_IO2 -PE3.GPIOParameters=GPIO_PuPd -PE3.GPIO_PuPd=GPIO_PULLUP -PE3.Locked=true -PE3.Signal=GPIO_Input -PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator -PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +ProjectManager.ProjectBuild=false PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator -PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true +RCC.DIVR3Freq_Value=38400000 +RCC.HSE_VALUE=8000000 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PB2.Signal=QUADSPI_CLK +RCC.DIVM3=25 +RCC.DIVM2=25 +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +RCC.DIVM1=2 +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0 +MxDb.Version=DB.6.0.10 +RCC.DIVP1Freq_Value=80000000 ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false +RCC.FMCFreq_Value=40000000 +RCC.USART16Freq_Value=20000000 +File.Version=6 +PE3.GPIOParameters=GPIO_PuPd +PE3.Locked=true +PE2.Signal=QUADSPI_BK1_IO2 +PA14\ (JTCK/SWCLK).Mode=Serial_Wire +PB6.Locked=true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +RCC.DIVR2Freq_Value=16000000 +CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE +ProjectManager.HalAssertFull=false +RCC.DIVP2Freq_Value=16000000 +ProjectManager.ProjectName=STM32H750VB_Bootloader +RCC.APB3Freq_Value=20000000 +RCC.MCO2PinFreq_Value=80000000 +Mcu.Package=LQFP100 +RCC.PLL3FRACN=0 +PD11.Locked=true +RCC.D1PPRE=RCC_APB3_DIV2 +USB_DEVICE.USBD_DEBUG_LEVEL-DFU_FS=0 +CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x90000000 +PD12.Signal=QUADSPI_BK1_IO1 +NVIC.OTG_FS_IRQn=true\:2\:0\:true\:false\:true\:false\:true +ProjectManager.ToolChainLocation= +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +PA10.Signal=USART1_RX +USB_OTG_FS.VirtualMode=Device_Only +RCC.DFSDMFreq_Value=20000000 +RCC.DIVR1Freq_Value=160000000 +USB_DEVICE.USBD_DFU_MEDIA-DFU_FS=@QSPI Flash/0x90000000/2048*4Kg +CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_8MB +PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator +RCC.TraceFreq_Value=160000000 +RCC.APB4Freq_Value=20000000 +RCC.CECFreq_Value=32000 +RCC.SAI23Freq_Value=160000000 +CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_ENABLE +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +RCC.LPUART1Freq_Value=20000000 +USB_OTG_FS.IPParameters=VirtualMode +NVIC.USART1_IRQn=true\:1\:0\:true\:false\:true\:true\:true +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator ProjectManager.CustomerFirmwarePackage= +RCC.Tim2OutputFreq_Value=40000000 +CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_BUFFERABLE +NVIC.RCC_IRQn=true\:0\:0\:false\:false\:true\:true\:false +RCC.DFSDMACLkFreq_Value=160000000 +RCC.VCO3OutputFreq_Value=76800000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_3_CYCLE +NVIC.QUADSPI_IRQn=true\:1\:0\:true\:false\:true\:true\:true +ProjectManager.ProjectFileName=STM32H750VB_Bootloader.ioc +RCC.DIVQ3=5 +CORTEX_M7.CPU_ICache=Disabled +RCC.DIVQ1=1 +PA13\ (JTMS/SWDIO).Mode=Serial_Wire +Mcu.PinsNb=20 +PA10.Mode=Asynchronous +ProjectManager.NoMain=false +USB_DEVICE.VirtualModeFS=Dfu_FS +RCC.SWPMI1Freq_Value=20000000 +CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE +RCC.SAI4BFreq_Value=160000000 +VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Signal=USB_DEVICE_VS_USB_DEVICE_DFU_FS +RCC.D2PPRE2=RCC_APB2_DIV2 +RCC.D2PPRE1=RCC_APB1_DIV2 ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32H750VBTx -ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.5.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x1000 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Core/Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain=SW4STM32 -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=STM32H750VB_Bootloader.ioc -ProjectManager.ProjectName=STM32H750VB_Bootloader -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=SW4STM32 -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_QUADSPI_Init-QUADSPI-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false -QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_5_CYCLE -QUADSPI.ClockPrescaler=16 -QUADSPI.FifoThreshold=4 -QUADSPI.FlashSize=23 -QUADSPI.IPParameters=FlashSize,ChipSelectHighTime,ClockPrescaler,FifoThreshold -RCC.ADCFreq_Value=50390625 -RCC.AHB12Freq_Value=60000000 -RCC.AHB4Freq_Value=60000000 -RCC.APB1Freq_Value=60000000 -RCC.APB2Freq_Value=60000000 -RCC.APB3Freq_Value=60000000 -RCC.APB4Freq_Value=60000000 -RCC.AXIClockFreq_Value=60000000 -RCC.CECFreq_Value=32000 -RCC.CKPERFreq_Value=64000000 -RCC.CortexFreq_Value=120000000 -RCC.CpuClockFreq_Value=120000000 -RCC.D1CPREFreq_Value=120000000 -RCC.DFSDMACLkFreq_Value=48000000 -RCC.DFSDMFreq_Value=60000000 -RCC.DIVM1=25 -RCC.DIVM3=25 -RCC.DIVN1=240 -RCC.DIVN3=192 -RCC.DIVP1Freq_Value=120000000 -RCC.DIVP2Freq_Value=50390625 -RCC.DIVP3Freq_Value=96000000 -RCC.DIVQ1=5 -RCC.DIVQ1Freq_Value=48000000 -RCC.DIVQ2Freq_Value=50390625 -RCC.DIVQ3=4 -RCC.DIVQ3Freq_Value=48000000 -RCC.DIVR1Freq_Value=120000000 -RCC.DIVR2Freq_Value=50390625 -RCC.DIVR3Freq_Value=96000000 -RCC.EnbaleCSS=true -RCC.FDCANFreq_Value=48000000 -RCC.FMCFreq_Value=60000000 -RCC.FamilyName=M -RCC.HCLK3ClockFreq_Value=60000000 -RCC.HCLKFreq_Value=60000000 -RCC.HPRE=RCC_HCLK_DIV2 -RCC.HRTIMFreq_Value=60000000 -RCC.I2C123Freq_Value=60000000 -RCC.I2C4Freq_Value=60000000 -RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value -RCC.LPTIM1Freq_Value=60000000 -RCC.LPTIM2Freq_Value=60000000 -RCC.LPTIM345Freq_Value=60000000 -RCC.LPUART1Freq_Value=60000000 -RCC.LTDCFreq_Value=96000000 -RCC.MCO1PinFreq_Value=64000000 -RCC.MCO2PinFreq_Value=120000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.QSPIFreq_Value=60000000 -RCC.RNGFreq_Value=48000000 -RCC.RTCFreq_Value=32000 -RCC.SAI1Freq_Value=48000000 -RCC.SAI23Freq_Value=48000000 -RCC.SAI4AFreq_Value=48000000 -RCC.SAI4BFreq_Value=48000000 -RCC.SDMMCFreq_Value=48000000 -RCC.SPDIFRXFreq_Value=48000000 -RCC.SPI123Freq_Value=48000000 -RCC.SPI45Freq_Value=60000000 -RCC.SPI6Freq_Value=60000000 -RCC.SWPMI1Freq_Value=60000000 -RCC.SYSCLKFreq_VALUE=120000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.Tim1OutputFreq_Value=60000000 -RCC.Tim2OutputFreq_Value=60000000 -RCC.TraceFreq_Value=120000000 -RCC.USART16Freq_Value=60000000 -RCC.USART234578Freq_Value=60000000 -RCC.USBFreq_Value=48000000 -RCC.VCO1OutputFreq_Value=240000000 -RCC.VCO2OutputFreq_Value=100781250 -RCC.VCO3OutputFreq_Value=192000000 -RCC.VCOInput1Freq_Value=1000000 -RCC.VCOInput2Freq_Value=781250 -RCC.VCOInput3Freq_Value=1000000 -USART1.BaudRate=921600 -USART1.IPParameters=VirtualMode-Asynchronous,BaudRate -USART1.VirtualMode-Asynchronous=VM_ASYNC -USB_DEVICE.CLASS_NAME_FS=DFU +RCC.QSPIFreq_Value=64000000 USB_DEVICE.IPParameters=VirtualMode-DFU_FS,VirtualModeFS,CLASS_NAME_FS,USBD_DFU_XFER_SIZE-DFU_FS,USBD_DFU_APP_DEFAULT_ADD-DFU_FS,USBD_DFU_MEDIA-DFU_FS,USBD_DEBUG_LEVEL-DFU_FS -USB_DEVICE.USBD_DEBUG_LEVEL-DFU_FS=0 +QUADSPI.IPParameters=FlashSize,ChipSelectHighTime,ClockPrescaler,FifoThreshold,ClockMode +RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1 +RCC.FamilyName=M +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PD12.Locked=true +RCC.SPI6Freq_Value=20000000 +RCC.D1CPREFreq_Value=80000000 +USART1.VirtualMode-Asynchronous=VM_ASYNC +CORTEX_M7.MPU_Control=__NULL +RCC.USART234578Freq_Value=20000000 +PA9.Mode=Asynchronous +RCC.SPI45Freq_Value=20000000 +RCC.Tim1OutputFreq_Value=40000000 +RCC.SPI123Freq_Value=160000000 +ProjectManager.TargetToolchain=Makefile +PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT +RCC.VCO1OutputFreq_Value=160000000 +PA9.Signal=USART1_TX +RCC.DIVN3=240 +RCC.HSE_Timout=1000 +RCC.DIVN2=100 +RCC.AXIClockFreq_Value=40000000 +PD13.Mode=Single Bank 1 +RCC.DIVN1=40 +CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0x0 +ProjectManager.RegisterCallBack= +RCC.USBFreq_Value=48000000 +PA1.Signal=GPIO_Output +RCC.CKPERFreq_Value=64000000 +NVIC.PVD_AVD_IRQn=true\:0\:0\:false\:false\:true\:true\:true +RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48 USB_DEVICE.USBD_DFU_APP_DEFAULT_ADD-DFU_FS=0x90000000 -USB_DEVICE.USBD_DFU_MEDIA-DFU_FS=@QSPI Flash/0x90000000/2048*4Kg -USB_DEVICE.USBD_DFU_XFER_SIZE-DFU_FS=4096 -USB_DEVICE.VirtualMode-DFU_FS=Dfu -USB_DEVICE.VirtualModeFS=Dfu_FS -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Mode=DFU_FS -VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS.Signal=USB_DEVICE_VS_USB_DEVICE_DFU_FS board=custom +ProjectManager.LastFirmware=true +RCC.VCOInput1Freq_Value=4000000 +RCC.AHB12Freq_Value=40000000 +RCC.APB2Freq_Value=20000000 +MxCube.Version=6.1.1 +USB_DEVICE.VirtualMode-DFU_FS=Dfu +RCC.FDCANFreq_Value=160000000 +RCC.RNGFreq_Value=48000000 +RCC.ADCFreq_Value=16000000 +VP_SYS_VS_Systick.Mode=SysTick +CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS +PE3.GPIO_PuPd=GPIO_PULLUP +PA9.Locked=true +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.HSEM1_IRQn=true\:0\:0\:false\:false\:true\:true\:true +QUADSPI.FifoThreshold=4 +ProjectManager.FreePins=false +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_Timout,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL3FRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +ProjectManager.AskForMigrate=true +Mcu.Name=STM32H750VBTx +RCC.LPTIM2Freq_Value=20000000 +CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB +NVIC.OTG_FS_EP1_OUT_IRQn=true\:1\:0\:true\:false\:true\:true\:true +CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS +ProjectManager.UnderRoot=false +CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE +CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings +Mcu.IP8=USB_OTG_FS +Mcu.IP6=USART1 +Mcu.IP7=USB_DEVICE +ProjectManager.CoupleFile=false +RCC.SYSCLKFreq_VALUE=80000000 +RCC.I2C123Freq_Value=20000000 +PA1.Locked=true +PD12.Mode=Single Bank 1 +PA12.Mode=Device_Only +PA10.Locked=true +NVIC.ForceEnableDMAVector=true +KeepUserPlacement=false +PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN +PD11.Signal=QUADSPI_BK1_IO0 +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PB2.Mode=Single Bank 1 +ProjectManager.CompilerOptimize=6 +RCC.QSPICLockSelection=RCC_QSPICLKSOURCE_CLKP +PA11.Signal=USB_OTG_FS_DM +ProjectManager.HeapSize=0x200 +Mcu.Pin15=PA13 (JTMS/SWDIO) +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Mcu.Pin16=PA14 (JTCK/SWCLK) +Mcu.Pin13=PA11 +PD11.Mode=Single Bank 1 +Mcu.Pin14=PA12 +Mcu.Pin19=VP_USB_DEVICE_VS_USB_DEVICE_DFU_FS +RCC.LPTIM345Freq_Value=20000000 +ProjectManager.ComputerToolchain=false +Mcu.Pin17=PB6 +Mcu.Pin18=VP_SYS_VS_Systick +RCC.LTDCFreq_Value=38400000 +RCC.SAI4AFreq_Value=160000000 +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +Mcu.Pin11=PA9 +Mcu.Pin12=PA10 +Mcu.Pin10=PD13 +RCC.DIVQ1Freq_Value=160000000 +PE3.Signal=GPIO_Input +USB_DEVICE.USBD_DFU_XFER_SIZE-DFU_FS=4096 +RCC.D3PPRE=RCC_APB4_DIV2 +NVIC.FPU_IRQn=true\:0\:0\:false\:false\:true\:true\:false +CORTEX_M7.CPU_DCache=Disabled +RCC.HCLK3ClockFreq_Value=40000000 +RCC.VCOInput2Freq_Value=320000 +RCC.APB1Freq_Value=20000000 +RCC.DIVR1=1 +ProjectManager.DeviceId=STM32H750VBTx +ProjectManager.LibraryCopy=1 +PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO diff --git a/STM32H750VB_Bootloader.xml b/STM32H750VB_Bootloader.xml deleted file mode 100644 index e406c1e..0000000 --- a/STM32H750VB_Bootloader.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - STM32H750VB_Bootloader - STM32H750VBTx - SWD - ST-LinkV2-1 - - diff --git a/USB_DEVICE/App/usb_device.c b/USB_DEVICE/App/usb_device.c index 5ecd1e1..31ca9c0 100644 --- a/USB_DEVICE/App/usb_device.c +++ b/USB_DEVICE/App/usb_device.c @@ -30,6 +30,7 @@ /* USER CODE BEGIN Includes */ #include "stm32h7xx_hal.h" +#include "pin_config.h" /* USER CODE END Includes */ @@ -70,11 +71,11 @@ void MX_USB_DEVICE_Init(void) { /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ - if(HAL_GPIO_ReadPin(GPIOE, GPIO_PIN_3) == GPIO_PIN_SET && g_DFU == 0) return; + if(HAL_GPIO_ReadPin(BTN_PORT, BTN_PIN) == BTN_INACTIVE_STATE && g_DFU == 0) return; g_DFU = 1; /* USER CODE END USB_DEVICE_Init_PreTreatment */ - + /* Init Device Library, add supported class and start the library. */ if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) { diff --git a/USB_DEVICE/App/usbd_desc.c b/USB_DEVICE/App/usbd_desc.c index 53dac0a..1db8ebd 100644 --- a/USB_DEVICE/App/usbd_desc.c +++ b/USB_DEVICE/App/usbd_desc.c @@ -95,19 +95,18 @@ /** * @} */ - + /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes * @brief Private functions declaration. * @{ */ - + static void Get_SerialNum(void); static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); - + /** * @} - */ - + */ /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes * @brief Private functions declaration for FS. @@ -199,7 +198,7 @@ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 + #pragma data_alignment=4 #endif __ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { USB_SIZ_STRING_SERIAL, @@ -332,8 +331,8 @@ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng } /** - * @brief Create the serial number string descriptor - * @param None + * @brief Create the serial number string descriptor + * @param None * @retval None */ static void Get_SerialNum(void) @@ -354,9 +353,9 @@ static void Get_SerialNum(void) } /** - * @brief Convert Hex 32Bits value into char + * @brief Convert Hex 32Bits value into char * @param value: value to convert - * @param pbuf: pointer to the buffer + * @param pbuf: pointer to the buffer * @param len: buffer length * @retval None */ diff --git a/USB_DEVICE/App/usbd_desc.h b/USB_DEVICE/App/usbd_desc.h index 122f582..2348ea1 100644 --- a/USB_DEVICE/App/usbd_desc.h +++ b/USB_DEVICE/App/usbd_desc.h @@ -17,7 +17,7 @@ * ****************************************************************************** */ -/* USER CODE END Header */ +/* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__C__ #define __USBD_DESC__C__ @@ -41,7 +41,7 @@ * @brief Usb device descriptors module. * @{ */ - + /** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants * @brief Constants. * @{ diff --git a/USB_DEVICE/App/usbd_dfu_if.c b/USB_DEVICE/App/usbd_dfu_if.c index 1f95732..f2d875a 100644 --- a/USB_DEVICE/App/usbd_dfu_if.c +++ b/USB_DEVICE/App/usbd_dfu_if.c @@ -25,6 +25,8 @@ #include "w25_qspi.h" #include "printf.h" +#include "pin_config.h" + /* USER CODE END INCLUDE */ /* Private typedef -----------------------------------------------------------*/ @@ -64,7 +66,7 @@ * @{ */ -#define FLASH_DESC_STR "@QSPI Flash/0x90000000/2048*4Kg" +#define FLASH_DESC_STR "@QSPI Flash/0x90000000/4096*4Kg" /* USER CODE BEGIN PRIVATE_DEFINES */ @@ -164,6 +166,10 @@ uint16_t MEM_If_Init_FS(void) w25_flash.mode = W25_MODE_QUAD; w25_flash.address_size = W25_ADDRESS_24BITS; +#if(USE_QPI_MODE == 1) + W25_QPI_Mode(&w25_flash, 0); +#endif // USE_QPI_MODE + W25_QSPI_Init(&w25_flash); printf("MEM_If_Init_FS: Mfg: 0x%x\r\n", w25_flash.manufacturer); return (USBD_OK); @@ -206,6 +212,7 @@ uint16_t MEM_If_Erase_FS(uint32_t Add) uint16_t MEM_If_Write_FS(uint8_t *src, uint8_t *dest, uint32_t Len) { /* USER CODE BEGIN 3 */ + HAL_GPIO_TogglePin(LED_PORT, LED_PIN); printf("Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08x 1St: 0x%02x\r\n", (uint32_t)dest, (uint32_t)src, Len, src[0]); uint8_t page_count = Len / 256; if(Len & 0xFFU) page_count++; @@ -230,6 +237,7 @@ uint8_t *MEM_If_Read_FS(uint8_t *src, uint8_t *dest, uint32_t Len) { /* Return a valid address to avoid HardFault */ /* USER CODE BEGIN 4 */ + HAL_GPIO_TogglePin(LED_PORT, LED_PIN); printf("Mem_If_Read_FS: Add: 0x%08x\r\n", (uint32_t)src); W25_QSPI_Read(&w25_flash, (uint32_t)src - 0x90000000, dest, Len); //HAL_Delay(100); diff --git a/USB_DEVICE/Target/usbd_conf.c b/USB_DEVICE/Target/usbd_conf.c index f69d0d7..6146349 100644 --- a/USB_DEVICE/Target/usbd_conf.c +++ b/USB_DEVICE/Target/usbd_conf.c @@ -71,11 +71,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ /* USER CODE END USB_OTG_FS_MspInit 0 */ - + __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -109,10 +109,10 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) /* USER CODE END USB_OTG_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration + + /**USB_OTG_FS GPIO Configuration PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP + PA12 ------> USB_OTG_FS_DP */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); @@ -197,7 +197,7 @@ static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #else void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ +{ USBD_SpeedTypeDef speed = USBD_SPEED_FULL; if ( hpcd->Init.speed == PCD_SPEED_HIGH) @@ -336,7 +336,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; pdev->pData = &hpcd_USB_OTG_FS; - + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; hpcd_USB_OTG_FS.Init.dev_endpoints = 9; hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; @@ -388,8 +388,8 @@ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) hal_status = HAL_PCD_DeInit(pdev->pData); usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + return usb_status; } /** @@ -401,11 +401,11 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_Start(pdev->pData); - - usb_status = USBD_Get_USB_Status(hal_status); - + + usb_status = USBD_Get_USB_Status(hal_status); + return usb_status; } @@ -420,9 +420,9 @@ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_Stop(pdev->pData); - + usb_status = USBD_Get_USB_Status(hal_status); - + return usb_status; } @@ -442,7 +442,7 @@ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uin hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); usb_status = USBD_Get_USB_Status(hal_status); - + return usb_status; } @@ -456,12 +456,12 @@ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -474,12 +474,12 @@ USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -492,12 +492,12 @@ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + return usb_status; } /** @@ -510,12 +510,12 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -527,14 +527,14 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; - + if((ep_addr & 0x80) == 0x80) { - return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + return hpcd->IN_ep[ep_addr & 0x7F].is_stall; } else { - return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; } } @@ -548,12 +548,12 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); - + usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + return usb_status; } /** @@ -561,19 +561,19 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a * @param pdev: Device handle * @param ep_addr: Endpoint number * @param pbuf: Pointer to data to be sent - * @param size: Data size + * @param size: Data size * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** @@ -584,16 +584,16 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, u * @param size: Data size * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); - - usb_status = USBD_Get_USB_Status(hal_status); - - return usb_status; + + usb_status = USBD_Get_USB_Status(hal_status); + + return usb_status; } /** diff --git a/USB_DEVICE/Target/usbd_conf.h b/USB_DEVICE/Target/usbd_conf.h index 98b0b98..26386b9 100644 --- a/USB_DEVICE/Target/usbd_conf.h +++ b/USB_DEVICE/Target/usbd_conf.h @@ -42,6 +42,7 @@ /* USER CODE END INCLUDE */ /** @addtogroup USBD_OTG_DRIVER + * @brief Driver for Usb device. * @{ */ diff --git a/build/STM32H750VB_Bootloader.bin b/build/STM32H750VB_Bootloader.bin new file mode 100755 index 0000000..d36ceff Binary files /dev/null and b/build/STM32H750VB_Bootloader.bin differ diff --git a/build/STM32H750VB_Bootloader.elf b/build/STM32H750VB_Bootloader.elf new file mode 100755 index 0000000..f2da942 Binary files /dev/null and b/build/STM32H750VB_Bootloader.elf differ diff --git a/build/STM32H750VB_Bootloader.hex b/build/STM32H750VB_Bootloader.hex new file mode 100644 index 0000000..f4309fd --- /dev/null +++ b/build/STM32H750VB_Bootloader.hex @@ -0,0 +1,2230 @@ +:020000040800F2 +:1000000000000220258200085F0600086106000843 +:100010006306000865060008670600080000000087 +:100020000000000000000000000000006906000859 +:100030006B060008000000006D0600086F0600084F +:10004000758200087706000875820008758200082E +:100050007F06000887060008758200087582000880 +:100060007582000875820008758200087582000894 +:100070007582000875820008758200087582000884 +:100080007582000875820008758200087582000874 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+LOAD build/stm32h7xx_hal_rcc.o +LOAD build/stm32h7xx_hal_rcc_ex.o +LOAD build/stm32h7xx_hal_flash.o +LOAD build/stm32h7xx_hal_flash_ex.o +LOAD build/stm32h7xx_hal_gpio.o +LOAD build/stm32h7xx_hal_hsem.o +LOAD build/stm32h7xx_hal_dma.o +LOAD build/stm32h7xx_hal_dma_ex.o +LOAD build/stm32h7xx_hal_mdma.o +LOAD build/stm32h7xx_hal_pwr.o +LOAD build/stm32h7xx_hal_pwr_ex.o +LOAD build/stm32h7xx_hal_cortex.o +LOAD build/stm32h7xx_hal.o +LOAD build/stm32h7xx_hal_i2c.o +LOAD build/stm32h7xx_hal_i2c_ex.o +LOAD build/stm32h7xx_hal_exti.o +LOAD build/stm32h7xx_hal_qspi.o +LOAD build/stm32h7xx_hal_tim.o +LOAD build/stm32h7xx_hal_tim_ex.o +LOAD build/stm32h7xx_hal_uart.o +LOAD build/stm32h7xx_hal_uart_ex.o +LOAD build/system_stm32h7xx.o +LOAD build/usbd_core.o +LOAD build/usbd_ctlreq.o +LOAD build/usbd_ioreq.o +LOAD build/usbd_dfu.o +LOAD build/startup_stm32h750xx.o +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtn.o + 0x0000000020020000 _estack = 0x20020000 + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0x298 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0x298 build/startup_stm32h750xx.o + 0x0000000008000000 g_pfnVectors + 0x0000000008000298 . = ALIGN (0x4) + +.text 0x0000000008000298 0x84c8 + 0x0000000008000298 . = ALIGN (0x4) + *(.text) + .text 0x0000000008000298 0x30 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x0000000008000298 __aeabi_uldivmod + .text 0x00000000080002c8 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + 0x00000000080002c8 __aeabi_ldiv0 + 0x00000000080002c8 __aeabi_idiv0 + *(.text*) + .text.__do_global_dtors_aux + 0x00000000080002cc 0x24 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + .text.frame_dummy + 0x00000000080002f0 0x1c /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + .text.MX_GPIO_Init + 0x000000000800030c 0xe4 build/main.o + .text.MX_QUADSPI_Init + 0x00000000080003f0 0x34 build/main.o + .text.MX_USART1_UART_Init + 0x0000000008000424 0x4c build/main.o + .text.SystemClock_Config + 0x0000000008000470 0xe0 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0x0000000008007c7e 0x2 + .text.USBD_DFU_GetUsrStringDesc + 0x0000000008007c80 0x20 build/usbd_dfu.o + .text.DFU_Leave + 0x0000000008007ca0 0x68 build/usbd_dfu.o + .text.USBD_DFU_EP0_TxReady + 0x0000000008007d08 0xe4 build/usbd_dfu.o + .text.DFU_Upload + 0x0000000008007dec 0xd6 build/usbd_dfu.o + *fill* 0x0000000008007ec2 0x2 + .text.DFU_GetStatus + 0x0000000008007ec4 0xd0 build/usbd_dfu.o + .text.DFU_GetState + 0x0000000008007f94 0x14 build/usbd_dfu.o + .text.DFU_Download + 0x0000000008007fa8 0x6c build/usbd_dfu.o + .text.DFU_Detach + 0x0000000008008014 0x60 build/usbd_dfu.o + .text.USBD_DFU_Setup + 0x0000000008008074 0x118 build/usbd_dfu.o + .text.USBD_DFU_DeInit + 0x000000000800818c 0x38 build/usbd_dfu.o + .text.USBD_DFU_Init + 0x00000000080081c4 0x50 build/usbd_dfu.o + .text.USBD_DFU_RegisterMedia + 0x0000000008008214 0xe build/usbd_dfu.o + 0x0000000008008214 USBD_DFU_RegisterMedia + *fill* 0x0000000008008222 0x2 + .text.Reset_Handler + 0x0000000008008224 0x50 build/startup_stm32h750xx.o + 0x0000000008008224 Reset_Handler + .text.Default_Handler + 0x0000000008008274 0x2 build/startup_stm32h750xx.o + 0x0000000008008274 RTC_Alarm_IRQHandler + 0x0000000008008274 HASH_RNG_IRQHandler + 0x0000000008008274 EXTI2_IRQHandler + 0x0000000008008274 TIM8_CC_IRQHandler + 0x0000000008008274 HRTIM1_Master_IRQHandler + 0x0000000008008274 UART8_IRQHandler + 0x0000000008008274 SPI4_IRQHandler + 0x0000000008008274 TIM1_CC_IRQHandler + 0x0000000008008274 BDMA_Channel6_IRQHandler + 0x0000000008008274 DMA2_Stream5_IRQHandler + 0x0000000008008274 HRTIM1_FLT_IRQHandler + 0x0000000008008274 JPEG_IRQHandler + 0x0000000008008274 DMA1_Stream5_IRQHandler + 0x0000000008008274 BDMA_Channel1_IRQHandler + 0x0000000008008274 HRTIM1_TIMD_IRQHandler + 0x0000000008008274 TAMP_STAMP_IRQHandler + 0x0000000008008274 EXTI3_IRQHandler + 0x0000000008008274 LPTIM4_IRQHandler + 0x0000000008008274 TIM8_TRG_COM_TIM14_IRQHandler + 0x0000000008008274 LPTIM2_IRQHandler + 0x0000000008008274 DFSDM1_FLT1_IRQHandler + 0x0000000008008274 DMAMUX2_OVR_IRQHandler + 0x0000000008008274 TIM8_UP_TIM13_IRQHandler + 0x0000000008008274 I2C3_ER_IRQHandler + 0x0000000008008274 DFSDM1_FLT2_IRQHandler + 0x0000000008008274 MDMA_IRQHandler + 0x0000000008008274 LPTIM3_IRQHandler + 0x0000000008008274 EXTI0_IRQHandler + 0x0000000008008274 I2C2_EV_IRQHandler + 0x0000000008008274 DMA1_Stream2_IRQHandler + 0x0000000008008274 OTG_HS_WKUP_IRQHandler + 0x0000000008008274 FDCAN1_IT1_IRQHandler + 0x0000000008008274 LTDC_ER_IRQHandler + 0x0000000008008274 DMA2_Stream2_IRQHandler + 0x0000000008008274 HRTIM1_TIME_IRQHandler + 0x0000000008008274 SPI1_IRQHandler + 0x0000000008008274 TIM6_DAC_IRQHandler + 0x0000000008008274 DCMI_IRQHandler + 0x0000000008008274 HRTIM1_TIMC_IRQHandler + 0x0000000008008274 DMA2_Stream3_IRQHandler + 0x0000000008008274 SAI2_IRQHandler + 0x0000000008008274 DFSDM1_FLT3_IRQHandler + 0x0000000008008274 USART6_IRQHandler + 0x0000000008008274 TIM17_IRQHandler + 0x0000000008008274 USART3_IRQHandler + 0x0000000008008274 BDMA_Channel7_IRQHandler + 0x0000000008008274 CRYP_IRQHandler + 0x0000000008008274 LPTIM5_IRQHandler + 0x0000000008008274 UART5_IRQHandler + 0x0000000008008274 ADC3_IRQHandler + 0x0000000008008274 DMA2_Stream0_IRQHandler + 0x0000000008008274 TIM4_IRQHandler + 0x0000000008008274 BDMA_Channel2_IRQHandler + 0x0000000008008274 I2C1_EV_IRQHandler + 0x0000000008008274 DMA1_Stream6_IRQHandler + 0x0000000008008274 DMAMUX1_OVR_IRQHandler + 0x0000000008008274 DMA1_Stream1_IRQHandler + 0x0000000008008274 TIM16_IRQHandler + 0x0000000008008274 UART4_IRQHandler + 0x0000000008008274 BDMA_Channel5_IRQHandler + 0x0000000008008274 TIM3_IRQHandler + 0x0000000008008274 TIM8_BRK_TIM12_IRQHandler + 0x0000000008008274 TIM1_TRG_COM_IRQHandler + 0x0000000008008274 Default_Handler + 0x0000000008008274 ECC_IRQHandler + 0x0000000008008274 CEC_IRQHandler + 0x0000000008008274 EXTI15_10_IRQHandler + 0x0000000008008274 BDMA_Channel0_IRQHandler + 0x0000000008008274 ADC_IRQHandler + 0x0000000008008274 DMA1_Stream7_IRQHandler + 0x0000000008008274 HRTIM1_TIMA_IRQHandler + 0x0000000008008274 SPI5_IRQHandler + 0x0000000008008274 TIM7_IRQHandler + 0x0000000008008274 SDMMC1_IRQHandler + 0x0000000008008274 TIM5_IRQHandler + 0x0000000008008274 DMA2_Stream7_IRQHandler + 0x0000000008008274 TIM15_IRQHandler + 0x0000000008008274 I2C3_EV_IRQHandler + 0x0000000008008274 EXTI9_5_IRQHandler + 0x0000000008008274 RTC_WKUP_IRQHandler + 0x0000000008008274 LTDC_IRQHandler + 0x0000000008008274 SAI3_IRQHandler + 0x0000000008008274 ETH_WKUP_IRQHandler + 0x0000000008008274 SPDIF_RX_IRQHandler + 0x0000000008008274 SPI2_IRQHandler + 0x0000000008008274 OTG_HS_EP1_IN_IRQHandler + 0x0000000008008274 DMA1_Stream0_IRQHandler + 0x0000000008008274 CRS_IRQHandler + 0x0000000008008274 EXTI4_IRQHandler + 0x0000000008008274 HRTIM1_TIMB_IRQHandler + 0x0000000008008274 FDCAN2_IT1_IRQHandler + 0x0000000008008274 ETH_IRQHandler + 0x0000000008008274 TIM1_UP_IRQHandler + 0x0000000008008274 BDMA_Channel4_IRQHandler + 0x0000000008008274 OTG_HS_EP1_OUT_IRQHandler + 0x0000000008008274 WWDG_IRQHandler + 0x0000000008008274 SPI6_IRQHandler + 0x0000000008008274 MDIOS_IRQHandler + 0x0000000008008274 I2C4_EV_IRQHandler + 0x0000000008008274 FDCAN2_IT0_IRQHandler + 0x0000000008008274 LPUART1_IRQHandler + 0x0000000008008274 FDCAN1_IT0_IRQHandler + 0x0000000008008274 TIM2_IRQHandler + 0x0000000008008274 OTG_FS_WKUP_IRQHandler + 0x0000000008008274 OTG_HS_IRQHandler + 0x0000000008008274 DMA2D_IRQHandler + 0x0000000008008274 TIM1_BRK_IRQHandler + 0x0000000008008274 EXTI1_IRQHandler + 0x0000000008008274 SDMMC2_IRQHandler + 0x0000000008008274 BDMA_Channel3_IRQHandler + 0x0000000008008274 UART7_IRQHandler + 0x0000000008008274 MDIOS_WKUP_IRQHandler + 0x0000000008008274 USART2_IRQHandler + 0x0000000008008274 DFSDM1_FLT0_IRQHandler + 0x0000000008008274 SAI4_IRQHandler + 0x0000000008008274 I2C2_ER_IRQHandler + 0x0000000008008274 DMA2_Stream1_IRQHandler + 0x0000000008008274 DMA2_Stream4_IRQHandler + 0x0000000008008274 SPI3_IRQHandler + 0x0000000008008274 WAKEUP_PIN_IRQHandler + 0x0000000008008274 DMA1_Stream4_IRQHandler + 0x0000000008008274 I2C1_ER_IRQHandler + 0x0000000008008274 FMC_IRQHandler + 0x0000000008008274 FDCAN_CAL_IRQHandler + 0x0000000008008274 SWPMI1_IRQHandler + 0x0000000008008274 COMP1_IRQHandler + 0x0000000008008274 LPTIM1_IRQHandler + 0x0000000008008274 I2C4_ER_IRQHandler + 0x0000000008008274 DMA2_Stream6_IRQHandler + 0x0000000008008274 SAI1_IRQHandler + 0x0000000008008274 DMA1_Stream3_IRQHandler + *fill* 0x0000000008008276 0x2 + .text.__libc_init_array + 0x0000000008008278 0x48 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) + 0x0000000008008278 __libc_init_array + .text.malloc 0x00000000080082c0 0x10 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) + 0x00000000080082c0 malloc + .text.free 0x00000000080082d0 0x10 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) + 0x00000000080082d0 free + .text.memset 0x00000000080082e0 0x10 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-memset.o) + 0x00000000080082e0 memset + .text._free_r 0x00000000080082f0 0xa0 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-freer.o) + 0x00000000080082f0 _free_r + .text._malloc_r + 0x0000000008008390 0xb4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x0000000008008390 _malloc_r + .text._sbrk_r 0x0000000008008444 0x20 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-sbrkr.o) + 0x0000000008008444 _sbrk_r + .text.__retarget_lock_acquire_recursive + 0x0000000008008464 0x2 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + 0x0000000008008464 __retarget_lock_acquire_recursive + .text.__retarget_lock_release_recursive + 0x0000000008008466 0x2 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + 0x0000000008008466 __retarget_lock_release_recursive + .text.__malloc_lock + 0x0000000008008468 0xc /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + 0x0000000008008468 __malloc_lock + .text.__malloc_unlock + 0x0000000008008474 0xc /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + 0x0000000008008474 __malloc_unlock + .text._sbrk 0x0000000008008480 0x1c /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a(sbrk.o) + 0x0000000008008480 _sbrk + .text.__udivmoddi4 + 0x000000000800849c 0x2aa /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x000000000800849c __udivmoddi4 + *(.glue_7) + .glue_7 0x0000000008008746 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x0000000008008746 0x0 linker stubs + *(.eh_frame) + *fill* 0x0000000008008746 0x2 + .eh_frame 0x0000000008008748 0x0 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + *(.init) + .init 0x0000000008008748 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crti.o + 0x0000000008008748 _init + .init 0x000000000800874c 0x8 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtn.o + *(.fini) + .fini 0x0000000008008754 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crti.o + 0x0000000008008754 _fini + .fini 0x0000000008008758 0x8 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtn.o + 0x0000000008008760 . = ALIGN (0x4) + 0x0000000008008760 _etext = . + +.vfp11_veneer 0x0000000008008760 0x0 + .vfp11_veneer 0x0000000008008760 0x0 linker stubs + +.v4_bx 0x0000000008008760 0x0 + .v4_bx 0x0000000008008760 0x0 linker stubs + +.iplt 0x0000000008008760 0x0 + .iplt 0x0000000008008760 0x0 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + +.rodata 0x0000000008008760 0x23c + 0x0000000008008760 . = ALIGN (0x4) + *(.rodata) + .rodata 0x0000000008008760 0x8 build/stm32h7xx_hal_uart_ex.o + *(.rodata*) + .rodata.main.str1.4 + 0x0000000008008768 0x68 build/main.o + .rodata._ftoa.str1.4 + 0x00000000080087d0 0x15 build/printf.o + *fill* 0x00000000080087e5 0x3 + .rodata.pow10.0 + 0x00000000080087e8 0x50 build/printf.o + .rodata.USBD_FS_ProductStrDescriptor.str1.4 + 0x0000000008008838 0x1f build/usbd_desc.o + *fill* 0x0000000008008857 0x1 + .rodata.USBD_FS_ManufacturerStrDescriptor.str1.4 + 0x0000000008008858 0x13 build/usbd_desc.o + *fill* 0x000000000800886b 0x1 + .rodata.USBD_FS_ConfigStrDescriptor.str1.4 + 0x000000000800886c 0xb build/usbd_desc.o + *fill* 0x0000000008008877 0x1 + .rodata.USBD_FS_InterfaceStrDescriptor.str1.4 + 0x0000000008008878 0xe build/usbd_desc.o + *fill* 0x0000000008008886 0x2 + .rodata.MEM_If_Read_FS.str1.4 + 0x0000000008008888 0x1e build/usbd_dfu_if.o + *fill* 0x00000000080088a6 0x2 + .rodata.MEM_If_Write_FS.str1.4 + 0x00000000080088a8 0x63 build/usbd_dfu_if.o + *fill* 0x000000000800890b 0x1 + .rodata.MEM_If_Erase_FS.str1.4 + 0x000000000800890c 0x1f build/usbd_dfu_if.o + *fill* 0x000000000800892b 0x1 + .rodata.MEM_If_Init_FS.str1.4 + 0x000000000800892c 0x1c build/usbd_dfu_if.o + .rodata.str1.4 + 0x0000000008008948 0x20 build/usbd_dfu_if.o + .rodata.UARTPrescTable + 0x0000000008008968 0x18 build/stm32h7xx_hal_uart.o + 0x0000000008008968 UARTPrescTable + .rodata.UARTEx_SetNbDataToProcess.str1.4 + 0x0000000008008980 0x9 build/stm32h7xx_hal_uart_ex.o + *fill* 0x0000000008008989 0x3 + .rodata.D1CorePrescTable + 0x000000000800898c 0x10 build/system_stm32h7xx.o + 0x000000000800898c D1CorePrescTable + 0x000000000800899c . = ALIGN (0x4) + +.ARM.extab + *(.ARM.extab* .gnu.linkonce.armextab.*) + +.ARM 0x000000000800899c 0x8 + 0x000000000800899c __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx.text.__udivmoddi4 + 0x000000000800899c 0x8 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x00000000080089a4 __exidx_end = . + +.rel.dyn 0x00000000080089a4 0x0 + .rel.iplt 0x00000000080089a4 0x0 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + +.preinit_array 0x00000000080089a4 0x0 + 0x00000000080089a4 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x00000000080089a4 PROVIDE (__preinit_array_end = .) + +.init_array 0x00000000080089a4 0x4 + 0x00000000080089a4 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x00000000080089a4 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + 0x00000000080089a8 PROVIDE (__init_array_end = .) + +.fini_array 0x00000000080089a8 0x4 + 0x00000000080089a8 PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x00000000080089a8 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + 0x00000000080089ac PROVIDE (__fini_array_end = .) + 0x00000000080089ac _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0x144 load address 0x00000000080089ac + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.FS_Desc 0x0000000020000000 0x1c build/usbd_desc.o + 0x0000000020000000 FS_Desc + .data.USBD_FS_DeviceDesc + 0x000000002000001c 0x12 build/usbd_desc.o + 0x000000002000001c USBD_FS_DeviceDesc + *fill* 0x000000002000002e 0x2 + .data.USBD_LangIDDesc + 0x0000000020000030 0x4 build/usbd_desc.o + 0x0000000020000030 USBD_LangIDDesc + .data.USBD_StringSerial + 0x0000000020000034 0x1a build/usbd_desc.o + 0x0000000020000034 USBD_StringSerial + *fill* 0x000000002000004e 0x2 + .data.USBD_DFU_fops_FS + 0x0000000020000050 0x1c build/usbd_dfu_if.o + 0x0000000020000050 USBD_DFU_fops_FS + .data.uwTickFreq + 0x000000002000006c 0x1 build/stm32h7xx_hal.o + 0x000000002000006c uwTickFreq + *fill* 0x000000002000006d 0x3 + .data.uwTickPrio + 0x0000000020000070 0x4 build/stm32h7xx_hal.o + 0x0000000020000070 uwTickPrio + .data.SystemCoreClock + 0x0000000020000074 0x4 build/system_stm32h7xx.o + 0x0000000020000074 SystemCoreClock + .data.SystemD2Clock + 0x0000000020000078 0x4 build/system_stm32h7xx.o + 0x0000000020000078 SystemD2Clock + .data.USBD_DFU + 0x000000002000007c 0x3c build/usbd_dfu.o + 0x000000002000007c USBD_DFU + .data.USBD_DFU_CfgDesc + 0x00000000200000b8 0x1b build/usbd_dfu.o + *fill* 0x00000000200000d3 0x1 + .data.USBD_DFU_DeviceQualifierDesc + 0x00000000200000d4 0xa build/usbd_dfu.o + *fill* 0x00000000200000de 0x2 + .data._impure_ptr + 0x00000000200000e0 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) + 0x00000000200000e0 _impure_ptr + .data.impure_data + 0x00000000200000e4 0x60 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) + 0x0000000020000144 . = ALIGN (0x4) + 0x0000000020000144 _edata = . + +.igot.plt 0x0000000020000144 0x0 load address 0x0000000008008af0 + .igot.plt 0x0000000020000144 0x0 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + 0x0000000020000144 . = ALIGN (0x4) + +.bss 0x0000000020000144 0xb20 load address 0x0000000008008af0 + 0x0000000020000144 _sbss = . + 0x0000000020000144 __bss_start__ = _sbss + *(.bss) + *(.bss*) + .bss.completed.1 + 0x0000000020000144 0x1 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + *fill* 0x0000000020000145 0x3 + .bss.object.0 0x0000000020000148 0x18 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + .bss.g_DFU 0x0000000020000160 0x1 build/main.o + 0x0000000020000160 g_DFU + *fill* 0x0000000020000161 0x3 + .bss.hqspi 0x0000000020000164 0x4c build/main.o + 0x0000000020000164 hqspi + .bss.huart1 0x00000000200001b0 0x8c build/main.o + 0x00000000200001b0 huart1 + .bss.hUsbDeviceFS + 0x000000002000023c 0x2d0 build/usb_device.o + 0x000000002000023c hUsbDeviceFS + .bss.USBD_StrDesc + 0x000000002000050c 0x200 build/usbd_desc.o + 0x000000002000050c USBD_StrDesc + .bss.w25_flash + 0x000000002000070c 0x10 build/usbd_dfu_if.o + 0x000000002000070c w25_flash + .bss.hpcd_USB_OTG_FS + 0x000000002000071c 0x408 build/usbd_conf.o + 0x000000002000071c hpcd_USB_OTG_FS + .bss.pFlash 0x0000000020000b24 0x1c build/stm32h7xx_hal_flash.o + 0x0000000020000b24 pFlash + .bss.uwTick 0x0000000020000b40 0x4 build/stm32h7xx_hal.o + 0x0000000020000b40 uwTick + .bss.cfgidx.0 0x0000000020000b44 0x1 build/usbd_ctlreq.o + *fill* 0x0000000020000b45 0x3 + .bss.USBD_StrDesc.0 + 0x0000000020000b48 0xff build/usbd_dfu.o + *fill* 0x0000000020000c47 0x1 + .bss.__malloc_free_list + 0x0000000020000c48 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x0000000020000c48 __malloc_free_list + .bss.__malloc_sbrk_start + 0x0000000020000c4c 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x0000000020000c4c __malloc_sbrk_start + .bss.heap_end.5507 + 0x0000000020000c50 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a(sbrk.o) + *(COMMON) + COMMON 0x0000000020000c54 0x9 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + 0x0000000020000c54 __lock___atexit_recursive_mutex + 0x0000000020000c55 __lock___arc4random_mutex + 0x0000000020000c56 __lock___env_recursive_mutex + 0x0000000020000c57 __lock___sinit_recursive_mutex + 0x0000000020000c58 __lock___malloc_recursive_mutex + 0x0000000020000c59 __lock___at_quick_exit_mutex + 0x0000000020000c5a __lock___dd_hash_mutex + 0x0000000020000c5b __lock___tz_mutex + 0x0000000020000c5c __lock___sfp_recursive_mutex + *fill* 0x0000000020000c5d 0x3 + COMMON 0x0000000020000c60 0x4 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) + 0x0000000020000c60 errno + 0x0000000020000c64 . = ALIGN (0x4) + 0x0000000020000c64 _ebss = . + 0x0000000020000c64 __bss_end__ = _ebss + +._user_heap_stack + 0x0000000020000c64 0x604 load address 0x0000000008008af0 + 0x0000000020000c68 . = ALIGN (0x8) + *fill* 0x0000000020000c64 0x4 + 0x0000000020000c68 PROVIDE (end = .) + [!provide] PROVIDE (_end = .) + 0x0000000020000e68 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000c68 0x200 + 0x0000000020001268 . = (. + _Min_Stack_Size) + *fill* 0x0000000020000e68 0x400 + 0x0000000020001268 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x2e + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crti.o + .ARM.attributes + 0x000000000000001e 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o + .ARM.attributes + 0x0000000000000050 0x32 build/main.o + .ARM.attributes + 0x0000000000000082 0x32 build/stm32h7xx_it.o + .ARM.attributes + 0x00000000000000b4 0x32 build/stm32h7xx_hal_msp.o + .ARM.attributes + 0x00000000000000e6 0x32 build/w25_qspi.o + .ARM.attributes + 0x0000000000000118 0x32 build/port_printf.o + .ARM.attributes + 0x000000000000014a 0x32 build/printf.o + .ARM.attributes + 0x000000000000017c 0x32 build/bootloader_control.o + .ARM.attributes + 0x00000000000001ae 0x32 build/usb_device.o + .ARM.attributes + 0x00000000000001e0 0x32 build/usbd_desc.o + .ARM.attributes + 0x0000000000000212 0x32 build/usbd_dfu_if.o + .ARM.attributes + 0x0000000000000244 0x32 build/usbd_conf.o + .ARM.attributes + 0x0000000000000276 0x32 build/stm32h7xx_hal_pcd.o + .ARM.attributes + 0x00000000000002a8 0x32 build/stm32h7xx_hal_pcd_ex.o + .ARM.attributes + 0x00000000000002da 0x32 build/stm32h7xx_ll_usb.o + .ARM.attributes + 0x000000000000030c 0x32 build/stm32h7xx_hal_rcc.o + .ARM.attributes + 0x000000000000033e 0x32 build/stm32h7xx_hal_rcc_ex.o + .ARM.attributes + 0x0000000000000370 0x32 build/stm32h7xx_hal_flash.o + .ARM.attributes + 0x00000000000003a2 0x32 build/stm32h7xx_hal_flash_ex.o + .ARM.attributes + 0x00000000000003d4 0x32 build/stm32h7xx_hal_gpio.o + .ARM.attributes + 0x0000000000000406 0x32 build/stm32h7xx_hal_hsem.o + .ARM.attributes + 0x0000000000000438 0x32 build/stm32h7xx_hal_dma.o + .ARM.attributes + 0x000000000000046a 0x32 build/stm32h7xx_hal_mdma.o + .ARM.attributes + 0x000000000000049c 0x32 build/stm32h7xx_hal_pwr.o + .ARM.attributes + 0x00000000000004ce 0x32 build/stm32h7xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000500 0x32 build/stm32h7xx_hal_cortex.o + .ARM.attributes + 0x0000000000000532 0x32 build/stm32h7xx_hal.o + .ARM.attributes + 0x0000000000000564 0x32 build/stm32h7xx_hal_qspi.o + .ARM.attributes + 0x0000000000000596 0x32 build/stm32h7xx_hal_uart.o + .ARM.attributes + 0x00000000000005c8 0x32 build/stm32h7xx_hal_uart_ex.o + .ARM.attributes + 0x00000000000005fa 0x32 build/system_stm32h7xx.o + .ARM.attributes + 0x000000000000062c 0x32 build/usbd_core.o + .ARM.attributes + 0x000000000000065e 0x32 build/usbd_ctlreq.o + .ARM.attributes + 0x0000000000000690 0x32 build/usbd_ioreq.o + .ARM.attributes + 0x00000000000006c2 0x32 build/usbd_dfu.o + .ARM.attributes + 0x00000000000006f4 0x21 build/startup_stm32h750xx.o + .ARM.attributes + 0x0000000000000715 0x30 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) + .ARM.attributes + 0x0000000000000745 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x0000000000000777 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) + .ARM.attributes + 0x00000000000007a9 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x00000000000007db 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-freer.o) + .ARM.attributes + 0x000000000000080d 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + .ARM.attributes + 0x000000000000083f 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-sbrkr.o) + .ARM.attributes + 0x0000000000000871 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + .ARM.attributes + 0x00000000000008a3 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + .ARM.attributes + 0x00000000000008d5 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) + .ARM.attributes + 0x0000000000000907 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a(sbrk.o) + .ARM.attributes + 0x0000000000000939 0x1e /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x0000000000000957 0x32 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000000000000989 0x1e /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x00000000000009a7 0x1e /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtn.o +OUTPUT(build/STM32H750VB_Bootloader.elf elf32-littlearm) +LOAD linker stubs +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a +LOAD /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a + +.debug_info 0x0000000000000000 0x28582 + .debug_info 0x0000000000000000 0x2598 build/main.o + .debug_info 0x0000000000002598 0x16c4 build/stm32h7xx_it.o + .debug_info 0x0000000000003c5c 0x1c4a build/stm32h7xx_hal_msp.o + .debug_info 0x00000000000058a6 0x120f build/w25_qspi.o + .debug_info 0x0000000000006ab5 0x863 build/port_printf.o + .debug_info 0x0000000000007318 0x184f build/printf.o + .debug_info 0x0000000000008b67 0x24f build/bootloader_control.o + .debug_info 0x0000000000008db6 0x95e build/usb_device.o + .debug_info 0x0000000000009714 0x63d build/usbd_desc.o + .debug_info 0x0000000000009d51 0xe39 build/usbd_dfu_if.o + .debug_info 0x000000000000ab8a 0x27c8 build/usbd_conf.o + .debug_info 0x000000000000d352 0x1b93 build/stm32h7xx_hal_pcd.o + .debug_info 0x000000000000eee5 0xaed build/stm32h7xx_hal_pcd_ex.o + .debug_info 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build/startup_stm32h750xx.o +FPU_IRQHandler build/stm32h7xx_it.o +FS_Desc build/usbd_desc.o + build/usb_device.o +HAL_DBGMCU_DisableDBGSleepMode build/stm32h7xx_hal.o +HAL_DBGMCU_DisableDBGStandbyMode build/stm32h7xx_hal.o +HAL_DBGMCU_DisableDBGStopMode build/stm32h7xx_hal.o +HAL_DBGMCU_EnableDBGSleepMode build/stm32h7xx_hal.o +HAL_DBGMCU_EnableDBGStandbyMode build/stm32h7xx_hal.o +HAL_DBGMCU_EnableDBGStopMode build/stm32h7xx_hal.o +HAL_DMAEx_ChangeMemory build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_ConfigMuxRequestGenerator build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_ConfigMuxSync build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_DisableMuxRequestGenerator build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_EnableMuxRequestGenerator build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_MUX_IRQHandler build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_MultiBufferStart build/stm32h7xx_hal_dma_ex.o +HAL_DMAEx_MultiBufferStart_IT build/stm32h7xx_hal_dma_ex.o +HAL_DMA_Abort build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_uart.o +HAL_DMA_Abort_IT build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_i2c.o +HAL_DMA_DeInit build/stm32h7xx_hal_dma.o +HAL_DMA_GetError build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_i2c.o +HAL_DMA_GetState build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_i2c.o +HAL_DMA_IRQHandler build/stm32h7xx_hal_dma.o +HAL_DMA_Init build/stm32h7xx_hal_dma.o +HAL_DMA_PollForTransfer build/stm32h7xx_hal_dma.o +HAL_DMA_RegisterCallback build/stm32h7xx_hal_dma.o +HAL_DMA_Start build/stm32h7xx_hal_dma.o +HAL_DMA_Start_IT build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_i2c.o +HAL_DMA_UnRegisterCallback build/stm32h7xx_hal_dma.o +HAL_DeInit build/stm32h7xx_hal.o +HAL_Delay build/stm32h7xx_hal.o + build/usbd_dfu.o + build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd_ex.o + build/usbd_conf.o +HAL_DisableCompensationCell build/stm32h7xx_hal.o +HAL_DisableDomain3DBGStandbyMode build/stm32h7xx_hal.o +HAL_DisableDomain3DBGStopMode build/stm32h7xx_hal.o +HAL_EXTI_ClearConfigLine build/stm32h7xx_hal_exti.o +HAL_EXTI_ClearPending build/stm32h7xx_hal_exti.o +HAL_EXTI_D1_ClearFlag build/stm32h7xx_hal.o +HAL_EXTI_D1_EventInputConfig build/stm32h7xx_hal.o +HAL_EXTI_D3_EventInputConfig build/stm32h7xx_hal.o +HAL_EXTI_EdgeConfig build/stm32h7xx_hal.o +HAL_EXTI_GenerateSWI build/stm32h7xx_hal_exti.o +HAL_EXTI_GenerateSWInterrupt build/stm32h7xx_hal.o +HAL_EXTI_GetConfigLine build/stm32h7xx_hal_exti.o +HAL_EXTI_GetHandle build/stm32h7xx_hal_exti.o +HAL_EXTI_GetPending build/stm32h7xx_hal_exti.o +HAL_EXTI_IRQHandler build/stm32h7xx_hal_exti.o +HAL_EXTI_RegisterCallback build/stm32h7xx_hal_exti.o +HAL_EXTI_SetConfigLine build/stm32h7xx_hal_exti.o +HAL_EnableCompensationCell build/stm32h7xx_hal.o +HAL_EnableDomain3DBGStandbyMode build/stm32h7xx_hal.o +HAL_EnableDomain3DBGStopMode build/stm32h7xx_hal.o +HAL_FLASHEx_ComputeCRC build/stm32h7xx_hal_flash_ex.o +HAL_FLASHEx_Erase build/stm32h7xx_hal_flash_ex.o +HAL_FLASHEx_Erase_IT build/stm32h7xx_hal_flash_ex.o +HAL_FLASHEx_Lock_Bank1 build/stm32h7xx_hal_flash_ex.o +HAL_FLASHEx_OBGetConfig build/stm32h7xx_hal_flash_ex.o +HAL_FLASHEx_OBProgram build/stm32h7xx_hal_flash_ex.o +HAL_FLASHEx_Unlock_Bank1 build/stm32h7xx_hal_flash_ex.o +HAL_FLASH_EndOfOperationCallback build/stm32h7xx_hal_flash.o +HAL_FLASH_GetError build/stm32h7xx_hal_flash.o +HAL_FLASH_IRQHandler build/stm32h7xx_hal_flash.o + build/stm32h7xx_it.o +HAL_FLASH_Lock build/stm32h7xx_hal_flash.o +HAL_FLASH_OB_Launch build/stm32h7xx_hal_flash.o +HAL_FLASH_OB_Lock build/stm32h7xx_hal_flash.o +HAL_FLASH_OB_Unlock build/stm32h7xx_hal_flash.o +HAL_FLASH_OperationErrorCallback build/stm32h7xx_hal_flash.o +HAL_FLASH_Program build/stm32h7xx_hal_flash.o +HAL_FLASH_Program_IT build/stm32h7xx_hal_flash.o +HAL_FLASH_Unlock build/stm32h7xx_hal_flash.o +HAL_GPIO_DeInit build/stm32h7xx_hal_gpio.o + build/usbd_conf.o + build/stm32h7xx_hal_msp.o +HAL_GPIO_EXTI_Callback build/stm32h7xx_hal_gpio.o +HAL_GPIO_EXTI_IRQHandler build/stm32h7xx_hal_gpio.o +HAL_GPIO_Init build/stm32h7xx_hal_gpio.o + build/stm32h7xx_hal_rcc.o + build/usbd_conf.o + build/stm32h7xx_hal_msp.o + build/main.o +HAL_GPIO_LockPin build/stm32h7xx_hal_gpio.o +HAL_GPIO_ReadPin build/stm32h7xx_hal_gpio.o + build/usb_device.o +HAL_GPIO_TogglePin build/stm32h7xx_hal_gpio.o + build/usbd_dfu_if.o +HAL_GPIO_WritePin build/stm32h7xx_hal_gpio.o + build/main.o +HAL_GetCurrentCPUID build/stm32h7xx_hal_cortex.o +HAL_GetDEVID build/stm32h7xx_hal.o +HAL_GetFMCMemorySwappingConfig build/stm32h7xx_hal.o +HAL_GetHalVersion build/stm32h7xx_hal.o +HAL_GetREVID build/stm32h7xx_hal.o + build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_rcc.o +HAL_GetTick build/stm32h7xx_hal.o + build/stm32h7xx_hal_uart_ex.o + build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_qspi.o + build/stm32h7xx_hal_i2c.o + build/stm32h7xx_hal_pwr_ex.o + build/stm32h7xx_hal_mdma.o + build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_flash.o + build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_rcc.o + build/stm32h7xx_hal_pcd_ex.o +HAL_GetTickFreq build/stm32h7xx_hal.o +HAL_GetTickPrio build/stm32h7xx_hal.o +HAL_GetUIDw0 build/stm32h7xx_hal.o +HAL_GetUIDw1 build/stm32h7xx_hal.o +HAL_GetUIDw2 build/stm32h7xx_hal.o +HAL_HSEM_ActivateNotification build/stm32h7xx_hal_hsem.o +HAL_HSEM_DeactivateNotification build/stm32h7xx_hal_hsem.o +HAL_HSEM_FastTake build/stm32h7xx_hal_hsem.o +HAL_HSEM_FreeCallback build/stm32h7xx_hal_hsem.o +HAL_HSEM_GetClearKey build/stm32h7xx_hal_hsem.o +HAL_HSEM_IRQHandler build/stm32h7xx_hal_hsem.o + build/stm32h7xx_it.o +HAL_HSEM_IsSemTaken build/stm32h7xx_hal_hsem.o +HAL_HSEM_Release build/stm32h7xx_hal_hsem.o +HAL_HSEM_ReleaseAll build/stm32h7xx_hal_hsem.o +HAL_HSEM_SetClearKey build/stm32h7xx_hal_hsem.o +HAL_HSEM_Take build/stm32h7xx_hal_hsem.o +HAL_HalfDuplex_EnableReceiver build/stm32h7xx_hal_uart.o +HAL_HalfDuplex_EnableTransmitter build/stm32h7xx_hal_uart.o +HAL_HalfDuplex_Init build/stm32h7xx_hal_uart.o +HAL_I2CEx_ConfigAnalogFilter build/stm32h7xx_hal_i2c_ex.o +HAL_I2CEx_ConfigDigitalFilter build/stm32h7xx_hal_i2c_ex.o +HAL_I2CEx_DisableFastModePlus build/stm32h7xx_hal_i2c_ex.o +HAL_I2CEx_DisableWakeUp build/stm32h7xx_hal_i2c_ex.o +HAL_I2CEx_EnableFastModePlus build/stm32h7xx_hal_i2c_ex.o +HAL_I2CEx_EnableWakeUp build/stm32h7xx_hal_i2c_ex.o +HAL_I2C_AbortCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_AddrCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_DeInit build/stm32h7xx_hal_i2c.o +HAL_I2C_DisableListen_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_ER_IRQHandler build/stm32h7xx_hal_i2c.o +HAL_I2C_EV_IRQHandler build/stm32h7xx_hal_i2c.o +HAL_I2C_EnableListen_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_ErrorCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_GetError build/stm32h7xx_hal_i2c.o +HAL_I2C_GetMode build/stm32h7xx_hal_i2c.o +HAL_I2C_GetState build/stm32h7xx_hal_i2c.o +HAL_I2C_Init build/stm32h7xx_hal_i2c.o +HAL_I2C_IsDeviceReady build/stm32h7xx_hal_i2c.o +HAL_I2C_ListenCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_MasterRxCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_MasterTxCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Abort_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Receive build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Receive_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Receive_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Transmit build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Transmit_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Master_Transmit_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_MemRxCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_MemTxCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_Mem_Read build/stm32h7xx_hal_i2c.o +HAL_I2C_Mem_Read_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Mem_Read_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Mem_Write build/stm32h7xx_hal_i2c.o +HAL_I2C_Mem_Write_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Mem_Write_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_MspDeInit build/stm32h7xx_hal_i2c.o +HAL_I2C_MspInit build/stm32h7xx_hal_i2c.o +HAL_I2C_SlaveRxCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_SlaveTxCpltCallback build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Receive build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Receive_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Receive_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_IT build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Transmit build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Transmit_DMA build/stm32h7xx_hal_i2c.o +HAL_I2C_Slave_Transmit_IT build/stm32h7xx_hal_i2c.o +HAL_IncTick build/stm32h7xx_hal.o + build/stm32h7xx_it.o +HAL_Init build/stm32h7xx_hal.o + build/main.o +HAL_InitTick build/stm32h7xx_hal.o + build/stm32h7xx_hal_rcc.o +HAL_LIN_Init build/stm32h7xx_hal_uart.o +HAL_LIN_SendBreak build/stm32h7xx_hal_uart.o +HAL_MDMA_Abort build/stm32h7xx_hal_mdma.o + build/stm32h7xx_hal_qspi.o +HAL_MDMA_Abort_IT build/stm32h7xx_hal_mdma.o + build/stm32h7xx_hal_qspi.o +HAL_MDMA_ConfigPostRequestMask build/stm32h7xx_hal_mdma.o +HAL_MDMA_DeInit build/stm32h7xx_hal_mdma.o +HAL_MDMA_GenerateSWRequest build/stm32h7xx_hal_mdma.o +HAL_MDMA_GetError build/stm32h7xx_hal_mdma.o +HAL_MDMA_GetState build/stm32h7xx_hal_mdma.o +HAL_MDMA_IRQHandler build/stm32h7xx_hal_mdma.o +HAL_MDMA_Init build/stm32h7xx_hal_mdma.o +HAL_MDMA_LinkedList_AddNode build/stm32h7xx_hal_mdma.o +HAL_MDMA_LinkedList_CreateNode build/stm32h7xx_hal_mdma.o +HAL_MDMA_LinkedList_DisableCircularMode build/stm32h7xx_hal_mdma.o +HAL_MDMA_LinkedList_EnableCircularMode build/stm32h7xx_hal_mdma.o +HAL_MDMA_LinkedList_RemoveNode build/stm32h7xx_hal_mdma.o +HAL_MDMA_PollForTransfer build/stm32h7xx_hal_mdma.o +HAL_MDMA_RegisterCallback build/stm32h7xx_hal_mdma.o +HAL_MDMA_Start build/stm32h7xx_hal_mdma.o +HAL_MDMA_Start_IT build/stm32h7xx_hal_mdma.o + build/stm32h7xx_hal_qspi.o +HAL_MDMA_UnRegisterCallback build/stm32h7xx_hal_mdma.o +HAL_MPU_ConfigRegion build/stm32h7xx_hal_cortex.o +HAL_MPU_Disable build/stm32h7xx_hal_cortex.o +HAL_MPU_Enable build/stm32h7xx_hal_cortex.o +HAL_MspDeInit build/stm32h7xx_hal.o +HAL_MspInit build/stm32h7xx_hal_msp.o +HAL_MultiProcessorEx_AddressLength_Set build/stm32h7xx_hal_uart_ex.o +HAL_MultiProcessor_DisableMuteMode build/stm32h7xx_hal_uart.o +HAL_MultiProcessor_EnableMuteMode build/stm32h7xx_hal_uart.o +HAL_MultiProcessor_EnterMuteMode build/stm32h7xx_hal_uart.o +HAL_MultiProcessor_Init build/stm32h7xx_hal_uart.o +HAL_NVIC_ClearPendingIRQ build/stm32h7xx_hal_cortex.o +HAL_NVIC_DisableIRQ build/stm32h7xx_hal_cortex.o + build/usbd_conf.o + build/stm32h7xx_hal_msp.o +HAL_NVIC_EnableIRQ build/stm32h7xx_hal_cortex.o + build/usbd_conf.o + build/stm32h7xx_hal_msp.o +HAL_NVIC_GetActive build/stm32h7xx_hal_cortex.o +HAL_NVIC_GetPendingIRQ build/stm32h7xx_hal_cortex.o +HAL_NVIC_GetPriority build/stm32h7xx_hal_cortex.o +HAL_NVIC_GetPriorityGrouping build/stm32h7xx_hal_cortex.o +HAL_NVIC_SetPendingIRQ build/stm32h7xx_hal_cortex.o +HAL_NVIC_SetPriority build/stm32h7xx_hal_cortex.o + build/stm32h7xx_hal.o + build/usbd_conf.o + build/stm32h7xx_hal_msp.o +HAL_NVIC_SetPriorityGrouping build/stm32h7xx_hal_cortex.o + build/stm32h7xx_hal.o +HAL_NVIC_SystemReset build/stm32h7xx_hal_cortex.o +HAL_PCDEx_ActivateBCD build/stm32h7xx_hal_pcd_ex.o +HAL_PCDEx_ActivateLPM build/stm32h7xx_hal_pcd_ex.o + build/stm32h7xx_hal_pcd.o +HAL_PCDEx_BCD_Callback build/stm32h7xx_hal_pcd_ex.o +HAL_PCDEx_BCD_VBUSDetect build/stm32h7xx_hal_pcd_ex.o +HAL_PCDEx_DeActivateBCD build/stm32h7xx_hal_pcd_ex.o +HAL_PCDEx_DeActivateLPM build/stm32h7xx_hal_pcd_ex.o +HAL_PCDEx_LPM_Callback build/stm32h7xx_hal_pcd_ex.o + build/stm32h7xx_hal_pcd.o +HAL_PCDEx_SetRxFiFo build/stm32h7xx_hal_pcd_ex.o + build/usbd_conf.o +HAL_PCDEx_SetTxFiFo build/stm32h7xx_hal_pcd_ex.o + build/usbd_conf.o +HAL_PCD_ActivateRemoteWakeup build/stm32h7xx_hal_pcd.o +HAL_PCD_ConnectCallback build/usbd_conf.o +HAL_PCD_DataInStageCallback build/usbd_conf.o +HAL_PCD_DataOutStageCallback build/usbd_conf.o +HAL_PCD_DeActivateRemoteWakeup build/stm32h7xx_hal_pcd.o +HAL_PCD_DeInit build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_DevConnect build/stm32h7xx_hal_pcd.o +HAL_PCD_DevDisconnect build/stm32h7xx_hal_pcd.o +HAL_PCD_DisconnectCallback build/usbd_conf.o +HAL_PCD_EP_Close build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_ClrStall build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_Flush build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_GetRxCount build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_Open build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_Receive build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_SetStall build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_EP_Transmit build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_GetState build/stm32h7xx_hal_pcd.o +HAL_PCD_IRQHandler build/stm32h7xx_hal_pcd.o + build/stm32h7xx_it.o +HAL_PCD_ISOINIncompleteCallback build/usbd_conf.o +HAL_PCD_ISOOUTIncompleteCallback build/usbd_conf.o +HAL_PCD_Init build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_MspDeInit build/usbd_conf.o +HAL_PCD_MspInit build/usbd_conf.o +HAL_PCD_ResetCallback build/usbd_conf.o +HAL_PCD_ResumeCallback build/usbd_conf.o +HAL_PCD_SOFCallback build/usbd_conf.o +HAL_PCD_SetAddress build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_SetupStageCallback build/usbd_conf.o +HAL_PCD_Start build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_Stop build/stm32h7xx_hal_pcd.o + build/usbd_conf.o +HAL_PCD_SuspendCallback build/usbd_conf.o +HAL_PWREx_AVDCallback build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_ClearPendingEvent build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_ClearWakeupFlag build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_ConfigAVD build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_ConfigD3Domain build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_ConfigSupply build/stm32h7xx_hal_pwr_ex.o + build/main.o +HAL_PWREx_ControlStopModeVoltageScaling build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_ControlVoltageScaling build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableAVD build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableBatteryCharging build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableBkUpReg build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableFlashPowerDown build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableMonitoring build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableUSBReg build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableUSBVoltageDetector build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_DisableWakeUpPin build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableAVD build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableBatteryCharging build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableBkUpReg build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableFlashPowerDown build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableMonitoring build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableUSBReg build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnableUSBVoltageDetector build/stm32h7xx_hal_pwr_ex.o + build/usb_device.o + build/main.o +HAL_PWREx_EnableWakeUpPin build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnterSTANDBYMode build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_EnterSTOPMode build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_GetStopModeVoltageRange build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_GetSupplyConfig build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_GetTemperatureLevel build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_GetVBATLevel build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_GetVoltageRange build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_GetWakeupFlag build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_PVD_AVD_IRQHandler build/stm32h7xx_hal_pwr_ex.o + build/stm32h7xx_it.o +HAL_PWREx_WAKEUP_PIN_IRQHandler build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_WKUP1_Callback build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_WKUP2_Callback build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_WKUP3_Callback build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_WKUP4_Callback build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_WKUP5_Callback build/stm32h7xx_hal_pwr_ex.o +HAL_PWREx_WKUP6_Callback build/stm32h7xx_hal_pwr_ex.o +HAL_PWR_ConfigPVD build/stm32h7xx_hal_pwr.o +HAL_PWR_DeInit build/stm32h7xx_hal_pwr.o +HAL_PWR_DisableBkUpAccess build/stm32h7xx_hal_pwr.o +HAL_PWR_DisablePVD build/stm32h7xx_hal_pwr.o +HAL_PWR_DisableSEVOnPend build/stm32h7xx_hal_pwr.o +HAL_PWR_DisableSleepOnExit build/stm32h7xx_hal_pwr.o +HAL_PWR_DisableWakeUpPin build/stm32h7xx_hal_pwr.o +HAL_PWR_EnableBkUpAccess build/stm32h7xx_hal_pwr.o +HAL_PWR_EnablePVD build/stm32h7xx_hal_pwr.o +HAL_PWR_EnableSEVOnPend build/stm32h7xx_hal_pwr.o +HAL_PWR_EnableSleepOnExit build/stm32h7xx_hal_pwr.o +HAL_PWR_EnableWakeUpPin build/stm32h7xx_hal_pwr.o +HAL_PWR_EnterSLEEPMode build/stm32h7xx_hal_pwr.o +HAL_PWR_EnterSTANDBYMode build/stm32h7xx_hal_pwr.o +HAL_PWR_EnterSTOPMode build/stm32h7xx_hal_pwr.o +HAL_PWR_PVDCallback build/stm32h7xx_hal_pwr.o + build/stm32h7xx_hal_pwr_ex.o +HAL_PWR_PVD_IRQHandler build/stm32h7xx_hal_pwr.o +HAL_QSPI_Abort build/stm32h7xx_hal_qspi.o +HAL_QSPI_AbortCpltCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_Abort_IT build/stm32h7xx_hal_qspi.o +HAL_QSPI_AutoPolling build/stm32h7xx_hal_qspi.o +HAL_QSPI_AutoPolling_IT build/stm32h7xx_hal_qspi.o + build/w25_qspi.o +HAL_QSPI_CmdCpltCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_Command build/stm32h7xx_hal_qspi.o + build/w25_qspi.o +HAL_QSPI_Command_IT build/stm32h7xx_hal_qspi.o +HAL_QSPI_DeInit build/stm32h7xx_hal_qspi.o +HAL_QSPI_ErrorCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_FifoThresholdCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_GetError build/stm32h7xx_hal_qspi.o +HAL_QSPI_GetFifoThreshold build/stm32h7xx_hal_qspi.o +HAL_QSPI_GetState build/stm32h7xx_hal_qspi.o +HAL_QSPI_IRQHandler build/stm32h7xx_hal_qspi.o + build/stm32h7xx_it.o +HAL_QSPI_Init build/stm32h7xx_hal_qspi.o + build/main.o +HAL_QSPI_MemoryMapped build/stm32h7xx_hal_qspi.o + build/main.o +HAL_QSPI_MspDeInit build/stm32h7xx_hal_msp.o +HAL_QSPI_MspInit build/stm32h7xx_hal_msp.o +HAL_QSPI_Receive build/stm32h7xx_hal_qspi.o + build/w25_qspi.o +HAL_QSPI_Receive_DMA build/stm32h7xx_hal_qspi.o +HAL_QSPI_Receive_IT build/stm32h7xx_hal_qspi.o +HAL_QSPI_RxCpltCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_SetFifoThreshold build/stm32h7xx_hal_qspi.o +HAL_QSPI_SetFlashID build/stm32h7xx_hal_qspi.o +HAL_QSPI_SetTimeout build/stm32h7xx_hal_qspi.o +HAL_QSPI_StatusMatchCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_TimeOutCallback build/stm32h7xx_hal_qspi.o +HAL_QSPI_Transmit build/stm32h7xx_hal_qspi.o + build/w25_qspi.o +HAL_QSPI_Transmit_DMA build/stm32h7xx_hal_qspi.o +HAL_QSPI_Transmit_IT build/stm32h7xx_hal_qspi.o +HAL_QSPI_TxCpltCallback build/stm32h7xx_hal_qspi.o +HAL_RCCEx_CRSConfig build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRSGetSynchronizationInfo build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRSSoftwareSynchronizationGenerate build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRSWaitSynchronization build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRS_ErrorCallback build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRS_ExpectedSyncCallback build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRS_IRQHandler build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRS_SyncOkCallback build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_CRS_SyncWarnCallback build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_DisableLSECSS build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_EnableLSECSS build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_EnableLSECSS_IT build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_GetD1PCLK1Freq build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_GetD1SysClockFreq build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_GetD3PCLK1Freq build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_uart.o +HAL_RCCEx_GetPLL1ClockFreq build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_GetPLL2ClockFreq build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_uart.o +HAL_RCCEx_GetPLL3ClockFreq build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_uart.o +HAL_RCCEx_GetPeriphCLKConfig build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_GetPeriphCLKFreq build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_KerWakeUpStopCLKConfig build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_LSECSS_Callback build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_LSECSS_IRQHandler build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_PeriphCLKConfig build/stm32h7xx_hal_rcc_ex.o + build/main.o +HAL_RCCEx_WWDGxSysResetConfig build/stm32h7xx_hal_rcc_ex.o +HAL_RCCEx_WakeUpStopCLKConfig build/stm32h7xx_hal_rcc_ex.o +HAL_RCC_CSSCallback build/stm32h7xx_hal_rcc.o +HAL_RCC_ClockConfig build/stm32h7xx_hal_rcc.o + build/main.o +HAL_RCC_DeInit build/stm32h7xx_hal_rcc.o +HAL_RCC_DisableCSS build/stm32h7xx_hal_rcc.o +HAL_RCC_EnableCSS build/stm32h7xx_hal_rcc.o +HAL_RCC_GetClockConfig build/stm32h7xx_hal_rcc.o +HAL_RCC_GetHCLKFreq build/stm32h7xx_hal_rcc.o + build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_pcd.o +HAL_RCC_GetOscConfig build/stm32h7xx_hal_rcc.o +HAL_RCC_GetPCLK1Freq build/stm32h7xx_hal_rcc.o + build/stm32h7xx_hal_uart.o +HAL_RCC_GetPCLK2Freq build/stm32h7xx_hal_rcc.o + build/stm32h7xx_hal_uart.o +HAL_RCC_GetSysClockFreq build/stm32h7xx_hal_rcc.o + build/stm32h7xx_hal.o + build/stm32h7xx_hal_rcc_ex.o +HAL_RCC_MCOConfig build/stm32h7xx_hal_rcc.o +HAL_RCC_NMI_IRQHandler build/stm32h7xx_hal_rcc.o +HAL_RCC_OscConfig build/stm32h7xx_hal_rcc.o + build/main.o +HAL_RS485Ex_Init build/stm32h7xx_hal_uart_ex.o +HAL_ResumeTick build/stm32h7xx_hal.o +HAL_SYSCFG_AnalogSwitchConfig build/stm32h7xx_hal.o +HAL_SYSCFG_CM7BootAddConfig build/stm32h7xx_hal.o +HAL_SYSCFG_CompensationCodeConfig build/stm32h7xx_hal.o +HAL_SYSCFG_CompensationCodeSelect build/stm32h7xx_hal.o +HAL_SYSCFG_DisableBOOST build/stm32h7xx_hal.o +HAL_SYSCFG_DisableIOSpeedOptimize build/stm32h7xx_hal.o +HAL_SYSCFG_DisableVREFBUF build/stm32h7xx_hal.o +HAL_SYSCFG_ETHInterfaceSelect build/stm32h7xx_hal.o +HAL_SYSCFG_EnableBOOST build/stm32h7xx_hal.o +HAL_SYSCFG_EnableIOSpeedOptimize build/stm32h7xx_hal.o +HAL_SYSCFG_EnableVREFBUF build/stm32h7xx_hal.o +HAL_SYSCFG_VREFBUF_HighImpedanceConfig build/stm32h7xx_hal.o +HAL_SYSCFG_VREFBUF_TrimmingConfig build/stm32h7xx_hal.o +HAL_SYSCFG_VREFBUF_VoltageScalingConfig build/stm32h7xx_hal.o +HAL_SYSTICK_CLKSourceConfig build/stm32h7xx_hal_cortex.o +HAL_SYSTICK_Callback build/stm32h7xx_hal_cortex.o +HAL_SYSTICK_Config build/stm32h7xx_hal_cortex.o + build/stm32h7xx_hal.o +HAL_SYSTICK_IRQHandler build/stm32h7xx_hal_cortex.o +HAL_SetFMCMemorySwappingConfig build/stm32h7xx_hal.o +HAL_SetTickFreq build/stm32h7xx_hal.o +HAL_SuspendTick build/stm32h7xx_hal.o +HAL_UARTEx_DisableFifoMode build/stm32h7xx_hal_uart_ex.o + build/main.o +HAL_UARTEx_DisableStopMode build/stm32h7xx_hal_uart_ex.o +HAL_UARTEx_EnableFifoMode build/stm32h7xx_hal_uart_ex.o +HAL_UARTEx_EnableStopMode build/stm32h7xx_hal_uart_ex.o +HAL_UARTEx_RxFifoFullCallback build/stm32h7xx_hal_uart_ex.o + build/stm32h7xx_hal_uart.o +HAL_UARTEx_SetRxFifoThreshold build/stm32h7xx_hal_uart_ex.o + build/main.o +HAL_UARTEx_SetTxFifoThreshold build/stm32h7xx_hal_uart_ex.o + build/main.o +HAL_UARTEx_StopModeWakeUpSourceConfig build/stm32h7xx_hal_uart_ex.o +HAL_UARTEx_TxFifoEmptyCallback build/stm32h7xx_hal_uart_ex.o + build/stm32h7xx_hal_uart.o +HAL_UARTEx_WakeupCallback build/stm32h7xx_hal_uart_ex.o + build/stm32h7xx_hal_uart.o +HAL_UART_Abort build/stm32h7xx_hal_uart.o +HAL_UART_AbortCpltCallback build/stm32h7xx_hal_uart.o +HAL_UART_AbortReceive build/stm32h7xx_hal_uart.o +HAL_UART_AbortReceiveCpltCallback build/stm32h7xx_hal_uart.o +HAL_UART_AbortReceive_IT build/stm32h7xx_hal_uart.o +HAL_UART_AbortTransmit build/stm32h7xx_hal_uart.o +HAL_UART_AbortTransmitCpltCallback build/stm32h7xx_hal_uart.o +HAL_UART_AbortTransmit_IT build/stm32h7xx_hal_uart.o +HAL_UART_Abort_IT build/stm32h7xx_hal_uart.o +HAL_UART_DMAPause build/stm32h7xx_hal_uart.o +HAL_UART_DMAResume build/stm32h7xx_hal_uart.o +HAL_UART_DMAStop build/stm32h7xx_hal_uart.o +HAL_UART_DeInit build/stm32h7xx_hal_uart.o +HAL_UART_DisableReceiverTimeout build/stm32h7xx_hal_uart.o +HAL_UART_EnableReceiverTimeout build/stm32h7xx_hal_uart.o +HAL_UART_ErrorCallback build/stm32h7xx_hal_uart.o +HAL_UART_GetError build/stm32h7xx_hal_uart.o +HAL_UART_GetState build/stm32h7xx_hal_uart.o +HAL_UART_IRQHandler build/stm32h7xx_hal_uart.o + build/stm32h7xx_it.o +HAL_UART_Init build/stm32h7xx_hal_uart.o + build/main.o +HAL_UART_MspDeInit build/stm32h7xx_hal_msp.o +HAL_UART_MspInit build/stm32h7xx_hal_msp.o + build/stm32h7xx_hal_uart_ex.o +HAL_UART_Receive build/stm32h7xx_hal_uart.o +HAL_UART_Receive_DMA build/stm32h7xx_hal_uart.o +HAL_UART_Receive_IT build/stm32h7xx_hal_uart.o +HAL_UART_ReceiverTimeout_Config build/stm32h7xx_hal_uart.o +HAL_UART_RxCpltCallback build/stm32h7xx_hal_uart.o +HAL_UART_RxHalfCpltCallback build/stm32h7xx_hal_uart.o +HAL_UART_Transmit build/stm32h7xx_hal_uart.o + build/port_printf.o +HAL_UART_Transmit_DMA build/stm32h7xx_hal_uart.o +HAL_UART_Transmit_IT build/stm32h7xx_hal_uart.o +HAL_UART_TxCpltCallback build/stm32h7xx_hal_uart.o +HAL_UART_TxHalfCpltCallback build/stm32h7xx_hal_uart.o +HASH_RNG_IRQHandler build/startup_stm32h750xx.o +HRTIM1_FLT_IRQHandler build/startup_stm32h750xx.o +HRTIM1_Master_IRQHandler build/startup_stm32h750xx.o +HRTIM1_TIMA_IRQHandler build/startup_stm32h750xx.o +HRTIM1_TIMB_IRQHandler build/startup_stm32h750xx.o +HRTIM1_TIMC_IRQHandler build/startup_stm32h750xx.o +HRTIM1_TIMD_IRQHandler build/startup_stm32h750xx.o +HRTIM1_TIME_IRQHandler build/startup_stm32h750xx.o +HSEM1_IRQHandler build/stm32h7xx_it.o +HardFault_Handler build/stm32h7xx_it.o +I2C1_ER_IRQHandler build/startup_stm32h750xx.o +I2C1_EV_IRQHandler build/startup_stm32h750xx.o +I2C2_ER_IRQHandler build/startup_stm32h750xx.o +I2C2_EV_IRQHandler build/startup_stm32h750xx.o +I2C3_ER_IRQHandler build/startup_stm32h750xx.o +I2C3_EV_IRQHandler build/startup_stm32h750xx.o +I2C4_ER_IRQHandler build/startup_stm32h750xx.o +I2C4_EV_IRQHandler build/startup_stm32h750xx.o +JPEG_IRQHandler build/startup_stm32h750xx.o +LPTIM1_IRQHandler build/startup_stm32h750xx.o +LPTIM2_IRQHandler build/startup_stm32h750xx.o +LPTIM3_IRQHandler build/startup_stm32h750xx.o +LPTIM4_IRQHandler build/startup_stm32h750xx.o +LPTIM5_IRQHandler build/startup_stm32h750xx.o +LPUART1_IRQHandler build/startup_stm32h750xx.o +LTDC_ER_IRQHandler build/startup_stm32h750xx.o +LTDC_IRQHandler build/startup_stm32h750xx.o +MDIOS_IRQHandler build/startup_stm32h750xx.o +MDIOS_WKUP_IRQHandler build/startup_stm32h750xx.o +MDMA_IRQHandler build/startup_stm32h750xx.o +MX_USB_DEVICE_Init build/usb_device.o + build/main.o +MemManage_Handler build/stm32h7xx_it.o +NMI_Handler build/stm32h7xx_it.o +OTG_FS_EP1_IN_IRQHandler build/stm32h7xx_it.o +OTG_FS_EP1_OUT_IRQHandler build/stm32h7xx_it.o +OTG_FS_IRQHandler build/stm32h7xx_it.o +OTG_FS_WKUP_IRQHandler build/startup_stm32h750xx.o +OTG_HS_EP1_IN_IRQHandler build/startup_stm32h750xx.o +OTG_HS_EP1_OUT_IRQHandler build/startup_stm32h750xx.o +OTG_HS_IRQHandler build/startup_stm32h750xx.o +OTG_HS_WKUP_IRQHandler build/startup_stm32h750xx.o +PVD_AVD_IRQHandler build/stm32h7xx_it.o +PendSV_Handler build/stm32h7xx_it.o +QUADSPI_IRQHandler build/stm32h7xx_it.o +RCC_IRQHandler build/stm32h7xx_it.o +RTC_Alarm_IRQHandler build/startup_stm32h750xx.o +RTC_WKUP_IRQHandler build/startup_stm32h750xx.o +Reset_Handler build/startup_stm32h750xx.o +SAI1_IRQHandler build/startup_stm32h750xx.o +SAI2_IRQHandler build/startup_stm32h750xx.o +SAI3_IRQHandler build/startup_stm32h750xx.o +SAI4_IRQHandler build/startup_stm32h750xx.o +SDMMC1_IRQHandler build/startup_stm32h750xx.o +SDMMC2_IRQHandler build/startup_stm32h750xx.o +SPDIF_RX_IRQHandler build/startup_stm32h750xx.o +SPI1_IRQHandler build/startup_stm32h750xx.o +SPI2_IRQHandler build/startup_stm32h750xx.o +SPI3_IRQHandler build/startup_stm32h750xx.o +SPI4_IRQHandler build/startup_stm32h750xx.o +SPI5_IRQHandler build/startup_stm32h750xx.o +SPI6_IRQHandler build/startup_stm32h750xx.o +SVC_Handler build/stm32h7xx_it.o +SWPMI1_IRQHandler build/startup_stm32h750xx.o +SysTick_Handler build/stm32h7xx_it.o +SystemClock_Config build/main.o +SystemCoreClock build/system_stm32h7xx.o + build/stm32h7xx_hal.o + build/stm32h7xx_hal_mdma.o + build/stm32h7xx_hal_dma.o + build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_rcc.o +SystemCoreClockUpdate build/system_stm32h7xx.o +SystemD2Clock build/system_stm32h7xx.o + build/stm32h7xx_hal.o + build/stm32h7xx_hal_rcc_ex.o + build/stm32h7xx_hal_rcc.o +SystemInit build/system_stm32h7xx.o + build/startup_stm32h750xx.o +TAMP_STAMP_IRQHandler build/startup_stm32h750xx.o +TIM15_IRQHandler build/startup_stm32h750xx.o +TIM16_IRQHandler build/startup_stm32h750xx.o +TIM17_IRQHandler build/startup_stm32h750xx.o +TIM1_BRK_IRQHandler build/startup_stm32h750xx.o +TIM1_CC_IRQHandler build/startup_stm32h750xx.o +TIM1_TRG_COM_IRQHandler build/startup_stm32h750xx.o +TIM1_UP_IRQHandler build/startup_stm32h750xx.o +TIM2_IRQHandler build/startup_stm32h750xx.o +TIM3_IRQHandler build/startup_stm32h750xx.o +TIM4_IRQHandler build/startup_stm32h750xx.o +TIM5_IRQHandler build/startup_stm32h750xx.o +TIM6_DAC_IRQHandler build/startup_stm32h750xx.o +TIM7_IRQHandler build/startup_stm32h750xx.o +TIM8_BRK_TIM12_IRQHandler build/startup_stm32h750xx.o +TIM8_CC_IRQHandler build/startup_stm32h750xx.o +TIM8_TRG_COM_TIM14_IRQHandler build/startup_stm32h750xx.o +TIM8_UP_TIM13_IRQHandler build/startup_stm32h750xx.o +UART4_IRQHandler build/startup_stm32h750xx.o +UART5_IRQHandler build/startup_stm32h750xx.o +UART7_IRQHandler build/startup_stm32h750xx.o +UART8_IRQHandler build/startup_stm32h750xx.o +UARTPrescTable build/stm32h7xx_hal_uart.o +UART_AdvFeatureConfig build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_uart_ex.o +UART_CheckIdleState build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_uart_ex.o +UART_SetConfig build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_uart_ex.o +UART_WaitOnFlagUntilTimeout build/stm32h7xx_hal_uart.o + build/stm32h7xx_hal_uart_ex.o +USART1_IRQHandler build/stm32h7xx_it.o +USART2_IRQHandler build/startup_stm32h750xx.o +USART3_IRQHandler build/startup_stm32h750xx.o +USART6_IRQHandler build/startup_stm32h750xx.o +USBD_ClrClassConfig build/usbd_core.o + build/usbd_ctlreq.o +USBD_CtlContinueRx build/usbd_ioreq.o + build/usbd_core.o +USBD_CtlContinueSendData build/usbd_ioreq.o + build/usbd_core.o +USBD_CtlError build/usbd_ctlreq.o + build/usbd_dfu.o +USBD_CtlPrepareRx build/usbd_ioreq.o + build/usbd_dfu.o +USBD_CtlReceiveStatus build/usbd_ioreq.o + build/usbd_core.o +USBD_CtlSendData build/usbd_ioreq.o + build/usbd_dfu.o + build/usbd_ctlreq.o +USBD_CtlSendStatus build/usbd_ioreq.o + build/usbd_ctlreq.o + build/usbd_core.o +USBD_DFU build/usbd_dfu.o + build/usb_device.o +USBD_DFU_RegisterMedia build/usbd_dfu.o + build/usb_device.o +USBD_DFU_fops_FS build/usbd_dfu_if.o + build/usb_device.o +USBD_DeInit build/usbd_core.o +USBD_FS_ConfigStrDescriptor build/usbd_desc.o +USBD_FS_DeviceDesc build/usbd_desc.o +USBD_FS_DeviceDescriptor build/usbd_desc.o +USBD_FS_InterfaceStrDescriptor build/usbd_desc.o +USBD_FS_LangIDStrDescriptor build/usbd_desc.o +USBD_FS_ManufacturerStrDescriptor build/usbd_desc.o +USBD_FS_ProductStrDescriptor build/usbd_desc.o +USBD_FS_SerialStrDescriptor build/usbd_desc.o +USBD_GetRxCount build/usbd_ioreq.o +USBD_GetString build/usbd_ctlreq.o + build/usbd_dfu.o + build/usbd_desc.o +USBD_Get_USB_Status build/usbd_conf.o +USBD_Init build/usbd_core.o + build/usb_device.o +USBD_LL_ClearStallEP build/usbd_conf.o + build/usbd_ctlreq.o +USBD_LL_CloseEP build/usbd_conf.o +USBD_LL_DataInStage build/usbd_core.o + build/usbd_conf.o +USBD_LL_DataOutStage build/usbd_core.o + build/usbd_conf.o +USBD_LL_DeInit build/usbd_conf.o + build/usbd_core.o +USBD_LL_Delay build/usbd_conf.o +USBD_LL_DevConnected build/usbd_core.o + build/usbd_conf.o +USBD_LL_DevDisconnected build/usbd_core.o + build/usbd_conf.o +USBD_LL_FlushEP build/usbd_conf.o +USBD_LL_GetRxDataSize build/usbd_conf.o + build/usbd_ioreq.o +USBD_LL_Init build/usbd_conf.o + build/usbd_core.o +USBD_LL_IsStallEP build/usbd_conf.o + build/usbd_ctlreq.o +USBD_LL_IsoINIncomplete build/usbd_core.o + build/usbd_conf.o +USBD_LL_IsoOUTIncomplete build/usbd_core.o + build/usbd_conf.o +USBD_LL_OpenEP build/usbd_conf.o + build/usbd_core.o +USBD_LL_PrepareReceive build/usbd_conf.o + build/usbd_ioreq.o + build/usbd_core.o +USBD_LL_Reset build/usbd_core.o + build/usbd_conf.o +USBD_LL_Resume build/usbd_core.o + build/usbd_conf.o +USBD_LL_SOF build/usbd_core.o + build/usbd_conf.o +USBD_LL_SetSpeed build/usbd_core.o + build/usbd_conf.o +USBD_LL_SetUSBAddress build/usbd_conf.o + build/usbd_ctlreq.o +USBD_LL_SetupStage build/usbd_core.o + build/usbd_conf.o +USBD_LL_StallEP build/usbd_conf.o + build/usbd_ctlreq.o + build/usbd_core.o +USBD_LL_Start build/usbd_conf.o + build/usbd_core.o +USBD_LL_Stop build/usbd_conf.o + build/usbd_core.o +USBD_LL_Suspend build/usbd_core.o + build/usbd_conf.o +USBD_LL_Transmit build/usbd_conf.o + build/usbd_ioreq.o +USBD_LangIDDesc build/usbd_desc.o +USBD_ParseSetupRequest build/usbd_ctlreq.o + build/usbd_core.o +USBD_RegisterClass build/usbd_core.o + build/usb_device.o +USBD_RunTestMode build/usbd_core.o +USBD_SetClassConfig build/usbd_core.o + build/usbd_ctlreq.o +USBD_Start build/usbd_core.o + build/usbd_dfu.o + build/usb_device.o +USBD_StdDevReq build/usbd_ctlreq.o + build/usbd_core.o +USBD_StdEPReq build/usbd_ctlreq.o + build/usbd_core.o +USBD_StdItfReq build/usbd_ctlreq.o + build/usbd_core.o +USBD_Stop build/usbd_core.o + build/usbd_dfu.o +USBD_StrDesc build/usbd_desc.o +USBD_StringSerial build/usbd_desc.o +USB_ActivateDedicatedEndpoint build/stm32h7xx_ll_usb.o +USB_ActivateEndpoint build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ActivateRemoteWakeup build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ActivateSetup build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ClearInterrupts build/stm32h7xx_ll_usb.o +USB_CoreInit build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DeActivateRemoteWakeup build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DeactivateDedicatedEndpoint build/stm32h7xx_ll_usb.o +USB_DeactivateEndpoint build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DevConnect build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DevDisconnect build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DevInit build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DisableGlobalInt build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_DoPing build/stm32h7xx_ll_usb.o +USB_DriveVbus build/stm32h7xx_ll_usb.o +USB_EP0StartXfer build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_EP0_OutStart build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_EPClearStall build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_EPSetStall build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_EPStartXfer build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_EnableGlobalInt build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_FlushRxFifo build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_FlushTxFifo build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_GetCurrentFrame build/stm32h7xx_ll_usb.o +USB_GetDevSpeed build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_GetHostSpeed build/stm32h7xx_ll_usb.o +USB_GetMode build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_HC_Halt build/stm32h7xx_ll_usb.o +USB_HC_Init build/stm32h7xx_ll_usb.o +USB_HC_ReadInterrupt build/stm32h7xx_ll_usb.o +USB_HC_StartXfer build/stm32h7xx_ll_usb.o +USB_HostInit build/stm32h7xx_ll_usb.o +USB_InitFSLSPClkSel build/stm32h7xx_ll_usb.o +USB_ReadDevAllInEpInterrupt build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ReadDevAllOutEpInterrupt build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ReadDevInEPInterrupt build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ReadDevOutEPInterrupt build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ReadInterrupts build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ReadPacket build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_ResetPort build/stm32h7xx_ll_usb.o +USB_SetCurrentMode build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_SetDevAddress build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_SetDevSpeed build/stm32h7xx_ll_usb.o +USB_SetTurnaroundTime build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_StopDevice build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +USB_StopHost build/stm32h7xx_ll_usb.o +USB_WritePacket build/stm32h7xx_ll_usb.o + build/stm32h7xx_hal_pcd.o +UsageFault_Handler build/stm32h7xx_it.o +W25_QPI_Mode build/w25_qspi.o + build/usbd_dfu_if.o + build/main.o +W25_QPI_ReadParams build/w25_qspi.o + build/main.o +W25_QSPI_Erase_Sector build/w25_qspi.o + build/usbd_dfu_if.o +W25_QSPI_Init build/w25_qspi.o + build/usbd_dfu_if.o + build/main.o +W25_QSPI_Program_Page build/w25_qspi.o + build/usbd_dfu_if.o +W25_QSPI_QuadEnable build/w25_qspi.o + build/main.o +W25_QSPI_Read build/w25_qspi.o + build/usbd_dfu_if.o +WAKEUP_PIN_IRQHandler build/startup_stm32h750xx.o +WWDG_IRQHandler build/startup_stm32h750xx.o +_W25_GetDefaultCommand build/w25_qspi.o +_W25_QSPI_Identify build/w25_qspi.o +_W25_Wait_Ready build/w25_qspi.o +_W25_Write_Enable build/w25_qspi.o +_W25_Write_Volatile_Enable build/w25_qspi.o +__aeabi_idiv0 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) +__aeabi_ldiv0 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) +__aeabi_uldivmod /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + build/stm32h7xx_hal_uart.o + build/printf.o +__atexit_dummy /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +__atexit_recursive_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +__bss_end__ /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__bss_start__ /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__call_exitprocs /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o) +__deregister_frame_info /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o +__dso_handle /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o +__fini_array_end /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o) +__fini_array_start /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o) +__init_array_end /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) +__init_array_start /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) +__libc_fini_array /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__libc_init_array /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) + build/startup_stm32h750xx.o + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__lock___arc4random_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__lock___at_quick_exit_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__lock___atexit_recursive_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o) +__lock___dd_hash_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__lock___env_recursive_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__lock___malloc_recursive_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) +__lock___sfp_recursive_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__lock___sinit_recursive_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__lock___tz_mutex /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__malloc_free_list /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-freer.o) +__malloc_lock /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-freer.o) +__malloc_sbrk_start /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) +__malloc_unlock /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-freer.o) +__on_exit_args /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +__preinit_array_end /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) +__preinit_array_start /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) +__register_exitproc /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-atexit.o) +__register_frame_info /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crtbegin.o +__retarget_lock_acquire /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__retarget_lock_acquire_recursive /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +__retarget_lock_close /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__retarget_lock_close_recursive /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__retarget_lock_init /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__retarget_lock_init_recursive /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__retarget_lock_release /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +__retarget_lock_release_recursive /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +__retarget_lock_try_acquire /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__retarget_lock_try_acquire_recursive /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-lock.o) +__sf_fake_stderr /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) +__sf_fake_stdin /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) +__sf_fake_stdout /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) +__stack /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__udivmoddi4 /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) +_ebss build/startup_stm32h750xx.o +_edata build/startup_stm32h750xx.o +_estack build/startup_stm32h750xx.o +_exit /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a(_exit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o) +_fini /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crti.o + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-fini.o) +_free_r /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-freer.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) +_global_atexit /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) +_global_impure_ptr /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o) +_impure_ptr /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-impure.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) +_init /usr/lib/gcc/arm-none-eabi/10.2.0/thumb/v7e-m+dp/hard/crti.o + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-init.o) +_mainCRTStartup /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +_malloc_r /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) +_putchar build/port_printf.o + build/printf.o +_reclaim_reent /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) +_sbrk /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a(sbrk.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-sbrkr.o) +_sbrk_r /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-sbrkr.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-nano-mallocr.o) +_sbss build/startup_stm32h750xx.o +_sdata build/startup_stm32h750xx.o +_sidata build/startup_stm32h750xx.o +_stack_init /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +_start /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +atexit /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +cleanup_glue /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) +end /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a(sbrk.o) +errno /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-reent.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-sbrkr.o) +exit /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-exit.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +fctprintf build/printf.o +free /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) + build/usbd_dfu.o +g_DFU build/main.o + build/usb_device.o +g_pfnVectors build/startup_stm32h750xx.o +hUsbDeviceFS build/usb_device.o +hardware_init_hook /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +hpcd_USB_OTG_FS build/usbd_conf.o + build/stm32h7xx_it.o +hqspi build/main.o + build/usbd_dfu_if.o + build/stm32h7xx_it.o +huart1 build/main.o + build/port_printf.o + build/stm32h7xx_it.o +main build/main.o + build/startup_stm32h750xx.o + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +malloc /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-malloc.o) + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-__atexit.o) + build/usbd_dfu.o +memset /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(lib_a-memset.o) + build/main.o + /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +pFlash build/stm32h7xx_hal_flash.o + build/stm32h7xx_hal_flash_ex.o +printf_ build/printf.o + build/usbd_dfu_if.o + build/main.o +snprintf_ build/printf.o +software_init_hook /usr/lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +sprintf_ build/printf.o +uwTick build/stm32h7xx_hal.o +uwTickFreq build/stm32h7xx_hal.o +uwTickPrio build/stm32h7xx_hal.o + build/stm32h7xx_hal_rcc.o +vprintf_ build/printf.o +vsnprintf_ build/printf.o +w25_flash build/usbd_dfu_if.o diff --git a/build/bootloader_control.d b/build/bootloader_control.d new file mode 100644 index 0000000..5667961 --- /dev/null +++ b/build/bootloader_control.d @@ -0,0 +1,67 @@ +build/bootloader_control.o: Core/Src/bootloader_control.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/bootloader_control.lst b/build/bootloader_control.lst new file mode 100644 index 0000000..3ed8ffb --- /dev/null +++ b/build/bootloader_control.lst @@ -0,0 +1,354 @@ +ARM GAS /tmp/cc2CqpQ9.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "bootloader_control.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.BL_CheckValidImage,"ax",%progbits + 17 .align 1 + 18 .global BL_CheckValidImage + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 BL_CheckValidImage: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Core/Src/bootloader_control.c" + 1:Core/Src/bootloader_control.c **** // + 2:Core/Src/bootloader_control.c **** // Created by imi415 on 2019/12/17. + 3:Core/Src/bootloader_control.c **** // + 4:Core/Src/bootloader_control.c **** + 5:Core/Src/bootloader_control.c **** #include + 6:Core/Src/bootloader_control.c **** + 7:Core/Src/bootloader_control.c **** HAL_StatusTypeDef BL_CheckValidImage(uint32_t base_address) { + 29 .loc 1 7 61 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 8:Core/Src/bootloader_control.c **** uint32_t qspi_sp = *(uint32_t *)base_address; + 34 .loc 1 8 5 view .LVU1 + 35 .loc 1 8 14 is_stmt 0 view .LVU2 + 36 0000 0368 ldr r3, [r0] + 37 .LVL1: + 9:Core/Src/bootloader_control.c **** if(qspi_sp < 0x40000000) { + 38 .loc 1 9 5 is_stmt 1 view .LVU3 + 39 .loc 1 9 7 is_stmt 0 view .LVU4 + 40 0002 B3F1804F cmp r3, #1073741824 + 41 0006 01D2 bcs .L3 + 10:Core/Src/bootloader_control.c **** return HAL_OK; + 42 .loc 1 10 16 view .LVU5 + 43 0008 0020 movs r0, #0 + 44 .LVL2: + 45 .loc 1 10 16 view .LVU6 + 46 000a 7047 bx lr + 47 .LVL3: + 48 .L3: + ARM GAS /tmp/cc2CqpQ9.s page 2 + + + 11:Core/Src/bootloader_control.c **** } + 12:Core/Src/bootloader_control.c **** else return HAL_ERROR; + 49 .loc 1 12 17 view .LVU7 + 50 000c 0120 movs r0, #1 + 51 .LVL4: + 13:Core/Src/bootloader_control.c **** } + 52 .loc 1 13 1 view .LVU8 + 53 000e 7047 bx lr + 54 .cfi_endproc + 55 .LFE141: + 57 .section .text.BL_GetEntryPoint,"ax",%progbits + 58 .align 1 + 59 .global BL_GetEntryPoint + 60 .syntax unified + 61 .thumb + 62 .thumb_func + 63 .fpu fpv5-d16 + 65 BL_GetEntryPoint: + 66 .LVL5: + 67 .LFB142: + 14:Core/Src/bootloader_control.c **** + 15:Core/Src/bootloader_control.c **** uint32_t BL_GetEntryPoint(uint32_t base_address) { + 68 .loc 1 15 50 is_stmt 1 view -0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 0, uses_anonymous_args = 0 + 72 @ link register save eliminated. + 16:Core/Src/bootloader_control.c **** uint32_t target_reset_vector = *(uint32_t *)(base_address + 0x04); + 73 .loc 1 16 5 view .LVU10 + 74 .loc 1 16 14 is_stmt 0 view .LVU11 + 75 0000 4068 ldr r0, [r0, #4] + 76 .LVL6: + 17:Core/Src/bootloader_control.c **** if(target_reset_vector > 0x90000000 && target_reset_vector < 0xA0000000) { + 77 .loc 1 17 5 is_stmt 1 view .LVU12 + 78 .loc 1 17 41 is_stmt 0 view .LVU13 + 79 0002 6FF01043 mvn r3, #-1879048192 + 80 0006 0344 add r3, r3, r0 + 81 .loc 1 17 7 view .LVU14 + 82 0008 6FF07042 mvn r2, #-268435456 + 83 000c 9342 cmp r3, r2 + 84 000e 00D3 bcc .L4 + 18:Core/Src/bootloader_control.c **** return target_reset_vector; + 19:Core/Src/bootloader_control.c **** } + 20:Core/Src/bootloader_control.c **** else return 0x00000000; + 85 .loc 1 20 17 view .LVU15 + 86 0010 0020 movs r0, #0 + 87 .LVL7: + 88 .L4: + 21:Core/Src/bootloader_control.c **** } + 89 .loc 1 21 1 view .LVU16 + 90 0012 7047 bx lr + 91 .cfi_endproc + 92 .LFE142: + 94 .section .text.BL_JumpToXIPStart,"ax",%progbits + 95 .align 1 + 96 .global BL_JumpToXIPStart + 97 .syntax unified + ARM GAS /tmp/cc2CqpQ9.s page 3 + + + 98 .thumb + 99 .thumb_func + 100 .fpu fpv5-d16 + 102 BL_JumpToXIPStart: + 103 .LVL8: + 104 .LFB143: + 22:Core/Src/bootloader_control.c **** + 23:Core/Src/bootloader_control.c **** void BL_JumpToXIPStart(uint32_t entry_point, uint32_t vector_base) { + 105 .loc 1 23 68 is_stmt 1 view -0 + 106 .cfi_startproc + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 .loc 1 23 68 is_stmt 0 view .LVU18 + 110 0000 08B5 push {r3, lr} + 111 .LCFI0: + 112 .cfi_def_cfa_offset 8 + 113 .cfi_offset 3, -8 + 114 .cfi_offset 14, -4 + 24:Core/Src/bootloader_control.c **** __disable_irq(); + 115 .loc 1 24 5 is_stmt 1 view .LVU19 + 116 .LBB4: + 117 .LBI4: + 118 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + ARM GAS /tmp/cc2CqpQ9.s page 4 + + + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + ARM GAS /tmp/cc2CqpQ9.s page 5 + + + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 119 .loc 2 140 27 view .LVU20 + 120 .LBB5: + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 121 .loc 2 142 3 view .LVU21 + 122 .syntax unified + 123 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 124 0002 72B6 cpsid i + ARM GAS /tmp/cc2CqpQ9.s page 6 + + + 125 @ 0 "" 2 + 126 .thumb + 127 .syntax unified + 128 .LBE5: + 129 .LBE4: + 25:Core/Src/bootloader_control.c **** SysTick->CTRL = 0; + 130 .loc 1 25 5 view .LVU22 + 131 .loc 1 25 19 is_stmt 0 view .LVU23 + 132 0004 4FF0E023 mov r3, #-536813568 + 133 0008 0022 movs r2, #0 + 134 000a 1A61 str r2, [r3, #16] + 26:Core/Src/bootloader_control.c **** SysTick->LOAD = 0; + 135 .loc 1 26 5 is_stmt 1 view .LVU24 + 136 .loc 1 26 19 is_stmt 0 view .LVU25 + 137 000c 5A61 str r2, [r3, #20] + 27:Core/Src/bootloader_control.c **** SysTick->VAL = 0; + 138 .loc 1 27 5 is_stmt 1 view .LVU26 + 139 .loc 1 27 19 is_stmt 0 view .LVU27 + 140 000e 9A61 str r2, [r3, #24] + 28:Core/Src/bootloader_control.c **** void (*entry)(void) = (void *)entry_point; + 141 .loc 1 28 5 is_stmt 1 view .LVU28 + 142 .LVL9: + 29:Core/Src/bootloader_control.c **** //__set_MSP(*(uint32_t *)vector_base); + 30:Core/Src/bootloader_control.c **** entry(); + 143 .loc 1 30 5 view .LVU29 + 144 0010 8047 blx r0 + 145 .LVL10: + 31:Core/Src/bootloader_control.c **** }... + 146 .loc 1 31 1 is_stmt 0 view .LVU30 + 147 0012 08BD pop {r3, pc} + 148 .cfi_endproc + 149 .LFE143: + 151 .text + 152 .Letext0: + 153 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 154 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 155 .file 5 "Drivers/CMSIS/Include/core_cm7.h" + 156 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + ARM GAS /tmp/cc2CqpQ9.s page 7 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 bootloader_control.c + /tmp/cc2CqpQ9.s:17 .text.BL_CheckValidImage:0000000000000000 $t + /tmp/cc2CqpQ9.s:25 .text.BL_CheckValidImage:0000000000000000 BL_CheckValidImage + /tmp/cc2CqpQ9.s:58 .text.BL_GetEntryPoint:0000000000000000 $t + /tmp/cc2CqpQ9.s:65 .text.BL_GetEntryPoint:0000000000000000 BL_GetEntryPoint + /tmp/cc2CqpQ9.s:95 .text.BL_JumpToXIPStart:0000000000000000 $t + /tmp/cc2CqpQ9.s:102 .text.BL_JumpToXIPStart:0000000000000000 BL_JumpToXIPStart + +NO UNDEFINED SYMBOLS diff --git a/build/bootloader_control.o b/build/bootloader_control.o new file mode 100644 index 0000000..1fcfbec Binary files /dev/null and b/build/bootloader_control.o differ diff --git a/build/main.d b/build/main.d new file mode 100644 index 0000000..b9f5350 --- /dev/null +++ b/build/main.d @@ -0,0 +1,81 @@ +build/main.o: Core/Src/main.c Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h \ + USB_DEVICE/App/usb_device.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/printf.h \ + Core/Inc/bootloader_control.h Core/Inc/w25_qspi.h +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +USB_DEVICE/App/usb_device.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/printf.h: +Core/Inc/bootloader_control.h: +Core/Inc/w25_qspi.h: diff --git a/build/main.lst b/build/main.lst new file mode 100644 index 0000000..e918763 --- /dev/null +++ b/build/main.lst @@ -0,0 +1,1614 @@ +ARM GAS /tmp/ccOSKXvF.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "main.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.MX_GPIO_Init,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 MX_GPIO_Init: + 25 .LFB149: + 26 .file 1 "Core/Src/main.c" + 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/main.c **** /** + 3:Core/Src/main.c **** ****************************************************************************** + 4:Core/Src/main.c **** * @file : main.c + 5:Core/Src/main.c **** * @brief : Main program body + 6:Core/Src/main.c **** ****************************************************************************** + 7:Core/Src/main.c **** * @attention + 8:Core/Src/main.c **** * + 9:Core/Src/main.c **** *

© Copyright (c) 2019 STMicroelectronics. + 10:Core/Src/main.c **** * All rights reserved.

+ 11:Core/Src/main.c **** * + 12:Core/Src/main.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Core/Src/main.c **** * the "License"; You may not use this file except in compliance with the + 14:Core/Src/main.c **** * License. You may obtain a copy of the License at: + 15:Core/Src/main.c **** * opensource.org/licenses/BSD-3-Clause + 16:Core/Src/main.c **** * + 17:Core/Src/main.c **** ****************************************************************************** + 18:Core/Src/main.c **** */ + 19:Core/Src/main.c **** /* USER CODE END Header */ + 20:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 21:Core/Src/main.c **** #include "main.h" + 22:Core/Src/main.c **** #include "usb_device.h" + 23:Core/Src/main.c **** + 24:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ + 25:Core/Src/main.c **** /* USER CODE BEGIN Includes */ + 26:Core/Src/main.c **** + 27:Core/Src/main.c **** #include "printf.h" + 28:Core/Src/main.c **** #include "bootloader_control.h" + 29:Core/Src/main.c **** #include "w25_qspi.h" + 30:Core/Src/main.c **** + 31:Core/Src/main.c **** /* USER CODE END Includes */ + 32:Core/Src/main.c **** + ARM GAS /tmp/ccOSKXvF.s page 2 + + + 33:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + 34:Core/Src/main.c **** /* USER CODE BEGIN PTD */ + 35:Core/Src/main.c **** + 36:Core/Src/main.c **** /* USER CODE END PTD */ + 37:Core/Src/main.c **** + 38:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ + 39:Core/Src/main.c **** /* USER CODE BEGIN PD */ + 40:Core/Src/main.c **** /* USER CODE END PD */ + 41:Core/Src/main.c **** + 42:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 43:Core/Src/main.c **** /* USER CODE BEGIN PM */ + 44:Core/Src/main.c **** + 45:Core/Src/main.c **** /* USER CODE END PM */ + 46:Core/Src/main.c **** + 47:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 48:Core/Src/main.c **** + 49:Core/Src/main.c **** QSPI_HandleTypeDef hqspi; + 50:Core/Src/main.c **** + 51:Core/Src/main.c **** UART_HandleTypeDef huart1; + 52:Core/Src/main.c **** + 53:Core/Src/main.c **** /* USER CODE BEGIN PV */ + 54:Core/Src/main.c **** + 55:Core/Src/main.c **** uint8_t g_DFU = 0; + 56:Core/Src/main.c **** + 57:Core/Src/main.c **** /* USER CODE END PV */ + 58:Core/Src/main.c **** + 59:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 60:Core/Src/main.c **** void SystemClock_Config(void); + 61:Core/Src/main.c **** static void MX_GPIO_Init(void); + 62:Core/Src/main.c **** static void MX_QUADSPI_Init(void); + 63:Core/Src/main.c **** static void MX_USART1_UART_Init(void); + 64:Core/Src/main.c **** /* USER CODE BEGIN PFP */ + 65:Core/Src/main.c **** + 66:Core/Src/main.c **** /* USER CODE END PFP */ + 67:Core/Src/main.c **** + 68:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ + 69:Core/Src/main.c **** /* USER CODE BEGIN 0 */ + 70:Core/Src/main.c **** + 71:Core/Src/main.c **** /* USER CODE END 0 */ + 72:Core/Src/main.c **** + 73:Core/Src/main.c **** /** + 74:Core/Src/main.c **** * @brief The application entry point. + 75:Core/Src/main.c **** * @retval int + 76:Core/Src/main.c **** */ + 77:Core/Src/main.c **** int main(void) + 78:Core/Src/main.c **** { + 79:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 80:Core/Src/main.c **** + 81:Core/Src/main.c **** /* USER CODE END 1 */ + 82:Core/Src/main.c **** + 83:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 84:Core/Src/main.c **** + 85:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 86:Core/Src/main.c **** HAL_Init(); + 87:Core/Src/main.c **** + 88:Core/Src/main.c **** /* USER CODE BEGIN Init */ + 89:Core/Src/main.c **** + ARM GAS /tmp/ccOSKXvF.s page 3 + + + 90:Core/Src/main.c **** /* USER CODE END Init */ + 91:Core/Src/main.c **** + 92:Core/Src/main.c **** /* Configure the system clock */ + 93:Core/Src/main.c **** SystemClock_Config(); + 94:Core/Src/main.c **** + 95:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ + 96:Core/Src/main.c **** + 97:Core/Src/main.c **** /* USER CODE END SysInit */ + 98:Core/Src/main.c **** + 99:Core/Src/main.c **** /* Initialize all configured peripherals */ + 100:Core/Src/main.c **** MX_GPIO_Init(); + 101:Core/Src/main.c **** MX_QUADSPI_Init(); + 102:Core/Src/main.c **** MX_USART1_UART_Init(); + 103:Core/Src/main.c **** MX_USB_DEVICE_Init(); + 104:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 105:Core/Src/main.c **** + 106:Core/Src/main.c **** if(!g_DFU) { + 107:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; + 108:Core/Src/main.c **** QSPI_MemoryMappedTypeDef sMemMappedCfg; + 109:Core/Src/main.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; + 110:Core/Src/main.c **** sCommand.AddressMode = QSPI_ADDRESS_4_LINES; + 111:Core/Src/main.c **** sCommand.AddressSize = QSPI_ADDRESS_24_BITS; + 112:Core/Src/main.c **** sCommand.DataMode = QSPI_DATA_4_LINES; + 113:Core/Src/main.c **** sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; + 114:Core/Src/main.c **** sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; + 115:Core/Src/main.c **** sCommand.AlternateBytes = 0xFF; + 116:Core/Src/main.c **** sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; + 117:Core/Src/main.c **** sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + 118:Core/Src/main.c **** sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + 119:Core/Src/main.c **** sCommand.Instruction = 0xEB; + 120:Core/Src/main.c **** sCommand.DummyCycles = 4; + 121:Core/Src/main.c **** sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; + 122:Core/Src/main.c **** sMemMappedCfg.TimeOutPeriod = 0; + 123:Core/Src/main.c **** + 124:Core/Src/main.c **** w25_qspi_t w25_flash; + 125:Core/Src/main.c **** w25_flash.interface = &hqspi; + 126:Core/Src/main.c **** w25_flash.mode = W25_MODE_QUAD; + 127:Core/Src/main.c **** w25_flash.address_size = W25_ADDRESS_24BITS; + 128:Core/Src/main.c **** + 129:Core/Src/main.c **** #if(USE_QPI_MODE == 1) + 130:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 0); // Special use case!! + 131:Core/Src/main.c **** #endif // USE_QPI_MODE + 132:Core/Src/main.c **** + 133:Core/Src/main.c **** W25_QSPI_Init(&w25_flash); + 134:Core/Src/main.c **** printf("Main: Mfg: 0x%x\r\n", w25_flash.manufacturer); + 135:Core/Src/main.c **** + 136:Core/Src/main.c **** W25_QSPI_QuadEnable(&w25_flash, 0); + 137:Core/Src/main.c **** + 138:Core/Src/main.c **** #if(USE_QPI_MODE == 1) + 139:Core/Src/main.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + 140:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 1); + 141:Core/Src/main.c **** #if(QPI_HIGH_SPEED == 1) // For 80MHz HIGHHHHHH speed QPI mode(33-80MHz), additional 4 dummy cycles + 142:Core/Src/main.c **** sCommand.DummyCycles = 4; // In QPI mode, M7-0 are used as dummy clocks. + 143:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_6, W25_QPI_WRAP_LENGTH_8); + 144:Core/Src/main.c **** #else + 145:Core/Src/main.c **** sCommand.DummyCycles = 0; // In QPI mode, M7-0 are used as dummy clocks. + 146:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); + ARM GAS /tmp/ccOSKXvF.s page 4 + + + 147:Core/Src/main.c **** #endif // QPI_HIGH_SPEED + 148:Core/Src/main.c **** #endif // USE_QPI_MODE + 149:Core/Src/main.c **** + 150:Core/Src/main.c **** if(HAL_QSPI_MemoryMapped(&hqspi, &sCommand, &sMemMappedCfg) == HAL_OK) { + 151:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); + 152:Core/Src/main.c **** if(BL_CheckValidImage(0x90000000) == HAL_OK) { + 153:Core/Src/main.c **** printf("Valid SP found!\r\n"); + 154:Core/Src/main.c **** uint32_t entry = BL_GetEntryPoint(0x90000000); + 155:Core/Src/main.c **** printf("Entry: 0x%08lx\r\n", entry); + 156:Core/Src/main.c **** BL_JumpToXIPStart(entry, 0x90000000); + 157:Core/Src/main.c **** } + 158:Core/Src/main.c **** else printf("No valid image found!\r\n"); + 159:Core/Src/main.c **** } + 160:Core/Src/main.c **** } + 161:Core/Src/main.c **** + 162:Core/Src/main.c **** /* USER CODE END 2 */ + 163:Core/Src/main.c **** + 164:Core/Src/main.c **** /* Infinite loop */ + 165:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ + 166:Core/Src/main.c **** while (1) + 167:Core/Src/main.c **** { + 168:Core/Src/main.c **** /* USER CODE END WHILE */ + 169:Core/Src/main.c **** + 170:Core/Src/main.c **** /* USER CODE BEGIN 3 */ + 171:Core/Src/main.c **** } + 172:Core/Src/main.c **** /* USER CODE END 3 */ + 173:Core/Src/main.c **** } + 174:Core/Src/main.c **** + 175:Core/Src/main.c **** /** + 176:Core/Src/main.c **** * @brief System Clock Configuration + 177:Core/Src/main.c **** * @retval None + 178:Core/Src/main.c **** */ + 179:Core/Src/main.c **** void SystemClock_Config(void) + 180:Core/Src/main.c **** { + 181:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 182:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 183:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 184:Core/Src/main.c **** + 185:Core/Src/main.c **** /** Supply configuration update enable + 186:Core/Src/main.c **** */ + 187:Core/Src/main.c **** HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + 188:Core/Src/main.c **** /** Configure the main internal regulator output voltage + 189:Core/Src/main.c **** */ + 190:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 191:Core/Src/main.c **** + 192:Core/Src/main.c **** while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + 193:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 194:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. + 195:Core/Src/main.c **** */ + 196:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI + 197:Core/Src/main.c **** |RCC_OSCILLATORTYPE_HSE; + 198:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 199:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + 200:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 201:Core/Src/main.c **** RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + 202:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 203:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + ARM GAS /tmp/ccOSKXvF.s page 5 + + + 204:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2; + 205:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 40; + 206:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; + 207:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 1; + 208:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 1; + 209:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + 210:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; + 211:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; + 212:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 213:Core/Src/main.c **** { + 214:Core/Src/main.c **** Error_Handler(); + 215:Core/Src/main.c **** } + 216:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks + 217:Core/Src/main.c **** */ + 218:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 219:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + 220:Core/Src/main.c **** |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + 221:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 222:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + 223:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + 224:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + 225:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + 226:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + 227:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + 228:Core/Src/main.c **** + 229:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 230:Core/Src/main.c **** { + 231:Core/Src/main.c **** Error_Handler(); + 232:Core/Src/main.c **** } + 233:Core/Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USB + 234:Core/Src/main.c **** |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; + 235:Core/Src/main.c **** PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_CLKP; + 236:Core/Src/main.c **** PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; + 237:Core/Src/main.c **** PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + 238:Core/Src/main.c **** PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + 239:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 240:Core/Src/main.c **** { + 241:Core/Src/main.c **** Error_Handler(); + 242:Core/Src/main.c **** } + 243:Core/Src/main.c **** /** Enable USB Voltage detector + 244:Core/Src/main.c **** */ + 245:Core/Src/main.c **** HAL_PWREx_EnableUSBVoltageDetector(); + 246:Core/Src/main.c **** } + 247:Core/Src/main.c **** + 248:Core/Src/main.c **** /** + 249:Core/Src/main.c **** * @brief QUADSPI Initialization Function + 250:Core/Src/main.c **** * @param None + 251:Core/Src/main.c **** * @retval None + 252:Core/Src/main.c **** */ + 253:Core/Src/main.c **** static void MX_QUADSPI_Init(void) + 254:Core/Src/main.c **** { + 255:Core/Src/main.c **** + 256:Core/Src/main.c **** /* USER CODE BEGIN QUADSPI_Init 0 */ + 257:Core/Src/main.c **** + 258:Core/Src/main.c **** /* USER CODE END QUADSPI_Init 0 */ + 259:Core/Src/main.c **** + 260:Core/Src/main.c **** /* USER CODE BEGIN QUADSPI_Init 1 */ + ARM GAS /tmp/ccOSKXvF.s page 6 + + + 261:Core/Src/main.c **** + 262:Core/Src/main.c **** /* USER CODE END QUADSPI_Init 1 */ + 263:Core/Src/main.c **** /* QUADSPI parameter configuration*/ + 264:Core/Src/main.c **** hqspi.Instance = QUADSPI; + 265:Core/Src/main.c **** hqspi.Init.ClockPrescaler = 2; + 266:Core/Src/main.c **** hqspi.Init.FifoThreshold = 4; + 267:Core/Src/main.c **** hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; + 268:Core/Src/main.c **** hqspi.Init.FlashSize = 24; + 269:Core/Src/main.c **** hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; + 270:Core/Src/main.c **** hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; + 271:Core/Src/main.c **** hqspi.Init.FlashID = QSPI_FLASH_ID_1; + 272:Core/Src/main.c **** hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + 273:Core/Src/main.c **** if (HAL_QSPI_Init(&hqspi) != HAL_OK) + 274:Core/Src/main.c **** { + 275:Core/Src/main.c **** Error_Handler(); + 276:Core/Src/main.c **** } + 277:Core/Src/main.c **** /* USER CODE BEGIN QUADSPI_Init 2 */ + 278:Core/Src/main.c **** + 279:Core/Src/main.c **** /* USER CODE END QUADSPI_Init 2 */ + 280:Core/Src/main.c **** + 281:Core/Src/main.c **** } + 282:Core/Src/main.c **** + 283:Core/Src/main.c **** /** + 284:Core/Src/main.c **** * @brief USART1 Initialization Function + 285:Core/Src/main.c **** * @param None + 286:Core/Src/main.c **** * @retval None + 287:Core/Src/main.c **** */ + 288:Core/Src/main.c **** static void MX_USART1_UART_Init(void) + 289:Core/Src/main.c **** { + 290:Core/Src/main.c **** + 291:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ + 292:Core/Src/main.c **** + 293:Core/Src/main.c **** /* USER CODE END USART1_Init 0 */ + 294:Core/Src/main.c **** + 295:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ + 296:Core/Src/main.c **** + 297:Core/Src/main.c **** /* USER CODE END USART1_Init 1 */ + 298:Core/Src/main.c **** huart1.Instance = USART1; + 299:Core/Src/main.c **** huart1.Init.BaudRate = 921600; + 300:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; + 301:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; + 302:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; + 303:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; + 304:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 305:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 306:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 307:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 308:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 309:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) + 310:Core/Src/main.c **** { + 311:Core/Src/main.c **** Error_Handler(); + 312:Core/Src/main.c **** } + 313:Core/Src/main.c **** if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + 314:Core/Src/main.c **** { + 315:Core/Src/main.c **** Error_Handler(); + 316:Core/Src/main.c **** } + 317:Core/Src/main.c **** if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + ARM GAS /tmp/ccOSKXvF.s page 7 + + + 318:Core/Src/main.c **** { + 319:Core/Src/main.c **** Error_Handler(); + 320:Core/Src/main.c **** } + 321:Core/Src/main.c **** if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + 322:Core/Src/main.c **** { + 323:Core/Src/main.c **** Error_Handler(); + 324:Core/Src/main.c **** } + 325:Core/Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ + 326:Core/Src/main.c **** + 327:Core/Src/main.c **** /* USER CODE END USART1_Init 2 */ + 328:Core/Src/main.c **** + 329:Core/Src/main.c **** } + 330:Core/Src/main.c **** + 331:Core/Src/main.c **** /** + 332:Core/Src/main.c **** * @brief GPIO Initialization Function + 333:Core/Src/main.c **** * @param None + 334:Core/Src/main.c **** * @retval None + 335:Core/Src/main.c **** */ + 336:Core/Src/main.c **** static void MX_GPIO_Init(void) + 337:Core/Src/main.c **** { + 27 .loc 1 337 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 48 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 0002 8CB0 sub sp, sp, #48 + 39 .LCFI1: + 40 .cfi_def_cfa_offset 64 + 338:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 41 .loc 1 338 3 view .LVU1 + 42 .loc 1 338 20 is_stmt 0 view .LVU2 + 43 0004 0024 movs r4, #0 + 44 0006 0794 str r4, [sp, #28] + 45 0008 0894 str r4, [sp, #32] + 46 000a 0994 str r4, [sp, #36] + 47 000c 0A94 str r4, [sp, #40] + 48 000e 0B94 str r4, [sp, #44] + 339:Core/Src/main.c **** + 340:Core/Src/main.c **** /* GPIO Ports Clock Enable */ + 341:Core/Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); + 49 .loc 1 341 3 is_stmt 1 view .LVU3 + 50 .LBB2: + 51 .loc 1 341 3 view .LVU4 + 52 .loc 1 341 3 view .LVU5 + 53 0010 314B ldr r3, .L3 + 54 0012 D3F8E020 ldr r2, [r3, #224] + 55 0016 42F01002 orr r2, r2, #16 + 56 001a C3F8E020 str r2, [r3, #224] + 57 .loc 1 341 3 view .LVU6 + 58 001e D3F8E020 ldr r2, [r3, #224] + 59 0022 02F01002 and r2, r2, #16 + ARM GAS /tmp/ccOSKXvF.s page 8 + + + 60 0026 0192 str r2, [sp, #4] + 61 .loc 1 341 3 view .LVU7 + 62 0028 019A ldr r2, [sp, #4] + 63 .LBE2: + 64 .loc 1 341 3 view .LVU8 + 342:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 65 .loc 1 342 3 view .LVU9 + 66 .LBB3: + 67 .loc 1 342 3 view .LVU10 + 68 .loc 1 342 3 view .LVU11 + 69 002a D3F8E020 ldr r2, [r3, #224] + 70 002e 42F00402 orr r2, r2, #4 + 71 0032 C3F8E020 str r2, [r3, #224] + 72 .loc 1 342 3 view .LVU12 + 73 0036 D3F8E020 ldr r2, [r3, #224] + 74 003a 02F00402 and r2, r2, #4 + 75 003e 0292 str r2, [sp, #8] + 76 .loc 1 342 3 view .LVU13 + 77 0040 029A ldr r2, [sp, #8] + 78 .LBE3: + 79 .loc 1 342 3 view .LVU14 + 343:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); + 80 .loc 1 343 3 view .LVU15 + 81 .LBB4: + 82 .loc 1 343 3 view .LVU16 + 83 .loc 1 343 3 view .LVU17 + 84 0042 D3F8E020 ldr r2, [r3, #224] + 85 0046 42F08002 orr r2, r2, #128 + 86 004a C3F8E020 str r2, [r3, #224] + 87 .loc 1 343 3 view .LVU18 + 88 004e D3F8E020 ldr r2, [r3, #224] + 89 0052 02F08002 and r2, r2, #128 + 90 0056 0392 str r2, [sp, #12] + 91 .loc 1 343 3 view .LVU19 + 92 0058 039A ldr r2, [sp, #12] + 93 .LBE4: + 94 .loc 1 343 3 view .LVU20 + 344:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 95 .loc 1 344 3 view .LVU21 + 96 .LBB5: + 97 .loc 1 344 3 view .LVU22 + 98 .loc 1 344 3 view .LVU23 + 99 005a D3F8E020 ldr r2, [r3, #224] + 100 005e 42F00102 orr r2, r2, #1 + 101 0062 C3F8E020 str r2, [r3, #224] + 102 .loc 1 344 3 view .LVU24 + 103 0066 D3F8E020 ldr r2, [r3, #224] + 104 006a 02F00102 and r2, r2, #1 + 105 006e 0492 str r2, [sp, #16] + 106 .loc 1 344 3 view .LVU25 + 107 0070 049A ldr r2, [sp, #16] + 108 .LBE5: + 109 .loc 1 344 3 view .LVU26 + 345:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 110 .loc 1 345 3 view .LVU27 + 111 .LBB6: + 112 .loc 1 345 3 view .LVU28 + ARM GAS /tmp/ccOSKXvF.s page 9 + + + 113 .loc 1 345 3 view .LVU29 + 114 0072 D3F8E020 ldr r2, [r3, #224] + 115 0076 42F00202 orr r2, r2, #2 + 116 007a C3F8E020 str r2, [r3, #224] + 117 .loc 1 345 3 view .LVU30 + 118 007e D3F8E020 ldr r2, [r3, #224] + 119 0082 02F00202 and r2, r2, #2 + 120 0086 0592 str r2, [sp, #20] + 121 .loc 1 345 3 view .LVU31 + 122 0088 059A ldr r2, [sp, #20] + 123 .LBE6: + 124 .loc 1 345 3 view .LVU32 + 346:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 125 .loc 1 346 3 view .LVU33 + 126 .LBB7: + 127 .loc 1 346 3 view .LVU34 + 128 .loc 1 346 3 view .LVU35 + 129 008a D3F8E020 ldr r2, [r3, #224] + 130 008e 42F00802 orr r2, r2, #8 + 131 0092 C3F8E020 str r2, [r3, #224] + 132 .loc 1 346 3 view .LVU36 + 133 0096 D3F8E030 ldr r3, [r3, #224] + 134 009a 03F00803 and r3, r3, #8 + 135 009e 0693 str r3, [sp, #24] + 136 .loc 1 346 3 view .LVU37 + 137 00a0 069B ldr r3, [sp, #24] + 138 .LBE7: + 139 .loc 1 346 3 view .LVU38 + 347:Core/Src/main.c **** + 348:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 349:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); + 140 .loc 1 349 3 view .LVU39 + 141 00a2 0E4D ldr r5, .L3+4 + 142 00a4 2246 mov r2, r4 + 143 00a6 0221 movs r1, #2 + 144 00a8 2846 mov r0, r5 + 145 00aa FFF7FEFF bl HAL_GPIO_WritePin + 146 .LVL0: + 350:Core/Src/main.c **** + 351:Core/Src/main.c **** /*Configure GPIO pin : PE3 */ + 352:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_3; + 147 .loc 1 352 3 view .LVU40 + 148 .loc 1 352 23 is_stmt 0 view .LVU41 + 149 00ae 0823 movs r3, #8 + 150 00b0 0793 str r3, [sp, #28] + 353:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 151 .loc 1 353 3 is_stmt 1 view .LVU42 + 152 .loc 1 353 24 is_stmt 0 view .LVU43 + 153 00b2 0894 str r4, [sp, #32] + 354:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; + 154 .loc 1 354 3 is_stmt 1 view .LVU44 + 155 .loc 1 354 24 is_stmt 0 view .LVU45 + 156 00b4 0126 movs r6, #1 + 157 00b6 0996 str r6, [sp, #36] + 355:Core/Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 158 .loc 1 355 3 is_stmt 1 view .LVU46 + 159 00b8 07A9 add r1, sp, #28 + ARM GAS /tmp/ccOSKXvF.s page 10 + + + 160 00ba 0948 ldr r0, .L3+8 + 161 00bc FFF7FEFF bl HAL_GPIO_Init + 162 .LVL1: + 356:Core/Src/main.c **** + 357:Core/Src/main.c **** /*Configure GPIO pin : PA1 */ + 358:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_1; + 163 .loc 1 358 3 view .LVU47 + 164 .loc 1 358 23 is_stmt 0 view .LVU48 + 165 00c0 0223 movs r3, #2 + 166 00c2 0793 str r3, [sp, #28] + 359:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 167 .loc 1 359 3 is_stmt 1 view .LVU49 + 168 .loc 1 359 24 is_stmt 0 view .LVU50 + 169 00c4 0896 str r6, [sp, #32] + 360:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 170 .loc 1 360 3 is_stmt 1 view .LVU51 + 171 .loc 1 360 24 is_stmt 0 view .LVU52 + 172 00c6 0994 str r4, [sp, #36] + 361:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 173 .loc 1 361 3 is_stmt 1 view .LVU53 + 174 .loc 1 361 25 is_stmt 0 view .LVU54 + 175 00c8 0A94 str r4, [sp, #40] + 362:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 176 .loc 1 362 3 is_stmt 1 view .LVU55 + 177 00ca 07A9 add r1, sp, #28 + 178 00cc 2846 mov r0, r5 + 179 00ce FFF7FEFF bl HAL_GPIO_Init + 180 .LVL2: + 363:Core/Src/main.c **** + 364:Core/Src/main.c **** } + 181 .loc 1 364 1 is_stmt 0 view .LVU56 + 182 00d2 0CB0 add sp, sp, #48 + 183 .LCFI2: + 184 .cfi_def_cfa_offset 16 + 185 @ sp needed + 186 00d4 70BD pop {r4, r5, r6, pc} + 187 .L4: + 188 00d6 00BF .align 2 + 189 .L3: + 190 00d8 00440258 .word 1476543488 + 191 00dc 00000258 .word 1476526080 + 192 00e0 00100258 .word 1476530176 + 193 .cfi_endproc + 194 .LFE149: + 196 .section .text.MX_QUADSPI_Init,"ax",%progbits + 197 .align 1 + 198 .syntax unified + 199 .thumb + 200 .thumb_func + 201 .fpu fpv5-d16 + 203 MX_QUADSPI_Init: + 204 .LFB147: + 254:Core/Src/main.c **** + 205 .loc 1 254 1 is_stmt 1 view -0 + 206 .cfi_startproc + 207 @ args = 0, pretend = 0, frame = 0 + 208 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccOSKXvF.s page 11 + + + 209 0000 08B5 push {r3, lr} + 210 .LCFI3: + 211 .cfi_def_cfa_offset 8 + 212 .cfi_offset 3, -8 + 213 .cfi_offset 14, -4 + 264:Core/Src/main.c **** hqspi.Init.ClockPrescaler = 2; + 214 .loc 1 264 3 view .LVU58 + 264:Core/Src/main.c **** hqspi.Init.ClockPrescaler = 2; + 215 .loc 1 264 18 is_stmt 0 view .LVU59 + 216 0002 0A48 ldr r0, .L7 + 217 0004 0A4B ldr r3, .L7+4 + 218 0006 0360 str r3, [r0] + 265:Core/Src/main.c **** hqspi.Init.FifoThreshold = 4; + 219 .loc 1 265 3 is_stmt 1 view .LVU60 + 265:Core/Src/main.c **** hqspi.Init.FifoThreshold = 4; + 220 .loc 1 265 29 is_stmt 0 view .LVU61 + 221 0008 0223 movs r3, #2 + 222 000a 4360 str r3, [r0, #4] + 266:Core/Src/main.c **** hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; + 223 .loc 1 266 3 is_stmt 1 view .LVU62 + 266:Core/Src/main.c **** hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; + 224 .loc 1 266 28 is_stmt 0 view .LVU63 + 225 000c 0423 movs r3, #4 + 226 000e 8360 str r3, [r0, #8] + 267:Core/Src/main.c **** hqspi.Init.FlashSize = 24; + 227 .loc 1 267 3 is_stmt 1 view .LVU64 + 267:Core/Src/main.c **** hqspi.Init.FlashSize = 24; + 228 .loc 1 267 29 is_stmt 0 view .LVU65 + 229 0010 0023 movs r3, #0 + 230 0012 C360 str r3, [r0, #12] + 268:Core/Src/main.c **** hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; + 231 .loc 1 268 3 is_stmt 1 view .LVU66 + 268:Core/Src/main.c **** hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; + 232 .loc 1 268 24 is_stmt 0 view .LVU67 + 233 0014 1822 movs r2, #24 + 234 0016 0261 str r2, [r0, #16] + 269:Core/Src/main.c **** hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; + 235 .loc 1 269 3 is_stmt 1 view .LVU68 + 269:Core/Src/main.c **** hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3; + 236 .loc 1 269 33 is_stmt 0 view .LVU69 + 237 0018 4FF40072 mov r2, #512 + 238 001c 4261 str r2, [r0, #20] + 270:Core/Src/main.c **** hqspi.Init.FlashID = QSPI_FLASH_ID_1; + 239 .loc 1 270 3 is_stmt 1 view .LVU70 + 270:Core/Src/main.c **** hqspi.Init.FlashID = QSPI_FLASH_ID_1; + 240 .loc 1 270 24 is_stmt 0 view .LVU71 + 241 001e 0122 movs r2, #1 + 242 0020 8261 str r2, [r0, #24] + 271:Core/Src/main.c **** hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + 243 .loc 1 271 3 is_stmt 1 view .LVU72 + 271:Core/Src/main.c **** hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + 244 .loc 1 271 22 is_stmt 0 view .LVU73 + 245 0022 C361 str r3, [r0, #28] + 272:Core/Src/main.c **** if (HAL_QSPI_Init(&hqspi) != HAL_OK) + 246 .loc 1 272 3 is_stmt 1 view .LVU74 + 272:Core/Src/main.c **** if (HAL_QSPI_Init(&hqspi) != HAL_OK) + 247 .loc 1 272 24 is_stmt 0 view .LVU75 + ARM GAS /tmp/ccOSKXvF.s page 12 + + + 248 0024 0362 str r3, [r0, #32] + 273:Core/Src/main.c **** { + 249 .loc 1 273 3 is_stmt 1 view .LVU76 + 273:Core/Src/main.c **** { + 250 .loc 1 273 7 is_stmt 0 view .LVU77 + 251 0026 FFF7FEFF bl HAL_QSPI_Init + 252 .LVL3: + 281:Core/Src/main.c **** + 253 .loc 1 281 1 view .LVU78 + 254 002a 08BD pop {r3, pc} + 255 .L8: + 256 .align 2 + 257 .L7: + 258 002c 00000000 .word .LANCHOR0 + 259 0030 00500052 .word 1375752192 + 260 .cfi_endproc + 261 .LFE147: + 263 .section .text.MX_USART1_UART_Init,"ax",%progbits + 264 .align 1 + 265 .syntax unified + 266 .thumb + 267 .thumb_func + 268 .fpu fpv5-d16 + 270 MX_USART1_UART_Init: + 271 .LFB148: + 289:Core/Src/main.c **** + 272 .loc 1 289 1 is_stmt 1 view -0 + 273 .cfi_startproc + 274 @ args = 0, pretend = 0, frame = 0 + 275 @ frame_needed = 0, uses_anonymous_args = 0 + 276 0000 38B5 push {r3, r4, r5, lr} + 277 .LCFI4: + 278 .cfi_def_cfa_offset 16 + 279 .cfi_offset 3, -16 + 280 .cfi_offset 4, -12 + 281 .cfi_offset 5, -8 + 282 .cfi_offset 14, -4 + 298:Core/Src/main.c **** huart1.Init.BaudRate = 921600; + 283 .loc 1 298 3 view .LVU80 + 298:Core/Src/main.c **** huart1.Init.BaudRate = 921600; + 284 .loc 1 298 19 is_stmt 0 view .LVU81 + 285 0002 104C ldr r4, .L11 + 286 0004 104B ldr r3, .L11+4 + 287 0006 2360 str r3, [r4] + 299:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; + 288 .loc 1 299 3 is_stmt 1 view .LVU82 + 299:Core/Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B; + 289 .loc 1 299 24 is_stmt 0 view .LVU83 + 290 0008 4FF46123 mov r3, #921600 + 291 000c 6360 str r3, [r4, #4] + 300:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; + 292 .loc 1 300 3 is_stmt 1 view .LVU84 + 300:Core/Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1; + 293 .loc 1 300 26 is_stmt 0 view .LVU85 + 294 000e 0025 movs r5, #0 + 295 0010 A560 str r5, [r4, #8] + 301:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; + ARM GAS /tmp/ccOSKXvF.s page 13 + + + 296 .loc 1 301 3 is_stmt 1 view .LVU86 + 301:Core/Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE; + 297 .loc 1 301 24 is_stmt 0 view .LVU87 + 298 0012 E560 str r5, [r4, #12] + 302:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; + 299 .loc 1 302 3 is_stmt 1 view .LVU88 + 302:Core/Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX; + 300 .loc 1 302 22 is_stmt 0 view .LVU89 + 301 0014 2561 str r5, [r4, #16] + 303:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 302 .loc 1 303 3 is_stmt 1 view .LVU90 + 303:Core/Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 303 .loc 1 303 20 is_stmt 0 view .LVU91 + 304 0016 0C23 movs r3, #12 + 305 0018 6361 str r3, [r4, #20] + 304:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 306 .loc 1 304 3 is_stmt 1 view .LVU92 + 304:Core/Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 307 .loc 1 304 25 is_stmt 0 view .LVU93 + 308 001a A561 str r5, [r4, #24] + 305:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 309 .loc 1 305 3 is_stmt 1 view .LVU94 + 305:Core/Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 310 .loc 1 305 28 is_stmt 0 view .LVU95 + 311 001c E561 str r5, [r4, #28] + 306:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 312 .loc 1 306 3 is_stmt 1 view .LVU96 + 306:Core/Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 313 .loc 1 306 30 is_stmt 0 view .LVU97 + 314 001e 2562 str r5, [r4, #32] + 307:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 315 .loc 1 307 3 is_stmt 1 view .LVU98 + 307:Core/Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 316 .loc 1 307 30 is_stmt 0 view .LVU99 + 317 0020 6562 str r5, [r4, #36] + 308:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) + 318 .loc 1 308 3 is_stmt 1 view .LVU100 + 308:Core/Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK) + 319 .loc 1 308 38 is_stmt 0 view .LVU101 + 320 0022 A562 str r5, [r4, #40] + 309:Core/Src/main.c **** { + 321 .loc 1 309 3 is_stmt 1 view .LVU102 + 309:Core/Src/main.c **** { + 322 .loc 1 309 7 is_stmt 0 view .LVU103 + 323 0024 2046 mov r0, r4 + 324 0026 FFF7FEFF bl HAL_UART_Init + 325 .LVL4: + 313:Core/Src/main.c **** { + 326 .loc 1 313 3 is_stmt 1 view .LVU104 + 313:Core/Src/main.c **** { + 327 .loc 1 313 7 is_stmt 0 view .LVU105 + 328 002a 2946 mov r1, r5 + 329 002c 2046 mov r0, r4 + 330 002e FFF7FEFF bl HAL_UARTEx_SetTxFifoThreshold + 331 .LVL5: + 317:Core/Src/main.c **** { + 332 .loc 1 317 3 is_stmt 1 view .LVU106 + ARM GAS /tmp/ccOSKXvF.s page 14 + + + 317:Core/Src/main.c **** { + 333 .loc 1 317 7 is_stmt 0 view .LVU107 + 334 0032 2946 mov r1, r5 + 335 0034 2046 mov r0, r4 + 336 0036 FFF7FEFF bl HAL_UARTEx_SetRxFifoThreshold + 337 .LVL6: + 321:Core/Src/main.c **** { + 338 .loc 1 321 3 is_stmt 1 view .LVU108 + 321:Core/Src/main.c **** { + 339 .loc 1 321 7 is_stmt 0 view .LVU109 + 340 003a 2046 mov r0, r4 + 341 003c FFF7FEFF bl HAL_UARTEx_DisableFifoMode + 342 .LVL7: + 329:Core/Src/main.c **** + 343 .loc 1 329 1 view .LVU110 + 344 0040 38BD pop {r3, r4, r5, pc} + 345 .L12: + 346 0042 00BF .align 2 + 347 .L11: + 348 0044 00000000 .word .LANCHOR1 + 349 0048 00100140 .word 1073811456 + 350 .cfi_endproc + 351 .LFE148: + 353 .section .text.SystemClock_Config,"ax",%progbits + 354 .align 1 + 355 .global SystemClock_Config + 356 .syntax unified + 357 .thumb + 358 .thumb_func + 359 .fpu fpv5-d16 + 361 SystemClock_Config: + 362 .LFB146: + 180:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 363 .loc 1 180 1 is_stmt 1 view -0 + 364 .cfi_startproc + 365 @ args = 0, pretend = 0, frame = 304 + 366 @ frame_needed = 0, uses_anonymous_args = 0 + 367 0000 70B5 push {r4, r5, r6, lr} + 368 .LCFI5: + 369 .cfi_def_cfa_offset 16 + 370 .cfi_offset 4, -16 + 371 .cfi_offset 5, -12 + 372 .cfi_offset 6, -8 + 373 .cfi_offset 14, -4 + 374 0002 CCB0 sub sp, sp, #304 + 375 .LCFI6: + 376 .cfi_def_cfa_offset 320 + 181:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 377 .loc 1 181 3 view .LVU112 + 181:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 378 .loc 1 181 22 is_stmt 0 view .LVU113 + 379 0004 4C22 movs r2, #76 + 380 0006 0021 movs r1, #0 + 381 0008 39A8 add r0, sp, #228 + 382 000a FFF7FEFF bl memset + 383 .LVL8: + 182:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + ARM GAS /tmp/ccOSKXvF.s page 15 + + + 384 .loc 1 182 3 is_stmt 1 view .LVU114 + 182:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 385 .loc 1 182 22 is_stmt 0 view .LVU115 + 386 000e 2022 movs r2, #32 + 387 0010 0021 movs r1, #0 + 388 0012 31A8 add r0, sp, #196 + 389 0014 FFF7FEFF bl memset + 390 .LVL9: + 183:Core/Src/main.c **** + 391 .loc 1 183 3 is_stmt 1 view .LVU116 + 183:Core/Src/main.c **** + 392 .loc 1 183 28 is_stmt 0 view .LVU117 + 393 0018 BC22 movs r2, #188 + 394 001a 0021 movs r1, #0 + 395 001c 02A8 add r0, sp, #8 + 396 001e FFF7FEFF bl memset + 397 .LVL10: + 187:Core/Src/main.c **** /** Configure the main internal regulator output voltage + 398 .loc 1 187 3 is_stmt 1 view .LVU118 + 399 0022 0220 movs r0, #2 + 400 0024 FFF7FEFF bl HAL_PWREx_ConfigSupply + 401 .LVL11: + 190:Core/Src/main.c **** + 402 .loc 1 190 3 view .LVU119 + 403 .LBB8: + 190:Core/Src/main.c **** + 404 .loc 1 190 3 view .LVU120 + 405 0028 0023 movs r3, #0 + 406 002a 0193 str r3, [sp, #4] + 190:Core/Src/main.c **** + 407 .loc 1 190 3 view .LVU121 + 190:Core/Src/main.c **** + 408 .loc 1 190 3 view .LVU122 + 409 002c 294B ldr r3, .L16 + 410 002e DA6A ldr r2, [r3, #44] + 411 0030 22F00102 bic r2, r2, #1 + 412 0034 DA62 str r2, [r3, #44] + 190:Core/Src/main.c **** + 413 .loc 1 190 3 view .LVU123 + 414 0036 DB6A ldr r3, [r3, #44] + 415 0038 03F00103 and r3, r3, #1 + 416 003c 0193 str r3, [sp, #4] + 190:Core/Src/main.c **** + 417 .loc 1 190 3 view .LVU124 + 418 003e 264B ldr r3, .L16+4 + 419 0040 9A69 ldr r2, [r3, #24] + 420 0042 42F44042 orr r2, r2, #49152 + 421 0046 9A61 str r2, [r3, #24] + 190:Core/Src/main.c **** + 422 .loc 1 190 3 view .LVU125 + 423 0048 9B69 ldr r3, [r3, #24] + 424 004a 03F44043 and r3, r3, #49152 + 425 004e 0193 str r3, [sp, #4] + 190:Core/Src/main.c **** + 426 .loc 1 190 3 view .LVU126 + 427 0050 019B ldr r3, [sp, #4] + 428 .LBE8: + ARM GAS /tmp/ccOSKXvF.s page 16 + + + 190:Core/Src/main.c **** + 429 .loc 1 190 3 view .LVU127 + 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 430 .loc 1 192 3 view .LVU128 + 431 .L14: + 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 432 .loc 1 192 48 discriminator 1 view .LVU129 + 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 433 .loc 1 192 8 discriminator 1 view .LVU130 + 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 434 .loc 1 192 10 is_stmt 0 discriminator 1 view .LVU131 + 435 0052 214B ldr r3, .L16+4 + 436 0054 9B69 ldr r3, [r3, #24] + 192:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 437 .loc 1 192 8 discriminator 1 view .LVU132 + 438 0056 13F4005F tst r3, #8192 + 439 005a FAD0 beq .L14 + 196:Core/Src/main.c **** |RCC_OSCILLATORTYPE_HSE; + 440 .loc 1 196 3 is_stmt 1 view .LVU133 + 196:Core/Src/main.c **** |RCC_OSCILLATORTYPE_HSE; + 441 .loc 1 196 36 is_stmt 0 view .LVU134 + 442 005c 2323 movs r3, #35 + 443 005e 3993 str r3, [sp, #228] + 198:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + 444 .loc 1 198 3 is_stmt 1 view .LVU135 + 198:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + 445 .loc 1 198 30 is_stmt 0 view .LVU136 + 446 0060 4FF48033 mov r3, #65536 + 447 0064 3A93 str r3, [sp, #232] + 199:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 448 .loc 1 199 3 is_stmt 1 view .LVU137 + 199:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 449 .loc 1 199 30 is_stmt 0 view .LVU138 + 450 0066 0122 movs r2, #1 + 451 0068 3C92 str r2, [sp, #240] + 200:Core/Src/main.c **** RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + 452 .loc 1 200 3 is_stmt 1 view .LVU139 + 200:Core/Src/main.c **** RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + 453 .loc 1 200 41 is_stmt 0 view .LVU140 + 454 006a 4025 movs r5, #64 + 455 006c 3D95 str r5, [sp, #244] + 201:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 456 .loc 1 201 3 is_stmt 1 view .LVU141 + 201:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 457 .loc 1 201 32 is_stmt 0 view .LVU142 + 458 006e 3F92 str r2, [sp, #252] + 202:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 459 .loc 1 202 3 is_stmt 1 view .LVU143 + 202:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 460 .loc 1 202 34 is_stmt 0 view .LVU144 + 461 0070 0223 movs r3, #2 + 462 0072 4293 str r3, [sp, #264] + 203:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2; + 463 .loc 1 203 3 is_stmt 1 view .LVU145 + 203:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2; + 464 .loc 1 203 35 is_stmt 0 view .LVU146 + 465 0074 4393 str r3, [sp, #268] + ARM GAS /tmp/ccOSKXvF.s page 17 + + + 204:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 40; + 466 .loc 1 204 3 is_stmt 1 view .LVU147 + 204:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 40; + 467 .loc 1 204 30 is_stmt 0 view .LVU148 + 468 0076 4493 str r3, [sp, #272] + 205:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; + 469 .loc 1 205 3 is_stmt 1 view .LVU149 + 205:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; + 470 .loc 1 205 30 is_stmt 0 view .LVU150 + 471 0078 2821 movs r1, #40 + 472 007a 4591 str r1, [sp, #276] + 206:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 1; + 473 .loc 1 206 3 is_stmt 1 view .LVU151 + 206:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 1; + 474 .loc 1 206 30 is_stmt 0 view .LVU152 + 475 007c 4693 str r3, [sp, #280] + 207:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 1; + 476 .loc 1 207 3 is_stmt 1 view .LVU153 + 207:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 1; + 477 .loc 1 207 30 is_stmt 0 view .LVU154 + 478 007e 4792 str r2, [sp, #284] + 208:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + 479 .loc 1 208 3 is_stmt 1 view .LVU155 + 208:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + 480 .loc 1 208 30 is_stmt 0 view .LVU156 + 481 0080 4892 str r2, [sp, #288] + 209:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; + 482 .loc 1 209 3 is_stmt 1 view .LVU157 + 209:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; + 483 .loc 1 209 32 is_stmt 0 view .LVU158 + 484 0082 0826 movs r6, #8 + 485 0084 4996 str r6, [sp, #292] + 210:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; + 486 .loc 1 210 3 is_stmt 1 view .LVU159 + 210:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; + 487 .loc 1 210 35 is_stmt 0 view .LVU160 + 488 0086 4A93 str r3, [sp, #296] + 211:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 489 .loc 1 211 3 is_stmt 1 view .LVU161 + 211:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 490 .loc 1 211 34 is_stmt 0 view .LVU162 + 491 0088 0024 movs r4, #0 + 492 008a 4B94 str r4, [sp, #300] + 212:Core/Src/main.c **** { + 493 .loc 1 212 3 is_stmt 1 view .LVU163 + 212:Core/Src/main.c **** { + 494 .loc 1 212 7 is_stmt 0 view .LVU164 + 495 008c 39A8 add r0, sp, #228 + 496 008e FFF7FEFF bl HAL_RCC_OscConfig + 497 .LVL12: + 218:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + 498 .loc 1 218 3 is_stmt 1 view .LVU165 + 218:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + 499 .loc 1 218 31 is_stmt 0 view .LVU166 + 500 0092 3F23 movs r3, #63 + 501 0094 3193 str r3, [sp, #196] + 221:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + ARM GAS /tmp/ccOSKXvF.s page 18 + + + 502 .loc 1 221 3 is_stmt 1 view .LVU167 + 221:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + 503 .loc 1 221 34 is_stmt 0 view .LVU168 + 504 0096 0323 movs r3, #3 + 505 0098 3293 str r3, [sp, #200] + 222:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + 506 .loc 1 222 3 is_stmt 1 view .LVU169 + 222:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + 507 .loc 1 222 35 is_stmt 0 view .LVU170 + 508 009a 3394 str r4, [sp, #204] + 223:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + 509 .loc 1 223 3 is_stmt 1 view .LVU171 + 223:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + 510 .loc 1 223 35 is_stmt 0 view .LVU172 + 511 009c 3496 str r6, [sp, #208] + 224:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + 512 .loc 1 224 3 is_stmt 1 view .LVU173 + 224:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + 513 .loc 1 224 36 is_stmt 0 view .LVU174 + 514 009e 3595 str r5, [sp, #212] + 225:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + 515 .loc 1 225 3 is_stmt 1 view .LVU175 + 225:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + 516 .loc 1 225 36 is_stmt 0 view .LVU176 + 517 00a0 3695 str r5, [sp, #216] + 226:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + 518 .loc 1 226 3 is_stmt 1 view .LVU177 + 226:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + 519 .loc 1 226 36 is_stmt 0 view .LVU178 + 520 00a2 4FF48063 mov r3, #1024 + 521 00a6 3793 str r3, [sp, #220] + 227:Core/Src/main.c **** + 522 .loc 1 227 3 is_stmt 1 view .LVU179 + 227:Core/Src/main.c **** + 523 .loc 1 227 36 is_stmt 0 view .LVU180 + 524 00a8 3895 str r5, [sp, #224] + 229:Core/Src/main.c **** { + 525 .loc 1 229 3 is_stmt 1 view .LVU181 + 229:Core/Src/main.c **** { + 526 .loc 1 229 7 is_stmt 0 view .LVU182 + 527 00aa 2146 mov r1, r4 + 528 00ac 31A8 add r0, sp, #196 + 529 00ae FFF7FEFF bl HAL_RCC_ClockConfig + 530 .LVL13: + 233:Core/Src/main.c **** |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; + 531 .loc 1 233 3 is_stmt 1 view .LVU183 + 233:Core/Src/main.c **** |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_CKPER; + 532 .loc 1 233 44 is_stmt 0 view .LVU184 + 533 00b2 0A4B ldr r3, .L16+8 + 534 00b4 0293 str r3, [sp, #8] + 235:Core/Src/main.c **** PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; + 535 .loc 1 235 3 is_stmt 1 view .LVU185 + 235:Core/Src/main.c **** PeriphClkInitStruct.CkperClockSelection = RCC_CLKPSOURCE_HSI; + 536 .loc 1 235 42 is_stmt 0 view .LVU186 + 537 00b6 3023 movs r3, #48 + 538 00b8 1493 str r3, [sp, #80] + 236:Core/Src/main.c **** PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + ARM GAS /tmp/ccOSKXvF.s page 19 + + + 539 .loc 1 236 3 is_stmt 1 view .LVU187 + 236:Core/Src/main.c **** PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + 540 .loc 1 236 43 is_stmt 0 view .LVU188 + 541 00ba 1694 str r4, [sp, #88] + 237:Core/Src/main.c **** PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + 542 .loc 1 237 3 is_stmt 1 view .LVU189 + 237:Core/Src/main.c **** PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + 543 .loc 1 237 45 is_stmt 0 view .LVU190 + 544 00bc 2094 str r4, [sp, #128] + 238:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 545 .loc 1 238 3 is_stmt 1 view .LVU191 + 238:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 546 .loc 1 238 41 is_stmt 0 view .LVU192 + 547 00be 4FF44013 mov r3, #3145728 + 548 00c2 2393 str r3, [sp, #140] + 239:Core/Src/main.c **** { + 549 .loc 1 239 3 is_stmt 1 view .LVU193 + 239:Core/Src/main.c **** { + 550 .loc 1 239 7 is_stmt 0 view .LVU194 + 551 00c4 0DEB0600 add r0, sp, r6 + 552 00c8 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 553 .LVL14: + 245:Core/Src/main.c **** } + 554 .loc 1 245 3 is_stmt 1 view .LVU195 + 555 00cc FFF7FEFF bl HAL_PWREx_EnableUSBVoltageDetector + 556 .LVL15: + 246:Core/Src/main.c **** + 557 .loc 1 246 1 is_stmt 0 view .LVU196 + 558 00d0 4CB0 add sp, sp, #304 + 559 .LCFI7: + 560 .cfi_def_cfa_offset 16 + 561 @ sp needed + 562 00d2 70BD pop {r4, r5, r6, pc} + 563 .L17: + 564 .align 2 + 565 .L16: + 566 00d4 00040058 .word 1476396032 + 567 00d8 00480258 .word 1476544512 + 568 00dc 01000482 .word -2113667071 + 569 .cfi_endproc + 570 .LFE146: + 572 .section .rodata.main.str1.4,"aMS",%progbits,1 + 573 .align 2 + 574 .LC0: + 575 0000 4D61696E .ascii "Main: Mfg: 0x%x\015\012\000" + 575 3A204D66 + 575 673A2030 + 575 7825780D + 575 0A00 + 576 0012 0000 .align 2 + 577 .LC1: + 578 0014 51535049 .ascii "QSPI mapped ok!\015\012\000" + 578 206D6170 + 578 70656420 + 578 6F6B210D + 578 0A00 + 579 0026 0000 .align 2 + ARM GAS /tmp/ccOSKXvF.s page 20 + + + 580 .LC2: + 581 0028 56616C69 .ascii "Valid SP found!\015\012\000" + 581 64205350 + 581 20666F75 + 581 6E64210D + 581 0A00 + 582 003a 0000 .align 2 + 583 .LC3: + 584 003c 456E7472 .ascii "Entry: 0x%08lx\015\012\000" + 584 793A2030 + 584 78253038 + 584 6C780D0A + 584 00 + 585 004d 000000 .align 2 + 586 .LC4: + 587 0050 4E6F2076 .ascii "No valid image found!\015\012\000" + 587 616C6964 + 587 20696D61 + 587 67652066 + 587 6F756E64 + 588 .section .text.main,"ax",%progbits + 589 .align 1 + 590 .global main + 591 .syntax unified + 592 .thumb + 593 .thumb_func + 594 .fpu fpv5-d16 + 596 main: + 597 .LFB145: + 78:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 598 .loc 1 78 1 is_stmt 1 view -0 + 599 .cfi_startproc + 600 @ args = 0, pretend = 0, frame = 80 + 601 @ frame_needed = 0, uses_anonymous_args = 0 + 602 0000 30B5 push {r4, r5, lr} + 603 .LCFI8: + 604 .cfi_def_cfa_offset 12 + 605 .cfi_offset 4, -12 + 606 .cfi_offset 5, -8 + 607 .cfi_offset 14, -4 + 608 0002 95B0 sub sp, sp, #84 + 609 .LCFI9: + 610 .cfi_def_cfa_offset 96 + 86:Core/Src/main.c **** + 611 .loc 1 86 3 view .LVU198 + 612 0004 FFF7FEFF bl HAL_Init + 613 .LVL16: + 93:Core/Src/main.c **** + 614 .loc 1 93 3 view .LVU199 + 615 0008 FFF7FEFF bl SystemClock_Config + 616 .LVL17: + 100:Core/Src/main.c **** MX_QUADSPI_Init(); + 617 .loc 1 100 3 view .LVU200 + 618 000c FFF7FEFF bl MX_GPIO_Init + 619 .LVL18: + 101:Core/Src/main.c **** MX_USART1_UART_Init(); + 620 .loc 1 101 3 view .LVU201 + ARM GAS /tmp/ccOSKXvF.s page 21 + + + 621 0010 FFF7FEFF bl MX_QUADSPI_Init + 622 .LVL19: + 102:Core/Src/main.c **** MX_USB_DEVICE_Init(); + 623 .loc 1 102 3 view .LVU202 + 624 0014 FFF7FEFF bl MX_USART1_UART_Init + 625 .LVL20: + 103:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 626 .loc 1 103 3 view .LVU203 + 627 0018 FFF7FEFF bl MX_USB_DEVICE_Init + 628 .LVL21: + 106:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; + 629 .loc 1 106 3 view .LVU204 + 106:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; + 630 .loc 1 106 6 is_stmt 0 view .LVU205 + 631 001c 344B ldr r3, .L25 + 632 001e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 106:Core/Src/main.c **** QSPI_CommandTypeDef sCommand; + 633 .loc 1 106 5 view .LVU206 + 634 0020 03B1 cbz r3, .L23 + 635 .L19: + 166:Core/Src/main.c **** { + 636 .loc 1 166 3 is_stmt 1 discriminator 2 view .LVU207 + 171:Core/Src/main.c **** /* USER CODE END 3 */ + 637 .loc 1 171 3 discriminator 2 view .LVU208 + 166:Core/Src/main.c **** { + 638 .loc 1 166 9 discriminator 2 view .LVU209 + 639 0022 FEE7 b .L19 + 640 .L23: + 641 .LBB9: + 107:Core/Src/main.c **** QSPI_MemoryMappedTypeDef sMemMappedCfg; + 642 .loc 1 107 7 view .LVU210 + 108:Core/Src/main.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; + 643 .loc 1 108 7 view .LVU211 + 109:Core/Src/main.c **** sCommand.AddressMode = QSPI_ADDRESS_4_LINES; + 644 .loc 1 109 7 view .LVU212 + 109:Core/Src/main.c **** sCommand.AddressMode = QSPI_ADDRESS_4_LINES; + 645 .loc 1 109 32 is_stmt 0 view .LVU213 + 646 0024 4FF48073 mov r3, #256 + 647 0028 0C93 str r3, [sp, #48] + 110:Core/Src/main.c **** sCommand.AddressSize = QSPI_ADDRESS_24_BITS; + 648 .loc 1 110 7 is_stmt 1 view .LVU214 + 110:Core/Src/main.c **** sCommand.AddressSize = QSPI_ADDRESS_24_BITS; + 649 .loc 1 110 28 is_stmt 0 view .LVU215 + 650 002a 4FF44063 mov r3, #3072 + 651 002e 0D93 str r3, [sp, #52] + 111:Core/Src/main.c **** sCommand.DataMode = QSPI_DATA_4_LINES; + 652 .loc 1 111 7 is_stmt 1 view .LVU216 + 111:Core/Src/main.c **** sCommand.DataMode = QSPI_DATA_4_LINES; + 653 .loc 1 111 28 is_stmt 0 view .LVU217 + 654 0030 4FF40053 mov r3, #8192 + 655 0034 0993 str r3, [sp, #36] + 112:Core/Src/main.c **** sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; + 656 .loc 1 112 7 is_stmt 1 view .LVU218 + 112:Core/Src/main.c **** sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; + 657 .loc 1 112 25 is_stmt 0 view .LVU219 + 658 0036 4FF04073 mov r3, #50331648 + 659 003a 0F93 str r3, [sp, #60] + ARM GAS /tmp/ccOSKXvF.s page 22 + + + 113:Core/Src/main.c **** sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; + 660 .loc 1 113 7 is_stmt 1 view .LVU220 + 113:Core/Src/main.c **** sCommand.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS; + 661 .loc 1 113 34 is_stmt 0 view .LVU221 + 662 003c 4FF44043 mov r3, #49152 + 663 0040 0E93 str r3, [sp, #56] + 114:Core/Src/main.c **** sCommand.AlternateBytes = 0xFF; + 664 .loc 1 114 7 is_stmt 1 view .LVU222 + 114:Core/Src/main.c **** sCommand.AlternateBytes = 0xFF; + 665 .loc 1 114 35 is_stmt 0 view .LVU223 + 666 0042 0024 movs r4, #0 + 667 0044 0A94 str r4, [sp, #40] + 115:Core/Src/main.c **** sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; + 668 .loc 1 115 7 is_stmt 1 view .LVU224 + 115:Core/Src/main.c **** sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; + 669 .loc 1 115 31 is_stmt 0 view .LVU225 + 670 0046 FF23 movs r3, #255 + 671 0048 0893 str r3, [sp, #32] + 116:Core/Src/main.c **** sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + 672 .loc 1 116 7 is_stmt 1 view .LVU226 + 116:Core/Src/main.c **** sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + 673 .loc 1 116 24 is_stmt 0 view .LVU227 + 674 004a 1194 str r4, [sp, #68] + 117:Core/Src/main.c **** sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + 675 .loc 1 117 7 is_stmt 1 view .LVU228 + 117:Core/Src/main.c **** sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + 676 .loc 1 117 33 is_stmt 0 view .LVU229 + 677 004c 1294 str r4, [sp, #72] + 118:Core/Src/main.c **** sCommand.Instruction = 0xEB; + 678 .loc 1 118 7 is_stmt 1 view .LVU230 + 118:Core/Src/main.c **** sCommand.Instruction = 0xEB; + 679 .loc 1 118 25 is_stmt 0 view .LVU231 + 680 004e 1394 str r4, [sp, #76] + 119:Core/Src/main.c **** sCommand.DummyCycles = 4; + 681 .loc 1 119 7 is_stmt 1 view .LVU232 + 119:Core/Src/main.c **** sCommand.DummyCycles = 4; + 682 .loc 1 119 28 is_stmt 0 view .LVU233 + 683 0050 EB23 movs r3, #235 + 684 0052 0693 str r3, [sp, #24] + 120:Core/Src/main.c **** sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; + 685 .loc 1 120 7 is_stmt 1 view .LVU234 + 120:Core/Src/main.c **** sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; + 686 .loc 1 120 28 is_stmt 0 view .LVU235 + 687 0054 0423 movs r3, #4 + 688 0056 0B93 str r3, [sp, #44] + 121:Core/Src/main.c **** sMemMappedCfg.TimeOutPeriod = 0; + 689 .loc 1 121 7 is_stmt 1 view .LVU236 + 121:Core/Src/main.c **** sMemMappedCfg.TimeOutPeriod = 0; + 690 .loc 1 121 39 is_stmt 0 view .LVU237 + 691 0058 0194 str r4, [sp, #4] + 122:Core/Src/main.c **** + 692 .loc 1 122 7 is_stmt 1 view .LVU238 + 122:Core/Src/main.c **** + 693 .loc 1 122 35 is_stmt 0 view .LVU239 + 694 005a 0094 str r4, [sp] + 124:Core/Src/main.c **** w25_flash.interface = &hqspi; + 695 .loc 1 124 7 is_stmt 1 view .LVU240 + ARM GAS /tmp/ccOSKXvF.s page 23 + + + 125:Core/Src/main.c **** w25_flash.mode = W25_MODE_QUAD; + 696 .loc 1 125 7 view .LVU241 + 125:Core/Src/main.c **** w25_flash.mode = W25_MODE_QUAD; + 697 .loc 1 125 27 is_stmt 0 view .LVU242 + 698 005c 254D ldr r5, .L25+4 + 699 005e 0295 str r5, [sp, #8] + 126:Core/Src/main.c **** w25_flash.address_size = W25_ADDRESS_24BITS; + 700 .loc 1 126 7 is_stmt 1 view .LVU243 + 126:Core/Src/main.c **** w25_flash.address_size = W25_ADDRESS_24BITS; + 701 .loc 1 126 22 is_stmt 0 view .LVU244 + 702 0060 0223 movs r3, #2 + 703 0062 8DF80C30 strb r3, [sp, #12] + 127:Core/Src/main.c **** + 704 .loc 1 127 7 is_stmt 1 view .LVU245 + 127:Core/Src/main.c **** + 705 .loc 1 127 30 is_stmt 0 view .LVU246 + 706 0066 8DF80D40 strb r4, [sp, #13] + 130:Core/Src/main.c **** #endif // USE_QPI_MODE + 707 .loc 1 130 7 is_stmt 1 view .LVU247 + 708 006a 2146 mov r1, r4 + 709 006c 02A8 add r0, sp, #8 + 710 006e FFF7FEFF bl W25_QPI_Mode + 711 .LVL22: + 133:Core/Src/main.c **** printf("Main: Mfg: 0x%x\r\n", w25_flash.manufacturer); + 712 .loc 1 133 7 view .LVU248 + 713 0072 02A8 add r0, sp, #8 + 714 0074 FFF7FEFF bl W25_QSPI_Init + 715 .LVL23: + 134:Core/Src/main.c **** + 716 .loc 1 134 7 view .LVU249 + 717 0078 9DF81410 ldrb r1, [sp, #20] @ zero_extendqisi2 + 718 007c 1E48 ldr r0, .L25+8 + 719 007e FFF7FEFF bl printf_ + 720 .LVL24: + 136:Core/Src/main.c **** + 721 .loc 1 136 7 view .LVU250 + 722 0082 2146 mov r1, r4 + 723 0084 02A8 add r0, sp, #8 + 724 0086 FFF7FEFF bl W25_QSPI_QuadEnable + 725 .LVL25: + 139:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 1); + 726 .loc 1 139 7 view .LVU251 + 139:Core/Src/main.c **** W25_QPI_Mode(&w25_flash, 1); + 727 .loc 1 139 32 is_stmt 0 view .LVU252 + 728 008a 4FF44073 mov r3, #768 + 729 008e 0C93 str r3, [sp, #48] + 140:Core/Src/main.c **** #if(QPI_HIGH_SPEED == 1) // For 80MHz HIGHHHHHH speed QPI mode(33-80MHz), additional 4 dummy cycles + 730 .loc 1 140 7 is_stmt 1 view .LVU253 + 731 0090 0121 movs r1, #1 + 732 0092 02A8 add r0, sp, #8 + 733 0094 FFF7FEFF bl W25_QPI_Mode + 734 .LVL26: + 145:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); + 735 .loc 1 145 7 view .LVU254 + 145:Core/Src/main.c **** W25_QPI_ReadParams(&w25_flash, W25_QPI_DUMMY_2, W25_QPI_WRAP_LENGTH_8); + 736 .loc 1 145 28 is_stmt 0 view .LVU255 + 737 0098 0B94 str r4, [sp, #44] + ARM GAS /tmp/ccOSKXvF.s page 24 + + + 146:Core/Src/main.c **** #endif // QPI_HIGH_SPEED + 738 .loc 1 146 7 is_stmt 1 view .LVU256 + 739 009a 2246 mov r2, r4 + 740 009c 2146 mov r1, r4 + 741 009e 02A8 add r0, sp, #8 + 742 00a0 FFF7FEFF bl W25_QPI_ReadParams + 743 .LVL27: + 150:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); + 744 .loc 1 150 7 view .LVU257 + 150:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); + 745 .loc 1 150 10 is_stmt 0 view .LVU258 + 746 00a4 6A46 mov r2, sp + 747 00a6 06A9 add r1, sp, #24 + 748 00a8 2846 mov r0, r5 + 749 00aa FFF7FEFF bl HAL_QSPI_MemoryMapped + 750 .LVL28: + 150:Core/Src/main.c **** printf("QSPI mapped ok!\r\n"); + 751 .loc 1 150 9 view .LVU259 + 752 00ae 00B1 cbz r0, .L24 + 753 .L20: + 754 00b0 B7E7 b .L19 + 755 .L24: + 151:Core/Src/main.c **** if(BL_CheckValidImage(0x90000000) == HAL_OK) { + 756 .loc 1 151 11 is_stmt 1 view .LVU260 + 757 00b2 1248 ldr r0, .L25+12 + 758 00b4 FFF7FEFF bl printf_ + 759 .LVL29: + 152:Core/Src/main.c **** printf("Valid SP found!\r\n"); + 760 .loc 1 152 11 view .LVU261 + 152:Core/Src/main.c **** printf("Valid SP found!\r\n"); + 761 .loc 1 152 14 is_stmt 0 view .LVU262 + 762 00b8 4FF01040 mov r0, #-1879048192 + 763 00bc FFF7FEFF bl BL_CheckValidImage + 764 .LVL30: + 152:Core/Src/main.c **** printf("Valid SP found!\r\n"); + 765 .loc 1 152 13 view .LVU263 + 766 00c0 88B9 cbnz r0, .L21 + 767 .LBB10: + 153:Core/Src/main.c **** uint32_t entry = BL_GetEntryPoint(0x90000000); + 768 .loc 1 153 15 is_stmt 1 view .LVU264 + 769 00c2 0F48 ldr r0, .L25+16 + 770 00c4 FFF7FEFF bl printf_ + 771 .LVL31: + 154:Core/Src/main.c **** printf("Entry: 0x%08lx\r\n", entry); + 772 .loc 1 154 15 view .LVU265 + 154:Core/Src/main.c **** printf("Entry: 0x%08lx\r\n", entry); + 773 .loc 1 154 32 is_stmt 0 view .LVU266 + 774 00c8 4FF01040 mov r0, #-1879048192 + 775 00cc FFF7FEFF bl BL_GetEntryPoint + 776 .LVL32: + 777 00d0 0446 mov r4, r0 + 778 .LVL33: + 155:Core/Src/main.c **** BL_JumpToXIPStart(entry, 0x90000000); + 779 .loc 1 155 15 is_stmt 1 view .LVU267 + 780 00d2 0146 mov r1, r0 + 781 00d4 0B48 ldr r0, .L25+20 + 782 .LVL34: + ARM GAS /tmp/ccOSKXvF.s page 25 + + + 155:Core/Src/main.c **** BL_JumpToXIPStart(entry, 0x90000000); + 783 .loc 1 155 15 is_stmt 0 view .LVU268 + 784 00d6 FFF7FEFF bl printf_ + 785 .LVL35: + 156:Core/Src/main.c **** } + 786 .loc 1 156 15 is_stmt 1 view .LVU269 + 787 00da 4FF01041 mov r1, #-1879048192 + 788 00de 2046 mov r0, r4 + 789 00e0 FFF7FEFF bl BL_JumpToXIPStart + 790 .LVL36: + 791 .LBE10: + 792 00e4 E4E7 b .L20 + 793 .LVL37: + 794 .L21: + 158:Core/Src/main.c **** } + 795 .loc 1 158 16 view .LVU270 + 796 00e6 0848 ldr r0, .L25+24 + 797 00e8 FFF7FEFF bl printf_ + 798 .LVL38: + 799 00ec E0E7 b .L20 + 800 .L26: + 801 00ee 00BF .align 2 + 802 .L25: + 803 00f0 00000000 .word .LANCHOR2 + 804 00f4 00000000 .word .LANCHOR0 + 805 00f8 00000000 .word .LC0 + 806 00fc 14000000 .word .LC1 + 807 0100 28000000 .word .LC2 + 808 0104 3C000000 .word .LC3 + 809 0108 50000000 .word .LC4 + 810 .LBE9: + 811 .cfi_endproc + 812 .LFE145: + 814 .section .text.Error_Handler,"ax",%progbits + 815 .align 1 + 816 .global Error_Handler + 817 .syntax unified + 818 .thumb + 819 .thumb_func + 820 .fpu fpv5-d16 + 822 Error_Handler: + 823 .LFB150: + 365:Core/Src/main.c **** + 366:Core/Src/main.c **** /* USER CODE BEGIN 4 */ + 367:Core/Src/main.c **** + 368:Core/Src/main.c **** /* USER CODE END 4 */ + 369:Core/Src/main.c **** + 370:Core/Src/main.c **** /** + 371:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. + 372:Core/Src/main.c **** * @retval None + 373:Core/Src/main.c **** */ + 374:Core/Src/main.c **** void Error_Handler(void) + 375:Core/Src/main.c **** { + 824 .loc 1 375 1 view -0 + 825 .cfi_startproc + 826 @ args = 0, pretend = 0, frame = 0 + 827 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccOSKXvF.s page 26 + + + 828 @ link register save eliminated. + 376:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ + 377:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ + 378:Core/Src/main.c **** + 379:Core/Src/main.c **** /* USER CODE END Error_Handler_Debug */ + 380:Core/Src/main.c **** } + 829 .loc 1 380 1 view .LVU272 + 830 0000 7047 bx lr + 831 .cfi_endproc + 832 .LFE150: + 834 .global g_DFU + 835 .global huart1 + 836 .global hqspi + 837 .section .bss.g_DFU,"aw",%nobits + 838 .set .LANCHOR2,. + 0 + 841 g_DFU: + 842 0000 00 .space 1 + 843 .section .bss.hqspi,"aw",%nobits + 844 .align 2 + 845 .set .LANCHOR0,. + 0 + 848 hqspi: + 849 0000 00000000 .space 76 + 849 00000000 + 849 00000000 + 849 00000000 + 849 00000000 + 850 .section .bss.huart1,"aw",%nobits + 851 .align 2 + 852 .set .LANCHOR1,. + 0 + 855 huart1: + 856 0000 00000000 .space 140 + 856 00000000 + 856 00000000 + 856 00000000 + 856 00000000 + 857 .text + 858 .Letext0: + 859 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 860 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 861 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 862 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 863 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" + 864 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h" + 865 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + 866 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 867 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 868 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" + 869 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" + 870 .file 13 "Core/Inc/w25_qspi.h" + 871 .file 14 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h" + 872 .file 15 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h" + 873 .file 16 "Core/Inc/printf.h" + 874 .file 17 "Core/Inc/bootloader_control.h" + 875 .file 18 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 876 .file 19 "USB_DEVICE/App/usb_device.h" + 877 .file 20 "" + ARM GAS /tmp/ccOSKXvF.s page 27 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 main.c + /tmp/ccOSKXvF.s:17 .text.MX_GPIO_Init:0000000000000000 $t + /tmp/ccOSKXvF.s:24 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init + /tmp/ccOSKXvF.s:190 .text.MX_GPIO_Init:00000000000000d8 $d + /tmp/ccOSKXvF.s:197 .text.MX_QUADSPI_Init:0000000000000000 $t + /tmp/ccOSKXvF.s:203 .text.MX_QUADSPI_Init:0000000000000000 MX_QUADSPI_Init + /tmp/ccOSKXvF.s:258 .text.MX_QUADSPI_Init:000000000000002c $d + /tmp/ccOSKXvF.s:264 .text.MX_USART1_UART_Init:0000000000000000 $t + /tmp/ccOSKXvF.s:270 .text.MX_USART1_UART_Init:0000000000000000 MX_USART1_UART_Init + /tmp/ccOSKXvF.s:348 .text.MX_USART1_UART_Init:0000000000000044 $d + /tmp/ccOSKXvF.s:354 .text.SystemClock_Config:0000000000000000 $t + /tmp/ccOSKXvF.s:361 .text.SystemClock_Config:0000000000000000 SystemClock_Config + /tmp/ccOSKXvF.s:566 .text.SystemClock_Config:00000000000000d4 $d + /tmp/ccOSKXvF.s:573 .rodata.main.str1.4:0000000000000000 $d + /tmp/ccOSKXvF.s:589 .text.main:0000000000000000 $t + /tmp/ccOSKXvF.s:596 .text.main:0000000000000000 main + /tmp/ccOSKXvF.s:803 .text.main:00000000000000f0 $d + /tmp/ccOSKXvF.s:815 .text.Error_Handler:0000000000000000 $t + /tmp/ccOSKXvF.s:822 .text.Error_Handler:0000000000000000 Error_Handler + /tmp/ccOSKXvF.s:841 .bss.g_DFU:0000000000000000 g_DFU + /tmp/ccOSKXvF.s:855 .bss.huart1:0000000000000000 huart1 + /tmp/ccOSKXvF.s:848 .bss.hqspi:0000000000000000 hqspi + /tmp/ccOSKXvF.s:842 .bss.g_DFU:0000000000000000 $d + /tmp/ccOSKXvF.s:844 .bss.hqspi:0000000000000000 $d + /tmp/ccOSKXvF.s:851 .bss.huart1:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_WritePin +HAL_GPIO_Init +HAL_QSPI_Init +HAL_UART_Init +HAL_UARTEx_SetTxFifoThreshold +HAL_UARTEx_SetRxFifoThreshold +HAL_UARTEx_DisableFifoMode +memset +HAL_PWREx_ConfigSupply +HAL_RCC_OscConfig +HAL_RCC_ClockConfig +HAL_RCCEx_PeriphCLKConfig +HAL_PWREx_EnableUSBVoltageDetector +HAL_Init +MX_USB_DEVICE_Init +W25_QPI_Mode +W25_QSPI_Init +printf_ +W25_QSPI_QuadEnable +W25_QPI_ReadParams +HAL_QSPI_MemoryMapped +BL_CheckValidImage +BL_GetEntryPoint +BL_JumpToXIPStart diff --git a/build/main.o b/build/main.o new file mode 100644 index 0000000..bf7e814 Binary files /dev/null and b/build/main.o differ diff --git a/build/port_printf.d b/build/port_printf.d new file mode 100644 index 0000000..e442c66 --- /dev/null +++ b/build/port_printf.d @@ -0,0 +1,69 @@ +build/port_printf.o: Core/Src/port_printf.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/printf.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/printf.h: diff --git a/build/port_printf.lst b/build/port_printf.lst new file mode 100644 index 0000000..e302182 --- /dev/null +++ b/build/port_printf.lst @@ -0,0 +1,98 @@ +ARM GAS /tmp/ccAYJ7K0.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "port_printf.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text._putchar,"ax",%progbits + 17 .align 1 + 18 .global _putchar + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 _putchar: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Core/Src/port_printf.c" + 1:Core/Src/port_printf.c **** // + 2:Core/Src/port_printf.c **** // Created by imi415 on 2019/12/06. + 3:Core/Src/port_printf.c **** // + 4:Core/Src/port_printf.c **** #include "stm32h7xx_hal.h" + 5:Core/Src/port_printf.c **** #include "printf.h" + 6:Core/Src/port_printf.c **** + 7:Core/Src/port_printf.c **** extern UART_HandleTypeDef huart1; + 8:Core/Src/port_printf.c **** + 9:Core/Src/port_printf.c **** void _putchar(char character) { + 29 .loc 1 9 31 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 9 31 is_stmt 0 view .LVU1 + 34 0000 00B5 push {lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 14, -4 + 38 0002 83B0 sub sp, sp, #12 + 39 .LCFI1: + 40 .cfi_def_cfa_offset 16 + 41 0004 8DF80700 strb r0, [sp, #7] + 10:Core/Src/port_printf.c **** HAL_UART_Transmit(&huart1, (uint8_t *)&character, 0x01, 1000); + 42 .loc 1 10 5 is_stmt 1 view .LVU2 + 43 0008 4FF47A73 mov r3, #1000 + 44 000c 0122 movs r2, #1 + 45 000e 0DF10701 add r1, sp, #7 + 46 0012 0348 ldr r0, .L3 + 47 .LVL1: + 48 .loc 1 10 5 is_stmt 0 view .LVU3 + ARM GAS /tmp/ccAYJ7K0.s page 2 + + + 49 0014 FFF7FEFF bl HAL_UART_Transmit + 50 .LVL2: + 11:Core/Src/port_printf.c **** }... + 51 .loc 1 11 1 view .LVU4 + 52 0018 03B0 add sp, sp, #12 + 53 .LCFI2: + 54 .cfi_def_cfa_offset 4 + 55 @ sp needed + 56 001a 5DF804FB ldr pc, [sp], #4 + 57 .L4: + 58 001e 00BF .align 2 + 59 .L3: + 60 0020 00000000 .word huart1 + 61 .cfi_endproc + 62 .LFE141: + 64 .text + 65 .Letext0: + 66 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 67 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 68 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 69 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 70 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 71 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" + ARM GAS /tmp/ccAYJ7K0.s page 3 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 port_printf.c + /tmp/ccAYJ7K0.s:17 .text._putchar:0000000000000000 $t + /tmp/ccAYJ7K0.s:25 .text._putchar:0000000000000000 _putchar + /tmp/ccAYJ7K0.s:60 .text._putchar:0000000000000020 $d + +UNDEFINED SYMBOLS +HAL_UART_Transmit +huart1 diff --git a/build/port_printf.o b/build/port_printf.o new file mode 100644 index 0000000..085bc6d Binary files /dev/null and b/build/port_printf.o differ diff --git a/build/printf.d b/build/printf.d new file mode 100644 index 0000000..c597341 --- /dev/null +++ b/build/printf.d @@ -0,0 +1,2 @@ +build/printf.o: Core/Src/printf.c Core/Inc/printf.h +Core/Inc/printf.h: diff --git a/build/printf.lst b/build/printf.lst new file mode 100644 index 0000000..f6819b7 --- /dev/null +++ b/build/printf.lst @@ -0,0 +1,5871 @@ +ARM GAS /tmp/ccibzHy5.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "printf.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text._out_buffer,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 _out_buffer: + 25 .LVL0: + 26 .LFB0: + 27 .file 1 "Core/Src/printf.c" + 1:Core/Src/printf.c **** /////////////////////////////////////////////////////////////////////////////// + 2:Core/Src/printf.c **** // \author (c) Marco Paland (info@paland.com) + 3:Core/Src/printf.c **** // 2014-2019, PALANDesign Hannover, Germany + 4:Core/Src/printf.c **** // + 5:Core/Src/printf.c **** // \license The MIT License (MIT) + 6:Core/Src/printf.c **** // + 7:Core/Src/printf.c **** // Permission is hereby granted, free of charge, to any person obtaining a copy + 8:Core/Src/printf.c **** // of this software and associated documentation files (the "Software"), to deal + 9:Core/Src/printf.c **** // in the Software without restriction, including without limitation the rights + 10:Core/Src/printf.c **** // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + 11:Core/Src/printf.c **** // copies of the Software, and to permit persons to whom the Software is + 12:Core/Src/printf.c **** // furnished to do so, subject to the following conditions: + 13:Core/Src/printf.c **** // + 14:Core/Src/printf.c **** // The above copyright notice and this permission notice shall be included in + 15:Core/Src/printf.c **** // all copies or substantial portions of the Software. + 16:Core/Src/printf.c **** // + 17:Core/Src/printf.c **** // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + 18:Core/Src/printf.c **** // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + 19:Core/Src/printf.c **** // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + 20:Core/Src/printf.c **** // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + 21:Core/Src/printf.c **** // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + 22:Core/Src/printf.c **** // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + 23:Core/Src/printf.c **** // THE SOFTWARE. + 24:Core/Src/printf.c **** // + 25:Core/Src/printf.c **** // \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on + 26:Core/Src/printf.c **** // embedded systems with a very limited resources. These routines are thread + 27:Core/Src/printf.c **** // safe and reentrant! + 28:Core/Src/printf.c **** // Use this instead of the bloated standard/newlib printf cause these use + 29:Core/Src/printf.c **** // malloc for printf (and may not be thread safe). + 30:Core/Src/printf.c **** // + 31:Core/Src/printf.c **** /////////////////////////////////////////////////////////////////////////////// + ARM GAS /tmp/ccibzHy5.s page 2 + + + 32:Core/Src/printf.c **** + 33:Core/Src/printf.c **** #include + 34:Core/Src/printf.c **** #include + 35:Core/Src/printf.c **** + 36:Core/Src/printf.c **** #include "printf.h" + 37:Core/Src/printf.c **** + 38:Core/Src/printf.c **** + 39:Core/Src/printf.c **** // define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the + 40:Core/Src/printf.c **** // printf_config.h header file + 41:Core/Src/printf.c **** // default: undefined + 42:Core/Src/printf.c **** #ifdef PRINTF_INCLUDE_CONFIG_H + 43:Core/Src/printf.c **** #include "printf_config.h" + 44:Core/Src/printf.c **** #endif + 45:Core/Src/printf.c **** + 46:Core/Src/printf.c **** + 47:Core/Src/printf.c **** // 'ntoa' conversion buffer size, this must be big enough to hold one converted + 48:Core/Src/printf.c **** // numeric number including padded zeros (dynamically created on stack) + 49:Core/Src/printf.c **** // default: 32 byte + 50:Core/Src/printf.c **** #ifndef PRINTF_NTOA_BUFFER_SIZE + 51:Core/Src/printf.c **** #define PRINTF_NTOA_BUFFER_SIZE 32U + 52:Core/Src/printf.c **** #endif + 53:Core/Src/printf.c **** + 54:Core/Src/printf.c **** // 'ftoa' conversion buffer size, this must be big enough to hold one converted + 55:Core/Src/printf.c **** // float number including padded zeros (dynamically created on stack) + 56:Core/Src/printf.c **** // default: 32 byte + 57:Core/Src/printf.c **** #ifndef PRINTF_FTOA_BUFFER_SIZE + 58:Core/Src/printf.c **** #define PRINTF_FTOA_BUFFER_SIZE 32U + 59:Core/Src/printf.c **** #endif + 60:Core/Src/printf.c **** + 61:Core/Src/printf.c **** // support for the floating point type (%f) + 62:Core/Src/printf.c **** // default: activated + 63:Core/Src/printf.c **** #ifndef PRINTF_DISABLE_SUPPORT_FLOAT + 64:Core/Src/printf.c **** #define PRINTF_SUPPORT_FLOAT + 65:Core/Src/printf.c **** #endif + 66:Core/Src/printf.c **** + 67:Core/Src/printf.c **** // support for exponential floating point notation (%e/%g) + 68:Core/Src/printf.c **** // default: activated + 69:Core/Src/printf.c **** #ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL + 70:Core/Src/printf.c **** #define PRINTF_SUPPORT_EXPONENTIAL + 71:Core/Src/printf.c **** #endif + 72:Core/Src/printf.c **** + 73:Core/Src/printf.c **** // define the default floating point precision + 74:Core/Src/printf.c **** // default: 6 digits + 75:Core/Src/printf.c **** #ifndef PRINTF_DEFAULT_FLOAT_PRECISION + 76:Core/Src/printf.c **** #define PRINTF_DEFAULT_FLOAT_PRECISION 6U + 77:Core/Src/printf.c **** #endif + 78:Core/Src/printf.c **** + 79:Core/Src/printf.c **** // define the largest float suitable to print with %f + 80:Core/Src/printf.c **** // default: 1e9 + 81:Core/Src/printf.c **** #ifndef PRINTF_MAX_FLOAT + 82:Core/Src/printf.c **** #define PRINTF_MAX_FLOAT 1e9 + 83:Core/Src/printf.c **** #endif + 84:Core/Src/printf.c **** + 85:Core/Src/printf.c **** // support for the long long types (%llu or %p) + 86:Core/Src/printf.c **** // default: activated + 87:Core/Src/printf.c **** #ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG + 88:Core/Src/printf.c **** #define PRINTF_SUPPORT_LONG_LONG + ARM GAS /tmp/ccibzHy5.s page 3 + + + 89:Core/Src/printf.c **** #endif + 90:Core/Src/printf.c **** + 91:Core/Src/printf.c **** // support for the ptrdiff_t type (%t) + 92:Core/Src/printf.c **** // ptrdiff_t is normally defined in as long or long long type + 93:Core/Src/printf.c **** // default: activated + 94:Core/Src/printf.c **** #ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T + 95:Core/Src/printf.c **** #define PRINTF_SUPPORT_PTRDIFF_T + 96:Core/Src/printf.c **** #endif + 97:Core/Src/printf.c **** + 98:Core/Src/printf.c **** /////////////////////////////////////////////////////////////////////////////// + 99:Core/Src/printf.c **** + 100:Core/Src/printf.c **** // internal flag definitions + 101:Core/Src/printf.c **** #define FLAGS_ZEROPAD (1U << 0U) + 102:Core/Src/printf.c **** #define FLAGS_LEFT (1U << 1U) + 103:Core/Src/printf.c **** #define FLAGS_PLUS (1U << 2U) + 104:Core/Src/printf.c **** #define FLAGS_SPACE (1U << 3U) + 105:Core/Src/printf.c **** #define FLAGS_HASH (1U << 4U) + 106:Core/Src/printf.c **** #define FLAGS_UPPERCASE (1U << 5U) + 107:Core/Src/printf.c **** #define FLAGS_CHAR (1U << 6U) + 108:Core/Src/printf.c **** #define FLAGS_SHORT (1U << 7U) + 109:Core/Src/printf.c **** #define FLAGS_LONG (1U << 8U) + 110:Core/Src/printf.c **** #define FLAGS_LONG_LONG (1U << 9U) + 111:Core/Src/printf.c **** #define FLAGS_PRECISION (1U << 10U) + 112:Core/Src/printf.c **** #define FLAGS_ADAPT_EXP (1U << 11U) + 113:Core/Src/printf.c **** + 114:Core/Src/printf.c **** + 115:Core/Src/printf.c **** // import float.h for DBL_MAX + 116:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_FLOAT) + 117:Core/Src/printf.c **** #include + 118:Core/Src/printf.c **** #endif + 119:Core/Src/printf.c **** + 120:Core/Src/printf.c **** + 121:Core/Src/printf.c **** // output function type + 122:Core/Src/printf.c **** typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen); + 123:Core/Src/printf.c **** + 124:Core/Src/printf.c **** + 125:Core/Src/printf.c **** // wrapper (used as buffer) for output function type + 126:Core/Src/printf.c **** typedef struct { + 127:Core/Src/printf.c **** void (*fct)(char character, void* arg); + 128:Core/Src/printf.c **** void* arg; + 129:Core/Src/printf.c **** } out_fct_wrap_type; + 130:Core/Src/printf.c **** + 131:Core/Src/printf.c **** + 132:Core/Src/printf.c **** // internal buffer output + 133:Core/Src/printf.c **** static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen) + 134:Core/Src/printf.c **** { + 28 .loc 1 134 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 135:Core/Src/printf.c **** if (idx < maxlen) { + 33 .loc 1 135 3 view .LVU1 + 34 .loc 1 135 6 is_stmt 0 view .LVU2 + 35 0000 9A42 cmp r2, r3 + 36 0002 00D2 bcs .L1 + 136:Core/Src/printf.c **** ((char*)buffer)[idx] = character; + ARM GAS /tmp/ccibzHy5.s page 4 + + + 37 .loc 1 136 5 is_stmt 1 view .LVU3 + 38 .loc 1 136 26 is_stmt 0 view .LVU4 + 39 0004 8854 strb r0, [r1, r2] + 40 .L1: + 137:Core/Src/printf.c **** } + 138:Core/Src/printf.c **** } + 41 .loc 1 138 1 view .LVU5 + 42 0006 7047 bx lr + 43 .cfi_endproc + 44 .LFE0: + 46 .section .text._out_null,"ax",%progbits + 47 .align 1 + 48 .syntax unified + 49 .thumb + 50 .thumb_func + 51 .fpu fpv5-d16 + 53 _out_null: + 54 .LVL1: + 55 .LFB1: + 139:Core/Src/printf.c **** + 140:Core/Src/printf.c **** + 141:Core/Src/printf.c **** // internal null output + 142:Core/Src/printf.c **** static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen) + 143:Core/Src/printf.c **** { + 56 .loc 1 143 1 is_stmt 1 view -0 + 57 .cfi_startproc + 58 @ args = 0, pretend = 0, frame = 0 + 59 @ frame_needed = 0, uses_anonymous_args = 0 + 60 @ link register save eliminated. + 144:Core/Src/printf.c **** (void)character; (void)buffer; (void)idx; (void)maxlen; + 61 .loc 1 144 3 view .LVU7 + 62 .loc 1 144 20 view .LVU8 + 63 .loc 1 144 34 view .LVU9 + 64 .loc 1 144 45 view .LVU10 + 145:Core/Src/printf.c **** } + 65 .loc 1 145 1 is_stmt 0 view .LVU11 + 66 0000 7047 bx lr + 67 .cfi_endproc + 68 .LFE1: + 70 .section .text._out_fct,"ax",%progbits + 71 .align 1 + 72 .syntax unified + 73 .thumb + 74 .thumb_func + 75 .fpu fpv5-d16 + 77 _out_fct: + 78 .LVL2: + 79 .LFB3: + 146:Core/Src/printf.c **** + 147:Core/Src/printf.c **** + 148:Core/Src/printf.c **** // internal _putchar wrapper + 149:Core/Src/printf.c **** static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen) + 150:Core/Src/printf.c **** { + 151:Core/Src/printf.c **** (void)buffer; (void)idx; (void)maxlen; + 152:Core/Src/printf.c **** if (character) { + 153:Core/Src/printf.c **** _putchar(character); + 154:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 5 + + + 155:Core/Src/printf.c **** } + 156:Core/Src/printf.c **** + 157:Core/Src/printf.c **** + 158:Core/Src/printf.c **** // internal output function wrapper + 159:Core/Src/printf.c **** static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen) + 160:Core/Src/printf.c **** { + 80 .loc 1 160 1 is_stmt 1 view -0 + 81 .cfi_startproc + 82 @ args = 0, pretend = 0, frame = 0 + 83 @ frame_needed = 0, uses_anonymous_args = 0 + 161:Core/Src/printf.c **** (void)idx; (void)maxlen; + 84 .loc 1 161 3 view .LVU13 + 85 .loc 1 161 14 view .LVU14 + 162:Core/Src/printf.c **** if (character) { + 86 .loc 1 162 3 view .LVU15 + 87 .loc 1 162 6 is_stmt 0 view .LVU16 + 88 0000 20B1 cbz r0, .L7 + 160:Core/Src/printf.c **** (void)idx; (void)maxlen; + 89 .loc 1 160 1 view .LVU17 + 90 0002 08B5 push {r3, lr} + 91 .LCFI0: + 92 .cfi_def_cfa_offset 8 + 93 .cfi_offset 3, -8 + 94 .cfi_offset 14, -4 + 163:Core/Src/printf.c **** // buffer is the output fct pointer + 164:Core/Src/printf.c **** ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg); + 95 .loc 1 164 5 is_stmt 1 view .LVU18 + 96 .loc 1 164 33 is_stmt 0 view .LVU19 + 97 0004 0A68 ldr r2, [r1] + 98 .LVL3: + 99 .loc 1 164 6 view .LVU20 + 100 0006 4968 ldr r1, [r1, #4] + 101 .LVL4: + 102 .loc 1 164 6 view .LVU21 + 103 0008 9047 blx r2 + 104 .LVL5: + 165:Core/Src/printf.c **** } + 166:Core/Src/printf.c **** } + 105 .loc 1 166 1 view .LVU22 + 106 000a 08BD pop {r3, pc} + 107 .LVL6: + 108 .L7: + 109 .LCFI1: + 110 .cfi_def_cfa_offset 0 + 111 .cfi_restore 3 + 112 .cfi_restore 14 + 113 .loc 1 166 1 view .LVU23 + 114 000c 7047 bx lr + 115 .cfi_endproc + 116 .LFE3: + 118 .section .text._atoi,"ax",%progbits + 119 .align 1 + 120 .syntax unified + 121 .thumb + 122 .thumb_func + 123 .fpu fpv5-d16 + 125 _atoi: + ARM GAS /tmp/ccibzHy5.s page 6 + + + 126 .LVL7: + 127 .LFB6: + 167:Core/Src/printf.c **** + 168:Core/Src/printf.c **** + 169:Core/Src/printf.c **** // internal secure strlen + 170:Core/Src/printf.c **** // \return The length of the string (excluding the terminating 0) limited by 'maxsize' + 171:Core/Src/printf.c **** static inline unsigned int _strnlen_s(const char* str, size_t maxsize) + 172:Core/Src/printf.c **** { + 173:Core/Src/printf.c **** const char* s; + 174:Core/Src/printf.c **** for (s = str; *s && maxsize--; ++s); + 175:Core/Src/printf.c **** return (unsigned int)(s - str); + 176:Core/Src/printf.c **** } + 177:Core/Src/printf.c **** + 178:Core/Src/printf.c **** + 179:Core/Src/printf.c **** // internal test if char is a digit (0-9) + 180:Core/Src/printf.c **** // \return true if char is a digit + 181:Core/Src/printf.c **** static inline bool _is_digit(char ch) + 182:Core/Src/printf.c **** { + 183:Core/Src/printf.c **** return (ch >= '0') && (ch <= '9'); + 184:Core/Src/printf.c **** } + 185:Core/Src/printf.c **** + 186:Core/Src/printf.c **** + 187:Core/Src/printf.c **** // internal ASCII string to unsigned int conversion + 188:Core/Src/printf.c **** static unsigned int _atoi(const char** str) + 189:Core/Src/printf.c **** { + 128 .loc 1 189 1 is_stmt 1 view -0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 @ link register save eliminated. + 133 .loc 1 189 1 is_stmt 0 view .LVU25 + 134 0000 0146 mov r1, r0 + 190:Core/Src/printf.c **** unsigned int i = 0U; + 135 .loc 1 190 3 is_stmt 1 view .LVU26 + 136 .LVL8: + 191:Core/Src/printf.c **** while (_is_digit(**str)) { + 137 .loc 1 191 3 view .LVU27 + 190:Core/Src/printf.c **** unsigned int i = 0U; + 138 .loc 1 190 16 is_stmt 0 view .LVU28 + 139 0002 0020 movs r0, #0 + 140 .LVL9: + 141 .loc 1 191 9 view .LVU29 + 142 0004 07E0 b .L11 + 143 .LVL10: + 144 .L12: + 192:Core/Src/printf.c **** i = i * 10U + (unsigned int)(*((*str)++) - '0'); + 145 .loc 1 192 5 is_stmt 1 view .LVU30 + 146 .loc 1 192 11 is_stmt 0 view .LVU31 + 147 0006 00EB8000 add r0, r0, r0, lsl #2 + 148 .LVL11: + 149 .loc 1 192 42 view .LVU32 + 150 000a 531C adds r3, r2, #1 + 151 000c 0B60 str r3, [r1] + 152 .loc 1 192 34 view .LVU33 + 153 000e 1378 ldrb r3, [r2] @ zero_extendqisi2 + 154 .loc 1 192 17 view .LVU34 + 155 0010 03EB4000 add r0, r3, r0, lsl #1 + ARM GAS /tmp/ccibzHy5.s page 7 + + + 156 .loc 1 192 7 view .LVU35 + 157 0014 3038 subs r0, r0, #48 + 158 .LVL12: + 159 .L11: + 191:Core/Src/printf.c **** while (_is_digit(**str)) { + 160 .loc 1 191 9 is_stmt 1 view .LVU36 + 191:Core/Src/printf.c **** while (_is_digit(**str)) { + 161 .loc 1 191 21 is_stmt 0 view .LVU37 + 162 0016 0A68 ldr r2, [r1] + 191:Core/Src/printf.c **** while (_is_digit(**str)) { + 163 .loc 1 191 10 view .LVU38 + 164 0018 1378 ldrb r3, [r2] @ zero_extendqisi2 + 165 .LVL13: + 166 .LBB20: + 167 .LBI20: + 181:Core/Src/printf.c **** { + 168 .loc 1 181 20 is_stmt 1 view .LVU39 + 169 .LBB21: + 183:Core/Src/printf.c **** } + 170 .loc 1 183 3 view .LVU40 + 183:Core/Src/printf.c **** } + 171 .loc 1 183 22 is_stmt 0 view .LVU41 + 172 001a 303B subs r3, r3, #48 + 173 .LVL14: + 183:Core/Src/printf.c **** } + 174 .loc 1 183 22 view .LVU42 + 175 001c DBB2 uxtb r3, r3 + 176 .LVL15: + 183:Core/Src/printf.c **** } + 177 .loc 1 183 22 view .LVU43 + 178 .LBE21: + 179 .LBE20: + 191:Core/Src/printf.c **** i = i * 10U + (unsigned int)(*((*str)++) - '0'); + 180 .loc 1 191 9 view .LVU44 + 181 001e 092B cmp r3, #9 + 182 0020 F1D9 bls .L12 + 193:Core/Src/printf.c **** } + 194:Core/Src/printf.c **** return i; + 183 .loc 1 194 3 is_stmt 1 view .LVU45 + 195:Core/Src/printf.c **** } + 184 .loc 1 195 1 is_stmt 0 view .LVU46 + 185 0022 7047 bx lr + 186 .cfi_endproc + 187 .LFE6: + 189 .section .text._out_rev,"ax",%progbits + 190 .align 1 + 191 .syntax unified + 192 .thumb + 193 .thumb_func + 194 .fpu fpv5-d16 + 196 _out_rev: + 197 .LVL16: + 198 .LFB7: + 196:Core/Src/printf.c **** + 197:Core/Src/printf.c **** + 198:Core/Src/printf.c **** // output the specified string in reverse, taking care of any zero-padding + 199:Core/Src/printf.c **** static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, + ARM GAS /tmp/ccibzHy5.s page 8 + + + 200:Core/Src/printf.c **** { + 199 .loc 1 200 1 is_stmt 1 view -0 + 200 .cfi_startproc + 201 @ args = 16, pretend = 0, frame = 8 + 202 @ frame_needed = 0, uses_anonymous_args = 0 + 203 .loc 1 200 1 is_stmt 0 view .LVU48 + 204 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 205 .LCFI2: + 206 .cfi_def_cfa_offset 36 + 207 .cfi_offset 4, -36 + 208 .cfi_offset 5, -32 + 209 .cfi_offset 6, -28 + 210 .cfi_offset 7, -24 + 211 .cfi_offset 8, -20 + 212 .cfi_offset 9, -16 + 213 .cfi_offset 10, -12 + 214 .cfi_offset 11, -8 + 215 .cfi_offset 14, -4 + 216 0004 83B0 sub sp, sp, #12 + 217 .LCFI3: + 218 .cfi_def_cfa_offset 48 + 219 0006 0546 mov r5, r0 + 220 0008 0E46 mov r6, r1 + 221 000a 9346 mov fp, r2 + 222 000c 1F46 mov r7, r3 + 223 000e DDF830A0 ldr r10, [sp, #48] + 224 0012 0D9C ldr r4, [sp, #52] + 225 0014 DDF83890 ldr r9, [sp, #56] + 201:Core/Src/printf.c **** const size_t start_idx = idx; + 226 .loc 1 201 3 is_stmt 1 view .LVU49 + 227 .LVL17: + 202:Core/Src/printf.c **** + 203:Core/Src/printf.c **** // pad spaces up to given width + 204:Core/Src/printf.c **** if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { + 228 .loc 1 204 3 view .LVU50 + 229 .loc 1 204 6 is_stmt 0 view .LVU51 + 230 0018 0F9B ldr r3, [sp, #60] + 231 .LVL18: + 232 .loc 1 204 6 view .LVU52 + 233 001a 13F0030F tst r3, #3 + 234 001e 19D1 bne .L15 + 235 .LBB22: + 205:Core/Src/printf.c **** for (size_t i = len; i < width; i++) { + 236 .loc 1 205 17 view .LVU53 + 237 0020 A046 mov r8, r4 + 238 .LBE22: + 239 0022 0192 str r2, [sp, #4] + 240 .LVL19: + 241 .L14: + 242 .LBB23: + 243 .loc 1 205 26 is_stmt 1 discriminator 1 view .LVU54 + 244 .loc 1 205 5 is_stmt 0 discriminator 1 view .LVU55 + 245 0024 C845 cmp r8, r9 + 246 0026 09D2 bcs .L25 + 206:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 247 .loc 1 206 7 is_stmt 1 discriminator 3 view .LVU56 + 248 0028 02F1010B add fp, r2, #1 + ARM GAS /tmp/ccibzHy5.s page 9 + + + 249 .LVL20: + 250 .loc 1 206 7 is_stmt 0 discriminator 3 view .LVU57 + 251 002c 3B46 mov r3, r7 + 252 002e 3146 mov r1, r6 + 253 0030 2020 movs r0, #32 + 254 0032 A847 blx r5 + 255 .LVL21: + 205:Core/Src/printf.c **** for (size_t i = len; i < width; i++) { + 256 .loc 1 205 37 is_stmt 1 discriminator 3 view .LVU58 + 205:Core/Src/printf.c **** for (size_t i = len; i < width; i++) { + 257 .loc 1 205 38 is_stmt 0 discriminator 3 view .LVU59 + 258 0034 08F10108 add r8, r8, #1 + 259 .LVL22: + 260 .loc 1 206 7 discriminator 3 view .LVU60 + 261 0038 5A46 mov r2, fp + 262 003a F3E7 b .L14 + 263 .LVL23: + 264 .L25: + 265 .loc 1 206 7 discriminator 3 view .LVU61 + 266 003c DDF804B0 ldr fp, [sp, #4] + 267 0040 08E0 b .L15 + 268 .LVL24: + 269 .L18: + 270 .loc 1 206 7 discriminator 3 view .LVU62 + 271 .LBE23: + 207:Core/Src/printf.c **** } + 208:Core/Src/printf.c **** } + 209:Core/Src/printf.c **** + 210:Core/Src/printf.c **** // reverse string + 211:Core/Src/printf.c **** while (len) { + 212:Core/Src/printf.c **** out(buf[--len], buffer, idx++, maxlen); + 272 .loc 1 212 5 is_stmt 1 view .LVU63 + 273 0042 013C subs r4, r4, #1 + 274 .LVL25: + 275 .loc 1 212 5 is_stmt 0 view .LVU64 + 276 0044 02F10108 add r8, r2, #1 + 277 .LVL26: + 278 .loc 1 212 5 view .LVU65 + 279 0048 3B46 mov r3, r7 + 280 004a 3146 mov r1, r6 + 281 004c 1AF80400 ldrb r0, [r10, r4] @ zero_extendqisi2 + 282 0050 A847 blx r5 + 283 .LVL27: + 284 0052 4246 mov r2, r8 + 285 .LVL28: + 286 .L15: + 211:Core/Src/printf.c **** out(buf[--len], buffer, idx++, maxlen); + 287 .loc 1 211 9 is_stmt 1 view .LVU66 + 288 0054 002C cmp r4, #0 + 289 0056 F4D1 bne .L18 + 213:Core/Src/printf.c **** } + 214:Core/Src/printf.c **** + 215:Core/Src/printf.c **** // append pad spaces up to given width + 216:Core/Src/printf.c **** if (flags & FLAGS_LEFT) { + 290 .loc 1 216 3 view .LVU67 + 291 .loc 1 216 6 is_stmt 0 view .LVU68 + 292 0058 0F9B ldr r3, [sp, #60] + ARM GAS /tmp/ccibzHy5.s page 10 + + + 293 005a 13F0020F tst r3, #2 + 294 005e 03D1 bne .L19 + 295 .LVL29: + 296 .L13: + 217:Core/Src/printf.c **** while (idx - start_idx < width) { + 218:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 219:Core/Src/printf.c **** } + 220:Core/Src/printf.c **** } + 221:Core/Src/printf.c **** + 222:Core/Src/printf.c **** return idx; + 223:Core/Src/printf.c **** } + 297 .loc 1 223 1 view .LVU69 + 298 0060 1046 mov r0, r2 + 299 0062 03B0 add sp, sp, #12 + 300 .LCFI4: + 301 .cfi_remember_state + 302 .cfi_def_cfa_offset 36 + 303 @ sp needed + 304 0064 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 305 .LVL30: + 306 .L19: + 307 .LCFI5: + 308 .cfi_restore_state + 217:Core/Src/printf.c **** while (idx - start_idx < width) { + 309 .loc 1 217 11 is_stmt 1 view .LVU70 + 217:Core/Src/printf.c **** while (idx - start_idx < width) { + 310 .loc 1 217 16 is_stmt 0 view .LVU71 + 311 0068 A2EB0B03 sub r3, r2, fp + 217:Core/Src/printf.c **** while (idx - start_idx < width) { + 312 .loc 1 217 11 view .LVU72 + 313 006c 4B45 cmp r3, r9 + 314 006e F7D2 bcs .L13 + 218:Core/Src/printf.c **** } + 315 .loc 1 218 7 is_stmt 1 view .LVU73 + 316 0070 541C adds r4, r2, #1 + 317 .LVL31: + 218:Core/Src/printf.c **** } + 318 .loc 1 218 7 is_stmt 0 view .LVU74 + 319 0072 3B46 mov r3, r7 + 320 0074 3146 mov r1, r6 + 321 0076 2020 movs r0, #32 + 322 0078 A847 blx r5 + 323 .LVL32: + 324 007a 2246 mov r2, r4 + 325 007c F4E7 b .L19 + 326 .cfi_endproc + 327 .LFE7: + 329 .section .text._ntoa_format,"ax",%progbits + 330 .align 1 + 331 .syntax unified + 332 .thumb + 333 .thumb_func + 334 .fpu fpv5-d16 + 336 _ntoa_format: + 337 .LVL33: + 338 .LFB8: + 224:Core/Src/printf.c **** + ARM GAS /tmp/ccibzHy5.s page 11 + + + 225:Core/Src/printf.c **** + 226:Core/Src/printf.c **** // internal itoa format + 227:Core/Src/printf.c **** static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, si + 228:Core/Src/printf.c **** { + 339 .loc 1 228 1 is_stmt 1 view -0 + 340 .cfi_startproc + 341 @ args = 28, pretend = 0, frame = 0 + 342 @ frame_needed = 0, uses_anonymous_args = 0 + 343 .loc 1 228 1 is_stmt 0 view .LVU76 + 344 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 345 .LCFI6: + 346 .cfi_def_cfa_offset 28 + 347 .cfi_offset 4, -28 + 348 .cfi_offset 5, -24 + 349 .cfi_offset 6, -20 + 350 .cfi_offset 7, -16 + 351 .cfi_offset 8, -12 + 352 .cfi_offset 9, -8 + 353 .cfi_offset 14, -4 + 354 0004 85B0 sub sp, sp, #20 + 355 .LCFI7: + 356 .cfi_def_cfa_offset 48 + 357 0006 9E46 mov lr, r3 + 358 0008 0C9D ldr r5, [sp, #48] + 359 000a 0D9C ldr r4, [sp, #52] + 360 000c 9DF83890 ldrb r9, [sp, #56] @ zero_extendqisi2 + 361 0010 DDF83C80 ldr r8, [sp, #60] + 362 0014 DDF840C0 ldr ip, [sp, #64] + 363 0018 119B ldr r3, [sp, #68] + 364 .LVL34: + 365 .loc 1 228 1 view .LVU77 + 366 001a 129E ldr r6, [sp, #72] + 229:Core/Src/printf.c **** // pad leading zeros + 230:Core/Src/printf.c **** if (!(flags & FLAGS_LEFT)) { + 367 .loc 1 230 3 is_stmt 1 view .LVU78 + 368 .loc 1 230 6 is_stmt 0 view .LVU79 + 369 001c 16F0020F tst r6, #2 + 370 0020 20D1 bne .L27 + 231:Core/Src/printf.c **** if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + 371 .loc 1 231 5 is_stmt 1 view .LVU80 + 372 .loc 1 231 8 is_stmt 0 view .LVU81 + 373 0022 6BB1 cbz r3, .L30 + 374 .loc 1 231 15 discriminator 1 view .LVU82 + 375 0024 16F0010F tst r6, #1 + 376 0028 0AD0 beq .L30 + 377 .loc 1 231 42 discriminator 2 view .LVU83 + 378 002a B9F1000F cmp r9, #0 + 379 002e 02D1 bne .L29 + 380 .loc 1 231 55 discriminator 3 view .LVU84 + 381 0030 16F00C0F tst r6, #12 + 382 0034 04D0 beq .L30 + 383 .L29: + 232:Core/Src/printf.c **** width--; + 384 .loc 1 232 7 is_stmt 1 view .LVU85 + 385 .loc 1 232 12 is_stmt 0 view .LVU86 + 386 0036 013B subs r3, r3, #1 + 387 .LVL35: + ARM GAS /tmp/ccibzHy5.s page 12 + + + 388 .loc 1 232 12 view .LVU87 + 389 0038 02E0 b .L30 + 390 .LVL36: + 391 .L31: + 233:Core/Src/printf.c **** } + 234:Core/Src/printf.c **** while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + 235:Core/Src/printf.c **** buf[len++] = '0'; + 392 .loc 1 235 7 is_stmt 1 view .LVU88 + 393 .loc 1 235 18 is_stmt 0 view .LVU89 + 394 003a 3027 movs r7, #48 + 395 003c 2F55 strb r7, [r5, r4] + 396 .loc 1 235 14 view .LVU90 + 397 003e 0134 adds r4, r4, #1 + 398 .LVL37: + 399 .L30: + 234:Core/Src/printf.c **** buf[len++] = '0'; + 400 .loc 1 234 11 is_stmt 1 view .LVU91 + 401 0040 1F2C cmp r4, #31 + 402 0042 98BF it ls + 403 0044 6445 cmpls r4, ip + 404 0046 F8D3 bcc .L31 + 405 .L32: + 236:Core/Src/printf.c **** } + 237:Core/Src/printf.c **** while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + 406 .loc 1 237 11 view .LVU92 + 407 0048 16F0010F tst r6, #1 + 408 004c 0AD0 beq .L27 + 409 .loc 1 237 61 is_stmt 0 discriminator 1 view .LVU93 + 410 004e 1F2C cmp r4, #31 + 411 0050 8CBF ite hi + 412 0052 0027 movhi r7, #0 + 413 0054 0127 movls r7, #1 + 414 .loc 1 237 53 discriminator 1 view .LVU94 + 415 0056 9C42 cmp r4, r3 + 416 0058 04D2 bcs .L27 + 417 005a 1FB1 cbz r7, .L27 + 238:Core/Src/printf.c **** buf[len++] = '0'; + 418 .loc 1 238 7 is_stmt 1 view .LVU95 + 419 .LVL38: + 420 .loc 1 238 18 is_stmt 0 view .LVU96 + 421 005c 3027 movs r7, #48 + 422 005e 2F55 strb r7, [r5, r4] + 423 .loc 1 238 14 view .LVU97 + 424 0060 0134 adds r4, r4, #1 + 425 .LVL39: + 426 .loc 1 238 14 view .LVU98 + 427 0062 F1E7 b .L32 + 428 .LVL40: + 429 .L27: + 239:Core/Src/printf.c **** } + 240:Core/Src/printf.c **** } + 241:Core/Src/printf.c **** + 242:Core/Src/printf.c **** // handle hash + 243:Core/Src/printf.c **** if (flags & FLAGS_HASH) { + 430 .loc 1 243 3 is_stmt 1 view .LVU99 + 431 .loc 1 243 6 is_stmt 0 view .LVU100 + 432 0064 16F0100F tst r6, #16 + ARM GAS /tmp/ccibzHy5.s page 13 + + + 433 0068 27D0 beq .L35 + 244:Core/Src/printf.c **** if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { + 434 .loc 1 244 5 is_stmt 1 view .LVU101 + 435 .loc 1 244 8 is_stmt 0 view .LVU102 + 436 006a 16F4806F tst r6, #1024 + 437 006e 11D1 bne .L36 + 438 .loc 1 244 36 discriminator 1 view .LVU103 + 439 0070 84B1 cbz r4, .L36 + 440 .loc 1 244 43 discriminator 2 view .LVU104 + 441 0072 9C42 cmp r4, r3 + 442 0074 18BF it ne + 443 0076 6445 cmpne r4, ip + 444 0078 0CD1 bne .L36 + 245:Core/Src/printf.c **** len--; + 445 .loc 1 245 7 is_stmt 1 view .LVU105 + 446 .LVL41: + 246:Core/Src/printf.c **** if (len && (base == 16U)) { + 447 .loc 1 246 7 view .LVU106 + 448 .loc 1 246 11 is_stmt 0 view .LVU107 + 449 007a B4F1010C subs ip, r4, #1 + 450 .LVL42: + 451 .loc 1 246 11 view .LVU108 + 452 007e 14BF ite ne + 453 0080 0127 movne r7, #1 + 454 0082 0027 moveq r7, #0 + 455 .loc 1 246 15 view .LVU109 + 456 0084 B8F1100F cmp r8, #16 + 457 0088 14BF ite ne + 458 008a 0027 movne r7, #0 + 459 008c 07F00107 andeq r7, r7, #1 + 460 .loc 1 246 10 view .LVU110 + 461 0090 2FB3 cbz r7, .L43 + 247:Core/Src/printf.c **** len--; + 462 .loc 1 247 9 is_stmt 1 view .LVU111 + 463 .loc 1 247 12 is_stmt 0 view .LVU112 + 464 0092 023C subs r4, r4, #2 + 465 .LVL43: + 466 .L36: + 248:Core/Src/printf.c **** } + 249:Core/Src/printf.c **** } + 250:Core/Src/printf.c **** if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + 467 .loc 1 250 5 is_stmt 1 view .LVU113 + 468 .loc 1 250 8 is_stmt 0 view .LVU114 + 469 0094 B8F1100F cmp r8, #16 + 470 0098 23D0 beq .L45 + 471 .L37: + 251:Core/Src/printf.c **** buf[len++] = 'x'; + 252:Core/Src/printf.c **** } + 253:Core/Src/printf.c **** else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + 472 .loc 1 253 10 is_stmt 1 view .LVU115 + 473 .loc 1 253 13 is_stmt 0 view .LVU116 + 474 009a B8F1100F cmp r8, #16 + 475 009e 29D0 beq .L46 + 476 .L39: + 254:Core/Src/printf.c **** buf[len++] = 'X'; + 255:Core/Src/printf.c **** } + 256:Core/Src/printf.c **** else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + ARM GAS /tmp/ccibzHy5.s page 14 + + + 477 .loc 1 256 10 is_stmt 1 view .LVU117 + 478 .loc 1 256 13 is_stmt 0 view .LVU118 + 479 00a0 1F2C cmp r4, #31 + 480 00a2 98BF it ls + 481 00a4 B8F1020F cmpls r8, #2 + 482 00a8 02D1 bne .L38 + 257:Core/Src/printf.c **** buf[len++] = 'b'; + 483 .loc 1 257 7 is_stmt 1 view .LVU119 + 484 .LVL44: + 485 .loc 1 257 18 is_stmt 0 view .LVU120 + 486 00aa 6227 movs r7, #98 + 487 00ac 2F55 strb r7, [r5, r4] + 488 .loc 1 257 14 view .LVU121 + 489 00ae 0134 adds r4, r4, #1 + 490 .LVL45: + 491 .L38: + 258:Core/Src/printf.c **** } + 259:Core/Src/printf.c **** if (len < PRINTF_NTOA_BUFFER_SIZE) { + 492 .loc 1 259 5 is_stmt 1 view .LVU122 + 493 .loc 1 259 8 is_stmt 0 view .LVU123 + 494 00b0 1F2C cmp r4, #31 + 495 00b2 02D8 bhi .L35 + 260:Core/Src/printf.c **** buf[len++] = '0'; + 496 .loc 1 260 7 is_stmt 1 view .LVU124 + 497 .LVL46: + 498 .loc 1 260 18 is_stmt 0 view .LVU125 + 499 00b4 3027 movs r7, #48 + 500 00b6 2F55 strb r7, [r5, r4] + 501 .loc 1 260 14 view .LVU126 + 502 00b8 0134 adds r4, r4, #1 + 503 .LVL47: + 504 .L35: + 261:Core/Src/printf.c **** } + 262:Core/Src/printf.c **** } + 263:Core/Src/printf.c **** + 264:Core/Src/printf.c **** if (len < PRINTF_NTOA_BUFFER_SIZE) { + 505 .loc 1 264 3 is_stmt 1 view .LVU127 + 506 .loc 1 264 6 is_stmt 0 view .LVU128 + 507 00ba 1F2C cmp r4, #31 + 508 00bc 05D8 bhi .L40 + 265:Core/Src/printf.c **** if (negative) { + 509 .loc 1 265 5 is_stmt 1 view .LVU129 + 510 .loc 1 265 8 is_stmt 0 view .LVU130 + 511 00be B9F1000F cmp r9, #0 + 512 00c2 20D0 beq .L41 + 266:Core/Src/printf.c **** buf[len++] = '-'; + 513 .loc 1 266 7 is_stmt 1 view .LVU131 + 514 .LVL48: + 515 .loc 1 266 18 is_stmt 0 view .LVU132 + 516 00c4 2D27 movs r7, #45 + 517 00c6 2F55 strb r7, [r5, r4] + 518 .loc 1 266 14 view .LVU133 + 519 00c8 0134 adds r4, r4, #1 + 520 .LVL49: + 521 .L40: + 267:Core/Src/printf.c **** } + 268:Core/Src/printf.c **** else if (flags & FLAGS_PLUS) { + ARM GAS /tmp/ccibzHy5.s page 15 + + + 269:Core/Src/printf.c **** buf[len++] = '+'; // ignore the space if the '+' exists + 270:Core/Src/printf.c **** } + 271:Core/Src/printf.c **** else if (flags & FLAGS_SPACE) { + 272:Core/Src/printf.c **** buf[len++] = ' '; + 273:Core/Src/printf.c **** } + 274:Core/Src/printf.c **** } + 275:Core/Src/printf.c **** + 276:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); + 522 .loc 1 276 3 is_stmt 1 view .LVU134 + 523 .loc 1 276 10 is_stmt 0 view .LVU135 + 524 00ca 0396 str r6, [sp, #12] + 525 00cc 0293 str r3, [sp, #8] + 526 00ce 0194 str r4, [sp, #4] + 527 00d0 0095 str r5, [sp] + 528 00d2 7346 mov r3, lr + 529 .LVL50: + 530 .loc 1 276 10 view .LVU136 + 531 00d4 FFF7FEFF bl _out_rev + 532 .LVL51: + 277:Core/Src/printf.c **** } + 533 .loc 1 277 1 view .LVU137 + 534 00d8 05B0 add sp, sp, #20 + 535 .LCFI8: + 536 .cfi_remember_state + 537 .cfi_def_cfa_offset 28 + 538 @ sp needed + 539 00da BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 540 .LVL52: + 541 .L43: + 542 .LCFI9: + 543 .cfi_restore_state + 245:Core/Src/printf.c **** if (len && (base == 16U)) { + 544 .loc 1 245 10 view .LVU138 + 545 00de 6446 mov r4, ip + 546 00e0 D8E7 b .L36 + 547 .LVL53: + 548 .L45: + 250:Core/Src/printf.c **** buf[len++] = 'x'; + 549 .loc 1 250 23 discriminator 1 view .LVU139 + 550 00e2 16F0200F tst r6, #32 + 551 00e6 D8D1 bne .L37 + 250:Core/Src/printf.c **** buf[len++] = 'x'; + 552 .loc 1 250 53 discriminator 2 view .LVU140 + 553 00e8 1F2C cmp r4, #31 + 554 00ea D6D8 bhi .L37 + 251:Core/Src/printf.c **** } + 555 .loc 1 251 7 is_stmt 1 view .LVU141 + 556 .LVL54: + 251:Core/Src/printf.c **** } + 557 .loc 1 251 18 is_stmt 0 view .LVU142 + 558 00ec 7827 movs r7, #120 + 559 00ee 2F55 strb r7, [r5, r4] + 251:Core/Src/printf.c **** } + 560 .loc 1 251 14 view .LVU143 + 561 00f0 0134 adds r4, r4, #1 + 562 .LVL55: + 251:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 16 + + + 563 .loc 1 251 18 view .LVU144 + 564 00f2 DDE7 b .L38 + 565 .L46: + 253:Core/Src/printf.c **** buf[len++] = 'X'; + 566 .loc 1 253 28 discriminator 1 view .LVU145 + 567 00f4 16F0200F tst r6, #32 + 568 00f8 D2D0 beq .L39 + 253:Core/Src/printf.c **** buf[len++] = 'X'; + 569 .loc 1 253 57 discriminator 2 view .LVU146 + 570 00fa 1F2C cmp r4, #31 + 571 00fc D0D8 bhi .L39 + 254:Core/Src/printf.c **** } + 572 .loc 1 254 7 is_stmt 1 view .LVU147 + 573 .LVL56: + 254:Core/Src/printf.c **** } + 574 .loc 1 254 18 is_stmt 0 view .LVU148 + 575 00fe 5827 movs r7, #88 + 576 0100 2F55 strb r7, [r5, r4] + 254:Core/Src/printf.c **** } + 577 .loc 1 254 14 view .LVU149 + 578 0102 0134 adds r4, r4, #1 + 579 .LVL57: + 254:Core/Src/printf.c **** } + 580 .loc 1 254 18 view .LVU150 + 581 0104 D4E7 b .L38 + 582 .L41: + 268:Core/Src/printf.c **** buf[len++] = '+'; // ignore the space if the '+' exists + 583 .loc 1 268 10 is_stmt 1 view .LVU151 + 268:Core/Src/printf.c **** buf[len++] = '+'; // ignore the space if the '+' exists + 584 .loc 1 268 13 is_stmt 0 view .LVU152 + 585 0106 16F0040F tst r6, #4 + 586 010a 03D0 beq .L42 + 269:Core/Src/printf.c **** } + 587 .loc 1 269 7 is_stmt 1 view .LVU153 + 588 .LVL58: + 269:Core/Src/printf.c **** } + 589 .loc 1 269 18 is_stmt 0 view .LVU154 + 590 010c 2B27 movs r7, #43 + 591 010e 2F55 strb r7, [r5, r4] + 269:Core/Src/printf.c **** } + 592 .loc 1 269 14 view .LVU155 + 593 0110 0134 adds r4, r4, #1 + 594 .LVL59: + 269:Core/Src/printf.c **** } + 595 .loc 1 269 14 view .LVU156 + 596 0112 DAE7 b .L40 + 597 .L42: + 271:Core/Src/printf.c **** buf[len++] = ' '; + 598 .loc 1 271 10 is_stmt 1 view .LVU157 + 271:Core/Src/printf.c **** buf[len++] = ' '; + 599 .loc 1 271 13 is_stmt 0 view .LVU158 + 600 0114 16F0080F tst r6, #8 + 601 0118 D7D0 beq .L40 + 272:Core/Src/printf.c **** } + 602 .loc 1 272 7 is_stmt 1 view .LVU159 + 603 .LVL60: + 272:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 17 + + + 604 .loc 1 272 18 is_stmt 0 view .LVU160 + 605 011a 2027 movs r7, #32 + 606 011c 2F55 strb r7, [r5, r4] + 272:Core/Src/printf.c **** } + 607 .loc 1 272 14 view .LVU161 + 608 011e 0134 adds r4, r4, #1 + 609 .LVL61: + 272:Core/Src/printf.c **** } + 610 .loc 1 272 14 view .LVU162 + 611 0120 D3E7 b .L40 + 612 .cfi_endproc + 613 .LFE8: + 615 .section .text._ntoa_long,"ax",%progbits + 616 .align 1 + 617 .syntax unified + 618 .thumb + 619 .thumb_func + 620 .fpu fpv5-d16 + 622 _ntoa_long: + 623 .LVL62: + 624 .LFB9: + 278:Core/Src/printf.c **** + 279:Core/Src/printf.c **** + 280:Core/Src/printf.c **** // internal itoa for 'long' type + 281:Core/Src/printf.c **** static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long v + 282:Core/Src/printf.c **** { + 625 .loc 1 282 1 is_stmt 1 view -0 + 626 .cfi_startproc + 627 @ args = 24, pretend = 0, frame = 32 + 628 @ frame_needed = 0, uses_anonymous_args = 0 + 629 .loc 1 282 1 is_stmt 0 view .LVU164 + 630 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 631 .LCFI10: + 632 .cfi_def_cfa_offset 24 + 633 .cfi_offset 4, -24 + 634 .cfi_offset 5, -20 + 635 .cfi_offset 6, -16 + 636 .cfi_offset 7, -12 + 637 .cfi_offset 8, -8 + 638 .cfi_offset 14, -4 + 639 0004 90B0 sub sp, sp, #64 + 640 .LCFI11: + 641 .cfi_def_cfa_offset 88 + 642 0006 169C ldr r4, [sp, #88] + 643 0008 189D ldr r5, [sp, #96] + 644 000a 1B9E ldr r6, [sp, #108] + 283:Core/Src/printf.c **** char buf[PRINTF_NTOA_BUFFER_SIZE]; + 645 .loc 1 283 3 is_stmt 1 view .LVU165 + 284:Core/Src/printf.c **** size_t len = 0U; + 646 .loc 1 284 3 view .LVU166 + 647 .LVL63: + 285:Core/Src/printf.c **** + 286:Core/Src/printf.c **** // no hash for 0 values + 287:Core/Src/printf.c **** if (!value) { + 648 .loc 1 287 3 view .LVU167 + 649 .loc 1 287 6 is_stmt 0 view .LVU168 + 650 000c 0CB9 cbnz r4, .L48 + ARM GAS /tmp/ccibzHy5.s page 18 + + + 288:Core/Src/printf.c **** flags &= ~FLAGS_HASH; + 651 .loc 1 288 5 is_stmt 1 view .LVU169 + 652 .loc 1 288 11 is_stmt 0 view .LVU170 + 653 000e 26F01006 bic r6, r6, #16 + 654 .LVL64: + 655 .L48: + 289:Core/Src/printf.c **** } + 290:Core/Src/printf.c **** + 291:Core/Src/printf.c **** // write if precision != 0 and value is != 0 + 292:Core/Src/printf.c **** if (!(flags & FLAGS_PRECISION) || value) { + 656 .loc 1 292 3 is_stmt 1 view .LVU171 + 657 .loc 1 292 6 is_stmt 0 view .LVU172 + 658 0012 16F4806E ands lr, r6, #1024 + 659 0016 1AD0 beq .L54 + 660 .loc 1 292 34 discriminator 1 view .LVU173 + 661 0018 84B3 cbz r4, .L55 + 662 001a 4FF0000E mov lr, #0 + 663 001e 16E0 b .L54 + 664 .LVL65: + 665 .L59: + 666 .LBB24: + 293:Core/Src/printf.c **** do { + 294:Core/Src/printf.c **** const char digit = (char)(value % base); + 295:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 667 .loc 1 295 18 discriminator 1 view .LVU174 + 668 0020 0CF1300C add ip, ip, #48 + 669 .LVL66: + 670 .loc 1 295 18 discriminator 1 view .LVU175 + 671 0024 5FFA8CFC uxtb ip, ip + 672 .LVL67: + 673 .L52: + 674 .loc 1 295 14 discriminator 8 view .LVU176 + 675 0028 0EF10107 add r7, lr, #1 + 676 .LVL68: + 677 .loc 1 295 18 discriminator 8 view .LVU177 + 678 002c 0DF14008 add r8, sp, #64 + 679 0030 C644 add lr, lr, r8 + 680 0032 0EF820CC strb ip, [lr, #-32] + 296:Core/Src/printf.c **** value /= base; + 681 .loc 1 296 7 is_stmt 1 discriminator 8 view .LVU178 + 682 .loc 1 296 13 is_stmt 0 discriminator 8 view .LVU179 + 683 0036 B4FBF5FC udiv ip, r4, r5 + 684 .LVL69: + 685 .loc 1 296 13 discriminator 8 view .LVU180 + 686 .LBE24: + 297:Core/Src/printf.c **** } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); + 687 .loc 1 297 13 is_stmt 1 discriminator 8 view .LVU181 + 688 .loc 1 297 20 is_stmt 0 discriminator 8 view .LVU182 + 689 003a AC42 cmp r4, r5 + 690 003c 34BF ite cc + 691 003e 0024 movcc r4, #0 + 692 .LVL70: + 693 .loc 1 297 20 discriminator 8 view .LVU183 + 694 0040 0124 movcs r4, #1 + 695 0042 1F2F cmp r7, #31 + 696 0044 88BF it hi + 697 0046 0024 movhi r4, #0 + ARM GAS /tmp/ccibzHy5.s page 19 + + + 698 .loc 1 297 5 discriminator 8 view .LVU184 + 699 0048 CCB1 cbz r4, .L50 + 700 .LBB25: + 295:Core/Src/printf.c **** value /= base; + 701 .loc 1 295 14 view .LVU185 + 702 004a BE46 mov lr, r7 + 296:Core/Src/printf.c **** value /= base; + 703 .loc 1 296 13 view .LVU186 + 704 004c 6446 mov r4, ip + 705 .LVL71: + 706 .L54: + 296:Core/Src/printf.c **** value /= base; + 707 .loc 1 296 13 view .LVU187 + 708 .LBE25: + 293:Core/Src/printf.c **** const char digit = (char)(value % base); + 709 .loc 1 293 5 is_stmt 1 view .LVU188 + 710 .LBB26: + 294:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 711 .loc 1 294 7 view .LVU189 + 294:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 712 .loc 1 294 39 is_stmt 0 view .LVU190 + 713 004e B4FBF5FC udiv ip, r4, r5 + 714 0052 05FB1C4C mls ip, r5, ip, r4 + 294:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 715 .loc 1 294 18 view .LVU191 + 716 0056 5FFA8CFC uxtb ip, ip + 717 .LVL72: + 295:Core/Src/printf.c **** value /= base; + 718 .loc 1 295 7 is_stmt 1 view .LVU192 + 295:Core/Src/printf.c **** value /= base; + 719 .loc 1 295 18 is_stmt 0 view .LVU193 + 720 005a BCF1090F cmp ip, #9 + 721 005e DFD9 bls .L59 + 295:Core/Src/printf.c **** value /= base; + 722 .loc 1 295 85 discriminator 2 view .LVU194 + 723 0060 16F0200F tst r6, #32 + 724 0064 08D0 beq .L56 + 295:Core/Src/printf.c **** value /= base; + 725 .loc 1 295 85 view .LVU195 + 726 0066 4127 movs r7, #65 + 727 .L53: + 295:Core/Src/printf.c **** value /= base; + 728 .loc 1 295 85 discriminator 7 view .LVU196 + 729 0068 BC44 add ip, ip, r7 + 730 .LVL73: + 295:Core/Src/printf.c **** value /= base; + 731 .loc 1 295 85 discriminator 7 view .LVU197 + 732 006a 5FFA8CFC uxtb ip, ip + 295:Core/Src/printf.c **** value /= base; + 733 .loc 1 295 18 discriminator 7 view .LVU198 + 734 006e ACF10A0C sub ip, ip, #10 + 735 0072 5FFA8CFC uxtb ip, ip + 736 0076 D7E7 b .L52 + 737 .LVL74: + 738 .L56: + 295:Core/Src/printf.c **** value /= base; + 739 .loc 1 295 85 view .LVU199 + ARM GAS /tmp/ccibzHy5.s page 20 + + + 740 0078 6127 movs r7, #97 + 741 007a F5E7 b .L53 + 742 .LVL75: + 743 .L55: + 295:Core/Src/printf.c **** value /= base; + 744 .loc 1 295 85 view .LVU200 + 745 .LBE26: + 284:Core/Src/printf.c **** + 746 .loc 1 284 10 view .LVU201 + 747 007c 2746 mov r7, r4 + 748 .LVL76: + 749 .L50: + 298:Core/Src/printf.c **** } + 299:Core/Src/printf.c **** + 300:Core/Src/printf.c **** return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width + 750 .loc 1 300 3 is_stmt 1 view .LVU202 + 751 .loc 1 300 10 is_stmt 0 view .LVU203 + 752 007e 0696 str r6, [sp, #24] + 753 0080 1A9C ldr r4, [sp, #104] + 754 0082 0594 str r4, [sp, #20] + 755 0084 199C ldr r4, [sp, #100] + 756 0086 0494 str r4, [sp, #16] + 757 0088 0395 str r5, [sp, #12] + 758 008a 9DF85C40 ldrb r4, [sp, #92] @ zero_extendqisi2 + 759 008e 0294 str r4, [sp, #8] + 760 0090 0197 str r7, [sp, #4] + 761 0092 08AC add r4, sp, #32 + 762 0094 0094 str r4, [sp] + 763 0096 FFF7FEFF bl _ntoa_format + 764 .LVL77: + 301:Core/Src/printf.c **** } + 765 .loc 1 301 1 view .LVU204 + 766 009a 10B0 add sp, sp, #64 + 767 .LCFI12: + 768 .cfi_def_cfa_offset 24 + 769 @ sp needed + 770 009c BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 771 .loc 1 301 1 view .LVU205 + 772 .cfi_endproc + 773 .LFE9: + 775 .global __aeabi_uldivmod + 776 .section .text._ntoa_long_long,"ax",%progbits + 777 .align 1 + 778 .syntax unified + 779 .thumb + 780 .thumb_func + 781 .fpu fpv5-d16 + 783 _ntoa_long_long: + 784 .LVL78: + 785 .LFB10: + 302:Core/Src/printf.c **** + 303:Core/Src/printf.c **** + 304:Core/Src/printf.c **** // internal itoa for 'long long' type + 305:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 306:Core/Src/printf.c **** static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned l + 307:Core/Src/printf.c **** { + 786 .loc 1 307 1 is_stmt 1 view -0 + ARM GAS /tmp/ccibzHy5.s page 21 + + + 787 .cfi_startproc + 788 @ args = 36, pretend = 0, frame = 48 + 789 @ frame_needed = 0, uses_anonymous_args = 0 + 790 .loc 1 307 1 is_stmt 0 view .LVU207 + 791 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 792 .LCFI13: + 793 .cfi_def_cfa_offset 36 + 794 .cfi_offset 4, -36 + 795 .cfi_offset 5, -32 + 796 .cfi_offset 6, -28 + 797 .cfi_offset 7, -24 + 798 .cfi_offset 8, -20 + 799 .cfi_offset 9, -16 + 800 .cfi_offset 10, -12 + 801 .cfi_offset 11, -8 + 802 .cfi_offset 14, -4 + 803 0004 95B0 sub sp, sp, #84 + 804 .LCFI14: + 805 .cfi_def_cfa_offset 120 + 806 0006 0990 str r0, [sp, #36] + 807 0008 0A91 str r1, [sp, #40] + 808 000a 0B92 str r2, [sp, #44] + 809 000c 9B46 mov fp, r3 + 810 000e 1E9D ldr r5, [sp, #120] + 811 0010 1F9E ldr r6, [sp, #124] + 812 0012 229F ldr r7, [sp, #136] + 813 0014 DDF88C80 ldr r8, [sp, #140] + 814 0018 DDF898A0 ldr r10, [sp, #152] + 308:Core/Src/printf.c **** char buf[PRINTF_NTOA_BUFFER_SIZE]; + 815 .loc 1 308 3 is_stmt 1 view .LVU208 + 309:Core/Src/printf.c **** size_t len = 0U; + 816 .loc 1 309 3 view .LVU209 + 817 .LVL79: + 310:Core/Src/printf.c **** + 311:Core/Src/printf.c **** // no hash for 0 values + 312:Core/Src/printf.c **** if (!value) { + 818 .loc 1 312 3 view .LVU210 + 819 .loc 1 312 6 is_stmt 0 view .LVU211 + 820 001c 55EA0603 orrs r3, r5, r6 + 821 .LVL80: + 822 .loc 1 312 6 view .LVU212 + 823 0020 01D1 bne .L61 + 313:Core/Src/printf.c **** flags &= ~FLAGS_HASH; + 824 .loc 1 313 5 is_stmt 1 view .LVU213 + 825 .loc 1 313 11 is_stmt 0 view .LVU214 + 826 0022 2AF0100A bic r10, r10, #16 + 827 .LVL81: + 828 .L61: + 314:Core/Src/printf.c **** } + 315:Core/Src/printf.c **** + 316:Core/Src/printf.c **** // write if precision != 0 and value is != 0 + 317:Core/Src/printf.c **** if (!(flags & FLAGS_PRECISION) || value) { + 829 .loc 1 317 3 is_stmt 1 view .LVU215 + 830 .loc 1 317 6 is_stmt 0 view .LVU216 + 831 0026 1AF48064 ands r4, r10, #1024 + 832 002a 23D0 beq .L67 + 833 .loc 1 317 34 discriminator 1 view .LVU217 + ARM GAS /tmp/ccibzHy5.s page 22 + + + 834 002c 55EA0603 orrs r3, r5, r6 + 835 0030 34D0 beq .L68 + 836 0032 0024 movs r4, #0 + 837 0034 1EE0 b .L67 + 838 .LVL82: + 839 .L73: + 840 .LBB27: + 318:Core/Src/printf.c **** do { + 319:Core/Src/printf.c **** const char digit = (char)(value % base); + 320:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 841 .loc 1 320 18 discriminator 1 view .LVU218 + 842 0036 03F13002 add r2, r3, #48 + 843 003a D2B2 uxtb r2, r2 + 844 .L65: + 845 .loc 1 320 14 discriminator 8 view .LVU219 + 846 003c 04F10109 add r9, r4, #1 + 847 .LVL83: + 848 .loc 1 320 18 discriminator 8 view .LVU220 + 849 0040 14AB add r3, sp, #80 + 850 .LVL84: + 851 .loc 1 320 18 discriminator 8 view .LVU221 + 852 0042 1C44 add r4, r4, r3 + 853 0044 04F8202C strb r2, [r4, #-32] + 321:Core/Src/printf.c **** value /= base; + 854 .loc 1 321 7 is_stmt 1 discriminator 8 view .LVU222 + 855 .loc 1 321 13 is_stmt 0 discriminator 8 view .LVU223 + 856 0048 3A46 mov r2, r7 + 857 004a 4346 mov r3, r8 + 858 004c 2846 mov r0, r5 + 859 004e 3146 mov r1, r6 + 860 0050 FFF7FEFF bl __aeabi_uldivmod + 861 .LVL85: + 862 .loc 1 321 13 discriminator 8 view .LVU224 + 863 .LBE27: + 322:Core/Src/printf.c **** } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); + 864 .loc 1 322 13 is_stmt 1 discriminator 8 view .LVU225 + 865 .loc 1 322 14 is_stmt 0 discriminator 8 view .LVU226 + 866 0054 BD42 cmp r5, r7 + 867 0056 76EB0803 sbcs r3, r6, r8 + 868 005a 2CBF ite cs + 869 005c 0123 movcs r3, #1 + 870 005e 0023 movcc r3, #0 + 871 .loc 1 322 20 discriminator 8 view .LVU227 + 872 0060 B9F11F0F cmp r9, #31 + 873 0064 8CBF ite hi + 874 0066 0023 movhi r3, #0 + 875 0068 03F00103 andls r3, r3, #1 + 876 .loc 1 322 5 discriminator 8 view .LVU228 + 877 006c C3B1 cbz r3, .L63 + 878 .LBB28: + 320:Core/Src/printf.c **** value /= base; + 879 .loc 1 320 14 view .LVU229 + 880 006e 4C46 mov r4, r9 + 321:Core/Src/printf.c **** value /= base; + 881 .loc 1 321 13 view .LVU230 + 882 0070 0546 mov r5, r0 + 883 0072 0E46 mov r6, r1 + ARM GAS /tmp/ccibzHy5.s page 23 + + + 884 .LVL86: + 885 .L67: + 321:Core/Src/printf.c **** value /= base; + 886 .loc 1 321 13 view .LVU231 + 887 .LBE28: + 318:Core/Src/printf.c **** const char digit = (char)(value % base); + 888 .loc 1 318 5 is_stmt 1 view .LVU232 + 889 .LBB29: + 319:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 890 .loc 1 319 7 view .LVU233 + 319:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 891 .loc 1 319 39 is_stmt 0 view .LVU234 + 892 0074 3A46 mov r2, r7 + 893 0076 4346 mov r3, r8 + 894 0078 2846 mov r0, r5 + 895 007a 3146 mov r1, r6 + 896 007c FFF7FEFF bl __aeabi_uldivmod + 897 .LVL87: + 319:Core/Src/printf.c **** buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + 898 .loc 1 319 18 view .LVU235 + 899 0080 D3B2 uxtb r3, r2 + 900 .LVL88: + 320:Core/Src/printf.c **** value /= base; + 901 .loc 1 320 7 is_stmt 1 view .LVU236 + 320:Core/Src/printf.c **** value /= base; + 902 .loc 1 320 18 is_stmt 0 view .LVU237 + 903 0082 092B cmp r3, #9 + 904 0084 D7D9 bls .L73 + 320:Core/Src/printf.c **** value /= base; + 905 .loc 1 320 85 discriminator 2 view .LVU238 + 906 0086 1AF0200F tst r10, #32 + 907 008a 05D0 beq .L69 + 320:Core/Src/printf.c **** value /= base; + 908 .loc 1 320 85 view .LVU239 + 909 008c 4122 movs r2, #65 + 910 .L66: + 320:Core/Src/printf.c **** value /= base; + 911 .loc 1 320 85 discriminator 7 view .LVU240 + 912 008e 1A44 add r2, r2, r3 + 913 0090 D2B2 uxtb r2, r2 + 320:Core/Src/printf.c **** value /= base; + 914 .loc 1 320 18 discriminator 7 view .LVU241 + 915 0092 0A3A subs r2, r2, #10 + 916 0094 D2B2 uxtb r2, r2 + 917 0096 D1E7 b .L65 + 918 .L69: + 320:Core/Src/printf.c **** value /= base; + 919 .loc 1 320 85 view .LVU242 + 920 0098 6122 movs r2, #97 + 921 009a F8E7 b .L66 + 922 .LVL89: + 923 .L68: + 320:Core/Src/printf.c **** value /= base; + 924 .loc 1 320 85 view .LVU243 + 925 .LBE29: + 309:Core/Src/printf.c **** + 926 .loc 1 309 10 view .LVU244 + ARM GAS /tmp/ccibzHy5.s page 24 + + + 927 009c 4FF00009 mov r9, #0 + 928 .LVL90: + 929 .L63: + 323:Core/Src/printf.c **** } + 324:Core/Src/printf.c **** + 325:Core/Src/printf.c **** return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width + 930 .loc 1 325 3 is_stmt 1 view .LVU245 + 931 .loc 1 325 10 is_stmt 0 view .LVU246 + 932 00a0 CDF818A0 str r10, [sp, #24] + 933 00a4 259B ldr r3, [sp, #148] + 934 00a6 0593 str r3, [sp, #20] + 935 00a8 249B ldr r3, [sp, #144] + 936 00aa 0493 str r3, [sp, #16] + 937 00ac 0397 str r7, [sp, #12] + 938 00ae 9DF88030 ldrb r3, [sp, #128] @ zero_extendqisi2 + 939 00b2 0293 str r3, [sp, #8] + 940 00b4 CDF80490 str r9, [sp, #4] + 941 00b8 0CAB add r3, sp, #48 + 942 00ba 0093 str r3, [sp] + 943 00bc 5B46 mov r3, fp + 944 00be 0B9A ldr r2, [sp, #44] + 945 00c0 0A99 ldr r1, [sp, #40] + 946 00c2 0998 ldr r0, [sp, #36] + 947 00c4 FFF7FEFF bl _ntoa_format + 948 .LVL91: + 326:Core/Src/printf.c **** } + 949 .loc 1 326 1 view .LVU247 + 950 00c8 15B0 add sp, sp, #84 + 951 .LCFI15: + 952 .cfi_def_cfa_offset 36 + 953 @ sp needed + 954 00ca BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 955 .loc 1 326 1 view .LVU248 + 956 .cfi_endproc + 957 .LFE10: + 959 .section .text._etoa,"ax",%progbits + 960 .align 1 + 961 .syntax unified + 962 .thumb + 963 .thumb_func + 964 .fpu fpv5-d16 + 966 _etoa: + 967 .LVL92: + 968 .LFB12: + 327:Core/Src/printf.c **** #endif // PRINTF_SUPPORT_LONG_LONG + 328:Core/Src/printf.c **** + 329:Core/Src/printf.c **** + 330:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_FLOAT) + 331:Core/Src/printf.c **** + 332:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 333:Core/Src/printf.c **** // forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT + 334:Core/Src/printf.c **** static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsign + 335:Core/Src/printf.c **** #endif + 336:Core/Src/printf.c **** + 337:Core/Src/printf.c **** + 338:Core/Src/printf.c **** // internal ftoa for fixed decimal floating point + 339:Core/Src/printf.c **** static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsign + ARM GAS /tmp/ccibzHy5.s page 25 + + + 340:Core/Src/printf.c **** { + 341:Core/Src/printf.c **** char buf[PRINTF_FTOA_BUFFER_SIZE]; + 342:Core/Src/printf.c **** size_t len = 0U; + 343:Core/Src/printf.c **** double diff = 0.0; + 344:Core/Src/printf.c **** + 345:Core/Src/printf.c **** // powers of 10 + 346:Core/Src/printf.c **** static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 10 + 347:Core/Src/printf.c **** + 348:Core/Src/printf.c **** // test for special values + 349:Core/Src/printf.c **** if (value != value) + 350:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); + 351:Core/Src/printf.c **** if (value < -DBL_MAX) + 352:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); + 353:Core/Src/printf.c **** if (value > DBL_MAX) + 354:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS + 355:Core/Src/printf.c **** + 356:Core/Src/printf.c **** // test for very large values + 357:Core/Src/printf.c **** // standard printf behavior is to print EVERY whole number digit -- which could be 100s of charac + 358:Core/Src/printf.c **** if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) { + 359:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 360:Core/Src/printf.c **** return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); + 361:Core/Src/printf.c **** #else + 362:Core/Src/printf.c **** return 0U; + 363:Core/Src/printf.c **** #endif + 364:Core/Src/printf.c **** } + 365:Core/Src/printf.c **** + 366:Core/Src/printf.c **** // test for negative + 367:Core/Src/printf.c **** bool negative = false; + 368:Core/Src/printf.c **** if (value < 0) { + 369:Core/Src/printf.c **** negative = true; + 370:Core/Src/printf.c **** value = 0 - value; + 371:Core/Src/printf.c **** } + 372:Core/Src/printf.c **** + 373:Core/Src/printf.c **** // set default precision, if not set explicitly + 374:Core/Src/printf.c **** if (!(flags & FLAGS_PRECISION)) { + 375:Core/Src/printf.c **** prec = PRINTF_DEFAULT_FLOAT_PRECISION; + 376:Core/Src/printf.c **** } + 377:Core/Src/printf.c **** // limit precision to 9, cause a prec >= 10 can lead to overflow errors + 378:Core/Src/printf.c **** while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { + 379:Core/Src/printf.c **** buf[len++] = '0'; + 380:Core/Src/printf.c **** prec--; + 381:Core/Src/printf.c **** } + 382:Core/Src/printf.c **** + 383:Core/Src/printf.c **** int whole = (int)value; + 384:Core/Src/printf.c **** double tmp = (value - whole) * pow10[prec]; + 385:Core/Src/printf.c **** unsigned long frac = (unsigned long)tmp; + 386:Core/Src/printf.c **** diff = tmp - frac; + 387:Core/Src/printf.c **** + 388:Core/Src/printf.c **** if (diff > 0.5) { + 389:Core/Src/printf.c **** ++frac; + 390:Core/Src/printf.c **** // handle rollover, e.g. case 0.99 with prec 1 is 1.0 + 391:Core/Src/printf.c **** if (frac >= pow10[prec]) { + 392:Core/Src/printf.c **** frac = 0; + 393:Core/Src/printf.c **** ++whole; + 394:Core/Src/printf.c **** } + 395:Core/Src/printf.c **** } + 396:Core/Src/printf.c **** else if (diff < 0.5) { + ARM GAS /tmp/ccibzHy5.s page 26 + + + 397:Core/Src/printf.c **** } + 398:Core/Src/printf.c **** else if ((frac == 0U) || (frac & 1U)) { + 399:Core/Src/printf.c **** // if halfway, round up if odd OR if last digit is 0 + 400:Core/Src/printf.c **** ++frac; + 401:Core/Src/printf.c **** } + 402:Core/Src/printf.c **** + 403:Core/Src/printf.c **** if (prec == 0U) { + 404:Core/Src/printf.c **** diff = value - (double)whole; + 405:Core/Src/printf.c **** if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + 406:Core/Src/printf.c **** // exactly 0.5 and ODD, then round up + 407:Core/Src/printf.c **** // 1.5 -> 2, but 2.5 -> 2 + 408:Core/Src/printf.c **** ++whole; + 409:Core/Src/printf.c **** } + 410:Core/Src/printf.c **** } + 411:Core/Src/printf.c **** else { + 412:Core/Src/printf.c **** unsigned int count = prec; + 413:Core/Src/printf.c **** // now do fractional part, as an unsigned number + 414:Core/Src/printf.c **** while (len < PRINTF_FTOA_BUFFER_SIZE) { + 415:Core/Src/printf.c **** --count; + 416:Core/Src/printf.c **** buf[len++] = (char)(48U + (frac % 10U)); + 417:Core/Src/printf.c **** if (!(frac /= 10U)) { + 418:Core/Src/printf.c **** break; + 419:Core/Src/printf.c **** } + 420:Core/Src/printf.c **** } + 421:Core/Src/printf.c **** // add extra 0s + 422:Core/Src/printf.c **** while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { + 423:Core/Src/printf.c **** buf[len++] = '0'; + 424:Core/Src/printf.c **** } + 425:Core/Src/printf.c **** if (len < PRINTF_FTOA_BUFFER_SIZE) { + 426:Core/Src/printf.c **** // add decimal + 427:Core/Src/printf.c **** buf[len++] = '.'; + 428:Core/Src/printf.c **** } + 429:Core/Src/printf.c **** } + 430:Core/Src/printf.c **** + 431:Core/Src/printf.c **** // do whole part, number is reversed + 432:Core/Src/printf.c **** while (len < PRINTF_FTOA_BUFFER_SIZE) { + 433:Core/Src/printf.c **** buf[len++] = (char)(48 + (whole % 10)); + 434:Core/Src/printf.c **** if (!(whole /= 10)) { + 435:Core/Src/printf.c **** break; + 436:Core/Src/printf.c **** } + 437:Core/Src/printf.c **** } + 438:Core/Src/printf.c **** + 439:Core/Src/printf.c **** // pad leading zeros + 440:Core/Src/printf.c **** if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { + 441:Core/Src/printf.c **** if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + 442:Core/Src/printf.c **** width--; + 443:Core/Src/printf.c **** } + 444:Core/Src/printf.c **** while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) { + 445:Core/Src/printf.c **** buf[len++] = '0'; + 446:Core/Src/printf.c **** } + 447:Core/Src/printf.c **** } + 448:Core/Src/printf.c **** + 449:Core/Src/printf.c **** if (len < PRINTF_FTOA_BUFFER_SIZE) { + 450:Core/Src/printf.c **** if (negative) { + 451:Core/Src/printf.c **** buf[len++] = '-'; + 452:Core/Src/printf.c **** } + 453:Core/Src/printf.c **** else if (flags & FLAGS_PLUS) { + ARM GAS /tmp/ccibzHy5.s page 27 + + + 454:Core/Src/printf.c **** buf[len++] = '+'; // ignore the space if the '+' exists + 455:Core/Src/printf.c **** } + 456:Core/Src/printf.c **** else if (flags & FLAGS_SPACE) { + 457:Core/Src/printf.c **** buf[len++] = ' '; + 458:Core/Src/printf.c **** } + 459:Core/Src/printf.c **** } + 460:Core/Src/printf.c **** + 461:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); + 462:Core/Src/printf.c **** } + 463:Core/Src/printf.c **** + 464:Core/Src/printf.c **** + 465:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 466:Core/Src/printf.c **** // internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse DBL_MAX) || (value < -DBL_MAX)) { + 998 .loc 1 470 3 is_stmt 1 view .LVU252 + 999 .loc 1 470 6 is_stmt 0 view .LVU253 + 1000 0018 B4EE400B vcmp.f64 d0, d0 + 1001 001c F1EE10FA vmrs APSR_nzcv, FPSCR + 1002 0020 40F0AC80 bne .L75 + 1003 .loc 1 470 24 discriminator 1 view .LVU254 + 1004 0024 9FED967B vldr.64 d7, .L116 + 1005 0028 B4EEC70B vcmpe.f64 d0, d7 + 1006 002c F1EE10FA vmrs APSR_nzcv, FPSCR + 1007 0030 00F3A480 bgt .L75 + 1008 .loc 1 470 45 discriminator 2 view .LVU255 + ARM GAS /tmp/ccibzHy5.s page 28 + + + 1009 0034 9FED947B vldr.64 d7, .L116+8 + 1010 0038 B4EEC70B vcmpe.f64 d0, d7 + 1011 003c F1EE10FA vmrs APSR_nzcv, FPSCR + 1012 0040 00F19C80 bmi .L75 + 471:Core/Src/printf.c **** return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); + 472:Core/Src/printf.c **** } + 473:Core/Src/printf.c **** + 474:Core/Src/printf.c **** // determine the sign + 475:Core/Src/printf.c **** const bool negative = value < 0; + 1013 .loc 1 475 3 is_stmt 1 view .LVU256 + 1014 .LVL94: + 476:Core/Src/printf.c **** if (negative) { + 1015 .loc 1 476 3 view .LVU257 + 1016 .loc 1 476 6 is_stmt 0 view .LVU258 + 1017 0044 B5EEC00B vcmpe.f64 d0, #0 + 1018 0048 F1EE10FA vmrs APSR_nzcv, FPSCR + 1019 004c 00F1A480 bmi .L114 + 1020 0050 B0EE405B vmov.f64 d5, d0 + 1021 .LVL95: + 1022 .L79: + 477:Core/Src/printf.c **** value = -value; + 478:Core/Src/printf.c **** } + 479:Core/Src/printf.c **** + 480:Core/Src/printf.c **** // default precision + 481:Core/Src/printf.c **** if (!(flags & FLAGS_PRECISION)) { + 1023 .loc 1 481 3 is_stmt 1 view .LVU259 + 1024 .loc 1 481 6 is_stmt 0 view .LVU260 + 1025 0054 19F48060 ands r0, r9, #1024 + 1026 .LVL96: + 1027 .loc 1 481 6 view .LVU261 + 1028 0058 00D1 bne .L81 + 482:Core/Src/printf.c **** prec = PRINTF_DEFAULT_FLOAT_PRECISION; + 1029 .loc 1 482 10 view .LVU262 + 1030 005a 0621 movs r1, #6 + 1031 .L81: + 1032 .LVL97: + 483:Core/Src/printf.c **** } + 484:Core/Src/printf.c **** + 485:Core/Src/printf.c **** // determine the decimal exponent + 486:Core/Src/printf.c **** // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) + 487:Core/Src/printf.c **** union { + 1033 .loc 1 487 3 is_stmt 1 view .LVU263 + 488:Core/Src/printf.c **** uint64_t U; + 489:Core/Src/printf.c **** double F; + 490:Core/Src/printf.c **** } conv; + 491:Core/Src/printf.c **** + 492:Core/Src/printf.c **** conv.F = value; + 1034 .loc 1 492 3 view .LVU264 + 493:Core/Src/printf.c **** int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 + 1035 .loc 1 493 3 view .LVU265 + 1036 005c 15EE902A vmov r2, s11 @ int + 1037 .LVL98: + 1038 .loc 1 493 14 is_stmt 0 view .LVU266 + 1039 0060 C2F30A53 ubfx r3, r2, #20, #11 + 1040 .LVL99: + 1041 .loc 1 493 7 view .LVU267 + 1042 0064 A3F2FF33 subw r3, r3, #1023 + ARM GAS /tmp/ccibzHy5.s page 29 + + + 1043 0068 07EE103A vmov s14, r3 @ int + 1044 .LVL100: + 494:Core/Src/printf.c **** conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is n + 1045 .loc 1 494 3 is_stmt 1 view .LVU268 + 1046 .loc 1 494 20 is_stmt 0 view .LVU269 + 1047 006c C2F3130E ubfx lr, r2, #0, #20 + 1048 .loc 1 494 44 view .LVU270 + 1049 0070 15EE102A vmov r2, s10 @ int + 1050 0074 4EF07F53 orr r3, lr, #1069547520 + 1051 .LVL101: + 1052 .loc 1 494 44 view .LVU271 + 1053 0078 43F44013 orr r3, r3, #3145728 + 495:Core/Src/printf.c **** // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 + 496:Core/Src/printf.c **** int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.28952965460216 + 1054 .loc 1 496 3 is_stmt 1 view .LVU272 + 1055 .loc 1 496 45 is_stmt 0 view .LVU273 + 1056 007c B8EEC77B vcvt.f64.s32 d7, s14 + 1057 .LVL102: + 1058 .loc 1 496 38 view .LVU274 + 1059 0080 9FED834B vldr.64 d4, .L116+16 + 1060 0084 9FED846B vldr.64 d6, .L116+24 + 1061 0088 07EE046B vmla.f64 d6, d7, d4 + 1062 .loc 1 496 75 view .LVU275 + 1063 008c B7EE087B vmov.f64 d7, #1.5e+0 + 1064 0090 43EC142B vmov d4, r2, r3 + 1065 0094 34EE477B vsub.f64 d7, d4, d7 + 1066 .loc 1 496 65 view .LVU276 + 1067 0098 9FED814B vldr.64 d4, .L116+32 + 1068 009c 07EE046B vmla.f64 d6, d7, d4 + 1069 .loc 1 496 7 view .LVU277 + 1070 00a0 FDEEC67B vcvt.s32.f64 s15, d6 + 1071 00a4 17EE908A vmov r8, s15 @ int + 1072 .LVL103: + 497:Core/Src/printf.c **** // now we want to compute 10^expval but we want to be sure it won't overflow + 498:Core/Src/printf.c **** exp2 = (int)(expval * 3.321928094887362 + 0.5); + 1073 .loc 1 498 3 is_stmt 1 view .LVU278 + 1074 .loc 1 498 23 is_stmt 0 view .LVU279 + 1075 00a8 B8EEE74B vcvt.f64.s32 d4, s15 + 1076 .loc 1 498 43 view .LVU280 + 1077 00ac 9FED7E6B vldr.64 d6, .L116+40 + 1078 00b0 B6EE007B vmov.f64 d7, #5.0e-1 + 1079 00b4 04EE067B vmla.f64 d7, d4, d6 + 1080 .loc 1 498 8 view .LVU281 + 1081 00b8 FDEEC76B vcvt.s32.f64 s13, d7 + 1082 .LVL104: + 499:Core/Src/printf.c **** const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; + 1083 .loc 1 499 3 is_stmt 1 view .LVU282 + 1084 .loc 1 499 55 is_stmt 0 view .LVU283 + 1085 00bc B8EEE67B vcvt.f64.s32 d7, s13 + 1086 00c0 9FED7B3B vldr.64 d3, .L116+48 + 1087 00c4 27EE037B vmul.f64 d7, d7, d3 + 1088 .loc 1 499 16 view .LVU284 + 1089 00c8 9FED7B3B vldr.64 d3, .L116+56 + 1090 00cc 14EE037B vnmls.f64 d7, d4, d3 + 1091 .LVL105: + 500:Core/Src/printf.c **** const double z2 = z * z; + 1092 .loc 1 500 3 is_stmt 1 view .LVU285 + ARM GAS /tmp/ccibzHy5.s page 30 + + + 1093 .loc 1 500 16 is_stmt 0 view .LVU286 + 1094 00d0 27EE074B vmul.f64 d4, d7, d7 + 1095 .LVL106: + 501:Core/Src/printf.c **** conv.U = (uint64_t)(exp2 + 1023) << 52U; + 1096 .loc 1 501 3 is_stmt 1 view .LVU287 + 1097 .loc 1 501 28 is_stmt 0 view .LVU288 + 1098 00d4 16EE903A vmov r3, s13 @ int + 1099 00d8 03F2FF33 addw r3, r3, #1023 + 1100 .loc 1 501 36 view .LVU289 + 1101 00dc 4FF0000B mov fp, #0 + 1102 00e0 4FEA035C lsl ip, r3, #20 + 502:Core/Src/printf.c **** // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_functi + 503:Core/Src/printf.c **** conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); + 1103 .loc 1 503 3 is_stmt 1 view .LVU290 + 1104 .loc 1 503 19 is_stmt 0 view .LVU291 + 1105 00e4 37EE073B vadd.f64 d3, d7, d7 + 1106 .loc 1 503 28 view .LVU292 + 1107 00e8 B0EE006B vmov.f64 d6, #2.0e+0 + 1108 00ec 36EE477B vsub.f64 d7, d6, d7 + 1109 .LVL107: + 1110 .loc 1 503 60 view .LVU293 + 1111 00f0 B2EE0C6B vmov.f64 d6, #1.4e+1 + 1112 00f4 84EE062B vdiv.f64 d2, d4, d6 + 1113 .loc 1 503 55 view .LVU294 + 1114 00f8 B2EE046B vmov.f64 d6, #1.0e+1 + 1115 00fc 32EE062B vadd.f64 d2, d2, d6 + 1116 .loc 1 503 49 view .LVU295 + 1117 0100 84EE026B vdiv.f64 d6, d4, d2 + 1118 .loc 1 503 43 view .LVU296 + 1119 0104 B1EE082B vmov.f64 d2, #6.0e+0 + 1120 0108 36EE026B vadd.f64 d6, d6, d2 + 1121 .loc 1 503 38 view .LVU297 + 1122 010c 84EE062B vdiv.f64 d2, d4, d6 + 1123 .loc 1 503 32 view .LVU298 + 1124 0110 37EE027B vadd.f64 d7, d7, d2 + 1125 .loc 1 503 23 view .LVU299 + 1126 0114 83EE076B vdiv.f64 d6, d3, d7 + 1127 .loc 1 503 15 view .LVU300 + 1128 0118 B7EE007B vmov.f64 d7, #1.0e+0 + 1129 011c 36EE077B vadd.f64 d7, d6, d7 + 1130 .loc 1 503 10 view .LVU301 + 1131 0120 4CEC16BB vmov d6, fp, ip + 1132 0124 27EE067B vmul.f64 d7, d7, d6 + 1133 0128 B0EE476B vmov.f64 d6, d7 @ int + 1134 .LVL108: + 504:Core/Src/printf.c **** // correct for rounding errors + 505:Core/Src/printf.c **** if (value < conv.F) { + 1135 .loc 1 505 3 is_stmt 1 view .LVU302 + 1136 .loc 1 505 6 is_stmt 0 view .LVU303 + 1137 012c B4EEC57B vcmpe.f64 d7, d5 + 1138 0130 F1EE10FA vmrs APSR_nzcv, FPSCR + 1139 0134 05DD ble .L82 + 506:Core/Src/printf.c **** expval--; + 1140 .loc 1 506 5 is_stmt 1 view .LVU304 + 1141 .loc 1 506 11 is_stmt 0 view .LVU305 + 1142 0136 08F1FF38 add r8, r8, #-1 + 1143 .LVL109: + ARM GAS /tmp/ccibzHy5.s page 31 + + + 507:Core/Src/printf.c **** conv.F /= 10; + 1144 .loc 1 507 5 is_stmt 1 view .LVU306 + 1145 .loc 1 507 12 is_stmt 0 view .LVU307 + 1146 013a B2EE044B vmov.f64 d4, #1.0e+1 + 1147 .LVL110: + 1148 .loc 1 507 12 view .LVU308 + 1149 013e 87EE046B vdiv.f64 d6, d7, d4 + 1150 .L82: + 508:Core/Src/printf.c **** } + 509:Core/Src/printf.c **** + 510:Core/Src/printf.c **** // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters + 511:Core/Src/printf.c **** unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; + 1151 .loc 1 511 3 is_stmt 1 view .LVU309 + 1152 .loc 1 511 43 is_stmt 0 view .LVU310 + 1153 0142 08F16303 add r3, r8, #99 + 1154 .loc 1 511 68 view .LVU311 + 1155 0146 C62B cmp r3, #198 + 1156 0148 29D8 bhi .L100 + 1157 .loc 1 511 68 view .LVU312 + 1158 014a 4FF0040B mov fp, #4 + 1159 .L84: + 1160 .LVL111: + 512:Core/Src/printf.c **** + 513:Core/Src/printf.c **** // in "%g" mode, "prec" is the number of *significant figures* not decimals + 514:Core/Src/printf.c **** if (flags & FLAGS_ADAPT_EXP) { + 1161 .loc 1 514 3 is_stmt 1 discriminator 4 view .LVU313 + 1162 .loc 1 514 6 is_stmt 0 discriminator 4 view .LVU314 + 1163 014e 19F4006F tst r9, #2048 + 1164 0152 2DD0 beq .L85 + 515:Core/Src/printf.c **** // do we want to fall-back to "%f" mode? + 516:Core/Src/printf.c **** if ((value >= 1e-4) && (value < 1e6)) { + 1165 .loc 1 516 5 is_stmt 1 view .LVU315 + 1166 .loc 1 516 8 is_stmt 0 view .LVU316 + 1167 0154 9FED5A7B vldr.64 d7, .L116+64 + 1168 0158 B4EEC75B vcmpe.f64 d5, d7 + 1169 015c F1EE10FA vmrs APSR_nzcv, FPSCR + 1170 0160 2BDB blt .L86 + 1171 .loc 1 516 25 discriminator 1 view .LVU317 + 1172 0162 9FED597B vldr.64 d7, .L116+72 + 1173 0166 B4EEC75B vcmpe.f64 d5, d7 + 1174 016a F1EE10FA vmrs APSR_nzcv, FPSCR + 1175 016e 24D5 bpl .L86 + 517:Core/Src/printf.c **** if ((int)prec > expval) { + 1176 .loc 1 517 7 is_stmt 1 view .LVU318 + 1177 .loc 1 517 10 is_stmt 0 view .LVU319 + 1178 0170 4145 cmp r1, r8 + 1179 0172 17DD ble .L101 + 518:Core/Src/printf.c **** prec = (unsigned)((int)prec - expval - 1); + 1180 .loc 1 518 9 is_stmt 1 view .LVU320 + 1181 .loc 1 518 37 is_stmt 0 view .LVU321 + 1182 0174 A1EB0801 sub r1, r1, r8 + 1183 .LVL112: + 1184 .loc 1 518 46 view .LVU322 + 1185 0178 0139 subs r1, r1, #1 + 1186 .LVL113: + 1187 .loc 1 518 46 view .LVU323 + 1188 017a 14E0 b .L89 + ARM GAS /tmp/ccibzHy5.s page 32 + + + 1189 .LVL114: + 1190 .L75: + 471:Core/Src/printf.c **** } + 1191 .loc 1 471 5 is_stmt 1 view .LVU324 + 471:Core/Src/printf.c **** } + 1192 .loc 1 471 12 is_stmt 0 view .LVU325 + 1193 017c CDF80890 str r9, [sp, #8] + 1194 0180 CDF804A0 str r10, [sp, #4] + 1195 0184 0091 str r1, [sp] + 1196 0186 3346 mov r3, r6 + 1197 .LVL115: + 471:Core/Src/printf.c **** } + 1198 .loc 1 471 12 view .LVU326 + 1199 0188 3A46 mov r2, r7 + 1200 .LVL116: + 471:Core/Src/printf.c **** } + 1201 .loc 1 471 12 view .LVU327 + 1202 018a 2946 mov r1, r5 + 1203 018c 2046 mov r0, r4 + 1204 .LVL117: + 471:Core/Src/printf.c **** } + 1205 .loc 1 471 12 view .LVU328 + 1206 018e FFF7FEFF bl _ftoa + 1207 .LVL118: + 1208 .L78: + 519:Core/Src/printf.c **** } + 520:Core/Src/printf.c **** else { + 521:Core/Src/printf.c **** prec = 0; + 522:Core/Src/printf.c **** } + 523:Core/Src/printf.c **** flags |= FLAGS_PRECISION; // make sure _ftoa respects precision + 524:Core/Src/printf.c **** // no characters in exponent + 525:Core/Src/printf.c **** minwidth = 0U; + 526:Core/Src/printf.c **** expval = 0; + 527:Core/Src/printf.c **** } + 528:Core/Src/printf.c **** else { + 529:Core/Src/printf.c **** // we use one sigfig for the whole part + 530:Core/Src/printf.c **** if ((prec > 0) && (flags & FLAGS_PRECISION)) { + 531:Core/Src/printf.c **** --prec; + 532:Core/Src/printf.c **** } + 533:Core/Src/printf.c **** } + 534:Core/Src/printf.c **** } + 535:Core/Src/printf.c **** + 536:Core/Src/printf.c **** // will everything fit? + 537:Core/Src/printf.c **** unsigned int fwidth = width; + 538:Core/Src/printf.c **** if (width > minwidth) { + 539:Core/Src/printf.c **** // we didn't fall-back so subtract the characters required for the exponent + 540:Core/Src/printf.c **** fwidth -= minwidth; + 541:Core/Src/printf.c **** } else { + 542:Core/Src/printf.c **** // not enough characters, so go back to default sizing + 543:Core/Src/printf.c **** fwidth = 0U; + 544:Core/Src/printf.c **** } + 545:Core/Src/printf.c **** if ((flags & FLAGS_LEFT) && minwidth) { + 546:Core/Src/printf.c **** // if we're padding on the right, DON'T pad the floating part + 547:Core/Src/printf.c **** fwidth = 0U; + 548:Core/Src/printf.c **** } + 549:Core/Src/printf.c **** + 550:Core/Src/printf.c **** // rescale the float value + ARM GAS /tmp/ccibzHy5.s page 33 + + + 551:Core/Src/printf.c **** if (expval) { + 552:Core/Src/printf.c **** value /= conv.F; + 553:Core/Src/printf.c **** } + 554:Core/Src/printf.c **** + 555:Core/Src/printf.c **** // output the floating part + 556:Core/Src/printf.c **** const size_t start_idx = idx; + 557:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADA + 558:Core/Src/printf.c **** + 559:Core/Src/printf.c **** // output the exponent part + 560:Core/Src/printf.c **** if (minwidth) { + 561:Core/Src/printf.c **** // output the exponential symbol + 562:Core/Src/printf.c **** out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); + 563:Core/Src/printf.c **** // output the exponent value + 564:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, + 565:Core/Src/printf.c **** // might need to right-pad spaces + 566:Core/Src/printf.c **** if (flags & FLAGS_LEFT) { + 567:Core/Src/printf.c **** while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); + 568:Core/Src/printf.c **** } + 569:Core/Src/printf.c **** } + 570:Core/Src/printf.c **** return idx; + 571:Core/Src/printf.c **** } + 1209 .loc 1 571 1 view .LVU329 + 1210 0192 09B0 add sp, sp, #36 + 1211 .LCFI18: + 1212 .cfi_remember_state + 1213 .cfi_def_cfa_offset 36 + 1214 @ sp needed + 1215 0194 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 1216 .LVL119: + 1217 .L114: + 1218 .LCFI19: + 1219 .cfi_restore_state + 477:Core/Src/printf.c **** } + 1220 .loc 1 477 5 is_stmt 1 view .LVU330 + 477:Core/Src/printf.c **** } + 1221 .loc 1 477 11 is_stmt 0 view .LVU331 + 1222 0198 B1EE405B vneg.f64 d5, d0 + 1223 .LVL120: + 477:Core/Src/printf.c **** } + 1224 .loc 1 477 11 view .LVU332 + 1225 019c 5AE7 b .L79 + 1226 .LVL121: + 1227 .L100: + 511:Core/Src/printf.c **** + 1228 .loc 1 511 68 view .LVU333 + 1229 019e 4FF0050B mov fp, #5 + 1230 01a2 D4E7 b .L84 + 1231 .LVL122: + 1232 .L101: + 521:Core/Src/printf.c **** } + 1233 .loc 1 521 14 view .LVU334 + 1234 01a4 0021 movs r1, #0 + 1235 .LVL123: + 1236 .L89: + 523:Core/Src/printf.c **** // no characters in exponent + 1237 .loc 1 523 7 is_stmt 1 view .LVU335 + 523:Core/Src/printf.c **** // no characters in exponent + ARM GAS /tmp/ccibzHy5.s page 34 + + + 1238 .loc 1 523 13 is_stmt 0 view .LVU336 + 1239 01a6 49F48069 orr r9, r9, #1024 + 1240 .LVL124: + 525:Core/Src/printf.c **** expval = 0; + 1241 .loc 1 525 7 is_stmt 1 view .LVU337 + 526:Core/Src/printf.c **** } + 1242 .loc 1 526 7 view .LVU338 + 525:Core/Src/printf.c **** expval = 0; + 1243 .loc 1 525 16 is_stmt 0 view .LVU339 + 1244 01aa 4FF0000B mov fp, #0 + 526:Core/Src/printf.c **** } + 1245 .loc 1 526 16 view .LVU340 + 1246 01ae D846 mov r8, fp + 1247 .LVL125: + 1248 .L85: + 537:Core/Src/printf.c **** if (width > minwidth) { + 1249 .loc 1 537 3 is_stmt 1 view .LVU341 + 538:Core/Src/printf.c **** // we didn't fall-back so subtract the characters required for the exponent + 1250 .loc 1 538 3 view .LVU342 + 538:Core/Src/printf.c **** // we didn't fall-back so subtract the characters required for the exponent + 1251 .loc 1 538 6 is_stmt 0 view .LVU343 + 1252 01b0 D345 cmp fp, r10 + 1253 01b2 08D2 bcs .L102 + 540:Core/Src/printf.c **** } else { + 1254 .loc 1 540 5 is_stmt 1 view .LVU344 + 540:Core/Src/printf.c **** } else { + 1255 .loc 1 540 12 is_stmt 0 view .LVU345 + 1256 01b4 AAEB0B03 sub r3, r10, fp + 1257 .LVL126: + 540:Core/Src/printf.c **** } else { + 1258 .loc 1 540 12 view .LVU346 + 1259 01b8 06E0 b .L90 + 1260 .LVL127: + 1261 .L86: + 530:Core/Src/printf.c **** --prec; + 1262 .loc 1 530 7 is_stmt 1 view .LVU347 + 530:Core/Src/printf.c **** --prec; + 1263 .loc 1 530 10 is_stmt 0 view .LVU348 + 1264 01ba 0029 cmp r1, #0 + 1265 01bc F8D0 beq .L85 + 530:Core/Src/printf.c **** --prec; + 1266 .loc 1 530 22 discriminator 1 view .LVU349 + 1267 01be 0028 cmp r0, #0 + 1268 01c0 F6D0 beq .L85 + 531:Core/Src/printf.c **** } + 1269 .loc 1 531 9 is_stmt 1 view .LVU350 + 1270 01c2 0139 subs r1, r1, #1 + 1271 .LVL128: + 531:Core/Src/printf.c **** } + 1272 .loc 1 531 9 is_stmt 0 view .LVU351 + 1273 01c4 F4E7 b .L85 + 1274 .LVL129: + 1275 .L102: + 543:Core/Src/printf.c **** } + 1276 .loc 1 543 12 view .LVU352 + 1277 01c6 0023 movs r3, #0 + 1278 .LVL130: + ARM GAS /tmp/ccibzHy5.s page 35 + + + 1279 .L90: + 545:Core/Src/printf.c **** // if we're padding on the right, DON'T pad the floating part + 1280 .loc 1 545 3 is_stmt 1 view .LVU353 + 545:Core/Src/printf.c **** // if we're padding on the right, DON'T pad the floating part + 1281 .loc 1 545 6 is_stmt 0 view .LVU354 + 1282 01c8 19F00202 ands r2, r9, #2 + 1283 01cc 0792 str r2, [sp, #28] + 1284 01ce 03D0 beq .L91 + 545:Core/Src/printf.c **** // if we're padding on the right, DON'T pad the floating part + 1285 .loc 1 545 28 discriminator 1 view .LVU355 + 1286 01d0 BBF1000F cmp fp, #0 + 1287 01d4 00D0 beq .L91 + 547:Core/Src/printf.c **** } + 1288 .loc 1 547 12 view .LVU356 + 1289 01d6 0023 movs r3, #0 + 1290 .LVL131: + 1291 .L91: + 551:Core/Src/printf.c **** value /= conv.F; + 1292 .loc 1 551 3 is_stmt 1 view .LVU357 + 551:Core/Src/printf.c **** value /= conv.F; + 1293 .loc 1 551 6 is_stmt 0 view .LVU358 + 1294 01d8 B8F1000F cmp r8, #0 + 1295 01dc 01D0 beq .L92 + 552:Core/Src/printf.c **** } + 1296 .loc 1 552 5 is_stmt 1 view .LVU359 + 552:Core/Src/printf.c **** } + 1297 .loc 1 552 11 is_stmt 0 view .LVU360 + 1298 01de 85EE065B vdiv.f64 d5, d5, d6 + 1299 .LVL132: + 1300 .L92: + 556:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADA + 1301 .loc 1 556 3 is_stmt 1 view .LVU361 + 557:Core/Src/printf.c **** + 1302 .loc 1 557 3 view .LVU362 + 557:Core/Src/printf.c **** + 1303 .loc 1 557 9 is_stmt 0 view .LVU363 + 1304 01e2 B5EEC00B vcmpe.f64 d0, #0 + 1305 01e6 F1EE10FA vmrs APSR_nzcv, FPSCR + 1306 01ea 37D4 bmi .L115 + 1307 .LVL133: + 1308 .L93: + 557:Core/Src/printf.c **** + 1309 .loc 1 557 9 discriminator 4 view .LVU364 + 1310 01ec 29F40062 bic r2, r9, #2048 + 1311 01f0 0292 str r2, [sp, #8] + 1312 01f2 0193 str r3, [sp, #4] + 1313 01f4 0091 str r1, [sp] + 1314 01f6 B0EE450B vmov.f64 d0, d5 + 1315 .LVL134: + 557:Core/Src/printf.c **** + 1316 .loc 1 557 9 discriminator 4 view .LVU365 + 1317 01fa 3346 mov r3, r6 + 1318 .LVL135: + 557:Core/Src/printf.c **** + 1319 .loc 1 557 9 discriminator 4 view .LVU366 + 1320 01fc 3A46 mov r2, r7 + 1321 01fe 2946 mov r1, r5 + ARM GAS /tmp/ccibzHy5.s page 36 + + + 1322 .LVL136: + 557:Core/Src/printf.c **** + 1323 .loc 1 557 9 discriminator 4 view .LVU367 + 1324 0200 2046 mov r0, r4 + 1325 0202 FFF7FEFF bl _ftoa + 1326 .LVL137: + 560:Core/Src/printf.c **** // output the exponential symbol + 1327 .loc 1 560 3 is_stmt 1 discriminator 4 view .LVU368 + 560:Core/Src/printf.c **** // output the exponential symbol + 1328 .loc 1 560 6 is_stmt 0 discriminator 4 view .LVU369 + 1329 0206 BBF1000F cmp fp, #0 + 1330 020a C2D0 beq .L78 + 562:Core/Src/printf.c **** // output the exponent value + 1331 .loc 1 562 5 is_stmt 1 view .LVU370 + 1332 020c 19F0200F tst r9, #32 + 1333 0210 27D0 beq .L104 + 1334 0212 4FF0450C mov ip, #69 + 1335 .L95: + 562:Core/Src/printf.c **** // output the exponent value + 1336 .loc 1 562 5 is_stmt 0 discriminator 4 view .LVU371 + 1337 0216 00F10109 add r9, r0, #1 + 1338 .LVL138: + 562:Core/Src/printf.c **** // output the exponent value + 1339 .loc 1 562 5 discriminator 4 view .LVU372 + 1340 021a 3346 mov r3, r6 + 1341 021c 0246 mov r2, r0 + 1342 021e 2946 mov r1, r5 + 1343 0220 6046 mov r0, ip + 1344 0222 A047 blx r4 + 1345 .LVL139: + 564:Core/Src/printf.c **** // might need to right-pad spaces + 1346 .loc 1 564 5 is_stmt 1 discriminator 4 view .LVU373 + 564:Core/Src/printf.c **** // might need to right-pad spaces + 1347 .loc 1 564 71 is_stmt 0 discriminator 4 view .LVU374 + 1348 0224 88EAE872 eor r2, r8, r8, asr #31 + 1349 0228 A2EBE872 sub r2, r2, r8, asr #31 + 564:Core/Src/printf.c **** // might need to right-pad spaces + 1350 .loc 1 564 11 discriminator 4 view .LVU375 + 1351 022c 0523 movs r3, #5 + 1352 022e 0593 str r3, [sp, #20] + 1353 0230 0BF1FF33 add r3, fp, #-1 + 1354 0234 0493 str r3, [sp, #16] + 1355 0236 0023 movs r3, #0 + 1356 0238 0393 str r3, [sp, #12] + 1357 023a 0A23 movs r3, #10 + 1358 023c 0293 str r3, [sp, #8] + 1359 023e 4FEAD873 lsr r3, r8, #31 + 1360 0242 0193 str r3, [sp, #4] + 1361 0244 0092 str r2, [sp] + 1362 0246 3346 mov r3, r6 + 1363 0248 4A46 mov r2, r9 + 1364 024a 2946 mov r1, r5 + 1365 024c 2046 mov r0, r4 + 1366 024e FFF7FEFF bl _ntoa_long + 1367 .LVL140: + 566:Core/Src/printf.c **** while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); + 1368 .loc 1 566 5 is_stmt 1 discriminator 4 view .LVU376 + ARM GAS /tmp/ccibzHy5.s page 37 + + + 566:Core/Src/printf.c **** while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); + 1369 .loc 1 566 8 is_stmt 0 discriminator 4 view .LVU377 + 1370 0252 079B ldr r3, [sp, #28] + 1371 0254 002B cmp r3, #0 + 1372 0256 9CD0 beq .L78 + 1373 0258 0246 mov r2, r0 + 1374 025a 0CE0 b .L96 + 1375 .LVL141: + 1376 .L115: + 557:Core/Src/printf.c **** + 1377 .loc 1 557 9 discriminator 1 view .LVU378 + 1378 025c B1EE455B vneg.f64 d5, d5 + 1379 .LVL142: + 557:Core/Src/printf.c **** + 1380 .loc 1 557 9 discriminator 1 view .LVU379 + 1381 0260 C4E7 b .L93 + 1382 .LVL143: + 1383 .L104: + 562:Core/Src/printf.c **** // output the exponent value + 1384 .loc 1 562 5 view .LVU380 + 1385 0262 4FF0650C mov ip, #101 + 1386 0266 D6E7 b .L95 + 1387 .LVL144: + 1388 .L97: + 567:Core/Src/printf.c **** } + 1389 .loc 1 567 39 is_stmt 1 discriminator 2 view .LVU381 + 1390 0268 02F10108 add r8, r2, #1 + 1391 .LVL145: + 567:Core/Src/printf.c **** } + 1392 .loc 1 567 39 is_stmt 0 discriminator 2 view .LVU382 + 1393 026c 3346 mov r3, r6 + 1394 026e 2946 mov r1, r5 + 1395 0270 2020 movs r0, #32 + 1396 0272 A047 blx r4 + 1397 .LVL146: + 1398 0274 4246 mov r2, r8 + 1399 .LVL147: + 1400 .L96: + 567:Core/Src/printf.c **** } + 1401 .loc 1 567 13 is_stmt 1 discriminator 1 view .LVU383 + 567:Core/Src/printf.c **** } + 1402 .loc 1 567 18 is_stmt 0 discriminator 1 view .LVU384 + 1403 0276 D31B subs r3, r2, r7 + 567:Core/Src/printf.c **** } + 1404 .loc 1 567 13 discriminator 1 view .LVU385 + 1405 0278 5345 cmp r3, r10 + 1406 027a F5D3 bcc .L97 + 567:Core/Src/printf.c **** } + 1407 .loc 1 567 13 discriminator 1 view .LVU386 + 1408 027c 1046 mov r0, r2 + 1409 027e 88E7 b .L78 + 1410 .L117: + 1411 .align 3 + 1412 .L116: + 1413 0280 FFFFFFFF .word -1 + 1414 0284 FFFFEF7F .word 2146435071 + 1415 0288 FFFFFFFF .word -1 + ARM GAS /tmp/ccibzHy5.s page 38 + + + 1416 028c FFFFEFFF .word -1048577 + 1417 0290 FB799F50 .word 1352628731 + 1418 0294 1344D33F .word 1070810131 + 1419 0298 B3C8608B .word -1956591437 + 1420 029c 288AC63F .word 1069976104 + 1421 02a0 61436F63 .word 1668236129 + 1422 02a4 A787D23F .word 1070761895 + 1423 02a8 71A37909 .word 158966641 + 1424 02ac 4F930A40 .word 1074434895 + 1425 02b0 EF39FAFE .word -17155601 + 1426 02b4 422EE63F .word 1072049730 + 1427 02b8 1655B5BB .word -1145744106 + 1428 02bc B16B0240 .word 1073900465 + 1429 02c0 2D431CEB .word -350469331 + 1430 02c4 E2361A3F .word 1058682594 + 1431 02c8 00000000 .word 0 + 1432 02cc 80842E41 .word 1093567616 + 1433 .cfi_endproc + 1434 .LFE12: + 1436 .section .rodata._ftoa.str1.4,"aMS",%progbits,1 + 1437 .align 2 + 1438 .LC0: + 1439 0000 666E6900 .ascii "fni\000" + 1440 .align 2 + 1441 .LC1: + 1442 0004 666E692B .ascii "fni+\000" + 1442 00 + 1443 0009 000000 .align 2 + 1444 .LC2: + 1445 000c 6E616E00 .ascii "nan\000" + 1446 .align 2 + 1447 .LC3: + 1448 0010 666E692D .ascii "fni-\000" + 1448 00 + 1449 .section .text._ftoa,"ax",%progbits + 1450 .align 1 + 1451 .syntax unified + 1452 .thumb + 1453 .thumb_func + 1454 .fpu fpv5-d16 + 1456 _ftoa: + 1457 .LVL148: + 1458 .LFB11: + 340:Core/Src/printf.c **** char buf[PRINTF_FTOA_BUFFER_SIZE]; + 1459 .loc 1 340 1 is_stmt 1 view -0 + 1460 .cfi_startproc + 1461 @ args = 12, pretend = 0, frame = 40 + 1462 @ frame_needed = 0, uses_anonymous_args = 0 + 340:Core/Src/printf.c **** char buf[PRINTF_FTOA_BUFFER_SIZE]; + 1463 .loc 1 340 1 is_stmt 0 view .LVU388 + 1464 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 1465 .LCFI20: + 1466 .cfi_def_cfa_offset 36 + 1467 .cfi_offset 4, -36 + 1468 .cfi_offset 5, -32 + 1469 .cfi_offset 6, -28 + 1470 .cfi_offset 7, -24 + ARM GAS /tmp/ccibzHy5.s page 39 + + + 1471 .cfi_offset 8, -20 + 1472 .cfi_offset 9, -16 + 1473 .cfi_offset 10, -12 + 1474 .cfi_offset 11, -8 + 1475 .cfi_offset 14, -4 + 1476 0004 8FB0 sub sp, sp, #60 + 1477 .LCFI21: + 1478 .cfi_def_cfa_offset 96 + 1479 0006 189D ldr r5, [sp, #96] + 1480 0008 199F ldr r7, [sp, #100] + 1481 000a 1A9E ldr r6, [sp, #104] + 341:Core/Src/printf.c **** size_t len = 0U; + 1482 .loc 1 341 3 is_stmt 1 view .LVU389 + 342:Core/Src/printf.c **** double diff = 0.0; + 1483 .loc 1 342 3 view .LVU390 + 1484 .LVL149: + 343:Core/Src/printf.c **** + 1485 .loc 1 343 3 view .LVU391 + 346:Core/Src/printf.c **** + 1486 .loc 1 346 3 view .LVU392 + 349:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); + 1487 .loc 1 349 3 view .LVU393 + 349:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); + 1488 .loc 1 349 6 is_stmt 0 view .LVU394 + 1489 000c B4EE400B vcmp.f64 d0, d0 + 1490 0010 F1EE10FA vmrs APSR_nzcv, FPSCR + 1491 0014 28D1 bne .L180 + 351:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); + 1492 .loc 1 351 3 is_stmt 1 view .LVU395 + 351:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); + 1493 .loc 1 351 6 is_stmt 0 view .LVU396 + 1494 0016 9FEDAC7B vldr.64 d7, .L185 + 1495 001a B4EEC70B vcmpe.f64 d0, d7 + 1496 001e F1EE10FA vmrs APSR_nzcv, FPSCR + 1497 0022 2AD4 bmi .L181 + 353:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS + 1498 .loc 1 353 3 is_stmt 1 view .LVU397 + 353:Core/Src/printf.c **** return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS + 1499 .loc 1 353 6 is_stmt 0 view .LVU398 + 1500 0024 9FEDAA7B vldr.64 d7, .L185+8 + 1501 0028 B4EEC70B vcmpe.f64 d0, d7 + 1502 002c F1EE10FA vmrs APSR_nzcv, FPSCR + 1503 0030 2CDC bgt .L182 + 358:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 1504 .loc 1 358 3 is_stmt 1 view .LVU399 + 358:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 1505 .loc 1 358 6 is_stmt 0 view .LVU400 + 1506 0032 9FEDA97B vldr.64 d7, .L185+16 + 1507 0036 B4EEC70B vcmpe.f64 d0, d7 + 1508 003a F1EE10FA vmrs APSR_nzcv, FPSCR + 1509 003e 36DC bgt .L127 + 358:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 1510 .loc 1 358 34 discriminator 1 view .LVU401 + 1511 0040 9FEDA77B vldr.64 d7, .L185+24 + 1512 0044 B4EEC70B vcmpe.f64 d0, d7 + 1513 0048 F1EE10FA vmrs APSR_nzcv, FPSCR + 1514 004c 2FD4 bmi .L127 + ARM GAS /tmp/ccibzHy5.s page 40 + + + 367:Core/Src/printf.c **** if (value < 0) { + 1515 .loc 1 367 3 is_stmt 1 view .LVU402 + 1516 .LVL150: + 368:Core/Src/printf.c **** negative = true; + 1517 .loc 1 368 3 view .LVU403 + 368:Core/Src/printf.c **** negative = true; + 1518 .loc 1 368 6 is_stmt 0 view .LVU404 + 1519 004e B5EEC00B vcmpe.f64 d0, #0 + 1520 0052 F1EE10FA vmrs APSR_nzcv, FPSCR + 1521 0056 30D4 bmi .L183 + 367:Core/Src/printf.c **** if (value < 0) { + 1522 .loc 1 367 8 view .LVU405 + 1523 0058 0024 movs r4, #0 + 1524 005a 0594 str r4, [sp, #20] + 1525 .LVL151: + 1526 .L130: + 374:Core/Src/printf.c **** prec = PRINTF_DEFAULT_FLOAT_PRECISION; + 1527 .loc 1 374 3 is_stmt 1 view .LVU406 + 374:Core/Src/printf.c **** prec = PRINTF_DEFAULT_FLOAT_PRECISION; + 1528 .loc 1 374 6 is_stmt 0 view .LVU407 + 1529 005c 16F4806F tst r6, #1024 + 1530 0060 00F08B80 beq .L165 + 1531 .L132: + 1532 .LVL152: + 375:Core/Src/printf.c **** } + 1533 .loc 1 375 10 view .LVU408 + 1534 0064 0024 movs r4, #0 + 1535 0066 38E0 b .L134 + 1536 .LVL153: + 1537 .L180: + 350:Core/Src/printf.c **** if (value < -DBL_MAX) + 1538 .loc 1 350 5 is_stmt 1 view .LVU409 + 350:Core/Src/printf.c **** if (value < -DBL_MAX) + 1539 .loc 1 350 12 is_stmt 0 view .LVU410 + 1540 0068 0396 str r6, [sp, #12] + 1541 006a 0297 str r7, [sp, #8] + 1542 006c 0324 movs r4, #3 + 1543 006e 0194 str r4, [sp, #4] + 1544 0070 9F4C ldr r4, .L185+40 + 1545 0072 0094 str r4, [sp] + 1546 0074 FFF7FEFF bl _out_rev + 1547 .LVL154: + 350:Core/Src/printf.c **** if (value < -DBL_MAX) + 1548 .loc 1 350 12 view .LVU411 + 1549 0078 F9E0 b .L118 + 1550 .LVL155: + 1551 .L181: + 352:Core/Src/printf.c **** if (value > DBL_MAX) + 1552 .loc 1 352 5 is_stmt 1 view .LVU412 + 352:Core/Src/printf.c **** if (value > DBL_MAX) + 1553 .loc 1 352 12 is_stmt 0 view .LVU413 + 1554 007a 0396 str r6, [sp, #12] + 1555 007c 0297 str r7, [sp, #8] + 1556 007e 0424 movs r4, #4 + 1557 0080 0194 str r4, [sp, #4] + 1558 0082 9C4C ldr r4, .L185+44 + 1559 0084 0094 str r4, [sp] + ARM GAS /tmp/ccibzHy5.s page 41 + + + 1560 0086 FFF7FEFF bl _out_rev + 1561 .LVL156: + 352:Core/Src/printf.c **** if (value > DBL_MAX) + 1562 .loc 1 352 12 view .LVU414 + 1563 008a F0E0 b .L118 + 1564 .LVL157: + 1565 .L182: + 354:Core/Src/printf.c **** + 1566 .loc 1 354 5 is_stmt 1 view .LVU415 + 354:Core/Src/printf.c **** + 1567 .loc 1 354 12 is_stmt 0 view .LVU416 + 1568 008c 16F00405 ands r5, r6, #4 + 1569 0090 09D0 beq .L162 + 1570 0092 994C ldr r4, .L185+48 + 1571 .L125: + 354:Core/Src/printf.c **** + 1572 .loc 1 354 12 discriminator 4 view .LVU417 + 1573 0094 4DB1 cbz r5, .L163 + 354:Core/Src/printf.c **** + 1574 .loc 1 354 12 view .LVU418 + 1575 0096 0425 movs r5, #4 + 1576 .L126: + 354:Core/Src/printf.c **** + 1577 .loc 1 354 12 discriminator 8 view .LVU419 + 1578 0098 0396 str r6, [sp, #12] + 1579 009a 0297 str r7, [sp, #8] + 1580 009c 0195 str r5, [sp, #4] + 1581 009e 0094 str r4, [sp] + 1582 00a0 FFF7FEFF bl _out_rev + 1583 .LVL158: + 354:Core/Src/printf.c **** + 1584 .loc 1 354 12 discriminator 8 view .LVU420 + 1585 00a4 E3E0 b .L118 + 1586 .LVL159: + 1587 .L162: + 354:Core/Src/printf.c **** + 1588 .loc 1 354 12 view .LVU421 + 1589 00a6 954C ldr r4, .L185+52 + 1590 00a8 F4E7 b .L125 + 1591 .L163: + 1592 00aa 0325 movs r5, #3 + 1593 00ac F4E7 b .L126 + 1594 .L127: + 360:Core/Src/printf.c **** #else + 1595 .loc 1 360 5 is_stmt 1 view .LVU422 + 360:Core/Src/printf.c **** #else + 1596 .loc 1 360 12 is_stmt 0 view .LVU423 + 1597 00ae 0296 str r6, [sp, #8] + 1598 00b0 0197 str r7, [sp, #4] + 1599 00b2 0095 str r5, [sp] + 1600 00b4 FFF7FEFF bl _etoa + 1601 .LVL160: + 360:Core/Src/printf.c **** #else + 1602 .loc 1 360 12 view .LVU424 + 1603 00b8 D9E0 b .L118 + 1604 .LVL161: + 1605 .L183: + ARM GAS /tmp/ccibzHy5.s page 42 + + + 369:Core/Src/printf.c **** value = 0 - value; + 1606 .loc 1 369 5 is_stmt 1 view .LVU425 + 370:Core/Src/printf.c **** } + 1607 .loc 1 370 5 view .LVU426 + 370:Core/Src/printf.c **** } + 1608 .loc 1 370 11 is_stmt 0 view .LVU427 + 1609 00ba 9FED8B7B vldr.64 d7, .L185+32 + 1610 00be 37EE400B vsub.f64 d0, d7, d0 + 1611 .LVL162: + 369:Core/Src/printf.c **** value = 0 - value; + 1612 .loc 1 369 14 view .LVU428 + 1613 00c2 0124 movs r4, #1 + 1614 00c4 0594 str r4, [sp, #20] + 1615 00c6 C9E7 b .L130 + 1616 .LVL163: + 1617 .L135: + 379:Core/Src/printf.c **** prec--; + 1618 .loc 1 379 5 is_stmt 1 view .LVU429 + 379:Core/Src/printf.c **** prec--; + 1619 .loc 1 379 16 is_stmt 0 view .LVU430 + 1620 00c8 0DF1380C add ip, sp, #56 + 1621 00cc A444 add ip, ip, r4 + 1622 00ce 4FF03008 mov r8, #48 + 1623 00d2 0CF8208C strb r8, [ip, #-32] + 380:Core/Src/printf.c **** } + 1624 .loc 1 380 5 is_stmt 1 view .LVU431 + 380:Core/Src/printf.c **** } + 1625 .loc 1 380 9 is_stmt 0 view .LVU432 + 1626 00d6 013D subs r5, r5, #1 + 1627 .LVL164: + 379:Core/Src/printf.c **** prec--; + 1628 .loc 1 379 12 view .LVU433 + 1629 00d8 0134 adds r4, r4, #1 + 1630 .LVL165: + 1631 .L134: + 378:Core/Src/printf.c **** buf[len++] = '0'; + 1632 .loc 1 378 9 is_stmt 1 view .LVU434 + 378:Core/Src/printf.c **** buf[len++] = '0'; + 1633 .loc 1 378 42 is_stmt 0 view .LVU435 + 1634 00da 1F2C cmp r4, #31 + 1635 00dc 8CBF ite hi + 1636 00de 4FF0000C movhi ip, #0 + 1637 00e2 4FF0010C movls ip, #1 + 1638 00e6 092D cmp r5, #9 + 1639 00e8 98BF it ls + 1640 00ea 4FF0000C movls ip, #0 + 378:Core/Src/printf.c **** buf[len++] = '0'; + 1641 .loc 1 378 9 view .LVU436 + 1642 00ee BCF1000F cmp ip, #0 + 1643 00f2 E9D1 bne .L135 + 383:Core/Src/printf.c **** double tmp = (value - whole) * pow10[prec]; + 1644 .loc 1 383 3 is_stmt 1 view .LVU437 + 383:Core/Src/printf.c **** double tmp = (value - whole) * pow10[prec]; + 1645 .loc 1 383 7 is_stmt 0 view .LVU438 + 1646 00f4 FDEEC07B vcvt.s32.f64 s15, d0 + 1647 00f8 17EE908A vmov r8, s15 @ int + 1648 .LVL166: + ARM GAS /tmp/ccibzHy5.s page 43 + + + 384:Core/Src/printf.c **** unsigned long frac = (unsigned long)tmp; + 1649 .loc 1 384 3 is_stmt 1 view .LVU439 + 384:Core/Src/printf.c **** unsigned long frac = (unsigned long)tmp; + 1650 .loc 1 384 23 is_stmt 0 view .LVU440 + 1651 00fc B8EEE77B vcvt.f64.s32 d7, s15 + 1652 0100 30EE477B vsub.f64 d7, d0, d7 + 384:Core/Src/printf.c **** unsigned long frac = (unsigned long)tmp; + 1653 .loc 1 384 39 view .LVU441 + 1654 0104 DFF8FCC1 ldr ip, .L185+60 + 1655 0108 0CEBC50C add ip, ip, r5, lsl #3 + 1656 010c 9CED006B vldr.64 d6, [ip] + 384:Core/Src/printf.c **** unsigned long frac = (unsigned long)tmp; + 1657 .loc 1 384 10 view .LVU442 + 1658 0110 27EE067B vmul.f64 d7, d7, d6 + 1659 .LVL167: + 385:Core/Src/printf.c **** diff = tmp - frac; + 1660 .loc 1 385 3 is_stmt 1 view .LVU443 + 385:Core/Src/printf.c **** diff = tmp - frac; + 1661 .loc 1 385 17 is_stmt 0 view .LVU444 + 1662 0114 FCEEC75B vcvt.u32.f64 s11, d7 + 1663 0118 15EE909A vmov r9, s11 @ int + 1664 .LVL168: + 386:Core/Src/printf.c **** + 1665 .loc 1 386 3 is_stmt 1 view .LVU445 + 386:Core/Src/printf.c **** + 1666 .loc 1 386 14 is_stmt 0 view .LVU446 + 1667 011c B8EE655B vcvt.f64.u32 d5, s11 + 386:Core/Src/printf.c **** + 1668 .loc 1 386 8 view .LVU447 + 1669 0120 37EE457B vsub.f64 d7, d7, d5 + 1670 .LVL169: + 388:Core/Src/printf.c **** ++frac; + 1671 .loc 1 388 3 is_stmt 1 view .LVU448 + 388:Core/Src/printf.c **** ++frac; + 1672 .loc 1 388 6 is_stmt 0 view .LVU449 + 1673 0124 B6EE005B vmov.f64 d5, #5.0e-1 + 1674 0128 B4EEC57B vcmpe.f64 d7, d5 + 1675 012c F1EE10FA vmrs APSR_nzcv, FPSCR + 1676 0130 25DD ble .L178 + 389:Core/Src/printf.c **** // handle rollover, e.g. case 0.99 with prec 1 is 1.0 + 1677 .loc 1 389 5 is_stmt 1 view .LVU450 + 1678 0132 09F10109 add r9, r9, #1 + 1679 .LVL170: + 391:Core/Src/printf.c **** frac = 0; + 1680 .loc 1 391 5 view .LVU451 + 391:Core/Src/printf.c **** frac = 0; + 1681 .loc 1 391 14 is_stmt 0 view .LVU452 + 1682 0136 07EE909A vmov s15, r9 @ int + 1683 013a B8EE677B vcvt.f64.u32 d7, s15 + 1684 .LVL171: + 391:Core/Src/printf.c **** frac = 0; + 1685 .loc 1 391 8 view .LVU453 + 1686 013e B4EEC76B vcmpe.f64 d6, d7 + 1687 0142 F1EE10FA vmrs APSR_nzcv, FPSCR + 1688 0146 03D8 bhi .L138 + 392:Core/Src/printf.c **** ++whole; + 1689 .loc 1 392 7 is_stmt 1 view .LVU454 + ARM GAS /tmp/ccibzHy5.s page 44 + + + 1690 .LVL172: + 393:Core/Src/printf.c **** } + 1691 .loc 1 393 7 view .LVU455 + 1692 0148 08F10108 add r8, r8, #1 + 1693 .LVL173: + 392:Core/Src/printf.c **** ++whole; + 1694 .loc 1 392 12 is_stmt 0 view .LVU456 + 1695 014c 4FF00009 mov r9, #0 + 1696 .LVL174: + 1697 .L138: + 403:Core/Src/printf.c **** diff = value - (double)whole; + 1698 .loc 1 403 3 is_stmt 1 view .LVU457 + 403:Core/Src/printf.c **** diff = value - (double)whole; + 1699 .loc 1 403 6 is_stmt 0 view .LVU458 + 1700 0150 2DBB cbnz r5, .L141 + 404:Core/Src/printf.c **** if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + 1701 .loc 1 404 5 is_stmt 1 view .LVU459 + 404:Core/Src/printf.c **** if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + 1702 .loc 1 404 20 is_stmt 0 view .LVU460 + 1703 0152 07EE908A vmov s15, r8 @ int + 1704 0156 B8EEE77B vcvt.f64.s32 d7, s15 + 404:Core/Src/printf.c **** if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + 1705 .loc 1 404 10 view .LVU461 + 1706 015a 30EE470B vsub.f64 d0, d0, d7 + 1707 .LVL175: + 405:Core/Src/printf.c **** // exactly 0.5 and ODD, then round up + 1708 .loc 1 405 5 is_stmt 1 view .LVU462 + 405:Core/Src/printf.c **** // exactly 0.5 and ODD, then round up + 1709 .loc 1 405 8 is_stmt 0 view .LVU463 + 1710 015e B6EE007B vmov.f64 d7, #5.0e-1 + 1711 0162 B4EEC70B vcmpe.f64 d0, d7 + 1712 0166 F1EE10FA vmrs APSR_nzcv, FPSCR + 1713 016a 00D5 bpl .L142 + 405:Core/Src/printf.c **** // exactly 0.5 and ODD, then round up + 1714 .loc 1 405 24 discriminator 2 view .LVU464 + 1715 016c 4BDD ble .L152 + 1716 .L142: + 405:Core/Src/printf.c **** // exactly 0.5 and ODD, then round up + 1717 .loc 1 405 41 discriminator 3 view .LVU465 + 1718 016e 18F0010F tst r8, #1 + 1719 0172 48D0 beq .L152 + 408:Core/Src/printf.c **** } + 1720 .loc 1 408 7 is_stmt 1 view .LVU466 + 1721 0174 08F10108 add r8, r8, #1 + 1722 .LVL176: + 408:Core/Src/printf.c **** } + 1723 .loc 1 408 7 is_stmt 0 view .LVU467 + 1724 0178 45E0 b .L152 + 1725 .LVL177: + 1726 .L165: + 375:Core/Src/printf.c **** } + 1727 .loc 1 375 10 view .LVU468 + 1728 017a 0625 movs r5, #6 + 1729 017c 72E7 b .L132 + 1730 .LVL178: + 1731 .L178: + 396:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 45 + + + 1732 .loc 1 396 8 is_stmt 1 view .LVU469 + 396:Core/Src/printf.c **** } + 1733 .loc 1 396 11 is_stmt 0 view .LVU470 + 1734 017e B6EE006B vmov.f64 d6, #5.0e-1 + 1735 .LVL179: + 396:Core/Src/printf.c **** } + 1736 .loc 1 396 11 view .LVU471 + 1737 0182 B4EEC67B vcmpe.f64 d7, d6 + 1738 0186 F1EE10FA vmrs APSR_nzcv, FPSCR + 1739 018a E1D4 bmi .L138 + 398:Core/Src/printf.c **** // if halfway, round up if odd OR if last digit is 0 + 1740 .loc 1 398 8 is_stmt 1 view .LVU472 + 398:Core/Src/printf.c **** // if halfway, round up if odd OR if last digit is 0 + 1741 .loc 1 398 11 is_stmt 0 view .LVU473 + 1742 018c B9F1000F cmp r9, #0 + 1743 0190 02D0 beq .L140 + 398:Core/Src/printf.c **** // if halfway, round up if odd OR if last digit is 0 + 1744 .loc 1 398 25 discriminator 1 view .LVU474 + 1745 0192 19F0010F tst r9, #1 + 1746 0196 DBD0 beq .L138 + 1747 .L140: + 400:Core/Src/printf.c **** } + 1748 .loc 1 400 5 is_stmt 1 view .LVU475 + 1749 0198 09F10109 add r9, r9, #1 + 1750 .LVL180: + 400:Core/Src/printf.c **** } + 1751 .loc 1 400 5 is_stmt 0 view .LVU476 + 1752 019c D8E7 b .L138 + 1753 .LVL181: + 1754 .L141: + 1755 .LBB30: + 414:Core/Src/printf.c **** --count; + 1756 .loc 1 414 11 is_stmt 1 view .LVU477 + 1757 019e 1F2C cmp r4, #31 + 1758 01a0 22D8 bhi .L148 + 415:Core/Src/printf.c **** buf[len++] = (char)(48U + (frac % 10U)); + 1759 .loc 1 415 7 view .LVU478 + 1760 01a2 013D subs r5, r5, #1 + 1761 .LVL182: + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1762 .loc 1 416 7 view .LVU479 + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1763 .loc 1 416 39 is_stmt 0 view .LVU480 + 1764 01a4 DFF860C1 ldr ip, .L185+64 + 1765 01a8 ACFB09EC umull lr, ip, ip, r9 + 1766 01ac 4FEADC0C lsr ip, ip, #3 + 1767 01b0 E346 mov fp, ip + 1768 01b2 0CEB8C0C add ip, ip, ip, lsl #2 + 1769 01b6 A9EB4C0C sub ip, r9, ip, lsl #1 + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1770 .loc 1 416 14 view .LVU481 + 1771 01ba 04F1010A add r10, r4, #1 + 1772 .LVL183: + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1773 .loc 1 416 20 view .LVU482 + 1774 01be 0CF1300C add ip, ip, #48 + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + ARM GAS /tmp/ccibzHy5.s page 46 + + + 1775 .loc 1 416 18 view .LVU483 + 1776 01c2 0DF1380E add lr, sp, #56 + 1777 01c6 7444 add r4, r4, lr + 1778 01c8 04F820CC strb ip, [r4, #-32] + 417:Core/Src/printf.c **** break; + 1779 .loc 1 417 7 is_stmt 1 view .LVU484 + 1780 .LVL184: + 417:Core/Src/printf.c **** break; + 1781 .loc 1 417 10 is_stmt 0 view .LVU485 + 1782 01cc B9F1090F cmp r9, #9 + 1783 01d0 34D9 bls .L166 + 417:Core/Src/printf.c **** break; + 1784 .loc 1 417 18 view .LVU486 + 1785 01d2 D946 mov r9, fp + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1786 .loc 1 416 14 view .LVU487 + 1787 01d4 5446 mov r4, r10 + 1788 01d6 E2E7 b .L141 + 1789 .LVL185: + 1790 .L150: + 423:Core/Src/printf.c **** } + 1791 .loc 1 423 7 is_stmt 1 view .LVU488 + 423:Core/Src/printf.c **** } + 1792 .loc 1 423 18 is_stmt 0 view .LVU489 + 1793 01d8 0EAD add r5, sp, #56 + 1794 01da 2544 add r5, r5, r4 + 1795 01dc 4FF03009 mov r9, #48 + 1796 01e0 05F8209C strb r9, [r5, #-32] + 422:Core/Src/printf.c **** buf[len++] = '0'; + 1797 .loc 1 422 53 view .LVU490 + 1798 01e4 6546 mov r5, ip + 423:Core/Src/printf.c **** } + 1799 .loc 1 423 14 view .LVU491 + 1800 01e6 0134 adds r4, r4, #1 + 1801 .LVL186: + 1802 .L148: + 422:Core/Src/printf.c **** buf[len++] = '0'; + 1803 .loc 1 422 11 is_stmt 1 view .LVU492 + 1804 01e8 1F2C cmp r4, #31 + 1805 01ea 03D8 bhi .L149 + 422:Core/Src/printf.c **** buf[len++] = '0'; + 1806 .loc 1 422 53 is_stmt 0 discriminator 1 view .LVU493 + 1807 01ec 05F1FF3C add ip, r5, #-1 + 1808 .LVL187: + 422:Core/Src/printf.c **** buf[len++] = '0'; + 1809 .loc 1 422 44 discriminator 1 view .LVU494 + 1810 01f0 002D cmp r5, #0 + 1811 01f2 F1D1 bne .L150 + 1812 .LVL188: + 1813 .L149: + 425:Core/Src/printf.c **** // add decimal + 1814 .loc 1 425 5 is_stmt 1 view .LVU495 + 425:Core/Src/printf.c **** // add decimal + 1815 .loc 1 425 8 is_stmt 0 view .LVU496 + 1816 01f4 1F2C cmp r4, #31 + 1817 01f6 06D8 bhi .L152 + 427:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 47 + + + 1818 .loc 1 427 7 is_stmt 1 view .LVU497 + 1819 .LVL189: + 427:Core/Src/printf.c **** } + 1820 .loc 1 427 18 is_stmt 0 view .LVU498 + 1821 01f8 0EAD add r5, sp, #56 + 1822 01fa 2544 add r5, r5, r4 + 1823 01fc 4FF02E0C mov ip, #46 + 1824 0200 05F820CC strb ip, [r5, #-32] + 427:Core/Src/printf.c **** } + 1825 .loc 1 427 14 view .LVU499 + 1826 0204 0134 adds r4, r4, #1 + 1827 .LVL190: + 1828 .L152: + 427:Core/Src/printf.c **** } + 1829 .loc 1 427 14 view .LVU500 + 1830 .LBE30: + 432:Core/Src/printf.c **** buf[len++] = (char)(48 + (whole % 10)); + 1831 .loc 1 432 9 is_stmt 1 view .LVU501 + 1832 0206 1F2C cmp r4, #31 + 1833 0208 1BD8 bhi .L151 + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1834 .loc 1 433 5 view .LVU502 + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1835 .loc 1 433 37 is_stmt 0 view .LVU503 + 1836 020a 3D4D ldr r5, .L185+56 + 1837 020c 85FB08C5 smull ip, r5, r5, r8 + 1838 0210 4FEAE87C asr ip, r8, #31 + 1839 0214 CCEBA50C rsb ip, ip, r5, asr #2 + 1840 0218 6546 mov r5, ip + 1841 021a 0CEB8C0C add ip, ip, ip, lsl #2 + 1842 021e A8EB4C0C sub ip, r8, ip, lsl #1 + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1843 .loc 1 433 12 view .LVU504 + 1844 0222 04F10109 add r9, r4, #1 + 1845 .LVL191: + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1846 .loc 1 433 18 view .LVU505 + 1847 0226 0CF1300C add ip, ip, #48 + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1848 .loc 1 433 16 view .LVU506 + 1849 022a 0DF13808 add r8, sp, #56 + 1850 .LVL192: + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1851 .loc 1 433 16 view .LVU507 + 1852 022e 4444 add r4, r4, r8 + 1853 0230 04F820CC strb ip, [r4, #-32] + 434:Core/Src/printf.c **** break; + 1854 .loc 1 434 5 is_stmt 1 view .LVU508 + 434:Core/Src/printf.c **** break; + 1855 .loc 1 434 17 is_stmt 0 view .LVU509 + 1856 0234 A846 mov r8, r5 + 1857 .LVL193: + 434:Core/Src/printf.c **** break; + 1858 .loc 1 434 8 view .LVU510 + 1859 0236 1DB1 cbz r5, .L167 + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1860 .loc 1 433 12 view .LVU511 + ARM GAS /tmp/ccibzHy5.s page 48 + + + 1861 0238 4C46 mov r4, r9 + 1862 023a E4E7 b .L152 + 1863 .LVL194: + 1864 .L166: + 1865 .LBB31: + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1866 .loc 1 416 14 view .LVU512 + 1867 023c 5446 mov r4, r10 + 1868 023e D3E7 b .L148 + 1869 .LVL195: + 1870 .L167: + 416:Core/Src/printf.c **** if (!(frac /= 10U)) { + 1871 .loc 1 416 14 view .LVU513 + 1872 .LBE31: + 433:Core/Src/printf.c **** if (!(whole /= 10)) { + 1873 .loc 1 433 12 view .LVU514 + 1874 0240 4C46 mov r4, r9 + 1875 .LVL196: + 1876 .L151: + 440:Core/Src/printf.c **** if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + 1877 .loc 1 440 3 is_stmt 1 view .LVU515 + 440:Core/Src/printf.c **** if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + 1878 .loc 1 440 29 is_stmt 0 view .LVU516 + 1879 0242 06F00305 and r5, r6, #3 + 440:Core/Src/printf.c **** if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + 1880 .loc 1 440 6 view .LVU517 + 1881 0246 012D cmp r5, #1 + 1882 0248 14D0 beq .L184 + 1883 .LVL197: + 1884 .L154: + 449:Core/Src/printf.c **** if (negative) { + 1885 .loc 1 449 3 is_stmt 1 view .LVU518 + 449:Core/Src/printf.c **** if (negative) { + 1886 .loc 1 449 6 is_stmt 0 view .LVU519 + 1887 024a 1F2C cmp r4, #31 + 1888 024c 08D8 bhi .L159 + 450:Core/Src/printf.c **** buf[len++] = '-'; + 1889 .loc 1 450 5 is_stmt 1 view .LVU520 + 450:Core/Src/printf.c **** buf[len++] = '-'; + 1890 .loc 1 450 8 is_stmt 0 view .LVU521 + 1891 024e 059D ldr r5, [sp, #20] + 1892 0250 25B3 cbz r5, .L160 + 451:Core/Src/printf.c **** } + 1893 .loc 1 451 7 is_stmt 1 view .LVU522 + 1894 .LVL198: + 451:Core/Src/printf.c **** } + 1895 .loc 1 451 18 is_stmt 0 view .LVU523 + 1896 0252 0EAD add r5, sp, #56 + 1897 0254 2544 add r5, r5, r4 + 1898 0256 4FF02D0C mov ip, #45 + 1899 025a 05F820CC strb ip, [r5, #-32] + 451:Core/Src/printf.c **** } + 1900 .loc 1 451 14 view .LVU524 + 1901 025e 0134 adds r4, r4, #1 + 1902 .LVL199: + 1903 .L159: + 461:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 49 + + + 1904 .loc 1 461 3 is_stmt 1 view .LVU525 + 461:Core/Src/printf.c **** } + 1905 .loc 1 461 10 is_stmt 0 view .LVU526 + 1906 0260 0396 str r6, [sp, #12] + 1907 0262 0297 str r7, [sp, #8] + 1908 0264 0194 str r4, [sp, #4] + 1909 0266 06AC add r4, sp, #24 + 1910 .LVL200: + 461:Core/Src/printf.c **** } + 1911 .loc 1 461 10 view .LVU527 + 1912 0268 0094 str r4, [sp] + 1913 026a FFF7FEFF bl _out_rev + 1914 .LVL201: + 1915 .L118: + 462:Core/Src/printf.c **** + 1916 .loc 1 462 1 view .LVU528 + 1917 026e 0FB0 add sp, sp, #60 + 1918 .LCFI22: + 1919 .cfi_remember_state + 1920 .cfi_def_cfa_offset 36 + 1921 @ sp needed + 1922 0270 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 1923 .LVL202: + 1924 .L184: + 1925 .LCFI23: + 1926 .cfi_restore_state + 441:Core/Src/printf.c **** width--; + 1927 .loc 1 441 5 is_stmt 1 view .LVU529 + 441:Core/Src/printf.c **** width--; + 1928 .loc 1 441 8 is_stmt 0 view .LVU530 + 1929 0274 6FB1 cbz r7, .L157 + 441:Core/Src/printf.c **** width--; + 1930 .loc 1 441 15 discriminator 1 view .LVU531 + 1931 0276 059D ldr r5, [sp, #20] + 1932 0278 15B9 cbnz r5, .L156 + 441:Core/Src/printf.c **** width--; + 1933 .loc 1 441 28 discriminator 2 view .LVU532 + 1934 027a 16F00C0F tst r6, #12 + 1935 027e 08D0 beq .L157 + 1936 .L156: + 442:Core/Src/printf.c **** } + 1937 .loc 1 442 7 is_stmt 1 view .LVU533 + 442:Core/Src/printf.c **** } + 1938 .loc 1 442 12 is_stmt 0 view .LVU534 + 1939 0280 013F subs r7, r7, #1 + 1940 .LVL203: + 442:Core/Src/printf.c **** } + 1941 .loc 1 442 12 view .LVU535 + 1942 0282 06E0 b .L157 + 1943 .L158: + 445:Core/Src/printf.c **** } + 1944 .loc 1 445 7 is_stmt 1 view .LVU536 + 1945 .LVL204: + 445:Core/Src/printf.c **** } + 1946 .loc 1 445 18 is_stmt 0 view .LVU537 + 1947 0284 0EAD add r5, sp, #56 + 1948 0286 2544 add r5, r5, r4 + ARM GAS /tmp/ccibzHy5.s page 50 + + + 1949 0288 4FF0300C mov ip, #48 + 1950 028c 05F820CC strb ip, [r5, #-32] + 445:Core/Src/printf.c **** } + 1951 .loc 1 445 14 view .LVU538 + 1952 0290 0134 adds r4, r4, #1 + 1953 .LVL205: + 1954 .L157: + 444:Core/Src/printf.c **** buf[len++] = '0'; + 1955 .loc 1 444 11 is_stmt 1 view .LVU539 + 1956 0292 1F2C cmp r4, #31 + 1957 0294 98BF it ls + 1958 0296 BC42 cmpls r4, r7 + 1959 0298 F4D3 bcc .L158 + 444:Core/Src/printf.c **** buf[len++] = '0'; + 1960 .loc 1 444 11 is_stmt 0 view .LVU540 + 1961 029a D6E7 b .L154 + 1962 .L160: + 453:Core/Src/printf.c **** buf[len++] = '+'; // ignore the space if the '+' exists + 1963 .loc 1 453 10 is_stmt 1 view .LVU541 + 453:Core/Src/printf.c **** buf[len++] = '+'; // ignore the space if the '+' exists + 1964 .loc 1 453 13 is_stmt 0 view .LVU542 + 1965 029c 16F0040F tst r6, #4 + 1966 02a0 07D0 beq .L161 + 454:Core/Src/printf.c **** } + 1967 .loc 1 454 7 is_stmt 1 view .LVU543 + 1968 .LVL206: + 454:Core/Src/printf.c **** } + 1969 .loc 1 454 18 is_stmt 0 view .LVU544 + 1970 02a2 0EAD add r5, sp, #56 + 1971 02a4 2544 add r5, r5, r4 + 1972 02a6 4FF02B0C mov ip, #43 + 1973 02aa 05F820CC strb ip, [r5, #-32] + 454:Core/Src/printf.c **** } + 1974 .loc 1 454 14 view .LVU545 + 1975 02ae 0134 adds r4, r4, #1 + 1976 .LVL207: + 454:Core/Src/printf.c **** } + 1977 .loc 1 454 14 view .LVU546 + 1978 02b0 D6E7 b .L159 + 1979 .L161: + 456:Core/Src/printf.c **** buf[len++] = ' '; + 1980 .loc 1 456 10 is_stmt 1 view .LVU547 + 456:Core/Src/printf.c **** buf[len++] = ' '; + 1981 .loc 1 456 13 is_stmt 0 view .LVU548 + 1982 02b2 16F0080F tst r6, #8 + 1983 02b6 D3D0 beq .L159 + 457:Core/Src/printf.c **** } + 1984 .loc 1 457 7 is_stmt 1 view .LVU549 + 1985 .LVL208: + 457:Core/Src/printf.c **** } + 1986 .loc 1 457 18 is_stmt 0 view .LVU550 + 1987 02b8 0EAD add r5, sp, #56 + 1988 02ba 2544 add r5, r5, r4 + 1989 02bc 4FF0200C mov ip, #32 + 1990 02c0 05F820CC strb ip, [r5, #-32] + 457:Core/Src/printf.c **** } + 1991 .loc 1 457 14 view .LVU551 + ARM GAS /tmp/ccibzHy5.s page 51 + + + 1992 02c4 0134 adds r4, r4, #1 + 1993 .LVL209: + 457:Core/Src/printf.c **** } + 1994 .loc 1 457 14 view .LVU552 + 1995 02c6 CBE7 b .L159 + 1996 .L186: + 1997 .align 3 + 1998 .L185: + 1999 02c8 FFFFFFFF .word -1 + 2000 02cc FFFFEFFF .word -1048577 + 2001 02d0 FFFFFFFF .word -1 + 2002 02d4 FFFFEF7F .word 2146435071 + 2003 02d8 00000000 .word 0 + 2004 02dc 65CDCD41 .word 1104006501 + 2005 02e0 00000000 .word 0 + 2006 02e4 65CDCDC1 .word -1043477147 + 2007 02e8 00000000 .word 0 + 2008 02ec 00000000 .word 0 + 2009 02f0 0C000000 .word .LC2 + 2010 02f4 10000000 .word .LC3 + 2011 02f8 04000000 .word .LC1 + 2012 02fc 00000000 .word .LC0 + 2013 0300 67666666 .word 1717986919 + 2014 0304 00000000 .word .LANCHOR0 + 2015 0308 CDCCCCCC .word -858993459 + 2016 .cfi_endproc + 2017 .LFE11: + 2019 .section .text._vsnprintf,"ax",%progbits + 2020 .align 1 + 2021 .syntax unified + 2022 .thumb + 2023 .thumb_func + 2024 .fpu fpv5-d16 + 2026 _vsnprintf: + 2027 .LVL210: + 2028 .LFB13: + 572:Core/Src/printf.c **** #endif // PRINTF_SUPPORT_EXPONENTIAL + 573:Core/Src/printf.c **** #endif // PRINTF_SUPPORT_FLOAT + 574:Core/Src/printf.c **** + 575:Core/Src/printf.c **** + 576:Core/Src/printf.c **** // internal vsnprintf + 577:Core/Src/printf.c **** static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_l + 578:Core/Src/printf.c **** { + 2029 .loc 1 578 1 is_stmt 1 view -0 + 2030 .cfi_startproc + 2031 @ args = 4, pretend = 0, frame = 16 + 2032 @ frame_needed = 0, uses_anonymous_args = 0 + 2033 .loc 1 578 1 is_stmt 0 view .LVU554 + 2034 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 2035 .LCFI24: + 2036 .cfi_def_cfa_offset 36 + 2037 .cfi_offset 4, -36 + 2038 .cfi_offset 5, -32 + 2039 .cfi_offset 6, -28 + 2040 .cfi_offset 7, -24 + 2041 .cfi_offset 8, -20 + 2042 .cfi_offset 9, -16 + ARM GAS /tmp/ccibzHy5.s page 52 + + + 2043 .cfi_offset 10, -12 + 2044 .cfi_offset 11, -8 + 2045 .cfi_offset 14, -4 + 2046 0004 8FB0 sub sp, sp, #60 + 2047 .LCFI25: + 2048 .cfi_def_cfa_offset 96 + 2049 0006 0746 mov r7, r0 + 2050 0008 1646 mov r6, r2 + 2051 000a 0D93 str r3, [sp, #52] + 579:Core/Src/printf.c **** unsigned int flags, width, precision, n; + 2052 .loc 1 579 3 is_stmt 1 view .LVU555 + 580:Core/Src/printf.c **** size_t idx = 0U; + 2053 .loc 1 580 3 view .LVU556 + 2054 .LVL211: + 581:Core/Src/printf.c **** + 582:Core/Src/printf.c **** if (!buffer) { + 2055 .loc 1 582 3 view .LVU557 + 2056 .loc 1 582 6 is_stmt 0 view .LVU558 + 2057 000c 8846 mov r8, r1 + 2058 000e 0029 cmp r1, #0 + 2059 0010 00F02283 beq .L283 + 2060 .L188: + 2061 .LVL212: + 2062 .LBB32: + 583:Core/Src/printf.c **** // use null output function + 584:Core/Src/printf.c **** out = _out_null; + 585:Core/Src/printf.c **** } + 586:Core/Src/printf.c **** + 587:Core/Src/printf.c **** while (*format) + 588:Core/Src/printf.c **** { + 589:Core/Src/printf.c **** // format specifier? %[flags][width][.precision][length] + 590:Core/Src/printf.c **** if (*format != '%') { + 591:Core/Src/printf.c **** // no + 592:Core/Src/printf.c **** out(*format, buffer, idx++, maxlen); + 593:Core/Src/printf.c **** format++; + 594:Core/Src/printf.c **** continue; + 595:Core/Src/printf.c **** } + 596:Core/Src/printf.c **** else { + 597:Core/Src/printf.c **** // yes, evaluate it + 598:Core/Src/printf.c **** format++; + 599:Core/Src/printf.c **** } + 600:Core/Src/printf.c **** + 601:Core/Src/printf.c **** // evaluate flags + 602:Core/Src/printf.c **** flags = 0U; + 603:Core/Src/printf.c **** do { + 604:Core/Src/printf.c **** switch (*format) { + 605:Core/Src/printf.c **** case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break; + 606:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 607:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 608:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 609:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 610:Core/Src/printf.c **** default : n = 0U; break; + 611:Core/Src/printf.c **** } + 612:Core/Src/printf.c **** } while (n); + 613:Core/Src/printf.c **** + 614:Core/Src/printf.c **** // evaluate width field + 615:Core/Src/printf.c **** width = 0U; + ARM GAS /tmp/ccibzHy5.s page 53 + + + 616:Core/Src/printf.c **** if (_is_digit(*format)) { + 617:Core/Src/printf.c **** width = _atoi(&format); + 618:Core/Src/printf.c **** } + 619:Core/Src/printf.c **** else if (*format == '*') { + 620:Core/Src/printf.c **** const int w = va_arg(va, int); + 621:Core/Src/printf.c **** if (w < 0) { + 622:Core/Src/printf.c **** flags |= FLAGS_LEFT; // reverse padding + 623:Core/Src/printf.c **** width = (unsigned int)-w; + 624:Core/Src/printf.c **** } + 625:Core/Src/printf.c **** else { + 626:Core/Src/printf.c **** width = (unsigned int)w; + 627:Core/Src/printf.c **** } + 628:Core/Src/printf.c **** format++; + 629:Core/Src/printf.c **** } + 630:Core/Src/printf.c **** + 631:Core/Src/printf.c **** // evaluate precision field + 632:Core/Src/printf.c **** precision = 0U; + 633:Core/Src/printf.c **** if (*format == '.') { + 634:Core/Src/printf.c **** flags |= FLAGS_PRECISION; + 635:Core/Src/printf.c **** format++; + 636:Core/Src/printf.c **** if (_is_digit(*format)) { + 637:Core/Src/printf.c **** precision = _atoi(&format); + 638:Core/Src/printf.c **** } + 639:Core/Src/printf.c **** else if (*format == '*') { + 640:Core/Src/printf.c **** const int prec = (int)va_arg(va, int); + 641:Core/Src/printf.c **** precision = prec > 0 ? (unsigned int)prec : 0U; + 642:Core/Src/printf.c **** format++; + 643:Core/Src/printf.c **** } + 644:Core/Src/printf.c **** } + 645:Core/Src/printf.c **** + 646:Core/Src/printf.c **** // evaluate length field + 647:Core/Src/printf.c **** switch (*format) { + 648:Core/Src/printf.c **** case 'l' : + 649:Core/Src/printf.c **** flags |= FLAGS_LONG; + 650:Core/Src/printf.c **** format++; + 651:Core/Src/printf.c **** if (*format == 'l') { + 652:Core/Src/printf.c **** flags |= FLAGS_LONG_LONG; + 653:Core/Src/printf.c **** format++; + 654:Core/Src/printf.c **** } + 655:Core/Src/printf.c **** break; + 656:Core/Src/printf.c **** case 'h' : + 657:Core/Src/printf.c **** flags |= FLAGS_SHORT; + 658:Core/Src/printf.c **** format++; + 659:Core/Src/printf.c **** if (*format == 'h') { + 660:Core/Src/printf.c **** flags |= FLAGS_CHAR; + 661:Core/Src/printf.c **** format++; + 662:Core/Src/printf.c **** } + 663:Core/Src/printf.c **** break; + 664:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_PTRDIFF_T) + 665:Core/Src/printf.c **** case 't' : + 666:Core/Src/printf.c **** flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + 667:Core/Src/printf.c **** format++; + 668:Core/Src/printf.c **** break; + 669:Core/Src/printf.c **** #endif + 670:Core/Src/printf.c **** case 'j' : + 671:Core/Src/printf.c **** flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + 672:Core/Src/printf.c **** format++; + ARM GAS /tmp/ccibzHy5.s page 54 + + + 673:Core/Src/printf.c **** break; + 674:Core/Src/printf.c **** case 'z' : + 675:Core/Src/printf.c **** flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + 676:Core/Src/printf.c **** format++; + 677:Core/Src/printf.c **** break; + 678:Core/Src/printf.c **** default : + 679:Core/Src/printf.c **** break; + 680:Core/Src/printf.c **** } + 681:Core/Src/printf.c **** + 682:Core/Src/printf.c **** // evaluate specifier + 683:Core/Src/printf.c **** switch (*format) { + 684:Core/Src/printf.c **** case 'd' : + 685:Core/Src/printf.c **** case 'i' : + 686:Core/Src/printf.c **** case 'u' : + 687:Core/Src/printf.c **** case 'x' : + 688:Core/Src/printf.c **** case 'X' : + 689:Core/Src/printf.c **** case 'o' : + 690:Core/Src/printf.c **** case 'b' : { + 691:Core/Src/printf.c **** // set the base + 692:Core/Src/printf.c **** unsigned int base; + 693:Core/Src/printf.c **** if (*format == 'x' || *format == 'X') { + 694:Core/Src/printf.c **** base = 16U; + 695:Core/Src/printf.c **** } + 696:Core/Src/printf.c **** else if (*format == 'o') { + 697:Core/Src/printf.c **** base = 8U; + 698:Core/Src/printf.c **** } + 699:Core/Src/printf.c **** else if (*format == 'b') { + 700:Core/Src/printf.c **** base = 2U; + 701:Core/Src/printf.c **** } + 702:Core/Src/printf.c **** else { + 703:Core/Src/printf.c **** base = 10U; + 704:Core/Src/printf.c **** flags &= ~FLAGS_HASH; // no hash for dec format + 705:Core/Src/printf.c **** } + 706:Core/Src/printf.c **** // uppercase + 707:Core/Src/printf.c **** if (*format == 'X') { + 708:Core/Src/printf.c **** flags |= FLAGS_UPPERCASE; + 709:Core/Src/printf.c **** } + 710:Core/Src/printf.c **** + 711:Core/Src/printf.c **** // no plus or space flag for u, x, X, o, b + 712:Core/Src/printf.c **** if ((*format != 'i') && (*format != 'd')) { + 713:Core/Src/printf.c **** flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + 714:Core/Src/printf.c **** } + 715:Core/Src/printf.c **** + 716:Core/Src/printf.c **** // ignore '0' flag when precision is given + 717:Core/Src/printf.c **** if (flags & FLAGS_PRECISION) { + 718:Core/Src/printf.c **** flags &= ~FLAGS_ZEROPAD; + 719:Core/Src/printf.c **** } + 720:Core/Src/printf.c **** + 721:Core/Src/printf.c **** // convert the integer + 722:Core/Src/printf.c **** if ((*format == 'i') || (*format == 'd')) { + 723:Core/Src/printf.c **** // signed + 724:Core/Src/printf.c **** if (flags & FLAGS_LONG_LONG) { + 725:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 726:Core/Src/printf.c **** const long long value = va_arg(va, long long); + 727:Core/Src/printf.c **** idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value + 728:Core/Src/printf.c **** #endif + 729:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 55 + + + 730:Core/Src/printf.c **** else if (flags & FLAGS_LONG) { + 731:Core/Src/printf.c **** const long value = va_arg(va, long); + 732:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - valu + 733:Core/Src/printf.c **** } + 734:Core/Src/printf.c **** else { + 735:Core/Src/printf.c **** const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) + 736:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 737:Core/Src/printf.c **** } + 738:Core/Src/printf.c **** } + 739:Core/Src/printf.c **** else { + 740:Core/Src/printf.c **** // unsigned + 741:Core/Src/printf.c **** if (flags & FLAGS_LONG_LONG) { + 742:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 743:Core/Src/printf.c **** idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, + 744:Core/Src/printf.c **** #endif + 745:Core/Src/printf.c **** } + 746:Core/Src/printf.c **** else if (flags & FLAGS_LONG) { + 747:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, prec + 748:Core/Src/printf.c **** } + 749:Core/Src/printf.c **** else { + 750:Core/Src/printf.c **** const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned in + 751:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 752:Core/Src/printf.c **** } + 753:Core/Src/printf.c **** } + 754:Core/Src/printf.c **** format++; + 755:Core/Src/printf.c **** break; + 756:Core/Src/printf.c **** } + 757:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_FLOAT) + 758:Core/Src/printf.c **** case 'f' : + 759:Core/Src/printf.c **** case 'F' : + 760:Core/Src/printf.c **** if (*format == 'F') flags |= FLAGS_UPPERCASE; + 761:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 762:Core/Src/printf.c **** format++; + 763:Core/Src/printf.c **** break; + 764:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 765:Core/Src/printf.c **** case 'e': + 766:Core/Src/printf.c **** case 'E': + 767:Core/Src/printf.c **** case 'g': + 768:Core/Src/printf.c **** case 'G': + 769:Core/Src/printf.c **** if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP; + 770:Core/Src/printf.c **** if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + 771:Core/Src/printf.c **** idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 772:Core/Src/printf.c **** format++; + 773:Core/Src/printf.c **** break; + 774:Core/Src/printf.c **** #endif // PRINTF_SUPPORT_EXPONENTIAL + 775:Core/Src/printf.c **** #endif // PRINTF_SUPPORT_FLOAT + 776:Core/Src/printf.c **** case 'c' : { + 777:Core/Src/printf.c **** unsigned int l = 1U; + 778:Core/Src/printf.c **** // pre padding + 779:Core/Src/printf.c **** if (!(flags & FLAGS_LEFT)) { + 780:Core/Src/printf.c **** while (l++ < width) { + 781:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 782:Core/Src/printf.c **** } + 783:Core/Src/printf.c **** } + 784:Core/Src/printf.c **** // char output + 785:Core/Src/printf.c **** out((char)va_arg(va, int), buffer, idx++, maxlen); + 786:Core/Src/printf.c **** // post padding + ARM GAS /tmp/ccibzHy5.s page 56 + + + 787:Core/Src/printf.c **** if (flags & FLAGS_LEFT) { + 788:Core/Src/printf.c **** while (l++ < width) { + 789:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 790:Core/Src/printf.c **** } + 791:Core/Src/printf.c **** } + 792:Core/Src/printf.c **** format++; + 793:Core/Src/printf.c **** break; + 2063 .loc 1 793 9 view .LVU559 + 2064 0014 0024 movs r4, #0 + 2065 .LVL213: + 2066 .L265: + 2067 .loc 1 793 9 view .LVU560 + 2068 .LBE32: + 587:Core/Src/printf.c **** { + 2069 .loc 1 587 9 is_stmt 1 view .LVU561 + 587:Core/Src/printf.c **** { + 2070 .loc 1 587 10 is_stmt 0 view .LVU562 + 2071 0016 0D9B ldr r3, [sp, #52] + 2072 0018 1878 ldrb r0, [r3] @ zero_extendqisi2 + 587:Core/Src/printf.c **** { + 2073 .loc 1 587 9 view .LVU563 + 2074 001a 0028 cmp r0, #0 + 2075 001c 00F01E83 beq .L284 + 590:Core/Src/printf.c **** // no + 2076 .loc 1 590 5 is_stmt 1 view .LVU564 + 590:Core/Src/printf.c **** // no + 2077 .loc 1 590 8 is_stmt 0 view .LVU565 + 2078 0020 2528 cmp r0, #37 + 2079 0022 09D0 beq .L190 + 592:Core/Src/printf.c **** format++; + 2080 .loc 1 592 7 is_stmt 1 view .LVU566 + 2081 0024 651C adds r5, r4, #1 + 2082 .LVL214: + 592:Core/Src/printf.c **** format++; + 2083 .loc 1 592 7 is_stmt 0 view .LVU567 + 2084 0026 3346 mov r3, r6 + 2085 0028 2246 mov r2, r4 + 2086 002a 4146 mov r1, r8 + 2087 002c B847 blx r7 + 2088 .LVL215: + 593:Core/Src/printf.c **** continue; + 2089 .loc 1 593 7 is_stmt 1 view .LVU568 + 593:Core/Src/printf.c **** continue; + 2090 .loc 1 593 13 is_stmt 0 view .LVU569 + 2091 002e 0D9B ldr r3, [sp, #52] + 2092 0030 0133 adds r3, r3, #1 + 2093 0032 0D93 str r3, [sp, #52] + 594:Core/Src/printf.c **** } + 2094 .loc 1 594 7 is_stmt 1 view .LVU570 + 592:Core/Src/printf.c **** format++; + 2095 .loc 1 592 7 is_stmt 0 view .LVU571 + 2096 0034 2C46 mov r4, r5 + 594:Core/Src/printf.c **** } + 2097 .loc 1 594 7 view .LVU572 + 2098 0036 EEE7 b .L265 + 2099 .LVL216: + 2100 .L190: + ARM GAS /tmp/ccibzHy5.s page 57 + + + 598:Core/Src/printf.c **** } + 2101 .loc 1 598 7 is_stmt 1 view .LVU573 + 598:Core/Src/printf.c **** } + 2102 .loc 1 598 13 is_stmt 0 view .LVU574 + 2103 0038 0133 adds r3, r3, #1 + 2104 003a 0D93 str r3, [sp, #52] + 602:Core/Src/printf.c **** do { + 2105 .loc 1 602 5 is_stmt 1 view .LVU575 + 2106 .LVL217: + 602:Core/Src/printf.c **** do { + 2107 .loc 1 602 11 is_stmt 0 view .LVU576 + 2108 003c 0025 movs r5, #0 + 2109 .LVL218: + 2110 .L192: + 603:Core/Src/printf.c **** switch (*format) { + 2111 .loc 1 603 5 is_stmt 1 view .LVU577 + 604:Core/Src/printf.c **** case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break; + 2112 .loc 1 604 7 view .LVU578 + 604:Core/Src/printf.c **** case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break; + 2113 .loc 1 604 15 is_stmt 0 view .LVU579 + 2114 003e 0D9B ldr r3, [sp, #52] + 2115 0040 1978 ldrb r1, [r3] @ zero_extendqisi2 + 2116 0042 A1F12002 sub r2, r1, #32 + 2117 0046 102A cmp r2, #16 + 2118 0048 0AD8 bhi .L193 + 2119 004a DFE802F0 tbb [pc, r2] + 2120 .L195: + 2121 004e 38 .byte (.L199-.L195)/2 + 2122 004f 09 .byte (.L193-.L195)/2 + 2123 0050 09 .byte (.L193-.L195)/2 + 2124 0051 3D .byte (.L198-.L195)/2 + 2125 0052 09 .byte (.L193-.L195)/2 + 2126 0053 09 .byte (.L193-.L195)/2 + 2127 0054 09 .byte (.L193-.L195)/2 + 2128 0055 09 .byte (.L193-.L195)/2 + 2129 0056 09 .byte (.L193-.L195)/2 + 2130 0057 09 .byte (.L193-.L195)/2 + 2131 0058 09 .byte (.L193-.L195)/2 + 2132 0059 33 .byte (.L197-.L195)/2 + 2133 005a 09 .byte (.L193-.L195)/2 + 2134 005b 2E .byte (.L196-.L195)/2 + 2135 005c 09 .byte (.L193-.L195)/2 + 2136 005d 09 .byte (.L193-.L195)/2 + 2137 005e 29 .byte (.L194-.L195)/2 + 2138 005f 00 .p2align 1 + 2139 .L193: + 2140 .LVL219: + 612:Core/Src/printf.c **** + 2141 .loc 1 612 13 is_stmt 1 view .LVU580 + 615:Core/Src/printf.c **** if (_is_digit(*format)) { + 2142 .loc 1 615 5 view .LVU581 + 616:Core/Src/printf.c **** width = _atoi(&format); + 2143 .loc 1 616 5 view .LVU582 + 2144 .LBB33: + 2145 .LBI33: + 181:Core/Src/printf.c **** { + 2146 .loc 1 181 20 view .LVU583 + ARM GAS /tmp/ccibzHy5.s page 58 + + + 2147 .LBB34: + 183:Core/Src/printf.c **** } + 2148 .loc 1 183 3 view .LVU584 + 183:Core/Src/printf.c **** } + 2149 .loc 1 183 22 is_stmt 0 view .LVU585 + 2150 0060 A1F13003 sub r3, r1, #48 + 2151 0064 DBB2 uxtb r3, r3 + 2152 .LVL220: + 183:Core/Src/printf.c **** } + 2153 .loc 1 183 22 view .LVU586 + 2154 .LBE34: + 2155 .LBE33: + 616:Core/Src/printf.c **** width = _atoi(&format); + 2156 .loc 1 616 8 view .LVU587 + 2157 0066 092B cmp r3, #9 + 2158 0068 33D9 bls .L285 + 619:Core/Src/printf.c **** const int w = va_arg(va, int); + 2159 .loc 1 619 10 is_stmt 1 view .LVU588 + 619:Core/Src/printf.c **** const int w = va_arg(va, int); + 2160 .loc 1 619 13 is_stmt 0 view .LVU589 + 2161 006a 2A29 cmp r1, #42 + 2162 006c 36D0 beq .L286 + 615:Core/Src/printf.c **** if (_is_digit(*format)) { + 2163 .loc 1 615 11 view .LVU590 + 2164 006e 0023 movs r3, #0 + 2165 0070 0A93 str r3, [sp, #40] + 2166 .LVL221: + 2167 .L203: + 632:Core/Src/printf.c **** if (*format == '.') { + 2168 .loc 1 632 5 is_stmt 1 view .LVU591 + 633:Core/Src/printf.c **** flags |= FLAGS_PRECISION; + 2169 .loc 1 633 5 view .LVU592 + 633:Core/Src/printf.c **** flags |= FLAGS_PRECISION; + 2170 .loc 1 633 9 is_stmt 0 view .LVU593 + 2171 0072 0D9B ldr r3, [sp, #52] + 2172 0074 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 633:Core/Src/printf.c **** flags |= FLAGS_PRECISION; + 2173 .loc 1 633 8 view .LVU594 + 2174 0076 2E2A cmp r2, #46 + 2175 0078 40D0 beq .L287 + 632:Core/Src/printf.c **** if (*format == '.') { + 2176 .loc 1 632 15 view .LVU595 + 2177 007a 4FF0000B mov fp, #0 + 2178 .LVL222: + 2179 .L206: + 647:Core/Src/printf.c **** case 'l' : + 2180 .loc 1 647 5 is_stmt 1 view .LVU596 + 647:Core/Src/printf.c **** case 'l' : + 2181 .loc 1 647 13 is_stmt 0 view .LVU597 + 2182 007e 0D9A ldr r2, [sp, #52] + 2183 0080 1378 ldrb r3, [r2] @ zero_extendqisi2 + 2184 0082 683B subs r3, r3, #104 + 2185 0084 122B cmp r3, #18 + 2186 0086 77D8 bhi .L208 + 2187 0088 DFE803F0 tbb [pc, r3] + 2188 .L210: + 2189 008c 64 .byte (.L214-.L210)/2 + ARM GAS /tmp/ccibzHy5.s page 59 + + + 2190 008d 76 .byte (.L208-.L210)/2 + 2191 008e D3 .byte (.L213-.L210)/2 + 2192 008f 76 .byte (.L208-.L210)/2 + 2193 0090 56 .byte (.L212-.L210)/2 + 2194 0091 76 .byte (.L208-.L210)/2 + 2195 0092 76 .byte (.L208-.L210)/2 + 2196 0093 76 .byte (.L208-.L210)/2 + 2197 0094 76 .byte (.L208-.L210)/2 + 2198 0095 76 .byte (.L208-.L210)/2 + 2199 0096 76 .byte (.L208-.L210)/2 + 2200 0097 76 .byte (.L208-.L210)/2 + 2201 0098 72 .byte (.L211-.L210)/2 + 2202 0099 76 .byte (.L208-.L210)/2 + 2203 009a 76 .byte (.L208-.L210)/2 + 2204 009b 76 .byte (.L208-.L210)/2 + 2205 009c 76 .byte (.L208-.L210)/2 + 2206 009d 76 .byte (.L208-.L210)/2 + 2207 009e D8 .byte (.L209-.L210)/2 + 2208 .LVL223: + 2209 009f 00 .p2align 1 + 2210 .L194: + 605:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 2211 .loc 1 605 19 is_stmt 1 view .LVU598 + 605:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 2212 .loc 1 605 25 is_stmt 0 view .LVU599 + 2213 00a0 45F00105 orr r5, r5, #1 + 2214 .LVL224: + 605:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 2215 .loc 1 605 43 is_stmt 1 view .LVU600 + 605:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 2216 .loc 1 605 49 is_stmt 0 view .LVU601 + 2217 00a4 0133 adds r3, r3, #1 + 2218 00a6 0D93 str r3, [sp, #52] + 605:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 2219 .loc 1 605 53 is_stmt 1 view .LVU602 + 2220 .LVL225: + 605:Core/Src/printf.c **** case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + 2221 .loc 1 605 61 view .LVU603 + 612:Core/Src/printf.c **** + 2222 .loc 1 612 13 view .LVU604 + 2223 00a8 C9E7 b .L192 + 2224 .LVL226: + 2225 .L196: + 606:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 2226 .loc 1 606 19 view .LVU605 + 606:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 2227 .loc 1 606 25 is_stmt 0 view .LVU606 + 2228 00aa 45F00205 orr r5, r5, #2 + 2229 .LVL227: + 606:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 2230 .loc 1 606 43 is_stmt 1 view .LVU607 + 606:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 2231 .loc 1 606 49 is_stmt 0 view .LVU608 + 2232 00ae 0133 adds r3, r3, #1 + 2233 00b0 0D93 str r3, [sp, #52] + 606:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 2234 .loc 1 606 53 is_stmt 1 view .LVU609 + ARM GAS /tmp/ccibzHy5.s page 60 + + + 2235 .LVL228: + 606:Core/Src/printf.c **** case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + 2236 .loc 1 606 61 view .LVU610 + 612:Core/Src/printf.c **** + 2237 .loc 1 612 13 view .LVU611 + 2238 00b2 C4E7 b .L192 + 2239 .LVL229: + 2240 .L197: + 607:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 2241 .loc 1 607 19 view .LVU612 + 607:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 2242 .loc 1 607 25 is_stmt 0 view .LVU613 + 2243 00b4 45F00405 orr r5, r5, #4 + 2244 .LVL230: + 607:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 2245 .loc 1 607 43 is_stmt 1 view .LVU614 + 607:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 2246 .loc 1 607 49 is_stmt 0 view .LVU615 + 2247 00b8 0133 adds r3, r3, #1 + 2248 00ba 0D93 str r3, [sp, #52] + 607:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 2249 .loc 1 607 53 is_stmt 1 view .LVU616 + 2250 .LVL231: + 607:Core/Src/printf.c **** case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + 2251 .loc 1 607 61 view .LVU617 + 612:Core/Src/printf.c **** + 2252 .loc 1 612 13 view .LVU618 + 2253 00bc BFE7 b .L192 + 2254 .LVL232: + 2255 .L199: + 608:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 2256 .loc 1 608 19 view .LVU619 + 608:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 2257 .loc 1 608 25 is_stmt 0 view .LVU620 + 2258 00be 45F00805 orr r5, r5, #8 + 2259 .LVL233: + 608:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 2260 .loc 1 608 43 is_stmt 1 view .LVU621 + 608:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 2261 .loc 1 608 49 is_stmt 0 view .LVU622 + 2262 00c2 0133 adds r3, r3, #1 + 2263 00c4 0D93 str r3, [sp, #52] + 608:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 2264 .loc 1 608 53 is_stmt 1 view .LVU623 + 2265 .LVL234: + 608:Core/Src/printf.c **** case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + 2266 .loc 1 608 61 view .LVU624 + 612:Core/Src/printf.c **** + 2267 .loc 1 612 13 view .LVU625 + 2268 00c6 BAE7 b .L192 + 2269 .LVL235: + 2270 .L198: + 609:Core/Src/printf.c **** default : n = 0U; break; + 2271 .loc 1 609 19 view .LVU626 + 609:Core/Src/printf.c **** default : n = 0U; break; + 2272 .loc 1 609 25 is_stmt 0 view .LVU627 + 2273 00c8 45F01005 orr r5, r5, #16 + ARM GAS /tmp/ccibzHy5.s page 61 + + + 2274 .LVL236: + 609:Core/Src/printf.c **** default : n = 0U; break; + 2275 .loc 1 609 43 is_stmt 1 view .LVU628 + 609:Core/Src/printf.c **** default : n = 0U; break; + 2276 .loc 1 609 49 is_stmt 0 view .LVU629 + 2277 00cc 0133 adds r3, r3, #1 + 2278 00ce 0D93 str r3, [sp, #52] + 609:Core/Src/printf.c **** default : n = 0U; break; + 2279 .loc 1 609 53 is_stmt 1 view .LVU630 + 2280 .LVL237: + 609:Core/Src/printf.c **** default : n = 0U; break; + 2281 .loc 1 609 61 view .LVU631 + 612:Core/Src/printf.c **** + 2282 .loc 1 612 13 view .LVU632 + 2283 00d0 B5E7 b .L192 + 2284 .LVL238: + 2285 .L285: + 617:Core/Src/printf.c **** } + 2286 .loc 1 617 7 view .LVU633 + 617:Core/Src/printf.c **** } + 2287 .loc 1 617 15 is_stmt 0 view .LVU634 + 2288 00d2 0DA8 add r0, sp, #52 + 2289 00d4 FFF7FEFF bl _atoi + 2290 .LVL239: + 2291 00d8 0A90 str r0, [sp, #40] + 2292 .LVL240: + 617:Core/Src/printf.c **** } + 2293 .loc 1 617 15 view .LVU635 + 2294 00da CAE7 b .L203 + 2295 .LVL241: + 2296 .L286: + 2297 .LBB35: + 620:Core/Src/printf.c **** if (w < 0) { + 2298 .loc 1 620 7 is_stmt 1 view .LVU636 + 620:Core/Src/printf.c **** if (w < 0) { + 2299 .loc 1 620 17 is_stmt 0 view .LVU637 + 2300 00dc 189B ldr r3, [sp, #96] + 2301 00de 1A1D adds r2, r3, #4 + 2302 00e0 1892 str r2, [sp, #96] + 2303 00e2 1868 ldr r0, [r3] + 621:Core/Src/printf.c **** flags |= FLAGS_LEFT; // reverse padding + 2304 .loc 1 621 7 is_stmt 1 view .LVU638 + 621:Core/Src/printf.c **** flags |= FLAGS_LEFT; // reverse padding + 2305 .loc 1 621 10 is_stmt 0 view .LVU639 + 2306 00e4 0028 cmp r0, #0 + 2307 00e6 04DB blt .L288 + 626:Core/Src/printf.c **** } + 2308 .loc 1 626 9 is_stmt 1 view .LVU640 + 626:Core/Src/printf.c **** } + 2309 .loc 1 626 15 is_stmt 0 view .LVU641 + 2310 00e8 0A90 str r0, [sp, #40] + 2311 .LVL242: + 2312 .L205: + 628:Core/Src/printf.c **** } + 2313 .loc 1 628 7 is_stmt 1 view .LVU642 + 628:Core/Src/printf.c **** } + 2314 .loc 1 628 13 is_stmt 0 view .LVU643 + ARM GAS /tmp/ccibzHy5.s page 62 + + + 2315 00ea 0D9B ldr r3, [sp, #52] + 2316 00ec 0133 adds r3, r3, #1 + 2317 00ee 0D93 str r3, [sp, #52] + 2318 00f0 BFE7 b .L203 + 2319 .LVL243: + 2320 .L288: + 622:Core/Src/printf.c **** width = (unsigned int)-w; + 2321 .loc 1 622 9 is_stmt 1 view .LVU644 + 622:Core/Src/printf.c **** width = (unsigned int)-w; + 2322 .loc 1 622 15 is_stmt 0 view .LVU645 + 2323 00f2 45F00205 orr r5, r5, #2 + 2324 .LVL244: + 623:Core/Src/printf.c **** } + 2325 .loc 1 623 9 is_stmt 1 view .LVU646 + 623:Core/Src/printf.c **** } + 2326 .loc 1 623 31 is_stmt 0 view .LVU647 + 2327 00f6 4342 rsbs r3, r0, #0 + 2328 00f8 0A93 str r3, [sp, #40] + 2329 .LVL245: + 623:Core/Src/printf.c **** } + 2330 .loc 1 623 31 view .LVU648 + 2331 00fa F6E7 b .L205 + 2332 .LVL246: + 2333 .L287: + 623:Core/Src/printf.c **** } + 2334 .loc 1 623 31 view .LVU649 + 2335 .LBE35: + 634:Core/Src/printf.c **** format++; + 2336 .loc 1 634 7 is_stmt 1 view .LVU650 + 634:Core/Src/printf.c **** format++; + 2337 .loc 1 634 13 is_stmt 0 view .LVU651 + 2338 00fc 45F48065 orr r5, r5, #1024 + 2339 .LVL247: + 635:Core/Src/printf.c **** if (_is_digit(*format)) { + 2340 .loc 1 635 7 is_stmt 1 view .LVU652 + 635:Core/Src/printf.c **** if (_is_digit(*format)) { + 2341 .loc 1 635 13 is_stmt 0 view .LVU653 + 2342 0100 5A1C adds r2, r3, #1 + 2343 0102 0D92 str r2, [sp, #52] + 636:Core/Src/printf.c **** precision = _atoi(&format); + 2344 .loc 1 636 7 is_stmt 1 view .LVU654 + 636:Core/Src/printf.c **** precision = _atoi(&format); + 2345 .loc 1 636 11 is_stmt 0 view .LVU655 + 2346 0104 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 + 2347 .LVL248: + 2348 .LBB36: + 2349 .LBI36: + 181:Core/Src/printf.c **** { + 2350 .loc 1 181 20 is_stmt 1 view .LVU656 + 2351 .LBB37: + 183:Core/Src/printf.c **** } + 2352 .loc 1 183 3 view .LVU657 + 183:Core/Src/printf.c **** } + 2353 .loc 1 183 22 is_stmt 0 view .LVU658 + 2354 0106 A2F13003 sub r3, r2, #48 + 2355 010a DBB2 uxtb r3, r3 + 2356 .LVL249: + ARM GAS /tmp/ccibzHy5.s page 63 + + + 183:Core/Src/printf.c **** } + 2357 .loc 1 183 22 view .LVU659 + 2358 .LBE37: + 2359 .LBE36: + 636:Core/Src/printf.c **** precision = _atoi(&format); + 2360 .loc 1 636 10 view .LVU660 + 2361 010c 092B cmp r3, #9 + 2362 010e 04D9 bls .L289 + 639:Core/Src/printf.c **** const int prec = (int)va_arg(va, int); + 2363 .loc 1 639 12 is_stmt 1 view .LVU661 + 639:Core/Src/printf.c **** const int prec = (int)va_arg(va, int); + 2364 .loc 1 639 15 is_stmt 0 view .LVU662 + 2365 0110 2A2A cmp r2, #42 + 2366 0112 07D0 beq .L290 + 632:Core/Src/printf.c **** if (*format == '.') { + 2367 .loc 1 632 15 view .LVU663 + 2368 0114 4FF0000B mov fp, #0 + 2369 0118 B1E7 b .L206 + 2370 .L289: + 637:Core/Src/printf.c **** } + 2371 .loc 1 637 9 is_stmt 1 view .LVU664 + 637:Core/Src/printf.c **** } + 2372 .loc 1 637 21 is_stmt 0 view .LVU665 + 2373 011a 0DA8 add r0, sp, #52 + 2374 011c FFF7FEFF bl _atoi + 2375 .LVL250: + 2376 0120 8346 mov fp, r0 + 2377 .LVL251: + 637:Core/Src/printf.c **** } + 2378 .loc 1 637 21 view .LVU666 + 2379 0122 ACE7 b .L206 + 2380 .LVL252: + 2381 .L290: + 2382 .LBB38: + 640:Core/Src/printf.c **** precision = prec > 0 ? (unsigned int)prec : 0U; + 2383 .loc 1 640 9 is_stmt 1 view .LVU667 + 640:Core/Src/printf.c **** precision = prec > 0 ? (unsigned int)prec : 0U; + 2384 .loc 1 640 19 is_stmt 0 view .LVU668 + 2385 0124 189B ldr r3, [sp, #96] + 2386 0126 1A1D adds r2, r3, #4 + 2387 0128 1892 str r2, [sp, #96] + 2388 012a 1B68 ldr r3, [r3] + 641:Core/Src/printf.c **** format++; + 2389 .loc 1 641 9 is_stmt 1 view .LVU669 + 641:Core/Src/printf.c **** format++; + 2390 .loc 1 641 51 is_stmt 0 view .LVU670 + 2391 012c 23EAE37B bic fp, r3, r3, asr #31 + 2392 .LVL253: + 642:Core/Src/printf.c **** } + 2393 .loc 1 642 9 is_stmt 1 view .LVU671 + 642:Core/Src/printf.c **** } + 2394 .loc 1 642 15 is_stmt 0 view .LVU672 + 2395 0130 0D9B ldr r3, [sp, #52] + 2396 0132 0133 adds r3, r3, #1 + 2397 0134 0D93 str r3, [sp, #52] + 2398 0136 A2E7 b .L206 + 2399 .L212: + ARM GAS /tmp/ccibzHy5.s page 64 + + + 642:Core/Src/printf.c **** } + 2400 .loc 1 642 15 view .LVU673 + 2401 .LBE38: + 649:Core/Src/printf.c **** format++; + 2402 .loc 1 649 9 is_stmt 1 view .LVU674 + 649:Core/Src/printf.c **** format++; + 2403 .loc 1 649 15 is_stmt 0 view .LVU675 + 2404 0138 45F48071 orr r1, r5, #256 + 2405 .LVL254: + 650:Core/Src/printf.c **** if (*format == 'l') { + 2406 .loc 1 650 9 is_stmt 1 view .LVU676 + 650:Core/Src/printf.c **** if (*format == 'l') { + 2407 .loc 1 650 15 is_stmt 0 view .LVU677 + 2408 013c 531C adds r3, r2, #1 + 2409 013e 0D93 str r3, [sp, #52] + 651:Core/Src/printf.c **** flags |= FLAGS_LONG_LONG; + 2410 .loc 1 651 9 is_stmt 1 view .LVU678 + 651:Core/Src/printf.c **** flags |= FLAGS_LONG_LONG; + 2411 .loc 1 651 13 is_stmt 0 view .LVU679 + 2412 0140 5278 ldrb r2, [r2, #1] @ zero_extendqisi2 + 651:Core/Src/printf.c **** flags |= FLAGS_LONG_LONG; + 2413 .loc 1 651 12 view .LVU680 + 2414 0142 6C2A cmp r2, #108 + 2415 0144 01D0 beq .L291 + 649:Core/Src/printf.c **** format++; + 2416 .loc 1 649 15 view .LVU681 + 2417 0146 0D46 mov r5, r1 + 2418 0148 16E0 b .L208 + 2419 .L291: + 652:Core/Src/printf.c **** format++; + 2420 .loc 1 652 11 is_stmt 1 view .LVU682 + 652:Core/Src/printf.c **** format++; + 2421 .loc 1 652 17 is_stmt 0 view .LVU683 + 2422 014a 45F44075 orr r5, r5, #768 + 2423 .LVL255: + 653:Core/Src/printf.c **** } + 2424 .loc 1 653 11 is_stmt 1 view .LVU684 + 653:Core/Src/printf.c **** } + 2425 .loc 1 653 17 is_stmt 0 view .LVU685 + 2426 014e 0133 adds r3, r3, #1 + 2427 0150 0D93 str r3, [sp, #52] + 2428 0152 11E0 b .L208 + 2429 .L214: + 657:Core/Src/printf.c **** format++; + 2430 .loc 1 657 9 is_stmt 1 view .LVU686 + 657:Core/Src/printf.c **** format++; + 2431 .loc 1 657 15 is_stmt 0 view .LVU687 + 2432 0154 45F08001 orr r1, r5, #128 + 2433 .LVL256: + 658:Core/Src/printf.c **** if (*format == 'h') { + 2434 .loc 1 658 9 is_stmt 1 view .LVU688 + 658:Core/Src/printf.c **** if (*format == 'h') { + 2435 .loc 1 658 15 is_stmt 0 view .LVU689 + 2436 0158 531C adds r3, r2, #1 + 2437 015a 0D93 str r3, [sp, #52] + 659:Core/Src/printf.c **** flags |= FLAGS_CHAR; + 2438 .loc 1 659 9 is_stmt 1 view .LVU690 + ARM GAS /tmp/ccibzHy5.s page 65 + + + 659:Core/Src/printf.c **** flags |= FLAGS_CHAR; + 2439 .loc 1 659 13 is_stmt 0 view .LVU691 + 2440 015c 5278 ldrb r2, [r2, #1] @ zero_extendqisi2 + 659:Core/Src/printf.c **** flags |= FLAGS_CHAR; + 2441 .loc 1 659 12 view .LVU692 + 2442 015e 682A cmp r2, #104 + 2443 0160 01D0 beq .L292 + 657:Core/Src/printf.c **** format++; + 2444 .loc 1 657 15 view .LVU693 + 2445 0162 0D46 mov r5, r1 + 2446 0164 08E0 b .L208 + 2447 .L292: + 660:Core/Src/printf.c **** format++; + 2448 .loc 1 660 11 is_stmt 1 view .LVU694 + 660:Core/Src/printf.c **** format++; + 2449 .loc 1 660 17 is_stmt 0 view .LVU695 + 2450 0166 45F0C005 orr r5, r5, #192 + 2451 .LVL257: + 661:Core/Src/printf.c **** } + 2452 .loc 1 661 11 is_stmt 1 view .LVU696 + 661:Core/Src/printf.c **** } + 2453 .loc 1 661 17 is_stmt 0 view .LVU697 + 2454 016a 0133 adds r3, r3, #1 + 2455 016c 0D93 str r3, [sp, #52] + 2456 016e 03E0 b .L208 + 2457 .L211: + 666:Core/Src/printf.c **** format++; + 2458 .loc 1 666 9 is_stmt 1 view .LVU698 + 666:Core/Src/printf.c **** format++; + 2459 .loc 1 666 15 is_stmt 0 view .LVU699 + 2460 0170 45F48075 orr r5, r5, #256 + 2461 .LVL258: + 667:Core/Src/printf.c **** break; + 2462 .loc 1 667 9 is_stmt 1 view .LVU700 + 667:Core/Src/printf.c **** break; + 2463 .loc 1 667 15 is_stmt 0 view .LVU701 + 2464 0174 0132 adds r2, r2, #1 + 2465 0176 0D92 str r2, [sp, #52] + 668:Core/Src/printf.c **** #endif + 2466 .loc 1 668 9 is_stmt 1 view .LVU702 + 2467 .L208: + 683:Core/Src/printf.c **** case 'd' : + 2468 .loc 1 683 5 view .LVU703 + 683:Core/Src/printf.c **** case 'd' : + 2469 .loc 1 683 13 is_stmt 0 view .LVU704 + 2470 0178 0D9B ldr r3, [sp, #52] + 2471 017a 1878 ldrb r0, [r3] @ zero_extendqisi2 + 2472 017c A0F12503 sub r3, r0, #37 + 2473 0180 532B cmp r3, #83 + 2474 0182 00F25F82 bhi .L215 + 2475 0186 DFE813F0 tbh [pc, r3, lsl #1] + 2476 .L217: + 2477 018a 5202 .2byte (.L223-.L217)/2 + 2478 018c 5D02 .2byte (.L215-.L217)/2 + 2479 018e 5D02 .2byte (.L215-.L217)/2 + 2480 0190 5D02 .2byte (.L215-.L217)/2 + 2481 0192 5D02 .2byte (.L215-.L217)/2 + ARM GAS /tmp/ccibzHy5.s page 66 + + + 2482 0194 5D02 .2byte (.L215-.L217)/2 + 2483 0196 5D02 .2byte (.L215-.L217)/2 + 2484 0198 5D02 .2byte (.L215-.L217)/2 + 2485 019a 5D02 .2byte (.L215-.L217)/2 + 2486 019c 5D02 .2byte (.L215-.L217)/2 + 2487 019e 5D02 .2byte (.L215-.L217)/2 + 2488 01a0 5D02 .2byte (.L215-.L217)/2 + 2489 01a2 5D02 .2byte (.L215-.L217)/2 + 2490 01a4 5D02 .2byte (.L215-.L217)/2 + 2491 01a6 5D02 .2byte (.L215-.L217)/2 + 2492 01a8 5D02 .2byte (.L215-.L217)/2 + 2493 01aa 5D02 .2byte (.L215-.L217)/2 + 2494 01ac 5D02 .2byte (.L215-.L217)/2 + 2495 01ae 5D02 .2byte (.L215-.L217)/2 + 2496 01b0 5D02 .2byte (.L215-.L217)/2 + 2497 01b2 5D02 .2byte (.L215-.L217)/2 + 2498 01b4 5D02 .2byte (.L215-.L217)/2 + 2499 01b6 5D02 .2byte (.L215-.L217)/2 + 2500 01b8 5D02 .2byte (.L215-.L217)/2 + 2501 01ba 5D02 .2byte (.L215-.L217)/2 + 2502 01bc 5D02 .2byte (.L215-.L217)/2 + 2503 01be 5D02 .2byte (.L215-.L217)/2 + 2504 01c0 5D02 .2byte (.L215-.L217)/2 + 2505 01c2 5D02 .2byte (.L215-.L217)/2 + 2506 01c4 5D02 .2byte (.L215-.L217)/2 + 2507 01c6 5D02 .2byte (.L215-.L217)/2 + 2508 01c8 5D02 .2byte (.L215-.L217)/2 + 2509 01ca 6D01 .2byte (.L220-.L217)/2 + 2510 01cc 4F01 .2byte (.L221-.L217)/2 + 2511 01ce 6D01 .2byte (.L220-.L217)/2 + 2512 01d0 5D02 .2byte (.L215-.L217)/2 + 2513 01d2 5D02 .2byte (.L215-.L217)/2 + 2514 01d4 5D02 .2byte (.L215-.L217)/2 + 2515 01d6 5D02 .2byte (.L215-.L217)/2 + 2516 01d8 5D02 .2byte (.L215-.L217)/2 + 2517 01da 5D02 .2byte (.L215-.L217)/2 + 2518 01dc 5D02 .2byte (.L215-.L217)/2 + 2519 01de 5D02 .2byte (.L215-.L217)/2 + 2520 01e0 5D02 .2byte (.L215-.L217)/2 + 2521 01e2 5D02 .2byte (.L215-.L217)/2 + 2522 01e4 5D02 .2byte (.L215-.L217)/2 + 2523 01e6 5D02 .2byte (.L215-.L217)/2 + 2524 01e8 5D02 .2byte (.L215-.L217)/2 + 2525 01ea 5D02 .2byte (.L215-.L217)/2 + 2526 01ec 5D02 .2byte (.L215-.L217)/2 + 2527 01ee 5D02 .2byte (.L215-.L217)/2 + 2528 01f0 5E00 .2byte (.L216-.L217)/2 + 2529 01f2 5D02 .2byte (.L215-.L217)/2 + 2530 01f4 5D02 .2byte (.L215-.L217)/2 + 2531 01f6 5D02 .2byte (.L215-.L217)/2 + 2532 01f8 5D02 .2byte (.L215-.L217)/2 + 2533 01fa 5D02 .2byte (.L215-.L217)/2 + 2534 01fc 5D02 .2byte (.L215-.L217)/2 + 2535 01fe 5D02 .2byte (.L215-.L217)/2 + 2536 0200 5D02 .2byte (.L215-.L217)/2 + 2537 0202 5D02 .2byte (.L215-.L217)/2 + 2538 0204 5E00 .2byte (.L216-.L217)/2 + ARM GAS /tmp/ccibzHy5.s page 67 + + + 2539 0206 9901 .2byte (.L222-.L217)/2 + 2540 0208 5E00 .2byte (.L216-.L217)/2 + 2541 020a 6D01 .2byte (.L220-.L217)/2 + 2542 020c 4F01 .2byte (.L221-.L217)/2 + 2543 020e 6D01 .2byte (.L220-.L217)/2 + 2544 0210 5D02 .2byte (.L215-.L217)/2 + 2545 0212 5E00 .2byte (.L216-.L217)/2 + 2546 0214 5D02 .2byte (.L215-.L217)/2 + 2547 0216 5D02 .2byte (.L215-.L217)/2 + 2548 0218 5D02 .2byte (.L215-.L217)/2 + 2549 021a 5D02 .2byte (.L215-.L217)/2 + 2550 021c 5D02 .2byte (.L215-.L217)/2 + 2551 021e 5E00 .2byte (.L216-.L217)/2 + 2552 0220 3702 .2byte (.L219-.L217)/2 + 2553 0222 5D02 .2byte (.L215-.L217)/2 + 2554 0224 5D02 .2byte (.L215-.L217)/2 + 2555 0226 D201 .2byte (.L218-.L217)/2 + 2556 0228 5D02 .2byte (.L215-.L217)/2 + 2557 022a 5E00 .2byte (.L216-.L217)/2 + 2558 022c 5D02 .2byte (.L215-.L217)/2 + 2559 022e 5D02 .2byte (.L215-.L217)/2 + 2560 0230 5E00 .2byte (.L216-.L217)/2 + 2561 .p2align 1 + 2562 .L213: + 671:Core/Src/printf.c **** format++; + 2563 .loc 1 671 9 is_stmt 1 view .LVU705 + 671:Core/Src/printf.c **** format++; + 2564 .loc 1 671 15 is_stmt 0 view .LVU706 + 2565 0232 45F40075 orr r5, r5, #512 + 2566 .LVL259: + 672:Core/Src/printf.c **** break; + 2567 .loc 1 672 9 is_stmt 1 view .LVU707 + 672:Core/Src/printf.c **** break; + 2568 .loc 1 672 15 is_stmt 0 view .LVU708 + 2569 0236 0132 adds r2, r2, #1 + 2570 0238 0D92 str r2, [sp, #52] + 673:Core/Src/printf.c **** case 'z' : + 2571 .loc 1 673 9 is_stmt 1 view .LVU709 + 2572 023a 9DE7 b .L208 + 2573 .L209: + 675:Core/Src/printf.c **** format++; + 2574 .loc 1 675 9 view .LVU710 + 675:Core/Src/printf.c **** format++; + 2575 .loc 1 675 15 is_stmt 0 view .LVU711 + 2576 023c 45F48075 orr r5, r5, #256 + 2577 .LVL260: + 676:Core/Src/printf.c **** break; + 2578 .loc 1 676 9 is_stmt 1 view .LVU712 + 676:Core/Src/printf.c **** break; + 2579 .loc 1 676 15 is_stmt 0 view .LVU713 + 2580 0240 0132 adds r2, r2, #1 + 2581 0242 0D92 str r2, [sp, #52] + 677:Core/Src/printf.c **** default : + 2582 .loc 1 677 9 is_stmt 1 view .LVU714 + 2583 0244 98E7 b .L208 + 2584 .L216: + 2585 .LBB39: + ARM GAS /tmp/ccibzHy5.s page 68 + + + 692:Core/Src/printf.c **** if (*format == 'x' || *format == 'X') { + 2586 .loc 1 692 9 view .LVU715 + 693:Core/Src/printf.c **** base = 16U; + 2587 .loc 1 693 9 view .LVU716 + 693:Core/Src/printf.c **** base = 16U; + 2588 .loc 1 693 12 is_stmt 0 view .LVU717 + 2589 0246 5828 cmp r0, #88 + 2590 0248 18BF it ne + 2591 024a 7828 cmpne r0, #120 + 2592 024c 07D0 beq .L274 + 696:Core/Src/printf.c **** base = 8U; + 2593 .loc 1 696 14 is_stmt 1 view .LVU718 + 696:Core/Src/printf.c **** base = 8U; + 2594 .loc 1 696 17 is_stmt 0 view .LVU719 + 2595 024e 6F28 cmp r0, #111 + 2596 0250 3CD0 beq .L275 + 699:Core/Src/printf.c **** base = 2U; + 2597 .loc 1 699 14 is_stmt 1 view .LVU720 + 699:Core/Src/printf.c **** base = 2U; + 2598 .loc 1 699 17 is_stmt 0 view .LVU721 + 2599 0252 6228 cmp r0, #98 + 2600 0254 3CD0 beq .L276 + 703:Core/Src/printf.c **** flags &= ~FLAGS_HASH; // no hash for dec format + 2601 .loc 1 703 11 is_stmt 1 view .LVU722 + 2602 .LVL261: + 704:Core/Src/printf.c **** } + 2603 .loc 1 704 11 view .LVU723 + 704:Core/Src/printf.c **** } + 2604 .loc 1 704 17 is_stmt 0 view .LVU724 + 2605 0256 25F01005 bic r5, r5, #16 + 2606 .LVL262: + 703:Core/Src/printf.c **** flags &= ~FLAGS_HASH; // no hash for dec format + 2607 .loc 1 703 16 view .LVU725 + 2608 025a 0A23 movs r3, #10 + 2609 025c 00E0 b .L224 + 2610 .LVL263: + 2611 .L274: + 694:Core/Src/printf.c **** } + 2612 .loc 1 694 16 view .LVU726 + 2613 025e 1023 movs r3, #16 + 2614 .L224: + 2615 .LVL264: + 707:Core/Src/printf.c **** flags |= FLAGS_UPPERCASE; + 2616 .loc 1 707 9 is_stmt 1 view .LVU727 + 707:Core/Src/printf.c **** flags |= FLAGS_UPPERCASE; + 2617 .loc 1 707 12 is_stmt 0 view .LVU728 + 2618 0260 5828 cmp r0, #88 + 2619 0262 37D0 beq .L293 + 2620 .L225: + 712:Core/Src/printf.c **** flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + 2621 .loc 1 712 9 is_stmt 1 view .LVU729 + 712:Core/Src/printf.c **** flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + 2622 .loc 1 712 12 is_stmt 0 view .LVU730 + 2623 0264 6928 cmp r0, #105 + 2624 0266 18BF it ne + 2625 0268 6428 cmpne r0, #100 + 2626 026a 01D0 beq .L226 + ARM GAS /tmp/ccibzHy5.s page 69 + + + 713:Core/Src/printf.c **** } + 2627 .loc 1 713 11 is_stmt 1 view .LVU731 + 713:Core/Src/printf.c **** } + 2628 .loc 1 713 17 is_stmt 0 view .LVU732 + 2629 026c 25F00C05 bic r5, r5, #12 + 2630 .LVL265: + 2631 .L226: + 717:Core/Src/printf.c **** flags &= ~FLAGS_ZEROPAD; + 2632 .loc 1 717 9 is_stmt 1 view .LVU733 + 717:Core/Src/printf.c **** flags &= ~FLAGS_ZEROPAD; + 2633 .loc 1 717 12 is_stmt 0 view .LVU734 + 2634 0270 15F4806F tst r5, #1024 + 2635 0274 01D0 beq .L227 + 718:Core/Src/printf.c **** } + 2636 .loc 1 718 11 is_stmt 1 view .LVU735 + 718:Core/Src/printf.c **** } + 2637 .loc 1 718 17 is_stmt 0 view .LVU736 + 2638 0276 25F00105 bic r5, r5, #1 + 2639 .LVL266: + 2640 .L227: + 722:Core/Src/printf.c **** // signed + 2641 .loc 1 722 9 is_stmt 1 view .LVU737 + 722:Core/Src/printf.c **** // signed + 2642 .loc 1 722 12 is_stmt 0 view .LVU738 + 2643 027a 6428 cmp r0, #100 + 2644 027c 18BF it ne + 2645 027e 6928 cmpne r0, #105 + 2646 0280 76D1 bne .L228 + 724:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 2647 .loc 1 724 11 is_stmt 1 view .LVU739 + 724:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 2648 .loc 1 724 14 is_stmt 0 view .LVU740 + 2649 0282 15F4007F tst r5, #512 + 2650 0286 28D1 bne .L294 + 730:Core/Src/printf.c **** const long value = va_arg(va, long); + 2651 .loc 1 730 16 is_stmt 1 view .LVU741 + 730:Core/Src/printf.c **** const long value = va_arg(va, long); + 2652 .loc 1 730 19 is_stmt 0 view .LVU742 + 2653 0288 15F4807F tst r5, #256 + 2654 028c 49D1 bne .L295 + 2655 .LBB40: + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2656 .loc 1 735 13 is_stmt 1 view .LVU743 + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2657 .loc 1 735 76 is_stmt 0 view .LVU744 + 2658 028e 15F0400F tst r5, #64 + 2659 0292 5FD0 beq .L233 + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2660 .loc 1 735 60 view .LVU745 + 2661 0294 189A ldr r2, [sp, #96] + 2662 0296 111D adds r1, r2, #4 + 2663 0298 1891 str r1, [sp, #96] + 2664 029a 1278 ldrb r2, [r2] @ zero_extendqisi2 + 2665 .L234: + 2666 .LVL267: + 736:Core/Src/printf.c **** } + 2667 .loc 1 736 13 is_stmt 1 discriminator 8 view .LVU746 + ARM GAS /tmp/ccibzHy5.s page 70 + + + 736:Core/Src/printf.c **** } + 2668 .loc 1 736 56 is_stmt 0 discriminator 8 view .LVU747 + 2669 029c 82EAE271 eor r1, r2, r2, asr #31 + 2670 02a0 A1EBE271 sub r1, r1, r2, asr #31 + 736:Core/Src/printf.c **** } + 2671 .loc 1 736 19 discriminator 8 view .LVU748 + 2672 02a4 0595 str r5, [sp, #20] + 2673 02a6 0A98 ldr r0, [sp, #40] + 2674 02a8 0490 str r0, [sp, #16] + 2675 02aa CDF80CB0 str fp, [sp, #12] + 2676 02ae 0293 str r3, [sp, #8] + 2677 02b0 D20F lsrs r2, r2, #31 + 2678 .LVL268: + 736:Core/Src/printf.c **** } + 2679 .loc 1 736 19 discriminator 8 view .LVU749 + 2680 02b2 0192 str r2, [sp, #4] + 2681 02b4 0091 str r1, [sp] + 2682 02b6 3346 mov r3, r6 + 2683 .LVL269: + 736:Core/Src/printf.c **** } + 2684 .loc 1 736 19 discriminator 8 view .LVU750 + 2685 02b8 2246 mov r2, r4 + 2686 02ba 4146 mov r1, r8 + 2687 02bc 3846 mov r0, r7 + 2688 02be FFF7FEFF bl _ntoa_long + 2689 .LVL270: + 736:Core/Src/printf.c **** } + 2690 .loc 1 736 19 discriminator 8 view .LVU751 + 2691 02c2 0446 mov r4, r0 + 2692 .LVL271: + 2693 .L231: + 736:Core/Src/printf.c **** } + 2694 .loc 1 736 19 discriminator 8 view .LVU752 + 2695 .LBE40: + 754:Core/Src/printf.c **** break; + 2696 .loc 1 754 9 is_stmt 1 view .LVU753 + 754:Core/Src/printf.c **** break; + 2697 .loc 1 754 15 is_stmt 0 view .LVU754 + 2698 02c4 0D9B ldr r3, [sp, #52] + 2699 02c6 0133 adds r3, r3, #1 + 2700 02c8 0D93 str r3, [sp, #52] + 755:Core/Src/printf.c **** } + 2701 .loc 1 755 9 is_stmt 1 view .LVU755 + 2702 02ca A4E6 b .L265 + 2703 .LVL272: + 2704 .L275: + 697:Core/Src/printf.c **** } + 2705 .loc 1 697 16 is_stmt 0 view .LVU756 + 2706 02cc 0823 movs r3, #8 + 2707 02ce C7E7 b .L224 + 2708 .L276: + 700:Core/Src/printf.c **** } + 2709 .loc 1 700 16 view .LVU757 + 2710 02d0 0223 movs r3, #2 + 2711 02d2 C5E7 b .L224 + 2712 .LVL273: + 2713 .L293: + ARM GAS /tmp/ccibzHy5.s page 71 + + + 708:Core/Src/printf.c **** } + 2714 .loc 1 708 11 is_stmt 1 view .LVU758 + 708:Core/Src/printf.c **** } + 2715 .loc 1 708 17 is_stmt 0 view .LVU759 + 2716 02d4 45F02005 orr r5, r5, #32 + 2717 .LVL274: + 708:Core/Src/printf.c **** } + 2718 .loc 1 708 17 view .LVU760 + 2719 02d8 C4E7 b .L225 + 2720 .L294: + 2721 .LBB41: + 726:Core/Src/printf.c **** idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value + 2722 .loc 1 726 13 is_stmt 1 view .LVU761 + 726:Core/Src/printf.c **** idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value + 2723 .loc 1 726 29 is_stmt 0 view .LVU762 + 2724 02da 189A ldr r2, [sp, #96] + 2725 02dc 0732 adds r2, r2, #7 + 2726 02de 22F00702 bic r2, r2, #7 + 2727 02e2 02F10801 add r1, r2, #8 + 2728 02e6 1891 str r1, [sp, #96] + 2729 02e8 5168 ldr r1, [r2, #4] + 727:Core/Src/printf.c **** #endif + 2730 .loc 1 727 13 is_stmt 1 view .LVU763 + 727:Core/Src/printf.c **** #endif + 2731 .loc 1 727 61 is_stmt 0 view .LVU764 + 2732 02ea 1268 ldr r2, [r2] + 2733 02ec 0846 mov r0, r1 + 2734 02ee 0029 cmp r1, #0 + 2735 02f0 13DB blt .L296 + 2736 .L230: + 727:Core/Src/printf.c **** #endif + 2737 .loc 1 727 19 view .LVU765 + 2738 02f2 0895 str r5, [sp, #32] + 2739 02f4 0A9D ldr r5, [sp, #40] + 2740 .LVL275: + 727:Core/Src/printf.c **** #endif + 2741 .loc 1 727 19 view .LVU766 + 2742 02f6 0795 str r5, [sp, #28] + 2743 02f8 CDF818B0 str fp, [sp, #24] + 2744 02fc 0493 str r3, [sp, #16] + 2745 02fe 0023 movs r3, #0 + 2746 .LVL276: + 727:Core/Src/printf.c **** #endif + 2747 .loc 1 727 19 view .LVU767 + 2748 0300 0593 str r3, [sp, #20] + 2749 0302 C90F lsrs r1, r1, #31 + 2750 0304 0291 str r1, [sp, #8] + 2751 0306 0092 str r2, [sp] + 2752 0308 0190 str r0, [sp, #4] + 2753 030a 3346 mov r3, r6 + 2754 030c 2246 mov r2, r4 + 2755 030e 4146 mov r1, r8 + 2756 0310 3846 mov r0, r7 + 2757 0312 FFF7FEFF bl _ntoa_long_long + 2758 .LVL277: + 727:Core/Src/printf.c **** #endif + 2759 .loc 1 727 19 view .LVU768 + ARM GAS /tmp/ccibzHy5.s page 72 + + + 2760 0316 0446 mov r4, r0 + 2761 .LVL278: + 727:Core/Src/printf.c **** #endif + 2762 .loc 1 727 19 view .LVU769 + 2763 .LBE41: + 2764 0318 D4E7 b .L231 + 2765 .LVL279: + 2766 .L296: + 2767 .LBB42: + 727:Core/Src/printf.c **** #endif + 2768 .loc 1 727 61 view .LVU770 + 2769 031a 5242 negs r2, r2 + 2770 031c 61EB4100 sbc r0, r1, r1, lsl #1 + 2771 0320 E7E7 b .L230 + 2772 .L295: + 2773 .LBE42: + 2774 .LBB43: + 731:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - valu + 2775 .loc 1 731 13 is_stmt 1 view .LVU771 + 731:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - valu + 2776 .loc 1 731 24 is_stmt 0 view .LVU772 + 2777 0322 189A ldr r2, [sp, #96] + 2778 0324 111D adds r1, r2, #4 + 2779 0326 1891 str r1, [sp, #96] + 2780 0328 1268 ldr r2, [r2] + 732:Core/Src/printf.c **** } + 2781 .loc 1 732 13 is_stmt 1 view .LVU773 + 732:Core/Src/printf.c **** } + 2782 .loc 1 732 56 is_stmt 0 view .LVU774 + 2783 032a 82EAE271 eor r1, r2, r2, asr #31 + 2784 032e A1EBE271 sub r1, r1, r2, asr #31 + 732:Core/Src/printf.c **** } + 2785 .loc 1 732 19 view .LVU775 + 2786 0332 0595 str r5, [sp, #20] + 2787 0334 0A98 ldr r0, [sp, #40] + 2788 0336 0490 str r0, [sp, #16] + 2789 0338 CDF80CB0 str fp, [sp, #12] + 2790 033c 0293 str r3, [sp, #8] + 2791 033e D20F lsrs r2, r2, #31 + 2792 0340 0192 str r2, [sp, #4] + 2793 0342 0091 str r1, [sp] + 2794 0344 3346 mov r3, r6 + 2795 .LVL280: + 732:Core/Src/printf.c **** } + 2796 .loc 1 732 19 view .LVU776 + 2797 0346 2246 mov r2, r4 + 2798 0348 4146 mov r1, r8 + 2799 034a 3846 mov r0, r7 + 2800 034c FFF7FEFF bl _ntoa_long + 2801 .LVL281: + 732:Core/Src/printf.c **** } + 2802 .loc 1 732 19 view .LVU777 + 2803 0350 0446 mov r4, r0 + 2804 .LVL282: + 732:Core/Src/printf.c **** } + 2805 .loc 1 732 19 view .LVU778 + 2806 .LBE43: + ARM GAS /tmp/ccibzHy5.s page 73 + + + 2807 0352 B7E7 b .L231 + 2808 .LVL283: + 2809 .L233: + 2810 .LBB44: + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2811 .loc 1 735 129 discriminator 2 view .LVU779 + 2812 0354 15F0800F tst r5, #128 + 2813 0358 05D0 beq .L235 + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2814 .loc 1 735 113 view .LVU780 + 2815 035a 189A ldr r2, [sp, #96] + 2816 035c 111D adds r1, r2, #4 + 2817 035e 1891 str r1, [sp, #96] + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2818 .loc 1 735 102 view .LVU781 + 2819 0360 B2F90020 ldrsh r2, [r2] + 2820 0364 9AE7 b .L234 + 2821 .L235: + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2822 .loc 1 735 129 view .LVU782 + 2823 0366 189A ldr r2, [sp, #96] + 2824 0368 111D adds r1, r2, #4 + 2825 036a 1891 str r1, [sp, #96] + 2826 036c 1268 ldr r2, [r2] + 2827 036e 95E7 b .L234 + 2828 .L228: + 735:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value + 2829 .loc 1 735 129 view .LVU783 + 2830 .LBE44: + 741:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 2831 .loc 1 741 11 is_stmt 1 view .LVU784 + 741:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 2832 .loc 1 741 14 is_stmt 0 view .LVU785 + 2833 0370 15F4007F tst r5, #512 + 2834 0374 1AD1 bne .L297 + 746:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, prec + 2835 .loc 1 746 16 is_stmt 1 view .LVU786 + 746:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, prec + 2836 .loc 1 746 19 is_stmt 0 view .LVU787 + 2837 0376 15F4807F tst r5, #256 + 2838 037a 33D1 bne .L298 + 2839 .LBB45: + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2840 .loc 1 750 13 is_stmt 1 view .LVU788 + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2841 .loc 1 750 103 is_stmt 0 view .LVU789 + 2842 037c 15F0400F tst r5, #64 + 2843 0380 45D0 beq .L238 + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2844 .loc 1 750 78 view .LVU790 + 2845 0382 189A ldr r2, [sp, #96] + 2846 0384 111D adds r1, r2, #4 + 2847 0386 1891 str r1, [sp, #96] + 2848 0388 1278 ldrb r2, [r2] @ zero_extendqisi2 + 2849 .L239: + 2850 .LVL284: + 751:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 74 + + + 2851 .loc 1 751 13 is_stmt 1 discriminator 8 view .LVU791 + 751:Core/Src/printf.c **** } + 2852 .loc 1 751 19 is_stmt 0 discriminator 8 view .LVU792 + 2853 038a 0595 str r5, [sp, #20] + 2854 038c 0A99 ldr r1, [sp, #40] + 2855 038e 0491 str r1, [sp, #16] + 2856 0390 CDF80CB0 str fp, [sp, #12] + 2857 0394 0293 str r3, [sp, #8] + 2858 0396 0023 movs r3, #0 + 2859 .LVL285: + 751:Core/Src/printf.c **** } + 2860 .loc 1 751 19 discriminator 8 view .LVU793 + 2861 0398 0193 str r3, [sp, #4] + 2862 039a 0092 str r2, [sp] + 2863 039c 3346 mov r3, r6 + 2864 039e 2246 mov r2, r4 + 2865 .LVL286: + 751:Core/Src/printf.c **** } + 2866 .loc 1 751 19 discriminator 8 view .LVU794 + 2867 03a0 4146 mov r1, r8 + 2868 03a2 3846 mov r0, r7 + 2869 03a4 FFF7FEFF bl _ntoa_long + 2870 .LVL287: + 751:Core/Src/printf.c **** } + 2871 .loc 1 751 19 discriminator 8 view .LVU795 + 2872 03a8 0446 mov r4, r0 + 2873 .LVL288: + 751:Core/Src/printf.c **** } + 2874 .loc 1 751 19 discriminator 8 view .LVU796 + 2875 03aa 8BE7 b .L231 + 2876 .LVL289: + 2877 .L297: + 751:Core/Src/printf.c **** } + 2878 .loc 1 751 19 discriminator 8 view .LVU797 + 2879 .LBE45: + 743:Core/Src/printf.c **** #endif + 2880 .loc 1 743 13 is_stmt 1 view .LVU798 + 743:Core/Src/printf.c **** #endif + 2881 .loc 1 743 19 is_stmt 0 view .LVU799 + 2882 03ac 189A ldr r2, [sp, #96] + 2883 03ae 0732 adds r2, r2, #7 + 2884 03b0 22F00702 bic r2, r2, #7 + 2885 03b4 02F10801 add r1, r2, #8 + 2886 03b8 1891 str r1, [sp, #96] + 2887 03ba 0895 str r5, [sp, #32] + 2888 03bc 0A99 ldr r1, [sp, #40] + 2889 03be 0791 str r1, [sp, #28] + 2890 03c0 CDF818B0 str fp, [sp, #24] + 2891 03c4 0021 movs r1, #0 + 2892 03c6 0493 str r3, [sp, #16] + 2893 03c8 0591 str r1, [sp, #20] + 2894 03ca 0291 str r1, [sp, #8] + 2895 03cc D2E90023 ldrd r2, [r2] + 2896 03d0 CDE90023 strd r2, [sp] + 2897 03d4 3346 mov r3, r6 + 2898 .LVL290: + 743:Core/Src/printf.c **** #endif + ARM GAS /tmp/ccibzHy5.s page 75 + + + 2899 .loc 1 743 19 view .LVU800 + 2900 03d6 2246 mov r2, r4 + 2901 03d8 4146 mov r1, r8 + 2902 03da 3846 mov r0, r7 + 2903 03dc FFF7FEFF bl _ntoa_long_long + 2904 .LVL291: + 743:Core/Src/printf.c **** #endif + 2905 .loc 1 743 19 view .LVU801 + 2906 03e0 0446 mov r4, r0 + 2907 .LVL292: + 743:Core/Src/printf.c **** #endif + 2908 .loc 1 743 19 view .LVU802 + 2909 03e2 6FE7 b .L231 + 2910 .LVL293: + 2911 .L298: + 747:Core/Src/printf.c **** } + 2912 .loc 1 747 13 is_stmt 1 view .LVU803 + 747:Core/Src/printf.c **** } + 2913 .loc 1 747 19 is_stmt 0 view .LVU804 + 2914 03e4 189A ldr r2, [sp, #96] + 2915 03e6 111D adds r1, r2, #4 + 2916 03e8 1891 str r1, [sp, #96] + 2917 03ea 0595 str r5, [sp, #20] + 2918 03ec 0A99 ldr r1, [sp, #40] + 2919 03ee 0491 str r1, [sp, #16] + 2920 03f0 CDF80CB0 str fp, [sp, #12] + 2921 03f4 0293 str r3, [sp, #8] + 2922 03f6 0023 movs r3, #0 + 2923 .LVL294: + 747:Core/Src/printf.c **** } + 2924 .loc 1 747 19 view .LVU805 + 2925 03f8 0193 str r3, [sp, #4] + 2926 03fa 1368 ldr r3, [r2] + 2927 03fc 0093 str r3, [sp] + 2928 03fe 3346 mov r3, r6 + 2929 0400 2246 mov r2, r4 + 2930 0402 4146 mov r1, r8 + 2931 0404 3846 mov r0, r7 + 2932 0406 FFF7FEFF bl _ntoa_long + 2933 .LVL295: + 747:Core/Src/printf.c **** } + 2934 .loc 1 747 19 view .LVU806 + 2935 040a 0446 mov r4, r0 + 2936 .LVL296: + 747:Core/Src/printf.c **** } + 2937 .loc 1 747 19 view .LVU807 + 2938 040c 5AE7 b .L231 + 2939 .LVL297: + 2940 .L238: + 2941 .LBB46: + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2942 .loc 1 750 174 discriminator 2 view .LVU808 + 2943 040e 15F0800F tst r5, #128 + 2944 0412 04D0 beq .L240 + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2945 .loc 1 750 149 view .LVU809 + 2946 0414 189A ldr r2, [sp, #96] + ARM GAS /tmp/ccibzHy5.s page 76 + + + 2947 0416 111D adds r1, r2, #4 + 2948 0418 1891 str r1, [sp, #96] + 2949 041a 1288 ldrh r2, [r2] + 2950 041c B5E7 b .L239 + 2951 .L240: + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2952 .loc 1 750 174 view .LVU810 + 2953 041e 189A ldr r2, [sp, #96] + 2954 0420 111D adds r1, r2, #4 + 2955 0422 1891 str r1, [sp, #96] + 2956 0424 1268 ldr r2, [r2] + 2957 0426 B0E7 b .L239 + 2958 .LVL298: + 2959 .L221: + 750:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags) + 2960 .loc 1 750 174 view .LVU811 + 2961 .LBE46: + 2962 .LBE39: + 760:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 2963 .loc 1 760 9 is_stmt 1 view .LVU812 + 760:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 2964 .loc 1 760 12 is_stmt 0 view .LVU813 + 2965 0428 4628 cmp r0, #70 + 2966 042a 18D0 beq .L299 + 2967 .L241: + 761:Core/Src/printf.c **** format++; + 2968 .loc 1 761 9 is_stmt 1 view .LVU814 + 761:Core/Src/printf.c **** format++; + 2969 .loc 1 761 15 is_stmt 0 view .LVU815 + 2970 042c 189B ldr r3, [sp, #96] + 2971 042e 0733 adds r3, r3, #7 + 2972 0430 23F00703 bic r3, r3, #7 + 2973 0434 03F10802 add r2, r3, #8 + 2974 0438 1892 str r2, [sp, #96] + 2975 043a 93ED000B vldr.64 d0, [r3] + 2976 043e 0295 str r5, [sp, #8] + 2977 0440 0A9B ldr r3, [sp, #40] + 2978 0442 0193 str r3, [sp, #4] + 2979 0444 CDF800B0 str fp, [sp] + 2980 0448 3346 mov r3, r6 + 2981 044a 2246 mov r2, r4 + 2982 044c 4146 mov r1, r8 + 2983 044e 3846 mov r0, r7 + 2984 0450 FFF7FEFF bl _ftoa + 2985 .LVL299: + 2986 0454 0446 mov r4, r0 + 2987 .LVL300: + 762:Core/Src/printf.c **** break; + 2988 .loc 1 762 9 is_stmt 1 view .LVU816 + 762:Core/Src/printf.c **** break; + 2989 .loc 1 762 15 is_stmt 0 view .LVU817 + 2990 0456 0D9B ldr r3, [sp, #52] + 2991 0458 0133 adds r3, r3, #1 + 2992 045a 0D93 str r3, [sp, #52] + 763:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_EXPONENTIAL) + 2993 .loc 1 763 9 is_stmt 1 view .LVU818 + 2994 045c DBE5 b .L265 + ARM GAS /tmp/ccibzHy5.s page 77 + + + 2995 .LVL301: + 2996 .L299: + 760:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 2997 .loc 1 760 29 discriminator 1 view .LVU819 + 760:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 2998 .loc 1 760 35 is_stmt 0 discriminator 1 view .LVU820 + 2999 045e 45F02005 orr r5, r5, #32 + 3000 .LVL302: + 760:Core/Src/printf.c **** idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 3001 .loc 1 760 35 discriminator 1 view .LVU821 + 3002 0462 E3E7 b .L241 + 3003 .L220: + 769:Core/Src/printf.c **** if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + 3004 .loc 1 769 9 is_stmt 1 view .LVU822 + 769:Core/Src/printf.c **** if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + 3005 .loc 1 769 29 is_stmt 0 view .LVU823 + 3006 0464 4728 cmp r0, #71 + 3007 0466 14BF ite ne + 3008 0468 0023 movne r3, #0 + 3009 046a 0123 moveq r3, #1 + 3010 046c 6728 cmp r0, #103 + 3011 046e 14BF ite ne + 3012 0470 1A46 movne r2, r3 + 3013 0472 43F00102 orreq r2, r3, #1 + 769:Core/Src/printf.c **** if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + 3014 .loc 1 769 12 view .LVU824 + 3015 0476 0AB1 cbz r2, .L242 + 769:Core/Src/printf.c **** if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + 3016 .loc 1 769 49 is_stmt 1 discriminator 1 view .LVU825 + 769:Core/Src/printf.c **** if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + 3017 .loc 1 769 55 is_stmt 0 discriminator 1 view .LVU826 + 3018 0478 45F40065 orr r5, r5, #2048 + 3019 .LVL303: + 3020 .L242: + 770:Core/Src/printf.c **** idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 3021 .loc 1 770 9 is_stmt 1 view .LVU827 + 770:Core/Src/printf.c **** idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 3022 .loc 1 770 29 is_stmt 0 view .LVU828 + 3023 047c 4528 cmp r0, #69 + 3024 047e 08BF it eq + 3025 0480 43F00103 orreq r3, r3, #1 + 770:Core/Src/printf.c **** idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 3026 .loc 1 770 12 view .LVU829 + 3027 0484 0BB1 cbz r3, .L243 + 770:Core/Src/printf.c **** idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 3028 .loc 1 770 49 is_stmt 1 discriminator 1 view .LVU830 + 770:Core/Src/printf.c **** idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + 3029 .loc 1 770 55 is_stmt 0 discriminator 1 view .LVU831 + 3030 0486 45F02005 orr r5, r5, #32 + 3031 .LVL304: + 3032 .L243: + 771:Core/Src/printf.c **** format++; + 3033 .loc 1 771 9 is_stmt 1 view .LVU832 + 771:Core/Src/printf.c **** format++; + 3034 .loc 1 771 15 is_stmt 0 view .LVU833 + 3035 048a 189B ldr r3, [sp, #96] + 3036 048c 0733 adds r3, r3, #7 + ARM GAS /tmp/ccibzHy5.s page 78 + + + 3037 048e 23F00703 bic r3, r3, #7 + 3038 0492 03F10802 add r2, r3, #8 + 3039 0496 1892 str r2, [sp, #96] + 3040 0498 93ED000B vldr.64 d0, [r3] + 3041 049c 0295 str r5, [sp, #8] + 3042 049e 0A9B ldr r3, [sp, #40] + 3043 04a0 0193 str r3, [sp, #4] + 3044 04a2 CDF800B0 str fp, [sp] + 3045 04a6 3346 mov r3, r6 + 3046 04a8 2246 mov r2, r4 + 3047 04aa 4146 mov r1, r8 + 3048 04ac 3846 mov r0, r7 + 3049 04ae FFF7FEFF bl _etoa + 3050 .LVL305: + 3051 04b2 0446 mov r4, r0 + 3052 .LVL306: + 772:Core/Src/printf.c **** break; + 3053 .loc 1 772 9 is_stmt 1 view .LVU834 + 772:Core/Src/printf.c **** break; + 3054 .loc 1 772 15 is_stmt 0 view .LVU835 + 3055 04b4 0D9B ldr r3, [sp, #52] + 3056 04b6 0133 adds r3, r3, #1 + 3057 04b8 0D93 str r3, [sp, #52] + 773:Core/Src/printf.c **** #endif // PRINTF_SUPPORT_EXPONENTIAL + 3058 .loc 1 773 9 is_stmt 1 view .LVU836 + 3059 04ba ACE5 b .L265 + 3060 .LVL307: + 3061 .L222: + 3062 .LBB47: + 777:Core/Src/printf.c **** // pre padding + 3063 .loc 1 777 9 view .LVU837 + 779:Core/Src/printf.c **** while (l++ < width) { + 3064 .loc 1 779 9 view .LVU838 + 779:Core/Src/printf.c **** while (l++ < width) { + 3065 .loc 1 779 12 is_stmt 0 view .LVU839 + 3066 04bc 15F00205 ands r5, r5, #2 + 3067 .LVL308: + 779:Core/Src/printf.c **** while (l++ < width) { + 3068 .loc 1 779 12 view .LVU840 + 3069 04c0 1FD0 beq .L277 + 777:Core/Src/printf.c **** // pre padding + 3070 .loc 1 777 22 view .LVU841 + 3071 04c2 4FF00109 mov r9, #1 + 3072 .LVL309: + 3073 .L245: + 785:Core/Src/printf.c **** // post padding + 3074 .loc 1 785 9 is_stmt 1 view .LVU842 + 785:Core/Src/printf.c **** // post padding + 3075 .loc 1 785 19 is_stmt 0 view .LVU843 + 3076 04c6 1898 ldr r0, [sp, #96] + 3077 04c8 031D adds r3, r0, #4 + 3078 04ca 1893 str r3, [sp, #96] + 785:Core/Src/printf.c **** // post padding + 3079 .loc 1 785 9 view .LVU844 + 3080 04cc 04F1010A add r10, r4, #1 + 3081 .LVL310: + 785:Core/Src/printf.c **** // post padding + ARM GAS /tmp/ccibzHy5.s page 79 + + + 3082 .loc 1 785 9 view .LVU845 + 3083 04d0 3346 mov r3, r6 + 3084 04d2 2246 mov r2, r4 + 3085 04d4 4146 mov r1, r8 + 3086 04d6 0078 ldrb r0, [r0] @ zero_extendqisi2 + 3087 04d8 B847 blx r7 + 3088 .LVL311: + 787:Core/Src/printf.c **** while (l++ < width) { + 3089 .loc 1 787 9 is_stmt 1 view .LVU846 + 787:Core/Src/printf.c **** while (l++ < width) { + 3090 .loc 1 787 12 is_stmt 0 view .LVU847 + 3091 04da BDB9 cbnz r5, .L300 + 3092 .LVL312: + 3093 .L248: + 792:Core/Src/printf.c **** break; + 3094 .loc 1 792 9 is_stmt 1 view .LVU848 + 792:Core/Src/printf.c **** break; + 3095 .loc 1 792 15 is_stmt 0 view .LVU849 + 3096 04dc 0D9B ldr r3, [sp, #52] + 3097 04de 0133 adds r3, r3, #1 + 3098 04e0 0D93 str r3, [sp, #52] + 3099 .loc 1 793 9 is_stmt 1 view .LVU850 + 3100 04e2 5446 mov r4, r10 + 3101 04e4 97E5 b .L265 + 3102 .LVL313: + 3103 .L246: + 781:Core/Src/printf.c **** } + 3104 .loc 1 781 13 view .LVU851 + 3105 04e6 02F1010A add r10, r2, #1 + 3106 .LVL314: + 781:Core/Src/printf.c **** } + 3107 .loc 1 781 13 is_stmt 0 view .LVU852 + 3108 04ea 3346 mov r3, r6 + 3109 04ec 4146 mov r1, r8 + 3110 04ee 2020 movs r0, #32 + 3111 04f0 B847 blx r7 + 3112 .LVL315: + 780:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3113 .loc 1 780 19 view .LVU853 + 3114 04f2 4B46 mov r3, r9 + 781:Core/Src/printf.c **** } + 3115 .loc 1 781 13 view .LVU854 + 3116 04f4 5246 mov r2, r10 + 3117 .LVL316: + 3118 .L244: + 780:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3119 .loc 1 780 17 is_stmt 1 view .LVU855 + 780:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3120 .loc 1 780 19 is_stmt 0 view .LVU856 + 3121 04f6 03F10109 add r9, r3, #1 + 3122 .LVL317: + 780:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3123 .loc 1 780 17 view .LVU857 + 3124 04fa 9B45 cmp fp, r3 + 3125 04fc F3D8 bhi .L246 + 780:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3126 .loc 1 780 17 view .LVU858 + ARM GAS /tmp/ccibzHy5.s page 80 + + + 3127 04fe 1446 mov r4, r2 + 3128 0500 E1E7 b .L245 + 3129 .LVL318: + 3130 .L277: + 777:Core/Src/printf.c **** // pre padding + 3131 .loc 1 777 22 view .LVU859 + 3132 0502 0123 movs r3, #1 + 3133 0504 DDF828B0 ldr fp, [sp, #40] + 3134 .LVL319: + 777:Core/Src/printf.c **** // pre padding + 3135 .loc 1 777 22 view .LVU860 + 3136 0508 2246 mov r2, r4 + 3137 050a F4E7 b .L244 + 3138 .LVL320: + 3139 .L300: + 777:Core/Src/printf.c **** // pre padding + 3140 .loc 1 777 22 view .LVU861 + 3141 050c 5246 mov r2, r10 + 3142 050e DDF828A0 ldr r10, [sp, #40] + 3143 .LVL321: + 777:Core/Src/printf.c **** // pre padding + 3144 .loc 1 777 22 view .LVU862 + 3145 0512 06E0 b .L247 + 3146 .LVL322: + 3147 .L249: + 789:Core/Src/printf.c **** } + 3148 .loc 1 789 13 is_stmt 1 view .LVU863 + 3149 0514 551C adds r5, r2, #1 + 3150 .LVL323: + 789:Core/Src/printf.c **** } + 3151 .loc 1 789 13 is_stmt 0 view .LVU864 + 3152 0516 3346 mov r3, r6 + 3153 0518 4146 mov r1, r8 + 3154 051a 2020 movs r0, #32 + 3155 051c B847 blx r7 + 3156 .LVL324: + 788:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3157 .loc 1 788 19 view .LVU865 + 3158 051e A146 mov r9, r4 + 789:Core/Src/printf.c **** } + 3159 .loc 1 789 13 view .LVU866 + 3160 0520 2A46 mov r2, r5 + 3161 .LVL325: + 3162 .L247: + 788:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3163 .loc 1 788 17 is_stmt 1 view .LVU867 + 788:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3164 .loc 1 788 19 is_stmt 0 view .LVU868 + 3165 0522 09F10104 add r4, r9, #1 + 3166 .LVL326: + 788:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3167 .loc 1 788 17 view .LVU869 + 3168 0526 CA45 cmp r10, r9 + 3169 0528 F4D8 bhi .L249 + 788:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3170 .loc 1 788 17 view .LVU870 + 3171 052a 9246 mov r10, r2 + ARM GAS /tmp/ccibzHy5.s page 81 + + + 3172 052c D6E7 b .L248 + 3173 .LVL327: + 3174 .L218: + 788:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3175 .loc 1 788 17 view .LVU871 + 3176 .LBE47: + 3177 .LBB48: + 794:Core/Src/printf.c **** } + 795:Core/Src/printf.c **** + 796:Core/Src/printf.c **** case 's' : { + 797:Core/Src/printf.c **** const char* p = va_arg(va, char*); + 3178 .loc 1 797 9 is_stmt 1 view .LVU872 + 3179 .loc 1 797 21 is_stmt 0 view .LVU873 + 3180 052e 189B ldr r3, [sp, #96] + 3181 0530 1A1D adds r2, r3, #4 + 3182 0532 1892 str r2, [sp, #96] + 3183 0534 D3F800A0 ldr r10, [r3] + 798:Core/Src/printf.c **** unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1); + 3184 .loc 1 798 9 is_stmt 1 view .LVU874 + 3185 .loc 1 798 26 is_stmt 0 view .LVU875 + 3186 0538 BBF1000F cmp fp, #0 + 3187 053c 1ED1 bne .L250 + 3188 053e 4FF0FF33 mov r3, #-1 + 3189 .L251: + 3190 0542 D146 mov r9, r10 + 3191 0544 02E0 b .L252 + 3192 .LVL328: + 3193 .L254: + 3194 .LBB49: + 3195 .LBB50: + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3196 .loc 1 174 38 is_stmt 1 view .LVU876 + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3197 .loc 1 174 34 view .LVU877 + 3198 0546 09F10109 add r9, r9, #1 + 3199 .LVL329: + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3200 .loc 1 174 30 is_stmt 0 view .LVU878 + 3201 054a 1346 mov r3, r2 + 3202 .LVL330: + 3203 .L252: + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3204 .loc 1 174 17 is_stmt 1 view .LVU879 + 3205 054c 99F80020 ldrb r2, [r9] @ zero_extendqisi2 + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3206 .loc 1 174 3 is_stmt 0 view .LVU880 + 3207 0550 12B1 cbz r2, .L253 + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3208 .loc 1 174 30 view .LVU881 + 3209 0552 5A1E subs r2, r3, #1 + 3210 .LVL331: + 174:Core/Src/printf.c **** return (unsigned int)(s - str); + 3211 .loc 1 174 20 view .LVU882 + 3212 0554 002B cmp r3, #0 + 3213 0556 F6D1 bne .L254 + 3214 .LVL332: + 3215 .L253: + ARM GAS /tmp/ccibzHy5.s page 82 + + + 175:Core/Src/printf.c **** } + 3216 .loc 1 175 3 is_stmt 1 view .LVU883 + 175:Core/Src/printf.c **** } + 3217 .loc 1 175 27 is_stmt 0 view .LVU884 + 3218 0558 A9EB0A09 sub r9, r9, r10 + 3219 .LVL333: + 175:Core/Src/printf.c **** } + 3220 .loc 1 175 27 view .LVU885 + 3221 .LBE50: + 3222 .LBE49: + 799:Core/Src/printf.c **** // pre padding + 800:Core/Src/printf.c **** if (flags & FLAGS_PRECISION) { + 3223 .loc 1 800 9 is_stmt 1 view .LVU886 + 3224 .loc 1 800 12 is_stmt 0 view .LVU887 + 3225 055c 15F48063 ands r3, r5, #1024 + 3226 0560 0B93 str r3, [sp, #44] + 3227 0562 02D0 beq .L255 + 801:Core/Src/printf.c **** l = (l < precision ? l : precision); + 3228 .loc 1 801 11 is_stmt 1 view .LVU888 + 3229 .loc 1 801 13 is_stmt 0 view .LVU889 + 3230 0564 D945 cmp r9, fp + 3231 0566 28BF it cs + 3232 0568 D946 movcs r9, fp + 3233 .LVL334: + 3234 .L255: + 802:Core/Src/printf.c **** } + 803:Core/Src/printf.c **** if (!(flags & FLAGS_LEFT)) { + 3235 .loc 1 803 9 is_stmt 1 view .LVU890 + 3236 .loc 1 803 12 is_stmt 0 view .LVU891 + 3237 056a 15F00203 ands r3, r5, #2 + 3238 056e 0C93 str r3, [sp, #48] + 3239 0570 06D0 beq .L301 + 3240 .loc 1 803 12 view .LVU892 + 3241 0572 2246 mov r2, r4 + 3242 0574 5C46 mov r4, fp + 3243 .LVL335: + 3244 .loc 1 803 12 view .LVU893 + 3245 0576 B346 mov fp, r6 + 3246 .LVL336: + 3247 .loc 1 803 12 view .LVU894 + 3248 0578 0B9E ldr r6, [sp, #44] + 3249 .LVL337: + 3250 .loc 1 803 12 view .LVU895 + 3251 057a 1DE0 b .L259 + 3252 .LVL338: + 3253 .L250: + 798:Core/Src/printf.c **** // pre padding + 3254 .loc 1 798 26 view .LVU896 + 3255 057c 5B46 mov r3, fp + 3256 057e E0E7 b .L251 + 3257 .LVL339: + 3258 .L301: + 798:Core/Src/printf.c **** // pre padding + 3259 .loc 1 798 26 view .LVU897 + 3260 0580 2246 mov r2, r4 + 3261 0582 0A9C ldr r4, [sp, #40] + 3262 .LVL340: + ARM GAS /tmp/ccibzHy5.s page 83 + + + 798:Core/Src/printf.c **** // pre padding + 3263 .loc 1 798 26 view .LVU898 + 3264 0584 4B46 mov r3, r9 + 3265 0586 07E0 b .L256 + 3266 .LVL341: + 3267 .L258: + 804:Core/Src/printf.c **** while (l++ < width) { + 805:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 3268 .loc 1 805 13 is_stmt 1 view .LVU899 + 3269 0588 02F10109 add r9, r2, #1 + 3270 .LVL342: + 3271 .loc 1 805 13 is_stmt 0 view .LVU900 + 3272 058c 3346 mov r3, r6 + 3273 058e 4146 mov r1, r8 + 3274 0590 2020 movs r0, #32 + 3275 0592 B847 blx r7 + 3276 .LVL343: + 804:Core/Src/printf.c **** while (l++ < width) { + 3277 .loc 1 804 19 view .LVU901 + 3278 0594 2B46 mov r3, r5 + 3279 .loc 1 805 13 view .LVU902 + 3280 0596 4A46 mov r2, r9 + 3281 .LVL344: + 3282 .L256: + 804:Core/Src/printf.c **** while (l++ < width) { + 3283 .loc 1 804 17 is_stmt 1 view .LVU903 + 804:Core/Src/printf.c **** while (l++ < width) { + 3284 .loc 1 804 19 is_stmt 0 view .LVU904 + 3285 0598 5D1C adds r5, r3, #1 + 3286 .LVL345: + 804:Core/Src/printf.c **** while (l++ < width) { + 3287 .loc 1 804 17 view .LVU905 + 3288 059a 9C42 cmp r4, r3 + 3289 059c F4D8 bhi .L258 + 804:Core/Src/printf.c **** while (l++ < width) { + 3290 .loc 1 804 19 view .LVU906 + 3291 059e A946 mov r9, r5 + 3292 05a0 5C46 mov r4, fp + 3293 05a2 B346 mov fp, r6 + 3294 .LVL346: + 804:Core/Src/printf.c **** while (l++ < width) { + 3295 .loc 1 804 19 view .LVU907 + 3296 05a4 0B9E ldr r6, [sp, #44] + 3297 .LVL347: + 804:Core/Src/printf.c **** while (l++ < width) { + 3298 .loc 1 804 19 view .LVU908 + 3299 05a6 07E0 b .L259 + 3300 .LVL348: + 3301 .L278: + 806:Core/Src/printf.c **** } + 807:Core/Src/printf.c **** } + 808:Core/Src/printf.c **** // string output + 809:Core/Src/printf.c **** while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { + 3302 .loc 1 809 69 view .LVU909 + 3303 05a8 1C46 mov r4, r3 + 3304 .LVL349: + 3305 .L261: + ARM GAS /tmp/ccibzHy5.s page 84 + + + 810:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3306 .loc 1 810 11 is_stmt 1 view .LVU910 + 3307 .loc 1 810 18 is_stmt 0 view .LVU911 + 3308 05aa 0AF1010A add r10, r10, #1 + 3309 .LVL350: + 3310 .loc 1 810 11 view .LVU912 + 3311 05ae 551C adds r5, r2, #1 + 3312 .LVL351: + 3313 .loc 1 810 11 view .LVU913 + 3314 05b0 5B46 mov r3, fp + 3315 05b2 4146 mov r1, r8 + 3316 05b4 B847 blx r7 + 3317 .LVL352: + 3318 05b6 2A46 mov r2, r5 + 3319 .LVL353: + 3320 .L259: + 809:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3321 .loc 1 809 15 is_stmt 1 view .LVU914 + 809:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3322 .loc 1 809 17 is_stmt 0 view .LVU915 + 3323 05b8 9AF80000 ldrb r0, [r10] @ zero_extendqisi2 + 809:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3324 .loc 1 809 15 view .LVU916 + 3325 05bc 20B1 cbz r0, .L260 + 809:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3326 .loc 1 809 26 discriminator 1 view .LVU917 + 3327 05be 002E cmp r6, #0 + 3328 05c0 F3D0 beq .L261 + 809:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3329 .loc 1 809 69 discriminator 2 view .LVU918 + 3330 05c2 631E subs r3, r4, #1 + 3331 .LVL354: + 809:Core/Src/printf.c **** out(*(p++), buffer, idx++, maxlen); + 3332 .loc 1 809 57 discriminator 2 view .LVU919 + 3333 05c4 002C cmp r4, #0 + 3334 05c6 EFD1 bne .L278 + 3335 .LVL355: + 3336 .L260: + 811:Core/Src/printf.c **** } + 812:Core/Src/printf.c **** // post padding + 813:Core/Src/printf.c **** if (flags & FLAGS_LEFT) { + 3337 .loc 1 813 12 view .LVU920 + 3338 05c8 1446 mov r4, r2 + 3339 05ca 5E46 mov r6, fp + 3340 .loc 1 813 9 is_stmt 1 view .LVU921 + 3341 .loc 1 813 12 is_stmt 0 view .LVU922 + 3342 05cc 0C9B ldr r3, [sp, #48] + 3343 05ce 1BB9 cbnz r3, .L302 + 3344 .LVL356: + 3345 .L263: + 814:Core/Src/printf.c **** while (l++ < width) { + 815:Core/Src/printf.c **** out(' ', buffer, idx++, maxlen); + 816:Core/Src/printf.c **** } + 817:Core/Src/printf.c **** } + 818:Core/Src/printf.c **** format++; + 3346 .loc 1 818 9 is_stmt 1 view .LVU923 + 3347 .loc 1 818 15 is_stmt 0 view .LVU924 + ARM GAS /tmp/ccibzHy5.s page 85 + + + 3348 05d0 0D9B ldr r3, [sp, #52] + 3349 05d2 0133 adds r3, r3, #1 + 3350 05d4 0D93 str r3, [sp, #52] + 819:Core/Src/printf.c **** break; + 3351 .loc 1 819 9 is_stmt 1 view .LVU925 + 3352 05d6 1EE5 b .L265 + 3353 .LVL357: + 3354 .L302: + 3355 .loc 1 819 9 is_stmt 0 view .LVU926 + 3356 05d8 DDF828A0 ldr r10, [sp, #40] + 3357 .LVL358: + 3358 .loc 1 819 9 view .LVU927 + 3359 05dc 06E0 b .L262 + 3360 .LVL359: + 3361 .L264: + 815:Core/Src/printf.c **** } + 3362 .loc 1 815 13 is_stmt 1 view .LVU928 + 3363 05de 551C adds r5, r2, #1 + 3364 .LVL360: + 815:Core/Src/printf.c **** } + 3365 .loc 1 815 13 is_stmt 0 view .LVU929 + 3366 05e0 3346 mov r3, r6 + 3367 05e2 4146 mov r1, r8 + 3368 05e4 2020 movs r0, #32 + 3369 05e6 B847 blx r7 + 3370 .LVL361: + 814:Core/Src/printf.c **** while (l++ < width) { + 3371 .loc 1 814 19 view .LVU930 + 3372 05e8 A146 mov r9, r4 + 815:Core/Src/printf.c **** } + 3373 .loc 1 815 13 view .LVU931 + 3374 05ea 2A46 mov r2, r5 + 3375 .LVL362: + 3376 .L262: + 814:Core/Src/printf.c **** while (l++ < width) { + 3377 .loc 1 814 17 is_stmt 1 view .LVU932 + 814:Core/Src/printf.c **** while (l++ < width) { + 3378 .loc 1 814 19 is_stmt 0 view .LVU933 + 3379 05ec 09F10104 add r4, r9, #1 + 3380 .LVL363: + 814:Core/Src/printf.c **** while (l++ < width) { + 3381 .loc 1 814 17 view .LVU934 + 3382 05f0 CA45 cmp r10, r9 + 3383 05f2 F4D8 bhi .L264 + 814:Core/Src/printf.c **** while (l++ < width) { + 3384 .loc 1 814 17 view .LVU935 + 3385 05f4 1446 mov r4, r2 + 3386 .LVL364: + 814:Core/Src/printf.c **** while (l++ < width) { + 3387 .loc 1 814 17 view .LVU936 + 3388 05f6 EBE7 b .L263 + 3389 .LVL365: + 3390 .L219: + 814:Core/Src/printf.c **** while (l++ < width) { + 3391 .loc 1 814 17 view .LVU937 + 3392 .LBE48: + 3393 .LBB51: + ARM GAS /tmp/ccibzHy5.s page 86 + + + 820:Core/Src/printf.c **** } + 821:Core/Src/printf.c **** + 822:Core/Src/printf.c **** case 'p' : { + 823:Core/Src/printf.c **** width = sizeof(void*) * 2U; + 3394 .loc 1 823 9 is_stmt 1 view .LVU938 + 824:Core/Src/printf.c **** flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; + 3395 .loc 1 824 9 view .LVU939 + 3396 .loc 1 824 15 is_stmt 0 view .LVU940 + 3397 05f8 45F02105 orr r5, r5, #33 + 3398 .LVL366: + 825:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 826:Core/Src/printf.c **** const bool is_ll = sizeof(uintptr_t) == sizeof(long long); + 3399 .loc 1 826 9 is_stmt 1 view .LVU941 + 827:Core/Src/printf.c **** if (is_ll) { + 3400 .loc 1 827 9 view .LVU942 + 828:Core/Src/printf.c **** idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, + 829:Core/Src/printf.c **** } + 830:Core/Src/printf.c **** else { + 831:Core/Src/printf.c **** #endif + 832:Core/Src/printf.c **** idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), + 3401 .loc 1 832 11 view .LVU943 + 3402 .loc 1 832 81 is_stmt 0 view .LVU944 + 3403 05fc 189B ldr r3, [sp, #96] + 3404 05fe 1A1D adds r2, r3, #4 + 3405 0600 1892 str r2, [sp, #96] + 3406 0602 1B68 ldr r3, [r3] + 3407 .loc 1 832 17 view .LVU945 + 3408 0604 0595 str r5, [sp, #20] + 3409 0606 0822 movs r2, #8 + 3410 0608 0492 str r2, [sp, #16] + 3411 060a CDF80CB0 str fp, [sp, #12] + 3412 060e 1022 movs r2, #16 + 3413 0610 0292 str r2, [sp, #8] + 3414 0612 0022 movs r2, #0 + 3415 0614 0192 str r2, [sp, #4] + 3416 0616 0093 str r3, [sp] + 3417 0618 3346 mov r3, r6 + 3418 061a 2246 mov r2, r4 + 3419 061c 4146 mov r1, r8 + 3420 061e 3846 mov r0, r7 + 3421 0620 FFF7FEFF bl _ntoa_long + 3422 .LVL367: + 3423 0624 0446 mov r4, r0 + 3424 .LVL368: + 833:Core/Src/printf.c **** #if defined(PRINTF_SUPPORT_LONG_LONG) + 834:Core/Src/printf.c **** } + 835:Core/Src/printf.c **** #endif + 836:Core/Src/printf.c **** format++; + 3425 .loc 1 836 9 is_stmt 1 view .LVU946 + 3426 .loc 1 836 15 is_stmt 0 view .LVU947 + 3427 0626 0D9B ldr r3, [sp, #52] + 3428 0628 0133 adds r3, r3, #1 + 3429 062a 0D93 str r3, [sp, #52] + 837:Core/Src/printf.c **** break; + 3430 .loc 1 837 9 is_stmt 1 view .LVU948 + 3431 062c F3E4 b .L265 + 3432 .LVL369: + ARM GAS /tmp/ccibzHy5.s page 87 + + + 3433 .L223: + 3434 .loc 1 837 9 is_stmt 0 view .LVU949 + 3435 .LBE51: + 838:Core/Src/printf.c **** } + 839:Core/Src/printf.c **** + 840:Core/Src/printf.c **** case '%' : + 841:Core/Src/printf.c **** out('%', buffer, idx++, maxlen); + 3436 .loc 1 841 9 is_stmt 1 view .LVU950 + 3437 062e 651C adds r5, r4, #1 + 3438 .LVL370: + 3439 .loc 1 841 9 is_stmt 0 view .LVU951 + 3440 0630 3346 mov r3, r6 + 3441 0632 2246 mov r2, r4 + 3442 0634 4146 mov r1, r8 + 3443 0636 2520 movs r0, #37 + 3444 0638 B847 blx r7 + 3445 .LVL371: + 842:Core/Src/printf.c **** format++; + 3446 .loc 1 842 9 is_stmt 1 view .LVU952 + 3447 .loc 1 842 15 is_stmt 0 view .LVU953 + 3448 063a 0D9B ldr r3, [sp, #52] + 3449 063c 0133 adds r3, r3, #1 + 3450 063e 0D93 str r3, [sp, #52] + 843:Core/Src/printf.c **** break; + 3451 .loc 1 843 9 is_stmt 1 view .LVU954 + 841:Core/Src/printf.c **** format++; + 3452 .loc 1 841 9 is_stmt 0 view .LVU955 + 3453 0640 2C46 mov r4, r5 + 3454 .loc 1 843 9 view .LVU956 + 3455 0642 E8E4 b .L265 + 3456 .LVL372: + 3457 .L215: + 844:Core/Src/printf.c **** + 845:Core/Src/printf.c **** default : + 846:Core/Src/printf.c **** out(*format, buffer, idx++, maxlen); + 3458 .loc 1 846 9 is_stmt 1 view .LVU957 + 3459 0644 651C adds r5, r4, #1 + 3460 .LVL373: + 3461 .loc 1 846 9 is_stmt 0 view .LVU958 + 3462 0646 3346 mov r3, r6 + 3463 0648 2246 mov r2, r4 + 3464 064a 4146 mov r1, r8 + 3465 064c B847 blx r7 + 3466 .LVL374: + 847:Core/Src/printf.c **** format++; + 3467 .loc 1 847 9 is_stmt 1 view .LVU959 + 3468 .loc 1 847 15 is_stmt 0 view .LVU960 + 3469 064e 0D9B ldr r3, [sp, #52] + 3470 0650 0133 adds r3, r3, #1 + 3471 0652 0D93 str r3, [sp, #52] + 848:Core/Src/printf.c **** break; + 3472 .loc 1 848 9 is_stmt 1 view .LVU961 + 846:Core/Src/printf.c **** format++; + 3473 .loc 1 846 9 is_stmt 0 view .LVU962 + 3474 0654 2C46 mov r4, r5 + 3475 .loc 1 848 9 view .LVU963 + 3476 0656 DEE4 b .L265 + ARM GAS /tmp/ccibzHy5.s page 88 + + + 3477 .LVL375: + 3478 .L283: + 584:Core/Src/printf.c **** } + 3479 .loc 1 584 9 view .LVU964 + 3480 0658 074F ldr r7, .L303 + 3481 065a DBE4 b .L188 + 3482 .LVL376: + 3483 .L284: + 849:Core/Src/printf.c **** } + 850:Core/Src/printf.c **** } + 851:Core/Src/printf.c **** + 852:Core/Src/printf.c **** // termination + 853:Core/Src/printf.c **** out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); + 3484 .loc 1 853 3 is_stmt 1 view .LVU965 + 3485 065c B442 cmp r4, r6 + 3486 065e 01D3 bcc .L279 + 3487 .loc 1 853 3 is_stmt 0 discriminator 1 view .LVU966 + 3488 0660 721E subs r2, r6, #1 + 3489 0662 00E0 b .L267 + 3490 .L279: + 3491 .loc 1 853 3 view .LVU967 + 3492 0664 2246 mov r2, r4 + 3493 .L267: + 3494 .loc 1 853 3 discriminator 4 view .LVU968 + 3495 0666 3346 mov r3, r6 + 3496 0668 4146 mov r1, r8 + 3497 066a 0020 movs r0, #0 + 3498 066c B847 blx r7 + 3499 .LVL377: + 854:Core/Src/printf.c **** + 855:Core/Src/printf.c **** // return written chars without terminating \0 + 856:Core/Src/printf.c **** return (int)idx; + 3500 .loc 1 856 3 is_stmt 1 discriminator 4 view .LVU969 + 857:Core/Src/printf.c **** } + 3501 .loc 1 857 1 is_stmt 0 discriminator 4 view .LVU970 + 3502 066e 2046 mov r0, r4 + 3503 0670 0FB0 add sp, sp, #60 + 3504 .LCFI26: + 3505 .cfi_def_cfa_offset 36 + 3506 @ sp needed + 3507 0672 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 3508 .LVL378: + 3509 .L304: + 3510 .loc 1 857 1 discriminator 4 view .LVU971 + 3511 0676 00BF .align 2 + 3512 .L303: + 3513 0678 00000000 .word _out_null + 3514 .cfi_endproc + 3515 .LFE13: + 3517 .section .text._out_char,"ax",%progbits + 3518 .align 1 + 3519 .syntax unified + 3520 .thumb + 3521 .thumb_func + 3522 .fpu fpv5-d16 + 3524 _out_char: + 3525 .LVL379: + ARM GAS /tmp/ccibzHy5.s page 89 + + + 3526 .LFB2: + 150:Core/Src/printf.c **** (void)buffer; (void)idx; (void)maxlen; + 3527 .loc 1 150 1 is_stmt 1 view -0 + 3528 .cfi_startproc + 3529 @ args = 0, pretend = 0, frame = 0 + 3530 @ frame_needed = 0, uses_anonymous_args = 0 + 151:Core/Src/printf.c **** if (character) { + 3531 .loc 1 151 3 view .LVU973 + 151:Core/Src/printf.c **** if (character) { + 3532 .loc 1 151 17 view .LVU974 + 151:Core/Src/printf.c **** if (character) { + 3533 .loc 1 151 28 view .LVU975 + 152:Core/Src/printf.c **** _putchar(character); + 3534 .loc 1 152 3 view .LVU976 + 152:Core/Src/printf.c **** _putchar(character); + 3535 .loc 1 152 6 is_stmt 0 view .LVU977 + 3536 0000 00B9 cbnz r0, .L311 + 3537 0002 7047 bx lr + 3538 .L311: + 150:Core/Src/printf.c **** (void)buffer; (void)idx; (void)maxlen; + 3539 .loc 1 150 1 view .LVU978 + 3540 0004 08B5 push {r3, lr} + 3541 .LCFI27: + 3542 .cfi_def_cfa_offset 8 + 3543 .cfi_offset 3, -8 + 3544 .cfi_offset 14, -4 + 153:Core/Src/printf.c **** } + 3545 .loc 1 153 5 is_stmt 1 view .LVU979 + 3546 0006 FFF7FEFF bl _putchar + 3547 .LVL380: + 155:Core/Src/printf.c **** + 3548 .loc 1 155 1 is_stmt 0 view .LVU980 + 3549 000a 08BD pop {r3, pc} + 3550 .cfi_endproc + 3551 .LFE2: + 3553 .section .text.printf_,"ax",%progbits + 3554 .align 1 + 3555 .global printf_ + 3556 .syntax unified + 3557 .thumb + 3558 .thumb_func + 3559 .fpu fpv5-d16 + 3561 printf_: + 3562 .LVL381: + 3563 .LFB14: + 858:Core/Src/printf.c **** + 859:Core/Src/printf.c **** + 860:Core/Src/printf.c **** /////////////////////////////////////////////////////////////////////////////// + 861:Core/Src/printf.c **** + 862:Core/Src/printf.c **** int printf_(const char* format, ...) + 863:Core/Src/printf.c **** { + 3564 .loc 1 863 1 is_stmt 1 view -0 + 3565 .cfi_startproc + 3566 @ args = 4, pretend = 16, frame = 8 + 3567 @ frame_needed = 0, uses_anonymous_args = 1 + 3568 .loc 1 863 1 is_stmt 0 view .LVU982 + 3569 0000 0FB4 push {r0, r1, r2, r3} + ARM GAS /tmp/ccibzHy5.s page 90 + + + 3570 .LCFI28: + 3571 .cfi_def_cfa_offset 16 + 3572 .cfi_offset 0, -16 + 3573 .cfi_offset 1, -12 + 3574 .cfi_offset 2, -8 + 3575 .cfi_offset 3, -4 + 3576 0002 00B5 push {lr} + 3577 .LCFI29: + 3578 .cfi_def_cfa_offset 20 + 3579 .cfi_offset 14, -20 + 3580 0004 85B0 sub sp, sp, #20 + 3581 .LCFI30: + 3582 .cfi_def_cfa_offset 40 + 3583 0006 06AA add r2, sp, #24 + 3584 0008 52F8043B ldr r3, [r2], #4 + 864:Core/Src/printf.c **** va_list va; + 3585 .loc 1 864 3 is_stmt 1 view .LVU983 + 865:Core/Src/printf.c **** va_start(va, format); + 3586 .loc 1 865 3 view .LVU984 + 3587 000c 0392 str r2, [sp, #12] + 866:Core/Src/printf.c **** char buffer[1]; + 3588 .loc 1 866 3 view .LVU985 + 867:Core/Src/printf.c **** const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va); + 3589 .loc 1 867 3 view .LVU986 + 3590 .loc 1 867 19 is_stmt 0 view .LVU987 + 3591 000e 0092 str r2, [sp] + 3592 0010 4FF0FF32 mov r2, #-1 + 3593 0014 02A9 add r1, sp, #8 + 3594 0016 0448 ldr r0, .L314 + 3595 0018 FFF7FEFF bl _vsnprintf + 3596 .LVL382: + 868:Core/Src/printf.c **** va_end(va); + 3597 .loc 1 868 3 is_stmt 1 view .LVU988 + 869:Core/Src/printf.c **** return ret; + 3598 .loc 1 869 3 view .LVU989 + 870:Core/Src/printf.c **** } + 3599 .loc 1 870 1 is_stmt 0 view .LVU990 + 3600 001c 05B0 add sp, sp, #20 + 3601 .LCFI31: + 3602 .cfi_def_cfa_offset 20 + 3603 @ sp needed + 3604 001e 5DF804EB ldr lr, [sp], #4 + 3605 .LCFI32: + 3606 .cfi_restore 14 + 3607 .cfi_def_cfa_offset 16 + 3608 0022 04B0 add sp, sp, #16 + 3609 .LCFI33: + 3610 .cfi_restore 3 + 3611 .cfi_restore 2 + 3612 .cfi_restore 1 + 3613 .cfi_restore 0 + 3614 .cfi_def_cfa_offset 0 + 3615 0024 7047 bx lr + 3616 .L315: + 3617 0026 00BF .align 2 + 3618 .L314: + 3619 0028 00000000 .word _out_char + ARM GAS /tmp/ccibzHy5.s page 91 + + + 3620 .cfi_endproc + 3621 .LFE14: + 3623 .section .text.sprintf_,"ax",%progbits + 3624 .align 1 + 3625 .global sprintf_ + 3626 .syntax unified + 3627 .thumb + 3628 .thumb_func + 3629 .fpu fpv5-d16 + 3631 sprintf_: + 3632 .LVL383: + 3633 .LFB15: + 871:Core/Src/printf.c **** + 872:Core/Src/printf.c **** + 873:Core/Src/printf.c **** int sprintf_(char* buffer, const char* format, ...) + 874:Core/Src/printf.c **** { + 3634 .loc 1 874 1 is_stmt 1 view -0 + 3635 .cfi_startproc + 3636 @ args = 4, pretend = 12, frame = 8 + 3637 @ frame_needed = 0, uses_anonymous_args = 1 + 3638 .loc 1 874 1 is_stmt 0 view .LVU992 + 3639 0000 0EB4 push {r1, r2, r3} + 3640 .LCFI34: + 3641 .cfi_def_cfa_offset 12 + 3642 .cfi_offset 1, -12 + 3643 .cfi_offset 2, -8 + 3644 .cfi_offset 3, -4 + 3645 0002 00B5 push {lr} + 3646 .LCFI35: + 3647 .cfi_def_cfa_offset 16 + 3648 .cfi_offset 14, -16 + 3649 0004 84B0 sub sp, sp, #16 + 3650 .LCFI36: + 3651 .cfi_def_cfa_offset 32 + 3652 0006 0146 mov r1, r0 + 3653 0008 05AA add r2, sp, #20 + 3654 000a 52F8043B ldr r3, [r2], #4 + 875:Core/Src/printf.c **** va_list va; + 3655 .loc 1 875 3 is_stmt 1 view .LVU993 + 876:Core/Src/printf.c **** va_start(va, format); + 3656 .loc 1 876 3 view .LVU994 + 3657 000e 0392 str r2, [sp, #12] + 877:Core/Src/printf.c **** const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va); + 3658 .loc 1 877 3 view .LVU995 + 3659 .loc 1 877 19 is_stmt 0 view .LVU996 + 3660 0010 0092 str r2, [sp] + 3661 0012 4FF0FF32 mov r2, #-1 + 3662 0016 0448 ldr r0, .L318 + 3663 .LVL384: + 3664 .loc 1 877 19 view .LVU997 + 3665 0018 FFF7FEFF bl _vsnprintf + 3666 .LVL385: + 878:Core/Src/printf.c **** va_end(va); + 3667 .loc 1 878 3 is_stmt 1 view .LVU998 + 879:Core/Src/printf.c **** return ret; + 3668 .loc 1 879 3 view .LVU999 + 880:Core/Src/printf.c **** } + ARM GAS /tmp/ccibzHy5.s page 92 + + + 3669 .loc 1 880 1 is_stmt 0 view .LVU1000 + 3670 001c 04B0 add sp, sp, #16 + 3671 .LCFI37: + 3672 .cfi_def_cfa_offset 16 + 3673 @ sp needed + 3674 001e 5DF804EB ldr lr, [sp], #4 + 3675 .LCFI38: + 3676 .cfi_restore 14 + 3677 .cfi_def_cfa_offset 12 + 3678 0022 03B0 add sp, sp, #12 + 3679 .LCFI39: + 3680 .cfi_restore 3 + 3681 .cfi_restore 2 + 3682 .cfi_restore 1 + 3683 .cfi_def_cfa_offset 0 + 3684 0024 7047 bx lr + 3685 .L319: + 3686 0026 00BF .align 2 + 3687 .L318: + 3688 0028 00000000 .word _out_buffer + 3689 .cfi_endproc + 3690 .LFE15: + 3692 .section .text.snprintf_,"ax",%progbits + 3693 .align 1 + 3694 .global snprintf_ + 3695 .syntax unified + 3696 .thumb + 3697 .thumb_func + 3698 .fpu fpv5-d16 + 3700 snprintf_: + 3701 .LVL386: + 3702 .LFB16: + 881:Core/Src/printf.c **** + 882:Core/Src/printf.c **** + 883:Core/Src/printf.c **** int snprintf_(char* buffer, size_t count, const char* format, ...) + 884:Core/Src/printf.c **** { + 3703 .loc 1 884 1 is_stmt 1 view -0 + 3704 .cfi_startproc + 3705 @ args = 4, pretend = 8, frame = 8 + 3706 @ frame_needed = 0, uses_anonymous_args = 1 + 3707 .loc 1 884 1 is_stmt 0 view .LVU1002 + 3708 0000 0CB4 push {r2, r3} + 3709 .LCFI40: + 3710 .cfi_def_cfa_offset 8 + 3711 .cfi_offset 2, -8 + 3712 .cfi_offset 3, -4 + 3713 0002 10B5 push {r4, lr} + 3714 .LCFI41: + 3715 .cfi_def_cfa_offset 16 + 3716 .cfi_offset 4, -16 + 3717 .cfi_offset 14, -12 + 3718 0004 84B0 sub sp, sp, #16 + 3719 .LCFI42: + 3720 .cfi_def_cfa_offset 32 + 3721 0006 0A46 mov r2, r1 + 3722 0008 06AC add r4, sp, #24 + 3723 000a 54F8043B ldr r3, [r4], #4 + ARM GAS /tmp/ccibzHy5.s page 93 + + + 885:Core/Src/printf.c **** va_list va; + 3724 .loc 1 885 3 is_stmt 1 view .LVU1003 + 886:Core/Src/printf.c **** va_start(va, format); + 3725 .loc 1 886 3 view .LVU1004 + 3726 000e 0394 str r4, [sp, #12] + 887:Core/Src/printf.c **** const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); + 3727 .loc 1 887 3 view .LVU1005 + 3728 .loc 1 887 19 is_stmt 0 view .LVU1006 + 3729 0010 0094 str r4, [sp] + 3730 0012 0146 mov r1, r0 + 3731 .LVL387: + 3732 .loc 1 887 19 view .LVU1007 + 3733 0014 0348 ldr r0, .L322 + 3734 .LVL388: + 3735 .loc 1 887 19 view .LVU1008 + 3736 0016 FFF7FEFF bl _vsnprintf + 3737 .LVL389: + 888:Core/Src/printf.c **** va_end(va); + 3738 .loc 1 888 3 is_stmt 1 view .LVU1009 + 889:Core/Src/printf.c **** return ret; + 3739 .loc 1 889 3 view .LVU1010 + 890:Core/Src/printf.c **** } + 3740 .loc 1 890 1 is_stmt 0 view .LVU1011 + 3741 001a 04B0 add sp, sp, #16 + 3742 .LCFI43: + 3743 .cfi_def_cfa_offset 16 + 3744 @ sp needed + 3745 001c BDE81040 pop {r4, lr} + 3746 .LCFI44: + 3747 .cfi_restore 14 + 3748 .cfi_restore 4 + 3749 .cfi_def_cfa_offset 8 + 3750 0020 02B0 add sp, sp, #8 + 3751 .LCFI45: + 3752 .cfi_restore 3 + 3753 .cfi_restore 2 + 3754 .cfi_def_cfa_offset 0 + 3755 0022 7047 bx lr + 3756 .L323: + 3757 .align 2 + 3758 .L322: + 3759 0024 00000000 .word _out_buffer + 3760 .cfi_endproc + 3761 .LFE16: + 3763 .section .text.vprintf_,"ax",%progbits + 3764 .align 1 + 3765 .global vprintf_ + 3766 .syntax unified + 3767 .thumb + 3768 .thumb_func + 3769 .fpu fpv5-d16 + 3771 vprintf_: + 3772 .LVL390: + 3773 .LFB17: + 891:Core/Src/printf.c **** + 892:Core/Src/printf.c **** + 893:Core/Src/printf.c **** int vprintf_(const char* format, va_list va) + ARM GAS /tmp/ccibzHy5.s page 94 + + + 894:Core/Src/printf.c **** { + 3774 .loc 1 894 1 is_stmt 1 view -0 + 3775 .cfi_startproc + 3776 @ args = 0, pretend = 0, frame = 8 + 3777 @ frame_needed = 0, uses_anonymous_args = 0 + 3778 .loc 1 894 1 is_stmt 0 view .LVU1013 + 3779 0000 00B5 push {lr} + 3780 .LCFI46: + 3781 .cfi_def_cfa_offset 4 + 3782 .cfi_offset 14, -4 + 3783 0002 85B0 sub sp, sp, #20 + 3784 .LCFI47: + 3785 .cfi_def_cfa_offset 24 + 3786 0004 0346 mov r3, r0 + 895:Core/Src/printf.c **** char buffer[1]; + 3787 .loc 1 895 3 is_stmt 1 view .LVU1014 + 896:Core/Src/printf.c **** return _vsnprintf(_out_char, buffer, (size_t)-1, format, va); + 3788 .loc 1 896 3 view .LVU1015 + 3789 .loc 1 896 10 is_stmt 0 view .LVU1016 + 3790 0006 0091 str r1, [sp] + 3791 0008 4FF0FF32 mov r2, #-1 + 3792 000c 03A9 add r1, sp, #12 + 3793 .LVL391: + 3794 .loc 1 896 10 view .LVU1017 + 3795 000e 0348 ldr r0, .L326 + 3796 .LVL392: + 3797 .loc 1 896 10 view .LVU1018 + 3798 0010 FFF7FEFF bl _vsnprintf + 3799 .LVL393: + 897:Core/Src/printf.c **** } + 3800 .loc 1 897 1 view .LVU1019 + 3801 0014 05B0 add sp, sp, #20 + 3802 .LCFI48: + 3803 .cfi_def_cfa_offset 4 + 3804 @ sp needed + 3805 0016 5DF804FB ldr pc, [sp], #4 + 3806 .L327: + 3807 001a 00BF .align 2 + 3808 .L326: + 3809 001c 00000000 .word _out_char + 3810 .cfi_endproc + 3811 .LFE17: + 3813 .section .text.vsnprintf_,"ax",%progbits + 3814 .align 1 + 3815 .global vsnprintf_ + 3816 .syntax unified + 3817 .thumb + 3818 .thumb_func + 3819 .fpu fpv5-d16 + 3821 vsnprintf_: + 3822 .LVL394: + 3823 .LFB18: + 898:Core/Src/printf.c **** + 899:Core/Src/printf.c **** + 900:Core/Src/printf.c **** int vsnprintf_(char* buffer, size_t count, const char* format, va_list va) + 901:Core/Src/printf.c **** { + 3824 .loc 1 901 1 is_stmt 1 view -0 + ARM GAS /tmp/ccibzHy5.s page 95 + + + 3825 .cfi_startproc + 3826 @ args = 0, pretend = 0, frame = 0 + 3827 @ frame_needed = 0, uses_anonymous_args = 0 + 3828 .loc 1 901 1 is_stmt 0 view .LVU1021 + 3829 0000 00B5 push {lr} + 3830 .LCFI49: + 3831 .cfi_def_cfa_offset 4 + 3832 .cfi_offset 14, -4 + 3833 0002 83B0 sub sp, sp, #12 + 3834 .LCFI50: + 3835 .cfi_def_cfa_offset 16 + 902:Core/Src/printf.c **** return _vsnprintf(_out_buffer, buffer, count, format, va); + 3836 .loc 1 902 3 is_stmt 1 view .LVU1022 + 3837 .loc 1 902 10 is_stmt 0 view .LVU1023 + 3838 0004 0093 str r3, [sp] + 3839 0006 1346 mov r3, r2 + 3840 .LVL395: + 3841 .loc 1 902 10 view .LVU1024 + 3842 0008 0A46 mov r2, r1 + 3843 .LVL396: + 3844 .loc 1 902 10 view .LVU1025 + 3845 000a 0146 mov r1, r0 + 3846 .LVL397: + 3847 .loc 1 902 10 view .LVU1026 + 3848 000c 0248 ldr r0, .L330 + 3849 .LVL398: + 3850 .loc 1 902 10 view .LVU1027 + 3851 000e FFF7FEFF bl _vsnprintf + 3852 .LVL399: + 903:Core/Src/printf.c **** } + 3853 .loc 1 903 1 view .LVU1028 + 3854 0012 03B0 add sp, sp, #12 + 3855 .LCFI51: + 3856 .cfi_def_cfa_offset 4 + 3857 @ sp needed + 3858 0014 5DF804FB ldr pc, [sp], #4 + 3859 .L331: + 3860 .align 2 + 3861 .L330: + 3862 0018 00000000 .word _out_buffer + 3863 .cfi_endproc + 3864 .LFE18: + 3866 .section .text.fctprintf,"ax",%progbits + 3867 .align 1 + 3868 .global fctprintf + 3869 .syntax unified + 3870 .thumb + 3871 .thumb_func + 3872 .fpu fpv5-d16 + 3874 fctprintf: + 3875 .LVL400: + 3876 .LFB19: + 904:Core/Src/printf.c **** + 905:Core/Src/printf.c **** + 906:Core/Src/printf.c **** int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...) + 907:Core/Src/printf.c **** { + 3877 .loc 1 907 1 is_stmt 1 view -0 + ARM GAS /tmp/ccibzHy5.s page 96 + + + 3878 .cfi_startproc + 3879 @ args = 4, pretend = 8, frame = 16 + 3880 @ frame_needed = 0, uses_anonymous_args = 1 + 3881 .loc 1 907 1 is_stmt 0 view .LVU1030 + 3882 0000 0CB4 push {r2, r3} + 3883 .LCFI52: + 3884 .cfi_def_cfa_offset 8 + 3885 .cfi_offset 2, -8 + 3886 .cfi_offset 3, -4 + 3887 0002 00B5 push {lr} + 3888 .LCFI53: + 3889 .cfi_def_cfa_offset 12 + 3890 .cfi_offset 14, -12 + 3891 0004 87B0 sub sp, sp, #28 + 3892 .LCFI54: + 3893 .cfi_def_cfa_offset 40 + 3894 0006 08AA add r2, sp, #32 + 3895 0008 52F8043B ldr r3, [r2], #4 + 908:Core/Src/printf.c **** va_list va; + 3896 .loc 1 908 3 is_stmt 1 view .LVU1031 + 909:Core/Src/printf.c **** va_start(va, format); + 3897 .loc 1 909 3 view .LVU1032 + 3898 000c 0592 str r2, [sp, #20] + 910:Core/Src/printf.c **** const out_fct_wrap_type out_fct_wrap = { out, arg }; + 3899 .loc 1 910 3 view .LVU1033 + 3900 .loc 1 910 27 is_stmt 0 view .LVU1034 + 3901 000e 0390 str r0, [sp, #12] + 3902 0010 0491 str r1, [sp, #16] + 911:Core/Src/printf.c **** const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); + 3903 .loc 1 911 3 is_stmt 1 view .LVU1035 + 3904 .loc 1 911 19 is_stmt 0 view .LVU1036 + 3905 0012 0092 str r2, [sp] + 3906 0014 4FF0FF32 mov r2, #-1 + 3907 0018 03A9 add r1, sp, #12 + 3908 001a 0448 ldr r0, .L334 + 3909 .LVL401: + 3910 .loc 1 911 19 view .LVU1037 + 3911 001c FFF7FEFF bl _vsnprintf + 3912 .LVL402: + 912:Core/Src/printf.c **** va_end(va); + 3913 .loc 1 912 3 is_stmt 1 view .LVU1038 + 913:Core/Src/printf.c **** return ret; + 3914 .loc 1 913 3 view .LVU1039 + 914:Core/Src/printf.c **** } + 3915 .loc 1 914 1 is_stmt 0 view .LVU1040 + 3916 0020 07B0 add sp, sp, #28 + 3917 .LCFI55: + 3918 .cfi_def_cfa_offset 12 + 3919 @ sp needed + 3920 0022 5DF804EB ldr lr, [sp], #4 + 3921 .LCFI56: + 3922 .cfi_restore 14 + 3923 .cfi_def_cfa_offset 8 + 3924 0026 02B0 add sp, sp, #8 + 3925 .LCFI57: + 3926 .cfi_restore 3 + 3927 .cfi_restore 2 + ARM GAS /tmp/ccibzHy5.s page 97 + + + 3928 .cfi_def_cfa_offset 0 + 3929 0028 7047 bx lr + 3930 .L335: + 3931 002a 00BF .align 2 + 3932 .L334: + 3933 002c 00000000 .word _out_fct + 3934 .cfi_endproc + 3935 .LFE19: + 3937 .section .rodata.pow10.0,"a" + 3938 .align 3 + 3939 .set .LANCHOR0,. + 0 + 3942 pow10.0: + 3943 0000 00000000 .word 0 + 3944 0004 0000F03F .word 1072693248 + 3945 0008 00000000 .word 0 + 3946 000c 00002440 .word 1076101120 + 3947 0010 00000000 .word 0 + 3948 0014 00005940 .word 1079574528 + 3949 0018 00000000 .word 0 + 3950 001c 00408F40 .word 1083129856 + 3951 0020 00000000 .word 0 + 3952 0024 0088C340 .word 1086556160 + 3953 0028 00000000 .word 0 + 3954 002c 006AF840 .word 1090021888 + 3955 0030 00000000 .word 0 + 3956 0034 80842E41 .word 1093567616 + 3957 0038 00000000 .word 0 + 3958 003c D0126341 .word 1097011920 + 3959 0040 00000000 .word 0 + 3960 0044 84D79741 .word 1100470148 + 3961 0048 00000000 .word 0 + 3962 004c 65CDCD41 .word 1104006501 + 3963 .text + 3964 .Letext0: + 3965 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3966 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3967 .file 4 "/usr/lib/gcc/arm-none-eabi/10.2.0/include/stdarg.h" + 3968 .file 5 "/usr/lib/gcc/arm-none-eabi/10.2.0/include/stddef.h" + 3969 .file 6 "" + 3970 .file 7 "Core/Inc/printf.h" + ARM GAS /tmp/ccibzHy5.s page 98 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 printf.c + /tmp/ccibzHy5.s:17 .text._out_buffer:0000000000000000 $t + /tmp/ccibzHy5.s:24 .text._out_buffer:0000000000000000 _out_buffer + /tmp/ccibzHy5.s:47 .text._out_null:0000000000000000 $t + /tmp/ccibzHy5.s:53 .text._out_null:0000000000000000 _out_null + /tmp/ccibzHy5.s:71 .text._out_fct:0000000000000000 $t + /tmp/ccibzHy5.s:77 .text._out_fct:0000000000000000 _out_fct + /tmp/ccibzHy5.s:119 .text._atoi:0000000000000000 $t + /tmp/ccibzHy5.s:125 .text._atoi:0000000000000000 _atoi + /tmp/ccibzHy5.s:190 .text._out_rev:0000000000000000 $t + /tmp/ccibzHy5.s:196 .text._out_rev:0000000000000000 _out_rev + /tmp/ccibzHy5.s:330 .text._ntoa_format:0000000000000000 $t + /tmp/ccibzHy5.s:336 .text._ntoa_format:0000000000000000 _ntoa_format + /tmp/ccibzHy5.s:616 .text._ntoa_long:0000000000000000 $t + /tmp/ccibzHy5.s:622 .text._ntoa_long:0000000000000000 _ntoa_long + /tmp/ccibzHy5.s:777 .text._ntoa_long_long:0000000000000000 $t + /tmp/ccibzHy5.s:783 .text._ntoa_long_long:0000000000000000 _ntoa_long_long + /tmp/ccibzHy5.s:960 .text._etoa:0000000000000000 $t + /tmp/ccibzHy5.s:966 .text._etoa:0000000000000000 _etoa + /tmp/ccibzHy5.s:1456 .text._ftoa:0000000000000000 _ftoa + /tmp/ccibzHy5.s:1413 .text._etoa:0000000000000280 $d + /tmp/ccibzHy5.s:1437 .rodata._ftoa.str1.4:0000000000000000 $d + /tmp/ccibzHy5.s:1450 .text._ftoa:0000000000000000 $t + /tmp/ccibzHy5.s:1999 .text._ftoa:00000000000002c8 $d + /tmp/ccibzHy5.s:2020 .text._vsnprintf:0000000000000000 $t + /tmp/ccibzHy5.s:2026 .text._vsnprintf:0000000000000000 _vsnprintf + /tmp/ccibzHy5.s:2121 .text._vsnprintf:000000000000004e $d + /tmp/ccibzHy5.s:2189 .text._vsnprintf:000000000000008c $d + /tmp/ccibzHy5.s:2477 .text._vsnprintf:000000000000018a $d + /tmp/ccibzHy5.s:2561 .text._vsnprintf:0000000000000232 $t + /tmp/ccibzHy5.s:3513 .text._vsnprintf:0000000000000678 $d + /tmp/ccibzHy5.s:3518 .text._out_char:0000000000000000 $t + /tmp/ccibzHy5.s:3524 .text._out_char:0000000000000000 _out_char + /tmp/ccibzHy5.s:3554 .text.printf_:0000000000000000 $t + /tmp/ccibzHy5.s:3561 .text.printf_:0000000000000000 printf_ + /tmp/ccibzHy5.s:3619 .text.printf_:0000000000000028 $d + /tmp/ccibzHy5.s:3624 .text.sprintf_:0000000000000000 $t + /tmp/ccibzHy5.s:3631 .text.sprintf_:0000000000000000 sprintf_ + /tmp/ccibzHy5.s:3688 .text.sprintf_:0000000000000028 $d + /tmp/ccibzHy5.s:3693 .text.snprintf_:0000000000000000 $t + /tmp/ccibzHy5.s:3700 .text.snprintf_:0000000000000000 snprintf_ + /tmp/ccibzHy5.s:3759 .text.snprintf_:0000000000000024 $d + /tmp/ccibzHy5.s:3764 .text.vprintf_:0000000000000000 $t + /tmp/ccibzHy5.s:3771 .text.vprintf_:0000000000000000 vprintf_ + /tmp/ccibzHy5.s:3809 .text.vprintf_:000000000000001c $d + /tmp/ccibzHy5.s:3814 .text.vsnprintf_:0000000000000000 $t + /tmp/ccibzHy5.s:3821 .text.vsnprintf_:0000000000000000 vsnprintf_ + /tmp/ccibzHy5.s:3862 .text.vsnprintf_:0000000000000018 $d + /tmp/ccibzHy5.s:3867 .text.fctprintf:0000000000000000 $t + /tmp/ccibzHy5.s:3874 .text.fctprintf:0000000000000000 fctprintf + /tmp/ccibzHy5.s:3933 .text.fctprintf:000000000000002c $d + /tmp/ccibzHy5.s:3938 .rodata.pow10.0:0000000000000000 $d + /tmp/ccibzHy5.s:3942 .rodata.pow10.0:0000000000000000 pow10.0 + /tmp/ccibzHy5.s:2138 .text._vsnprintf:000000000000005f $d + /tmp/ccibzHy5.s:2138 .text._vsnprintf:0000000000000060 $t + /tmp/ccibzHy5.s:2209 .text._vsnprintf:000000000000009f $d + ARM GAS /tmp/ccibzHy5.s page 99 + + + /tmp/ccibzHy5.s:2209 .text._vsnprintf:00000000000000a0 $t + +UNDEFINED SYMBOLS +__aeabi_uldivmod +_putchar diff --git a/build/printf.o b/build/printf.o new file mode 100644 index 0000000..5f66c61 Binary files /dev/null and b/build/printf.o differ diff --git a/build/startup_stm32h750xx.d b/build/startup_stm32h750xx.d new file mode 100644 index 0000000..9929b46 --- /dev/null +++ b/build/startup_stm32h750xx.d @@ -0,0 +1 @@ +build/startup_stm32h750xx.o: startup_stm32h750xx.s diff --git a/build/startup_stm32h750xx.o b/build/startup_stm32h750xx.o new file mode 100644 index 0000000..f7a966c Binary files /dev/null and b/build/startup_stm32h750xx.o differ diff --git a/build/stm32h7xx_hal.d b/build/stm32h7xx_hal.d new file mode 100644 index 0000000..76cbcd0 --- /dev/null +++ b/build/stm32h7xx_hal.d @@ -0,0 +1,67 @@ +build/stm32h7xx_hal.o: Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal.lst b/build/stm32h7xx_hal.lst new file mode 100644 index 0000000..3d4b6e2 --- /dev/null +++ b/build/stm32h7xx_hal.lst @@ -0,0 +1,3709 @@ +ARM GAS /tmp/ccfvUJpJ.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_MspInit,"ax",%progbits + 17 .align 1 + 18 .weak HAL_MspInit + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_MspInit: + 26 .LFB143: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @file stm32h7xx_hal.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This is the common part of the HAL initialization + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** @verbatim + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ============================================================================== + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ##### How to use this driver ##### + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ============================================================================== + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** [..] + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** The common HAL driver contains a set of generic and common APIs that can be + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** used by the PPP peripheral drivers and the user to start using the HAL. + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** [..] + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** The HAL contains two APIs' categories: + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Common HAL APIs + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Services HAL APIs + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** @endverbatim + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ****************************************************************************** + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @attention + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** *

© Copyright (c) 2017 STMicroelectronics. + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * All rights reserved.

+ 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This software component is licensed by ST under BSD 3-Clause license, + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * the "License"; You may not use this file except in compliance with the + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * License. You may obtain a copy of the License at: + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * opensource.org/licenses/BSD-3-Clause + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + ARM GAS /tmp/ccfvUJpJ.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ****************************************************************************** + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Includes ------------------------------------------------------------------*/ + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #include "stm32h7xx_hal.h" + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @addtogroup STM32H7xx_HAL_Driver + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @{ + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @defgroup HAL HAL + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief HAL module driver. + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @{ + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Private typedef -----------------------------------------------------------*/ + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Private define ------------------------------------------------------------*/ + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief STM32H7xx HAL Driver version number V1.9.0 + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define __STM32H7xx_HAL_VERSION_SUB1 (0x09UL) /*!< [23:16] sub1 version */ + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\ + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** |(__STM32H7xx_HAL_VERSION_RC)) + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */ + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Private macro -------------------------------------------------------------*/ + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Private variables ---------------------------------------------------------*/ + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Exported variables --------------------------------------------------------*/ + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @defgroup HAL_Exported_Variables HAL Exported Variables + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @{ + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __IO uint32_t uwTick; + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @} + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Private function prototypes -----------------------------------------------*/ + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Private functions ---------------------------------------------------------*/ + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @defgroup HAL_Private_Functions HAL Private Functions + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @{ + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @defgroup HAL_Group1 Initialization and de-initialization Functions + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Initialization and de-initialization functions + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** @verbatim + ARM GAS /tmp/ccfvUJpJ.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** =============================================================================== + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ##### Initialization and de-initialization functions ##### + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** =============================================================================== + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** [..] This section provides functions allowing to: + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Initializes the Flash interface the NVIC allocation and initial clock + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** configuration. It initializes the systick also when timeout is needed + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** and the backup domain when enabled. + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) De-Initializes common part of the HAL. + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Configure The time base source to have 1ms time base with a dedicated + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** Tick interrupt priority. + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (++) SysTick timer is used by default as source of time base, but user + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** can eventually implement his proper time base source (a general purpose + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** timer for example or other time source), keeping in mind that Time base + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** handled in milliseconds basis. + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (++) Time base configuration function (HAL_InitTick ()) is called automatically + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** at the beginning of the program after reset by HAL_Init() or at any time + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** when clock is configured, by HAL_RCC_ClockConfig(). + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (++) Source of time base is configured to generate interrupts at regular + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** time intervals. Care must be taken if HAL_Delay() is called from a + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** peripheral ISR process, the Tick interrupt line must have higher priority + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (numerically lower) than the peripheral interrupt. Otherwise the caller + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ISR process will be blocked. + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (++) functions affecting time base configurations are declared as __weak + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** to make override possible in case of other implementations in user file. + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** @endverbatim + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @{ + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief This function is used to initialize the HAL Library; it must be the first + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * instruction to be executed in the main program (before to call any other + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * HAL function), it performs the following: + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * Configures the SysTick to generate an interrupt each 1 millisecond, + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * which is clocked by the HSI (at this stage, the clock is not yet + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * configured and thus the system is running from the internal HSI at 16 MHz). + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * Set NVIC Group Priority to 4. + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * Calls the HAL_MspInit() callback function defined in user file + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note SysTick is used as time base for the HAL_Delay() function, the application + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * need to ensure that the SysTick time base is always set to 1 millisecond + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * to have correct HAL operation. + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval HAL status + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_StatusTypeDef HAL_Init(void) + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t common_system_clock; + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure Cortex-M4 Instruction cache through ART accelerator */ + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + ARM GAS /tmp/ccfvUJpJ.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Set Interrupt Group Priority */ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Update the SystemCoreClock global variable */ + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(RCC_D1CFGR_D1CPRE) + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1 + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Update the SystemD2Clock global variable */ + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(RCC_D1CFGR_HPRE) + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_ + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RC + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SystemCoreClock = SystemD2Clock; + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SystemCoreClock = common_system_clock; + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_ERROR; + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Init the low level hardware */ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_MspInit(); + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Return function status */ + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_OK; + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief This function de-Initializes common part of the HAL and stops the systick. + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This function is optional. + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval HAL status + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void) + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Reset of all peripherals */ + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB3_FORCE_RESET(); + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB3_RELEASE_RESET(); + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB1_FORCE_RESET(); + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB1_RELEASE_RESET(); + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB2_FORCE_RESET(); + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB2_RELEASE_RESET(); + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB4_FORCE_RESET(); + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB4_RELEASE_RESET(); + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB3_FORCE_RESET(); + ARM GAS /tmp/ccfvUJpJ.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB3_RELEASE_RESET(); + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB1L_FORCE_RESET(); + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB1L_RELEASE_RESET(); + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB1H_FORCE_RESET(); + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB1H_RELEASE_RESET(); + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB2_FORCE_RESET(); + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB4_FORCE_RESET(); + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB4_RELEASE_RESET(); + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* De-Init the low level hardware */ + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_MspDeInit(); + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Return function status */ + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_OK; + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Initializes the MSP. + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak void HAL_MspInit(void) + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 28 .loc 1 229 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** the HAL_MspInit could be implemented in the user file + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 33 .loc 1 233 1 view .LVU1 + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE143: + 38 .section .text.HAL_MspDeInit,"ax",%progbits + 39 .align 1 + 40 .weak HAL_MspDeInit + 41 .syntax unified + 42 .thumb + 43 .thumb_func + 44 .fpu fpv5-d16 + 46 HAL_MspDeInit: + 47 .LFB144: + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief DeInitializes the MSP. + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak void HAL_MspDeInit(void) + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 48 .loc 1 240 1 view -0 + ARM GAS /tmp/ccfvUJpJ.s page 6 + + + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** the HAL_MspDeInit could be implemented in the user file + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 53 .loc 1 244 1 view .LVU3 + 54 0000 7047 bx lr + 55 .cfi_endproc + 56 .LFE144: + 58 .section .text.HAL_DeInit,"ax",%progbits + 59 .align 1 + 60 .global HAL_DeInit + 61 .syntax unified + 62 .thumb + 63 .thumb_func + 64 .fpu fpv5-d16 + 66 HAL_DeInit: + 67 .LFB142: + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Reset of all peripherals */ + 68 .loc 1 188 1 view -0 + 69 .cfi_startproc + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 0, uses_anonymous_args = 0 + 72 0000 10B5 push {r4, lr} + 73 .LCFI0: + 74 .cfi_def_cfa_offset 8 + 75 .cfi_offset 4, -8 + 76 .cfi_offset 14, -4 + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB3_RELEASE_RESET(); + 77 .loc 1 190 3 view .LVU5 + 78 0002 194B ldr r3, .L5 + 79 0004 194A ldr r2, .L5+4 + 80 0006 DA67 str r2, [r3, #124] + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 81 .loc 1 191 3 view .LVU6 + 82 0008 0024 movs r4, #0 + 83 000a DC67 str r4, [r3, #124] + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB1_RELEASE_RESET(); + 84 .loc 1 193 3 view .LVU7 + 85 000c 184A ldr r2, .L5+8 + 86 000e C3F88020 str r2, [r3, #128] + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 87 .loc 1 194 3 view .LVU8 + 88 0012 C3F88040 str r4, [r3, #128] + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB2_RELEASE_RESET(); + 89 .loc 1 196 3 view .LVU9 + 90 0016 40F27122 movw r2, #625 + 91 001a C3F88420 str r2, [r3, #132] + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 92 .loc 1 197 3 view .LVU10 + 93 001e C3F88440 str r4, [r3, #132] + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_AHB4_RELEASE_RESET(); + 94 .loc 1 199 3 view .LVU11 + 95 0022 144A ldr r2, .L5+12 + ARM GAS /tmp/ccfvUJpJ.s page 7 + + + 96 0024 C3F88820 str r2, [r3, #136] + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 97 .loc 1 200 2 view .LVU12 + 98 0028 C3F88840 str r4, [r3, #136] + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB3_RELEASE_RESET(); + 99 .loc 1 202 3 view .LVU13 + 100 002c 1822 movs r2, #24 + 101 002e C3F88C20 str r2, [r3, #140] + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 102 .loc 1 203 3 view .LVU14 + 103 0032 C3F88C40 str r4, [r3, #140] + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB1L_RELEASE_RESET(); + 104 .loc 1 205 3 view .LVU15 + 105 0036 104A ldr r2, .L5+16 + 106 0038 C3F89020 str r2, [r3, #144] + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 107 .loc 1 206 3 view .LVU16 + 108 003c C3F89040 str r4, [r3, #144] + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB1H_RELEASE_RESET(); + 109 .loc 1 208 3 view .LVU17 + 110 0040 4FF49B72 mov r2, #310 + 111 0044 C3F89420 str r2, [r3, #148] + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 112 .loc 1 209 3 view .LVU18 + 113 0048 C3F89440 str r4, [r3, #148] + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 114 .loc 1 211 4 view .LVU19 + 115 004c 0B4A ldr r2, .L5+20 + 116 004e C3F89820 str r2, [r3, #152] + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 117 .loc 1 212 4 view .LVU20 + 118 0052 C3F89840 str r4, [r3, #152] + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __HAL_RCC_APB4_RELEASE_RESET(); + 119 .loc 1 214 3 view .LVU21 + 120 0056 0A4A ldr r2, .L5+24 + 121 0058 C3F89C20 str r2, [r3, #156] + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 122 .loc 1 215 3 view .LVU22 + 123 005c C3F89C40 str r4, [r3, #156] + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 124 .loc 1 218 3 view .LVU23 + 125 0060 FFF7FEFF bl HAL_MspDeInit + 126 .LVL0: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 127 .loc 1 221 3 view .LVU24 + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 128 .loc 1 222 1 is_stmt 0 view .LVU25 + 129 0064 2046 mov r0, r4 + 130 0066 10BD pop {r4, pc} + 131 .L6: + 132 .align 2 + 133 .L5: + 134 0068 00440258 .word 1476543488 + 135 006c 31500100 .word 86065 + 136 0070 23C0000A .word 167821347 + 137 0074 FF072803 .word 52955135 + 138 0078 FFC3FFE8 .word -385891329 + ARM GAS /tmp/ccfvUJpJ.s page 8 + + + 139 007c 3330D731 .word 836186163 + 140 0080 AADE2000 .word 2154154 + 141 .cfi_endproc + 142 .LFE142: + 144 .section .text.HAL_InitTick,"ax",%progbits + 145 .align 1 + 146 .weak HAL_InitTick + 147 .syntax unified + 148 .thumb + 149 .thumb_func + 150 .fpu fpv5-d16 + 152 HAL_InitTick: + 153 .LVL1: + 154 .LFB145: + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief This function configures the source of the time base. + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * The time source is configured to have 1ms time base with a dedicated + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * Tick interrupt priority. + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This function is called automatically at the beginning of program after + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note In the default implementation, SysTick timer is the source of time base. + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * It is used to generate interrupts at regular time intervals. + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * The the SysTick interrupt must have higher priority (numerically lower) + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * The function is declared as __weak to be overwritten in case of other + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * implementation in user file. + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param TickPriority: Tick interrupt priority. + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval HAL status + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 155 .loc 1 263 1 is_stmt 1 view -0 + 156 .cfi_startproc + 157 @ args = 0, pretend = 0, frame = 0 + 158 @ frame_needed = 0, uses_anonymous_args = 0 + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if((uint32_t)uwTickFreq == 0UL) + 159 .loc 1 265 3 view .LVU27 + 160 .loc 1 265 27 is_stmt 0 view .LVU28 + 161 0000 104B ldr r3, .L18 + 162 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 163 .loc 1 265 5 view .LVU29 + 164 0004 0BB9 cbnz r3, .L16 + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_ERROR; + 165 .loc 1 267 12 view .LVU30 + 166 0006 0120 movs r0, #1 + 167 .LVL2: + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure the SysTick to have interrupt in 1ms time basis*/ + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_ERROR; + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + ARM GAS /tmp/ccfvUJpJ.s page 9 + + + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure the SysTick IRQ priority */ + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uwTickPrio = TickPriority; + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_ERROR; + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Return function status */ + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_OK; + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 168 .loc 1 289 1 view .LVU31 + 169 0008 7047 bx lr + 170 .LVL3: + 171 .L16: + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value + 172 .loc 1 263 1 view .LVU32 + 173 000a 10B5 push {r4, lr} + 174 .LCFI1: + 175 .cfi_def_cfa_offset 8 + 176 .cfi_offset 4, -8 + 177 .cfi_offset 14, -4 + 178 000c 0446 mov r4, r0 + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 179 .loc 1 271 5 is_stmt 1 view .LVU33 + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 180 .loc 1 271 54 is_stmt 0 view .LVU34 + 181 000e 4FF47A70 mov r0, #1000 + 182 .LVL4: + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 183 .loc 1 271 54 view .LVU35 + 184 0012 B0FBF3F3 udiv r3, r0, r3 + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 185 .loc 1 271 9 view .LVU36 + 186 0016 0C4A ldr r2, .L18+4 + 187 0018 1068 ldr r0, [r2] + 188 001a B0FBF3F0 udiv r0, r0, r3 + 189 001e FFF7FEFF bl HAL_SYSTICK_Config + 190 .LVL5: + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 191 .loc 1 271 8 view .LVU37 + 192 0022 68B9 cbnz r0, .L10 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 193 .loc 1 277 3 is_stmt 1 view .LVU38 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 194 .loc 1 277 6 is_stmt 0 view .LVU39 + 195 0024 0F2C cmp r4, #15 + 196 0026 01D9 bls .L17 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 197 .loc 1 284 12 view .LVU40 + 198 0028 0120 movs r0, #1 + 199 002a 0AE0 b .L8 + 200 .L17: + ARM GAS /tmp/ccfvUJpJ.s page 10 + + + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uwTickPrio = TickPriority; + 201 .loc 1 279 5 is_stmt 1 view .LVU41 + 202 002c 0022 movs r2, #0 + 203 002e 2146 mov r1, r4 + 204 0030 4FF0FF30 mov r0, #-1 + 205 0034 FFF7FEFF bl HAL_NVIC_SetPriority + 206 .LVL6: + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 207 .loc 1 280 5 view .LVU42 + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 208 .loc 1 280 16 is_stmt 0 view .LVU43 + 209 0038 044B ldr r3, .L18+8 + 210 003a 1C60 str r4, [r3] + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 211 .loc 1 288 3 is_stmt 1 view .LVU44 + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 212 .loc 1 288 10 is_stmt 0 view .LVU45 + 213 003c 0020 movs r0, #0 + 214 003e 00E0 b .L8 + 215 .L10: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 216 .loc 1 273 14 view .LVU46 + 217 0040 0120 movs r0, #1 + 218 .L8: + 219 .loc 1 289 1 view .LVU47 + 220 0042 10BD pop {r4, pc} + 221 .LVL7: + 222 .L19: + 223 .loc 1 289 1 view .LVU48 + 224 .align 2 + 225 .L18: + 226 0044 00000000 .word .LANCHOR0 + 227 0048 00000000 .word SystemCoreClock + 228 004c 00000000 .word .LANCHOR1 + 229 .cfi_endproc + 230 .LFE145: + 232 .section .text.HAL_Init,"ax",%progbits + 233 .align 1 + 234 .global HAL_Init + 235 .syntax unified + 236 .thumb + 237 .thumb_func + 238 .fpu fpv5-d16 + 240 HAL_Init: + 241 .LFB141: + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 242 .loc 1 135 1 is_stmt 1 view -0 + 243 .cfi_startproc + 244 @ args = 0, pretend = 0, frame = 0 + 245 @ frame_needed = 0, uses_anonymous_args = 0 + 246 0000 10B5 push {r4, lr} + 247 .LCFI2: + 248 .cfi_def_cfa_offset 8 + 249 .cfi_offset 4, -8 + 250 .cfi_offset 14, -4 + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 251 .loc 1 137 1 view .LVU50 + ARM GAS /tmp/ccfvUJpJ.s page 11 + + + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 252 .loc 1 147 3 view .LVU51 + 253 0002 0320 movs r0, #3 + 254 0004 FFF7FEFF bl HAL_NVIC_SetPriorityGrouping + 255 .LVL8: + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 256 .loc 1 151 3 view .LVU52 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 257 .loc 1 151 25 is_stmt 0 view .LVU53 + 258 0008 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 259 .LVL9: + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 260 .loc 1 151 77 view .LVU54 + 261 000c 0F49 ldr r1, .L25 + 262 000e 8B69 ldr r3, [r1, #24] + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 263 .loc 1 151 106 view .LVU55 + 264 0010 C3F30323 ubfx r3, r3, #8, #4 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 265 .loc 1 151 72 view .LVU56 + 266 0014 0E4A ldr r2, .L25+4 + 267 0016 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 268 .loc 1 151 133 view .LVU57 + 269 0018 03F01F03 and r3, r3, #31 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 270 .loc 1 151 23 view .LVU58 + 271 001c D840 lsrs r0, r0, r3 + 272 .LVL10: + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 273 .loc 1 158 3 is_stmt 1 view .LVU59 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 274 .loc 1 158 66 is_stmt 0 view .LVU60 + 275 001e 8B69 ldr r3, [r1, #24] + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 276 .loc 1 158 93 view .LVU61 + 277 0020 03F00F03 and r3, r3, #15 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 278 .loc 1 158 61 view .LVU62 + 279 0024 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 280 .loc 1 158 118 view .LVU63 + 281 0026 03F01F03 and r3, r3, #31 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 282 .loc 1 158 40 view .LVU64 + 283 002a 20FA03F3 lsr r3, r0, r3 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 284 .loc 1 158 17 view .LVU65 + 285 002e 094A ldr r2, .L25+8 + 286 0030 1360 str r3, [r2] + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 287 .loc 1 166 3 is_stmt 1 view .LVU66 + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 288 .loc 1 166 19 is_stmt 0 view .LVU67 + 289 0032 094B ldr r3, .L25+12 + 290 0034 1860 str r0, [r3] + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + ARM GAS /tmp/ccfvUJpJ.s page 12 + + + 291 .loc 1 170 3 is_stmt 1 view .LVU68 + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 292 .loc 1 170 6 is_stmt 0 view .LVU69 + 293 0036 0020 movs r0, #0 + 294 .LVL11: + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 295 .loc 1 170 6 view .LVU70 + 296 0038 FFF7FEFF bl HAL_InitTick + 297 .LVL12: + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 298 .loc 1 170 5 view .LVU71 + 299 003c 10B1 cbz r0, .L24 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 300 .loc 1 172 12 view .LVU72 + 301 003e 0124 movs r4, #1 + 302 .L21: + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 303 .loc 1 180 1 view .LVU73 + 304 0040 2046 mov r0, r4 + 305 0042 10BD pop {r4, pc} + 306 .L24: + 307 0044 0446 mov r4, r0 + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 308 .loc 1 176 3 is_stmt 1 view .LVU74 + 309 0046 FFF7FEFF bl HAL_MspInit + 310 .LVL13: + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 311 .loc 1 179 3 view .LVU75 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 312 .loc 1 179 10 is_stmt 0 view .LVU76 + 313 004a F9E7 b .L21 + 314 .L26: + 315 .align 2 + 316 .L25: + 317 004c 00440258 .word 1476543488 + 318 0050 00000000 .word D1CorePrescTable + 319 0054 00000000 .word SystemD2Clock + 320 0058 00000000 .word SystemCoreClock + 321 .cfi_endproc + 322 .LFE141: + 324 .section .text.HAL_IncTick,"ax",%progbits + 325 .align 1 + 326 .weak HAL_IncTick + 327 .syntax unified + 328 .thumb + 329 .thumb_func + 330 .fpu fpv5-d16 + 332 HAL_IncTick: + 333 .LFB146: + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @} + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @defgroup HAL_Group2 HAL Control functions + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief HAL Control functions + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + ARM GAS /tmp/ccfvUJpJ.s page 13 + + + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** @verbatim + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** =============================================================================== + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** ##### HAL Control functions ##### + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** =============================================================================== + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** [..] This section provides functions allowing to: + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Provide a tick value in millisecond + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Provide a blocking delay in millisecond + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Suspend the time base source interrupt + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Resume the time base source interrupt + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Get the HAL API driver version + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Get the device identifier + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Get the device revision identifier + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Enable/Disable Debug module during SLEEP mode + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Enable/Disable Debug module during STOP mode + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** (+) Enable/Disable Debug module during STANDBY mode + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** @endverbatim + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @{ + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief This function is called to increment a global variable "uwTick" + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * used as application time base. + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note In the default implementation, this variable is incremented each 1ms + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * in Systick ISR. + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * implementations in user file. + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak void HAL_IncTick(void) + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 334 .loc 1 328 1 is_stmt 1 view -0 + 335 .cfi_startproc + 336 @ args = 0, pretend = 0, frame = 0 + 337 @ frame_needed = 0, uses_anonymous_args = 0 + 338 @ link register save eliminated. + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uwTick += (uint32_t)uwTickFreq; + 339 .loc 1 329 3 view .LVU78 + 340 .loc 1 329 13 is_stmt 0 view .LVU79 + 341 0000 034B ldr r3, .L28 + 342 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 343 .loc 1 329 10 view .LVU80 + 344 0004 034A ldr r2, .L28+4 + 345 0006 1168 ldr r1, [r2] + 346 0008 0B44 add r3, r3, r1 + 347 000a 1360 str r3, [r2] + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 348 .loc 1 330 1 view .LVU81 + 349 000c 7047 bx lr + 350 .L29: + 351 000e 00BF .align 2 + 352 .L28: + 353 0010 00000000 .word .LANCHOR0 + 354 0014 00000000 .word .LANCHOR2 + 355 .cfi_endproc + 356 .LFE146: + 358 .section .text.HAL_GetTick,"ax",%progbits + ARM GAS /tmp/ccfvUJpJ.s page 14 + + + 359 .align 1 + 360 .weak HAL_GetTick + 361 .syntax unified + 362 .thumb + 363 .thumb_func + 364 .fpu fpv5-d16 + 366 HAL_GetTick: + 367 .LFB147: + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Provides a tick value in millisecond. + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * implementations in user file. + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval tick value + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak uint32_t HAL_GetTick(void) + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 368 .loc 1 339 1 is_stmt 1 view -0 + 369 .cfi_startproc + 370 @ args = 0, pretend = 0, frame = 0 + 371 @ frame_needed = 0, uses_anonymous_args = 0 + 372 @ link register save eliminated. + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return uwTick; + 373 .loc 1 340 3 view .LVU83 + 374 .loc 1 340 10 is_stmt 0 view .LVU84 + 375 0000 014B ldr r3, .L31 + 376 0002 1868 ldr r0, [r3] + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 377 .loc 1 341 1 view .LVU85 + 378 0004 7047 bx lr + 379 .L32: + 380 0006 00BF .align 2 + 381 .L31: + 382 0008 00000000 .word .LANCHOR2 + 383 .cfi_endproc + 384 .LFE147: + 386 .section .text.HAL_GetTickPrio,"ax",%progbits + 387 .align 1 + 388 .global HAL_GetTickPrio + 389 .syntax unified + 390 .thumb + 391 .thumb_func + 392 .fpu fpv5-d16 + 394 HAL_GetTickPrio: + 395 .LFB148: + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief This function returns a tick priority. + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval tick priority + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetTickPrio(void) + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 396 .loc 1 348 1 is_stmt 1 view -0 + 397 .cfi_startproc + 398 @ args = 0, pretend = 0, frame = 0 + 399 @ frame_needed = 0, uses_anonymous_args = 0 + 400 @ link register save eliminated. + ARM GAS /tmp/ccfvUJpJ.s page 15 + + + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return uwTickPrio; + 401 .loc 1 349 3 view .LVU87 + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 402 .loc 1 350 1 is_stmt 0 view .LVU88 + 403 0000 014B ldr r3, .L34 + 404 0002 1868 ldr r0, [r3] + 405 0004 7047 bx lr + 406 .L35: + 407 0006 00BF .align 2 + 408 .L34: + 409 0008 00000000 .word .LANCHOR1 + 410 .cfi_endproc + 411 .LFE148: + 413 .section .text.HAL_SetTickFreq,"ax",%progbits + 414 .align 1 + 415 .global HAL_SetTickFreq + 416 .syntax unified + 417 .thumb + 418 .thumb_func + 419 .fpu fpv5-d16 + 421 HAL_SetTickFreq: + 422 .LVL14: + 423 .LFB149: + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Set new tick Freq. + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval Status + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 424 .loc 1 357 1 is_stmt 1 view -0 + 425 .cfi_startproc + 426 @ args = 0, pretend = 0, frame = 0 + 427 @ frame_needed = 0, uses_anonymous_args = 0 + 428 .loc 1 357 1 is_stmt 0 view .LVU90 + 429 0000 10B5 push {r4, lr} + 430 .LCFI3: + 431 .cfi_def_cfa_offset 8 + 432 .cfi_offset 4, -8 + 433 .cfi_offset 14, -4 + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 434 .loc 1 358 3 is_stmt 1 view .LVU91 + 435 .LVL15: + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 436 .loc 1 359 3 view .LVU92 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_TICKFREQ(Freq)); + 437 .loc 1 361 3 view .LVU93 + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (uwTickFreq != Freq) + 438 .loc 1 363 3 view .LVU94 + 439 .loc 1 363 18 is_stmt 0 view .LVU95 + 440 0002 084B ldr r3, .L41 + 441 0004 1C78 ldrb r4, [r3] @ zero_extendqisi2 + 442 .loc 1 363 6 view .LVU96 + 443 0006 8442 cmp r4, r0 + 444 0008 01D1 bne .L40 + ARM GAS /tmp/ccfvUJpJ.s page 16 + + + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 445 .loc 1 358 21 view .LVU97 + 446 000a 0020 movs r0, #0 + 447 .LVL16: + 448 .L37: + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Back up uwTickFreq frequency */ + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** prevTickFreq = uwTickFreq; + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Update uwTickFreq global variable used by HAL_InitTick() */ + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uwTickFreq = Freq; + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Apply the new tick Freq */ + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** status = HAL_InitTick(uwTickPrio); + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (status != HAL_OK) + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Restore previous tick frequency */ + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uwTickFreq = prevTickFreq; + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return status; + 449 .loc 1 381 3 is_stmt 1 view .LVU98 + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 450 .loc 1 382 1 is_stmt 0 view .LVU99 + 451 000c 10BD pop {r4, pc} + 452 .LVL17: + 453 .L40: + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 454 .loc 1 367 5 is_stmt 1 view .LVU100 + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 455 .loc 1 370 5 view .LVU101 + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 456 .loc 1 370 16 is_stmt 0 view .LVU102 + 457 000e 1870 strb r0, [r3] + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (status != HAL_OK) + 458 .loc 1 373 5 is_stmt 1 view .LVU103 + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (status != HAL_OK) + 459 .loc 1 373 14 is_stmt 0 view .LVU104 + 460 0010 054B ldr r3, .L41+4 + 461 0012 1868 ldr r0, [r3] + 462 .LVL18: + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (status != HAL_OK) + 463 .loc 1 373 14 view .LVU105 + 464 0014 FFF7FEFF bl HAL_InitTick + 465 .LVL19: + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 466 .loc 1 374 5 is_stmt 1 view .LVU106 + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 467 .loc 1 374 8 is_stmt 0 view .LVU107 + 468 0018 0028 cmp r0, #0 + 469 001a F7D0 beq .L37 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 470 .loc 1 377 7 is_stmt 1 view .LVU108 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 471 .loc 1 377 18 is_stmt 0 view .LVU109 + ARM GAS /tmp/ccfvUJpJ.s page 17 + + + 472 001c 014B ldr r3, .L41 + 473 001e 1C70 strb r4, [r3] + 474 0020 F4E7 b .L37 + 475 .L42: + 476 0022 00BF .align 2 + 477 .L41: + 478 0024 00000000 .word .LANCHOR0 + 479 0028 00000000 .word .LANCHOR1 + 480 .cfi_endproc + 481 .LFE149: + 483 .section .text.HAL_GetTickFreq,"ax",%progbits + 484 .align 1 + 485 .global HAL_GetTickFreq + 486 .syntax unified + 487 .thumb + 488 .thumb_func + 489 .fpu fpv5-d16 + 491 HAL_GetTickFreq: + 492 .LFB150: + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Return tick frequency. + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval tick period in Hz + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_TickFreqTypeDef HAL_GetTickFreq(void) + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 493 .loc 1 389 1 is_stmt 1 view -0 + 494 .cfi_startproc + 495 @ args = 0, pretend = 0, frame = 0 + 496 @ frame_needed = 0, uses_anonymous_args = 0 + 497 @ link register save eliminated. + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return uwTickFreq; + 498 .loc 1 390 3 view .LVU111 + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 499 .loc 1 391 1 is_stmt 0 view .LVU112 + 500 0000 014B ldr r3, .L44 + 501 0002 1878 ldrb r0, [r3] @ zero_extendqisi2 + 502 0004 7047 bx lr + 503 .L45: + 504 0006 00BF .align 2 + 505 .L44: + 506 0008 00000000 .word .LANCHOR0 + 507 .cfi_endproc + 508 .LFE150: + 510 .section .text.HAL_Delay,"ax",%progbits + 511 .align 1 + 512 .weak HAL_Delay + 513 .syntax unified + 514 .thumb + 515 .thumb_func + 516 .fpu fpv5-d16 + 518 HAL_Delay: + 519 .LVL20: + 520 .LFB151: + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief This function provides minimum delay (in milliseconds) based + ARM GAS /tmp/ccfvUJpJ.s page 18 + + + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * on variable incremented. + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * It is used to generate interrupts at regular time intervals where uwTick + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * is incremented. + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * implementations in user file. + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param Delay specifies the delay time length, in milliseconds. + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak void HAL_Delay(uint32_t Delay) + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 521 .loc 1 405 1 is_stmt 1 view -0 + 522 .cfi_startproc + 523 @ args = 0, pretend = 0, frame = 0 + 524 @ frame_needed = 0, uses_anonymous_args = 0 + 525 .loc 1 405 1 is_stmt 0 view .LVU114 + 526 0000 38B5 push {r3, r4, r5, lr} + 527 .LCFI4: + 528 .cfi_def_cfa_offset 16 + 529 .cfi_offset 3, -16 + 530 .cfi_offset 4, -12 + 531 .cfi_offset 5, -8 + 532 .cfi_offset 14, -4 + 533 0002 0446 mov r4, r0 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t tickstart = HAL_GetTick(); + 534 .loc 1 406 3 is_stmt 1 view .LVU115 + 535 .loc 1 406 24 is_stmt 0 view .LVU116 + 536 0004 FFF7FEFF bl HAL_GetTick + 537 .LVL21: + 538 .loc 1 406 24 view .LVU117 + 539 0008 0546 mov r5, r0 + 540 .LVL22: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t wait = Delay; + 541 .loc 1 407 3 is_stmt 1 view .LVU118 + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Add a freq to guarantee minimum wait */ + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if (wait < HAL_MAX_DELAY) + 542 .loc 1 410 3 view .LVU119 + 543 .loc 1 410 6 is_stmt 0 view .LVU120 + 544 000a B4F1FF3F cmp r4, #-1 + 545 000e 02D0 beq .L48 + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** wait += (uint32_t)(uwTickFreq); + 546 .loc 1 412 5 is_stmt 1 view .LVU121 + 547 .loc 1 412 13 is_stmt 0 view .LVU122 + 548 0010 044B ldr r3, .L50 + 549 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 550 .loc 1 412 10 view .LVU123 + 551 0014 1C44 add r4, r4, r3 + 552 .LVL23: + 553 .L48: + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** while ((HAL_GetTick() - tickstart) < wait) + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 554 .loc 1 417 3 is_stmt 1 discriminator 1 view .LVU124 + ARM GAS /tmp/ccfvUJpJ.s page 19 + + + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 555 .loc 1 415 9 discriminator 1 view .LVU125 + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 556 .loc 1 415 11 is_stmt 0 discriminator 1 view .LVU126 + 557 0016 FFF7FEFF bl HAL_GetTick + 558 .LVL24: + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 559 .loc 1 415 25 discriminator 1 view .LVU127 + 560 001a 401B subs r0, r0, r5 + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 561 .loc 1 415 9 discriminator 1 view .LVU128 + 562 001c A042 cmp r0, r4 + 563 001e FAD3 bcc .L48 + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 564 .loc 1 418 1 view .LVU129 + 565 0020 38BD pop {r3, r4, r5, pc} + 566 .LVL25: + 567 .L51: + 568 .loc 1 418 1 view .LVU130 + 569 0022 00BF .align 2 + 570 .L50: + 571 0024 00000000 .word .LANCHOR0 + 572 .cfi_endproc + 573 .LFE151: + 575 .section .text.HAL_SuspendTick,"ax",%progbits + 576 .align 1 + 577 .weak HAL_SuspendTick + 578 .syntax unified + 579 .thumb + 580 .thumb_func + 581 .fpu fpv5-d16 + 583 HAL_SuspendTick: + 584 .LFB152: + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Suspend Tick increment. + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * is called, the the SysTick interrupt will be disabled and so Tick increment + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * is suspended. + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * implementations in user file. + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak void HAL_SuspendTick(void) + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 585 .loc 1 431 1 is_stmt 1 view -0 + 586 .cfi_startproc + 587 @ args = 0, pretend = 0, frame = 0 + 588 @ frame_needed = 0, uses_anonymous_args = 0 + 589 @ link register save eliminated. + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Disable SysTick Interrupt */ + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + 590 .loc 1 433 3 view .LVU132 + 591 .loc 1 433 17 is_stmt 0 view .LVU133 + 592 0000 4FF0E022 mov r2, #-536813568 + 593 0004 1369 ldr r3, [r2, #16] + ARM GAS /tmp/ccfvUJpJ.s page 20 + + + 594 0006 23F00203 bic r3, r3, #2 + 595 000a 1361 str r3, [r2, #16] + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 596 .loc 1 434 1 view .LVU134 + 597 000c 7047 bx lr + 598 .cfi_endproc + 599 .LFE152: + 601 .section .text.HAL_ResumeTick,"ax",%progbits + 602 .align 1 + 603 .weak HAL_ResumeTick + 604 .syntax unified + 605 .thumb + 606 .thumb_func + 607 .fpu fpv5-d16 + 609 HAL_ResumeTick: + 610 .LFB153: + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Resume Tick increment. + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * is called, the the SysTick interrupt will be enabled and so Tick increment + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * is resumed. + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * implementations in user file. + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __weak void HAL_ResumeTick(void) + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 611 .loc 1 447 1 is_stmt 1 view -0 + 612 .cfi_startproc + 613 @ args = 0, pretend = 0, frame = 0 + 614 @ frame_needed = 0, uses_anonymous_args = 0 + 615 @ link register save eliminated. + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Enable SysTick Interrupt */ + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + 616 .loc 1 449 3 view .LVU136 + 617 .loc 1 449 18 is_stmt 0 view .LVU137 + 618 0000 4FF0E022 mov r2, #-536813568 + 619 0004 1369 ldr r3, [r2, #16] + 620 0006 43F00203 orr r3, r3, #2 + 621 000a 1361 str r3, [r2, #16] + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 622 .loc 1 450 1 view .LVU138 + 623 000c 7047 bx lr + 624 .cfi_endproc + 625 .LFE153: + 627 .section .text.HAL_GetHalVersion,"ax",%progbits + 628 .align 1 + 629 .global HAL_GetHalVersion + 630 .syntax unified + 631 .thumb + 632 .thumb_func + 633 .fpu fpv5-d16 + 635 HAL_GetHalVersion: + 636 .LFB154: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + ARM GAS /tmp/ccfvUJpJ.s page 21 + + + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Returns the HAL revision + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval version : 0xXYZR (8bits for each decimal, R for RC) + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetHalVersion(void) + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 637 .loc 1 457 1 is_stmt 1 view -0 + 638 .cfi_startproc + 639 @ args = 0, pretend = 0, frame = 0 + 640 @ frame_needed = 0, uses_anonymous_args = 0 + 641 @ link register save eliminated. + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return __STM32H7xx_HAL_VERSION; + 642 .loc 1 458 2 view .LVU140 + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 643 .loc 1 459 1 is_stmt 0 view .LVU141 + 644 0000 0048 ldr r0, .L55 + 645 0002 7047 bx lr + 646 .L56: + 647 .align 2 + 648 .L55: + 649 0004 00000901 .word 17367040 + 650 .cfi_endproc + 651 .LFE154: + 653 .section .text.HAL_GetREVID,"ax",%progbits + 654 .align 1 + 655 .global HAL_GetREVID + 656 .syntax unified + 657 .thumb + 658 .thumb_func + 659 .fpu fpv5-d16 + 661 HAL_GetREVID: + 662 .LFB155: + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Returns the device revision identifier. + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval Device revision identifier + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetREVID(void) + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 663 .loc 1 466 1 is_stmt 1 view -0 + 664 .cfi_startproc + 665 @ args = 0, pretend = 0, frame = 0 + 666 @ frame_needed = 0, uses_anonymous_args = 0 + 667 @ link register save eliminated. + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return((DBGMCU->IDCODE) >> 16); + 668 .loc 1 467 4 view .LVU143 + 669 .loc 1 467 18 is_stmt 0 view .LVU144 + 670 0000 014B ldr r3, .L58 + 671 0002 1868 ldr r0, [r3] + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 672 .loc 1 468 1 view .LVU145 + 673 0004 000C lsrs r0, r0, #16 + 674 0006 7047 bx lr + 675 .L59: + 676 .align 2 + 677 .L58: + 678 0008 0010005C .word 1543507968 + ARM GAS /tmp/ccfvUJpJ.s page 22 + + + 679 .cfi_endproc + 680 .LFE155: + 682 .section .text.HAL_GetDEVID,"ax",%progbits + 683 .align 1 + 684 .global HAL_GetDEVID + 685 .syntax unified + 686 .thumb + 687 .thumb_func + 688 .fpu fpv5-d16 + 690 HAL_GetDEVID: + 691 .LFB156: + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Returns the device identifier. + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval Device identifier + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetDEVID(void) + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 692 .loc 1 475 1 is_stmt 1 view -0 + 693 .cfi_startproc + 694 @ args = 0, pretend = 0, frame = 0 + 695 @ frame_needed = 0, uses_anonymous_args = 0 + 696 @ link register save eliminated. + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + 697 .loc 1 476 4 view .LVU147 + 698 .loc 1 476 18 is_stmt 0 view .LVU148 + 699 0000 024B ldr r3, .L61 + 700 0002 1868 ldr r0, [r3] + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 701 .loc 1 477 1 view .LVU149 + 702 0004 C0F30B00 ubfx r0, r0, #0, #12 + 703 0008 7047 bx lr + 704 .L62: + 705 000a 00BF .align 2 + 706 .L61: + 707 000c 0010005C .word 1543507968 + 708 .cfi_endproc + 709 .LFE156: + 711 .section .text.HAL_GetUIDw0,"ax",%progbits + 712 .align 1 + 713 .global HAL_GetUIDw0 + 714 .syntax unified + 715 .thumb + 716 .thumb_func + 717 .fpu fpv5-d16 + 719 HAL_GetUIDw0: + 720 .LFB157: + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Return the first word of the unique device identifier (UID based on 96 bits) + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval Device identifier + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetUIDw0(void) + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 721 .loc 1 484 1 is_stmt 1 view -0 + 722 .cfi_startproc + 723 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccfvUJpJ.s page 23 + + + 724 @ frame_needed = 0, uses_anonymous_args = 0 + 725 @ link register save eliminated. + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return(READ_REG(*((uint32_t *)UID_BASE))); + 726 .loc 1 485 3 view .LVU151 + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 727 .loc 1 486 1 is_stmt 0 view .LVU152 + 728 0000 014B ldr r3, .L64 + 729 0002 D3F80008 ldr r0, [r3, #2048] + 730 0006 7047 bx lr + 731 .L65: + 732 .align 2 + 733 .L64: + 734 0008 00E0F11F .word 535945216 + 735 .cfi_endproc + 736 .LFE157: + 738 .section .text.HAL_GetUIDw1,"ax",%progbits + 739 .align 1 + 740 .global HAL_GetUIDw1 + 741 .syntax unified + 742 .thumb + 743 .thumb_func + 744 .fpu fpv5-d16 + 746 HAL_GetUIDw1: + 747 .LFB158: + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Return the second word of the unique device identifier (UID based on 96 bits) + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval Device identifier + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetUIDw1(void) + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 748 .loc 1 493 1 is_stmt 1 view -0 + 749 .cfi_startproc + 750 @ args = 0, pretend = 0, frame = 0 + 751 @ frame_needed = 0, uses_anonymous_args = 0 + 752 @ link register save eliminated. + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + 753 .loc 1 494 3 view .LVU154 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 754 .loc 1 495 1 is_stmt 0 view .LVU155 + 755 0000 014B ldr r3, .L67 + 756 0002 D3F80408 ldr r0, [r3, #2052] + 757 0006 7047 bx lr + 758 .L68: + 759 .align 2 + 760 .L67: + 761 0008 00E0F11F .word 535945216 + 762 .cfi_endproc + 763 .LFE158: + 765 .section .text.HAL_GetUIDw2,"ax",%progbits + 766 .align 1 + 767 .global HAL_GetUIDw2 + 768 .syntax unified + 769 .thumb + 770 .thumb_func + 771 .fpu fpv5-d16 + 773 HAL_GetUIDw2: + ARM GAS /tmp/ccfvUJpJ.s page 24 + + + 774 .LFB159: + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Return the third word of the unique device identifier (UID based on 96 bits) + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval Device identifier + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetUIDw2(void) + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 775 .loc 1 502 1 is_stmt 1 view -0 + 776 .cfi_startproc + 777 @ args = 0, pretend = 0, frame = 0 + 778 @ frame_needed = 0, uses_anonymous_args = 0 + 779 @ link register save eliminated. + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + 780 .loc 1 503 3 view .LVU157 + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 781 .loc 1 504 1 is_stmt 0 view .LVU158 + 782 0000 014B ldr r3, .L70 + 783 0002 D3F80808 ldr r0, [r3, #2056] + 784 0006 7047 bx lr + 785 .L71: + 786 .align 2 + 787 .L70: + 788 0008 00E0F11F .word 535945216 + 789 .cfi_endproc + 790 .LFE159: + 792 .section .text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig,"ax",%progbits + 793 .align 1 + 794 .global HAL_SYSCFG_VREFBUF_VoltageScalingConfig + 795 .syntax unified + 796 .thumb + 797 .thumb_func + 798 .fpu fpv5-d16 + 800 HAL_SYSCFG_VREFBUF_VoltageScalingConfig: + 801 .LVL26: + 802 .LFB160: + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Configure the internal voltage reference buffer voltage scale. + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param VoltageScaling specifies the output voltage to achieve + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values: + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This requires VDDA equal to or higher than 2.4 V + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This requires VDDA equal to or higher than 2.8 V + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V. + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This requires VDDA equal to or higher than 1.8 V + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V. + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This requires VDDA equal to or higher than 2.1 V + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 803 .loc 1 521 1 is_stmt 1 view -0 + 804 .cfi_startproc + 805 @ args = 0, pretend = 0, frame = 0 + 806 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccfvUJpJ.s page 25 + + + 807 @ link register save eliminated. + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + 808 .loc 1 523 3 view .LVU160 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); + 809 .loc 1 525 3 view .LVU161 + 810 0000 034A ldr r2, .L73 + 811 0002 1368 ldr r3, [r2] + 812 0004 23F07003 bic r3, r3, #112 + 813 0008 0343 orrs r3, r3, r0 + 814 000a 1360 str r3, [r2] + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 815 .loc 1 526 1 is_stmt 0 view .LVU162 + 816 000c 7047 bx lr + 817 .L74: + 818 000e 00BF .align 2 + 819 .L73: + 820 0010 003C0058 .word 1476410368 + 821 .cfi_endproc + 822 .LFE160: + 824 .section .text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig,"ax",%progbits + 825 .align 1 + 826 .global HAL_SYSCFG_VREFBUF_HighImpedanceConfig + 827 .syntax unified + 828 .thumb + 829 .thumb_func + 830 .fpu fpv5-d16 + 832 HAL_SYSCFG_VREFBUF_HighImpedanceConfig: + 833 .LVL27: + 834 .LFB161: + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Configure the internal voltage reference buffer high impedance mode. + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param Mode specifies the high impedance mode + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values: + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFI + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 835 .loc 1 537 1 is_stmt 1 view -0 + 836 .cfi_startproc + 837 @ args = 0, pretend = 0, frame = 0 + 838 @ frame_needed = 0, uses_anonymous_args = 0 + 839 @ link register save eliminated. + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + 840 .loc 1 539 3 view .LVU164 + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); + 841 .loc 1 541 3 view .LVU165 + 842 0000 034A ldr r2, .L76 + 843 0002 1368 ldr r3, [r2] + 844 0004 23F00203 bic r3, r3, #2 + 845 0008 0343 orrs r3, r3, r0 + ARM GAS /tmp/ccfvUJpJ.s page 26 + + + 846 000a 1360 str r3, [r2] + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 847 .loc 1 542 1 is_stmt 0 view .LVU166 + 848 000c 7047 bx lr + 849 .L77: + 850 000e 00BF .align 2 + 851 .L76: + 852 0010 003C0058 .word 1476410368 + 853 .cfi_endproc + 854 .LFE161: + 856 .section .text.HAL_SYSCFG_VREFBUF_TrimmingConfig,"ax",%progbits + 857 .align 1 + 858 .global HAL_SYSCFG_VREFBUF_TrimmingConfig + 859 .syntax unified + 860 .thumb + 861 .thumb_func + 862 .fpu fpv5-d16 + 864 HAL_SYSCFG_VREFBUF_TrimmingConfig: + 865 .LVL28: + 866 .LFB162: + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 867 .loc 1 549 1 is_stmt 1 view -0 + 868 .cfi_startproc + 869 @ args = 0, pretend = 0, frame = 0 + 870 @ frame_needed = 0, uses_anonymous_args = 0 + 871 @ link register save eliminated. + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + 872 .loc 1 551 3 view .LVU168 + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); + 873 .loc 1 553 3 view .LVU169 + 874 0000 034A ldr r2, .L79 + 875 0002 5368 ldr r3, [r2, #4] + 876 0004 23F03F03 bic r3, r3, #63 + 877 0008 0343 orrs r3, r3, r0 + 878 000a 5360 str r3, [r2, #4] + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 879 .loc 1 554 1 is_stmt 0 view .LVU170 + 880 000c 7047 bx lr + 881 .L80: + 882 000e 00BF .align 2 + 883 .L79: + 884 0010 003C0058 .word 1476410368 + 885 .cfi_endproc + 886 .LFE162: + 888 .section .text.HAL_SYSCFG_EnableVREFBUF,"ax",%progbits + 889 .align 1 + 890 .global HAL_SYSCFG_EnableVREFBUF + 891 .syntax unified + 892 .thumb + ARM GAS /tmp/ccfvUJpJ.s page 27 + + + 893 .thumb_func + 894 .fpu fpv5-d16 + 896 HAL_SYSCFG_EnableVREFBUF: + 897 .LFB163: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval HAL_OK/HAL_TIMEOUT + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 898 .loc 1 561 1 is_stmt 1 view -0 + 899 .cfi_startproc + 900 @ args = 0, pretend = 0, frame = 0 + 901 @ frame_needed = 0, uses_anonymous_args = 0 + 902 0000 10B5 push {r4, lr} + 903 .LCFI5: + 904 .cfi_def_cfa_offset 8 + 905 .cfi_offset 4, -8 + 906 .cfi_offset 14, -4 + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t tickstart; + 907 .loc 1 562 3 view .LVU172 + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + 908 .loc 1 564 3 view .LVU173 + 909 0002 0B4A ldr r2, .L88 + 910 0004 1368 ldr r3, [r2] + 911 0006 43F00103 orr r3, r3, #1 + 912 000a 1360 str r3, [r2] + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Get Start Tick*/ + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** tickstart = HAL_GetTick(); + 913 .loc 1 567 3 view .LVU174 + 914 .loc 1 567 15 is_stmt 0 view .LVU175 + 915 000c FFF7FEFF bl HAL_GetTick + 916 .LVL29: + 917 0010 0446 mov r4, r0 + 918 .LVL30: + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Wait for VRR bit */ + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + 919 .loc 1 570 3 is_stmt 1 view .LVU176 + 920 .L82: + 921 .loc 1 570 8 view .LVU177 + 922 .loc 1 570 9 is_stmt 0 view .LVU178 + 923 0012 074B ldr r3, .L88 + 924 0014 1B68 ldr r3, [r3] + 925 .loc 1 570 8 view .LVU179 + 926 0016 13F0080F tst r3, #8 + 927 001a 06D1 bne .L87 + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + 928 .loc 1 572 5 is_stmt 1 view .LVU180 + 929 .loc 1 572 9 is_stmt 0 view .LVU181 + 930 001c FFF7FEFF bl HAL_GetTick + 931 .LVL31: + 932 .loc 1 572 23 view .LVU182 + ARM GAS /tmp/ccfvUJpJ.s page 28 + + + 933 0020 001B subs r0, r0, r4 + 934 .loc 1 572 7 view .LVU183 + 935 0022 0A28 cmp r0, #10 + 936 0024 F5D9 bls .L82 + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_TIMEOUT; + 937 .loc 1 574 14 view .LVU184 + 938 0026 0320 movs r0, #3 + 939 0028 00E0 b .L83 + 940 .L87: + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return HAL_OK; + 941 .loc 1 578 10 view .LVU185 + 942 002a 0020 movs r0, #0 + 943 .L83: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 944 .loc 1 579 1 view .LVU186 + 945 002c 10BD pop {r4, pc} + 946 .LVL32: + 947 .L89: + 948 .loc 1 579 1 view .LVU187 + 949 002e 00BF .align 2 + 950 .L88: + 951 0030 003C0058 .word 1476410368 + 952 .cfi_endproc + 953 .LFE163: + 955 .section .text.HAL_SYSCFG_DisableVREFBUF,"ax",%progbits + 956 .align 1 + 957 .global HAL_SYSCFG_DisableVREFBUF + 958 .syntax unified + 959 .thumb + 960 .thumb_func + 961 .fpu fpv5-d16 + 963 HAL_SYSCFG_DisableVREFBUF: + 964 .LFB164: + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_DisableVREFBUF(void) + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 965 .loc 1 587 1 is_stmt 1 view -0 + 966 .cfi_startproc + 967 @ args = 0, pretend = 0, frame = 0 + 968 @ frame_needed = 0, uses_anonymous_args = 0 + 969 @ link register save eliminated. + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + 970 .loc 1 588 3 view .LVU189 + 971 0000 024A ldr r2, .L91 + 972 0002 1368 ldr r3, [r2] + 973 0004 23F00103 bic r3, r3, #1 + 974 0008 1360 str r3, [r2] + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + ARM GAS /tmp/ccfvUJpJ.s page 29 + + + 975 .loc 1 589 1 is_stmt 0 view .LVU190 + 976 000a 7047 bx lr + 977 .L92: + 978 .align 2 + 979 .L91: + 980 000c 003C0058 .word 1476410368 + 981 .cfi_endproc + 982 .LFE164: + 984 .section .text.HAL_SYSCFG_ETHInterfaceSelect,"ax",%progbits + 985 .align 1 + 986 .global HAL_SYSCFG_ETHInterfaceSelect + 987 .syntax unified + 988 .thumb + 989 .thumb_func + 990 .fpu fpv5-d16 + 992 HAL_SYSCFG_ETHInterfaceSelect: + 993 .LVL33: + 994 .LFB165: + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_PMCR_EPIS_SEL) + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Ethernet PHY Interface Selection either MII or RMII + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values: + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_ETH_MII : Select the Media Independent Interface + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 995 .loc 1 601 1 is_stmt 1 view -0 + 996 .cfi_startproc + 997 @ args = 0, pretend = 0, frame = 0 + 998 @ frame_needed = 0, uses_anonymous_args = 0 + 999 @ link register save eliminated. + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface)); + 1000 .loc 1 603 3 view .LVU192 + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); + 1001 .loc 1 605 3 view .LVU193 + 1002 0000 034A ldr r2, .L94 + 1003 0002 5368 ldr r3, [r2, #4] + 1004 0004 23F46003 bic r3, r3, #14680064 + 1005 0008 0343 orrs r3, r3, r0 + 1006 000a 5360 str r3, [r2, #4] + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1007 .loc 1 606 1 is_stmt 0 view .LVU194 + 1008 000c 7047 bx lr + 1009 .L95: + 1010 000e 00BF .align 2 + 1011 .L94: + 1012 0010 00040058 .word 1476396032 + 1013 .cfi_endproc + 1014 .LFE165: + 1016 .section .text.HAL_SYSCFG_AnalogSwitchConfig,"ax",%progbits + 1017 .align 1 + ARM GAS /tmp/ccfvUJpJ.s page 30 + + + 1018 .global HAL_SYSCFG_AnalogSwitchConfig + 1019 .syntax unified + 1020 .thumb + 1021 .thumb_func + 1022 .fpu fpv5-d16 + 1024 HAL_SYSCFG_AnalogSwitchConfig: + 1025 .LVL34: + 1026 .LFB166: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* SYSCFG_PMCR_EPIS_SEL */ + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Analog Switch control for dual analog pads. + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_AnalogSwitch: Selects the analog pad + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one or a combination of the following values: + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C) + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one or a combination of the following values: + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PA0_OPEN + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PA0_CLOSE + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PA1_OPEN + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PA1_CLOSE + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PC2_OPEN + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PC2_CLOSE + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PC3_OPEN + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_SWITCH_PC3_CLOSE + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1027 .loc 1 631 1 is_stmt 1 view -0 + 1028 .cfi_startproc + 1029 @ args = 0, pretend = 0, frame = 0 + 1030 @ frame_needed = 0, uses_anonymous_args = 0 + 1031 @ link register save eliminated. + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); + 1032 .loc 1 633 3 view .LVU196 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); + 1033 .loc 1 634 3 view .LVU197 + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); + 1034 .loc 1 636 3 view .LVU198 + 1035 0000 034A ldr r2, .L97 + 1036 0002 5368 ldr r3, [r2, #4] + 1037 0004 23EA0003 bic r3, r3, r0 + 1038 0008 0B43 orrs r3, r3, r1 + 1039 000a 5360 str r3, [r2, #4] + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1040 .loc 1 637 1 is_stmt 0 view .LVU199 + 1041 000c 7047 bx lr + 1042 .L98: + 1043 000e 00BF .align 2 + 1044 .L97: + ARM GAS /tmp/ccfvUJpJ.s page 31 + + + 1045 0010 00040058 .word 1476396032 + 1046 .cfi_endproc + 1047 .LFE166: + 1049 .section .text.HAL_SYSCFG_EnableBOOST,"ax",%progbits + 1050 .align 1 + 1051 .global HAL_SYSCFG_EnableBOOST + 1052 .syntax unified + 1053 .thumb + 1054 .thumb_func + 1055 .fpu fpv5-d16 + 1057 HAL_SYSCFG_EnableBOOST: + 1058 .LFB167: + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_PMCR_BOOSTEN) + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enables the booster to reduce the total harmonic distortion of the analog + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * switch when the supply voltage is lower than 2.7 V. + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note Activating the booster allows to guaranty the analog switch AC performance + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * when the supply voltage is below 2.7 V: in this case, the analog switch + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * performance is the same on the full voltage range + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_EnableBOOST(void) + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1059 .loc 1 649 1 is_stmt 1 view -0 + 1060 .cfi_startproc + 1061 @ args = 0, pretend = 0, frame = 0 + 1062 @ frame_needed = 0, uses_anonymous_args = 0 + 1063 @ link register save eliminated. + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; + 1064 .loc 1 650 2 view .LVU201 + 1065 0000 024A ldr r2, .L100 + 1066 0002 5368 ldr r3, [r2, #4] + 1067 0004 43F48073 orr r3, r3, #256 + 1068 0008 5360 str r3, [r2, #4] + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1069 .loc 1 651 1 is_stmt 0 view .LVU202 + 1070 000a 7047 bx lr + 1071 .L101: + 1072 .align 2 + 1073 .L100: + 1074 000c 00040058 .word 1476396032 + 1075 .cfi_endproc + 1076 .LFE167: + 1078 .section .text.HAL_SYSCFG_DisableBOOST,"ax",%progbits + 1079 .align 1 + 1080 .global HAL_SYSCFG_DisableBOOST + 1081 .syntax unified + 1082 .thumb + 1083 .thumb_func + 1084 .fpu fpv5-d16 + 1086 HAL_SYSCFG_DisableBOOST: + 1087 .LFB168: + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disables the booster + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note Activating the booster allows to guaranty the analog switch AC performance + ARM GAS /tmp/ccfvUJpJ.s page 32 + + + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * when the supply voltage is below 2.7 V: in this case, the analog switch + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * performance is the same on the full voltage range + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_DisableBOOST(void) + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1088 .loc 1 661 1 is_stmt 1 view -0 + 1089 .cfi_startproc + 1090 @ args = 0, pretend = 0, frame = 0 + 1091 @ frame_needed = 0, uses_anonymous_args = 0 + 1092 @ link register save eliminated. + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; + 1093 .loc 1 662 2 view .LVU204 + 1094 0000 024A ldr r2, .L103 + 1095 0002 5368 ldr r3, [r2, #4] + 1096 0004 23F48073 bic r3, r3, #256 + 1097 0008 5360 str r3, [r2, #4] + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1098 .loc 1 663 1 is_stmt 0 view .LVU205 + 1099 000a 7047 bx lr + 1100 .L104: + 1101 .align 2 + 1102 .L103: + 1103 000c 00040058 .word 1476396032 + 1104 .cfi_endproc + 1105 .LFE168: + 1107 .section .text.HAL_SYSCFG_CM7BootAddConfig,"ax",%progbits + 1108 .align 1 + 1109 .global HAL_SYSCFG_CM7BootAddConfig + 1110 .syntax unified + 1111 .thumb + 1112 .thumb_func + 1113 .fpu fpv5-d16 + 1115 HAL_SYSCFG_CM7BootAddConfig: + 1116 .LVL35: + 1117 .LFB169: + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* SYSCFG_PMCR_BOOSTEN */ + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief BootCM7 address 0 configuration + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values: + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1 + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1118 .loc 1 677 1 is_stmt 1 view -0 + 1119 .cfi_startproc + 1120 @ args = 0, pretend = 0, frame = 0 + 1121 @ frame_needed = 0, uses_anonymous_args = 0 + 1122 @ link register save eliminated. + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + ARM GAS /tmp/ccfvUJpJ.s page 33 + + + 1123 .loc 1 679 3 view .LVU207 + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + 1124 .loc 1 680 3 view .LVU208 + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + 1125 .loc 1 681 3 view .LVU209 + 1126 .loc 1 681 6 is_stmt 0 view .LVU210 + 1127 0000 48B9 cbnz r0, .L106 + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure CM7 BOOT ADD0 */ + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos) + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos) + 1128 .loc 1 687 5 is_stmt 1 view .LVU211 + 1129 0002 0A48 ldr r0, .L108 + 1130 .LVL36: + 1131 .loc 1 687 5 is_stmt 0 view .LVU212 + 1132 0004 D0F80833 ldr r3, [r0, #776] + 1133 0008 9BB2 uxth r3, r3 + 1134 000a 094A ldr r2, .L108+4 + 1135 000c 0A40 ands r2, r2, r1 + 1136 000e 1343 orrs r3, r3, r2 + 1137 0010 C0F80833 str r3, [r0, #776] + 1138 0014 7047 bx lr + 1139 .LVL37: + 1140 .L106: + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*DUAL_CORE*/ + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure CM7 BOOT ADD1 */ + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16)); + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16)); + 1141 .loc 1 696 5 is_stmt 1 view .LVU213 + 1142 0016 054A ldr r2, .L108 + 1143 0018 D2F80C03 ldr r0, [r2, #780] + 1144 .LVL38: + 1145 .loc 1 696 5 is_stmt 0 view .LVU214 + 1146 001c 044B ldr r3, .L108+4 + 1147 001e 0340 ands r3, r3, r0 + 1148 0020 43EA1141 orr r1, r3, r1, lsr #16 + 1149 .LVL39: + 1150 .loc 1 696 5 view .LVU215 + 1151 0024 C2F80C13 str r1, [r2, #780] + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*DUAL_CORE*/ + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1152 .loc 1 699 1 view .LVU216 + 1153 0028 7047 bx lr + 1154 .L109: + 1155 002a 00BF .align 2 + 1156 .L108: + 1157 002c 00040058 .word 1476396032 + 1158 0030 0000FFFF .word -65536 + 1159 .cfi_endproc + ARM GAS /tmp/ccfvUJpJ.s page 34 + + + 1160 .LFE169: + 1162 .section .text.HAL_EnableCompensationCell,"ax",%progbits + 1163 .align 1 + 1164 .global HAL_EnableCompensationCell + 1165 .syntax unified + 1166 .thumb + 1167 .thumb_func + 1168 .fpu fpv5-d16 + 1170 HAL_EnableCompensationCell: + 1171 .LFB170: + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */ + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief BootCM4 address 0 configuration + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values: + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1 + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure CM4 BOOT ADD0 */ + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos)) + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Configure CM4 BOOT ADD1 */ + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16)); + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enables the Cortex-M7 boot + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_EnableCM7BOOT(void) + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7); + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disables the Cortex-M7 boot + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note Disabling the boot will gate the CPU clock + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_DisableCM7BOOT(void) + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + ARM GAS /tmp/ccfvUJpJ.s page 35 + + + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ; + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enables the Cortex-M4 boot + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_EnableCM4BOOT(void) + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disables the Cortex-M4 boot + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note Disabling the boot will gate the CPU clock + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_DisableCM4BOOT(void) + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*DUAL_CORE*/ + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enables the I/O Compensation Cell. + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note The I/O compensation cell can be used only when the device supply + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * voltage ranges from 2.4 to 3.6 V. + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableCompensationCell(void) + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1172 .loc 1 776 1 is_stmt 1 view -0 + 1173 .cfi_startproc + 1174 @ args = 0, pretend = 0, frame = 0 + 1175 @ frame_needed = 0, uses_anonymous_args = 0 + 1176 @ link register save eliminated. + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ; + 1177 .loc 1 777 3 view .LVU218 + 1178 0000 024A ldr r2, .L111 + 1179 0002 136A ldr r3, [r2, #32] + 1180 0004 43F00103 orr r3, r3, #1 + 1181 0008 1362 str r3, [r2, #32] + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1182 .loc 1 778 1 is_stmt 0 view .LVU219 + 1183 000a 7047 bx lr + 1184 .L112: + 1185 .align 2 + 1186 .L111: + 1187 000c 00040058 .word 1476396032 + 1188 .cfi_endproc + 1189 .LFE170: + 1191 .section .text.HAL_DisableCompensationCell,"ax",%progbits + 1192 .align 1 + 1193 .global HAL_DisableCompensationCell + 1194 .syntax unified + 1195 .thumb + 1196 .thumb_func + 1197 .fpu fpv5-d16 + ARM GAS /tmp/ccfvUJpJ.s page 36 + + + 1199 HAL_DisableCompensationCell: + 1200 .LFB171: + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Power-down the I/O Compensation Cell. + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note The I/O compensation cell can be used only when the device supply + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * voltage ranges from 2.4 to 3.6 V. + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableCompensationCell(void) + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1201 .loc 1 787 1 is_stmt 1 view -0 + 1202 .cfi_startproc + 1203 @ args = 0, pretend = 0, frame = 0 + 1204 @ frame_needed = 0, uses_anonymous_args = 0 + 1205 @ link register save eliminated. + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); + 1206 .loc 1 788 3 view .LVU221 + 1207 0000 024A ldr r2, .L114 + 1208 0002 136A ldr r3, [r2, #32] + 1209 0004 23F00103 bic r3, r3, #1 + 1210 0008 1362 str r3, [r2, #32] + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1211 .loc 1 789 1 is_stmt 0 view .LVU222 + 1212 000a 7047 bx lr + 1213 .L115: + 1214 .align 2 + 1215 .L114: + 1216 000c 00040058 .word 1476396032 + 1217 .cfi_endproc + 1218 .LFE171: + 1220 .section .text.HAL_SYSCFG_EnableIOSpeedOptimize,"ax",%progbits + 1221 .align 1 + 1222 .global HAL_SYSCFG_EnableIOSpeedOptimize + 1223 .syntax unified + 1224 .thumb + 1225 .thumb_func + 1226 .fpu fpv5-d16 + 1228 HAL_SYSCFG_EnableIOSpeedOptimize: + 1229 .LFB172: + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief To Enable optimize the I/O speed when the product voltage is low. + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * higher than 2.5 V might be destructive. + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_EnableIOSpeedOptimize(void) + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1230 .loc 1 800 1 is_stmt 1 view -0 + 1231 .cfi_startproc + 1232 @ args = 0, pretend = 0, frame = 0 + 1233 @ frame_needed = 0, uses_anonymous_args = 0 + 1234 @ link register save eliminated. + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_CCCSR_HSLV) + ARM GAS /tmp/ccfvUJpJ.s page 37 + + + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); + 1235 .loc 1 802 3 view .LVU224 + 1236 0000 024A ldr r2, .L117 + 1237 0002 136A ldr r3, [r2, #32] + 1238 0004 43F48033 orr r3, r3, #65536 + 1239 0008 1362 str r3, [r2, #32] + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCC + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* SYSCFG_CCCSR_HSLV */ + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1240 .loc 1 806 1 is_stmt 0 view .LVU225 + 1241 000a 7047 bx lr + 1242 .L118: + 1243 .align 2 + 1244 .L117: + 1245 000c 00040058 .word 1476396032 + 1246 .cfi_endproc + 1247 .LFE172: + 1249 .section .text.HAL_SYSCFG_DisableIOSpeedOptimize,"ax",%progbits + 1250 .align 1 + 1251 .global HAL_SYSCFG_DisableIOSpeedOptimize + 1252 .syntax unified + 1253 .thumb + 1254 .thumb_func + 1255 .fpu fpv5-d16 + 1257 HAL_SYSCFG_DisableIOSpeedOptimize: + 1258 .LFB173: + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief To Disable optimize the I/O speed when the product voltage is low. + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * higher than 2.5 V might be destructive. + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_DisableIOSpeedOptimize(void) + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1259 .loc 1 816 1 is_stmt 1 view -0 + 1260 .cfi_startproc + 1261 @ args = 0, pretend = 0, frame = 0 + 1262 @ frame_needed = 0, uses_anonymous_args = 0 + 1263 @ link register save eliminated. + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_CCCSR_HSLV) + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); + 1264 .loc 1 818 3 view .LVU227 + 1265 0000 024A ldr r2, .L120 + 1266 0002 136A ldr r3, [r2, #32] + 1267 0004 23F48033 bic r3, r3, #65536 + 1268 0008 1362 str r3, [r2, #32] + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #else + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_C + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* SYSCFG_CCCSR_HSLV */ + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1269 .loc 1 822 1 is_stmt 0 view .LVU228 + 1270 000a 7047 bx lr + 1271 .L121: + 1272 .align 2 + ARM GAS /tmp/ccfvUJpJ.s page 38 + + + 1273 .L120: + 1274 000c 00040058 .word 1476396032 + 1275 .cfi_endproc + 1276 .LFE173: + 1278 .section .text.HAL_SYSCFG_CompensationCodeSelect,"ax",%progbits + 1279 .align 1 + 1280 .global HAL_SYSCFG_CompensationCodeSelect + 1281 .syntax unified + 1282 .thumb + 1283 .thumb_func + 1284 .fpu fpv5-d16 + 1286 HAL_SYSCFG_CompensationCodeSelect: + 1287 .LVL40: + 1288 .LFB174: + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Code selection for the I/O Compensation cell + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values: + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCF + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode) + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1289 .loc 1 833 1 is_stmt 1 view -0 + 1290 .cfi_startproc + 1291 @ args = 0, pretend = 0, frame = 0 + 1292 @ frame_needed = 0, uses_anonymous_args = 0 + 1293 @ link register save eliminated. + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode)); + 1294 .loc 1 835 3 view .LVU230 + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode)); + 1295 .loc 1 836 3 view .LVU231 + 1296 0000 034A ldr r2, .L123 + 1297 0002 136A ldr r3, [r2, #32] + 1298 0004 23F00203 bic r3, r3, #2 + 1299 0008 0343 orrs r3, r3, r0 + 1300 000a 1362 str r3, [r2, #32] + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1301 .loc 1 837 1 is_stmt 0 view .LVU232 + 1302 000c 7047 bx lr + 1303 .L124: + 1304 000e 00BF .align 2 + 1305 .L123: + 1306 0010 00040058 .word 1476396032 + 1307 .cfi_endproc + 1308 .LFE174: + 1310 .section .text.HAL_SYSCFG_CompensationCodeConfig,"ax",%progbits + 1311 .align 1 + 1312 .global HAL_SYSCFG_CompensationCodeConfig + 1313 .syntax unified + 1314 .thumb + 1315 .thumb_func + 1316 .fpu fpv5-d16 + 1318 HAL_SYSCFG_CompensationCodeConfig: + ARM GAS /tmp/ccfvUJpJ.s page 39 + + + 1319 .LVL41: + 1320 .LFB175: + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Code selection for the I/O Compensation cell + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_PMOSCode: PMOS compensation code + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This code is applied to the I/O compensation cell when the CS bit of the + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * SYSCFG_CMPCR is set + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_NMOSCode: NMOS compensation code + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This code is applied to the I/O compensation cell when the CS bit of the + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * SYSCFG_CMPCR is set + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1321 .loc 1 850 1 is_stmt 1 view -0 + 1322 .cfi_startproc + 1323 @ args = 0, pretend = 0, frame = 0 + 1324 @ frame_needed = 0, uses_anonymous_args = 0 + 1325 @ link register save eliminated. + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + 1326 .loc 1 852 3 view .LVU234 + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + 1327 .loc 1 853 3 view .LVU235 + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uin + 1328 .loc 1 854 3 view .LVU236 + 1329 0000 044A ldr r2, .L126 + 1330 0002 936A ldr r3, [r2, #40] + 1331 0004 23F0FF03 bic r3, r3, #255 + 1332 0008 41EA0011 orr r1, r1, r0, lsl #4 + 1333 .LVL42: + 1334 .loc 1 854 3 is_stmt 0 view .LVU237 + 1335 000c 0B43 orrs r3, r3, r1 + 1336 000e 9362 str r3, [r2, #40] + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1337 .loc 1 855 1 view .LVU238 + 1338 0010 7047 bx lr + 1339 .L127: + 1340 0012 00BF .align 2 + 1341 .L126: + 1342 0014 00040058 .word 1476396032 + 1343 .cfi_endproc + 1344 .LFE175: + 1346 .section .text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits + 1347 .align 1 + 1348 .global HAL_DBGMCU_EnableDBGSleepMode + 1349 .syntax unified + 1350 .thumb + 1351 .thumb_func + 1352 .fpu fpv5-d16 + 1354 HAL_DBGMCU_EnableDBGSleepMode: + 1355 .LFB176: + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_CCCR_NCC_MMC) + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Code selection for the I/O Compensation cell + ARM GAS /tmp/ccfvUJpJ.s page 40 + + + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This code is applied to the I/O compensation cell when the CS bit of the + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * SYSCFG_CMPCR is set + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This code is applied to the I/O compensation cell when the CS bit of the + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * SYSCFG_CMPCR is set + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCod + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /* SYSCFG_CCCR_NCC_MMC */ + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @brief SYSCFG ADC2 internal input alternate connection macros + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param Adc2AltRout0 This parameter can be a value of : + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16] + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16] + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0) + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0)); + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0); + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @} + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** @brief SYSCFG ADC2 internal input alternate connection macros + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param Adc2AltRout1 This parameter can be a value of : + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17] + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17] + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1)); + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1); + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @} + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + ARM GAS /tmp/ccfvUJpJ.s page 41 + + + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDBGSleepMode(void) + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1356 .loc 1 918 1 is_stmt 1 view -0 + 1357 .cfi_startproc + 1358 @ args = 0, pretend = 0, frame = 0 + 1359 @ frame_needed = 0, uses_anonymous_args = 0 + 1360 @ link register save eliminated. + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); + 1361 .loc 1 919 3 view .LVU240 + 1362 0000 024A ldr r2, .L129 + 1363 0002 5368 ldr r3, [r2, #4] + 1364 0004 43F00103 orr r3, r3, #1 + 1365 0008 5360 str r3, [r2, #4] + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1366 .loc 1 920 1 is_stmt 0 view .LVU241 + 1367 000a 7047 bx lr + 1368 .L130: + 1369 .align 2 + 1370 .L129: + 1371 000c 0010005C .word 1543507968 + 1372 .cfi_endproc + 1373 .LFE176: + 1375 .section .text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits + 1376 .align 1 + 1377 .global HAL_DBGMCU_DisableDBGSleepMode + 1378 .syntax unified + 1379 .thumb + 1380 .thumb_func + 1381 .fpu fpv5-d16 + 1383 HAL_DBGMCU_DisableDBGSleepMode: + 1384 .LFB177: + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDBGSleepMode(void) + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1385 .loc 1 927 1 is_stmt 1 view -0 + 1386 .cfi_startproc + 1387 @ args = 0, pretend = 0, frame = 0 + 1388 @ frame_needed = 0, uses_anonymous_args = 0 + 1389 @ link register save eliminated. + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); + 1390 .loc 1 928 3 view .LVU243 + 1391 0000 024A ldr r2, .L132 + 1392 0002 5368 ldr r3, [r2, #4] + 1393 0004 23F00103 bic r3, r3, #1 + 1394 0008 5360 str r3, [r2, #4] + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1395 .loc 1 929 1 is_stmt 0 view .LVU244 + 1396 000a 7047 bx lr + 1397 .L133: + 1398 .align 2 + 1399 .L132: + 1400 000c 0010005C .word 1543507968 + 1401 .cfi_endproc + ARM GAS /tmp/ccfvUJpJ.s page 42 + + + 1402 .LFE177: + 1404 .section .text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits + 1405 .align 1 + 1406 .global HAL_DBGMCU_EnableDBGStopMode + 1407 .syntax unified + 1408 .thumb + 1409 .thumb_func + 1410 .fpu fpv5-d16 + 1412 HAL_DBGMCU_EnableDBGStopMode: + 1413 .LFB178: + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain1/CDomain STOP mode + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDBGStopMode(void) + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1414 .loc 1 937 1 is_stmt 1 view -0 + 1415 .cfi_startproc + 1416 @ args = 0, pretend = 0, frame = 0 + 1417 @ frame_needed = 0, uses_anonymous_args = 0 + 1418 @ link register save eliminated. + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); + 1419 .loc 1 938 3 view .LVU246 + 1420 0000 024A ldr r2, .L135 + 1421 0002 5368 ldr r3, [r2, #4] + 1422 0004 43F00203 orr r3, r3, #2 + 1423 0008 5360 str r3, [r2, #4] + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1424 .loc 1 939 1 is_stmt 0 view .LVU247 + 1425 000a 7047 bx lr + 1426 .L136: + 1427 .align 2 + 1428 .L135: + 1429 000c 0010005C .word 1543507968 + 1430 .cfi_endproc + 1431 .LFE178: + 1433 .section .text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits + 1434 .align 1 + 1435 .global HAL_DBGMCU_DisableDBGStopMode + 1436 .syntax unified + 1437 .thumb + 1438 .thumb_func + 1439 .fpu fpv5-d16 + 1441 HAL_DBGMCU_DisableDBGStopMode: + 1442 .LFB179: + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain1/CDomain STOP mode + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDBGStopMode(void) + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1443 .loc 1 946 1 is_stmt 1 view -0 + 1444 .cfi_startproc + 1445 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccfvUJpJ.s page 43 + + + 1446 @ frame_needed = 0, uses_anonymous_args = 0 + 1447 @ link register save eliminated. + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); + 1448 .loc 1 947 3 view .LVU249 + 1449 0000 024A ldr r2, .L138 + 1450 0002 5368 ldr r3, [r2, #4] + 1451 0004 23F00203 bic r3, r3, #2 + 1452 0008 5360 str r3, [r2, #4] + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1453 .loc 1 948 1 is_stmt 0 view .LVU250 + 1454 000a 7047 bx lr + 1455 .L139: + 1456 .align 2 + 1457 .L138: + 1458 000c 0010005C .word 1543507968 + 1459 .cfi_endproc + 1460 .LFE179: + 1462 .section .text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits + 1463 .align 1 + 1464 .global HAL_DBGMCU_EnableDBGStandbyMode + 1465 .syntax unified + 1466 .thumb + 1467 .thumb_func + 1468 .fpu fpv5-d16 + 1470 HAL_DBGMCU_EnableDBGStandbyMode: + 1471 .LFB180: + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDBGStandbyMode(void) + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1472 .loc 1 955 1 is_stmt 1 view -0 + 1473 .cfi_startproc + 1474 @ args = 0, pretend = 0, frame = 0 + 1475 @ frame_needed = 0, uses_anonymous_args = 0 + 1476 @ link register save eliminated. + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); + 1477 .loc 1 956 3 view .LVU252 + 1478 0000 024A ldr r2, .L141 + 1479 0002 5368 ldr r3, [r2, #4] + 1480 0004 43F00403 orr r3, r3, #4 + 1481 0008 5360 str r3, [r2, #4] + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1482 .loc 1 957 1 is_stmt 0 view .LVU253 + 1483 000a 7047 bx lr + 1484 .L142: + 1485 .align 2 + 1486 .L141: + 1487 000c 0010005C .word 1543507968 + 1488 .cfi_endproc + 1489 .LFE180: + 1491 .section .text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits + 1492 .align 1 + 1493 .global HAL_DBGMCU_DisableDBGStandbyMode + 1494 .syntax unified + ARM GAS /tmp/ccfvUJpJ.s page 44 + + + 1495 .thumb + 1496 .thumb_func + 1497 .fpu fpv5-d16 + 1499 HAL_DBGMCU_DisableDBGStandbyMode: + 1500 .LFB181: + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDBGStandbyMode(void) + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1501 .loc 1 964 1 is_stmt 1 view -0 + 1502 .cfi_startproc + 1503 @ args = 0, pretend = 0, frame = 0 + 1504 @ frame_needed = 0, uses_anonymous_args = 0 + 1505 @ link register save eliminated. + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); + 1506 .loc 1 965 3 view .LVU255 + 1507 0000 024A ldr r2, .L144 + 1508 0002 5368 ldr r3, [r2, #4] + 1509 0004 23F00403 bic r3, r3, #4 + 1510 0008 5360 str r3, [r2, #4] + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1511 .loc 1 966 1 is_stmt 0 view .LVU256 + 1512 000a 7047 bx lr + 1513 .L145: + 1514 .align 2 + 1515 .L144: + 1516 000c 0010005C .word 1543507968 + 1517 .cfi_endproc + 1518 .LFE181: + 1520 .section .text.HAL_EnableDomain3DBGStopMode,"ax",%progbits + 1521 .align 1 + 1522 .global HAL_EnableDomain3DBGStopMode + 1523 .syntax unified + 1524 .thumb + 1525 .thumb_func + 1526 .fpu fpv5-d16 + 1528 HAL_EnableDomain3DBGStopMode: + 1529 .LFB182: + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain1 SLEEP mode + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDomain2DBGSleepMode(void) + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain2 SLEEP mode + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDomain2DBGSleepMode(void) + ARM GAS /tmp/ccfvUJpJ.s page 45 + + + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain2 STOP mode + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDomain2DBGStopMode(void) + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain2 STOP mode + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDomain2DBGStopMode(void) +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain2 STANDBY mode +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDomain2DBGStandbyMode(void) +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain2 STANDBY mode +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDomain2DBGStandbyMode(void) +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*DUAL_CORE*/ +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain3/SRDomain STOP mode +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDomain3DBGStopMode(void) +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1530 .loc 1 1029 1 is_stmt 1 view -0 + 1531 .cfi_startproc + 1532 @ args = 0, pretend = 0, frame = 0 + 1533 @ frame_needed = 0, uses_anonymous_args = 0 + 1534 @ link register save eliminated. +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); + 1535 .loc 1 1030 3 view .LVU258 + 1536 0000 024A ldr r2, .L147 + 1537 0002 5368 ldr r3, [r2, #4] + 1538 0004 43F08003 orr r3, r3, #128 + ARM GAS /tmp/ccfvUJpJ.s page 46 + + + 1539 0008 5360 str r3, [r2, #4] +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1540 .loc 1 1031 1 is_stmt 0 view .LVU259 + 1541 000a 7047 bx lr + 1542 .L148: + 1543 .align 2 + 1544 .L147: + 1545 000c 0010005C .word 1543507968 + 1546 .cfi_endproc + 1547 .LFE182: + 1549 .section .text.HAL_DisableDomain3DBGStopMode,"ax",%progbits + 1550 .align 1 + 1551 .global HAL_DisableDomain3DBGStopMode + 1552 .syntax unified + 1553 .thumb + 1554 .thumb_func + 1555 .fpu fpv5-d16 + 1557 HAL_DisableDomain3DBGStopMode: + 1558 .LFB183: +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain3/SRDomain STOP mode +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDomain3DBGStopMode(void) +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1559 .loc 1 1037 1 is_stmt 1 view -0 + 1560 .cfi_startproc + 1561 @ args = 0, pretend = 0, frame = 0 + 1562 @ frame_needed = 0, uses_anonymous_args = 0 + 1563 @ link register save eliminated. +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); + 1564 .loc 1 1038 3 view .LVU261 + 1565 0000 024A ldr r2, .L150 + 1566 0002 5368 ldr r3, [r2, #4] + 1567 0004 23F08003 bic r3, r3, #128 + 1568 0008 5360 str r3, [r2, #4] +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1569 .loc 1 1039 1 is_stmt 0 view .LVU262 + 1570 000a 7047 bx lr + 1571 .L151: + 1572 .align 2 + 1573 .L150: + 1574 000c 0010005C .word 1543507968 + 1575 .cfi_endproc + 1576 .LFE183: + 1578 .section .text.HAL_EnableDomain3DBGStandbyMode,"ax",%progbits + 1579 .align 1 + 1580 .global HAL_EnableDomain3DBGStandbyMode + 1581 .syntax unified + 1582 .thumb + 1583 .thumb_func + 1584 .fpu fpv5-d16 + 1586 HAL_EnableDomain3DBGStandbyMode: + 1587 .LFB184: +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode + ARM GAS /tmp/ccfvUJpJ.s page 47 + + +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EnableDomain3DBGStandbyMode(void) +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1588 .loc 1 1046 1 is_stmt 1 view -0 + 1589 .cfi_startproc + 1590 @ args = 0, pretend = 0, frame = 0 + 1591 @ frame_needed = 0, uses_anonymous_args = 0 + 1592 @ link register save eliminated. +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); + 1593 .loc 1 1047 3 view .LVU264 + 1594 0000 024A ldr r2, .L153 + 1595 0002 5368 ldr r3, [r2, #4] + 1596 0004 43F48073 orr r3, r3, #256 + 1597 0008 5360 str r3, [r2, #4] +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1598 .loc 1 1048 1 is_stmt 0 view .LVU265 + 1599 000a 7047 bx lr + 1600 .L154: + 1601 .align 2 + 1602 .L153: + 1603 000c 0010005C .word 1543507968 + 1604 .cfi_endproc + 1605 .LFE184: + 1607 .section .text.HAL_DisableDomain3DBGStandbyMode,"ax",%progbits + 1608 .align 1 + 1609 .global HAL_DisableDomain3DBGStandbyMode + 1610 .syntax unified + 1611 .thumb + 1612 .thumb_func + 1613 .fpu fpv5-d16 + 1615 HAL_DisableDomain3DBGStandbyMode: + 1616 .LFB185: +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_DisableDomain3DBGStandbyMode(void) +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1617 .loc 1 1055 1 is_stmt 1 view -0 + 1618 .cfi_startproc + 1619 @ args = 0, pretend = 0, frame = 0 + 1620 @ frame_needed = 0, uses_anonymous_args = 0 + 1621 @ link register save eliminated. +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); + 1622 .loc 1 1056 3 view .LVU267 + 1623 0000 024A ldr r2, .L156 + 1624 0002 5368 ldr r3, [r2, #4] + 1625 0004 23F48073 bic r3, r3, #256 + 1626 0008 5360 str r3, [r2, #4] +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1627 .loc 1 1057 1 is_stmt 0 view .LVU268 + 1628 000a 7047 bx lr + 1629 .L157: + 1630 .align 2 + 1631 .L156: + ARM GAS /tmp/ccfvUJpJ.s page 48 + + + 1632 000c 0010005C .word 1543507968 + 1633 .cfi_endproc + 1634 .LFE185: + 1636 .section .text.HAL_SetFMCMemorySwappingConfig,"ax",%progbits + 1637 .align 1 + 1638 .global HAL_SetFMCMemorySwappingConfig + 1639 .syntax unified + 1640 .thumb + 1641 .thumb_func + 1642 .fpu fpv5-d16 + 1644 HAL_SetFMCMemorySwappingConfig: + 1645 .LVL43: + 1646 .LFB186: +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Set the FMC Memory Mapping Swapping config. +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval HAL state +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig) +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1647 .loc 1 1066 1 is_stmt 1 view -0 + 1648 .cfi_startproc + 1649 @ args = 0, pretend = 0, frame = 0 + 1650 @ frame_needed = 0, uses_anonymous_args = 0 + 1651 @ link register save eliminated. +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig)); + 1652 .loc 1 1068 3 view .LVU270 +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig); + 1653 .loc 1 1069 3 view .LVU271 + 1654 0000 034A ldr r2, .L159 + 1655 0002 1368 ldr r3, [r2] + 1656 0004 23F04073 bic r3, r3, #50331648 + 1657 0008 0343 orrs r3, r3, r0 + 1658 000a 1360 str r3, [r2] +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1659 .loc 1 1070 1 is_stmt 0 view .LVU272 + 1660 000c 7047 bx lr + 1661 .L160: + 1662 000e 00BF .align 2 + 1663 .L159: + 1664 0010 00400052 .word 1375748096 + 1665 .cfi_endproc + 1666 .LFE186: + 1668 .section .text.HAL_GetFMCMemorySwappingConfig,"ax",%progbits + 1669 .align 1 + 1670 .global HAL_GetFMCMemorySwappingConfig + 1671 .syntax unified + 1672 .thumb + 1673 .thumb_func + 1674 .fpu fpv5-d16 + 1676 HAL_GetFMCMemorySwappingConfig: + 1677 .LFB187: +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** + ARM GAS /tmp/ccfvUJpJ.s page 49 + + +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Get FMC Bank mapping mode. +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval The FMC Bank mapping mode. This parameter can be +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** uint32_t HAL_GetFMCMemorySwappingConfig(void) +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1678 .loc 1 1078 1 is_stmt 1 view -0 + 1679 .cfi_startproc + 1680 @ args = 0, pretend = 0, frame = 0 + 1681 @ frame_needed = 0, uses_anonymous_args = 0 + 1682 @ link register save eliminated. +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP); + 1683 .loc 1 1079 3 view .LVU274 + 1684 .loc 1 1079 10 is_stmt 0 view .LVU275 + 1685 0000 024B ldr r3, .L162 + 1686 0002 1868 ldr r0, [r3] +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1687 .loc 1 1080 1 view .LVU276 + 1688 0004 00F04070 and r0, r0, #50331648 + 1689 0008 7047 bx lr + 1690 .L163: + 1691 000a 00BF .align 2 + 1692 .L162: + 1693 000c 00400052 .word 1375748096 + 1694 .cfi_endproc + 1695 .LFE187: + 1697 .section .text.HAL_EXTI_EdgeConfig,"ax",%progbits + 1698 .align 1 + 1699 .global HAL_EXTI_EdgeConfig + 1700 .syntax unified + 1701 .thumb + 1702 .thumb_func + 1703 .fpu fpv5-d16 + 1705 HAL_EXTI_EdgeConfig: + 1706 .LVL44: + 1707 .LFB188: +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Configure the EXTI input event line edge +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LI +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Edge: Specifies EXTI line Edge used. +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values : +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ) +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1708 .loc 1 1095 1 is_stmt 1 view -0 + 1709 .cfi_startproc + 1710 @ args = 0, pretend = 0, frame = 0 + 1711 @ frame_needed = 0, uses_anonymous_args = 0 + 1712 @ link register save eliminated. + 1713 .loc 1 1095 1 is_stmt 0 view .LVU278 + ARM GAS /tmp/ccfvUJpJ.s page 50 + + + 1714 0000 30B4 push {r4, r5} + 1715 .LCFI6: + 1716 .cfi_def_cfa_offset 8 + 1717 .cfi_offset 4, -8 + 1718 .cfi_offset 5, -4 +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + 1719 .loc 1 1097 3 is_stmt 1 view .LVU279 +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge)); + 1720 .loc 1 1098 3 view .LVU280 +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Clear Rising Falling edge configuration */ +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint3 + 1721 .loc 1 1101 3 view .LVU281 + 1722 0002 4309 lsrs r3, r0, #5 + 1723 0004 20F01F0C bic ip, r0, #31 + 1724 0008 114C ldr r4, .L168 + 1725 000a 5CF80450 ldr r5, [ip, r4] + 1726 000e 00F01F00 and r0, r0, #31 + 1727 .LVL45: + 1728 .loc 1 1101 3 is_stmt 0 view .LVU282 + 1729 0012 0122 movs r2, #1 + 1730 0014 02FA00F0 lsl r0, r2, r0 + 1731 0018 25EA0005 bic r5, r5, r0 + 1732 001c 4CF80450 str r5, [ip, r4] +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint + 1733 .loc 1 1102 3 is_stmt 1 view .LVU283 + 1734 0020 03F13073 add r3, r3, #46137344 + 1735 0024 5B01 lsls r3, r3, #5 + 1736 0026 1A68 ldr r2, [r3] + 1737 0028 22EA0002 bic r2, r2, r0 + 1738 002c 1A60 str r2, [r3] +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE) + 1739 .loc 1 1104 3 view .LVU284 + 1740 .loc 1 1104 5 is_stmt 0 view .LVU285 + 1741 002e 11F4801F tst r1, #1048576 + 1742 0032 02D0 beq .L165 +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint3 + 1743 .loc 1 1106 4 is_stmt 1 view .LVU286 + 1744 0034 1A68 ldr r2, [r3] + 1745 0036 0243 orrs r2, r2, r0 + 1746 0038 1A60 str r2, [r3] + 1747 .L165: +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE) + 1748 .loc 1 1108 3 view .LVU287 + 1749 .loc 1 1108 5 is_stmt 0 view .LVU288 + 1750 003a 11F4001F tst r1, #2097152 + 1751 003e 04D0 beq .L164 +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32 + 1752 .loc 1 1110 4 is_stmt 1 view .LVU289 + 1753 0040 5CF80430 ldr r3, [ip, r4] + 1754 0044 1843 orrs r0, r0, r3 + 1755 0046 4CF80400 str r0, [ip, r4] + ARM GAS /tmp/ccfvUJpJ.s page 51 + + + 1756 .L164: +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1757 .loc 1 1112 1 is_stmt 0 view .LVU290 + 1758 004a 30BC pop {r4, r5} + 1759 .LCFI7: + 1760 .cfi_restore 5 + 1761 .cfi_restore 4 + 1762 .cfi_def_cfa_offset 0 + 1763 004c 7047 bx lr + 1764 .L169: + 1765 004e 00BF .align 2 + 1766 .L168: + 1767 0050 04000058 .word 1476395012 + 1768 .cfi_endproc + 1769 .LFE188: + 1771 .section .text.HAL_EXTI_GenerateSWInterrupt,"ax",%progbits + 1772 .align 1 + 1773 .global HAL_EXTI_GenerateSWInterrupt + 1774 .syntax unified + 1775 .thumb + 1776 .thumb_func + 1777 .fpu fpv5-d16 + 1779 HAL_EXTI_GenerateSWInterrupt: + 1780 .LVL46: + 1781 .LFB189: +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Generates a Software interrupt on selected EXTI line. +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1782 .loc 1 1121 1 is_stmt 1 view -0 + 1783 .cfi_startproc + 1784 @ args = 0, pretend = 0, frame = 0 + 1785 @ frame_needed = 0, uses_anonymous_args = 0 + 1786 @ link register save eliminated. +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + 1787 .loc 1 1123 3 view .LVU292 +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32 + 1788 .loc 1 1125 3 view .LVU293 + 1789 0000 20F01F0C bic ip, r0, #31 + 1790 0004 0549 ldr r1, .L171 + 1791 0006 5CF80130 ldr r3, [ip, r1] + 1792 000a 00F01F00 and r0, r0, #31 + 1793 .LVL47: + 1794 .loc 1 1125 3 is_stmt 0 view .LVU294 + 1795 000e 0122 movs r2, #1 + 1796 0010 02FA00F0 lsl r0, r2, r0 + 1797 0014 1843 orrs r0, r0, r3 + 1798 0016 4CF80100 str r0, [ip, r1] +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + ARM GAS /tmp/ccfvUJpJ.s page 52 + + + 1799 .loc 1 1126 1 view .LVU295 + 1800 001a 7047 bx lr + 1801 .L172: + 1802 .align 2 + 1803 .L171: + 1804 001c 08000058 .word 1476395016 + 1805 .cfi_endproc + 1806 .LFE189: + 1808 .section .text.HAL_EXTI_D1_ClearFlag,"ax",%progbits + 1809 .align 1 + 1810 .global HAL_EXTI_D1_ClearFlag + 1811 .syntax unified + 1812 .thumb + 1813 .thumb_func + 1814 .fpu fpv5-d16 + 1816 HAL_EXTI_D1_ClearFlag: + 1817 .LVL48: + 1818 .LFB190: +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Clears the EXTI's line pending flags for Domain D1 +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line) +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1819 .loc 1 1136 1 is_stmt 1 view -0 + 1820 .cfi_startproc + 1821 @ args = 0, pretend = 0, frame = 0 + 1822 @ frame_needed = 0, uses_anonymous_args = 0 + 1823 @ link register save eliminated. +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + 1824 .loc 1 1138 2 view .LVU297 +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint3 + 1825 .loc 1 1139 2 view .LVU298 + 1826 0000 00F01F02 and r2, r0, #31 + 1827 0004 4009 lsrs r0, r0, #5 + 1828 .LVL49: + 1829 .loc 1 1139 2 is_stmt 0 view .LVU299 + 1830 0006 0001 lsls r0, r0, #4 + 1831 0008 0123 movs r3, #1 + 1832 000a 9340 lsls r3, r3, r2 + 1833 000c 014A ldr r2, .L174 + 1834 000e 8350 str r3, [r0, r2] +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1835 .loc 1 1141 1 view .LVU300 + 1836 0010 7047 bx lr + 1837 .L175: + 1838 0012 00BF .align 2 + 1839 .L174: + 1840 0014 88000058 .word 1476395144 + 1841 .cfi_endproc + 1842 .LFE190: + ARM GAS /tmp/ccfvUJpJ.s page 53 + + + 1844 .section .text.HAL_EXTI_D1_EventInputConfig,"ax",%progbits + 1845 .align 1 + 1846 .global HAL_EXTI_D1_EventInputConfig + 1847 .syntax unified + 1848 .thumb + 1849 .thumb_func + 1850 .fpu fpv5-d16 + 1852 HAL_EXTI_D1_EventInputConfig: + 1853 .LVL50: + 1854 .LFB191: +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Clears the EXTI's line pending flags for Domain D2 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line) +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameters */ +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_D2_LINE(EXTI_Line)); +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint3 +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*DUAL_CORE*/ +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Configure the EXTI input event line for Domain D1 +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one or a combination of the following values : +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg EXTI_MODE_IT : Interrupt Mode selected +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg EXTI_MODE_EVT : Event Mode selected +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1855 .loc 1 1171 1 is_stmt 1 view -0 + 1856 .cfi_startproc + 1857 @ args = 0, pretend = 0, frame = 0 + 1858 @ frame_needed = 0, uses_anonymous_args = 0 + 1859 .loc 1 1171 1 is_stmt 0 view .LVU302 + 1860 0000 10B5 push {r4, lr} + 1861 .LCFI8: + 1862 .cfi_def_cfa_offset 8 + 1863 .cfi_offset 4, -8 + 1864 .cfi_offset 14, -4 +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + 1865 .loc 1 1173 3 is_stmt 1 view .LVU303 +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + 1866 .loc 1 1174 3 view .LVU304 +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + ARM GAS /tmp/ccfvUJpJ.s page 54 + + + 1867 .loc 1 1176 3 view .LVU305 + 1868 .loc 1 1176 5 is_stmt 0 view .LVU306 + 1869 0002 11F4803F tst r1, #65536 + 1870 0006 0ED0 beq .L177 +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( EXTI_LineCmd == 0UL) + 1871 .loc 1 1178 6 is_stmt 1 view .LVU307 + 1872 .loc 1 1178 8 is_stmt 0 view .LVU308 + 1873 0008 EAB9 cbnz r2, .L178 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Clear EXTI line configuration */ +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)) + 1874 .loc 1 1181 9 is_stmt 1 view .LVU309 + 1875 000a 1C4B ldr r3, .L182 + 1876 000c 03EB5013 add r3, r3, r0, lsr #5 + 1877 0010 1B01 lsls r3, r3, #4 + 1878 0012 1C68 ldr r4, [r3] + 1879 0014 00F01F0E and lr, r0, #31 + 1880 0018 4FF0010C mov ip, #1 + 1881 001c 0CFA0EFC lsl ip, ip, lr + 1882 0020 24EA0C04 bic r4, r4, ip + 1883 0024 1C60 str r4, [r3] + 1884 .L177: +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + 1885 .loc 1 1189 3 view .LVU310 + 1886 .loc 1 1189 5 is_stmt 0 view .LVU311 + 1887 0026 11F4003F tst r1, #131072 + 1888 002a 0BD0 beq .L176 +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( EXTI_LineCmd == 0UL) + 1889 .loc 1 1191 5 is_stmt 1 view .LVU312 + 1890 .loc 1 1191 7 is_stmt 0 view .LVU313 + 1891 002c D2B9 cbnz r2, .L180 +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Clear EXTI line configuration */ +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)) + 1892 .loc 1 1194 7 is_stmt 1 view .LVU314 + 1893 002e 4309 lsrs r3, r0, #5 + 1894 0030 1B01 lsls r3, r3, #4 + 1895 0032 1349 ldr r1, .L182+4 + 1896 .LVL51: + 1897 .loc 1 1194 7 is_stmt 0 view .LVU315 + 1898 0034 5A58 ldr r2, [r3, r1] + 1899 .LVL52: + 1900 .loc 1 1194 7 view .LVU316 + 1901 0036 00F01F04 and r4, r0, #31 + 1902 003a 0120 movs r0, #1 + 1903 .LVL53: + 1904 .loc 1 1194 7 view .LVU317 + 1905 003c A040 lsls r0, r0, r4 + ARM GAS /tmp/ccfvUJpJ.s page 55 + + + 1906 003e 22EA0000 bic r0, r2, r0 + 1907 0042 5850 str r0, [r3, r1] + 1908 .L176: +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1909 .loc 1 1201 1 view .LVU318 + 1910 0044 10BD pop {r4, pc} + 1911 .LVL54: + 1912 .L178: +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1913 .loc 1 1185 9 is_stmt 1 view .LVU319 + 1914 0046 0D4B ldr r3, .L182 + 1915 0048 03EB5013 add r3, r3, r0, lsr #5 + 1916 004c 1B01 lsls r3, r3, #4 + 1917 004e 1C68 ldr r4, [r3] + 1918 0050 00F01F0E and lr, r0, #31 + 1919 0054 4FF0010C mov ip, #1 + 1920 0058 0CFA0EFC lsl ip, ip, lr + 1921 005c 44EA0C04 orr r4, r4, ip + 1922 0060 1C60 str r4, [r3] + 1923 0062 E0E7 b .L177 + 1924 .L180: +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1925 .loc 1 1198 7 view .LVU320 + 1926 0064 4309 lsrs r3, r0, #5 + 1927 0066 1B01 lsls r3, r3, #4 + 1928 0068 054C ldr r4, .L182+4 + 1929 006a 1A59 ldr r2, [r3, r4] + 1930 .LVL55: +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1931 .loc 1 1198 7 is_stmt 0 view .LVU321 + 1932 006c 00F01F00 and r0, r0, #31 + 1933 .LVL56: +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1934 .loc 1 1198 7 view .LVU322 + 1935 0070 0121 movs r1, #1 + 1936 .LVL57: +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 1937 .loc 1 1198 7 view .LVU323 + 1938 0072 01FA00F0 lsl r0, r1, r0 + 1939 0076 1043 orrs r0, r0, r2 + 1940 0078 1851 str r0, [r3, r4] + 1941 .loc 1 1201 1 view .LVU324 + 1942 007a E3E7 b .L176 + 1943 .L183: + 1944 .align 2 + 1945 .L182: + 1946 007c 08008005 .word 92274696 + 1947 0080 84000058 .word 1476395140 + 1948 .cfi_endproc + 1949 .LFE191: + 1951 .section .text.HAL_EXTI_D3_EventInputConfig,"ax",%progbits + ARM GAS /tmp/ccfvUJpJ.s page 56 + + + 1952 .align 1 + 1953 .global HAL_EXTI_D3_EventInputConfig + 1954 .syntax unified + 1955 .thumb + 1956 .thumb_func + 1957 .fpu fpv5-d16 + 1959 HAL_EXTI_D3_EventInputConfig: + 1960 .LVL58: + 1961 .LFB192: +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #if defined(DUAL_CORE) +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Configure the EXTI input event line for Domain D2 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one or a combination of the following values : +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg EXTI_MODE_IT : Interrupt Mode selected +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg EXTI_MODE_EVT : Event Mode selected +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_D2_LINE(EXTI_Line)); +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( EXTI_LineCmd == 0UL) +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Clear EXTI line configuration */ +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(u +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (ui +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( EXTI_LineCmd == 0UL) +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Clear EXTI line configuration */ +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)) +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** #endif /*DUAL_CORE*/ +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** + ARM GAS /tmp/ccfvUJpJ.s page 57 + + +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /** +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @brief Configure the EXTI input event line for Domain D3 +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53) +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event. +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * This parameter can be one of the following values : +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** * @retval None +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** */ +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSr +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + 1962 .loc 1 1265 1 is_stmt 1 view -0 + 1963 .cfi_startproc + 1964 @ args = 0, pretend = 0, frame = 0 + 1965 @ frame_needed = 0, uses_anonymous_args = 0 + 1966 .loc 1 1265 1 is_stmt 0 view .LVU326 + 1967 0000 10B5 push {r4, lr} + 1968 .LCFI9: + 1969 .cfi_def_cfa_offset 8 + 1970 .cfi_offset 4, -8 + 1971 .cfi_offset 14, -4 +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** __IO uint32_t *pRegv; + 1972 .loc 1 1266 3 is_stmt 1 view .LVU327 +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Check the parameter */ +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_D3_LINE(EXTI_Line)); + 1973 .loc 1 1269 3 view .LVU328 +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc)); + 1974 .loc 1 1270 3 view .LVU329 +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if( EXTI_LineCmd == 0UL) + 1975 .loc 1 1272 3 view .LVU330 + 1976 .loc 1 1272 5 is_stmt 0 view .LVU331 + 1977 0002 11BB cbnz r1, .L185 +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** /* Clear EXTI line configuration */ +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uin + 1978 .loc 1 1275 5 is_stmt 1 view .LVU332 + 1979 0004 20F01F03 bic r3, r0, #31 + 1980 0008 194C ldr r4, .L190 + 1981 000a 1959 ldr r1, [r3, r4] + 1982 .LVL59: + 1983 .loc 1 1275 5 is_stmt 0 view .LVU333 + 1984 000c 00F01F0E and lr, r0, #31 + 1985 0010 4FF0010C mov ip, #1 + 1986 0014 0CFA0EFC lsl ip, ip, lr + 1987 0018 21EA0C01 bic r1, r1, ip + 1988 001c 1951 str r1, [r3, r4] + 1989 .L186: +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { + ARM GAS /tmp/ccfvUJpJ.s page 58 + + +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint3 +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** if(((EXTI_Line>>4)%2UL) == 0UL) + 1990 .loc 1 1282 3 is_stmt 1 view .LVU334 + 1991 .loc 1 1282 5 is_stmt 0 view .LVU335 + 1992 001e 10F0100F tst r0, #16 + 1993 0022 20D1 bne .L187 +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL)); + 1994 .loc 1 1284 5 is_stmt 1 view .LVU336 + 1995 .loc 1 1284 83 is_stmt 0 view .LVU337 + 1996 0024 20F01F03 bic r3, r0, #31 + 1997 .loc 1 1284 62 view .LVU338 + 1998 0028 1249 ldr r1, .L190+4 + 1999 002a 1944 add r1, r1, r3 + 2000 .LVL60: + 2001 .L188: +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** else +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** { +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL)); +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((E + 2002 .loc 1 1290 3 is_stmt 1 view .LVU339 + 2003 002c 0B68 ldr r3, [r1] + 2004 002e 4000 lsls r0, r0, #1 + 2005 .LVL61: + 2006 .loc 1 1290 3 is_stmt 0 view .LVU340 + 2007 0030 00F01E00 and r0, r0, #30 + 2008 0034 4FF0030C mov ip, #3 + 2009 0038 0CFA00FC lsl ip, ip, r0 + 2010 003c 23EA0C03 bic r3, r3, ip + 2011 0040 02FA00F0 lsl r0, r2, r0 + 2012 0044 1843 orrs r0, r0, r3 + 2013 0046 0860 str r0, [r1] +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2014 .loc 1 1292 1 view .LVU341 + 2015 0048 10BD pop {r4, pc} + 2016 .LVL62: + 2017 .L185: +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2018 .loc 1 1279 5 is_stmt 1 view .LVU342 + 2019 004a 20F01F03 bic r3, r0, #31 + 2020 004e 084C ldr r4, .L190 + 2021 0050 1959 ldr r1, [r3, r4] + 2022 .LVL63: +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2023 .loc 1 1279 5 is_stmt 0 view .LVU343 + 2024 0052 00F01F0E and lr, r0, #31 + 2025 0056 4FF0010C mov ip, #1 + 2026 005a 0CFA0EFC lsl ip, ip, lr + 2027 005e 41EA0C01 orr r1, r1, ip + 2028 0062 1951 str r1, [r3, r4] + 2029 0064 DBE7 b .L186 + 2030 .L187: + ARM GAS /tmp/ccfvUJpJ.s page 59 + + +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2031 .loc 1 1288 5 is_stmt 1 view .LVU344 +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2032 .loc 1 1288 83 is_stmt 0 view .LVU345 + 2033 0066 20F01F03 bic r3, r0, #31 +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2034 .loc 1 1288 62 view .LVU346 + 2035 006a 0349 ldr r1, .L190+8 + 2036 006c 1944 add r1, r1, r3 + 2037 .LVL64: +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c **** } + 2038 .loc 1 1288 62 view .LVU347 + 2039 006e DDE7 b .L188 + 2040 .L191: + 2041 .align 2 + 2042 .L190: + 2043 0070 0C000058 .word 1476395020 + 2044 0074 10000058 .word 1476395024 + 2045 0078 14000058 .word 1476395028 + 2046 .cfi_endproc + 2047 .LFE192: + 2049 .global uwTickFreq + 2050 .global uwTickPrio + 2051 .global uwTick + 2052 .section .bss.uwTick,"aw",%nobits + 2053 .align 2 + 2054 .set .LANCHOR2,. + 0 + 2057 uwTick: + 2058 0000 00000000 .space 4 + 2059 .section .data.uwTickFreq,"aw" + 2060 .set .LANCHOR0,. + 0 + 2063 uwTickFreq: + 2064 0000 01 .byte 1 + 2065 .section .data.uwTickPrio,"aw" + 2066 .align 2 + 2067 .set .LANCHOR1,. + 0 + 2070 uwTickPrio: + 2071 0000 10000000 .word 16 + 2072 .text + 2073 .Letext0: + 2074 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2075 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2076 .file 4 "Drivers/CMSIS/Include/core_cm7.h" + 2077 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + 2078 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 2079 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 2080 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 2081 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h" + 2082 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" + ARM GAS /tmp/ccfvUJpJ.s page 60 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal.c + /tmp/ccfvUJpJ.s:17 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccfvUJpJ.s:25 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccfvUJpJ.s:39 .text.HAL_MspDeInit:0000000000000000 $t + /tmp/ccfvUJpJ.s:46 .text.HAL_MspDeInit:0000000000000000 HAL_MspDeInit + /tmp/ccfvUJpJ.s:59 .text.HAL_DeInit:0000000000000000 $t + /tmp/ccfvUJpJ.s:66 .text.HAL_DeInit:0000000000000000 HAL_DeInit + /tmp/ccfvUJpJ.s:134 .text.HAL_DeInit:0000000000000068 $d + /tmp/ccfvUJpJ.s:145 .text.HAL_InitTick:0000000000000000 $t + /tmp/ccfvUJpJ.s:152 .text.HAL_InitTick:0000000000000000 HAL_InitTick + /tmp/ccfvUJpJ.s:226 .text.HAL_InitTick:0000000000000044 $d + /tmp/ccfvUJpJ.s:233 .text.HAL_Init:0000000000000000 $t + /tmp/ccfvUJpJ.s:240 .text.HAL_Init:0000000000000000 HAL_Init + /tmp/ccfvUJpJ.s:317 .text.HAL_Init:000000000000004c $d + /tmp/ccfvUJpJ.s:325 .text.HAL_IncTick:0000000000000000 $t + /tmp/ccfvUJpJ.s:332 .text.HAL_IncTick:0000000000000000 HAL_IncTick + /tmp/ccfvUJpJ.s:353 .text.HAL_IncTick:0000000000000010 $d + /tmp/ccfvUJpJ.s:359 .text.HAL_GetTick:0000000000000000 $t + /tmp/ccfvUJpJ.s:366 .text.HAL_GetTick:0000000000000000 HAL_GetTick + /tmp/ccfvUJpJ.s:382 .text.HAL_GetTick:0000000000000008 $d + /tmp/ccfvUJpJ.s:387 .text.HAL_GetTickPrio:0000000000000000 $t + /tmp/ccfvUJpJ.s:394 .text.HAL_GetTickPrio:0000000000000000 HAL_GetTickPrio + /tmp/ccfvUJpJ.s:409 .text.HAL_GetTickPrio:0000000000000008 $d + /tmp/ccfvUJpJ.s:414 .text.HAL_SetTickFreq:0000000000000000 $t + /tmp/ccfvUJpJ.s:421 .text.HAL_SetTickFreq:0000000000000000 HAL_SetTickFreq + /tmp/ccfvUJpJ.s:478 .text.HAL_SetTickFreq:0000000000000024 $d + /tmp/ccfvUJpJ.s:484 .text.HAL_GetTickFreq:0000000000000000 $t + /tmp/ccfvUJpJ.s:491 .text.HAL_GetTickFreq:0000000000000000 HAL_GetTickFreq + /tmp/ccfvUJpJ.s:506 .text.HAL_GetTickFreq:0000000000000008 $d + /tmp/ccfvUJpJ.s:511 .text.HAL_Delay:0000000000000000 $t + /tmp/ccfvUJpJ.s:518 .text.HAL_Delay:0000000000000000 HAL_Delay + /tmp/ccfvUJpJ.s:571 .text.HAL_Delay:0000000000000024 $d + /tmp/ccfvUJpJ.s:576 .text.HAL_SuspendTick:0000000000000000 $t + /tmp/ccfvUJpJ.s:583 .text.HAL_SuspendTick:0000000000000000 HAL_SuspendTick + /tmp/ccfvUJpJ.s:602 .text.HAL_ResumeTick:0000000000000000 $t + /tmp/ccfvUJpJ.s:609 .text.HAL_ResumeTick:0000000000000000 HAL_ResumeTick + /tmp/ccfvUJpJ.s:628 .text.HAL_GetHalVersion:0000000000000000 $t + /tmp/ccfvUJpJ.s:635 .text.HAL_GetHalVersion:0000000000000000 HAL_GetHalVersion + /tmp/ccfvUJpJ.s:649 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/tmp/ccfvUJpJ.s:2063 .data.uwTickFreq:0000000000000000 uwTickFreq + /tmp/ccfvUJpJ.s:2070 .data.uwTickPrio:0000000000000000 uwTickPrio + /tmp/ccfvUJpJ.s:2057 .bss.uwTick:0000000000000000 uwTick + /tmp/ccfvUJpJ.s:2053 .bss.uwTick:0000000000000000 $d + /tmp/ccfvUJpJ.s:2066 .data.uwTickPrio:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_SYSTICK_Config +HAL_NVIC_SetPriority +SystemCoreClock +HAL_NVIC_SetPriorityGrouping +HAL_RCC_GetSysClockFreq +D1CorePrescTable +SystemD2Clock diff --git a/build/stm32h7xx_hal.o b/build/stm32h7xx_hal.o new file mode 100644 index 0000000..ede7c68 Binary files /dev/null and b/build/stm32h7xx_hal.o differ diff --git a/build/stm32h7xx_hal_cortex.d b/build/stm32h7xx_hal_cortex.d new file mode 100644 index 0000000..00f16fb --- /dev/null +++ b/build/stm32h7xx_hal_cortex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_cortex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_cortex.lst b/build/stm32h7xx_hal_cortex.lst new file mode 100644 index 0000000..1c85a28 --- /dev/null +++ b/build/stm32h7xx_hal_cortex.lst @@ -0,0 +1,5700 @@ +ARM GAS /tmp/ccV0GlXv.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_cortex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits + 17 .align 1 + 18 .global HAL_NVIC_SetPriorityGrouping + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_NVIC_SetPriorityGrouping: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @file stm32h7xx_hal_cortex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief CORTEX HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * functionalities of the CORTEX: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + Peripheral Control functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @verbatim + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ##### How to use this driver ##### + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..] + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** =========================================================== + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..] + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** The Cortex-M exceptions are managed by CMSIS functions. + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** function according to the following table. + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (#) please refer to programming manual for details in how to configure priority. + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. + ARM GAS /tmp/ccV0GlXv.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+@) Lowest preemption priority + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+@) Lowest sub priority + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..] + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ======================================================== + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..] + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** Setup SysTick Timer for time base. + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** is a CMSIS function that: + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Resets the SysTick Counter register. + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Starts the SysTick Counter. + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** inside the stm32h7xx_hal_cortex.h file. + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @endverbatim + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ****************************************************************************** + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @attention + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * All rights reserved.

+ 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * License. You may obtain a copy of the License at: + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ****************************************************************************** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #include "stm32h7xx_hal.h" + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{ + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + ARM GAS /tmp/ccV0GlXv.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief CORTEX HAL module driver + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{ + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/ + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{ + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initialization and Configuration functions + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @verbatim + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ============================================================================== + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ============================================================================== + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..] + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** Systick functionalities + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @endverbatim + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{ + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Sets the priority grouping field (preemption priority and subpriority) + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * using the required unlock sequence. + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length. + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values: + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 4 bits for subpriority + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 3 bits for subpriority + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 2 bits for subpriority + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 1 bits for subpriority + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 0 bits for subpriority + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + ARM GAS /tmp/ccV0GlXv.s page 4 + + + 29 .loc 1 144 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 34 .loc 1 146 3 view .LVU1 + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); + 35 .loc 1 149 3 view .LVU2 + 36 .LBB38: + 37 .LBI38: + 38 .file 2 "Drivers/CMSIS/Include/core_cm7.h" + 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h + 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 + 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 + 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm7.h **** /* + 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm7.h **** * + 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm7.h **** * + 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm7.h **** * + 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm7.h **** * + 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm7.h **** */ + 24:Drivers/CMSIS/Include/core_cm7.h **** + 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm7.h **** #endif + 30:Drivers/CMSIS/Include/core_cm7.h **** + 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm7.h **** + 34:Drivers/CMSIS/Include/core_cm7.h **** #include + 35:Drivers/CMSIS/Include/core_cm7.h **** + 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm7.h **** #endif + 39:Drivers/CMSIS/Include/core_cm7.h **** + 40:Drivers/CMSIS/Include/core_cm7.h **** /** + 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: + ARM GAS /tmp/ccV0GlXv.s page 5 + + + 43:Drivers/CMSIS/Include/core_cm7.h **** + 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm7.h **** + 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm7.h **** + 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm7.h **** */ + 53:Drivers/CMSIS/Include/core_cm7.h **** + 54:Drivers/CMSIS/Include/core_cm7.h **** + 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm7.h **** /** + 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 + 60:Drivers/CMSIS/Include/core_cm7.h **** @{ + 61:Drivers/CMSIS/Include/core_cm7.h **** */ + 62:Drivers/CMSIS/Include/core_cm7.h **** + 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm7.h **** + 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ + 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 + 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 + 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS + 70:Drivers/CMSIS/Include/core_cm7.h **** + 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm7.h **** + 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun + 75:Drivers/CMSIS/Include/core_cm7.h **** */ + 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) + 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP + 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 80:Drivers/CMSIS/Include/core_cm7.h **** #else + 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 83:Drivers/CMSIS/Include/core_cm7.h **** #endif + 84:Drivers/CMSIS/Include/core_cm7.h **** #else + 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 86:Drivers/CMSIS/Include/core_cm7.h **** #endif + 87:Drivers/CMSIS/Include/core_cm7.h **** + 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP + 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 92:Drivers/CMSIS/Include/core_cm7.h **** #else + 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN + 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 95:Drivers/CMSIS/Include/core_cm7.h **** #endif + 96:Drivers/CMSIS/Include/core_cm7.h **** #else + 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 98:Drivers/CMSIS/Include/core_cm7.h **** #endif + 99:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 6 + + + 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) + 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 104:Drivers/CMSIS/Include/core_cm7.h **** #else + 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 107:Drivers/CMSIS/Include/core_cm7.h **** #endif + 108:Drivers/CMSIS/Include/core_cm7.h **** #else + 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 110:Drivers/CMSIS/Include/core_cm7.h **** #endif + 111:Drivers/CMSIS/Include/core_cm7.h **** + 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) + 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ + 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 116:Drivers/CMSIS/Include/core_cm7.h **** #else + 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 119:Drivers/CMSIS/Include/core_cm7.h **** #endif + 120:Drivers/CMSIS/Include/core_cm7.h **** #else + 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 122:Drivers/CMSIS/Include/core_cm7.h **** #endif + 123:Drivers/CMSIS/Include/core_cm7.h **** + 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) + 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ + 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 128:Drivers/CMSIS/Include/core_cm7.h **** #else + 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 131:Drivers/CMSIS/Include/core_cm7.h **** #endif + 132:Drivers/CMSIS/Include/core_cm7.h **** #else + 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 134:Drivers/CMSIS/Include/core_cm7.h **** #endif + 135:Drivers/CMSIS/Include/core_cm7.h **** + 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) + 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ + 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 140:Drivers/CMSIS/Include/core_cm7.h **** #else + 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 143:Drivers/CMSIS/Include/core_cm7.h **** #endif + 144:Drivers/CMSIS/Include/core_cm7.h **** #else + 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 146:Drivers/CMSIS/Include/core_cm7.h **** #endif + 147:Drivers/CMSIS/Include/core_cm7.h **** + 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) + 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) + 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 152:Drivers/CMSIS/Include/core_cm7.h **** #else + 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 155:Drivers/CMSIS/Include/core_cm7.h **** #endif + 156:Drivers/CMSIS/Include/core_cm7.h **** #else + ARM GAS /tmp/ccV0GlXv.s page 7 + + + 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 158:Drivers/CMSIS/Include/core_cm7.h **** #endif + 159:Drivers/CMSIS/Include/core_cm7.h **** + 160:Drivers/CMSIS/Include/core_cm7.h **** #endif + 161:Drivers/CMSIS/Include/core_cm7.h **** + 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 163:Drivers/CMSIS/Include/core_cm7.h **** + 164:Drivers/CMSIS/Include/core_cm7.h **** + 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 166:Drivers/CMSIS/Include/core_cm7.h **** } + 167:Drivers/CMSIS/Include/core_cm7.h **** #endif + 168:Drivers/CMSIS/Include/core_cm7.h **** + 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ + 170:Drivers/CMSIS/Include/core_cm7.h **** + 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC + 172:Drivers/CMSIS/Include/core_cm7.h **** + 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT + 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm7.h **** + 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 178:Drivers/CMSIS/Include/core_cm7.h **** #endif + 179:Drivers/CMSIS/Include/core_cm7.h **** + 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ + 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES + 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV + 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U + 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" + 185:Drivers/CMSIS/Include/core_cm7.h **** #endif + 186:Drivers/CMSIS/Include/core_cm7.h **** + 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT + 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U + 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" + 190:Drivers/CMSIS/Include/core_cm7.h **** #endif + 191:Drivers/CMSIS/Include/core_cm7.h **** + 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT + 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U + 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 195:Drivers/CMSIS/Include/core_cm7.h **** #endif + 196:Drivers/CMSIS/Include/core_cm7.h **** + 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT + 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U + 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" + 200:Drivers/CMSIS/Include/core_cm7.h **** #endif + 201:Drivers/CMSIS/Include/core_cm7.h **** + 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT + 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U + 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" + 205:Drivers/CMSIS/Include/core_cm7.h **** #endif + 206:Drivers/CMSIS/Include/core_cm7.h **** + 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT + 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U + 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" + 210:Drivers/CMSIS/Include/core_cm7.h **** #endif + 211:Drivers/CMSIS/Include/core_cm7.h **** + 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS + 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U + ARM GAS /tmp/ccV0GlXv.s page 8 + + + 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 215:Drivers/CMSIS/Include/core_cm7.h **** #endif + 216:Drivers/CMSIS/Include/core_cm7.h **** + 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig + 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U + 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 220:Drivers/CMSIS/Include/core_cm7.h **** #endif + 221:Drivers/CMSIS/Include/core_cm7.h **** #endif + 222:Drivers/CMSIS/Include/core_cm7.h **** + 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ + 224:Drivers/CMSIS/Include/core_cm7.h **** /** + 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 226:Drivers/CMSIS/Include/core_cm7.h **** + 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used + 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. + 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. + 230:Drivers/CMSIS/Include/core_cm7.h **** */ + 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 233:Drivers/CMSIS/Include/core_cm7.h **** #else + 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 235:Drivers/CMSIS/Include/core_cm7.h **** #endif + 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 238:Drivers/CMSIS/Include/core_cm7.h **** + 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ + 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 243:Drivers/CMSIS/Include/core_cm7.h **** + 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ + 245:Drivers/CMSIS/Include/core_cm7.h **** + 246:Drivers/CMSIS/Include/core_cm7.h **** + 247:Drivers/CMSIS/Include/core_cm7.h **** + 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction + 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: + 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register + 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register + 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register + 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register + 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register + 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register + 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register + 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 259:Drivers/CMSIS/Include/core_cm7.h **** /** + 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 262:Drivers/CMSIS/Include/core_cm7.h **** */ + 263:Drivers/CMSIS/Include/core_cm7.h **** + 264:Drivers/CMSIS/Include/core_cm7.h **** /** + 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers + 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. + 268:Drivers/CMSIS/Include/core_cm7.h **** @{ + 269:Drivers/CMSIS/Include/core_cm7.h **** */ + 270:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 9 + + + 271:Drivers/CMSIS/Include/core_cm7.h **** /** + 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). + 273:Drivers/CMSIS/Include/core_cm7.h **** */ + 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 275:Drivers/CMSIS/Include/core_cm7.h **** { + 276:Drivers/CMSIS/Include/core_cm7.h **** struct + 277:Drivers/CMSIS/Include/core_cm7.h **** { + 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; + 289:Drivers/CMSIS/Include/core_cm7.h **** + 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ + 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR + 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 293:Drivers/CMSIS/Include/core_cm7.h **** + 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR + 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 296:Drivers/CMSIS/Include/core_cm7.h **** + 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR + 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 299:Drivers/CMSIS/Include/core_cm7.h **** + 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR + 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 302:Drivers/CMSIS/Include/core_cm7.h **** + 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR + 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR + 305:Drivers/CMSIS/Include/core_cm7.h **** + 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR + 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR + 308:Drivers/CMSIS/Include/core_cm7.h **** + 309:Drivers/CMSIS/Include/core_cm7.h **** + 310:Drivers/CMSIS/Include/core_cm7.h **** /** + 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 312:Drivers/CMSIS/Include/core_cm7.h **** */ + 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 314:Drivers/CMSIS/Include/core_cm7.h **** { + 315:Drivers/CMSIS/Include/core_cm7.h **** struct + 316:Drivers/CMSIS/Include/core_cm7.h **** { + 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; + 322:Drivers/CMSIS/Include/core_cm7.h **** + 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ + 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 326:Drivers/CMSIS/Include/core_cm7.h **** + 327:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 10 + + + 328:Drivers/CMSIS/Include/core_cm7.h **** /** + 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 330:Drivers/CMSIS/Include/core_cm7.h **** */ + 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 332:Drivers/CMSIS/Include/core_cm7.h **** { + 333:Drivers/CMSIS/Include/core_cm7.h **** struct + 334:Drivers/CMSIS/Include/core_cm7.h **** { + 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ + 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; + 350:Drivers/CMSIS/Include/core_cm7.h **** + 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ + 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR + 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 354:Drivers/CMSIS/Include/core_cm7.h **** + 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 357:Drivers/CMSIS/Include/core_cm7.h **** + 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR + 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 360:Drivers/CMSIS/Include/core_cm7.h **** + 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR + 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 363:Drivers/CMSIS/Include/core_cm7.h **** + 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR + 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR + 366:Drivers/CMSIS/Include/core_cm7.h **** + 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR + 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR + 369:Drivers/CMSIS/Include/core_cm7.h **** + 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR + 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 372:Drivers/CMSIS/Include/core_cm7.h **** + 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR + 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR + 375:Drivers/CMSIS/Include/core_cm7.h **** + 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR + 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR + 378:Drivers/CMSIS/Include/core_cm7.h **** + 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 381:Drivers/CMSIS/Include/core_cm7.h **** + 382:Drivers/CMSIS/Include/core_cm7.h **** + 383:Drivers/CMSIS/Include/core_cm7.h **** /** + 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). + ARM GAS /tmp/ccV0GlXv.s page 11 + + + 385:Drivers/CMSIS/Include/core_cm7.h **** */ + 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 387:Drivers/CMSIS/Include/core_cm7.h **** { + 388:Drivers/CMSIS/Include/core_cm7.h **** struct + 389:Drivers/CMSIS/Include/core_cm7.h **** { + 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; + 397:Drivers/CMSIS/Include/core_cm7.h **** + 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ + 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT + 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT + 401:Drivers/CMSIS/Include/core_cm7.h **** + 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 404:Drivers/CMSIS/Include/core_cm7.h **** + 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 407:Drivers/CMSIS/Include/core_cm7.h **** + 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ + 409:Drivers/CMSIS/Include/core_cm7.h **** + 410:Drivers/CMSIS/Include/core_cm7.h **** + 411:Drivers/CMSIS/Include/core_cm7.h **** /** + 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers + 415:Drivers/CMSIS/Include/core_cm7.h **** @{ + 416:Drivers/CMSIS/Include/core_cm7.h **** */ + 417:Drivers/CMSIS/Include/core_cm7.h **** + 418:Drivers/CMSIS/Include/core_cm7.h **** /** + 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 420:Drivers/CMSIS/Include/core_cm7.h **** */ + 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 422:Drivers/CMSIS/Include/core_cm7.h **** { + 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; + 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; + 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; + 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; + 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; + 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi + 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; + 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis + 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; + 437:Drivers/CMSIS/Include/core_cm7.h **** + 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ + 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I + 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I + 441:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 12 + + + 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ + 443:Drivers/CMSIS/Include/core_cm7.h **** + 444:Drivers/CMSIS/Include/core_cm7.h **** + 445:Drivers/CMSIS/Include/core_cm7.h **** /** + 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers + 449:Drivers/CMSIS/Include/core_cm7.h **** @{ + 450:Drivers/CMSIS/Include/core_cm7.h **** */ + 451:Drivers/CMSIS/Include/core_cm7.h **** + 452:Drivers/CMSIS/Include/core_cm7.h **** /** + 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). + 454:Drivers/CMSIS/Include/core_cm7.h **** */ + 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 456:Drivers/CMSIS/Include/core_cm7.h **** { + 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe + 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist + 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register + 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register + 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis + 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis + 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; + 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg + 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; + 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 + 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 + 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 + 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; + 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; + 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU + 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC + 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by + 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by + ARM GAS /tmp/ccV0GlXv.s page 13 + + + 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; + 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo + 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont + 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; + 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis + 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; + 508:Drivers/CMSIS/Include/core_cm7.h **** + 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ + 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 512:Drivers/CMSIS/Include/core_cm7.h **** + 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 515:Drivers/CMSIS/Include/core_cm7.h **** + 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 518:Drivers/CMSIS/Include/core_cm7.h **** + 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 521:Drivers/CMSIS/Include/core_cm7.h **** + 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 524:Drivers/CMSIS/Include/core_cm7.h **** + 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ + 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 528:Drivers/CMSIS/Include/core_cm7.h **** + 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 531:Drivers/CMSIS/Include/core_cm7.h **** + 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 534:Drivers/CMSIS/Include/core_cm7.h **** + 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 537:Drivers/CMSIS/Include/core_cm7.h **** + 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 540:Drivers/CMSIS/Include/core_cm7.h **** + 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 543:Drivers/CMSIS/Include/core_cm7.h **** + 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 546:Drivers/CMSIS/Include/core_cm7.h **** + 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 549:Drivers/CMSIS/Include/core_cm7.h **** + 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB + 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB + 552:Drivers/CMSIS/Include/core_cm7.h **** + 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 555:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 14 + + + 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ + 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB + 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 559:Drivers/CMSIS/Include/core_cm7.h **** + 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 563:Drivers/CMSIS/Include/core_cm7.h **** + 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 566:Drivers/CMSIS/Include/core_cm7.h **** + 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 569:Drivers/CMSIS/Include/core_cm7.h **** + 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB + 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB + 572:Drivers/CMSIS/Include/core_cm7.h **** + 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 575:Drivers/CMSIS/Include/core_cm7.h **** + 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 578:Drivers/CMSIS/Include/core_cm7.h **** + 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB + 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB + 581:Drivers/CMSIS/Include/core_cm7.h **** + 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ + 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 585:Drivers/CMSIS/Include/core_cm7.h **** + 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 588:Drivers/CMSIS/Include/core_cm7.h **** + 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 591:Drivers/CMSIS/Include/core_cm7.h **** + 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ + 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB + 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB + 595:Drivers/CMSIS/Include/core_cm7.h **** + 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB + 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB + 598:Drivers/CMSIS/Include/core_cm7.h **** + 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB + 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB + 601:Drivers/CMSIS/Include/core_cm7.h **** + 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 604:Drivers/CMSIS/Include/core_cm7.h **** + 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB + 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB + 607:Drivers/CMSIS/Include/core_cm7.h **** + 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB + 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB + 610:Drivers/CMSIS/Include/core_cm7.h **** + 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + ARM GAS /tmp/ccV0GlXv.s page 15 + + + 613:Drivers/CMSIS/Include/core_cm7.h **** + 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB + 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB + 616:Drivers/CMSIS/Include/core_cm7.h **** + 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB + 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB + 619:Drivers/CMSIS/Include/core_cm7.h **** + 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ + 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB + 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB + 623:Drivers/CMSIS/Include/core_cm7.h **** + 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB + 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB + 626:Drivers/CMSIS/Include/core_cm7.h **** + 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB + 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB + 629:Drivers/CMSIS/Include/core_cm7.h **** + 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 632:Drivers/CMSIS/Include/core_cm7.h **** + 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB + 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB + 635:Drivers/CMSIS/Include/core_cm7.h **** + 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB + 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB + 638:Drivers/CMSIS/Include/core_cm7.h **** + 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB + 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB + 641:Drivers/CMSIS/Include/core_cm7.h **** + 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB + 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB + 644:Drivers/CMSIS/Include/core_cm7.h **** + 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB + 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB + 647:Drivers/CMSIS/Include/core_cm7.h **** + 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB + 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB + 650:Drivers/CMSIS/Include/core_cm7.h **** + 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB + 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB + 653:Drivers/CMSIS/Include/core_cm7.h **** + 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB + 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB + 656:Drivers/CMSIS/Include/core_cm7.h **** + 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB + 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB + 659:Drivers/CMSIS/Include/core_cm7.h **** + 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB + 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB + 662:Drivers/CMSIS/Include/core_cm7.h **** + 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ + 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB + 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB + 666:Drivers/CMSIS/Include/core_cm7.h **** + 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB + 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB + 669:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 16 + + + 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB + 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB + 672:Drivers/CMSIS/Include/core_cm7.h **** + 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ + 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB + 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB + 676:Drivers/CMSIS/Include/core_cm7.h **** + 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB + 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB + 679:Drivers/CMSIS/Include/core_cm7.h **** + 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB + 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB + 682:Drivers/CMSIS/Include/core_cm7.h **** + 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB + 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB + 685:Drivers/CMSIS/Include/core_cm7.h **** + 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB + 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB + 688:Drivers/CMSIS/Include/core_cm7.h **** + 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB + 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB + 691:Drivers/CMSIS/Include/core_cm7.h **** + 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ + 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB + 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB + 695:Drivers/CMSIS/Include/core_cm7.h **** + 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB + 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB + 698:Drivers/CMSIS/Include/core_cm7.h **** + 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB + 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB + 701:Drivers/CMSIS/Include/core_cm7.h **** + 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB + 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB + 704:Drivers/CMSIS/Include/core_cm7.h **** + 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB + 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB + 707:Drivers/CMSIS/Include/core_cm7.h **** + 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB + 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB + 710:Drivers/CMSIS/Include/core_cm7.h **** + 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB + 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB + 713:Drivers/CMSIS/Include/core_cm7.h **** + 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ + 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB + 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB + 717:Drivers/CMSIS/Include/core_cm7.h **** + 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB + 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB + 720:Drivers/CMSIS/Include/core_cm7.h **** + 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB + 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB + 723:Drivers/CMSIS/Include/core_cm7.h **** + 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB + 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB + 726:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 17 + + + 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB + 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB + 729:Drivers/CMSIS/Include/core_cm7.h **** + 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB + 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB + 732:Drivers/CMSIS/Include/core_cm7.h **** + 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ + 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB + 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB + 736:Drivers/CMSIS/Include/core_cm7.h **** + 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB + 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB + 739:Drivers/CMSIS/Include/core_cm7.h **** + 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB + 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB + 742:Drivers/CMSIS/Include/core_cm7.h **** + 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ + 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB + 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB + 746:Drivers/CMSIS/Include/core_cm7.h **** + 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB + 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB + 749:Drivers/CMSIS/Include/core_cm7.h **** + 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB + 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB + 752:Drivers/CMSIS/Include/core_cm7.h **** + 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB + 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB + 755:Drivers/CMSIS/Include/core_cm7.h **** + 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB + 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB + 758:Drivers/CMSIS/Include/core_cm7.h **** + 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ + 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB + 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB + 762:Drivers/CMSIS/Include/core_cm7.h **** + 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB + 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB + 765:Drivers/CMSIS/Include/core_cm7.h **** + 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ + 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB + 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB + 769:Drivers/CMSIS/Include/core_cm7.h **** + 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB + 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB + 772:Drivers/CMSIS/Include/core_cm7.h **** + 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB + 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB + 775:Drivers/CMSIS/Include/core_cm7.h **** + 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB + 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB + 778:Drivers/CMSIS/Include/core_cm7.h **** + 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB + 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB + 781:Drivers/CMSIS/Include/core_cm7.h **** + 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ + 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB + ARM GAS /tmp/ccV0GlXv.s page 18 + + + 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB + 785:Drivers/CMSIS/Include/core_cm7.h **** + 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB + 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB + 788:Drivers/CMSIS/Include/core_cm7.h **** + 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB + 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB + 791:Drivers/CMSIS/Include/core_cm7.h **** + 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB + 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB + 794:Drivers/CMSIS/Include/core_cm7.h **** + 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB + 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB + 797:Drivers/CMSIS/Include/core_cm7.h **** + 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB + 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB + 800:Drivers/CMSIS/Include/core_cm7.h **** + 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB + 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB + 803:Drivers/CMSIS/Include/core_cm7.h **** + 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ + 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB + 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB + 807:Drivers/CMSIS/Include/core_cm7.h **** + 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB + 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB + 810:Drivers/CMSIS/Include/core_cm7.h **** + 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ + 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB + 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB + 814:Drivers/CMSIS/Include/core_cm7.h **** + 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ + 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB + 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB + 818:Drivers/CMSIS/Include/core_cm7.h **** + 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB + 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB + 821:Drivers/CMSIS/Include/core_cm7.h **** + 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ + 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB + 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB + 825:Drivers/CMSIS/Include/core_cm7.h **** + 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB + 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB + 828:Drivers/CMSIS/Include/core_cm7.h **** + 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ + 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB + 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB + 832:Drivers/CMSIS/Include/core_cm7.h **** + 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB + 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB + 835:Drivers/CMSIS/Include/core_cm7.h **** + 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ + 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB + 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB + 839:Drivers/CMSIS/Include/core_cm7.h **** + 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB + ARM GAS /tmp/ccV0GlXv.s page 19 + + + 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB + 842:Drivers/CMSIS/Include/core_cm7.h **** + 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB + 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB + 845:Drivers/CMSIS/Include/core_cm7.h **** + 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB + 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB + 848:Drivers/CMSIS/Include/core_cm7.h **** + 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ + 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB + 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB + 852:Drivers/CMSIS/Include/core_cm7.h **** + 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB + 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB + 855:Drivers/CMSIS/Include/core_cm7.h **** + 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB + 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB + 858:Drivers/CMSIS/Include/core_cm7.h **** + 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB + 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB + 861:Drivers/CMSIS/Include/core_cm7.h **** + 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ + 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB + 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB + 865:Drivers/CMSIS/Include/core_cm7.h **** + 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB + 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB + 868:Drivers/CMSIS/Include/core_cm7.h **** + 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ + 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB + 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB + 872:Drivers/CMSIS/Include/core_cm7.h **** + 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB + 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB + 875:Drivers/CMSIS/Include/core_cm7.h **** + 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB + 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB + 878:Drivers/CMSIS/Include/core_cm7.h **** + 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ + 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB + 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB + 882:Drivers/CMSIS/Include/core_cm7.h **** + 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB + 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB + 885:Drivers/CMSIS/Include/core_cm7.h **** + 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB + 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB + 888:Drivers/CMSIS/Include/core_cm7.h **** + 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ + 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB + 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB + 892:Drivers/CMSIS/Include/core_cm7.h **** + 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB + 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB + 895:Drivers/CMSIS/Include/core_cm7.h **** + 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB + 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB + ARM GAS /tmp/ccV0GlXv.s page 20 + + + 898:Drivers/CMSIS/Include/core_cm7.h **** + 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB + 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB + 901:Drivers/CMSIS/Include/core_cm7.h **** + 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB + 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB + 904:Drivers/CMSIS/Include/core_cm7.h **** + 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB + 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB + 907:Drivers/CMSIS/Include/core_cm7.h **** + 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ + 909:Drivers/CMSIS/Include/core_cm7.h **** + 910:Drivers/CMSIS/Include/core_cm7.h **** + 911:Drivers/CMSIS/Include/core_cm7.h **** /** + 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB + 915:Drivers/CMSIS/Include/core_cm7.h **** @{ + 916:Drivers/CMSIS/Include/core_cm7.h **** */ + 917:Drivers/CMSIS/Include/core_cm7.h **** + 918:Drivers/CMSIS/Include/core_cm7.h **** /** + 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. + 920:Drivers/CMSIS/Include/core_cm7.h **** */ + 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 922:Drivers/CMSIS/Include/core_cm7.h **** { + 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist + 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; + 927:Drivers/CMSIS/Include/core_cm7.h **** + 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ + 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I + 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I + 931:Drivers/CMSIS/Include/core_cm7.h **** + 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ + 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: + 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: + 935:Drivers/CMSIS/Include/core_cm7.h **** + 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: + 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: + 938:Drivers/CMSIS/Include/core_cm7.h **** + 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: + 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: + 941:Drivers/CMSIS/Include/core_cm7.h **** + 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: + 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: + 944:Drivers/CMSIS/Include/core_cm7.h **** + 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: + 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: + 947:Drivers/CMSIS/Include/core_cm7.h **** + 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ + 949:Drivers/CMSIS/Include/core_cm7.h **** + 950:Drivers/CMSIS/Include/core_cm7.h **** + 951:Drivers/CMSIS/Include/core_cm7.h **** /** + 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. + ARM GAS /tmp/ccV0GlXv.s page 21 + + + 955:Drivers/CMSIS/Include/core_cm7.h **** @{ + 956:Drivers/CMSIS/Include/core_cm7.h **** */ + 957:Drivers/CMSIS/Include/core_cm7.h **** + 958:Drivers/CMSIS/Include/core_cm7.h **** /** + 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). + 960:Drivers/CMSIS/Include/core_cm7.h **** */ + 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 962:Drivers/CMSIS/Include/core_cm7.h **** { + 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; + 968:Drivers/CMSIS/Include/core_cm7.h **** + 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ + 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 972:Drivers/CMSIS/Include/core_cm7.h **** + 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 975:Drivers/CMSIS/Include/core_cm7.h **** + 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 978:Drivers/CMSIS/Include/core_cm7.h **** + 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 981:Drivers/CMSIS/Include/core_cm7.h **** + 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ + 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 985:Drivers/CMSIS/Include/core_cm7.h **** + 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ + 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 989:Drivers/CMSIS/Include/core_cm7.h **** + 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ + 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 993:Drivers/CMSIS/Include/core_cm7.h **** + 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 996:Drivers/CMSIS/Include/core_cm7.h **** + 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 999:Drivers/CMSIS/Include/core_cm7.h **** +1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ +1001:Drivers/CMSIS/Include/core_cm7.h **** +1002:Drivers/CMSIS/Include/core_cm7.h **** +1003:Drivers/CMSIS/Include/core_cm7.h **** /** +1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) +1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) +1007:Drivers/CMSIS/Include/core_cm7.h **** @{ +1008:Drivers/CMSIS/Include/core_cm7.h **** */ +1009:Drivers/CMSIS/Include/core_cm7.h **** +1010:Drivers/CMSIS/Include/core_cm7.h **** /** +1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + ARM GAS /tmp/ccV0GlXv.s page 22 + + +1012:Drivers/CMSIS/Include/core_cm7.h **** */ +1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1014:Drivers/CMSIS/Include/core_cm7.h **** { +1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union +1016:Drivers/CMSIS/Include/core_cm7.h **** { +1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ +1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ +1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ +1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ +1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; +1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ +1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; +1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ +1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; +1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; +1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * +1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ +1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg +1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; +1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ +1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ +1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; +1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re +1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re +1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re +1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re +1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re +1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re +1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re +1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re +1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re +1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re +1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re +1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re +1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; +1048:Drivers/CMSIS/Include/core_cm7.h **** +1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ +1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM +1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM +1052:Drivers/CMSIS/Include/core_cm7.h **** +1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ +1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM +1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM +1056:Drivers/CMSIS/Include/core_cm7.h **** +1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM +1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM +1059:Drivers/CMSIS/Include/core_cm7.h **** +1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM +1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM +1062:Drivers/CMSIS/Include/core_cm7.h **** +1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM +1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM +1065:Drivers/CMSIS/Include/core_cm7.h **** +1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM +1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM +1068:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 23 + + +1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM +1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM +1071:Drivers/CMSIS/Include/core_cm7.h **** +1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM +1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM +1074:Drivers/CMSIS/Include/core_cm7.h **** +1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM +1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM +1077:Drivers/CMSIS/Include/core_cm7.h **** +1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM +1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM +1080:Drivers/CMSIS/Include/core_cm7.h **** +1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ +1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM +1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM +1084:Drivers/CMSIS/Include/core_cm7.h **** +1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ +1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM +1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM +1088:Drivers/CMSIS/Include/core_cm7.h **** +1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ +1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM +1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM +1092:Drivers/CMSIS/Include/core_cm7.h **** +1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ +1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM +1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM +1096:Drivers/CMSIS/Include/core_cm7.h **** +1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM +1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM +1099:Drivers/CMSIS/Include/core_cm7.h **** +1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM +1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM +1102:Drivers/CMSIS/Include/core_cm7.h **** +1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ +1104:Drivers/CMSIS/Include/core_cm7.h **** +1105:Drivers/CMSIS/Include/core_cm7.h **** +1106:Drivers/CMSIS/Include/core_cm7.h **** /** +1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) +1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) +1110:Drivers/CMSIS/Include/core_cm7.h **** @{ +1111:Drivers/CMSIS/Include/core_cm7.h **** */ +1112:Drivers/CMSIS/Include/core_cm7.h **** +1113:Drivers/CMSIS/Include/core_cm7.h **** /** +1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). +1115:Drivers/CMSIS/Include/core_cm7.h **** */ +1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1117:Drivers/CMSIS/Include/core_cm7.h **** { +1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ +1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ +1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe +1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ +1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ +1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe +1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register + ARM GAS /tmp/ccV0GlXv.s page 24 + + +1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ +1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ +1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ +1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ +1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ +1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ +1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; +1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ +1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ +1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ +1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; +1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ +1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ +1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; +1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ +1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; +1145:Drivers/CMSIS/Include/core_cm7.h **** +1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ +1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR +1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR +1149:Drivers/CMSIS/Include/core_cm7.h **** +1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR +1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR +1152:Drivers/CMSIS/Include/core_cm7.h **** +1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR +1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR +1155:Drivers/CMSIS/Include/core_cm7.h **** +1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR +1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR +1158:Drivers/CMSIS/Include/core_cm7.h **** +1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR +1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR +1161:Drivers/CMSIS/Include/core_cm7.h **** +1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR +1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR +1164:Drivers/CMSIS/Include/core_cm7.h **** +1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR +1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR +1167:Drivers/CMSIS/Include/core_cm7.h **** +1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR +1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR +1170:Drivers/CMSIS/Include/core_cm7.h **** +1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR +1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR +1173:Drivers/CMSIS/Include/core_cm7.h **** +1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR +1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR +1176:Drivers/CMSIS/Include/core_cm7.h **** +1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR +1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR +1179:Drivers/CMSIS/Include/core_cm7.h **** +1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR +1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR +1182:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 25 + + +1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR +1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR +1185:Drivers/CMSIS/Include/core_cm7.h **** +1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR +1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR +1188:Drivers/CMSIS/Include/core_cm7.h **** +1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR +1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR +1191:Drivers/CMSIS/Include/core_cm7.h **** +1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR +1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR +1194:Drivers/CMSIS/Include/core_cm7.h **** +1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR +1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR +1197:Drivers/CMSIS/Include/core_cm7.h **** +1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR +1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR +1200:Drivers/CMSIS/Include/core_cm7.h **** +1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ +1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI +1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI +1204:Drivers/CMSIS/Include/core_cm7.h **** +1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ +1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC +1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC +1208:Drivers/CMSIS/Include/core_cm7.h **** +1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ +1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE +1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE +1212:Drivers/CMSIS/Include/core_cm7.h **** +1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ +1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU +1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU +1216:Drivers/CMSIS/Include/core_cm7.h **** +1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ +1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL +1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL +1220:Drivers/CMSIS/Include/core_cm7.h **** +1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ +1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS +1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS +1224:Drivers/CMSIS/Include/core_cm7.h **** +1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ +1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN +1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN +1228:Drivers/CMSIS/Include/core_cm7.h **** +1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN +1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN +1231:Drivers/CMSIS/Include/core_cm7.h **** +1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN +1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN +1234:Drivers/CMSIS/Include/core_cm7.h **** +1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN +1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN +1237:Drivers/CMSIS/Include/core_cm7.h **** +1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN +1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN + ARM GAS /tmp/ccV0GlXv.s page 26 + + +1240:Drivers/CMSIS/Include/core_cm7.h **** +1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN +1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN +1243:Drivers/CMSIS/Include/core_cm7.h **** +1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN +1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN +1246:Drivers/CMSIS/Include/core_cm7.h **** +1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN +1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN +1249:Drivers/CMSIS/Include/core_cm7.h **** +1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN +1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN +1252:Drivers/CMSIS/Include/core_cm7.h **** +1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ +1254:Drivers/CMSIS/Include/core_cm7.h **** +1255:Drivers/CMSIS/Include/core_cm7.h **** +1256:Drivers/CMSIS/Include/core_cm7.h **** /** +1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) +1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) +1260:Drivers/CMSIS/Include/core_cm7.h **** @{ +1261:Drivers/CMSIS/Include/core_cm7.h **** */ +1262:Drivers/CMSIS/Include/core_cm7.h **** +1263:Drivers/CMSIS/Include/core_cm7.h **** /** +1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). +1265:Drivers/CMSIS/Include/core_cm7.h **** */ +1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1267:Drivers/CMSIS/Include/core_cm7.h **** { +1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg +1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis +1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; +1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg +1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; +1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * +1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; +1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis +1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi +1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte +1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; +1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ +1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ +1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ +1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; +1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ +1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ +1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ +1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; +1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ +1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ +1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; +1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ +1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; +1293:Drivers/CMSIS/Include/core_cm7.h **** +1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ +1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP +1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP + ARM GAS /tmp/ccV0GlXv.s page 27 + + +1297:Drivers/CMSIS/Include/core_cm7.h **** +1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ +1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP +1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP +1301:Drivers/CMSIS/Include/core_cm7.h **** +1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ +1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS +1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS +1305:Drivers/CMSIS/Include/core_cm7.h **** +1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS +1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS +1308:Drivers/CMSIS/Include/core_cm7.h **** +1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS +1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS +1311:Drivers/CMSIS/Include/core_cm7.h **** +1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS +1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS +1314:Drivers/CMSIS/Include/core_cm7.h **** +1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ +1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC +1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC +1318:Drivers/CMSIS/Include/core_cm7.h **** +1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC +1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC +1321:Drivers/CMSIS/Include/core_cm7.h **** +1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ +1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI +1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI +1325:Drivers/CMSIS/Include/core_cm7.h **** +1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ +1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF +1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF +1329:Drivers/CMSIS/Include/core_cm7.h **** +1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF +1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF +1332:Drivers/CMSIS/Include/core_cm7.h **** +1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF +1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF +1335:Drivers/CMSIS/Include/core_cm7.h **** +1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF +1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF +1338:Drivers/CMSIS/Include/core_cm7.h **** +1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF +1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF +1341:Drivers/CMSIS/Include/core_cm7.h **** +1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF +1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF +1344:Drivers/CMSIS/Include/core_cm7.h **** +1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF +1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF +1347:Drivers/CMSIS/Include/core_cm7.h **** +1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ +1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA +1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA +1351:Drivers/CMSIS/Include/core_cm7.h **** +1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA +1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA + ARM GAS /tmp/ccV0GlXv.s page 28 + + +1354:Drivers/CMSIS/Include/core_cm7.h **** +1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ +1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF +1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF +1358:Drivers/CMSIS/Include/core_cm7.h **** +1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF +1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF +1361:Drivers/CMSIS/Include/core_cm7.h **** +1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF +1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF +1364:Drivers/CMSIS/Include/core_cm7.h **** +1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF +1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF +1367:Drivers/CMSIS/Include/core_cm7.h **** +1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF +1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF +1370:Drivers/CMSIS/Include/core_cm7.h **** +1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF +1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF +1373:Drivers/CMSIS/Include/core_cm7.h **** +1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF +1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF +1376:Drivers/CMSIS/Include/core_cm7.h **** +1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ +1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA +1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA +1380:Drivers/CMSIS/Include/core_cm7.h **** +1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA +1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA +1383:Drivers/CMSIS/Include/core_cm7.h **** +1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ +1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC +1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC +1387:Drivers/CMSIS/Include/core_cm7.h **** +1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ +1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV +1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV +1391:Drivers/CMSIS/Include/core_cm7.h **** +1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV +1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV +1394:Drivers/CMSIS/Include/core_cm7.h **** +1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV +1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV +1397:Drivers/CMSIS/Include/core_cm7.h **** +1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV +1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV +1400:Drivers/CMSIS/Include/core_cm7.h **** +1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV +1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV +1403:Drivers/CMSIS/Include/core_cm7.h **** +1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV +1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV +1406:Drivers/CMSIS/Include/core_cm7.h **** +1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ +1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV +1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV +1410:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 29 + + +1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV +1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV +1413:Drivers/CMSIS/Include/core_cm7.h **** +1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ +1415:Drivers/CMSIS/Include/core_cm7.h **** +1416:Drivers/CMSIS/Include/core_cm7.h **** +1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1418:Drivers/CMSIS/Include/core_cm7.h **** /** +1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) +1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) +1422:Drivers/CMSIS/Include/core_cm7.h **** @{ +1423:Drivers/CMSIS/Include/core_cm7.h **** */ +1424:Drivers/CMSIS/Include/core_cm7.h **** +1425:Drivers/CMSIS/Include/core_cm7.h **** /** +1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). +1427:Drivers/CMSIS/Include/core_cm7.h **** */ +1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1429:Drivers/CMSIS/Include/core_cm7.h **** { +1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ +1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ +1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ +1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register +1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re +1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address +1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and +1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address +1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and +1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address +1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and +1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; +1442:Drivers/CMSIS/Include/core_cm7.h **** +1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U +1444:Drivers/CMSIS/Include/core_cm7.h **** +1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ +1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU +1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU +1448:Drivers/CMSIS/Include/core_cm7.h **** +1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU +1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU +1451:Drivers/CMSIS/Include/core_cm7.h **** +1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU +1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU +1454:Drivers/CMSIS/Include/core_cm7.h **** +1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ +1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU +1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU +1458:Drivers/CMSIS/Include/core_cm7.h **** +1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU +1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU +1461:Drivers/CMSIS/Include/core_cm7.h **** +1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU +1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU +1464:Drivers/CMSIS/Include/core_cm7.h **** +1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ +1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU +1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU + ARM GAS /tmp/ccV0GlXv.s page 30 + + +1468:Drivers/CMSIS/Include/core_cm7.h **** +1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ +1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU +1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU +1472:Drivers/CMSIS/Include/core_cm7.h **** +1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU +1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU +1475:Drivers/CMSIS/Include/core_cm7.h **** +1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU +1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU +1478:Drivers/CMSIS/Include/core_cm7.h **** +1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ +1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU +1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU +1482:Drivers/CMSIS/Include/core_cm7.h **** +1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU +1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU +1485:Drivers/CMSIS/Include/core_cm7.h **** +1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU +1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU +1488:Drivers/CMSIS/Include/core_cm7.h **** +1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU +1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU +1491:Drivers/CMSIS/Include/core_cm7.h **** +1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU +1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU +1494:Drivers/CMSIS/Include/core_cm7.h **** +1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU +1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU +1497:Drivers/CMSIS/Include/core_cm7.h **** +1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU +1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU +1500:Drivers/CMSIS/Include/core_cm7.h **** +1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU +1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU +1503:Drivers/CMSIS/Include/core_cm7.h **** +1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU +1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU +1506:Drivers/CMSIS/Include/core_cm7.h **** +1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU +1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU +1509:Drivers/CMSIS/Include/core_cm7.h **** +1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ +1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +1512:Drivers/CMSIS/Include/core_cm7.h **** +1513:Drivers/CMSIS/Include/core_cm7.h **** +1514:Drivers/CMSIS/Include/core_cm7.h **** /** +1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) +1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) +1518:Drivers/CMSIS/Include/core_cm7.h **** @{ +1519:Drivers/CMSIS/Include/core_cm7.h **** */ +1520:Drivers/CMSIS/Include/core_cm7.h **** +1521:Drivers/CMSIS/Include/core_cm7.h **** /** +1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). +1523:Drivers/CMSIS/Include/core_cm7.h **** */ +1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + ARM GAS /tmp/ccV0GlXv.s page 31 + + +1525:Drivers/CMSIS/Include/core_cm7.h **** { +1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R +1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R +1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co +1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 +1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 +1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 +1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; +1534:Drivers/CMSIS/Include/core_cm7.h **** +1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ +1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC +1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC +1538:Drivers/CMSIS/Include/core_cm7.h **** +1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC +1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC +1541:Drivers/CMSIS/Include/core_cm7.h **** +1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC +1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC +1544:Drivers/CMSIS/Include/core_cm7.h **** +1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC +1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC +1547:Drivers/CMSIS/Include/core_cm7.h **** +1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC +1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC +1550:Drivers/CMSIS/Include/core_cm7.h **** +1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC +1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC +1553:Drivers/CMSIS/Include/core_cm7.h **** +1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC +1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC +1556:Drivers/CMSIS/Include/core_cm7.h **** +1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC +1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC +1559:Drivers/CMSIS/Include/core_cm7.h **** +1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC +1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC +1562:Drivers/CMSIS/Include/core_cm7.h **** +1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ +1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA +1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA +1566:Drivers/CMSIS/Include/core_cm7.h **** +1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ +1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS +1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS +1570:Drivers/CMSIS/Include/core_cm7.h **** +1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS +1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS +1573:Drivers/CMSIS/Include/core_cm7.h **** +1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS +1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS +1576:Drivers/CMSIS/Include/core_cm7.h **** +1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS +1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS +1579:Drivers/CMSIS/Include/core_cm7.h **** +1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ +1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR + ARM GAS /tmp/ccV0GlXv.s page 32 + + +1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR +1583:Drivers/CMSIS/Include/core_cm7.h **** +1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR +1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR +1586:Drivers/CMSIS/Include/core_cm7.h **** +1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR +1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR +1589:Drivers/CMSIS/Include/core_cm7.h **** +1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR +1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR +1592:Drivers/CMSIS/Include/core_cm7.h **** +1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR +1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR +1595:Drivers/CMSIS/Include/core_cm7.h **** +1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR +1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR +1598:Drivers/CMSIS/Include/core_cm7.h **** +1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR +1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR +1601:Drivers/CMSIS/Include/core_cm7.h **** +1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR +1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR +1604:Drivers/CMSIS/Include/core_cm7.h **** +1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ +1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR +1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR +1608:Drivers/CMSIS/Include/core_cm7.h **** +1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR +1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR +1611:Drivers/CMSIS/Include/core_cm7.h **** +1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR +1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR +1614:Drivers/CMSIS/Include/core_cm7.h **** +1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR +1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR +1617:Drivers/CMSIS/Include/core_cm7.h **** +1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ +1619:Drivers/CMSIS/Include/core_cm7.h **** +1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ +1621:Drivers/CMSIS/Include/core_cm7.h **** +1622:Drivers/CMSIS/Include/core_cm7.h **** +1623:Drivers/CMSIS/Include/core_cm7.h **** /** +1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers +1627:Drivers/CMSIS/Include/core_cm7.h **** @{ +1628:Drivers/CMSIS/Include/core_cm7.h **** */ +1629:Drivers/CMSIS/Include/core_cm7.h **** +1630:Drivers/CMSIS/Include/core_cm7.h **** /** +1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). +1632:Drivers/CMSIS/Include/core_cm7.h **** */ +1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1634:Drivers/CMSIS/Include/core_cm7.h **** { +1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status +1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg +1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe +1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont + ARM GAS /tmp/ccV0GlXv.s page 33 + + +1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; +1640:Drivers/CMSIS/Include/core_cm7.h **** +1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ +1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core +1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core +1644:Drivers/CMSIS/Include/core_cm7.h **** +1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core +1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core +1647:Drivers/CMSIS/Include/core_cm7.h **** +1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core +1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core +1650:Drivers/CMSIS/Include/core_cm7.h **** +1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core +1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core +1653:Drivers/CMSIS/Include/core_cm7.h **** +1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core +1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core +1656:Drivers/CMSIS/Include/core_cm7.h **** +1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core +1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core +1659:Drivers/CMSIS/Include/core_cm7.h **** +1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core +1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core +1662:Drivers/CMSIS/Include/core_cm7.h **** +1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core +1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core +1665:Drivers/CMSIS/Include/core_cm7.h **** +1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core +1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core +1668:Drivers/CMSIS/Include/core_cm7.h **** +1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core +1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core +1671:Drivers/CMSIS/Include/core_cm7.h **** +1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core +1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core +1674:Drivers/CMSIS/Include/core_cm7.h **** +1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core +1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core +1677:Drivers/CMSIS/Include/core_cm7.h **** +1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ +1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core +1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core +1681:Drivers/CMSIS/Include/core_cm7.h **** +1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core +1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core +1684:Drivers/CMSIS/Include/core_cm7.h **** +1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ +1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core +1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core +1688:Drivers/CMSIS/Include/core_cm7.h **** +1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core +1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core +1691:Drivers/CMSIS/Include/core_cm7.h **** +1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core +1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core +1694:Drivers/CMSIS/Include/core_cm7.h **** +1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core + ARM GAS /tmp/ccV0GlXv.s page 34 + + +1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core +1697:Drivers/CMSIS/Include/core_cm7.h **** +1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core +1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core +1700:Drivers/CMSIS/Include/core_cm7.h **** +1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core +1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core +1703:Drivers/CMSIS/Include/core_cm7.h **** +1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core +1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core +1706:Drivers/CMSIS/Include/core_cm7.h **** +1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core +1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core +1709:Drivers/CMSIS/Include/core_cm7.h **** +1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core +1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core +1712:Drivers/CMSIS/Include/core_cm7.h **** +1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core +1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core +1715:Drivers/CMSIS/Include/core_cm7.h **** +1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core +1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core +1718:Drivers/CMSIS/Include/core_cm7.h **** +1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core +1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core +1721:Drivers/CMSIS/Include/core_cm7.h **** +1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core +1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core +1724:Drivers/CMSIS/Include/core_cm7.h **** +1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ +1726:Drivers/CMSIS/Include/core_cm7.h **** +1727:Drivers/CMSIS/Include/core_cm7.h **** +1728:Drivers/CMSIS/Include/core_cm7.h **** /** +1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros +1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +1732:Drivers/CMSIS/Include/core_cm7.h **** @{ +1733:Drivers/CMSIS/Include/core_cm7.h **** */ +1734:Drivers/CMSIS/Include/core_cm7.h **** +1735:Drivers/CMSIS/Include/core_cm7.h **** /** +1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. +1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. +1740:Drivers/CMSIS/Include/core_cm7.h **** */ +1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +1742:Drivers/CMSIS/Include/core_cm7.h **** +1743:Drivers/CMSIS/Include/core_cm7.h **** /** +1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. +1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. +1748:Drivers/CMSIS/Include/core_cm7.h **** */ +1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +1750:Drivers/CMSIS/Include/core_cm7.h **** +1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ +1752:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 35 + + +1753:Drivers/CMSIS/Include/core_cm7.h **** +1754:Drivers/CMSIS/Include/core_cm7.h **** /** +1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions +1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. +1758:Drivers/CMSIS/Include/core_cm7.h **** @{ +1759:Drivers/CMSIS/Include/core_cm7.h **** */ +1760:Drivers/CMSIS/Include/core_cm7.h **** +1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ +1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas +1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address +1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas +1770:Drivers/CMSIS/Include/core_cm7.h **** +1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register +1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct +1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st +1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc +1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct +1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct +1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct +1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration +1779:Drivers/CMSIS/Include/core_cm7.h **** +1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * +1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * +1783:Drivers/CMSIS/Include/core_cm7.h **** #endif +1784:Drivers/CMSIS/Include/core_cm7.h **** +1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +1787:Drivers/CMSIS/Include/core_cm7.h **** +1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ +1789:Drivers/CMSIS/Include/core_cm7.h **** +1790:Drivers/CMSIS/Include/core_cm7.h **** +1791:Drivers/CMSIS/Include/core_cm7.h **** +1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* +1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer +1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: +1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions +1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions +1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions +1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions +1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ +1800:Drivers/CMSIS/Include/core_cm7.h **** /** +1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +1802:Drivers/CMSIS/Include/core_cm7.h **** */ +1803:Drivers/CMSIS/Include/core_cm7.h **** +1804:Drivers/CMSIS/Include/core_cm7.h **** +1805:Drivers/CMSIS/Include/core_cm7.h **** +1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ +1807:Drivers/CMSIS/Include/core_cm7.h **** /** +1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions + ARM GAS /tmp/ccV0GlXv.s page 36 + + +1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. +1811:Drivers/CMSIS/Include/core_cm7.h **** @{ +1812:Drivers/CMSIS/Include/core_cm7.h **** */ +1813:Drivers/CMSIS/Include/core_cm7.h **** +1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL +1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +1817:Drivers/CMSIS/Include/core_cm7.h **** #endif +1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +1819:Drivers/CMSIS/Include/core_cm7.h **** #else +1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ +1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ +1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive +1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority +1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority +1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset +1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ +1833:Drivers/CMSIS/Include/core_cm7.h **** +1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL +1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +1837:Drivers/CMSIS/Include/core_cm7.h **** #endif +1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1839:Drivers/CMSIS/Include/core_cm7.h **** #else +1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector +1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector +1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ +1843:Drivers/CMSIS/Include/core_cm7.h **** +1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 +1845:Drivers/CMSIS/Include/core_cm7.h **** +1846:Drivers/CMSIS/Include/core_cm7.h **** +1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ +1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret +1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu +1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu +1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret +1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu +1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu +1854:Drivers/CMSIS/Include/core_cm7.h **** +1855:Drivers/CMSIS/Include/core_cm7.h **** +1856:Drivers/CMSIS/Include/core_cm7.h **** /** +1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping +1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. +1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. +1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. +1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. +1864:Drivers/CMSIS/Include/core_cm7.h **** */ +1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + 39 .loc 2 1865 22 view .LVU3 + ARM GAS /tmp/ccV0GlXv.s page 37 + + + 40 .LBB39: +1866:Drivers/CMSIS/Include/core_cm7.h **** { +1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; + 41 .loc 2 1867 3 view .LVU4 +1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a + 42 .loc 2 1868 3 view .LVU5 +1869:Drivers/CMSIS/Include/core_cm7.h **** +1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register + 43 .loc 2 1870 3 view .LVU6 + 44 .loc 2 1870 14 is_stmt 0 view .LVU7 + 45 0000 0649 ldr r1, .L2 + 46 0002 CB68 ldr r3, [r1, #12] + 47 .LVL1: +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan + 48 .loc 2 1871 3 is_stmt 1 view .LVU8 + 49 .loc 2 1871 13 is_stmt 0 view .LVU9 + 50 0004 23F4E063 bic r3, r3, #1792 + 51 .LVL2: + 52 .loc 2 1871 13 view .LVU10 + 53 0008 1B04 lsls r3, r3, #16 + 54 000a 1B0C lsrs r3, r3, #16 + 55 .LVL3: +1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | + 56 .loc 2 1872 3 is_stmt 1 view .LVU11 +1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a + 57 .loc 2 1874 35 is_stmt 0 view .LVU12 + 58 000c 0002 lsls r0, r0, #8 + 59 .LVL4: + 60 .loc 2 1874 35 view .LVU13 + 61 000e 00F4E060 and r0, r0, #1792 +1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 62 .loc 2 1873 62 view .LVU14 + 63 0012 0343 orrs r3, r3, r0 + 64 .LVL5: +1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | + 65 .loc 2 1872 14 view .LVU15 + 66 0014 024A ldr r2, .L2+4 + 67 0016 1A43 orrs r2, r2, r3 + 68 .LVL6: +1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; + 69 .loc 2 1875 3 is_stmt 1 view .LVU16 + 70 .loc 2 1875 14 is_stmt 0 view .LVU17 + 71 0018 CA60 str r2, [r1, #12] + 72 .LVL7: + 73 .loc 2 1875 14 view .LVU18 + 74 .LBE39: + 75 .LBE38: + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 76 .loc 1 150 1 view .LVU19 + 77 001a 7047 bx lr + 78 .L3: + 79 .align 2 + 80 .L2: + 81 001c 00ED00E0 .word -536810240 + 82 0020 0000FA05 .word 100270080 + 83 .cfi_endproc + ARM GAS /tmp/ccV0GlXv.s page 38 + + + 84 .LFE141: + 86 .section .text.HAL_NVIC_SetPriority,"ax",%progbits + 87 .align 1 + 88 .global HAL_NVIC_SetPriority + 89 .syntax unified + 90 .thumb + 91 .thumb_func + 92 .fpu fpv5-d16 + 94 HAL_NVIC_SetPriority: + 95 .LVL8: + 96 .LFB142: + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param PreemptPriority The preemption priority for the IRQn channel. + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * A lower priority value indicates a higher priority + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * A lower priority value indicates a higher priority. + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 97 .loc 1 166 1 is_stmt 1 view -0 + 98 .cfi_startproc + 99 @ args = 0, pretend = 0, frame = 0 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 101 .loc 1 166 1 is_stmt 0 view .LVU21 + 102 0000 00B5 push {lr} + 103 .LCFI0: + 104 .cfi_def_cfa_offset 4 + 105 .cfi_offset 14, -4 + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t prioritygroup; + 106 .loc 1 167 3 is_stmt 1 view .LVU22 + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + 107 .loc 1 170 3 view .LVU23 + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 108 .loc 1 171 3 view .LVU24 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); + 109 .loc 1 173 3 view .LVU25 + 110 .LBB46: + 111 .LBI46: +1876:Drivers/CMSIS/Include/core_cm7.h **** } +1877:Drivers/CMSIS/Include/core_cm7.h **** +1878:Drivers/CMSIS/Include/core_cm7.h **** +1879:Drivers/CMSIS/Include/core_cm7.h **** /** +1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping +1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. +1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +1883:Drivers/CMSIS/Include/core_cm7.h **** */ + ARM GAS /tmp/ccV0GlXv.s page 39 + + +1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) + 112 .loc 2 1884 26 view .LVU26 + 113 .LBB47: +1885:Drivers/CMSIS/Include/core_cm7.h **** { +1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 114 .loc 2 1886 3 view .LVU27 + 115 .loc 2 1886 26 is_stmt 0 view .LVU28 + 116 0002 174B ldr r3, .L10 + 117 0004 DB68 ldr r3, [r3, #12] + 118 .loc 2 1886 11 view .LVU29 + 119 0006 C3F30223 ubfx r3, r3, #8, #3 + 120 .LVL9: + 121 .loc 2 1886 11 view .LVU30 + 122 .LBE47: + 123 .LBE46: + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 124 .loc 1 175 3 is_stmt 1 view .LVU31 + 125 .LBB48: + 126 .LBI48: +1887:Drivers/CMSIS/Include/core_cm7.h **** } +1888:Drivers/CMSIS/Include/core_cm7.h **** +1889:Drivers/CMSIS/Include/core_cm7.h **** +1890:Drivers/CMSIS/Include/core_cm7.h **** /** +1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt +1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. +1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1895:Drivers/CMSIS/Include/core_cm7.h **** */ +1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +1897:Drivers/CMSIS/Include/core_cm7.h **** { +1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1899:Drivers/CMSIS/Include/core_cm7.h **** { +1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1901:Drivers/CMSIS/Include/core_cm7.h **** } +1902:Drivers/CMSIS/Include/core_cm7.h **** } +1903:Drivers/CMSIS/Include/core_cm7.h **** +1904:Drivers/CMSIS/Include/core_cm7.h **** +1905:Drivers/CMSIS/Include/core_cm7.h **** /** +1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status +1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. +1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. +1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1912:Drivers/CMSIS/Include/core_cm7.h **** */ +1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +1914:Drivers/CMSIS/Include/core_cm7.h **** { +1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1916:Drivers/CMSIS/Include/core_cm7.h **** { +1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1918:Drivers/CMSIS/Include/core_cm7.h **** } +1919:Drivers/CMSIS/Include/core_cm7.h **** else +1920:Drivers/CMSIS/Include/core_cm7.h **** { +1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1922:Drivers/CMSIS/Include/core_cm7.h **** } +1923:Drivers/CMSIS/Include/core_cm7.h **** } + ARM GAS /tmp/ccV0GlXv.s page 40 + + +1924:Drivers/CMSIS/Include/core_cm7.h **** +1925:Drivers/CMSIS/Include/core_cm7.h **** +1926:Drivers/CMSIS/Include/core_cm7.h **** /** +1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt +1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. +1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1931:Drivers/CMSIS/Include/core_cm7.h **** */ +1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +1933:Drivers/CMSIS/Include/core_cm7.h **** { +1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1935:Drivers/CMSIS/Include/core_cm7.h **** { +1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +1939:Drivers/CMSIS/Include/core_cm7.h **** } +1940:Drivers/CMSIS/Include/core_cm7.h **** } +1941:Drivers/CMSIS/Include/core_cm7.h **** +1942:Drivers/CMSIS/Include/core_cm7.h **** +1943:Drivers/CMSIS/Include/core_cm7.h **** /** +1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt +1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe +1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. +1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. +1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1950:Drivers/CMSIS/Include/core_cm7.h **** */ +1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +1952:Drivers/CMSIS/Include/core_cm7.h **** { +1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1954:Drivers/CMSIS/Include/core_cm7.h **** { +1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1956:Drivers/CMSIS/Include/core_cm7.h **** } +1957:Drivers/CMSIS/Include/core_cm7.h **** else +1958:Drivers/CMSIS/Include/core_cm7.h **** { +1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1960:Drivers/CMSIS/Include/core_cm7.h **** } +1961:Drivers/CMSIS/Include/core_cm7.h **** } +1962:Drivers/CMSIS/Include/core_cm7.h **** +1963:Drivers/CMSIS/Include/core_cm7.h **** +1964:Drivers/CMSIS/Include/core_cm7.h **** /** +1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt +1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1969:Drivers/CMSIS/Include/core_cm7.h **** */ +1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +1971:Drivers/CMSIS/Include/core_cm7.h **** { +1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1973:Drivers/CMSIS/Include/core_cm7.h **** { +1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1975:Drivers/CMSIS/Include/core_cm7.h **** } +1976:Drivers/CMSIS/Include/core_cm7.h **** } +1977:Drivers/CMSIS/Include/core_cm7.h **** +1978:Drivers/CMSIS/Include/core_cm7.h **** +1979:Drivers/CMSIS/Include/core_cm7.h **** /** +1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt + ARM GAS /tmp/ccV0GlXv.s page 41 + + +1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1984:Drivers/CMSIS/Include/core_cm7.h **** */ +1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +1986:Drivers/CMSIS/Include/core_cm7.h **** { +1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1988:Drivers/CMSIS/Include/core_cm7.h **** { +1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1990:Drivers/CMSIS/Include/core_cm7.h **** } +1991:Drivers/CMSIS/Include/core_cm7.h **** } +1992:Drivers/CMSIS/Include/core_cm7.h **** +1993:Drivers/CMSIS/Include/core_cm7.h **** +1994:Drivers/CMSIS/Include/core_cm7.h **** /** +1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt +1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific +1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. +1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. +2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +2001:Drivers/CMSIS/Include/core_cm7.h **** */ +2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +2003:Drivers/CMSIS/Include/core_cm7.h **** { +2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2005:Drivers/CMSIS/Include/core_cm7.h **** { +2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +2007:Drivers/CMSIS/Include/core_cm7.h **** } +2008:Drivers/CMSIS/Include/core_cm7.h **** else +2009:Drivers/CMSIS/Include/core_cm7.h **** { +2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +2011:Drivers/CMSIS/Include/core_cm7.h **** } +2012:Drivers/CMSIS/Include/core_cm7.h **** } +2013:Drivers/CMSIS/Include/core_cm7.h **** +2014:Drivers/CMSIS/Include/core_cm7.h **** +2015:Drivers/CMSIS/Include/core_cm7.h **** /** +2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority +2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. +2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. +2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. +2023:Drivers/CMSIS/Include/core_cm7.h **** */ +2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +2025:Drivers/CMSIS/Include/core_cm7.h **** { +2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2027:Drivers/CMSIS/Include/core_cm7.h **** { +2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( +2029:Drivers/CMSIS/Include/core_cm7.h **** } +2030:Drivers/CMSIS/Include/core_cm7.h **** else +2031:Drivers/CMSIS/Include/core_cm7.h **** { +2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( +2033:Drivers/CMSIS/Include/core_cm7.h **** } +2034:Drivers/CMSIS/Include/core_cm7.h **** } +2035:Drivers/CMSIS/Include/core_cm7.h **** +2036:Drivers/CMSIS/Include/core_cm7.h **** +2037:Drivers/CMSIS/Include/core_cm7.h **** /** + ARM GAS /tmp/ccV0GlXv.s page 42 + + +2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority +2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. +2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. +2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc +2045:Drivers/CMSIS/Include/core_cm7.h **** */ +2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +2047:Drivers/CMSIS/Include/core_cm7.h **** { +2048:Drivers/CMSIS/Include/core_cm7.h **** +2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2050:Drivers/CMSIS/Include/core_cm7.h **** { +2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); +2052:Drivers/CMSIS/Include/core_cm7.h **** } +2053:Drivers/CMSIS/Include/core_cm7.h **** else +2054:Drivers/CMSIS/Include/core_cm7.h **** { +2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); +2056:Drivers/CMSIS/Include/core_cm7.h **** } +2057:Drivers/CMSIS/Include/core_cm7.h **** } +2058:Drivers/CMSIS/Include/core_cm7.h **** +2059:Drivers/CMSIS/Include/core_cm7.h **** +2060:Drivers/CMSIS/Include/core_cm7.h **** /** +2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority +2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, +2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. +2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). +2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). +2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP +2070:Drivers/CMSIS/Include/core_cm7.h **** */ +2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin + 127 .loc 2 2071 26 view .LVU32 + 128 .LBB49: +2072:Drivers/CMSIS/Include/core_cm7.h **** { +2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 129 .loc 2 2073 3 view .LVU33 +2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; + 130 .loc 2 2074 3 view .LVU34 +2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; + 131 .loc 2 2075 3 view .LVU35 +2076:Drivers/CMSIS/Include/core_cm7.h **** +2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 132 .loc 2 2077 3 view .LVU36 + 133 .loc 2 2077 31 is_stmt 0 view .LVU37 + 134 000a C3F1070C rsb ip, r3, #7 + 135 .loc 2 2077 23 view .LVU38 + 136 000e BCF1040F cmp ip, #4 + 137 0012 28BF it cs + 138 0014 4FF0040C movcs ip, #4 + 139 .LVL10: +2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 140 .loc 2 2078 3 is_stmt 1 view .LVU39 + 141 .loc 2 2078 44 is_stmt 0 view .LVU40 + 142 0018 03F1040E add lr, r3, #4 + ARM GAS /tmp/ccV0GlXv.s page 43 + + + 143 .loc 2 2078 109 view .LVU41 + 144 001c BEF1060F cmp lr, #6 + 145 0020 14D9 bls .L8 + 146 0022 033B subs r3, r3, #3 + 147 .LVL11: + 148 .L5: +2079:Drivers/CMSIS/Include/core_cm7.h **** +2080:Drivers/CMSIS/Include/core_cm7.h **** return ( + 149 .loc 2 2080 3 is_stmt 1 view .LVU42 +2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 150 .loc 2 2081 30 is_stmt 0 view .LVU43 + 151 0024 4FF0FF3E mov lr, #-1 + 152 .LVL12: + 153 .loc 2 2081 30 view .LVU44 + 154 0028 0EFA0CFC lsl ip, lr, ip + 155 .LVL13: + 156 .loc 2 2081 30 view .LVU45 + 157 002c 21EA0C01 bic r1, r1, ip + 158 .LVL14: + 159 .loc 2 2081 82 view .LVU46 + 160 0030 9940 lsls r1, r1, r3 +2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 161 .loc 2 2082 30 view .LVU47 + 162 0032 0EFA03F3 lsl r3, lr, r3 + 163 .LVL15: + 164 .loc 2 2082 30 view .LVU48 + 165 0036 22EA0303 bic r3, r2, r3 +2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 166 .loc 2 2081 102 view .LVU49 + 167 003a 1943 orrs r1, r1, r3 + 168 .LVL16: +2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 169 .loc 2 2081 102 view .LVU50 + 170 .LBE49: + 171 .LBE48: + 172 .LBB51: + 173 .LBI51: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 174 .loc 2 2024 22 is_stmt 1 view .LVU51 + 175 .LBB52: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 176 .loc 2 2026 3 view .LVU52 +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 177 .loc 2 2026 6 is_stmt 0 view .LVU53 + 178 003c 0028 cmp r0, #0 + 179 003e 07DB blt .L6 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 180 .loc 2 2028 5 is_stmt 1 view .LVU54 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 181 .loc 2 2028 49 is_stmt 0 view .LVU55 + 182 0040 0901 lsls r1, r1, #4 + 183 .LVL17: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 184 .loc 2 2028 49 view .LVU56 + 185 0042 C9B2 uxtb r1, r1 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 186 .loc 2 2028 47 view .LVU57 + ARM GAS /tmp/ccV0GlXv.s page 44 + + + 187 0044 074B ldr r3, .L10+4 + 188 0046 1954 strb r1, [r3, r0] + 189 .LVL18: + 190 .L4: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 191 .loc 2 2028 47 view .LVU58 + 192 .LBE52: + 193 .LBE51: + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 194 .loc 1 176 1 view .LVU59 + 195 0048 5DF804FB ldr pc, [sp], #4 + 196 .LVL19: + 197 .L8: + 198 .LBB54: + 199 .LBB50: +2078:Drivers/CMSIS/Include/core_cm7.h **** + 200 .loc 2 2078 109 view .LVU60 + 201 004c 0023 movs r3, #0 + 202 .LVL20: +2078:Drivers/CMSIS/Include/core_cm7.h **** + 203 .loc 2 2078 109 view .LVU61 + 204 004e E9E7 b .L5 + 205 .LVL21: + 206 .L6: +2078:Drivers/CMSIS/Include/core_cm7.h **** + 207 .loc 2 2078 109 view .LVU62 + 208 .LBE50: + 209 .LBE54: + 210 .LBB55: + 211 .LBB53: +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 212 .loc 2 2032 5 is_stmt 1 view .LVU63 +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 213 .loc 2 2032 33 is_stmt 0 view .LVU64 + 214 0050 00F00F00 and r0, r0, #15 + 215 .LVL22: +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 216 .loc 2 2032 49 view .LVU65 + 217 0054 0901 lsls r1, r1, #4 + 218 .LVL23: +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 219 .loc 2 2032 49 view .LVU66 + 220 0056 C9B2 uxtb r1, r1 +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 221 .loc 2 2032 47 view .LVU67 + 222 0058 034B ldr r3, .L10+8 + 223 005a 1954 strb r1, [r3, r0] + 224 .LVL24: +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 225 .loc 2 2032 47 view .LVU68 + 226 .LBE53: + 227 .LBE55: + 228 .loc 1 176 1 view .LVU69 + 229 005c F4E7 b .L4 + 230 .L11: + 231 005e 00BF .align 2 + 232 .L10: + ARM GAS /tmp/ccV0GlXv.s page 45 + + + 233 0060 00ED00E0 .word -536810240 + 234 0064 00E400E0 .word -536812544 + 235 0068 14ED00E0 .word -536810220 + 236 .cfi_endproc + 237 .LFE142: + 239 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits + 240 .align 1 + 241 .global HAL_NVIC_EnableIRQ + 242 .syntax unified + 243 .thumb + 244 .thumb_func + 245 .fpu fpv5-d16 + 247 HAL_NVIC_EnableIRQ: + 248 .LVL25: + 249 .LFB143: + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * function should be called before. + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 250 .loc 1 188 1 is_stmt 1 view -0 + 251 .cfi_startproc + 252 @ args = 0, pretend = 0, frame = 0 + 253 @ frame_needed = 0, uses_anonymous_args = 0 + 254 @ link register save eliminated. + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 255 .loc 1 190 3 view .LVU71 + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Enable interrupt */ + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); + 256 .loc 1 193 3 view .LVU72 + 257 .LBB56: + 258 .LBI56: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 259 .loc 2 1896 22 view .LVU73 + 260 .LBB57: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 261 .loc 2 1898 3 view .LVU74 +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 262 .loc 2 1898 6 is_stmt 0 view .LVU75 + 263 0000 0028 cmp r0, #0 + 264 .LVL26: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 265 .loc 2 1898 6 view .LVU76 + 266 0002 07DB blt .L12 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 267 .loc 2 1900 5 is_stmt 1 view .LVU77 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 268 .loc 2 1900 81 is_stmt 0 view .LVU78 + ARM GAS /tmp/ccV0GlXv.s page 46 + + + 269 0004 00F01F02 and r2, r0, #31 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 270 .loc 2 1900 34 view .LVU79 + 271 0008 4009 lsrs r0, r0, #5 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 272 .loc 2 1900 45 view .LVU80 + 273 000a 0123 movs r3, #1 + 274 000c 9340 lsls r3, r3, r2 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 275 .loc 2 1900 43 view .LVU81 + 276 000e 024A ldr r2, .L14 + 277 0010 42F82030 str r3, [r2, r0, lsl #2] + 278 .LVL27: + 279 .L12: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 280 .loc 2 1900 43 view .LVU82 + 281 .LBE57: + 282 .LBE56: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 283 .loc 1 194 1 view .LVU83 + 284 0014 7047 bx lr + 285 .L15: + 286 0016 00BF .align 2 + 287 .L14: + 288 0018 00E100E0 .word -536813312 + 289 .cfi_endproc + 290 .LFE143: + 292 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits + 293 .align 1 + 294 .global HAL_NVIC_DisableIRQ + 295 .syntax unified + 296 .thumb + 297 .thumb_func + 298 .fpu fpv5-d16 + 300 HAL_NVIC_DisableIRQ: + 301 .LVL28: + 302 .LFB144: + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 303 .loc 1 204 1 is_stmt 1 view -0 + 304 .cfi_startproc + 305 @ args = 0, pretend = 0, frame = 0 + 306 @ frame_needed = 0, uses_anonymous_args = 0 + 307 @ link register save eliminated. + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 308 .loc 1 206 3 view .LVU85 + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Disable interrupt */ + ARM GAS /tmp/ccV0GlXv.s page 47 + + + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); + 309 .loc 1 209 3 view .LVU86 + 310 .LBB64: + 311 .LBI64: +1932:Drivers/CMSIS/Include/core_cm7.h **** { + 312 .loc 2 1932 22 view .LVU87 + 313 .LBB65: +1934:Drivers/CMSIS/Include/core_cm7.h **** { + 314 .loc 2 1934 3 view .LVU88 +1934:Drivers/CMSIS/Include/core_cm7.h **** { + 315 .loc 2 1934 6 is_stmt 0 view .LVU89 + 316 0000 0028 cmp r0, #0 + 317 .LVL29: +1934:Drivers/CMSIS/Include/core_cm7.h **** { + 318 .loc 2 1934 6 view .LVU90 + 319 0002 0CDB blt .L16 +1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + 320 .loc 2 1936 5 is_stmt 1 view .LVU91 +1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + 321 .loc 2 1936 81 is_stmt 0 view .LVU92 + 322 0004 00F01F02 and r2, r0, #31 +1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + 323 .loc 2 1936 34 view .LVU93 + 324 0008 4009 lsrs r0, r0, #5 +1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + 325 .loc 2 1936 45 view .LVU94 + 326 000a 0123 movs r3, #1 + 327 000c 9340 lsls r3, r3, r2 +1936:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + 328 .loc 2 1936 43 view .LVU95 + 329 000e 2030 adds r0, r0, #32 + 330 0010 034A ldr r2, .L18 + 331 0012 42F82030 str r3, [r2, r0, lsl #2] +1937:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); + 332 .loc 2 1937 5 is_stmt 1 view .LVU96 + 333 .LBB66: + 334 .LBI66: + 335 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + ARM GAS /tmp/ccV0GlXv.s page 48 + + + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + ARM GAS /tmp/ccV0GlXv.s page 49 + + + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccV0GlXv.s page 50 + + + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + ARM GAS /tmp/ccV0GlXv.s page 51 + + + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + ARM GAS /tmp/ccV0GlXv.s page 52 + + + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccV0GlXv.s page 53 + + + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccV0GlXv.s page 54 + + + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + ARM GAS /tmp/ccV0GlXv.s page 55 + + + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccV0GlXv.s page 56 + + + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccV0GlXv.s page 57 + + + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + ARM GAS /tmp/ccV0GlXv.s page 58 + + + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccV0GlXv.s page 59 + + + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccV0GlXv.s page 60 + + + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccV0GlXv.s page 61 + + + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccV0GlXv.s page 62 + + + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + ARM GAS /tmp/ccV0GlXv.s page 63 + + + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 336 .loc 3 877 27 view .LVU97 + 337 .LBB67: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 338 .loc 3 879 3 view .LVU98 + 339 .syntax unified + 340 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 341 0016 BFF34F8F dsb 0xF + 342 @ 0 "" 2 + 343 .thumb + 344 .syntax unified + 345 .LBE67: + 346 .LBE66: +1938:Drivers/CMSIS/Include/core_cm7.h **** } + 347 .loc 2 1938 5 view .LVU99 + 348 .LBB68: + 349 .LBI68: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 350 .loc 3 866 27 view .LVU100 + 351 .LBB69: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 352 .loc 3 868 3 view .LVU101 + 353 .syntax unified + 354 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 355 001a BFF36F8F isb 0xF + 356 @ 0 "" 2 + 357 .LVL30: + 358 .thumb + 359 .syntax unified + 360 .L16: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 361 .loc 3 868 3 is_stmt 0 view .LVU102 + 362 .LBE69: + 363 .LBE68: + 364 .LBE65: + 365 .LBE64: + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 366 .loc 1 210 1 view .LVU103 + 367 001e 7047 bx lr + 368 .L19: + 369 .align 2 + 370 .L18: + 371 0020 00E100E0 .word -536813312 + 372 .cfi_endproc + 373 .LFE144: + 375 .section .text.HAL_NVIC_SystemReset,"ax",%progbits + 376 .align 1 + 377 .global HAL_NVIC_SystemReset + 378 .syntax unified + 379 .thumb + 380 .thumb_func + 381 .fpu fpv5-d16 + 383 HAL_NVIC_SystemReset: + 384 .LFB145: + ARM GAS /tmp/ccV0GlXv.s page 64 + + + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 385 .loc 1 217 1 is_stmt 1 view -0 + 386 .cfi_startproc + 387 @ Volatile: function does not return. + 388 @ args = 0, pretend = 0, frame = 0 + 389 @ frame_needed = 0, uses_anonymous_args = 0 + 390 @ link register save eliminated. + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* System Reset */ + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SystemReset(); + 391 .loc 1 219 3 view .LVU105 + 392 .LBB76: + 393 .LBI76: +2083:Drivers/CMSIS/Include/core_cm7.h **** ); +2084:Drivers/CMSIS/Include/core_cm7.h **** } +2085:Drivers/CMSIS/Include/core_cm7.h **** +2086:Drivers/CMSIS/Include/core_cm7.h **** +2087:Drivers/CMSIS/Include/core_cm7.h **** /** +2088:Drivers/CMSIS/Include/core_cm7.h **** \brief Decode Priority +2089:Drivers/CMSIS/Include/core_cm7.h **** \details Decodes an interrupt priority value with a given priority group to +2090:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value and subpriority value. +2091:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2092:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +2093:Drivers/CMSIS/Include/core_cm7.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC +2094:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2095:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). +2096:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pSubPriority Subpriority value (starting from 0). +2097:Drivers/CMSIS/Include/core_cm7.h **** */ +2098:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons +2099:Drivers/CMSIS/Include/core_cm7.h **** { +2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used +2101:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; +2102:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; +2103:Drivers/CMSIS/Include/core_cm7.h **** +2104:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV +2105:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint +2106:Drivers/CMSIS/Include/core_cm7.h **** +2107:Drivers/CMSIS/Include/core_cm7.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 +2108:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 +2109:Drivers/CMSIS/Include/core_cm7.h **** } +2110:Drivers/CMSIS/Include/core_cm7.h **** +2111:Drivers/CMSIS/Include/core_cm7.h **** +2112:Drivers/CMSIS/Include/core_cm7.h **** /** +2113:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Vector +2114:Drivers/CMSIS/Include/core_cm7.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. +2115:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2116:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2117:Drivers/CMSIS/Include/core_cm7.h **** VTOR must been relocated to SRAM before. +2118:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number +2119:Drivers/CMSIS/Include/core_cm7.h **** \param [in] vector Address of interrupt handler function +2120:Drivers/CMSIS/Include/core_cm7.h **** */ +2121:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) + ARM GAS /tmp/ccV0GlXv.s page 65 + + +2122:Drivers/CMSIS/Include/core_cm7.h **** { +2123:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +2124:Drivers/CMSIS/Include/core_cm7.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +2125:Drivers/CMSIS/Include/core_cm7.h **** } +2126:Drivers/CMSIS/Include/core_cm7.h **** +2127:Drivers/CMSIS/Include/core_cm7.h **** +2128:Drivers/CMSIS/Include/core_cm7.h **** /** +2129:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Vector +2130:Drivers/CMSIS/Include/core_cm7.h **** \details Reads an interrupt vector from interrupt vector table. +2131:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2132:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2133:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2134:Drivers/CMSIS/Include/core_cm7.h **** \return Address of interrupt handler function +2135:Drivers/CMSIS/Include/core_cm7.h **** */ +2136:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +2137:Drivers/CMSIS/Include/core_cm7.h **** { +2138:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +2139:Drivers/CMSIS/Include/core_cm7.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +2140:Drivers/CMSIS/Include/core_cm7.h **** } +2141:Drivers/CMSIS/Include/core_cm7.h **** +2142:Drivers/CMSIS/Include/core_cm7.h **** +2143:Drivers/CMSIS/Include/core_cm7.h **** /** +2144:Drivers/CMSIS/Include/core_cm7.h **** \brief System Reset +2145:Drivers/CMSIS/Include/core_cm7.h **** \details Initiates a system reset request to reset the MCU. +2146:Drivers/CMSIS/Include/core_cm7.h **** */ +2147:Drivers/CMSIS/Include/core_cm7.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) + 394 .loc 2 2147 34 view .LVU106 + 395 .LBB77: +2148:Drivers/CMSIS/Include/core_cm7.h **** { +2149:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure all outstanding memor + 396 .loc 2 2149 3 view .LVU107 + 397 .LBB78: + 398 .LBI78: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399 .loc 3 877 27 view .LVU108 + 400 .LBB79: + 401 .loc 3 879 3 view .LVU109 + 402 .syntax unified + 403 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 404 0000 BFF34F8F dsb 0xF + 405 @ 0 "" 2 + 406 .thumb + 407 .syntax unified + 408 .LBE79: + 409 .LBE78: +2150:Drivers/CMSIS/Include/core_cm7.h **** buffered write are completed +2151:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 410 .loc 2 2151 3 view .LVU110 +2152:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 411 .loc 2 2152 32 is_stmt 0 view .LVU111 + 412 0004 0549 ldr r1, .L22 + 413 0006 CA68 ldr r2, [r1, #12] + 414 .loc 2 2152 40 view .LVU112 + 415 0008 02F4E062 and r2, r2, #1792 +2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 416 .loc 2 2151 17 view .LVU113 + 417 000c 044B ldr r3, .L22+4 + ARM GAS /tmp/ccV0GlXv.s page 66 + + + 418 000e 1343 orrs r3, r3, r2 +2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 419 .loc 2 2151 15 view .LVU114 + 420 0010 CB60 str r3, [r1, #12] +2153:Drivers/CMSIS/Include/core_cm7.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange +2154:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure completion of memory + 421 .loc 2 2154 3 is_stmt 1 view .LVU115 + 422 .LBB80: + 423 .LBI80: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 424 .loc 3 877 27 view .LVU116 + 425 .LBB81: + 426 .loc 3 879 3 view .LVU117 + 427 .syntax unified + 428 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 429 0012 BFF34F8F dsb 0xF + 430 @ 0 "" 2 + 431 .thumb + 432 .syntax unified + 433 .L21: + 434 .LBE81: + 435 .LBE80: +2155:Drivers/CMSIS/Include/core_cm7.h **** +2156:Drivers/CMSIS/Include/core_cm7.h **** for(;;) /* wait until reset */ + 436 .loc 2 2156 3 view .LVU118 +2157:Drivers/CMSIS/Include/core_cm7.h **** { +2158:Drivers/CMSIS/Include/core_cm7.h **** __NOP(); + 437 .loc 2 2158 5 view .LVU119 + 438 .syntax unified + 439 @ 2158 "Drivers/CMSIS/Include/core_cm7.h" 1 + 440 0016 00BF nop + 441 @ 0 "" 2 +2156:Drivers/CMSIS/Include/core_cm7.h **** { + 442 .loc 2 2156 8 view .LVU120 + 443 .thumb + 444 .syntax unified + 445 0018 FDE7 b .L21 + 446 .L23: + 447 001a 00BF .align 2 + 448 .L22: + 449 001c 00ED00E0 .word -536810240 + 450 0020 0400FA05 .word 100270084 + 451 .LBE77: + 452 .LBE76: + 453 .cfi_endproc + 454 .LFE145: + 456 .section .text.HAL_SYSTICK_Config,"ax",%progbits + 457 .align 1 + 458 .global HAL_SYSTICK_Config + 459 .syntax unified + 460 .thumb + 461 .thumb_func + 462 .fpu fpv5-d16 + 464 HAL_SYSTICK_Config: + 465 .LVL31: + 466 .LFB146: + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + ARM GAS /tmp/ccV0GlXv.s page 67 + + + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval status - 0 Function succeeded. + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * - 1 Function failed. + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 467 .loc 1 230 1 view -0 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 0 + 470 @ frame_needed = 0, uses_anonymous_args = 0 + 471 @ link register save eliminated. + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 472 .loc 1 231 4 view .LVU122 + 473 .LBB82: + 474 .LBI82: +2159:Drivers/CMSIS/Include/core_cm7.h **** } +2160:Drivers/CMSIS/Include/core_cm7.h **** } +2161:Drivers/CMSIS/Include/core_cm7.h **** +2162:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_NVICFunctions */ +2163:Drivers/CMSIS/Include/core_cm7.h **** +2164:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## MPU functions #################################### */ +2165:Drivers/CMSIS/Include/core_cm7.h **** +2166:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +2167:Drivers/CMSIS/Include/core_cm7.h **** +2168:Drivers/CMSIS/Include/core_cm7.h **** #include "mpu_armv7.h" +2169:Drivers/CMSIS/Include/core_cm7.h **** +2170:Drivers/CMSIS/Include/core_cm7.h **** #endif +2171:Drivers/CMSIS/Include/core_cm7.h **** +2172:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## FPU functions #################################### */ +2173:Drivers/CMSIS/Include/core_cm7.h **** /** +2174:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +2175:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions +2176:Drivers/CMSIS/Include/core_cm7.h **** \brief Function that provides FPU type. +2177:Drivers/CMSIS/Include/core_cm7.h **** @{ +2178:Drivers/CMSIS/Include/core_cm7.h **** */ +2179:Drivers/CMSIS/Include/core_cm7.h **** +2180:Drivers/CMSIS/Include/core_cm7.h **** /** +2181:Drivers/CMSIS/Include/core_cm7.h **** \brief get FPU type +2182:Drivers/CMSIS/Include/core_cm7.h **** \details returns the FPU type +2183:Drivers/CMSIS/Include/core_cm7.h **** \returns +2184:Drivers/CMSIS/Include/core_cm7.h **** - \b 0: No FPU +2185:Drivers/CMSIS/Include/core_cm7.h **** - \b 1: Single precision FPU +2186:Drivers/CMSIS/Include/core_cm7.h **** - \b 2: Double + Single precision FPU +2187:Drivers/CMSIS/Include/core_cm7.h **** */ +2188:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) +2189:Drivers/CMSIS/Include/core_cm7.h **** { +2190:Drivers/CMSIS/Include/core_cm7.h **** uint32_t mvfr0; +2191:Drivers/CMSIS/Include/core_cm7.h **** +2192:Drivers/CMSIS/Include/core_cm7.h **** mvfr0 = SCB->MVFR0; +2193:Drivers/CMSIS/Include/core_cm7.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) +2194:Drivers/CMSIS/Include/core_cm7.h **** { +2195:Drivers/CMSIS/Include/core_cm7.h **** return 2U; /* Double + Single precision FPU */ +2196:Drivers/CMSIS/Include/core_cm7.h **** } + ARM GAS /tmp/ccV0GlXv.s page 68 + + +2197:Drivers/CMSIS/Include/core_cm7.h **** else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) +2198:Drivers/CMSIS/Include/core_cm7.h **** { +2199:Drivers/CMSIS/Include/core_cm7.h **** return 1U; /* Single precision FPU */ +2200:Drivers/CMSIS/Include/core_cm7.h **** } +2201:Drivers/CMSIS/Include/core_cm7.h **** else +2202:Drivers/CMSIS/Include/core_cm7.h **** { +2203:Drivers/CMSIS/Include/core_cm7.h **** return 0U; /* No FPU */ +2204:Drivers/CMSIS/Include/core_cm7.h **** } +2205:Drivers/CMSIS/Include/core_cm7.h **** } +2206:Drivers/CMSIS/Include/core_cm7.h **** +2207:Drivers/CMSIS/Include/core_cm7.h **** +2208:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_FpuFunctions */ +2209:Drivers/CMSIS/Include/core_cm7.h **** +2210:Drivers/CMSIS/Include/core_cm7.h **** +2211:Drivers/CMSIS/Include/core_cm7.h **** +2212:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## Cache functions #################################### */ +2213:Drivers/CMSIS/Include/core_cm7.h **** /** +2214:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +2215:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_CacheFunctions Cache Functions +2216:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that configure Instruction and Data cache. +2217:Drivers/CMSIS/Include/core_cm7.h **** @{ +2218:Drivers/CMSIS/Include/core_cm7.h **** */ +2219:Drivers/CMSIS/Include/core_cm7.h **** +2220:Drivers/CMSIS/Include/core_cm7.h **** /* Cache Size ID Register Macros */ +2221:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Po +2222:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos +2223:Drivers/CMSIS/Include/core_cm7.h **** +2224:Drivers/CMSIS/Include/core_cm7.h **** +2225:Drivers/CMSIS/Include/core_cm7.h **** /** +2226:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable I-Cache +2227:Drivers/CMSIS/Include/core_cm7.h **** \details Turns on I-Cache +2228:Drivers/CMSIS/Include/core_cm7.h **** */ +2229:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableICache (void) +2230:Drivers/CMSIS/Include/core_cm7.h **** { +2231:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) +2232:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2233:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2234:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */ +2235:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2236:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2237:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ +2238:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2239:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2240:Drivers/CMSIS/Include/core_cm7.h **** #endif +2241:Drivers/CMSIS/Include/core_cm7.h **** } +2242:Drivers/CMSIS/Include/core_cm7.h **** +2243:Drivers/CMSIS/Include/core_cm7.h **** +2244:Drivers/CMSIS/Include/core_cm7.h **** /** +2245:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable I-Cache +2246:Drivers/CMSIS/Include/core_cm7.h **** \details Turns off I-Cache +2247:Drivers/CMSIS/Include/core_cm7.h **** */ +2248:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableICache (void) +2249:Drivers/CMSIS/Include/core_cm7.h **** { +2250:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) +2251:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2252:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2253:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + ARM GAS /tmp/ccV0GlXv.s page 69 + + +2254:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */ +2255:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2256:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2257:Drivers/CMSIS/Include/core_cm7.h **** #endif +2258:Drivers/CMSIS/Include/core_cm7.h **** } +2259:Drivers/CMSIS/Include/core_cm7.h **** +2260:Drivers/CMSIS/Include/core_cm7.h **** +2261:Drivers/CMSIS/Include/core_cm7.h **** /** +2262:Drivers/CMSIS/Include/core_cm7.h **** \brief Invalidate I-Cache +2263:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates I-Cache +2264:Drivers/CMSIS/Include/core_cm7.h **** */ +2265:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateICache (void) +2266:Drivers/CMSIS/Include/core_cm7.h **** { +2267:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) +2268:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2269:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2270:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; +2271:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2272:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2273:Drivers/CMSIS/Include/core_cm7.h **** #endif +2274:Drivers/CMSIS/Include/core_cm7.h **** } +2275:Drivers/CMSIS/Include/core_cm7.h **** +2276:Drivers/CMSIS/Include/core_cm7.h **** +2277:Drivers/CMSIS/Include/core_cm7.h **** /** +2278:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable D-Cache +2279:Drivers/CMSIS/Include/core_cm7.h **** \details Turns on D-Cache +2280:Drivers/CMSIS/Include/core_cm7.h **** */ +2281:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableDCache (void) +2282:Drivers/CMSIS/Include/core_cm7.h **** { +2283:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2287:Drivers/CMSIS/Include/core_cm7.h **** +2288:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2289:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2290:Drivers/CMSIS/Include/core_cm7.h **** +2291:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2292:Drivers/CMSIS/Include/core_cm7.h **** +2293:Drivers/CMSIS/Include/core_cm7.h **** /* invalidate D-Cache */ +2294:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2295:Drivers/CMSIS/Include/core_cm7.h **** do { +2296:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2297:Drivers/CMSIS/Include/core_cm7.h **** do { +2298:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | +2299:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +2300:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2301:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2302:Drivers/CMSIS/Include/core_cm7.h **** #endif +2303:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2304:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2305:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2306:Drivers/CMSIS/Include/core_cm7.h **** +2307:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ +2308:Drivers/CMSIS/Include/core_cm7.h **** +2309:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2310:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); + ARM GAS /tmp/ccV0GlXv.s page 70 + + +2311:Drivers/CMSIS/Include/core_cm7.h **** #endif +2312:Drivers/CMSIS/Include/core_cm7.h **** } +2313:Drivers/CMSIS/Include/core_cm7.h **** +2314:Drivers/CMSIS/Include/core_cm7.h **** +2315:Drivers/CMSIS/Include/core_cm7.h **** /** +2316:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable D-Cache +2317:Drivers/CMSIS/Include/core_cm7.h **** \details Turns off D-Cache +2318:Drivers/CMSIS/Include/core_cm7.h **** */ +2319:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableDCache (void) +2320:Drivers/CMSIS/Include/core_cm7.h **** { +2321:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2322:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2323:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2324:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2325:Drivers/CMSIS/Include/core_cm7.h **** +2326:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2327:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2328:Drivers/CMSIS/Include/core_cm7.h **** +2329:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ +2330:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2331:Drivers/CMSIS/Include/core_cm7.h **** +2332:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2333:Drivers/CMSIS/Include/core_cm7.h **** +2334:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */ +2335:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2336:Drivers/CMSIS/Include/core_cm7.h **** do { +2337:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2338:Drivers/CMSIS/Include/core_cm7.h **** do { +2339:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | +2340:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +2341:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2342:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2343:Drivers/CMSIS/Include/core_cm7.h **** #endif +2344:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2345:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2346:Drivers/CMSIS/Include/core_cm7.h **** +2347:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2348:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2349:Drivers/CMSIS/Include/core_cm7.h **** #endif +2350:Drivers/CMSIS/Include/core_cm7.h **** } +2351:Drivers/CMSIS/Include/core_cm7.h **** +2352:Drivers/CMSIS/Include/core_cm7.h **** +2353:Drivers/CMSIS/Include/core_cm7.h **** /** +2354:Drivers/CMSIS/Include/core_cm7.h **** \brief Invalidate D-Cache +2355:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates D-Cache +2356:Drivers/CMSIS/Include/core_cm7.h **** */ +2357:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache (void) +2358:Drivers/CMSIS/Include/core_cm7.h **** { +2359:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2360:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2361:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2362:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2363:Drivers/CMSIS/Include/core_cm7.h **** +2364:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2365:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2366:Drivers/CMSIS/Include/core_cm7.h **** +2367:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; + ARM GAS /tmp/ccV0GlXv.s page 71 + + +2368:Drivers/CMSIS/Include/core_cm7.h **** +2369:Drivers/CMSIS/Include/core_cm7.h **** /* invalidate D-Cache */ +2370:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2371:Drivers/CMSIS/Include/core_cm7.h **** do { +2372:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2373:Drivers/CMSIS/Include/core_cm7.h **** do { +2374:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | +2375:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +2376:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2377:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2378:Drivers/CMSIS/Include/core_cm7.h **** #endif +2379:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2380:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2381:Drivers/CMSIS/Include/core_cm7.h **** +2382:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2383:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2384:Drivers/CMSIS/Include/core_cm7.h **** #endif +2385:Drivers/CMSIS/Include/core_cm7.h **** } +2386:Drivers/CMSIS/Include/core_cm7.h **** +2387:Drivers/CMSIS/Include/core_cm7.h **** +2388:Drivers/CMSIS/Include/core_cm7.h **** /** +2389:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean D-Cache +2390:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans D-Cache +2391:Drivers/CMSIS/Include/core_cm7.h **** */ +2392:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache (void) +2393:Drivers/CMSIS/Include/core_cm7.h **** { +2394:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2396:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2397:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2398:Drivers/CMSIS/Include/core_cm7.h **** +2399:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2400:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2401:Drivers/CMSIS/Include/core_cm7.h **** +2402:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2403:Drivers/CMSIS/Include/core_cm7.h **** +2404:Drivers/CMSIS/Include/core_cm7.h **** /* clean D-Cache */ +2405:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2406:Drivers/CMSIS/Include/core_cm7.h **** do { +2407:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2408:Drivers/CMSIS/Include/core_cm7.h **** do { +2409:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | +2410:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); +2411:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2412:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2413:Drivers/CMSIS/Include/core_cm7.h **** #endif +2414:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2415:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2416:Drivers/CMSIS/Include/core_cm7.h **** +2417:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2418:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2419:Drivers/CMSIS/Include/core_cm7.h **** #endif +2420:Drivers/CMSIS/Include/core_cm7.h **** } +2421:Drivers/CMSIS/Include/core_cm7.h **** +2422:Drivers/CMSIS/Include/core_cm7.h **** +2423:Drivers/CMSIS/Include/core_cm7.h **** /** +2424:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean & Invalidate D-Cache + ARM GAS /tmp/ccV0GlXv.s page 72 + + +2425:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and Invalidates D-Cache +2426:Drivers/CMSIS/Include/core_cm7.h **** */ +2427:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache (void) +2428:Drivers/CMSIS/Include/core_cm7.h **** { +2429:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2431:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2433:Drivers/CMSIS/Include/core_cm7.h **** +2434:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2435:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2436:Drivers/CMSIS/Include/core_cm7.h **** +2437:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2438:Drivers/CMSIS/Include/core_cm7.h **** +2439:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */ +2440:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2441:Drivers/CMSIS/Include/core_cm7.h **** do { +2442:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2443:Drivers/CMSIS/Include/core_cm7.h **** do { +2444:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | +2445:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +2446:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2447:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2448:Drivers/CMSIS/Include/core_cm7.h **** #endif +2449:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2450:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2451:Drivers/CMSIS/Include/core_cm7.h **** +2452:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2453:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2454:Drivers/CMSIS/Include/core_cm7.h **** #endif +2455:Drivers/CMSIS/Include/core_cm7.h **** } +2456:Drivers/CMSIS/Include/core_cm7.h **** +2457:Drivers/CMSIS/Include/core_cm7.h **** +2458:Drivers/CMSIS/Include/core_cm7.h **** /** +2459:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Invalidate by address +2460:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates D-Cache for the given address +2461:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary) +2462:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes) +2463:Drivers/CMSIS/Include/core_cm7.h **** */ +2464:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +2465:Drivers/CMSIS/Include/core_cm7.h **** { +2466:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2467:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize; +2468:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t)addr; +2469:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words ( +2470:Drivers/CMSIS/Include/core_cm7.h **** +2471:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2472:Drivers/CMSIS/Include/core_cm7.h **** +2473:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) { +2474:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCIMVAC = op_addr; +2475:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize; +2476:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize; +2477:Drivers/CMSIS/Include/core_cm7.h **** } +2478:Drivers/CMSIS/Include/core_cm7.h **** +2479:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2480:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2481:Drivers/CMSIS/Include/core_cm7.h **** #endif + ARM GAS /tmp/ccV0GlXv.s page 73 + + +2482:Drivers/CMSIS/Include/core_cm7.h **** } +2483:Drivers/CMSIS/Include/core_cm7.h **** +2484:Drivers/CMSIS/Include/core_cm7.h **** +2485:Drivers/CMSIS/Include/core_cm7.h **** /** +2486:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Clean by address +2487:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans D-Cache for the given address +2488:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary) +2489:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes) +2490:Drivers/CMSIS/Include/core_cm7.h **** */ +2491:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +2492:Drivers/CMSIS/Include/core_cm7.h **** { +2493:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2494:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize; +2495:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr; +2496:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words ( +2497:Drivers/CMSIS/Include/core_cm7.h **** +2498:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2499:Drivers/CMSIS/Include/core_cm7.h **** +2500:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) { +2501:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCMVAC = op_addr; +2502:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize; +2503:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize; +2504:Drivers/CMSIS/Include/core_cm7.h **** } +2505:Drivers/CMSIS/Include/core_cm7.h **** +2506:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2507:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2508:Drivers/CMSIS/Include/core_cm7.h **** #endif +2509:Drivers/CMSIS/Include/core_cm7.h **** } +2510:Drivers/CMSIS/Include/core_cm7.h **** +2511:Drivers/CMSIS/Include/core_cm7.h **** +2512:Drivers/CMSIS/Include/core_cm7.h **** /** +2513:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Clean and Invalidate by address +2514:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and invalidates D_Cache for the given address +2515:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary) +2516:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes) +2517:Drivers/CMSIS/Include/core_cm7.h **** */ +2518:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +2519:Drivers/CMSIS/Include/core_cm7.h **** { +2520:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2521:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize; +2522:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr; +2523:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words ( +2524:Drivers/CMSIS/Include/core_cm7.h **** +2525:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2526:Drivers/CMSIS/Include/core_cm7.h **** +2527:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) { +2528:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCIMVAC = op_addr; +2529:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize; +2530:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize; +2531:Drivers/CMSIS/Include/core_cm7.h **** } +2532:Drivers/CMSIS/Include/core_cm7.h **** +2533:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2534:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2535:Drivers/CMSIS/Include/core_cm7.h **** #endif +2536:Drivers/CMSIS/Include/core_cm7.h **** } +2537:Drivers/CMSIS/Include/core_cm7.h **** +2538:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccV0GlXv.s page 74 + + +2539:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_CacheFunctions */ +2540:Drivers/CMSIS/Include/core_cm7.h **** +2541:Drivers/CMSIS/Include/core_cm7.h **** +2542:Drivers/CMSIS/Include/core_cm7.h **** +2543:Drivers/CMSIS/Include/core_cm7.h **** /* ################################## SysTick function ######################################## +2544:Drivers/CMSIS/Include/core_cm7.h **** /** +2545:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +2546:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +2547:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that configure the System. +2548:Drivers/CMSIS/Include/core_cm7.h **** @{ +2549:Drivers/CMSIS/Include/core_cm7.h **** */ +2550:Drivers/CMSIS/Include/core_cm7.h **** +2551:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +2552:Drivers/CMSIS/Include/core_cm7.h **** +2553:Drivers/CMSIS/Include/core_cm7.h **** /** +2554:Drivers/CMSIS/Include/core_cm7.h **** \brief System Tick Configuration +2555:Drivers/CMSIS/Include/core_cm7.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +2556:Drivers/CMSIS/Include/core_cm7.h **** Counter is in free running mode to generate periodic interrupts. +2557:Drivers/CMSIS/Include/core_cm7.h **** \param [in] ticks Number of ticks between two interrupts. +2558:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Function succeeded. +2559:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Function failed. +2560:Drivers/CMSIS/Include/core_cm7.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the +2561:Drivers/CMSIS/Include/core_cm7.h **** function SysTick_Config is not included. In this case, the file device. +2562:Drivers/CMSIS/Include/core_cm7.h **** must contain a vendor-specific implementation of this function. +2563:Drivers/CMSIS/Include/core_cm7.h **** */ +2564:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + 475 .loc 2 2564 26 view .LVU123 + 476 .LBB83: +2565:Drivers/CMSIS/Include/core_cm7.h **** { +2566:Drivers/CMSIS/Include/core_cm7.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 477 .loc 2 2566 3 view .LVU124 + 478 .loc 2 2566 14 is_stmt 0 view .LVU125 + 479 0000 0138 subs r0, r0, #1 + 480 .LVL32: + 481 .loc 2 2566 6 view .LVU126 + 482 0002 B0F1807F cmp r0, #16777216 + 483 0006 0BD2 bcs .L26 +2567:Drivers/CMSIS/Include/core_cm7.h **** { +2568:Drivers/CMSIS/Include/core_cm7.h **** return (1UL); /* Reload value impossible */ +2569:Drivers/CMSIS/Include/core_cm7.h **** } +2570:Drivers/CMSIS/Include/core_cm7.h **** +2571:Drivers/CMSIS/Include/core_cm7.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 484 .loc 2 2571 3 is_stmt 1 view .LVU127 + 485 .loc 2 2571 18 is_stmt 0 view .LVU128 + 486 0008 4FF0E023 mov r3, #-536813568 + 487 000c 5861 str r0, [r3, #20] +2572:Drivers/CMSIS/Include/core_cm7.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int + 488 .loc 2 2572 3 is_stmt 1 view .LVU129 + 489 .LVL33: + 490 .LBB84: + 491 .LBI84: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 492 .loc 2 2024 22 view .LVU130 + 493 .LBB85: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 494 .loc 2 2026 3 view .LVU131 +2032:Drivers/CMSIS/Include/core_cm7.h **** } + ARM GAS /tmp/ccV0GlXv.s page 75 + + + 495 .loc 2 2032 5 view .LVU132 +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 496 .loc 2 2032 47 is_stmt 0 view .LVU133 + 497 000e 054A ldr r2, .L27 + 498 0010 F021 movs r1, #240 + 499 0012 82F82310 strb r1, [r2, #35] + 500 .LVL34: +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 501 .loc 2 2032 47 view .LVU134 + 502 .LBE85: + 503 .LBE84: +2573:Drivers/CMSIS/Include/core_cm7.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val + 504 .loc 2 2573 3 is_stmt 1 view .LVU135 + 505 .loc 2 2573 18 is_stmt 0 view .LVU136 + 506 0016 0020 movs r0, #0 + 507 .LVL35: + 508 .loc 2 2573 18 view .LVU137 + 509 0018 9861 str r0, [r3, #24] +2574:Drivers/CMSIS/Include/core_cm7.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 510 .loc 2 2574 3 is_stmt 1 view .LVU138 + 511 .loc 2 2574 18 is_stmt 0 view .LVU139 + 512 001a 0722 movs r2, #7 + 513 001c 1A61 str r2, [r3, #16] +2575:Drivers/CMSIS/Include/core_cm7.h **** SysTick_CTRL_TICKINT_Msk | +2576:Drivers/CMSIS/Include/core_cm7.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi +2577:Drivers/CMSIS/Include/core_cm7.h **** return (0UL); /* Function successful */ + 514 .loc 2 2577 3 is_stmt 1 view .LVU140 + 515 .loc 2 2577 10 is_stmt 0 view .LVU141 + 516 001e 7047 bx lr + 517 .L26: +2568:Drivers/CMSIS/Include/core_cm7.h **** } + 518 .loc 2 2568 12 view .LVU142 + 519 0020 0120 movs r0, #1 + 520 .LVL36: +2568:Drivers/CMSIS/Include/core_cm7.h **** } + 521 .loc 2 2568 12 view .LVU143 + 522 .LBE83: + 523 .LBE82: + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 524 .loc 1 232 1 view .LVU144 + 525 0022 7047 bx lr + 526 .L28: + 527 .align 2 + 528 .L27: + 529 0024 00ED00E0 .word -536810240 + 530 .cfi_endproc + 531 .LFE146: + 533 .section .text.HAL_MPU_Disable,"ax",%progbits + 534 .align 1 + 535 .global HAL_MPU_Disable + 536 .syntax unified + 537 .thumb + 538 .thumb_func + 539 .fpu fpv5-d16 + 541 HAL_MPU_Disable: + 542 .LFB147: + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + ARM GAS /tmp/ccV0GlXv.s page 76 + + + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @} + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Cortex control functions + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @verbatim + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ============================================================================== + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ##### Peripheral Control functions ##### + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ============================================================================== + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** [..] + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** @endverbatim + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @{ + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #if (__MPU_PRESENT == 1) + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Disables the MPU + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_MPU_Disable(void) + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 543 .loc 1 258 1 is_stmt 1 view -0 + 544 .cfi_startproc + 545 @ args = 0, pretend = 0, frame = 0 + 546 @ frame_needed = 0, uses_anonymous_args = 0 + 547 @ link register save eliminated. + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Make sure outstanding transfers are done */ + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __DMB(); + 548 .loc 1 260 3 view .LVU146 + 549 .LBB86: + 550 .LBI86: + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 551 .loc 3 888 27 view .LVU147 + 552 .LBB87: + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 553 .loc 3 890 3 view .LVU148 + 554 .syntax unified + 555 @ 890 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 556 0000 BFF35F8F dmb 0xF + 557 @ 0 "" 2 + 558 .thumb + 559 .syntax unified + 560 .LBE87: + 561 .LBE86: + ARM GAS /tmp/ccV0GlXv.s page 77 + + + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Disable fault exceptions */ + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + 562 .loc 1 263 3 view .LVU149 + 563 .loc 1 263 14 is_stmt 0 view .LVU150 + 564 0004 044B ldr r3, .L30 + 565 0006 5A6A ldr r2, [r3, #36] + 566 0008 22F48032 bic r2, r2, #65536 + 567 000c 5A62 str r2, [r3, #36] + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/ + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->CTRL = 0; + 568 .loc 1 266 3 is_stmt 1 view .LVU151 + 569 .loc 1 266 13 is_stmt 0 view .LVU152 + 570 000e 0022 movs r2, #0 + 571 0010 C3F89420 str r2, [r3, #148] + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 572 .loc 1 267 1 view .LVU153 + 573 0014 7047 bx lr + 574 .L31: + 575 0016 00BF .align 2 + 576 .L30: + 577 0018 00ED00E0 .word -536810240 + 578 .cfi_endproc + 579 .LFE147: + 581 .section .text.HAL_MPU_Enable,"ax",%progbits + 582 .align 1 + 583 .global HAL_MPU_Enable + 584 .syntax unified + 585 .thumb + 586 .thumb_func + 587 .fpu fpv5-d16 + 589 HAL_MPU_Enable: + 590 .LVL37: + 591 .LFB148: + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Enables the MPU + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault, + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values: + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 592 .loc 1 281 1 is_stmt 1 view -0 + 593 .cfi_startproc + 594 @ args = 0, pretend = 0, frame = 0 + 595 @ frame_needed = 0, uses_anonymous_args = 0 + 596 @ link register save eliminated. + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Enable the MPU */ + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + 597 .loc 1 283 3 view .LVU155 + ARM GAS /tmp/ccV0GlXv.s page 78 + + + 598 .loc 1 283 27 is_stmt 0 view .LVU156 + 599 0000 40F00100 orr r0, r0, #1 + 600 .LVL38: + 601 .loc 1 283 13 view .LVU157 + 602 0004 054B ldr r3, .L33 + 603 0006 C3F89400 str r0, [r3, #148] + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Enable fault exceptions */ + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + 604 .loc 1 286 3 is_stmt 1 view .LVU158 + 605 .loc 1 286 14 is_stmt 0 view .LVU159 + 606 000a 5A6A ldr r2, [r3, #36] + 607 000c 42F48032 orr r2, r2, #65536 + 608 0010 5A62 str r2, [r3, #36] + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Ensure MPU setting take effects */ + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __DSB(); + 609 .loc 1 289 3 is_stmt 1 view .LVU160 + 610 .LBB88: + 611 .LBI88: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 612 .loc 3 877 27 view .LVU161 + 613 .LBB89: + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 614 .loc 3 879 3 view .LVU162 + 615 .syntax unified + 616 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 617 0012 BFF34F8F dsb 0xF + 618 @ 0 "" 2 + 619 .thumb + 620 .syntax unified + 621 .LBE89: + 622 .LBE88: + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __ISB(); + 623 .loc 1 290 3 view .LVU163 + 624 .LBB90: + 625 .LBI90: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 626 .loc 3 866 27 view .LVU164 + 627 .LBB91: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 628 .loc 3 868 3 view .LVU165 + 629 .syntax unified + 630 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 631 0016 BFF36F8F isb 0xF + 632 @ 0 "" 2 + 633 .thumb + 634 .syntax unified + 635 .LBE91: + 636 .LBE90: + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 637 .loc 1 291 1 is_stmt 0 view .LVU166 + 638 001a 7047 bx lr + 639 .L34: + 640 .align 2 + 641 .L33: + 642 001c 00ED00E0 .word -536810240 + ARM GAS /tmp/ccV0GlXv.s page 79 + + + 643 .cfi_endproc + 644 .LFE148: + 646 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits + 647 .align 1 + 648 .global HAL_MPU_ConfigRegion + 649 .syntax unified + 650 .thumb + 651 .thumb_func + 652 .fpu fpv5-d16 + 654 HAL_MPU_ConfigRegion: + 655 .LVL39: + 656 .LFB149: + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected. + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * the initialization and configuration information. + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 657 .loc 1 299 1 is_stmt 1 view -0 + 658 .cfi_startproc + 659 @ args = 0, pretend = 0, frame = 0 + 660 @ frame_needed = 0, uses_anonymous_args = 0 + 661 @ link register save eliminated. + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + 662 .loc 1 301 3 view .LVU168 + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + 663 .loc 1 302 3 view .LVU169 + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Set the Region number */ + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; + 664 .loc 1 305 3 view .LVU170 + 665 .loc 1 305 22 is_stmt 0 view .LVU171 + 666 0000 4278 ldrb r2, [r0, #1] @ zero_extendqisi2 + 667 .loc 1 305 12 view .LVU172 + 668 0002 164B ldr r3, .L38 + 669 0004 C3F89820 str r2, [r3, #152] + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** if ((MPU_Init->Enable) != 0UL) + 670 .loc 1 307 3 is_stmt 1 view .LVU173 + 671 .loc 1 307 16 is_stmt 0 view .LVU174 + 672 0008 0378 ldrb r3, [r0] @ zero_extendqisi2 + 673 .loc 1 307 6 view .LVU175 + 674 000a FBB1 cbz r3, .L36 + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + 675 .loc 1 310 5 is_stmt 1 view .LVU176 + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + 676 .loc 1 311 5 view .LVU177 + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + 677 .loc 1 312 5 view .LVU178 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + 678 .loc 1 313 5 view .LVU179 + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + ARM GAS /tmp/ccV0GlXv.s page 80 + + + 679 .loc 1 314 5 view .LVU180 + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + 680 .loc 1 315 5 view .LVU181 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + 681 .loc 1 316 5 view .LVU182 + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + 682 .loc 1 317 5 view .LVU183 + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; + 683 .loc 1 319 5 view .LVU184 + 684 .loc 1 319 25 is_stmt 0 view .LVU185 + 685 000c 4368 ldr r3, [r0, #4] + 686 .loc 1 319 15 view .LVU186 + 687 000e 134A ldr r2, .L38 + 688 0010 C2F89C30 str r3, [r2, #156] + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 689 .loc 1 320 5 is_stmt 1 view .LVU187 + 690 .loc 1 320 36 is_stmt 0 view .LVU188 + 691 0014 017B ldrb r1, [r0, #12] @ zero_extendqisi2 + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 692 .loc 1 321 36 view .LVU189 + 693 0016 C37A ldrb r3, [r0, #11] @ zero_extendqisi2 + 694 .loc 1 321 62 view .LVU190 + 695 0018 1B06 lsls r3, r3, #24 + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 696 .loc 1 320 84 view .LVU191 + 697 001a 43EA0173 orr r3, r3, r1, lsl #28 + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 698 .loc 1 322 36 view .LVU192 + 699 001e 817A ldrb r1, [r0, #10] @ zero_extendqisi2 + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 700 .loc 1 321 84 view .LVU193 + 701 0020 43EAC143 orr r3, r3, r1, lsl #19 + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 702 .loc 1 323 36 view .LVU194 + 703 0024 417B ldrb r1, [r0, #13] @ zero_extendqisi2 + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 704 .loc 1 322 84 view .LVU195 + 705 0026 43EA8143 orr r3, r3, r1, lsl #18 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 706 .loc 1 324 36 view .LVU196 + 707 002a 817B ldrb r1, [r0, #14] @ zero_extendqisi2 + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 708 .loc 1 323 84 view .LVU197 + 709 002c 43EA4143 orr r3, r3, r1, lsl #17 + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 710 .loc 1 325 36 view .LVU198 + 711 0030 C17B ldrb r1, [r0, #15] @ zero_extendqisi2 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 712 .loc 1 324 84 view .LVU199 + 713 0032 43EA0143 orr r3, r3, r1, lsl #16 + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 714 .loc 1 326 36 view .LVU200 + 715 0036 417A ldrb r1, [r0, #9] @ zero_extendqisi2 + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 716 .loc 1 325 84 view .LVU201 + 717 0038 43EA0123 orr r3, r3, r1, lsl #8 + ARM GAS /tmp/ccV0GlXv.s page 81 + + + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 718 .loc 1 327 36 view .LVU202 + 719 003c 017A ldrb r1, [r0, #8] @ zero_extendqisi2 + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 720 .loc 1 326 84 view .LVU203 + 721 003e 43EA4103 orr r3, r3, r1, lsl #1 + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 722 .loc 1 328 36 view .LVU204 + 723 0042 0178 ldrb r1, [r0] @ zero_extendqisi2 + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 724 .loc 1 327 84 view .LVU205 + 725 0044 0B43 orrs r3, r3, r1 + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 726 .loc 1 320 15 view .LVU206 + 727 0046 C2F8A030 str r3, [r2, #160] + 728 004a 7047 bx lr + 729 .L36: + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** else + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RBAR = 0x00; + 730 .loc 1 332 5 is_stmt 1 view .LVU207 + 731 .loc 1 332 15 is_stmt 0 view .LVU208 + 732 004c 034B ldr r3, .L38 + 733 004e 0022 movs r2, #0 + 734 0050 C3F89C20 str r2, [r3, #156] + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** MPU->RASR = 0x00; + 735 .loc 1 333 5 is_stmt 1 view .LVU209 + 736 .loc 1 333 15 is_stmt 0 view .LVU210 + 737 0054 C3F8A020 str r2, [r3, #160] + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 738 .loc 1 335 1 view .LVU211 + 739 0058 7047 bx lr + 740 .L39: + 741 005a 00BF .align 2 + 742 .L38: + 743 005c 00ED00E0 .word -536810240 + 744 .cfi_endproc + 745 .LFE149: + 747 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits + 748 .align 1 + 749 .global HAL_NVIC_GetPriorityGrouping + 750 .syntax unified + 751 .thumb + 752 .thumb_func + 753 .fpu fpv5-d16 + 755 HAL_NVIC_GetPriorityGrouping: + 756 .LFB150: + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #endif /* __MPU_PRESENT */ + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + ARM GAS /tmp/ccV0GlXv.s page 82 + + + 757 .loc 1 343 1 is_stmt 1 view -0 + 758 .cfi_startproc + 759 @ args = 0, pretend = 0, frame = 0 + 760 @ frame_needed = 0, uses_anonymous_args = 0 + 761 @ link register save eliminated. + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); + 762 .loc 1 345 3 view .LVU213 + 763 .LBB92: + 764 .LBI92: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 765 .loc 2 1884 26 view .LVU214 + 766 .LBB93: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 767 .loc 2 1886 3 view .LVU215 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 768 .loc 2 1886 26 is_stmt 0 view .LVU216 + 769 0000 024B ldr r3, .L41 + 770 0002 D868 ldr r0, [r3, #12] + 771 .LBE93: + 772 .LBE92: + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 773 .loc 1 346 1 view .LVU217 + 774 0004 C0F30220 ubfx r0, r0, #8, #3 + 775 0008 7047 bx lr + 776 .L42: + 777 000a 00BF .align 2 + 778 .L41: + 779 000c 00ED00E0 .word -536810240 + 780 .cfi_endproc + 781 .LFE150: + 783 .section .text.HAL_NVIC_GetPriority,"ax",%progbits + 784 .align 1 + 785 .global HAL_NVIC_GetPriority + 786 .syntax unified + 787 .thumb + 788 .thumb_func + 789 .fpu fpv5-d16 + 791 HAL_NVIC_GetPriority: + 792 .LVL40: + 793 .LFB151: + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param PriorityGroup the priority grouping bits length. + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values: + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 4 bits for subpriority + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 3 bits for subpriority + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 2 bits for subpriority + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 1 bits for subpriority + ARM GAS /tmp/ccV0GlXv.s page 83 + + + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * 0 bits for subpriority + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0). + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3 + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 794 .loc 1 370 1 is_stmt 1 view -0 + 795 .cfi_startproc + 796 @ args = 0, pretend = 0, frame = 0 + 797 @ frame_needed = 0, uses_anonymous_args = 0 + 798 .loc 1 370 1 is_stmt 0 view .LVU219 + 799 0000 10B5 push {r4, lr} + 800 .LCFI1: + 801 .cfi_def_cfa_offset 8 + 802 .cfi_offset 4, -8 + 803 .cfi_offset 14, -4 + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 804 .loc 1 372 3 is_stmt 1 view .LVU220 + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); + 805 .loc 1 374 3 view .LVU221 + 806 .LVL41: + 807 .LBB98: + 808 .LBI98: +2046:Drivers/CMSIS/Include/core_cm7.h **** { + 809 .loc 2 2046 26 view .LVU222 + 810 .LBB99: +2049:Drivers/CMSIS/Include/core_cm7.h **** { + 811 .loc 2 2049 3 view .LVU223 +2049:Drivers/CMSIS/Include/core_cm7.h **** { + 812 .loc 2 2049 6 is_stmt 0 view .LVU224 + 813 0002 0028 cmp r0, #0 + 814 .LVL42: +2049:Drivers/CMSIS/Include/core_cm7.h **** { + 815 .loc 2 2049 6 view .LVU225 + 816 0004 1EDB blt .L44 +2051:Drivers/CMSIS/Include/core_cm7.h **** } + 817 .loc 2 2051 5 is_stmt 1 view .LVU226 +2051:Drivers/CMSIS/Include/core_cm7.h **** } + 818 .loc 2 2051 31 is_stmt 0 view .LVU227 + 819 0006 134C ldr r4, .L49 + 820 0008 205C ldrb r0, [r4, r0] @ zero_extendqisi2 +2051:Drivers/CMSIS/Include/core_cm7.h **** } + 821 .loc 2 2051 65 view .LVU228 + 822 000a 0009 lsrs r0, r0, #4 + 823 .L45: + 824 .LVL43: +2051:Drivers/CMSIS/Include/core_cm7.h **** } + 825 .loc 2 2051 65 view .LVU229 + 826 .LBE99: + 827 .LBE98: + 828 .LBB101: + 829 .LBI101: +2098:Drivers/CMSIS/Include/core_cm7.h **** { + ARM GAS /tmp/ccV0GlXv.s page 84 + + + 830 .loc 2 2098 22 is_stmt 1 view .LVU230 + 831 .LBB102: +2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; + 832 .loc 2 2100 3 view .LVU231 +2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; + 833 .loc 2 2100 12 is_stmt 0 view .LVU232 + 834 000c 01F00701 and r1, r1, #7 + 835 .LVL44: +2101:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; + 836 .loc 2 2101 3 is_stmt 1 view .LVU233 +2102:Drivers/CMSIS/Include/core_cm7.h **** + 837 .loc 2 2102 3 view .LVU234 +2104:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 838 .loc 2 2104 3 view .LVU235 +2104:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 839 .loc 2 2104 31 is_stmt 0 view .LVU236 + 840 0010 C1F1070C rsb ip, r1, #7 +2104:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 841 .loc 2 2104 23 view .LVU237 + 842 0014 BCF1040F cmp ip, #4 + 843 0018 28BF it cs + 844 001a 4FF0040C movcs ip, #4 + 845 .LVL45: +2105:Drivers/CMSIS/Include/core_cm7.h **** + 846 .loc 2 2105 3 is_stmt 1 view .LVU238 +2105:Drivers/CMSIS/Include/core_cm7.h **** + 847 .loc 2 2105 44 is_stmt 0 view .LVU239 + 848 001e 0C1D adds r4, r1, #4 +2105:Drivers/CMSIS/Include/core_cm7.h **** + 849 .loc 2 2105 109 view .LVU240 + 850 0020 062C cmp r4, #6 + 851 0022 15D9 bls .L47 + 852 0024 0339 subs r1, r1, #3 + 853 .LVL46: + 854 .L46: +2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 855 .loc 2 2107 3 is_stmt 1 view .LVU241 +2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 856 .loc 2 2107 33 is_stmt 0 view .LVU242 + 857 0026 20FA01F4 lsr r4, r0, r1 + 858 .LVL47: +2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 859 .loc 2 2107 53 view .LVU243 + 860 002a 4FF0FF3E mov lr, #-1 + 861 002e 0EFA0CFC lsl ip, lr, ip + 862 .LVL48: +2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 863 .loc 2 2107 53 view .LVU244 + 864 0032 24EA0C04 bic r4, r4, ip +2107:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 865 .loc 2 2107 21 view .LVU245 + 866 0036 1460 str r4, [r2] +2108:Drivers/CMSIS/Include/core_cm7.h **** } + 867 .loc 2 2108 3 is_stmt 1 view .LVU246 +2108:Drivers/CMSIS/Include/core_cm7.h **** } + 868 .loc 2 2108 53 is_stmt 0 view .LVU247 + 869 0038 0EFA01F1 lsl r1, lr, r1 + ARM GAS /tmp/ccV0GlXv.s page 85 + + + 870 .LVL49: +2108:Drivers/CMSIS/Include/core_cm7.h **** } + 871 .loc 2 2108 53 view .LVU248 + 872 003c 20EA0100 bic r0, r0, r1 + 873 .LVL50: +2108:Drivers/CMSIS/Include/core_cm7.h **** } + 874 .loc 2 2108 21 view .LVU249 + 875 0040 1860 str r0, [r3] + 876 .LVL51: +2108:Drivers/CMSIS/Include/core_cm7.h **** } + 877 .loc 2 2108 21 view .LVU250 + 878 .LBE102: + 879 .LBE101: + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 880 .loc 1 375 1 view .LVU251 + 881 0042 10BD pop {r4, pc} + 882 .LVL52: + 883 .L44: + 884 .LBB104: + 885 .LBB100: +2055:Drivers/CMSIS/Include/core_cm7.h **** } + 886 .loc 2 2055 5 is_stmt 1 view .LVU252 +2055:Drivers/CMSIS/Include/core_cm7.h **** } + 887 .loc 2 2055 51 is_stmt 0 view .LVU253 + 888 0044 00F00F00 and r0, r0, #15 +2055:Drivers/CMSIS/Include/core_cm7.h **** } + 889 .loc 2 2055 32 view .LVU254 + 890 0048 034C ldr r4, .L49+4 + 891 004a 205C ldrb r0, [r4, r0] @ zero_extendqisi2 +2055:Drivers/CMSIS/Include/core_cm7.h **** } + 892 .loc 2 2055 65 view .LVU255 + 893 004c 0009 lsrs r0, r0, #4 + 894 004e DDE7 b .L45 + 895 .LVL53: + 896 .L47: +2055:Drivers/CMSIS/Include/core_cm7.h **** } + 897 .loc 2 2055 65 view .LVU256 + 898 .LBE100: + 899 .LBE104: + 900 .LBB105: + 901 .LBB103: +2105:Drivers/CMSIS/Include/core_cm7.h **** + 902 .loc 2 2105 109 view .LVU257 + 903 0050 0021 movs r1, #0 + 904 .LVL54: +2105:Drivers/CMSIS/Include/core_cm7.h **** + 905 .loc 2 2105 109 view .LVU258 + 906 0052 E8E7 b .L46 + 907 .L50: + 908 .align 2 + 909 .L49: + 910 0054 00E400E0 .word -536812544 + 911 0058 14ED00E0 .word -536810220 + 912 .LBE103: + 913 .LBE105: + 914 .cfi_endproc + 915 .LFE151: + ARM GAS /tmp/ccV0GlXv.s page 86 + + + 917 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits + 918 .align 1 + 919 .global HAL_NVIC_SetPendingIRQ + 920 .syntax unified + 921 .thumb + 922 .thumb_func + 923 .fpu fpv5-d16 + 925 HAL_NVIC_SetPendingIRQ: + 926 .LVL55: + 927 .LFB152: + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 928 .loc 1 385 1 is_stmt 1 view -0 + 929 .cfi_startproc + 930 @ args = 0, pretend = 0, frame = 0 + 931 @ frame_needed = 0, uses_anonymous_args = 0 + 932 @ link register save eliminated. + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 933 .loc 1 387 3 view .LVU260 + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Set interrupt pending */ + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); + 934 .loc 1 390 3 view .LVU261 + 935 .LBB106: + 936 .LBI106: +1970:Drivers/CMSIS/Include/core_cm7.h **** { + 937 .loc 2 1970 22 view .LVU262 + 938 .LBB107: +1972:Drivers/CMSIS/Include/core_cm7.h **** { + 939 .loc 2 1972 3 view .LVU263 +1972:Drivers/CMSIS/Include/core_cm7.h **** { + 940 .loc 2 1972 6 is_stmt 0 view .LVU264 + 941 0000 0028 cmp r0, #0 + 942 .LVL56: +1972:Drivers/CMSIS/Include/core_cm7.h **** { + 943 .loc 2 1972 6 view .LVU265 + 944 0002 08DB blt .L51 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 945 .loc 2 1974 5 is_stmt 1 view .LVU266 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 946 .loc 2 1974 81 is_stmt 0 view .LVU267 + 947 0004 00F01F02 and r2, r0, #31 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 948 .loc 2 1974 34 view .LVU268 + 949 0008 4009 lsrs r0, r0, #5 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 950 .loc 2 1974 45 view .LVU269 + 951 000a 0123 movs r3, #1 + ARM GAS /tmp/ccV0GlXv.s page 87 + + + 952 000c 9340 lsls r3, r3, r2 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 953 .loc 2 1974 43 view .LVU270 + 954 000e 4030 adds r0, r0, #64 + 955 0010 014A ldr r2, .L53 + 956 0012 42F82030 str r3, [r2, r0, lsl #2] + 957 .LVL57: + 958 .L51: +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 959 .loc 2 1974 43 view .LVU271 + 960 .LBE107: + 961 .LBE106: + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 962 .loc 1 391 1 view .LVU272 + 963 0016 7047 bx lr + 964 .L54: + 965 .align 2 + 966 .L53: + 967 0018 00E100E0 .word -536813312 + 968 .cfi_endproc + 969 .LFE152: + 971 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits + 972 .align 1 + 973 .global HAL_NVIC_GetPendingIRQ + 974 .syntax unified + 975 .thumb + 976 .thumb_func + 977 .fpu fpv5-d16 + 979 HAL_NVIC_GetPendingIRQ: + 980 .LVL58: + 981 .LFB153: + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval status - 0 Interrupt status is not pending. + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 982 .loc 1 403 1 is_stmt 1 view -0 + 983 .cfi_startproc + 984 @ args = 0, pretend = 0, frame = 0 + 985 @ frame_needed = 0, uses_anonymous_args = 0 + 986 @ link register save eliminated. + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 987 .loc 1 405 3 view .LVU274 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Return 1 if pending else 0 */ + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); + 988 .loc 1 408 3 view .LVU275 + 989 .LBB108: + 990 .LBI108: + ARM GAS /tmp/ccV0GlXv.s page 88 + + +1951:Drivers/CMSIS/Include/core_cm7.h **** { + 991 .loc 2 1951 26 view .LVU276 + 992 .LBB109: +1953:Drivers/CMSIS/Include/core_cm7.h **** { + 993 .loc 2 1953 3 view .LVU277 +1953:Drivers/CMSIS/Include/core_cm7.h **** { + 994 .loc 2 1953 6 is_stmt 0 view .LVU278 + 995 0000 0028 cmp r0, #0 + 996 .LVL59: +1953:Drivers/CMSIS/Include/core_cm7.h **** { + 997 .loc 2 1953 6 view .LVU279 + 998 0002 0BDB blt .L57 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 999 .loc 2 1955 5 is_stmt 1 view .LVU280 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1000 .loc 2 1955 54 is_stmt 0 view .LVU281 + 1001 0004 4309 lsrs r3, r0, #5 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1002 .loc 2 1955 35 view .LVU282 + 1003 0006 4033 adds r3, r3, #64 + 1004 0008 054A ldr r2, .L58 + 1005 000a 52F82330 ldr r3, [r2, r3, lsl #2] +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1006 .loc 2 1955 91 view .LVU283 + 1007 000e 00F01F00 and r0, r0, #31 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1008 .loc 2 1955 103 view .LVU284 + 1009 0012 23FA00F0 lsr r0, r3, r0 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1010 .loc 2 1955 12 view .LVU285 + 1011 0016 00F00100 and r0, r0, #1 + 1012 001a 7047 bx lr + 1013 .L57: +1959:Drivers/CMSIS/Include/core_cm7.h **** } + 1014 .loc 2 1959 11 view .LVU286 + 1015 001c 0020 movs r0, #0 + 1016 .LVL60: +1959:Drivers/CMSIS/Include/core_cm7.h **** } + 1017 .loc 2 1959 11 view .LVU287 + 1018 .LBE109: + 1019 .LBE108: + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1020 .loc 1 409 1 view .LVU288 + 1021 001e 7047 bx lr + 1022 .L59: + 1023 .align 2 + 1024 .L58: + 1025 0020 00E100E0 .word -536813312 + 1026 .cfi_endproc + 1027 .LFE153: + 1029 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits + 1030 .align 1 + 1031 .global HAL_NVIC_ClearPendingIRQ + 1032 .syntax unified + 1033 .thumb + 1034 .thumb_func + 1035 .fpu fpv5-d16 + ARM GAS /tmp/ccV0GlXv.s page 89 + + + 1037 HAL_NVIC_ClearPendingIRQ: + 1038 .LVL61: + 1039 .LFB154: + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 1040 .loc 1 419 1 is_stmt 1 view -0 + 1041 .cfi_startproc + 1042 @ args = 0, pretend = 0, frame = 0 + 1043 @ frame_needed = 0, uses_anonymous_args = 0 + 1044 @ link register save eliminated. + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 1045 .loc 1 421 3 view .LVU290 + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Clear pending interrupt */ + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); + 1046 .loc 1 424 3 view .LVU291 + 1047 .LBB110: + 1048 .LBI110: +1985:Drivers/CMSIS/Include/core_cm7.h **** { + 1049 .loc 2 1985 22 view .LVU292 + 1050 .LBB111: +1987:Drivers/CMSIS/Include/core_cm7.h **** { + 1051 .loc 2 1987 3 view .LVU293 +1987:Drivers/CMSIS/Include/core_cm7.h **** { + 1052 .loc 2 1987 6 is_stmt 0 view .LVU294 + 1053 0000 0028 cmp r0, #0 + 1054 .LVL62: +1987:Drivers/CMSIS/Include/core_cm7.h **** { + 1055 .loc 2 1987 6 view .LVU295 + 1056 0002 08DB blt .L60 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1057 .loc 2 1989 5 is_stmt 1 view .LVU296 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1058 .loc 2 1989 81 is_stmt 0 view .LVU297 + 1059 0004 00F01F02 and r2, r0, #31 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1060 .loc 2 1989 34 view .LVU298 + 1061 0008 4009 lsrs r0, r0, #5 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1062 .loc 2 1989 45 view .LVU299 + 1063 000a 0123 movs r3, #1 + 1064 000c 9340 lsls r3, r3, r2 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1065 .loc 2 1989 43 view .LVU300 + 1066 000e 6030 adds r0, r0, #96 + 1067 0010 014A ldr r2, .L62 + 1068 0012 42F82030 str r3, [r2, r0, lsl #2] + 1069 .LVL63: + ARM GAS /tmp/ccV0GlXv.s page 90 + + + 1070 .L60: +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1071 .loc 2 1989 43 view .LVU301 + 1072 .LBE111: + 1073 .LBE110: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1074 .loc 1 425 1 view .LVU302 + 1075 0016 7047 bx lr + 1076 .L63: + 1077 .align 2 + 1078 .L62: + 1079 0018 00E100E0 .word -536813312 + 1080 .cfi_endproc + 1081 .LFE154: + 1083 .section .text.HAL_NVIC_GetActive,"ax",%progbits + 1084 .align 1 + 1085 .global HAL_NVIC_GetActive + 1086 .syntax unified + 1087 .thumb + 1088 .thumb_func + 1089 .fpu fpv5-d16 + 1091 HAL_NVIC_GetActive: + 1092 .LVL64: + 1093 .LFB155: + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param IRQn External interrupt number + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval status - 0 Interrupt status is not pending. + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 1094 .loc 1 436 1 is_stmt 1 view -0 + 1095 .cfi_startproc + 1096 @ args = 0, pretend = 0, frame = 0 + 1097 @ frame_needed = 0, uses_anonymous_args = 0 + 1098 @ link register save eliminated. + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 1099 .loc 1 438 3 view .LVU304 + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Return 1 if active else 0 */ + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return NVIC_GetActive(IRQn); + 1100 .loc 1 441 3 view .LVU305 + 1101 .LBB112: + 1102 .LBI112: +2002:Drivers/CMSIS/Include/core_cm7.h **** { + 1103 .loc 2 2002 26 view .LVU306 + 1104 .LBB113: +2004:Drivers/CMSIS/Include/core_cm7.h **** { + 1105 .loc 2 2004 3 view .LVU307 +2004:Drivers/CMSIS/Include/core_cm7.h **** { + 1106 .loc 2 2004 6 is_stmt 0 view .LVU308 + 1107 0000 0028 cmp r0, #0 + ARM GAS /tmp/ccV0GlXv.s page 91 + + + 1108 .LVL65: +2004:Drivers/CMSIS/Include/core_cm7.h **** { + 1109 .loc 2 2004 6 view .LVU309 + 1110 0002 0BDB blt .L66 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1111 .loc 2 2006 5 is_stmt 1 view .LVU310 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1112 .loc 2 2006 54 is_stmt 0 view .LVU311 + 1113 0004 4309 lsrs r3, r0, #5 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1114 .loc 2 2006 35 view .LVU312 + 1115 0006 8033 adds r3, r3, #128 + 1116 0008 054A ldr r2, .L67 + 1117 000a 52F82330 ldr r3, [r2, r3, lsl #2] +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1118 .loc 2 2006 91 view .LVU313 + 1119 000e 00F01F00 and r0, r0, #31 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1120 .loc 2 2006 103 view .LVU314 + 1121 0012 23FA00F0 lsr r0, r3, r0 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1122 .loc 2 2006 12 view .LVU315 + 1123 0016 00F00100 and r0, r0, #1 + 1124 001a 7047 bx lr + 1125 .L66: +2010:Drivers/CMSIS/Include/core_cm7.h **** } + 1126 .loc 2 2010 11 view .LVU316 + 1127 001c 0020 movs r0, #0 + 1128 .LVL66: +2010:Drivers/CMSIS/Include/core_cm7.h **** } + 1129 .loc 2 2010 11 view .LVU317 + 1130 .LBE113: + 1131 .LBE112: + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1132 .loc 1 442 1 view .LVU318 + 1133 001e 7047 bx lr + 1134 .L68: + 1135 .align 2 + 1136 .L67: + 1137 0020 00E100E0 .word -536813312 + 1138 .cfi_endproc + 1139 .LFE155: + 1141 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits + 1142 .align 1 + 1143 .global HAL_SYSTICK_CLKSourceConfig + 1144 .syntax unified + 1145 .thumb + 1146 .thumb_func + 1147 .fpu fpv5-d16 + 1149 HAL_SYSTICK_CLKSourceConfig: + 1150 .LVL67: + 1151 .LFB156: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Configures the SysTick clock source. + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * This parameter can be one of the following values: + ARM GAS /tmp/ccV0GlXv.s page 92 + + + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 1152 .loc 1 453 1 is_stmt 1 view -0 + 1153 .cfi_startproc + 1154 @ args = 0, pretend = 0, frame = 0 + 1155 @ frame_needed = 0, uses_anonymous_args = 0 + 1156 @ link register save eliminated. + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* Check the parameters */ + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + 1157 .loc 1 455 3 view .LVU320 + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 1158 .loc 1 456 3 view .LVU321 + 1159 .loc 1 456 6 is_stmt 0 view .LVU322 + 1160 0000 0428 cmp r0, #4 + 1161 0002 06D0 beq .L72 + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** else + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 1162 .loc 1 462 5 is_stmt 1 view .LVU323 + 1163 .loc 1 462 19 is_stmt 0 view .LVU324 + 1164 0004 4FF0E022 mov r2, #-536813568 + 1165 0008 1369 ldr r3, [r2, #16] + 1166 000a 23F00403 bic r3, r3, #4 + 1167 000e 1361 str r3, [r2, #16] + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1168 .loc 1 464 1 view .LVU325 + 1169 0010 7047 bx lr + 1170 .L72: + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1171 .loc 1 458 5 is_stmt 1 view .LVU326 + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1172 .loc 1 458 19 is_stmt 0 view .LVU327 + 1173 0012 4FF0E022 mov r2, #-536813568 + 1174 0016 1369 ldr r3, [r2, #16] + 1175 0018 43F00403 orr r3, r3, #4 + 1176 001c 1361 str r3, [r2, #16] + 1177 001e 7047 bx lr + 1178 .cfi_endproc + 1179 .LFE156: + 1181 .section .text.HAL_SYSTICK_Callback,"ax",%progbits + 1182 .align 1 + 1183 .weak HAL_SYSTICK_Callback + 1184 .syntax unified + 1185 .thumb + 1186 .thumb_func + 1187 .fpu fpv5-d16 + 1189 HAL_SYSTICK_Callback: + 1190 .LFB158: + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + ARM GAS /tmp/ccV0GlXv.s page 93 + + + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief SYSTICK callback. + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval None + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 1191 .loc 1 480 1 is_stmt 1 view -0 + 1192 .cfi_startproc + 1193 @ args = 0, pretend = 0, frame = 0 + 1194 @ frame_needed = 0, uses_anonymous_args = 0 + 1195 @ link register save eliminated. + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1196 .loc 1 484 1 view .LVU329 + 1197 0000 7047 bx lr + 1198 .cfi_endproc + 1199 .LFE158: + 1201 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits + 1202 .align 1 + 1203 .global HAL_SYSTICK_IRQHandler + 1204 .syntax unified + 1205 .thumb + 1206 .thumb_func + 1207 .fpu fpv5-d16 + 1209 HAL_SYSTICK_IRQHandler: + 1210 .LFB157: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 1211 .loc 1 471 1 view -0 + 1212 .cfi_startproc + 1213 @ args = 0, pretend = 0, frame = 0 + 1214 @ frame_needed = 0, uses_anonymous_args = 0 + 1215 0000 08B5 push {r3, lr} + 1216 .LCFI2: + 1217 .cfi_def_cfa_offset 8 + 1218 .cfi_offset 3, -8 + 1219 .cfi_offset 14, -4 + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1220 .loc 1 472 3 view .LVU331 + 1221 0002 FFF7FEFF bl HAL_SYSTICK_Callback + 1222 .LVL68: + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 1223 .loc 1 473 1 is_stmt 0 view .LVU332 + 1224 0006 08BD pop {r3, pc} + 1225 .cfi_endproc + 1226 .LFE157: + 1228 .section .text.HAL_GetCurrentCPUID,"ax",%progbits + ARM GAS /tmp/ccV0GlXv.s page 94 + + + 1229 .align 1 + 1230 .global HAL_GetCurrentCPUID + 1231 .syntax unified + 1232 .thumb + 1233 .thumb_func + 1234 .fpu fpv5-d16 + 1236 HAL_GetCurrentCPUID: + 1237 .LFB159: + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #if defined(DUAL_CORE) + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Returns the current CPU ID. + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval CPU identifier + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_GetCurrentCPUID(void) + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U) + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return CM7_CPUID; + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** else + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return CM4_CPUID; + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** #else + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** /** + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @brief Returns the current CPU ID. + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** * @retval CPU identifier + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** */ + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** uint32_t HAL_GetCurrentCPUID(void) + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** { + 1238 .loc 1 511 1 is_stmt 1 view -0 + 1239 .cfi_startproc + 1240 @ args = 0, pretend = 0, frame = 0 + 1241 @ frame_needed = 0, uses_anonymous_args = 0 + 1242 @ link register save eliminated. + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** return CM7_CPUID; + 1243 .loc 1 512 3 view .LVU334 + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c **** } + 1244 .loc 1 513 1 is_stmt 0 view .LVU335 + 1245 0000 0320 movs r0, #3 + 1246 0002 7047 bx lr + 1247 .cfi_endproc + 1248 .LFE159: + 1250 .text + 1251 .Letext0: + 1252 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1253 .file 5 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1254 .file 6 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1255 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h" + ARM GAS /tmp/ccV0GlXv.s page 95 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_cortex.c + /tmp/ccV0GlXv.s:17 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t + /tmp/ccV0GlXv.s:25 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping + /tmp/ccV0GlXv.s:81 .text.HAL_NVIC_SetPriorityGrouping:000000000000001c $d + /tmp/ccV0GlXv.s:87 .text.HAL_NVIC_SetPriority:0000000000000000 $t + /tmp/ccV0GlXv.s:94 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority + /tmp/ccV0GlXv.s:233 .text.HAL_NVIC_SetPriority:0000000000000060 $d + /tmp/ccV0GlXv.s:240 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t + /tmp/ccV0GlXv.s:247 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ + /tmp/ccV0GlXv.s:288 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d + /tmp/ccV0GlXv.s:293 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t + /tmp/ccV0GlXv.s:300 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ + /tmp/ccV0GlXv.s:371 .text.HAL_NVIC_DisableIRQ:0000000000000020 $d + /tmp/ccV0GlXv.s:376 .text.HAL_NVIC_SystemReset:0000000000000000 $t + /tmp/ccV0GlXv.s:383 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset + /tmp/ccV0GlXv.s:449 .text.HAL_NVIC_SystemReset:000000000000001c $d + /tmp/ccV0GlXv.s:457 .text.HAL_SYSTICK_Config:0000000000000000 $t + /tmp/ccV0GlXv.s:464 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config + /tmp/ccV0GlXv.s:529 .text.HAL_SYSTICK_Config:0000000000000024 $d + /tmp/ccV0GlXv.s:534 .text.HAL_MPU_Disable:0000000000000000 $t + /tmp/ccV0GlXv.s:541 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable + /tmp/ccV0GlXv.s:577 .text.HAL_MPU_Disable:0000000000000018 $d + /tmp/ccV0GlXv.s:582 .text.HAL_MPU_Enable:0000000000000000 $t + /tmp/ccV0GlXv.s:589 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable + /tmp/ccV0GlXv.s:642 .text.HAL_MPU_Enable:000000000000001c $d + /tmp/ccV0GlXv.s:647 .text.HAL_MPU_ConfigRegion:0000000000000000 $t + /tmp/ccV0GlXv.s:654 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion + /tmp/ccV0GlXv.s:743 .text.HAL_MPU_ConfigRegion:000000000000005c $d + /tmp/ccV0GlXv.s:748 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t + /tmp/ccV0GlXv.s:755 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping + /tmp/ccV0GlXv.s:779 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d + /tmp/ccV0GlXv.s:784 .text.HAL_NVIC_GetPriority:0000000000000000 $t + /tmp/ccV0GlXv.s:791 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority + /tmp/ccV0GlXv.s:910 .text.HAL_NVIC_GetPriority:0000000000000054 $d + /tmp/ccV0GlXv.s:918 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t + /tmp/ccV0GlXv.s:925 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ + /tmp/ccV0GlXv.s:967 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d + /tmp/ccV0GlXv.s:972 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t + /tmp/ccV0GlXv.s:979 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ + /tmp/ccV0GlXv.s:1025 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d + /tmp/ccV0GlXv.s:1030 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t + /tmp/ccV0GlXv.s:1037 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ + /tmp/ccV0GlXv.s:1079 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d + /tmp/ccV0GlXv.s:1084 .text.HAL_NVIC_GetActive:0000000000000000 $t + /tmp/ccV0GlXv.s:1091 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive + /tmp/ccV0GlXv.s:1137 .text.HAL_NVIC_GetActive:0000000000000020 $d + /tmp/ccV0GlXv.s:1142 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t + /tmp/ccV0GlXv.s:1149 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig + /tmp/ccV0GlXv.s:1182 .text.HAL_SYSTICK_Callback:0000000000000000 $t + /tmp/ccV0GlXv.s:1189 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback + /tmp/ccV0GlXv.s:1202 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t + /tmp/ccV0GlXv.s:1209 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler + /tmp/ccV0GlXv.s:1229 .text.HAL_GetCurrentCPUID:0000000000000000 $t + /tmp/ccV0GlXv.s:1236 .text.HAL_GetCurrentCPUID:0000000000000000 HAL_GetCurrentCPUID + +NO UNDEFINED SYMBOLS + ARM GAS /tmp/ccV0GlXv.s page 96 + + diff --git a/build/stm32h7xx_hal_cortex.o b/build/stm32h7xx_hal_cortex.o new file mode 100644 index 0000000..489f3f0 Binary files /dev/null and b/build/stm32h7xx_hal_cortex.o differ diff --git a/build/stm32h7xx_hal_dma.d b/build/stm32h7xx_hal_dma.d new file mode 100644 index 0000000..de0bf29 --- /dev/null +++ b/build/stm32h7xx_hal_dma.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_dma.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_dma.lst b/build/stm32h7xx_hal_dma.lst new file mode 100644 index 0000000..832b82c --- /dev/null +++ b/build/stm32h7xx_hal_dma.lst @@ -0,0 +1,11178 @@ +ARM GAS /tmp/ccXv4DVv.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_dma.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.DMA_SetConfig,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 DMA_SetConfig: + 25 .LVL0: + 26 .LFB153: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @file stm32h7xx_hal_dma.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief DMA HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * functionalities of the Direct Memory Access (DMA) peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + IO operation functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + Peripheral State and errors functions + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @verbatim + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ##### How to use this driver ##### + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (#) Enable and configure the peripheral to be connected to the DMA Stream + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (except for internal SRAM/FLASH memories: no initialization is + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** necessary) please refer to Reference manual for connection between peripherals + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** and DMA requests . + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (#) For a given Stream, program the required configuration through the following parameters: + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Transfer Direction, Source and Destination data formats, + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Circular, Normal or peripheral flow control mode, Stream Priority level, + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** *** Polling mode IO operation *** + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ================================= + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** address and destination address and the Length of data to be transferred + ARM GAS /tmp/ccXv4DVv.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case a fixed Timeout can be configured by User depending from his application. + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** *** Interrupt mode IO operation *** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =================================== + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Source address and destination address and the Length of data to be transferred. In t + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case the DMA interrupt is configured + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** add his own function by customization of function pointer XferCpltCallback and + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** XferErrorCallback (i.e a member of DMA handle structure). + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** detection. + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (#) Use HAL_DMA_Abort() function to abort the current transfer + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Half-Word data size for the peripheral to access its data register and set Word data siz + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** for the Memory to gain in access time. Each two half words will be packed and written in + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** a single access to a Word in the Memory). + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** and Destination. In this case the Peripheral Data Size will be applied to both Source + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** and Destination. + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** *** DMA HAL driver macros list *** + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ============================================= + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Below the list of most used macros in DMA HAL driver. + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (@) You can refer to the DMA HAL driver header file for more useful macros. + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @endverbatim + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ****************************************************************************** + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @attention + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * All rights reserved.

+ 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * This software component is licensed by ST under BSD 3-Clause license, + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the "License"; You may not use this file except in compliance with the + ARM GAS /tmp/ccXv4DVv.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * License. You may obtain a copy of the License at: + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * opensource.org/licenses/BSD-3-Clause + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ****************************************************************************** + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/ + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #include "stm32h7xx_hal.h" + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup STM32H7xx_HAL_Driver + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @defgroup DMA DMA + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief DMA HAL module driver + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Private types -------------------------------------------------------------*/ + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** typedef struct + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t ISR; /*!< DMA interrupt status register */ + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t Reserved0; + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } DMA_Base_Registers; + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** typedef struct + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t ISR; /*!< BDMA interrupt status register */ + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } BDMA_Base_Registers; + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/ + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Private constants ---------------------------------------------------------*/ + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Private_Constants + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direct + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direct + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* DMA to BDMA conversion */ + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BD + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BD + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_PERIPH_TO_MEMORY) + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U) + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U) + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U) + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U) + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U) + ARM GAS /tmp/ccXv4DVv.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #if defined(UART9) + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__ + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__ + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__ + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__ + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #else + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__ + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__ + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__ + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__ + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #endif + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @} + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Private macros ------------------------------------------------------------*/ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Private functions ---------------------------------------------------------*/ + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @} + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Exported functions ---------------------------------------------------------*/ + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group1 + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @verbatim + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =============================================================================== + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ##### Initialization and de-initialization functions ##### + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =============================================================================== + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** This section provides functions allowing to initialize the DMA Stream source + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** and destination incrementation and data sizes, transfer direction, + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** The HAL_DMA_Init() function follows the DMA configuration procedures as described in + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** reference manual. + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** The HAL_DMA_DeInit function allows to deinitialize the DMA stream. + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @endverbatim + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + ARM GAS /tmp/ccXv4DVv.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Initialize the DMA according to the specified + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * parameters in the DMA_InitTypeDef and create the associated handle. + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t registerValue; + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the parameters */ + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the memory burst, peripheral burst and FIFO threshold parameters only + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** when FIFO mode is enabled */ + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Allocate lock resource */ + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change DMA peripheral state */ + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the peripheral */ + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check if the DMA Stream is effectively disabled */ + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check for the Timeout */ + ARM GAS /tmp/ccXv4DVv.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the CR register value */ + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Prepare the DMA Stream configuration */ + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue |= hdma->Init.Direction | + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get memory burst and peripheral burst */ + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** lock when transfering data to/from USART/UART */ + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #if (STM32H7_DEV_ID == 0x450UL) + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #endif /* STM32H7_DEV_ID == 0x450UL */ + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue |= DMA_SxCR_TRBUFF; + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #if (STM32H7_DEV_ID == 0x450UL) + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #endif /* STM32H7_DEV_ID == 0x450UL */ + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Write to DMA Stream CR register */ + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the FCR register value */ + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear Direct mode and FIFO threshold bits */ + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Prepare the DMA Stream FIFO configuration */ + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue |= hdma->Init.FIFOMode; + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* the FIFO threshold is not used when the FIFO mode is disabled */ + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the FIFO threshold */ + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue |= hdma->Init.FIFOThreshold; + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check compatibility between FIFO threshold level and size of the memory burst */ + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* for INCR4, INCR8, INCR16 */ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (DMA_CheckFifoParam(hdma) != HAL_OK) + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Write to DMA Stream FCR */ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags */ + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the request parameter */ + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Allocate lock resource */ + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change DMA peripheral state */ + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the CR register value */ + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ + ARM GAS /tmp/ccXv4DVv.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_CCR_CT)); + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Prepare the DMA Channel configuration */ + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MODE(hdma->Init.Mode) | + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Write to DMA Channel CR register */ + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* calculation of the channel index */ + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags */ + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize parameters for DMAMUX channel : + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* if memory to memory force the request to 0*/ + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.Request = DMA_REQUEST_MEM2MEM; + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Set peripheral request to DMAMUX channel */ + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize parameters for DMAMUX request generator : + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERAT + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize parameters for DMAMUX request generator : + ARM GAS /tmp/ccXv4DVv.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset the DMAMUX request generator register */ + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR = 0U; + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen = 0U; + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize the error code */ + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize the DMA state */ + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_OK; + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief DeInitializes the DMA peripheral + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the selected DMA Streamx */ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Streamx control register */ + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Streamx number of data to transfer register */ + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Streamx peripheral address register */ + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Streamx memory 0 address register */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Streamx memory 1 address register */ + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Streamx FIFO control register */ + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get DMA steam Base Address */ + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Channel control register */ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U; + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Channel Number of Data to Transfer register */ + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U; + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Channel peripheral address register */ + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U; + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Channel memory 0 address register */ + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset DMA Channel memory 1 address register */ + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U; + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get DMA steam Base Address */ + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Return error status */ + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */ + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** #endif /* BDMA1 */ + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize parameters for DMAMUX channel : + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->DMAmuxChannel != 0U) + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Resett he DMAMUX channel that corresponds to the DMA stream */ + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel->CCR = 0U; + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERAT + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize parameters for DMAMUX request generator : + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Reset the DMAMUX request generator register */ + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR = 0U; + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen = 0U; + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clean callbacks */ + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize the error code */ + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize the DMA state */ + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Release Lock */ + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_OK; + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @} + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group2 + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @verbatim + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =============================================================================== + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ##### IO operation functions ##### + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =============================================================================== + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] This section provides functions allowing to: + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Configure the source, destination address and data length and Start DMA transfer + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Configure the source, destination address and data length and + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Start DMA transfer with interrupt + ARM GAS /tmp/ccXv4DVv.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Register and Unregister DMA callbacks + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Abort DMA transfer + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Poll for transfer complete + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Handle DMA interrupt request + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @endverbatim + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Starts the DMA Transfer. + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param SrcAddress: The source memory Buffer address + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param DstAddress: The destination memory Buffer address + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param DataLength: The length of data to be transferred from source to destination + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the parameters */ + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process locked */ + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_LOCK(hdma); + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change DMA peripheral state */ + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize the error code */ + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the peripheral */ + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Enable the Peripheral */ + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process unlocked */ + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Set the error code to busy */ + ARM GAS /tmp/ccXv4DVv.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Return error status */ + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return status; + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Start the DMA Transfer with interrupt enabled. + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param SrcAddress: The source memory Buffer address + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param DstAddress: The destination memory Buffer address + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param DataLength: The length of data to be transferred from source to destination + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the parameters */ + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process locked */ + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_LOCK(hdma); + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change DMA peripheral state */ + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Initialize the error code */ + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the peripheral */ + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Enable Common interrupts*/ + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Enable Half Transfer IT if corresponding Callback is set */ + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Enable Common interrupts */ + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /*Enable Half Transfer IT if corresponding Callback is set */ + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check if DMAMUX Synchronization is enabled */ + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Enable DMAMUX sync overrun IT*/ + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->DMAmuxRequestGen != 0U) + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* enable the request gen overrun IT */ + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Enable the Peripheral */ + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process unlocked */ + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Set the error code to busy */ + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Return error status */ + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return status; + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Aborts the DMA Transfer. + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * effectively disabled is added. If a Stream is disabled + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * while a data transfer is ongoing, the current data will be transferred + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * and the Stream will be effectively disabled only after the transfer of + ARM GAS /tmp/ccXv4DVv.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * this single data is finished. + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** const __IO uint32_t *enableRegister; + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral state */ + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable all the transfer interrupts */ + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable DMA All Interrupts */ + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_I + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable DMA All Interrupts */ + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CC + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* disable the DMAMUX sync overrun IT */ + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the stream */ + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check if the DMA Stream is effectively disabled */ + ARM GAS /tmp/ccXv4DVv.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** while(((*enableRegister) & DMA_SxCR_EN) != 0U) + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check for the Timeout */ + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->DMAmuxRequestGen != 0U) + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* disable the request gen overrun IT */ + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_OK; + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + ARM GAS /tmp/ccXv4DVv.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Aborts the DMA Transfer in Interrupt mode. + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Set Abort State */ + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ABORT; + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the stream */ + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable DMA All Interrupts */ + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CC + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the channel */ + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* disable the DMAMUX sync overrun IT */ + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all flags */ + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->DMAmuxRequestGen != 0U) + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* disable the request gen overrun IT */ + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + ARM GAS /tmp/ccXv4DVv.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Call User Abort callback */ + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferAbortCallback != NULL) + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback(hdma); + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_OK; + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Polling for transfer complete. + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param CompleteLevel: Specifies the DMA level complete. + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT mo + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * This model could be used for debug purpose. + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (a + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param Timeout: Timeout duration. + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t cpltlevel_mask; + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* IT status register */ + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t *isr_reg; + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* IT clear flag register */ + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t *ifcr_reg; + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* No transfer ongoing */ + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Polling mode not supported in circular mode and double buffering mode */ +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the level transfer complete flag */ +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer Complete flag */ +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half Transfer Complete flag */ +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Polling mode not supported in circular mode */ +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U) +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the level transfer complete flag */ +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer Complete flag */ +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU); +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half Transfer Complete flag */ +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU); +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** while(((*isr_reg) & cpltlevel_mask) == 0U) +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ + ARM GAS /tmp/ccXv4DVv.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_FE; +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the FIFO error flag */ +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_DME; +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the Direct Mode error flag */ +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_TE; +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the transfer error flag */ +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* When a DMA transfer error occurs */ +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all flags */ +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU)); +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check for the Timeout (Not applicable in circular mode)*/ +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(Timeout != HAL_MAX_DELAY) +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* if timeout then abort the current transfer */ +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERR +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (void) HAL_DMA_Abort(hdma); +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** Note that the Abort function will +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** - Clear the transfer error flags +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** - Unlock +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** - Set the State +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check for DMAMUX Request generator (if used) overrun status */ +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->DMAmuxRequestGen != 0U) +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check for DMAMUX Synchronization overrun */ +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Get the level transfer complete flag */ +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the half transfer and transfer complete flags */ +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ + ARM GAS /tmp/ccXv4DVv.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the half transfer and transfer complete flags */ +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA channel */ +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU)); +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return status; +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Handles DMA interrupt request. +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval None +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tmpisr_dma, tmpisr_bdma; +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t ccr_reg; +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t count = 0U; +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t timeout = SystemCoreClock / 9600U; +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* calculate DMA base and stream number */ +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** tmpisr_dma = regs_dma->ISR; +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** tmpisr_bdma = regs_bdma->ISR; +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer Error Interrupt management ***************************************/ +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the transfer error interrupt */ +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the transfer error flag */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + ARM GAS /tmp/ccXv4DVv.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_TE; +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* FIFO Error Interrupt management ******************************************/ +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the FIFO error flag */ +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_FE; +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Direct Mode Error Interrupt management ***********************************/ +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the direct mode error flag */ +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_DME; +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the half transfer complete flag */ +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Multi_Buffering mode enabled */ +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 0 */ +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half transfer callback */ +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 1 */ +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferM1HalfCpltCallback != NULL) +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half transfer callback */ +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback(hdma); +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the half transfer interrupt */ +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half transfer callback */ +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the transfer complete flag */ +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(HAL_DMA_STATE_ABORT == hdma->State) +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable all the transfer interrupts */ +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferAbortCallback != NULL) +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback(hdma); +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return; +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 0 */ + ARM GAS /tmp/ccXv4DVv.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferM1CpltCallback != NULL) +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer complete Callback for memory1 */ +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback(hdma); +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 1 */ +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer complete Callback for memory0 */ +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback(hdma); +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the transfer complete interrupt */ +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer complete callback */ +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback(hdma); +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* manage error case */ +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ABORT; +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the stream */ +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** do +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (++count > timeout) +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + ARM GAS /tmp/ccXv4DVv.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state to error if DMA disable fails */ +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state to Ready if DMA disable success */ +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferErrorCallback != NULL) +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer error callback */ +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback(hdma); +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_ +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the half transfer complete flag */ +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((ccr_reg & BDMA_CCR_DBM) != 0U) +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 0 */ +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((ccr_reg & BDMA_CCR_CT) == 0U) +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferM1HalfCpltCallback != NULL) +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half transfer Callback for Memory 1 */ +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback(hdma); +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 1 */ +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half transfer Callback for Memory 0 */ +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((ccr_reg & BDMA_CCR_CIRC) == 0U) +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the half transfer interrupt */ +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* DMA peripheral state is not updated in Half Transfer */ +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* but in Transfer Complete case */ +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Half transfer callback */ +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the transfer complete flag */ +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((ccr_reg & BDMA_CCR_DBM) != 0U) +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 0 */ +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((ccr_reg & BDMA_CCR_CT) == 0U) +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferM1CpltCallback != NULL) +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer complete Callback for Memory 1 */ +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback(hdma); +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Current memory buffer used is Memory 1 */ +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer complete Callback for Memory 0 */ +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback(hdma); +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((ccr_reg & BDMA_CCR_CIRC) == 0U) +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + ARM GAS /tmp/ccXv4DVv.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer complete callback */ +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback(hdma); +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer Error Interrupt management **************************************/ +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* When a DMA transfer error occurs */ +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Disable ALL DMA IT */ +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all flags */ +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Update error code */ +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process Unlocked */ +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Change the DMA state */ +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (hdma->XferErrorCallback != NULL) +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Transfer error callback */ +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback(hdma); +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Nothing To Do */ +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Nothing To Do */ +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Register callbacks +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param CallbackID: User Callback identifier +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param pCallback: pointer to private callback function which has pointer to +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. + ARM GAS /tmp/ccXv4DVv.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process locked */ +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_LOCK(hdma); +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** switch (CallbackID) +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback = pCallback; +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = pCallback; +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_M1CPLT_CB_ID: +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = pCallback; +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_M1HALFCPLT_CB_ID: +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = pCallback; +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = pCallback; +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = pCallback; +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** default: +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Return error status */ +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Release Lock */ +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return status; +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief UnRegister callbacks +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param CallbackID: User Callback identifier +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the DMA peripheral handle */ +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma == NULL) +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Process locked */ +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_LOCK(hdma); +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** switch (CallbackID) +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback = NULL; +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_M1CPLT_CB_ID: +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_M1HALFCPLT_CB_ID: +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case HAL_DMA_XFER_ALL_CB_ID: +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferCpltCallback = NULL; +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + ARM GAS /tmp/ccXv4DVv.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** default: +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Release Lock */ +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return status; +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @} +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group3 +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @verbatim +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =============================================================================== +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ##### State and Errors functions ##### +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** =============================================================================== +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** [..] +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** This subsection provides functions allowing to +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Check the DMA state +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (+) Get error code +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** @endverbatim +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Returns the DMA state. +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL state +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return hdma->State; +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Return the DMA error code +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval DMA Error Code +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) + ARM GAS /tmp/ccXv4DVv.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return hdma->ErrorCode; +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @} +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @} +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @{ +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Sets the DMA Transfer parameter. +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param SrcAddress: The source memory Buffer address +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param DstAddress: The destination memory Buffer address +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param DataLength: The length of data to be transferred from source to destination +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval None +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 28 .loc 1 1768 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 1768 1 is_stmt 0 view .LVU1 + 34 0000 F0B4 push {r4, r5, r6, r7} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 16 + 37 .cfi_offset 4, -16 + 38 .cfi_offset 5, -12 + 39 .cfi_offset 6, -8 + 40 .cfi_offset 7, -4 +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* calculate DMA base and stream number */ +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 41 .loc 1 1770 3 is_stmt 1 view .LVU2 + 42 .loc 1 1770 62 is_stmt 0 view .LVU3 + 43 0002 876D ldr r7, [r0, #88] + 44 .LVL1: +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + 45 .loc 1 1771 3 is_stmt 1 view .LVU4 +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 46 .loc 1 1773 3 view .LVU5 + 47 .loc 1 1773 6 is_stmt 0 view .LVU6 + 48 0004 0468 ldr r4, [r0] + 49 0006 664E ldr r6, .L14 + 50 0008 664D ldr r5, .L14+4 + 51 000a AC42 cmp r4, r5 + 52 000c 18BF it ne + ARM GAS /tmp/ccXv4DVv.s page 33 + + + 53 000e B442 cmpne r4, r6 + 54 0010 42D0 beq .L2 + 55 .loc 1 1773 6 discriminator 2 view .LVU7 + 56 0012 1835 adds r5, r5, #24 + 57 0014 AC42 cmp r4, r5 + 58 0016 3FD0 beq .L2 + 59 .loc 1 1773 6 discriminator 4 view .LVU8 + 60 0018 1835 adds r5, r5, #24 + 61 001a AC42 cmp r4, r5 + 62 001c 3CD0 beq .L2 + 63 .loc 1 1773 6 discriminator 6 view .LVU9 + 64 001e 1835 adds r5, r5, #24 + 65 0020 AC42 cmp r4, r5 + 66 0022 39D0 beq .L2 + 67 .loc 1 1773 6 discriminator 8 view .LVU10 + 68 0024 1835 adds r5, r5, #24 + 69 0026 AC42 cmp r4, r5 + 70 0028 36D0 beq .L2 + 71 .loc 1 1773 6 discriminator 10 view .LVU11 + 72 002a 1835 adds r5, r5, #24 + 73 002c AC42 cmp r4, r5 + 74 002e 33D0 beq .L2 + 75 .loc 1 1773 6 discriminator 12 view .LVU12 + 76 0030 1835 adds r5, r5, #24 + 77 0032 AC42 cmp r4, r5 + 78 0034 30D0 beq .L2 + 79 .loc 1 1773 6 discriminator 14 view .LVU13 + 80 0036 05F55675 add r5, r5, #856 + 81 003a AC42 cmp r4, r5 + 82 003c 2CD0 beq .L2 + 83 .loc 1 1773 6 discriminator 16 view .LVU14 + 84 003e 1835 adds r5, r5, #24 + 85 0040 AC42 cmp r4, r5 + 86 0042 29D0 beq .L2 + 87 .loc 1 1773 6 discriminator 18 view .LVU15 + 88 0044 1835 adds r5, r5, #24 + 89 0046 AC42 cmp r4, r5 + 90 0048 26D0 beq .L2 + 91 .loc 1 1773 6 discriminator 20 view .LVU16 + 92 004a 1835 adds r5, r5, #24 + 93 004c AC42 cmp r4, r5 + 94 004e 23D0 beq .L2 + 95 .loc 1 1773 6 discriminator 22 view .LVU17 + 96 0050 1835 adds r5, r5, #24 + 97 0052 AC42 cmp r4, r5 + 98 0054 20D0 beq .L2 + 99 .loc 1 1773 6 discriminator 24 view .LVU18 + 100 0056 1835 adds r5, r5, #24 + 101 0058 AC42 cmp r4, r5 + 102 005a 1DD0 beq .L2 + 103 .loc 1 1773 6 discriminator 26 view .LVU19 + 104 005c 1835 adds r5, r5, #24 + 105 005e AC42 cmp r4, r5 + 106 0060 1AD0 beq .L2 + 107 .loc 1 1773 6 discriminator 28 view .LVU20 + 108 0062 1835 adds r5, r5, #24 + 109 0064 AC42 cmp r4, r5 + ARM GAS /tmp/ccXv4DVv.s page 34 + + + 110 0066 17D0 beq .L2 + 111 .loc 1 1773 6 discriminator 30 view .LVU21 + 112 0068 4F4D ldr r5, .L14+8 + 113 006a AC42 cmp r4, r5 + 114 006c 14D0 beq .L2 + 115 .loc 1 1773 6 discriminator 32 view .LVU22 + 116 006e 1435 adds r5, r5, #20 + 117 0070 AC42 cmp r4, r5 + 118 0072 11D0 beq .L2 + 119 .loc 1 1773 6 discriminator 34 view .LVU23 + 120 0074 1435 adds r5, r5, #20 + 121 0076 AC42 cmp r4, r5 + 122 0078 0ED0 beq .L2 + 123 .loc 1 1773 6 discriminator 36 view .LVU24 + 124 007a 1435 adds r5, r5, #20 + 125 007c AC42 cmp r4, r5 + 126 007e 0BD0 beq .L2 + 127 .loc 1 1773 6 discriminator 38 view .LVU25 + 128 0080 1435 adds r5, r5, #20 + 129 0082 AC42 cmp r4, r5 + 130 0084 08D0 beq .L2 + 131 .loc 1 1773 6 discriminator 40 view .LVU26 + 132 0086 1435 adds r5, r5, #20 + 133 0088 AC42 cmp r4, r5 + 134 008a 05D0 beq .L2 + 135 .loc 1 1773 6 discriminator 42 view .LVU27 + 136 008c 1435 adds r5, r5, #20 + 137 008e AC42 cmp r4, r5 + 138 0090 02D0 beq .L2 + 139 .loc 1 1773 6 discriminator 44 view .LVU28 + 140 0092 1435 adds r5, r5, #20 + 141 0094 AC42 cmp r4, r5 + 142 0096 07D1 bne .L3 + 143 .L2: +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 144 .loc 1 1776 5 is_stmt 1 view .LVU29 + 145 .loc 1 1776 9 is_stmt 0 view .LVU30 + 146 0098 446E ldr r4, [r0, #100] + 147 .loc 1 1776 42 view .LVU31 + 148 009a 856E ldr r5, [r0, #104] + 149 .loc 1 1776 36 view .LVU32 + 150 009c 6560 str r5, [r4, #4] +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(hdma->DMAmuxRequestGen != 0U) + 151 .loc 1 1778 5 is_stmt 1 view .LVU33 + 152 .loc 1 1778 12 is_stmt 0 view .LVU34 + 153 009e C46E ldr r4, [r0, #108] + 154 .loc 1 1778 7 view .LVU35 + 155 00a0 14B1 cbz r4, .L3 +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 156 .loc 1 1781 7 is_stmt 1 view .LVU36 + 157 .loc 1 1781 11 is_stmt 0 view .LVU37 + 158 00a2 046F ldr r4, [r0, #112] + ARM GAS /tmp/ccXv4DVv.s page 35 + + + 159 .loc 1 1781 49 view .LVU38 + 160 00a4 456F ldr r5, [r0, #116] + 161 .loc 1 1781 43 view .LVU39 + 162 00a6 6560 str r5, [r4, #4] + 163 .L3: +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 164 .loc 1 1785 3 is_stmt 1 view .LVU40 + 165 .loc 1 1785 6 is_stmt 0 view .LVU41 + 166 00a8 0468 ldr r4, [r0] + 167 00aa 3D4E ldr r6, .L14 + 168 00ac 3D4D ldr r5, .L14+4 + 169 00ae AC42 cmp r4, r5 + 170 00b0 18BF it ne + 171 00b2 B442 cmpne r4, r6 + 172 00b4 52D0 beq .L4 + 173 .loc 1 1785 6 discriminator 2 view .LVU42 + 174 00b6 1835 adds r5, r5, #24 + 175 00b8 AC42 cmp r4, r5 + 176 00ba 4FD0 beq .L4 + 177 .loc 1 1785 6 discriminator 4 view .LVU43 + 178 00bc 1835 adds r5, r5, #24 + 179 00be AC42 cmp r4, r5 + 180 00c0 4CD0 beq .L4 + 181 .loc 1 1785 6 discriminator 6 view .LVU44 + 182 00c2 1835 adds r5, r5, #24 + 183 00c4 AC42 cmp r4, r5 + 184 00c6 49D0 beq .L4 + 185 .loc 1 1785 6 discriminator 8 view .LVU45 + 186 00c8 1835 adds r5, r5, #24 + 187 00ca AC42 cmp r4, r5 + 188 00cc 46D0 beq .L4 + 189 .loc 1 1785 6 discriminator 10 view .LVU46 + 190 00ce 1835 adds r5, r5, #24 + 191 00d0 AC42 cmp r4, r5 + 192 00d2 43D0 beq .L4 + 193 .loc 1 1785 6 discriminator 12 view .LVU47 + 194 00d4 1835 adds r5, r5, #24 + 195 00d6 AC42 cmp r4, r5 + 196 00d8 40D0 beq .L4 + 197 .loc 1 1785 6 discriminator 14 view .LVU48 + 198 00da 05F55675 add r5, r5, #856 + 199 00de AC42 cmp r4, r5 + 200 00e0 3CD0 beq .L4 + 201 .loc 1 1785 6 discriminator 16 view .LVU49 + 202 00e2 1835 adds r5, r5, #24 + 203 00e4 AC42 cmp r4, r5 + 204 00e6 39D0 beq .L4 + 205 .loc 1 1785 6 discriminator 18 view .LVU50 + 206 00e8 1835 adds r5, r5, #24 + 207 00ea AC42 cmp r4, r5 + 208 00ec 36D0 beq .L4 + 209 .loc 1 1785 6 discriminator 20 view .LVU51 + 210 00ee 1835 adds r5, r5, #24 + 211 00f0 AC42 cmp r4, r5 + ARM GAS /tmp/ccXv4DVv.s page 36 + + + 212 00f2 33D0 beq .L4 + 213 .loc 1 1785 6 discriminator 22 view .LVU52 + 214 00f4 1835 adds r5, r5, #24 + 215 00f6 AC42 cmp r4, r5 + 216 00f8 30D0 beq .L4 + 217 .loc 1 1785 6 discriminator 24 view .LVU53 + 218 00fa 1835 adds r5, r5, #24 + 219 00fc AC42 cmp r4, r5 + 220 00fe 2DD0 beq .L4 + 221 .loc 1 1785 6 discriminator 26 view .LVU54 + 222 0100 1835 adds r5, r5, #24 + 223 0102 AC42 cmp r4, r5 + 224 0104 2AD0 beq .L4 + 225 .loc 1 1785 6 discriminator 28 view .LVU55 + 226 0106 1835 adds r5, r5, #24 + 227 0108 AC42 cmp r4, r5 + 228 010a 27D0 beq .L4 +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear DBM bit */ +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Stream data length */ +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Peripheral to Memory */ +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Stream destination address */ +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Stream source address */ +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Memory to Peripheral */ +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Stream source address */ +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Stream destination address */ +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + 229 .loc 1 1815 8 is_stmt 1 view .LVU56 + 230 .loc 1 1815 11 is_stmt 0 view .LVU57 + 231 010c 264E ldr r6, .L14+8 + 232 010e 274D ldr r5, .L14+12 + 233 0110 AC42 cmp r4, r5 + 234 0112 18BF it ne + 235 0114 B442 cmpne r4, r6 + 236 0116 11D0 beq .L5 + 237 .loc 1 1815 11 discriminator 2 view .LVU58 + 238 0118 254D ldr r5, .L14+16 + ARM GAS /tmp/ccXv4DVv.s page 37 + + + 239 011a AC42 cmp r4, r5 + 240 011c 0ED0 beq .L5 + 241 .loc 1 1815 11 discriminator 4 view .LVU59 + 242 011e 1435 adds r5, r5, #20 + 243 0120 AC42 cmp r4, r5 + 244 0122 0BD0 beq .L5 + 245 .loc 1 1815 11 discriminator 6 view .LVU60 + 246 0124 1435 adds r5, r5, #20 + 247 0126 AC42 cmp r4, r5 + 248 0128 08D0 beq .L5 + 249 .loc 1 1815 11 discriminator 8 view .LVU61 + 250 012a 1435 adds r5, r5, #20 + 251 012c AC42 cmp r4, r5 + 252 012e 05D0 beq .L5 + 253 .loc 1 1815 11 discriminator 10 view .LVU62 + 254 0130 1435 adds r5, r5, #20 + 255 0132 AC42 cmp r4, r5 + 256 0134 02D0 beq .L5 + 257 .loc 1 1815 11 discriminator 12 view .LVU63 + 258 0136 1435 adds r5, r5, #20 + 259 0138 AC42 cmp r4, r5 + 260 013a 24D1 bne .L1 + 261 .L5: +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Clear all flags */ +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + 262 .loc 1 1818 5 is_stmt 1 view .LVU64 + 263 .loc 1 1818 47 is_stmt 0 view .LVU65 + 264 013c C46D ldr r4, [r0, #92] + 265 .loc 1 1818 61 view .LVU66 + 266 013e 04F01F05 and r5, r4, #31 + 267 .loc 1 1818 39 view .LVU67 + 268 0142 0124 movs r4, #1 + 269 0144 AC40 lsls r4, r4, r5 + 270 .loc 1 1818 21 view .LVU68 + 271 0146 7C60 str r4, [r7, #4] +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Channel data length */ +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + 272 .loc 1 1821 5 is_stmt 1 view .LVU69 + 273 .loc 1 1821 34 is_stmt 0 view .LVU70 + 274 0148 0468 ldr r4, [r0] + 275 .loc 1 1821 53 view .LVU71 + 276 014a 6360 str r3, [r4, #4] +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Peripheral to Memory */ +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 277 .loc 1 1824 5 is_stmt 1 view .LVU72 + 278 .loc 1 1824 19 is_stmt 0 view .LVU73 + 279 014c 8368 ldr r3, [r0, #8] + 280 .LVL2: + 281 .loc 1 1824 7 view .LVU74 + 282 014e 402B cmp r3, #64 + 283 0150 20D0 beq .L12 +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Channel destination address */ +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + ARM GAS /tmp/ccXv4DVv.s page 38 + + +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Channel source address */ +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Memory to Peripheral */ +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Channel source address */ +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + 284 .loc 1 1836 7 is_stmt 1 view .LVU75 + 285 .loc 1 1836 36 is_stmt 0 view .LVU76 + 286 0152 0368 ldr r3, [r0] + 287 .loc 1 1836 54 view .LVU77 + 288 0154 9960 str r1, [r3, #8] + 289 .LVL3: +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Configure DMA Channel destination address */ +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + 290 .loc 1 1839 7 is_stmt 1 view .LVU78 + 291 .loc 1 1839 36 is_stmt 0 view .LVU79 + 292 0156 0368 ldr r3, [r0] + 293 .loc 1 1839 55 view .LVU80 + 294 0158 DA60 str r2, [r3, #12] +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Nothing To Do */ +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 295 .loc 1 1845 3 is_stmt 1 view .LVU81 +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 296 .loc 1 1846 1 is_stmt 0 view .LVU82 + 297 015a 14E0 b .L1 + 298 .LVL4: + 299 .L4: +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 300 .loc 1 1788 5 is_stmt 1 view .LVU83 +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 301 .loc 1 1788 37 is_stmt 0 view .LVU84 + 302 015c C46D ldr r4, [r0, #92] +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 303 .loc 1 1788 51 view .LVU85 + 304 015e 04F01F0C and ip, r4, #31 +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 305 .loc 1 1788 29 view .LVU86 + 306 0162 3F24 movs r4, #63 + 307 0164 04FA0CF4 lsl r4, r4, ip +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 308 .loc 1 1788 20 view .LVU87 + 309 0168 BC60 str r4, [r7, #8] +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 310 .loc 1 1791 5 is_stmt 1 view .LVU88 +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 311 .loc 1 1791 32 is_stmt 0 view .LVU89 + 312 016a 0568 ldr r5, [r0] +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 313 .loc 1 1791 48 view .LVU90 + ARM GAS /tmp/ccXv4DVv.s page 39 + + + 314 016c 2C68 ldr r4, [r5] + 315 016e 24F48024 bic r4, r4, #262144 + 316 0172 2C60 str r4, [r5] +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 317 .loc 1 1794 5 is_stmt 1 view .LVU91 +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 318 .loc 1 1794 32 is_stmt 0 view .LVU92 + 319 0174 0468 ldr r4, [r0] +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 320 .loc 1 1794 50 view .LVU93 + 321 0176 6360 str r3, [r4, #4] +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 322 .loc 1 1797 5 is_stmt 1 view .LVU94 +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 323 .loc 1 1797 19 is_stmt 0 view .LVU95 + 324 0178 8368 ldr r3, [r0, #8] + 325 .LVL5: +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 326 .loc 1 1797 7 view .LVU96 + 327 017a 402B cmp r3, #64 + 328 017c 05D0 beq .L13 +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 329 .loc 1 1809 7 is_stmt 1 view .LVU97 +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 330 .loc 1 1809 34 is_stmt 0 view .LVU98 + 331 017e 0368 ldr r3, [r0] +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 332 .loc 1 1809 51 view .LVU99 + 333 0180 9960 str r1, [r3, #8] + 334 .LVL6: +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 335 .loc 1 1812 7 is_stmt 1 view .LVU100 +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 336 .loc 1 1812 34 is_stmt 0 view .LVU101 + 337 0182 0368 ldr r3, [r0] +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 338 .loc 1 1812 52 view .LVU102 + 339 0184 DA60 str r2, [r3, #12] + 340 .L1: + 341 .loc 1 1846 1 view .LVU103 + 342 0186 F0BC pop {r4, r5, r6, r7} + 343 .LCFI1: + 344 .cfi_remember_state + 345 .cfi_restore 7 + 346 .cfi_restore 6 + 347 .cfi_restore 5 + 348 .cfi_restore 4 + 349 .cfi_def_cfa_offset 0 + 350 .LVL7: + 351 .loc 1 1846 1 view .LVU104 + 352 0188 7047 bx lr + 353 .LVL8: + 354 .L13: + 355 .LCFI2: + 356 .cfi_restore_state +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 357 .loc 1 1800 7 is_stmt 1 view .LVU105 + ARM GAS /tmp/ccXv4DVv.s page 40 + + +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 358 .loc 1 1800 34 is_stmt 0 view .LVU106 + 359 018a 0368 ldr r3, [r0] +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 360 .loc 1 1800 51 view .LVU107 + 361 018c 9A60 str r2, [r3, #8] + 362 .LVL9: +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 363 .loc 1 1803 7 is_stmt 1 view .LVU108 +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 364 .loc 1 1803 34 is_stmt 0 view .LVU109 + 365 018e 0368 ldr r3, [r0] +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 366 .loc 1 1803 52 view .LVU110 + 367 0190 D960 str r1, [r3, #12] + 368 0192 F8E7 b .L1 + 369 .LVL10: + 370 .L12: +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 371 .loc 1 1827 7 is_stmt 1 view .LVU111 +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 372 .loc 1 1827 36 is_stmt 0 view .LVU112 + 373 0194 0368 ldr r3, [r0] +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 374 .loc 1 1827 54 view .LVU113 + 375 0196 9A60 str r2, [r3, #8] + 376 .LVL11: +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 377 .loc 1 1830 7 is_stmt 1 view .LVU114 +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 378 .loc 1 1830 36 is_stmt 0 view .LVU115 + 379 0198 0368 ldr r3, [r0] +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 380 .loc 1 1830 55 view .LVU116 + 381 019a D960 str r1, [r3, #12] + 382 019c F3E7 b .L1 + 383 .L15: + 384 019e 00BF .align 2 + 385 .L14: + 386 01a0 10000240 .word 1073872912 + 387 01a4 28000240 .word 1073872936 + 388 01a8 08540258 .word 1476547592 + 389 01ac 1C540258 .word 1476547612 + 390 01b0 30540258 .word 1476547632 + 391 .cfi_endproc + 392 .LFE153: + 394 .section .text.DMA_CalcBaseAndBitshift,"ax",%progbits + 395 .align 1 + 396 .syntax unified + 397 .thumb + 398 .thumb_func + 399 .fpu fpv5-d16 + 401 DMA_CalcBaseAndBitshift: + 402 .LVL12: + 403 .LFB154: +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** + ARM GAS /tmp/ccXv4DVv.s page 41 + + +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Returns the DMA Stream base address depending on stream number +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval Stream base address +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 404 .loc 1 1855 1 is_stmt 1 view -0 + 405 .cfi_startproc + 406 @ args = 0, pretend = 0, frame = 0 + 407 @ frame_needed = 0, uses_anonymous_args = 0 + 408 @ link register save eliminated. +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 409 .loc 1 1856 3 view .LVU118 + 410 .loc 1 1856 6 is_stmt 0 view .LVU119 + 411 0000 0368 ldr r3, [r0] + 412 0002 2749 ldr r1, .L23 + 413 0004 274A ldr r2, .L23+4 + 414 0006 9342 cmp r3, r2 + 415 0008 18BF it ne + 416 000a 8B42 cmpne r3, r1 + 417 000c 2FD0 beq .L17 + 418 .loc 1 1856 6 discriminator 2 view .LVU120 + 419 000e 1832 adds r2, r2, #24 + 420 0010 9342 cmp r3, r2 + 421 0012 2CD0 beq .L17 + 422 .loc 1 1856 6 discriminator 4 view .LVU121 + 423 0014 1832 adds r2, r2, #24 + 424 0016 9342 cmp r3, r2 + 425 0018 29D0 beq .L17 + 426 .loc 1 1856 6 discriminator 6 view .LVU122 + 427 001a 1832 adds r2, r2, #24 + 428 001c 9342 cmp r3, r2 + 429 001e 26D0 beq .L17 + 430 .loc 1 1856 6 discriminator 8 view .LVU123 + 431 0020 1832 adds r2, r2, #24 + 432 0022 9342 cmp r3, r2 + 433 0024 23D0 beq .L17 + 434 .loc 1 1856 6 discriminator 10 view .LVU124 + 435 0026 1832 adds r2, r2, #24 + 436 0028 9342 cmp r3, r2 + 437 002a 20D0 beq .L17 + 438 .loc 1 1856 6 discriminator 12 view .LVU125 + 439 002c 1832 adds r2, r2, #24 + 440 002e 9342 cmp r3, r2 + 441 0030 1DD0 beq .L17 + 442 .loc 1 1856 6 discriminator 14 view .LVU126 + 443 0032 02F55672 add r2, r2, #856 + 444 0036 9342 cmp r3, r2 + 445 0038 19D0 beq .L17 + 446 .loc 1 1856 6 discriminator 16 view .LVU127 + 447 003a 1832 adds r2, r2, #24 + 448 003c 9342 cmp r3, r2 + 449 003e 16D0 beq .L17 + 450 .loc 1 1856 6 discriminator 18 view .LVU128 + 451 0040 1832 adds r2, r2, #24 + 452 0042 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 42 + + + 453 0044 13D0 beq .L17 + 454 .loc 1 1856 6 discriminator 20 view .LVU129 + 455 0046 1832 adds r2, r2, #24 + 456 0048 9342 cmp r3, r2 + 457 004a 10D0 beq .L17 + 458 .loc 1 1856 6 discriminator 22 view .LVU130 + 459 004c 1832 adds r2, r2, #24 + 460 004e 9342 cmp r3, r2 + 461 0050 0DD0 beq .L17 + 462 .loc 1 1856 6 discriminator 24 view .LVU131 + 463 0052 1832 adds r2, r2, #24 + 464 0054 9342 cmp r3, r2 + 465 0056 0AD0 beq .L17 + 466 .loc 1 1856 6 discriminator 26 view .LVU132 + 467 0058 1832 adds r2, r2, #24 + 468 005a 9342 cmp r3, r2 + 469 005c 07D0 beq .L17 + 470 .loc 1 1856 6 discriminator 28 view .LVU133 + 471 005e 1832 adds r2, r2, #24 + 472 0060 9342 cmp r3, r2 + 473 0062 04D0 beq .L17 +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* lookup table for necessary bitshift of flags within status registers */ +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (stream_number > 3U) +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* return pointer to HISR and HIFCR */ +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* return pointer to LISR and LIFCR */ +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else /* BDMA instance(s) */ +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* return pointer to ISR and IFCR */ +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); + 474 .loc 1 1878 5 is_stmt 1 view .LVU134 + 475 .loc 1 1878 70 is_stmt 0 view .LVU135 + 476 0064 23F0FF03 bic r3, r3, #255 + 477 .loc 1 1878 29 view .LVU136 + 478 0068 8365 str r3, [r0, #88] +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return hdma->StreamBaseAddress; + 479 .loc 1 1881 3 is_stmt 1 view .LVU137 +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 480 .loc 1 1882 1 is_stmt 0 view .LVU138 + 481 006a 806D ldr r0, [r0, #88] + 482 .LVL13: + 483 .loc 1 1882 1 view .LVU139 + ARM GAS /tmp/ccXv4DVv.s page 43 + + + 484 006c 7047 bx lr + 485 .LVL14: + 486 .L17: +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 487 .loc 1 1855 1 view .LVU140 + 488 006e 10B4 push {r4} + 489 .LCFI3: + 490 .cfi_def_cfa_offset 4 + 491 .cfi_offset 4, -4 + 492 .LBB2: +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 493 .loc 1 1858 5 is_stmt 1 view .LVU141 +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 494 .loc 1 1858 70 is_stmt 0 view .LVU142 + 495 0070 D9B2 uxtb r1, r3 +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 496 .loc 1 1858 79 view .LVU143 + 497 0072 1039 subs r1, r1, #16 +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 498 .loc 1 1858 14 view .LVU144 + 499 0074 0C4A ldr r2, .L23+8 + 500 0076 A2FB0142 umull r4, r2, r2, r1 + 501 .LVL15: +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; + 502 .loc 1 1861 5 is_stmt 1 view .LVU145 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 503 .loc 1 1862 5 view .LVU146 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 504 .loc 1 1862 58 is_stmt 0 view .LVU147 + 505 007a C2F30212 ubfx r2, r2, #4, #3 + 506 .LVL16: +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 507 .loc 1 1862 43 view .LVU148 + 508 007e 0B4C ldr r4, .L23+12 + 509 0080 A25C ldrb r2, [r4, r2] @ zero_extendqisi2 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 510 .loc 1 1862 23 view .LVU149 + 511 0082 C265 str r2, [r0, #92] +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 512 .loc 1 1864 5 is_stmt 1 view .LVU150 +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 513 .loc 1 1864 8 is_stmt 0 view .LVU151 + 514 0084 5F29 cmp r1, #95 + 515 0086 07D9 bls .L19 +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 516 .loc 1 1867 7 is_stmt 1 view .LVU152 +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 517 .loc 1 1867 73 is_stmt 0 view .LVU153 + 518 0088 094A ldr r2, .L23+16 + 519 008a 1A40 ands r2, r2, r3 +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 520 .loc 1 1867 96 view .LVU154 + 521 008c 0432 adds r2, r2, #4 +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 522 .loc 1 1867 31 view .LVU155 + 523 008e 8265 str r2, [r0, #88] + 524 .L18: + ARM GAS /tmp/ccXv4DVv.s page 44 + + + 525 .LBE2: +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 526 .loc 1 1881 3 is_stmt 1 view .LVU156 + 527 .loc 1 1882 1 is_stmt 0 view .LVU157 + 528 0090 806D ldr r0, [r0, #88] + 529 .LVL17: + 530 .loc 1 1882 1 view .LVU158 + 531 0092 5DF8044B ldr r4, [sp], #4 + 532 .LCFI4: + 533 .cfi_remember_state + 534 .cfi_restore 4 + 535 .cfi_def_cfa_offset 0 + 536 0096 7047 bx lr + 537 .LVL18: + 538 .L19: + 539 .LCFI5: + 540 .cfi_restore_state + 541 .LBB3: +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 542 .loc 1 1872 7 is_stmt 1 view .LVU159 +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 543 .loc 1 1872 72 is_stmt 0 view .LVU160 + 544 0098 054A ldr r2, .L23+16 + 545 009a 1A40 ands r2, r2, r3 +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 546 .loc 1 1872 31 view .LVU161 + 547 009c 8265 str r2, [r0, #88] + 548 009e F7E7 b .L18 + 549 .L24: + 550 .align 2 + 551 .L23: + 552 00a0 10000240 .word 1073872912 + 553 00a4 28000240 .word 1073872936 + 554 00a8 ABAAAAAA .word -1431655765 + 555 00ac 00000000 .word .LANCHOR0 + 556 00b0 00FCFFFF .word -1024 + 557 .LBE3: + 558 .cfi_endproc + 559 .LFE154: + 561 .section .text.DMA_CheckFifoParam,"ax",%progbits + 562 .align 1 + 563 .syntax unified + 564 .thumb + 565 .thumb_func + 566 .fpu fpv5-d16 + 568 DMA_CheckFifoParam: + 569 .LVL19: + 570 .LFB155: +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Check compatibility between FIFO threshold level and size of the memory burst +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 45 + + + 571 .loc 1 1891 1 is_stmt 1 view -0 + 572 .cfi_startproc + 573 @ args = 0, pretend = 0, frame = 0 + 574 @ frame_needed = 0, uses_anonymous_args = 0 + 575 @ link register save eliminated. +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 576 .loc 1 1892 3 view .LVU163 +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Memory Data size equal to Byte */ +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + 577 .loc 1 1895 3 view .LVU164 + 578 .loc 1 1895 17 is_stmt 0 view .LVU165 + 579 0000 8369 ldr r3, [r0, #24] + 580 .loc 1 1895 6 view .LVU166 + 581 0002 9BB9 cbnz r3, .L26 +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** switch (hdma->Init.FIFOThreshold) + 582 .loc 1 1897 5 is_stmt 1 view .LVU167 + 583 .loc 1 1897 23 is_stmt 0 view .LVU168 + 584 0004 836A ldr r3, [r0, #40] + 585 .loc 1 1897 5 view .LVU169 + 586 0006 012B cmp r3, #1 + 587 0008 0AD0 beq .L27 + 588 000a 022B cmp r3, #2 + 589 000c 02D0 beq .L28 + 590 000e 0BB1 cbz r3, .L28 + 591 0010 0020 movs r0, #0 + 592 .LVL20: + 593 .loc 1 1897 5 view .LVU170 + 594 0012 7047 bx lr + 595 .LVL21: + 596 .L28: +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_1QUARTERFULL: +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_3QUARTERSFULL: +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 597 .loc 1 1902 9 is_stmt 1 view .LVU171 + 598 .loc 1 1902 24 is_stmt 0 view .LVU172 + 599 0014 C36A ldr r3, [r0, #44] + 600 .loc 1 1902 12 view .LVU173 + 601 0016 13F0807F tst r3, #16777216 + 602 001a 2AD1 bne .L36 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 603 .loc 1 1892 21 view .LVU174 + 604 001c 0020 movs r0, #0 + 605 .LVL22: +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 606 .loc 1 1892 21 view .LVU175 + 607 001e 7047 bx lr + 608 .LVL23: + 609 .L27: +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 46 + + +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_HALFFULL: +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 610 .loc 1 1909 9 is_stmt 1 view .LVU176 + 611 .loc 1 1909 23 is_stmt 0 view .LVU177 + 612 0020 C36A ldr r3, [r0, #44] + 613 .loc 1 1909 12 view .LVU178 + 614 0022 B3F1C07F cmp r3, #25165824 + 615 0026 26D0 beq .L37 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 616 .loc 1 1892 21 view .LVU179 + 617 0028 0020 movs r0, #0 + 618 .LVL24: +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 619 .loc 1 1892 21 view .LVU180 + 620 002a 7047 bx lr + 621 .LVL25: + 622 .L26: +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_FULL: +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** default: +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Memory Data size equal to Half-Word */ +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 623 .loc 1 1924 8 is_stmt 1 view .LVU181 + 624 .loc 1 1924 11 is_stmt 0 view .LVU182 + 625 002c B3F5005F cmp r3, #8192 + 626 0030 0AD0 beq .L44 +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** switch (hdma->Init.FIFOThreshold) +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_1QUARTERFULL: +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_3QUARTERSFULL: +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_HALFFULL: +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_FULL: +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if (hdma->Init.MemBurst == DMA_MBURST_INC16) +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + ARM GAS /tmp/ccXv4DVv.s page 47 + + +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** default: +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Memory Data size equal to Word */ +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** switch (hdma->Init.FIFOThreshold) + 627 .loc 1 1955 5 is_stmt 1 view .LVU183 + 628 .loc 1 1955 23 is_stmt 0 view .LVU184 + 629 0032 836A ldr r3, [r0, #40] + 630 .loc 1 1955 5 view .LVU185 + 631 0034 022B cmp r3, #2 + 632 0036 26D9 bls .L41 + 633 0038 032B cmp r3, #3 + 634 003a 26D1 bne .L42 +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_1QUARTERFULL: +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_HALFFULL: +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_3QUARTERSFULL: +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_FULL: +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 635 .loc 1 1964 9 is_stmt 1 view .LVU186 + 636 .loc 1 1964 24 is_stmt 0 view .LVU187 + 637 003c C36A ldr r3, [r0, #44] + 638 .loc 1 1964 12 view .LVU188 + 639 003e 13F0807F tst r3, #16777216 + 640 0042 24D1 bne .L43 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 641 .loc 1 1892 21 view .LVU189 + 642 0044 0020 movs r0, #0 + 643 .LVL26: +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 644 .loc 1 1892 21 view .LVU190 + 645 0046 7047 bx lr + 646 .LVL27: + 647 .L44: +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 648 .loc 1 1926 5 is_stmt 1 view .LVU191 +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 649 .loc 1 1926 23 is_stmt 0 view .LVU192 + 650 0048 836A ldr r3, [r0, #40] + 651 004a 032B cmp r3, #3 + 652 004c 03D8 bhi .L31 + 653 004e DFE803F0 tbb [pc, r3] + 654 .L33: + 655 0052 14 .byte (.L38-.L33)/2 + 656 0053 04 .byte (.L34-.L33)/2 + 657 0054 14 .byte (.L38-.L33)/2 + 658 0055 0A .byte (.L32-.L33)/2 + 659 .p2align 1 + 660 .L31: + ARM GAS /tmp/ccXv4DVv.s page 48 + + + 661 0056 0020 movs r0, #0 + 662 .LVL28: +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 663 .loc 1 1926 23 view .LVU193 + 664 0058 7047 bx lr + 665 .LVL29: + 666 .L34: +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 667 .loc 1 1934 9 is_stmt 1 view .LVU194 +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 668 .loc 1 1934 24 is_stmt 0 view .LVU195 + 669 005a C36A ldr r3, [r0, #44] +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 670 .loc 1 1934 12 view .LVU196 + 671 005c 13F0807F tst r3, #16777216 + 672 0060 0DD1 bne .L39 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 673 .loc 1 1892 21 view .LVU197 + 674 0062 0020 movs r0, #0 + 675 .LVL30: +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 676 .loc 1 1892 21 view .LVU198 + 677 0064 7047 bx lr + 678 .LVL31: + 679 .L32: +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 680 .loc 1 1941 9 is_stmt 1 view .LVU199 +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 681 .loc 1 1941 23 is_stmt 0 view .LVU200 + 682 0066 C36A ldr r3, [r0, #44] +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 683 .loc 1 1941 12 view .LVU201 + 684 0068 B3F1C07F cmp r3, #25165824 + 685 006c 09D0 beq .L40 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 686 .loc 1 1892 21 view .LVU202 + 687 006e 0020 movs r0, #0 + 688 .LVL32: +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 689 .loc 1 1892 21 view .LVU203 + 690 0070 7047 bx lr + 691 .LVL33: + 692 .L36: +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 693 .loc 1 1904 18 view .LVU204 + 694 0072 0120 movs r0, #1 + 695 .LVL34: +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 696 .loc 1 1904 18 view .LVU205 + 697 0074 7047 bx lr + 698 .LVL35: + 699 .L37: +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 700 .loc 1 1911 18 view .LVU206 + 701 0076 0120 movs r0, #1 + 702 .LVL36: +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 49 + + + 703 .loc 1 1911 18 view .LVU207 + 704 0078 7047 bx lr + 705 .LVL37: + 706 .L38: +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 707 .loc 1 1930 16 view .LVU208 + 708 007a 0120 movs r0, #1 + 709 .LVL38: +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 710 .loc 1 1930 16 view .LVU209 + 711 007c 7047 bx lr + 712 .LVL39: + 713 .L39: +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 714 .loc 1 1936 18 view .LVU210 + 715 007e 0120 movs r0, #1 + 716 .LVL40: +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 717 .loc 1 1936 18 view .LVU211 + 718 0080 7047 bx lr + 719 .LVL41: + 720 .L40: +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 721 .loc 1 1943 18 view .LVU212 + 722 0082 0120 movs r0, #1 + 723 .LVL42: +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 724 .loc 1 1943 18 view .LVU213 + 725 0084 7047 bx lr + 726 .LVL43: + 727 .L41: +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 728 .loc 1 1960 16 view .LVU214 + 729 0086 0120 movs r0, #1 + 730 .LVL44: +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 731 .loc 1 1960 16 view .LVU215 + 732 0088 7047 bx lr + 733 .LVL45: + 734 .L42: +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 735 .loc 1 1955 5 view .LVU216 + 736 008a 0020 movs r0, #0 + 737 .LVL46: +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 738 .loc 1 1955 5 view .LVU217 + 739 008c 7047 bx lr + 740 .LVL47: + 741 .L43: +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** status = HAL_ERROR; + 742 .loc 1 1966 18 view .LVU218 + 743 008e 0120 movs r0, #1 + 744 .LVL48: +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 50 + + +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** default: +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return status; + 745 .loc 1 1975 3 is_stmt 1 view .LVU219 +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 746 .loc 1 1976 1 is_stmt 0 view .LVU220 + 747 0090 7047 bx lr + 748 .cfi_endproc + 749 .LFE155: + 751 .section .text.DMA_CalcDMAMUXChannelBaseAndMask,"ax",%progbits + 752 .align 1 + 753 .syntax unified + 754 .thumb + 755 .thumb_func + 756 .fpu fpv5-d16 + 758 DMA_CalcDMAMUXChannelBaseAndMask: + 759 .LVL49: + 760 .LFB156: +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream num +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 761 .loc 1 1985 1 is_stmt 1 view -0 + 762 .cfi_startproc + 763 @ args = 0, pretend = 0, frame = 0 + 764 @ frame_needed = 0, uses_anonymous_args = 0 + 765 @ link register save eliminated. +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t stream_number; + 766 .loc 1 1986 3 view .LVU222 +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); + 767 .loc 1 1987 3 view .LVU223 + 768 .loc 1 1987 59 is_stmt 0 view .LVU224 + 769 0000 0368 ldr r3, [r0] + 770 .LVL50: +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + 771 .loc 1 1989 3 is_stmt 1 view .LVU225 + 772 .loc 1 1989 6 is_stmt 0 view .LVU226 + 773 0002 2249 ldr r1, .L50 + 774 0004 224A ldr r2, .L50+4 + 775 0006 9342 cmp r3, r2 + 776 0008 18BF it ne + 777 000a 8B42 cmpne r3, r1 + 778 000c 28D0 beq .L46 + 779 .loc 1 1989 6 discriminator 2 view .LVU227 + 780 000e 1432 adds r2, r2, #20 + 781 0010 9342 cmp r3, r2 + 782 0012 25D0 beq .L46 + 783 .loc 1 1989 6 discriminator 4 view .LVU228 + ARM GAS /tmp/ccXv4DVv.s page 51 + + + 784 0014 1432 adds r2, r2, #20 + 785 0016 9342 cmp r3, r2 + 786 0018 22D0 beq .L46 + 787 .loc 1 1989 6 discriminator 6 view .LVU229 + 788 001a 1432 adds r2, r2, #20 + 789 001c 9342 cmp r3, r2 + 790 001e 1FD0 beq .L46 + 791 .loc 1 1989 6 discriminator 8 view .LVU230 + 792 0020 1432 adds r2, r2, #20 + 793 0022 9342 cmp r3, r2 + 794 0024 1CD0 beq .L46 + 795 .loc 1 1989 6 discriminator 10 view .LVU231 + 796 0026 1432 adds r2, r2, #20 + 797 0028 9342 cmp r3, r2 + 798 002a 19D0 beq .L46 + 799 .loc 1 1989 6 discriminator 12 view .LVU232 + 800 002c 1432 adds r2, r2, #20 + 801 002e 9342 cmp r3, r2 + 802 0030 16D0 beq .L46 +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* BDMA Channels are connected to DMAMUX2 channels */ +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (str +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + 803 .loc 1 2000 5 is_stmt 1 view .LVU233 + 804 .loc 1 2000 61 is_stmt 0 view .LVU234 + 805 0032 DAB2 uxtb r2, r3 + 806 .loc 1 2000 70 view .LVU235 + 807 0034 103A subs r2, r2, #16 + 808 .loc 1 2000 19 view .LVU236 + 809 0036 1749 ldr r1, .L50+8 + 810 0038 A1FB0212 umull r1, r2, r1, r2 + 811 003c 1209 lsrs r2, r2, #4 + 812 .LVL51: +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ + 813 .loc 1 2002 5 is_stmt 1 view .LVU237 + 814 .loc 1 2002 58 is_stmt 0 view .LVU238 + 815 003e 1649 ldr r1, .L50+12 + 816 0040 1944 add r1, r1, r3 + 817 .loc 1 2002 7 view .LVU239 + 818 0042 A829 cmp r1, #168 + 819 0044 1FD9 bls .L47 + 820 .L48: +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** (stream_baseaddress >= ((uint32_t)DMA2_Stream0))) +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** stream_number += 8U; +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (str + 821 .loc 1 2007 5 is_stmt 1 view .LVU240 + 822 .loc 1 2007 54 is_stmt 0 view .LVU241 + ARM GAS /tmp/ccXv4DVv.s page 52 + + + 823 0046 154B ldr r3, .L50+16 + 824 .LVL52: + 825 .loc 1 2007 54 view .LVU242 + 826 0048 1344 add r3, r3, r2 + 827 004a 9B00 lsls r3, r3, #2 + 828 .loc 1 2007 25 view .LVU243 + 829 004c 0366 str r3, [r0, #96] +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + 830 .loc 1 2008 5 is_stmt 1 view .LVU244 + 831 .loc 1 2008 31 is_stmt 0 view .LVU245 + 832 004e 144B ldr r3, .L50+20 + 833 0050 4366 str r3, [r0, #100] +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + 834 .loc 1 2009 5 is_stmt 1 view .LVU246 + 835 .loc 1 2009 59 is_stmt 0 view .LVU247 + 836 0052 02F01F02 and r2, r2, #31 + 837 .LVL53: + 838 .loc 1 2009 41 view .LVU248 + 839 0056 0123 movs r3, #1 + 840 0058 03FA02F2 lsl r2, r3, r2 + 841 .loc 1 2009 35 view .LVU249 + 842 005c 8266 str r2, [r0, #104] +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 843 .loc 1 2011 1 view .LVU250 + 844 005e 7047 bx lr + 845 .LVL54: + 846 .L46: +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (str + 847 .loc 1 1992 5 is_stmt 1 view .LVU251 +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (str + 848 .loc 1 1992 61 is_stmt 0 view .LVU252 + 849 0060 DBB2 uxtb r3, r3 + 850 .LVL55: +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (str + 851 .loc 1 1992 70 view .LVU253 + 852 0062 083B subs r3, r3, #8 +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (str + 853 .loc 1 1992 19 view .LVU254 + 854 0064 0F4A ldr r2, .L50+24 + 855 0066 A2FB0323 umull r2, r3, r2, r3 + 856 .LVL56: +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + 857 .loc 1 1993 5 is_stmt 1 view .LVU255 +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + 858 .loc 1 1993 54 is_stmt 0 view .LVU256 + 859 006a 0F4A ldr r2, .L50+28 + 860 006c 02EB1312 add r2, r2, r3, lsr #4 + 861 0070 9200 lsls r2, r2, #2 +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + 862 .loc 1 1993 25 view .LVU257 + 863 0072 0266 str r2, [r0, #96] +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + 864 .loc 1 1994 5 is_stmt 1 view .LVU258 +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + 865 .loc 1 1994 31 is_stmt 0 view .LVU259 + 866 0074 0D4A ldr r2, .L50+32 + ARM GAS /tmp/ccXv4DVv.s page 53 + + + 867 0076 4266 str r2, [r0, #100] +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 868 .loc 1 1995 5 is_stmt 1 view .LVU260 +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 869 .loc 1 1995 59 is_stmt 0 view .LVU261 + 870 0078 C3F30413 ubfx r3, r3, #4, #5 + 871 .LVL57: +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 872 .loc 1 1995 41 view .LVU262 + 873 007c 0122 movs r2, #1 + 874 007e 02FA03F3 lsl r3, r2, r3 +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 875 .loc 1 1995 35 view .LVU263 + 876 0082 8366 str r3, [r0, #104] + 877 0084 7047 bx lr + 878 .LVL58: + 879 .L47: +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 880 .loc 1 2005 7 is_stmt 1 view .LVU264 +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 881 .loc 1 2005 21 is_stmt 0 view .LVU265 + 882 0086 0832 adds r2, r2, #8 + 883 .LVL59: +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 884 .loc 1 2005 21 view .LVU266 + 885 0088 DDE7 b .L48 + 886 .L51: + 887 008a 00BF .align 2 + 888 .L50: + 889 008c 08540258 .word 1476547592 + 890 0090 1C540258 .word 1476547612 + 891 0094 ABAAAAAA .word -1431655765 + 892 0098 F0FBFDBF .word -1073873936 + 893 009c 00820010 .word 268468736 + 894 00a0 80080240 .word 1073875072 + 895 00a4 CDCCCCCC .word -858993459 + 896 00a8 00960016 .word 369137152 + 897 00ac 80580258 .word 1476548736 + 898 .cfi_endproc + 899 .LFE156: + 901 .section .text.DMA_CalcDMAMUXRequestGenBaseAndMask,"ax",%progbits + 902 .align 1 + 903 .syntax unified + 904 .thumb + 905 .thumb_func + 906 .fpu fpv5-d16 + 908 DMA_CalcDMAMUXRequestGenBaseAndMask: + 909 .LVL60: + 910 .LFB157: +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /** +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @brief Updates the DMA handle with the DMAMUX request generator params +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** * @retval HAL status +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** */ +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) + ARM GAS /tmp/ccXv4DVv.s page 54 + + +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 911 .loc 1 2020 1 is_stmt 1 view -0 + 912 .cfi_startproc + 913 @ args = 0, pretend = 0, frame = 0 + 914 @ frame_needed = 0, uses_anonymous_args = 0 + 915 @ link register save eliminated. +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + 916 .loc 1 2021 3 view .LVU268 + 917 .loc 1 2021 12 is_stmt 0 view .LVU269 + 918 0000 0179 ldrb r1, [r0, #4] @ zero_extendqisi2 + 919 .LVL61: +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) + 920 .loc 1 2023 3 is_stmt 1 view .LVU270 + 921 .loc 1 2023 42 is_stmt 0 view .LVU271 + 922 0002 4A1E subs r2, r1, #1 + 923 .loc 1 2023 5 view .LVU272 + 924 0004 072A cmp r2, #7 + 925 0006 2CD8 bhi .L57 +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + 926 .loc 1 2020 1 view .LVU273 + 927 0008 30B4 push {r4, r5} + 928 .LCFI6: + 929 .cfi_def_cfa_offset 8 + 930 .cfi_offset 4, -8 + 931 .cfi_offset 5, -4 +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + 932 .loc 1 2025 5 is_stmt 1 view .LVU274 + 933 .loc 1 2025 8 is_stmt 0 view .LVU275 + 934 000a 0368 ldr r3, [r0] + 935 000c 154D ldr r5, .L60 + 936 000e 164C ldr r4, .L60+4 + 937 0010 A342 cmp r3, r4 + 938 0012 18BF it ne + 939 0014 AB42 cmpne r3, r5 + 940 0016 18D0 beq .L54 + 941 .loc 1 2025 8 discriminator 2 view .LVU276 + 942 0018 1434 adds r4, r4, #20 + 943 001a A342 cmp r3, r4 + 944 001c 15D0 beq .L54 + 945 .loc 1 2025 8 discriminator 4 view .LVU277 + 946 001e 1434 adds r4, r4, #20 + 947 0020 A342 cmp r3, r4 + 948 0022 12D0 beq .L54 + 949 .loc 1 2025 8 discriminator 6 view .LVU278 + 950 0024 1434 adds r4, r4, #20 + 951 0026 A342 cmp r3, r4 + 952 0028 0FD0 beq .L54 + 953 .loc 1 2025 8 discriminator 8 view .LVU279 + 954 002a 1434 adds r4, r4, #20 + 955 002c A342 cmp r3, r4 + 956 002e 0CD0 beq .L54 + 957 .loc 1 2025 8 discriminator 10 view .LVU280 + 958 0030 1434 adds r4, r4, #20 + 959 0032 A342 cmp r3, r4 + 960 0034 09D0 beq .L54 + ARM GAS /tmp/ccXv4DVv.s page 55 + + + 961 .loc 1 2025 8 discriminator 12 view .LVU281 + 962 0036 1434 adds r4, r4, #20 + 963 0038 A342 cmp r3, r4 + 964 003a 06D0 beq .L54 +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* BDMA Channels are connected to DMAMUX2 request generator blocks */ +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestG +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** else +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestG + 965 .loc 1 2035 7 is_stmt 1 view .LVU282 + 966 .loc 1 2035 62 is_stmt 0 view .LVU283 + 967 003c 0B4B ldr r3, .L60+8 + 968 003e 0B44 add r3, r3, r1 + 969 0040 9B00 lsls r3, r3, #2 + 970 .loc 1 2035 30 view .LVU284 + 971 0042 C366 str r3, [r0, #108] +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + 972 .loc 1 2037 7 is_stmt 1 view .LVU285 + 973 .loc 1 2037 36 is_stmt 0 view .LVU286 + 974 0044 0A4B ldr r3, .L60+12 + 975 0046 0367 str r3, [r0, #112] + 976 0048 05E0 b .L55 + 977 .L54: +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 978 .loc 1 2028 7 is_stmt 1 view .LVU287 +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 979 .loc 1 2028 62 is_stmt 0 view .LVU288 + 980 004a 0A4B ldr r3, .L60+16 + 981 004c 0B44 add r3, r3, r1 + 982 004e 9B00 lsls r3, r3, #2 +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 983 .loc 1 2028 30 view .LVU289 + 984 0050 C366 str r3, [r0, #108] +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 985 .loc 1 2030 7 is_stmt 1 view .LVU290 +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 986 .loc 1 2030 36 is_stmt 0 view .LVU291 + 987 0052 094B ldr r3, .L60+20 + 988 0054 0367 str r3, [r0, #112] + 989 .L55: +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); + 990 .loc 1 2040 5 is_stmt 1 view .LVU292 + 991 .loc 1 2040 44 is_stmt 0 view .LVU293 + 992 0056 0123 movs r3, #1 + 993 0058 03FA02F2 lsl r2, r3, r2 + 994 .loc 1 2040 38 view .LVU294 + 995 005c 4267 str r2, [r0, #116] +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 56 + + + 996 .loc 1 2042 1 view .LVU295 + 997 005e 30BC pop {r4, r5} + 998 .LCFI7: + 999 .cfi_restore 5 + 1000 .cfi_restore 4 + 1001 .cfi_def_cfa_offset 0 + 1002 0060 7047 bx lr + 1003 .L57: + 1004 .loc 1 2042 1 view .LVU296 + 1005 0062 7047 bx lr + 1006 .L61: + 1007 .align 2 + 1008 .L60: + 1009 0064 08540258 .word 1476547592 + 1010 0068 1C540258 .word 1476547612 + 1011 006c 3F820010 .word 268468799 + 1012 0070 40090240 .word 1073875264 + 1013 0074 3F960016 .word 369137215 + 1014 0078 40590258 .word 1476548928 + 1015 .cfi_endproc + 1016 .LFE157: + 1018 .section .text.HAL_DMA_Init,"ax",%progbits + 1019 .align 1 + 1020 .global HAL_DMA_Init + 1021 .syntax unified + 1022 .thumb + 1023 .thumb_func + 1024 .fpu fpv5-d16 + 1026 HAL_DMA_Init: + 1027 .LVL62: + 1028 .LFB141: + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t registerValue; + 1029 .loc 1 212 1 is_stmt 1 view -0 + 1030 .cfi_startproc + 1031 @ args = 0, pretend = 0, frame = 0 + 1032 @ frame_needed = 0, uses_anonymous_args = 0 + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t registerValue; + 1033 .loc 1 212 1 is_stmt 0 view .LVU298 + 1034 0000 70B5 push {r4, r5, r6, lr} + 1035 .LCFI8: + 1036 .cfi_def_cfa_offset 16 + 1037 .cfi_offset 4, -16 + 1038 .cfi_offset 5, -12 + 1039 .cfi_offset 6, -8 + 1040 .cfi_offset 14, -4 + 1041 0002 0446 mov r4, r0 + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 1042 .loc 1 213 3 is_stmt 1 view .LVU299 + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 1043 .loc 1 214 3 view .LVU300 + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 1044 .loc 1 214 24 is_stmt 0 view .LVU301 + 1045 0004 FFF7FEFF bl HAL_GetTick + 1046 .LVL63: + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 1047 .loc 1 215 3 is_stmt 1 view .LVU302 + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 57 + + + 1048 .loc 1 216 3 view .LVU303 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1049 .loc 1 219 3 view .LVU304 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1050 .loc 1 219 5 is_stmt 0 view .LVU305 + 1051 0008 002C cmp r4, #0 + 1052 000a 00F0B681 beq .L82 + 1053 000e 0546 mov r5, r0 + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 1054 .loc 1 225 3 is_stmt 1 view .LVU306 + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 1055 .loc 1 226 3 view .LVU307 + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 1056 .loc 1 227 3 view .LVU308 + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 1057 .loc 1 228 3 view .LVU309 + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 1058 .loc 1 229 3 view .LVU310 + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 1059 .loc 1 230 3 view .LVU311 + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 1060 .loc 1 231 3 view .LVU312 + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1061 .loc 1 232 3 view .LVU313 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1062 .loc 1 234 3 view .LVU314 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1063 .loc 1 234 6 is_stmt 0 view .LVU315 + 1064 0010 2368 ldr r3, [r4] + 1065 0012 5349 ldr r1, .L93 + 1066 0014 534A ldr r2, .L93+4 + 1067 0016 9342 cmp r3, r2 + 1068 0018 18BF it ne + 1069 001a 8B42 cmpne r3, r1 + 1070 001c 0CBF ite eq + 1071 001e 0122 moveq r2, #1 + 1072 0020 0022 movne r2, #0 + 1073 0022 50D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1074 .loc 1 234 6 discriminator 2 view .LVU316 + 1075 0024 3031 adds r1, r1, #48 + 1076 0026 8B42 cmp r3, r1 + 1077 0028 4DD0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1078 .loc 1 234 6 discriminator 4 view .LVU317 + 1079 002a 1831 adds r1, r1, #24 + 1080 002c 8B42 cmp r3, r1 + 1081 002e 4AD0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1082 .loc 1 234 6 discriminator 6 view .LVU318 + 1083 0030 1831 adds r1, r1, #24 + 1084 0032 8B42 cmp r3, r1 + 1085 0034 47D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1086 .loc 1 234 6 discriminator 8 view .LVU319 + 1087 0036 1831 adds r1, r1, #24 + 1088 0038 8B42 cmp r3, r1 + ARM GAS /tmp/ccXv4DVv.s page 58 + + + 1089 003a 44D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1090 .loc 1 234 6 discriminator 10 view .LVU320 + 1091 003c 1831 adds r1, r1, #24 + 1092 003e 8B42 cmp r3, r1 + 1093 0040 41D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1094 .loc 1 234 6 discriminator 12 view .LVU321 + 1095 0042 1831 adds r1, r1, #24 + 1096 0044 8B42 cmp r3, r1 + 1097 0046 3ED0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1098 .loc 1 234 6 discriminator 14 view .LVU322 + 1099 0048 01F55671 add r1, r1, #856 + 1100 004c 8B42 cmp r3, r1 + 1101 004e 3AD0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1102 .loc 1 234 6 discriminator 16 view .LVU323 + 1103 0050 1831 adds r1, r1, #24 + 1104 0052 8B42 cmp r3, r1 + 1105 0054 37D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1106 .loc 1 234 6 discriminator 18 view .LVU324 + 1107 0056 1831 adds r1, r1, #24 + 1108 0058 8B42 cmp r3, r1 + 1109 005a 34D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1110 .loc 1 234 6 discriminator 20 view .LVU325 + 1111 005c 1831 adds r1, r1, #24 + 1112 005e 8B42 cmp r3, r1 + 1113 0060 31D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1114 .loc 1 234 6 discriminator 22 view .LVU326 + 1115 0062 1831 adds r1, r1, #24 + 1116 0064 8B42 cmp r3, r1 + 1117 0066 2ED0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1118 .loc 1 234 6 discriminator 24 view .LVU327 + 1119 0068 1831 adds r1, r1, #24 + 1120 006a 8B42 cmp r3, r1 + 1121 006c 2BD0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1122 .loc 1 234 6 discriminator 26 view .LVU328 + 1123 006e 1831 adds r1, r1, #24 + 1124 0070 8B42 cmp r3, r1 + 1125 0072 28D0 beq .L64 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1126 .loc 1 234 6 discriminator 28 view .LVU329 + 1127 0074 1831 adds r1, r1, #24 + 1128 0076 8B42 cmp r3, r1 + 1129 0078 25D0 beq .L64 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1130 .loc 1 353 8 is_stmt 1 view .LVU330 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1131 .loc 1 353 11 is_stmt 0 view .LVU331 + 1132 007a 3B49 ldr r1, .L93+8 + 1133 007c 3B4A ldr r2, .L93+12 + ARM GAS /tmp/ccXv4DVv.s page 59 + + + 1134 007e 9342 cmp r3, r2 + 1135 0080 18BF it ne + 1136 0082 8B42 cmpne r3, r1 + 1137 0084 00F03181 beq .L65 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1138 .loc 1 353 11 discriminator 2 view .LVU332 + 1139 0088 394A ldr r2, .L93+16 + 1140 008a 9342 cmp r3, r2 + 1141 008c 00F02D81 beq .L65 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1142 .loc 1 353 11 discriminator 4 view .LVU333 + 1143 0090 1432 adds r2, r2, #20 + 1144 0092 9342 cmp r3, r2 + 1145 0094 00F02981 beq .L65 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1146 .loc 1 353 11 discriminator 6 view .LVU334 + 1147 0098 1432 adds r2, r2, #20 + 1148 009a 9342 cmp r3, r2 + 1149 009c 00F02581 beq .L65 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1150 .loc 1 353 11 discriminator 8 view .LVU335 + 1151 00a0 1432 adds r2, r2, #20 + 1152 00a2 9342 cmp r3, r2 + 1153 00a4 00F02181 beq .L65 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1154 .loc 1 353 11 discriminator 10 view .LVU336 + 1155 00a8 1432 adds r2, r2, #20 + 1156 00aa 9342 cmp r3, r2 + 1157 00ac 00F01D81 beq .L65 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1158 .loc 1 353 11 discriminator 12 view .LVU337 + 1159 00b0 1432 adds r2, r2, #20 + 1160 00b2 9342 cmp r3, r2 + 1161 00b4 00F01981 beq .L65 + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; + 1162 .loc 1 400 5 is_stmt 1 view .LVU338 + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ERROR; + 1163 .loc 1 400 21 is_stmt 0 view .LVU339 + 1164 00b8 4023 movs r3, #64 + 1165 00ba 6365 str r3, [r4, #84] + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1166 .loc 1 401 5 is_stmt 1 view .LVU340 + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1167 .loc 1 401 21 is_stmt 0 view .LVU341 + 1168 00bc 0323 movs r3, #3 + 1169 00be 84F83530 strb r3, [r4, #53] + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1170 .loc 1 403 5 is_stmt 1 view .LVU342 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1171 .loc 1 403 12 is_stmt 0 view .LVU343 + 1172 00c2 0120 movs r0, #1 + 1173 .LVL64: + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1174 .loc 1 403 12 view .LVU344 + 1175 00c4 4AE0 b .L63 + 1176 .LVL65: + 1177 .L64: + ARM GAS /tmp/ccXv4DVv.s page 60 + + + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + 1178 .loc 1 236 5 is_stmt 1 view .LVU345 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* Check the memory burst, peripheral burst and FIFO threshold parameters only + 1179 .loc 1 237 5 view .LVU346 + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1180 .loc 1 240 5 view .LVU347 + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + 1181 .loc 1 242 7 view .LVU348 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + 1182 .loc 1 243 7 view .LVU349 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1183 .loc 1 244 7 view .LVU350 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1184 .loc 1 248 5 view .LVU351 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1185 .loc 1 248 5 view .LVU352 + 1186 00c6 0021 movs r1, #0 + 1187 00c8 84F83410 strb r1, [r4, #52] + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1188 .loc 1 248 5 view .LVU353 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1189 .loc 1 251 5 view .LVU354 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1190 .loc 1 251 17 is_stmt 0 view .LVU355 + 1191 00cc 0221 movs r1, #2 + 1192 00ce 84F83510 strb r1, [r4, #53] + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1193 .loc 1 254 5 is_stmt 1 view .LVU356 + 1194 00d2 7ABB cbnz r2, .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1195 .loc 1 254 5 is_stmt 0 discriminator 2 view .LVU357 + 1196 00d4 274A ldr r2, .L93+20 + 1197 00d6 9342 cmp r3, r2 + 1198 00d8 2CD0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1199 .loc 1 254 5 discriminator 4 view .LVU358 + 1200 00da 1832 adds r2, r2, #24 + 1201 00dc 9342 cmp r3, r2 + 1202 00de 29D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1203 .loc 1 254 5 discriminator 6 view .LVU359 + 1204 00e0 1832 adds r2, r2, #24 + 1205 00e2 9342 cmp r3, r2 + 1206 00e4 26D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1207 .loc 1 254 5 discriminator 8 view .LVU360 + 1208 00e6 1832 adds r2, r2, #24 + 1209 00e8 9342 cmp r3, r2 + 1210 00ea 23D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1211 .loc 1 254 5 discriminator 10 view .LVU361 + 1212 00ec 1832 adds r2, r2, #24 + 1213 00ee 9342 cmp r3, r2 + 1214 00f0 20D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1215 .loc 1 254 5 discriminator 12 view .LVU362 + 1216 00f2 1832 adds r2, r2, #24 + ARM GAS /tmp/ccXv4DVv.s page 61 + + + 1217 00f4 9342 cmp r3, r2 + 1218 00f6 1DD0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1219 .loc 1 254 5 discriminator 14 view .LVU363 + 1220 00f8 02F55672 add r2, r2, #856 + 1221 00fc 9342 cmp r3, r2 + 1222 00fe 19D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1223 .loc 1 254 5 discriminator 16 view .LVU364 + 1224 0100 1832 adds r2, r2, #24 + 1225 0102 9342 cmp r3, r2 + 1226 0104 16D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1227 .loc 1 254 5 discriminator 18 view .LVU365 + 1228 0106 1832 adds r2, r2, #24 + 1229 0108 9342 cmp r3, r2 + 1230 010a 13D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1231 .loc 1 254 5 discriminator 20 view .LVU366 + 1232 010c 1832 adds r2, r2, #24 + 1233 010e 9342 cmp r3, r2 + 1234 0110 10D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1235 .loc 1 254 5 discriminator 22 view .LVU367 + 1236 0112 1832 adds r2, r2, #24 + 1237 0114 9342 cmp r3, r2 + 1238 0116 0DD0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1239 .loc 1 254 5 discriminator 24 view .LVU368 + 1240 0118 1832 adds r2, r2, #24 + 1241 011a 9342 cmp r3, r2 + 1242 011c 0AD0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1243 .loc 1 254 5 discriminator 26 view .LVU369 + 1244 011e 1832 adds r2, r2, #24 + 1245 0120 9342 cmp r3, r2 + 1246 0122 07D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1247 .loc 1 254 5 discriminator 28 view .LVU370 + 1248 0124 1832 adds r2, r2, #24 + 1249 0126 9342 cmp r3, r2 + 1250 0128 04D0 beq .L67 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1251 .loc 1 254 5 discriminator 30 view .LVU371 + 1252 012a 1A68 ldr r2, [r3] + 1253 012c 22F00102 bic r2, r2, #1 + 1254 0130 1A60 str r2, [r3] + 1255 0132 03E0 b .L70 + 1256 .L67: + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1257 .loc 1 254 5 discriminator 29 view .LVU372 + 1258 0134 1A68 ldr r2, [r3] + 1259 0136 22F00102 bic r2, r2, #1 + 1260 013a 1A60 str r2, [r3] + 1261 .LVL66: + 1262 .L70: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 62 + + + 1263 .loc 1 257 10 is_stmt 1 view .LVU373 + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1264 .loc 1 257 41 is_stmt 0 view .LVU374 + 1265 013c 2368 ldr r3, [r4] + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1266 .loc 1 257 52 view .LVU375 + 1267 013e 1A68 ldr r2, [r3] + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1268 .loc 1 257 10 view .LVU376 + 1269 0140 12F0010F tst r2, #1 + 1270 0144 18D0 beq .L87 + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1271 .loc 1 260 7 is_stmt 1 view .LVU377 + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1272 .loc 1 260 11 is_stmt 0 view .LVU378 + 1273 0146 FFF7FEFF bl HAL_GetTick + 1274 .LVL67: + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1275 .loc 1 260 25 view .LVU379 + 1276 014a 431B subs r3, r0, r5 + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1277 .loc 1 260 9 view .LVU380 + 1278 014c 052B cmp r3, #5 + 1279 014e F5D9 bls .L70 + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1280 .loc 1 263 9 is_stmt 1 view .LVU381 + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1281 .loc 1 263 25 is_stmt 0 view .LVU382 + 1282 0150 2023 movs r3, #32 + 1283 0152 6365 str r3, [r4, #84] + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1284 .loc 1 266 9 is_stmt 1 view .LVU383 + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1285 .loc 1 266 21 is_stmt 0 view .LVU384 + 1286 0154 0323 movs r3, #3 + 1287 0156 84F83530 strb r3, [r4, #53] + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1288 .loc 1 268 9 is_stmt 1 view .LVU385 + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1289 .loc 1 268 16 is_stmt 0 view .LVU386 + 1290 015a 0120 movs r0, #1 + 1291 .LVL68: + 1292 .L63: + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1293 .loc 1 455 1 view .LVU387 + 1294 015c 70BD pop {r4, r5, r6, pc} + 1295 .LVL69: + 1296 .L94: + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1297 .loc 1 455 1 view .LVU388 + 1298 015e 00BF .align 2 + 1299 .L93: + 1300 0160 10000240 .word 1073872912 + 1301 0164 28000240 .word 1073872936 + 1302 0168 08540258 .word 1476547592 + 1303 016c 1C540258 .word 1476547612 + 1304 0170 30540258 .word 1476547632 + ARM GAS /tmp/ccXv4DVv.s page 63 + + + 1305 0174 40000240 .word 1073872960 + 1306 .LVL70: + 1307 .L87: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1308 .loc 1 273 5 is_stmt 1 view .LVU389 + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1309 .loc 1 273 19 is_stmt 0 view .LVU390 + 1310 0178 1A68 ldr r2, [r3] + 1311 .LVL71: + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + 1312 .loc 1 276 5 is_stmt 1 view .LVU391 + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + 1313 .loc 1 276 19 is_stmt 0 view .LVU392 + 1314 017a 8148 ldr r0, .L95 + 1315 017c 1040 ands r0, r0, r2 + 1316 .LVL72: + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 1317 .loc 1 282 5 is_stmt 1 view .LVU393 + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 1318 .loc 1 282 33 is_stmt 0 view .LVU394 + 1319 017e A168 ldr r1, [r4, #8] + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 1320 .loc 1 283 23 view .LVU395 + 1321 0180 E268 ldr r2, [r4, #12] + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 1322 .loc 1 282 54 view .LVU396 + 1323 0182 0A43 orrs r2, r2, r1 + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 1324 .loc 1 283 56 view .LVU397 + 1325 0184 2169 ldr r1, [r4, #16] + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 1326 .loc 1 283 44 view .LVU398 + 1327 0186 0A43 orrs r2, r2, r1 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 1328 .loc 1 284 23 view .LVU399 + 1329 0188 6169 ldr r1, [r4, #20] + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 1330 .loc 1 283 74 view .LVU400 + 1331 018a 0A43 orrs r2, r2, r1 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 1332 .loc 1 284 56 view .LVU401 + 1333 018c A169 ldr r1, [r4, #24] + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 1334 .loc 1 284 44 view .LVU402 + 1335 018e 0A43 orrs r2, r2, r1 + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1336 .loc 1 285 23 view .LVU403 + 1337 0190 E169 ldr r1, [r4, #28] + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 1338 .loc 1 284 74 view .LVU404 + 1339 0192 0A43 orrs r2, r2, r1 + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1340 .loc 1 285 56 view .LVU405 + 1341 0194 216A ldr r1, [r4, #32] + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1342 .loc 1 285 44 view .LVU406 + 1343 0196 0A43 orrs r2, r2, r1 + ARM GAS /tmp/ccXv4DVv.s page 64 + + + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 1344 .loc 1 282 19 view .LVU407 + 1345 0198 0243 orrs r2, r2, r0 + 1346 .LVL73: + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1347 .loc 1 288 5 is_stmt 1 view .LVU408 + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1348 .loc 1 288 18 is_stmt 0 view .LVU409 + 1349 019a 616A ldr r1, [r4, #36] + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1350 .loc 1 288 7 view .LVU410 + 1351 019c 0429 cmp r1, #4 + 1352 019e 00F09980 beq .L88 + 1353 .L72: + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1354 .loc 1 297 5 is_stmt 1 view .LVU411 + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1355 .loc 1 297 15 is_stmt 0 view .LVU412 + 1356 01a2 7849 ldr r1, .L95+4 + 1357 01a4 0868 ldr r0, [r1] + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1358 .loc 1 297 24 view .LVU413 + 1359 01a6 7849 ldr r1, .L95+8 + 1360 01a8 0140 ands r1, r1, r0 + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1361 .loc 1 297 7 view .LVU414 + 1362 01aa B1F1005F cmp r1, #536870912 + 1363 01ae 11D3 bcc .L73 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1364 .loc 1 300 7 is_stmt 1 view .LVU415 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1365 .loc 1 300 10 is_stmt 0 view .LVU416 + 1366 01b0 6168 ldr r1, [r4, #4] + 1367 01b2 A1F12905 sub r5, r1, #41 + 1368 .LVL74: + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1369 .loc 1 300 10 view .LVU417 + 1370 01b6 A1F13F00 sub r0, r1, #63 + 1371 01ba 0328 cmp r0, #3 + 1372 01bc 88BF it hi + 1373 01be 052D cmphi r5, #5 + 1374 01c0 06D9 bls .L74 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1375 .loc 1 300 10 discriminator 2 view .LVU418 + 1376 01c2 A1F14700 sub r0, r1, #71 + 1377 01c6 0128 cmp r0, #1 + 1378 01c8 02D9 bls .L74 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1379 .loc 1 300 10 discriminator 4 view .LVU419 + 1380 01ca 4F39 subs r1, r1, #79 + 1381 01cc 0329 cmp r1, #3 + 1382 01ce 01D8 bhi .L73 + 1383 .L74: + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1384 .loc 1 302 9 is_stmt 1 view .LVU420 + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1385 .loc 1 302 23 is_stmt 0 view .LVU421 + ARM GAS /tmp/ccXv4DVv.s page 65 + + + 1386 01d0 42F48012 orr r2, r2, #1048576 + 1387 .LVL75: + 1388 .L73: + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1389 .loc 1 309 5 is_stmt 1 view .LVU422 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1390 .loc 1 309 50 is_stmt 0 view .LVU423 + 1391 01d4 1A60 str r2, [r3] + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1392 .loc 1 312 5 is_stmt 1 view .LVU424 + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1393 .loc 1 312 50 is_stmt 0 view .LVU425 + 1394 01d6 2668 ldr r6, [r4] + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1395 .loc 1 312 19 view .LVU426 + 1396 01d8 7569 ldr r5, [r6, #20] + 1397 .LVL76: + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1398 .loc 1 315 5 is_stmt 1 view .LVU427 + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1399 .loc 1 315 19 is_stmt 0 view .LVU428 + 1400 01da 25F00705 bic r5, r5, #7 + 1401 .LVL77: + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1402 .loc 1 318 5 is_stmt 1 view .LVU429 + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1403 .loc 1 318 32 is_stmt 0 view .LVU430 + 1404 01de 636A ldr r3, [r4, #36] + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1405 .loc 1 318 19 view .LVU431 + 1406 01e0 1D43 orrs r5, r5, r3 + 1407 .LVL78: + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1408 .loc 1 321 5 is_stmt 1 view .LVU432 + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1409 .loc 1 321 7 is_stmt 0 view .LVU433 + 1410 01e2 042B cmp r3, #4 + 1411 01e4 08D1 bne .L75 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1412 .loc 1 324 7 is_stmt 1 view .LVU434 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1413 .loc 1 324 34 is_stmt 0 view .LVU435 + 1414 01e6 A36A ldr r3, [r4, #40] + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1415 .loc 1 324 21 view .LVU436 + 1416 01e8 1D43 orrs r5, r5, r3 + 1417 .LVL79: + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1418 .loc 1 328 7 is_stmt 1 view .LVU437 + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1419 .loc 1 328 20 is_stmt 0 view .LVU438 + 1420 01ea E36A ldr r3, [r4, #44] + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1421 .loc 1 328 9 view .LVU439 + 1422 01ec 23B1 cbz r3, .L75 + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1423 .loc 1 330 9 is_stmt 1 view .LVU440 + ARM GAS /tmp/ccXv4DVv.s page 66 + + + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1424 .loc 1 330 13 is_stmt 0 view .LVU441 + 1425 01ee 2046 mov r0, r4 + 1426 01f0 FFF7FEFF bl DMA_CheckFifoParam + 1427 .LVL80: + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1428 .loc 1 330 12 view .LVU442 + 1429 01f4 0028 cmp r0, #0 + 1430 01f6 72D1 bne .L89 + 1431 .L75: + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1432 .loc 1 344 5 is_stmt 1 view .LVU443 + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1433 .loc 1 344 51 is_stmt 0 view .LVU444 + 1434 01f8 7561 str r5, [r6, #20] + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1435 .loc 1 348 5 is_stmt 1 view .LVU445 + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1436 .loc 1 348 38 is_stmt 0 view .LVU446 + 1437 01fa 2046 mov r0, r4 + 1438 01fc FFF7FEFF bl DMA_CalcBaseAndBitshift + 1439 .LVL81: + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1440 .loc 1 351 5 is_stmt 1 view .LVU447 + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1441 .loc 1 351 37 is_stmt 0 view .LVU448 + 1442 0200 E36D ldr r3, [r4, #92] + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1443 .loc 1 351 51 view .LVU449 + 1444 0202 03F01F02 and r2, r3, #31 + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1445 .loc 1 351 29 view .LVU450 + 1446 0206 3F23 movs r3, #63 + 1447 0208 9340 lsls r3, r3, r2 + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1448 .loc 1 351 20 view .LVU451 + 1449 020a 8360 str r3, [r0, #8] + 1450 .LVL82: + 1451 .L76: + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1452 .loc 1 406 3 is_stmt 1 view .LVU452 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1453 .loc 1 406 6 is_stmt 0 view .LVU453 + 1454 020c 2368 ldr r3, [r4] + 1455 020e 5F49 ldr r1, .L95+12 + 1456 0210 5F4A ldr r2, .L95+16 + 1457 0212 9342 cmp r3, r2 + 1458 0214 18BF it ne + 1459 0216 8B42 cmpne r3, r1 + 1460 0218 42D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1461 .loc 1 406 6 discriminator 2 view .LVU454 + 1462 021a 1832 adds r2, r2, #24 + 1463 021c 9342 cmp r3, r2 + 1464 021e 3FD0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1465 .loc 1 406 6 discriminator 4 view .LVU455 + ARM GAS /tmp/ccXv4DVv.s page 67 + + + 1466 0220 1832 adds r2, r2, #24 + 1467 0222 9342 cmp r3, r2 + 1468 0224 3CD0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1469 .loc 1 406 6 discriminator 6 view .LVU456 + 1470 0226 1832 adds r2, r2, #24 + 1471 0228 9342 cmp r3, r2 + 1472 022a 39D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1473 .loc 1 406 6 discriminator 8 view .LVU457 + 1474 022c 1832 adds r2, r2, #24 + 1475 022e 9342 cmp r3, r2 + 1476 0230 36D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1477 .loc 1 406 6 discriminator 10 view .LVU458 + 1478 0232 1832 adds r2, r2, #24 + 1479 0234 9342 cmp r3, r2 + 1480 0236 33D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1481 .loc 1 406 6 discriminator 12 view .LVU459 + 1482 0238 1832 adds r2, r2, #24 + 1483 023a 9342 cmp r3, r2 + 1484 023c 30D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1485 .loc 1 406 6 discriminator 14 view .LVU460 + 1486 023e 02F55672 add r2, r2, #856 + 1487 0242 9342 cmp r3, r2 + 1488 0244 2CD0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1489 .loc 1 406 6 discriminator 16 view .LVU461 + 1490 0246 1832 adds r2, r2, #24 + 1491 0248 9342 cmp r3, r2 + 1492 024a 29D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1493 .loc 1 406 6 discriminator 18 view .LVU462 + 1494 024c 1832 adds r2, r2, #24 + 1495 024e 9342 cmp r3, r2 + 1496 0250 26D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1497 .loc 1 406 6 discriminator 20 view .LVU463 + 1498 0252 1832 adds r2, r2, #24 + 1499 0254 9342 cmp r3, r2 + 1500 0256 23D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1501 .loc 1 406 6 discriminator 22 view .LVU464 + 1502 0258 1832 adds r2, r2, #24 + 1503 025a 9342 cmp r3, r2 + 1504 025c 20D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1505 .loc 1 406 6 discriminator 24 view .LVU465 + 1506 025e 1832 adds r2, r2, #24 + 1507 0260 9342 cmp r3, r2 + 1508 0262 1DD0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1509 .loc 1 406 6 discriminator 26 view .LVU466 + 1510 0264 1832 adds r2, r2, #24 + 1511 0266 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 68 + + + 1512 0268 1AD0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1513 .loc 1 406 6 discriminator 28 view .LVU467 + 1514 026a 1832 adds r2, r2, #24 + 1515 026c 9342 cmp r3, r2 + 1516 026e 17D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1517 .loc 1 406 6 discriminator 30 view .LVU468 + 1518 0270 484A ldr r2, .L95+20 + 1519 0272 9342 cmp r3, r2 + 1520 0274 14D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1521 .loc 1 406 6 discriminator 32 view .LVU469 + 1522 0276 1432 adds r2, r2, #20 + 1523 0278 9342 cmp r3, r2 + 1524 027a 11D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1525 .loc 1 406 6 discriminator 34 view .LVU470 + 1526 027c 1432 adds r2, r2, #20 + 1527 027e 9342 cmp r3, r2 + 1528 0280 0ED0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1529 .loc 1 406 6 discriminator 36 view .LVU471 + 1530 0282 1432 adds r2, r2, #20 + 1531 0284 9342 cmp r3, r2 + 1532 0286 0BD0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1533 .loc 1 406 6 discriminator 38 view .LVU472 + 1534 0288 1432 adds r2, r2, #20 + 1535 028a 9342 cmp r3, r2 + 1536 028c 08D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1537 .loc 1 406 6 discriminator 40 view .LVU473 + 1538 028e 1432 adds r2, r2, #20 + 1539 0290 9342 cmp r3, r2 + 1540 0292 05D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1541 .loc 1 406 6 discriminator 42 view .LVU474 + 1542 0294 1432 adds r2, r2, #20 + 1543 0296 9342 cmp r3, r2 + 1544 0298 02D0 beq .L78 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1545 .loc 1 406 6 discriminator 44 view .LVU475 + 1546 029a 1432 adds r2, r2, #20 + 1547 029c 9342 cmp r3, r2 + 1548 029e 13D1 bne .L79 + 1549 .L78: + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1550 .loc 1 411 5 is_stmt 1 view .LVU476 + 1551 02a0 2046 mov r0, r4 + 1552 02a2 FFF7FEFF bl DMA_CalcDMAMUXChannelBaseAndMask + 1553 .LVL83: + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1554 .loc 1 413 5 view .LVU477 + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1555 .loc 1 413 18 is_stmt 0 view .LVU478 + 1556 02a6 A368 ldr r3, [r4, #8] + ARM GAS /tmp/ccXv4DVv.s page 69 + + + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1557 .loc 1 413 7 view .LVU479 + 1558 02a8 802B cmp r3, #128 + 1559 02aa 59D0 beq .L90 + 1560 .L80: + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1561 .loc 1 420 5 is_stmt 1 view .LVU480 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1562 .loc 1 420 9 is_stmt 0 view .LVU481 + 1563 02ac 236E ldr r3, [r4, #96] + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1564 .loc 1 420 52 view .LVU482 + 1565 02ae 2279 ldrb r2, [r4, #4] @ zero_extendqisi2 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1566 .loc 1 420 30 view .LVU483 + 1567 02b0 1A60 str r2, [r3] + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1568 .loc 1 423 5 is_stmt 1 view .LVU484 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1569 .loc 1 423 9 is_stmt 0 view .LVU485 + 1570 02b2 636E ldr r3, [r4, #100] + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1571 .loc 1 423 42 view .LVU486 + 1572 02b4 A26E ldr r2, [r4, #104] + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1573 .loc 1 423 36 view .LVU487 + 1574 02b6 5A60 str r2, [r3, #4] + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1575 .loc 1 428 5 is_stmt 1 view .LVU488 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1576 .loc 1 428 19 is_stmt 0 view .LVU489 + 1577 02b8 6368 ldr r3, [r4, #4] + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1578 .loc 1 428 55 view .LVU490 + 1579 02ba 013B subs r3, r3, #1 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1580 .loc 1 428 7 view .LVU491 + 1581 02bc 072B cmp r3, #7 + 1582 02be 52D9 bls .L91 + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 1583 .loc 1 442 7 is_stmt 1 view .LVU492 + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 1584 .loc 1 442 30 is_stmt 0 view .LVU493 + 1585 02c0 0023 movs r3, #0 + 1586 02c2 E366 str r3, [r4, #108] + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 1587 .loc 1 443 7 is_stmt 1 view .LVU494 + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 1588 .loc 1 443 36 is_stmt 0 view .LVU495 + 1589 02c4 2367 str r3, [r4, #112] + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1590 .loc 1 444 7 is_stmt 1 view .LVU496 + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1591 .loc 1 444 40 is_stmt 0 view .LVU497 + 1592 02c6 6367 str r3, [r4, #116] + 1593 .L79: + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 70 + + + 1594 .loc 1 449 3 is_stmt 1 view .LVU498 + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1595 .loc 1 449 19 is_stmt 0 view .LVU499 + 1596 02c8 0020 movs r0, #0 + 1597 02ca 6065 str r0, [r4, #84] + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1598 .loc 1 452 3 is_stmt 1 view .LVU500 + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1599 .loc 1 452 15 is_stmt 0 view .LVU501 + 1600 02cc 0123 movs r3, #1 + 1601 02ce 84F83530 strb r3, [r4, #53] + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1602 .loc 1 454 3 is_stmt 1 view .LVU502 + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1603 .loc 1 454 10 is_stmt 0 view .LVU503 + 1604 02d2 43E7 b .L63 + 1605 .LVL84: + 1606 .L88: + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1607 .loc 1 291 7 is_stmt 1 view .LVU504 + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1608 .loc 1 291 35 is_stmt 0 view .LVU505 + 1609 02d4 E16A ldr r1, [r4, #44] + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1610 .loc 1 291 57 view .LVU506 + 1611 02d6 206B ldr r0, [r4, #48] + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1612 .loc 1 291 45 view .LVU507 + 1613 02d8 0143 orrs r1, r1, r0 + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1614 .loc 1 291 21 view .LVU508 + 1615 02da 0A43 orrs r2, r2, r1 + 1616 .LVL85: + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1617 .loc 1 291 21 view .LVU509 + 1618 02dc 61E7 b .L72 + 1619 .LVL86: + 1620 .L89: + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1621 .loc 1 333 11 is_stmt 1 view .LVU510 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1622 .loc 1 333 27 is_stmt 0 view .LVU511 + 1623 02de 4023 movs r3, #64 + 1624 02e0 6365 str r3, [r4, #84] + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1625 .loc 1 336 11 is_stmt 1 view .LVU512 + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1626 .loc 1 336 23 is_stmt 0 view .LVU513 + 1627 02e2 0120 movs r0, #1 + 1628 02e4 84F83500 strb r0, [r4, #53] + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1629 .loc 1 338 11 is_stmt 1 view .LVU514 + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1630 .loc 1 338 18 is_stmt 0 view .LVU515 + 1631 02e8 38E7 b .L63 + 1632 .LVL87: + 1633 .L65: + ARM GAS /tmp/ccXv4DVv.s page 71 + + + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1634 .loc 1 355 5 is_stmt 1 view .LVU516 + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1635 .loc 1 358 7 view .LVU517 + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1636 .loc 1 362 5 view .LVU518 + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1637 .loc 1 362 5 view .LVU519 + 1638 02ea 0022 movs r2, #0 + 1639 02ec 84F83420 strb r2, [r4, #52] + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1640 .loc 1 362 5 view .LVU520 + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1641 .loc 1 365 5 view .LVU521 + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1642 .loc 1 365 17 is_stmt 0 view .LVU522 + 1643 02f0 0222 movs r2, #2 + 1644 02f2 84F83520 strb r2, [r4, #53] + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1645 .loc 1 368 5 is_stmt 1 view .LVU523 + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1646 .loc 1 368 19 is_stmt 0 view .LVU524 + 1647 02f6 1A68 ldr r2, [r3] + 1648 .LVL88: + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + 1649 .loc 1 371 5 is_stmt 1 view .LVU525 + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + 1650 .loc 1 371 19 is_stmt 0 view .LVU526 + 1651 02f8 2749 ldr r1, .L95+24 + 1652 02fa 1140 ands r1, r1, r2 + 1653 .LVL89: + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1654 .loc 1 377 5 is_stmt 1 view .LVU527 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1655 .loc 1 377 23 is_stmt 0 view .LVU528 + 1656 02fc A268 ldr r2, [r4, #8] + 1657 02fe 402A cmp r2, #64 + 1658 0300 2CD0 beq .L83 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1659 .loc 1 377 23 discriminator 1 view .LVU529 + 1660 0302 802A cmp r2, #128 + 1661 0304 27D0 beq .L92 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1662 .loc 1 377 23 view .LVU530 + 1663 0306 0022 movs r2, #0 + 1664 .L77: + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + 1665 .loc 1 378 23 view .LVU531 + 1666 0308 E068 ldr r0, [r4, #12] + 1667 .LVL90: + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1668 .loc 1 377 78 view .LVU532 + 1669 030a 42EAD002 orr r2, r2, r0, lsr #3 + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + 1670 .loc 1 379 23 view .LVU533 + 1671 030e 2069 ldr r0, [r4, #16] + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + ARM GAS /tmp/ccXv4DVv.s page 72 + + + 1672 .loc 1 378 78 view .LVU534 + 1673 0310 42EAD002 orr r2, r2, r0, lsr #3 + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + 1674 .loc 1 380 23 view .LVU535 + 1675 0314 6069 ldr r0, [r4, #20] + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + 1676 .loc 1 379 78 view .LVU536 + 1677 0316 42EAD002 orr r2, r2, r0, lsr #3 + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MODE(hdma->Init.Mode) | + 1678 .loc 1 381 23 view .LVU537 + 1679 031a A069 ldr r0, [r4, #24] + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + 1680 .loc 1 380 78 view .LVU538 + 1681 031c 42EAD002 orr r2, r2, r0, lsr #3 + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + 1682 .loc 1 382 23 view .LVU539 + 1683 0320 E069 ldr r0, [r4, #28] + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_MODE(hdma->Init.Mode) | + 1684 .loc 1 381 78 view .LVU540 + 1685 0322 42EAD002 orr r2, r2, r0, lsr #3 + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1686 .loc 1 383 23 view .LVU541 + 1687 0326 206A ldr r0, [r4, #32] + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + 1688 .loc 1 382 78 view .LVU542 + 1689 0328 42EA1012 orr r2, r2, r0, lsr #4 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1690 .loc 1 377 19 view .LVU543 + 1691 032c 0A43 orrs r2, r2, r1 + 1692 .LVL91: + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1693 .loc 1 386 5 is_stmt 1 view .LVU544 + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1694 .loc 1 386 51 is_stmt 0 view .LVU545 + 1695 032e 1A60 str r2, [r3] + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1696 .loc 1 389 5 is_stmt 1 view .LVU546 + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1697 .loc 1 389 53 is_stmt 0 view .LVU547 + 1698 0330 2268 ldr r2, [r4] + 1699 .LVL92: + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1700 .loc 1 389 65 view .LVU548 + 1701 0332 1A4B ldr r3, .L95+28 + 1702 .LVL93: + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1703 .loc 1 389 65 view .LVU549 + 1704 0334 1344 add r3, r3, r2 + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1705 .loc 1 389 92 view .LVU550 + 1706 0336 1A4A ldr r2, .L95+32 + 1707 0338 A2FB0323 umull r2, r3, r2, r3 + 1708 033c 1B09 lsrs r3, r3, #4 + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1709 .loc 1 389 147 view .LVU551 + 1710 033e 9B00 lsls r3, r3, #2 + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 73 + + + 1711 .loc 1 389 23 view .LVU552 + 1712 0340 E365 str r3, [r4, #92] + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1713 .loc 1 393 5 is_stmt 1 view .LVU553 + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1714 .loc 1 393 40 is_stmt 0 view .LVU554 + 1715 0342 2046 mov r0, r4 + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1716 .loc 1 393 40 view .LVU555 + 1717 0344 FFF7FEFF bl DMA_CalcBaseAndBitshift + 1718 .LVL94: + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1719 .loc 1 396 5 is_stmt 1 view .LVU556 + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1720 .loc 1 396 50 is_stmt 0 view .LVU557 + 1721 0348 E26D ldr r2, [r4, #92] + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1722 .loc 1 396 64 view .LVU558 + 1723 034a 02F01F01 and r1, r2, #31 + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1724 .loc 1 396 42 view .LVU559 + 1725 034e 0122 movs r2, #1 + 1726 0350 8A40 lsls r2, r2, r1 + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1727 .loc 1 396 21 view .LVU560 + 1728 0352 4260 str r2, [r0, #4] + 1729 0354 5AE7 b .L76 + 1730 .LVL95: + 1731 .L92: + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + 1732 .loc 1 377 23 view .LVU561 + 1733 0356 4FF48042 mov r2, #16384 + 1734 035a D5E7 b .L77 + 1735 .L83: + 1736 035c 1022 movs r2, #16 + 1737 035e D3E7 b .L77 + 1738 .LVL96: + 1739 .L90: + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1740 .loc 1 416 7 is_stmt 1 view .LVU562 + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1741 .loc 1 416 26 is_stmt 0 view .LVU563 + 1742 0360 0023 movs r3, #0 + 1743 0362 6360 str r3, [r4, #4] + 1744 0364 A2E7 b .L80 + 1745 .L91: + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1746 .loc 1 432 7 is_stmt 1 view .LVU564 + 1747 0366 2046 mov r0, r4 + 1748 0368 FFF7FEFF bl DMA_CalcDMAMUXRequestGenBaseAndMask + 1749 .LVL97: + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1750 .loc 1 435 7 view .LVU565 + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1751 .loc 1 435 11 is_stmt 0 view .LVU566 + 1752 036c E36E ldr r3, [r4, #108] + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 74 + + + 1753 .loc 1 435 36 view .LVU567 + 1754 036e 0022 movs r2, #0 + 1755 0370 1A60 str r2, [r3] + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1756 .loc 1 438 7 is_stmt 1 view .LVU568 + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1757 .loc 1 438 11 is_stmt 0 view .LVU569 + 1758 0372 236F ldr r3, [r4, #112] + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1759 .loc 1 438 49 view .LVU570 + 1760 0374 626F ldr r2, [r4, #116] + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1761 .loc 1 438 43 view .LVU571 + 1762 0376 5A60 str r2, [r3, #4] + 1763 0378 A6E7 b .L79 + 1764 .LVL98: + 1765 .L82: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1766 .loc 1 221 12 view .LVU572 + 1767 037a 0120 movs r0, #1 + 1768 .LVL99: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1769 .loc 1 221 12 view .LVU573 + 1770 037c EEE6 b .L63 + 1771 .L96: + 1772 037e 00BF .align 2 + 1773 .L95: + 1774 0380 3F8010FE .word -32473025 + 1775 0384 0010005C .word 1543507968 + 1776 0388 0000FFFF .word -65536 + 1777 038c 10000240 .word 1073872912 + 1778 0390 28000240 .word 1073872936 + 1779 0394 08540258 .word 1476547592 + 1780 0398 0F00FEFF .word -131057 + 1781 039c F8ABFDA7 .word -1476547592 + 1782 03a0 CDCCCCCC .word -858993459 + 1783 .cfi_endproc + 1784 .LFE141: + 1786 .section .text.HAL_DMA_DeInit,"ax",%progbits + 1787 .align 1 + 1788 .global HAL_DMA_DeInit + 1789 .syntax unified + 1790 .thumb + 1791 .thumb_func + 1792 .fpu fpv5-d16 + 1794 HAL_DMA_DeInit: + 1795 .LVL100: + 1796 .LFB142: + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 1797 .loc 1 464 1 is_stmt 1 view -0 + 1798 .cfi_startproc + 1799 @ args = 0, pretend = 0, frame = 0 + 1800 @ frame_needed = 0, uses_anonymous_args = 0 + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 1801 .loc 1 465 3 view .LVU575 + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1802 .loc 1 466 3 view .LVU576 + ARM GAS /tmp/ccXv4DVv.s page 75 + + + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1803 .loc 1 469 3 view .LVU577 + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1804 .loc 1 469 5 is_stmt 0 view .LVU578 + 1805 0000 0028 cmp r0, #0 + 1806 0002 00F0DB80 beq .L108 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** DMA_Base_Registers *regs_dma; + 1807 .loc 1 464 1 view .LVU579 + 1808 0006 10B5 push {r4, lr} + 1809 .LCFI9: + 1810 .cfi_def_cfa_offset 8 + 1811 .cfi_offset 4, -8 + 1812 .cfi_offset 14, -4 + 1813 0008 0446 mov r4, r0 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1814 .loc 1 475 3 is_stmt 1 view .LVU580 + 1815 000a 0368 ldr r3, [r0] + 1816 000c 6C49 ldr r1, .L116 + 1817 000e 6D4A ldr r2, .L116+4 + 1818 0010 9342 cmp r3, r2 + 1819 0012 18BF it ne + 1820 0014 8B42 cmpne r3, r1 + 1821 0016 2FD0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1822 .loc 1 475 3 is_stmt 0 discriminator 2 view .LVU581 + 1823 0018 1832 adds r2, r2, #24 + 1824 001a 9342 cmp r3, r2 + 1825 001c 2CD0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1826 .loc 1 475 3 discriminator 4 view .LVU582 + 1827 001e 1832 adds r2, r2, #24 + 1828 0020 9342 cmp r3, r2 + 1829 0022 29D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1830 .loc 1 475 3 discriminator 6 view .LVU583 + 1831 0024 1832 adds r2, r2, #24 + 1832 0026 9342 cmp r3, r2 + 1833 0028 26D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1834 .loc 1 475 3 discriminator 8 view .LVU584 + 1835 002a 1832 adds r2, r2, #24 + 1836 002c 9342 cmp r3, r2 + 1837 002e 23D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1838 .loc 1 475 3 discriminator 10 view .LVU585 + 1839 0030 1832 adds r2, r2, #24 + 1840 0032 9342 cmp r3, r2 + 1841 0034 20D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1842 .loc 1 475 3 discriminator 12 view .LVU586 + 1843 0036 1832 adds r2, r2, #24 + 1844 0038 9342 cmp r3, r2 + 1845 003a 1DD0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1846 .loc 1 475 3 discriminator 14 view .LVU587 + 1847 003c 02F55672 add r2, r2, #856 + 1848 0040 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 76 + + + 1849 0042 19D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1850 .loc 1 475 3 discriminator 16 view .LVU588 + 1851 0044 1832 adds r2, r2, #24 + 1852 0046 9342 cmp r3, r2 + 1853 0048 16D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1854 .loc 1 475 3 discriminator 18 view .LVU589 + 1855 004a 1832 adds r2, r2, #24 + 1856 004c 9342 cmp r3, r2 + 1857 004e 13D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1858 .loc 1 475 3 discriminator 20 view .LVU590 + 1859 0050 1832 adds r2, r2, #24 + 1860 0052 9342 cmp r3, r2 + 1861 0054 10D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1862 .loc 1 475 3 discriminator 22 view .LVU591 + 1863 0056 1832 adds r2, r2, #24 + 1864 0058 9342 cmp r3, r2 + 1865 005a 0DD0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1866 .loc 1 475 3 discriminator 24 view .LVU592 + 1867 005c 1832 adds r2, r2, #24 + 1868 005e 9342 cmp r3, r2 + 1869 0060 0AD0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1870 .loc 1 475 3 discriminator 26 view .LVU593 + 1871 0062 1832 adds r2, r2, #24 + 1872 0064 9342 cmp r3, r2 + 1873 0066 07D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1874 .loc 1 475 3 discriminator 28 view .LVU594 + 1875 0068 1832 adds r2, r2, #24 + 1876 006a 9342 cmp r3, r2 + 1877 006c 04D0 beq .L99 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1878 .loc 1 475 3 discriminator 30 view .LVU595 + 1879 006e 1A68 ldr r2, [r3] + 1880 0070 22F00102 bic r2, r2, #1 + 1881 0074 1A60 str r2, [r3] + 1882 0076 03E0 b .L101 + 1883 .L99: + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1884 .loc 1 475 3 discriminator 29 view .LVU596 + 1885 0078 1A68 ldr r2, [r3] + 1886 007a 22F00102 bic r2, r2, #1 + 1887 007e 1A60 str r2, [r3] + 1888 .L101: + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1889 .loc 1 477 3 is_stmt 1 view .LVU597 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1890 .loc 1 477 6 is_stmt 0 view .LVU598 + 1891 0080 2368 ldr r3, [r4] + 1892 0082 4F49 ldr r1, .L116 + 1893 0084 4F4A ldr r2, .L116+4 + 1894 0086 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 77 + + + 1895 0088 18BF it ne + 1896 008a 8B42 cmpne r3, r1 + 1897 008c 44D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1898 .loc 1 477 6 discriminator 2 view .LVU599 + 1899 008e 1832 adds r2, r2, #24 + 1900 0090 9342 cmp r3, r2 + 1901 0092 41D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1902 .loc 1 477 6 discriminator 4 view .LVU600 + 1903 0094 1832 adds r2, r2, #24 + 1904 0096 9342 cmp r3, r2 + 1905 0098 3ED0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1906 .loc 1 477 6 discriminator 6 view .LVU601 + 1907 009a 1832 adds r2, r2, #24 + 1908 009c 9342 cmp r3, r2 + 1909 009e 3BD0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1910 .loc 1 477 6 discriminator 8 view .LVU602 + 1911 00a0 1832 adds r2, r2, #24 + 1912 00a2 9342 cmp r3, r2 + 1913 00a4 38D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1914 .loc 1 477 6 discriminator 10 view .LVU603 + 1915 00a6 1832 adds r2, r2, #24 + 1916 00a8 9342 cmp r3, r2 + 1917 00aa 35D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1918 .loc 1 477 6 discriminator 12 view .LVU604 + 1919 00ac 1832 adds r2, r2, #24 + 1920 00ae 9342 cmp r3, r2 + 1921 00b0 32D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1922 .loc 1 477 6 discriminator 14 view .LVU605 + 1923 00b2 02F55672 add r2, r2, #856 + 1924 00b6 9342 cmp r3, r2 + 1925 00b8 2ED0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1926 .loc 1 477 6 discriminator 16 view .LVU606 + 1927 00ba 1832 adds r2, r2, #24 + 1928 00bc 9342 cmp r3, r2 + 1929 00be 2BD0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1930 .loc 1 477 6 discriminator 18 view .LVU607 + 1931 00c0 1832 adds r2, r2, #24 + 1932 00c2 9342 cmp r3, r2 + 1933 00c4 28D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1934 .loc 1 477 6 discriminator 20 view .LVU608 + 1935 00c6 1832 adds r2, r2, #24 + 1936 00c8 9342 cmp r3, r2 + 1937 00ca 25D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1938 .loc 1 477 6 discriminator 22 view .LVU609 + 1939 00cc 1832 adds r2, r2, #24 + 1940 00ce 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 78 + + + 1941 00d0 22D0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1942 .loc 1 477 6 discriminator 24 view .LVU610 + 1943 00d2 1832 adds r2, r2, #24 + 1944 00d4 9342 cmp r3, r2 + 1945 00d6 1FD0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1946 .loc 1 477 6 discriminator 26 view .LVU611 + 1947 00d8 1832 adds r2, r2, #24 + 1948 00da 9342 cmp r3, r2 + 1949 00dc 1CD0 beq .L102 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1950 .loc 1 477 6 discriminator 28 view .LVU612 + 1951 00de 1832 adds r2, r2, #24 + 1952 00e0 9342 cmp r3, r2 + 1953 00e2 19D0 beq .L102 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1954 .loc 1 503 8 is_stmt 1 view .LVU613 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1955 .loc 1 503 11 is_stmt 0 view .LVU614 + 1956 00e4 3849 ldr r1, .L116+8 + 1957 00e6 394A ldr r2, .L116+12 + 1958 00e8 9342 cmp r3, r2 + 1959 00ea 18BF it ne + 1960 00ec 8B42 cmpne r3, r1 + 1961 00ee 47D0 beq .L103 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1962 .loc 1 503 11 discriminator 2 view .LVU615 + 1963 00f0 374A ldr r2, .L116+16 + 1964 00f2 9342 cmp r3, r2 + 1965 00f4 44D0 beq .L103 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1966 .loc 1 503 11 discriminator 4 view .LVU616 + 1967 00f6 1432 adds r2, r2, #20 + 1968 00f8 9342 cmp r3, r2 + 1969 00fa 41D0 beq .L103 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1970 .loc 1 503 11 discriminator 6 view .LVU617 + 1971 00fc 1432 adds r2, r2, #20 + 1972 00fe 9342 cmp r3, r2 + 1973 0100 3ED0 beq .L103 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1974 .loc 1 503 11 discriminator 8 view .LVU618 + 1975 0102 1432 adds r2, r2, #20 + 1976 0104 9342 cmp r3, r2 + 1977 0106 3BD0 beq .L103 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1978 .loc 1 503 11 discriminator 10 view .LVU619 + 1979 0108 1432 adds r2, r2, #20 + 1980 010a 9342 cmp r3, r2 + 1981 010c 38D0 beq .L103 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 1982 .loc 1 503 11 discriminator 12 view .LVU620 + 1983 010e 1432 adds r2, r2, #20 + 1984 0110 9342 cmp r3, r2 + 1985 0112 35D0 beq .L103 + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 79 + + + 1986 .loc 1 529 12 view .LVU621 + 1987 0114 0120 movs r0, #1 + 1988 .LVL101: + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 1989 .loc 1 529 12 view .LVU622 + 1990 0116 32E0 b .L98 + 1991 .LVL102: + 1992 .L102: + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1993 .loc 1 480 5 is_stmt 1 view .LVU623 + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1994 .loc 1 480 52 is_stmt 0 view .LVU624 + 1995 0118 0022 movs r2, #0 + 1996 011a 1A60 str r2, [r3] + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1997 .loc 1 483 5 is_stmt 1 view .LVU625 + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 1998 .loc 1 483 34 is_stmt 0 view .LVU626 + 1999 011c 2368 ldr r3, [r4] + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2000 .loc 1 483 52 view .LVU627 + 2001 011e 5A60 str r2, [r3, #4] + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2002 .loc 1 486 5 is_stmt 1 view .LVU628 + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2003 .loc 1 486 34 is_stmt 0 view .LVU629 + 2004 0120 2368 ldr r3, [r4] + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2005 .loc 1 486 52 view .LVU630 + 2006 0122 9A60 str r2, [r3, #8] + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2007 .loc 1 489 5 is_stmt 1 view .LVU631 + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2008 .loc 1 489 34 is_stmt 0 view .LVU632 + 2009 0124 2368 ldr r3, [r4] + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2010 .loc 1 489 52 view .LVU633 + 2011 0126 DA60 str r2, [r3, #12] + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2012 .loc 1 492 5 is_stmt 1 view .LVU634 + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2013 .loc 1 492 34 is_stmt 0 view .LVU635 + 2014 0128 2368 ldr r3, [r4] + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2015 .loc 1 492 52 view .LVU636 + 2016 012a 1A61 str r2, [r3, #16] + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2017 .loc 1 495 5 is_stmt 1 view .LVU637 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2018 .loc 1 495 34 is_stmt 0 view .LVU638 + 2019 012c 2368 ldr r3, [r4] + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2020 .loc 1 495 52 view .LVU639 + 2021 012e 2122 movs r2, #33 + 2022 0130 5A61 str r2, [r3, #20] + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2023 .loc 1 498 5 is_stmt 1 view .LVU640 + ARM GAS /tmp/ccXv4DVv.s page 80 + + + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2024 .loc 1 498 38 is_stmt 0 view .LVU641 + 2025 0132 2046 mov r0, r4 + 2026 .LVL103: + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2027 .loc 1 498 38 view .LVU642 + 2028 0134 FFF7FEFF bl DMA_CalcBaseAndBitshift + 2029 .LVL104: + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2030 .loc 1 501 5 is_stmt 1 view .LVU643 + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2031 .loc 1 501 37 is_stmt 0 view .LVU644 + 2032 0138 E36D ldr r3, [r4, #92] + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2033 .loc 1 501 51 view .LVU645 + 2034 013a 03F01F02 and r2, r3, #31 + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2035 .loc 1 501 29 view .LVU646 + 2036 013e 3F23 movs r3, #63 + 2037 0140 9340 lsls r3, r3, r2 + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2038 .loc 1 501 20 view .LVU647 + 2039 0142 8360 str r3, [r0, #8] + 2040 .LVL105: + 2041 .L105: + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2042 .loc 1 538 5 is_stmt 1 view .LVU648 + 2043 0144 2046 mov r0, r4 + 2044 0146 FFF7FEFF bl DMA_CalcDMAMUXChannelBaseAndMask + 2045 .LVL106: + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2046 .loc 1 540 5 view .LVU649 + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2047 .loc 1 540 12 is_stmt 0 view .LVU650 + 2048 014a 236E ldr r3, [r4, #96] + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2049 .loc 1 540 7 view .LVU651 + 2050 014c 23B1 cbz r3, .L106 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2051 .loc 1 543 7 is_stmt 1 view .LVU652 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2052 .loc 1 543 32 is_stmt 0 view .LVU653 + 2053 014e 0022 movs r2, #0 + 2054 0150 1A60 str r2, [r3] + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2055 .loc 1 546 7 is_stmt 1 view .LVU654 + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2056 .loc 1 546 11 is_stmt 0 view .LVU655 + 2057 0152 636E ldr r3, [r4, #100] + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2058 .loc 1 546 44 view .LVU656 + 2059 0154 A26E ldr r2, [r4, #104] + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2060 .loc 1 546 38 view .LVU657 + 2061 0156 5A60 str r2, [r3, #4] + 2062 .L106: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 81 + + + 2063 .loc 1 549 5 is_stmt 1 view .LVU658 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2064 .loc 1 549 19 is_stmt 0 view .LVU659 + 2065 0158 6368 ldr r3, [r4, #4] + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2066 .loc 1 549 55 view .LVU660 + 2067 015a 013B subs r3, r3, #1 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2068 .loc 1 549 7 view .LVU661 + 2069 015c 072B cmp r3, #7 + 2070 015e 23D9 bls .L115 + 2071 .L107: + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 2072 .loc 1 562 5 is_stmt 1 view .LVU662 + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 2073 .loc 1 562 28 is_stmt 0 view .LVU663 + 2074 0160 0020 movs r0, #0 + 2075 0162 E066 str r0, [r4, #108] + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 2076 .loc 1 563 5 is_stmt 1 view .LVU664 + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 2077 .loc 1 563 34 is_stmt 0 view .LVU665 + 2078 0164 2067 str r0, [r4, #112] + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2079 .loc 1 564 5 is_stmt 1 view .LVU666 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2080 .loc 1 564 38 is_stmt 0 view .LVU667 + 2081 0166 6067 str r0, [r4, #116] + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 2082 .loc 1 569 3 is_stmt 1 view .LVU668 + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 2083 .loc 1 569 32 is_stmt 0 view .LVU669 + 2084 0168 E063 str r0, [r4, #60] + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 2085 .loc 1 570 3 is_stmt 1 view .LVU670 + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 2086 .loc 1 570 32 is_stmt 0 view .LVU671 + 2087 016a 2064 str r0, [r4, #64] + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 2088 .loc 1 571 3 is_stmt 1 view .LVU672 + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 2089 .loc 1 571 32 is_stmt 0 view .LVU673 + 2090 016c 6064 str r0, [r4, #68] + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 2091 .loc 1 572 3 is_stmt 1 view .LVU674 + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 2092 .loc 1 572 32 is_stmt 0 view .LVU675 + 2093 016e A064 str r0, [r4, #72] + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 2094 .loc 1 573 3 is_stmt 1 view .LVU676 + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 2095 .loc 1 573 32 is_stmt 0 view .LVU677 + 2096 0170 E064 str r0, [r4, #76] + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2097 .loc 1 574 3 is_stmt 1 view .LVU678 + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2098 .loc 1 574 32 is_stmt 0 view .LVU679 + ARM GAS /tmp/ccXv4DVv.s page 82 + + + 2099 0172 2065 str r0, [r4, #80] + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2100 .loc 1 577 3 is_stmt 1 view .LVU680 + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2101 .loc 1 577 19 is_stmt 0 view .LVU681 + 2102 0174 6065 str r0, [r4, #84] + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2103 .loc 1 580 3 is_stmt 1 view .LVU682 + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2104 .loc 1 580 15 is_stmt 0 view .LVU683 + 2105 0176 84F83500 strb r0, [r4, #53] + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2106 .loc 1 583 3 is_stmt 1 view .LVU684 + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2107 .loc 1 583 3 view .LVU685 + 2108 017a 84F83400 strb r0, [r4, #52] + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2109 .loc 1 583 3 view .LVU686 + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2110 .loc 1 585 3 view .LVU687 + 2111 .L98: + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2112 .loc 1 586 1 is_stmt 0 view .LVU688 + 2113 017e 10BD pop {r4, pc} + 2114 .LVL107: + 2115 .L103: + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2116 .loc 1 506 5 is_stmt 1 view .LVU689 + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2117 .loc 1 506 52 is_stmt 0 view .LVU690 + 2118 0180 0022 movs r2, #0 + 2119 0182 1A60 str r2, [r3] + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2120 .loc 1 509 5 is_stmt 1 view .LVU691 + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2121 .loc 1 509 34 is_stmt 0 view .LVU692 + 2122 0184 2368 ldr r3, [r4] + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2123 .loc 1 509 53 view .LVU693 + 2124 0186 5A60 str r2, [r3, #4] + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2125 .loc 1 512 5 is_stmt 1 view .LVU694 + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2126 .loc 1 512 34 is_stmt 0 view .LVU695 + 2127 0188 2368 ldr r3, [r4] + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2128 .loc 1 512 53 view .LVU696 + 2129 018a 9A60 str r2, [r3, #8] + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2130 .loc 1 515 5 is_stmt 1 view .LVU697 + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2131 .loc 1 515 34 is_stmt 0 view .LVU698 + 2132 018c 2368 ldr r3, [r4] + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2133 .loc 1 515 53 view .LVU699 + 2134 018e DA60 str r2, [r3, #12] + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 83 + + + 2135 .loc 1 518 5 is_stmt 1 view .LVU700 + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2136 .loc 1 518 34 is_stmt 0 view .LVU701 + 2137 0190 2368 ldr r3, [r4] + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2138 .loc 1 518 53 view .LVU702 + 2139 0192 1A61 str r2, [r3, #16] + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2140 .loc 1 521 5 is_stmt 1 view .LVU703 + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2141 .loc 1 521 40 is_stmt 0 view .LVU704 + 2142 0194 2046 mov r0, r4 + 2143 .LVL108: + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2144 .loc 1 521 40 view .LVU705 + 2145 0196 FFF7FEFF bl DMA_CalcBaseAndBitshift + 2146 .LVL109: + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2147 .loc 1 524 5 is_stmt 1 view .LVU706 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2148 .loc 1 524 50 is_stmt 0 view .LVU707 + 2149 019a E36D ldr r3, [r4, #92] + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2150 .loc 1 524 64 view .LVU708 + 2151 019c 03F01F02 and r2, r3, #31 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2152 .loc 1 524 42 view .LVU709 + 2153 01a0 0123 movs r3, #1 + 2154 01a2 9340 lsls r3, r3, r2 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2155 .loc 1 524 21 view .LVU710 + 2156 01a4 4360 str r3, [r0, #4] + 2157 01a6 CDE7 b .L105 + 2158 .LVL110: + 2159 .L115: + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2160 .loc 1 553 7 is_stmt 1 view .LVU711 + 2161 01a8 2046 mov r0, r4 + 2162 01aa FFF7FEFF bl DMA_CalcDMAMUXRequestGenBaseAndMask + 2163 .LVL111: + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2164 .loc 1 556 7 view .LVU712 + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2165 .loc 1 556 11 is_stmt 0 view .LVU713 + 2166 01ae E36E ldr r3, [r4, #108] + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2167 .loc 1 556 36 view .LVU714 + 2168 01b0 0022 movs r2, #0 + 2169 01b2 1A60 str r2, [r3] + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2170 .loc 1 559 7 is_stmt 1 view .LVU715 + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2171 .loc 1 559 11 is_stmt 0 view .LVU716 + 2172 01b4 236F ldr r3, [r4, #112] + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2173 .loc 1 559 49 view .LVU717 + 2174 01b6 626F ldr r2, [r4, #116] + ARM GAS /tmp/ccXv4DVv.s page 84 + + + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2175 .loc 1 559 43 view .LVU718 + 2176 01b8 5A60 str r2, [r3, #4] + 2177 01ba D1E7 b .L107 + 2178 .LVL112: + 2179 .L108: + 2180 .LCFI10: + 2181 .cfi_def_cfa_offset 0 + 2182 .cfi_restore 4 + 2183 .cfi_restore 14 + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2184 .loc 1 471 12 view .LVU719 + 2185 01bc 0120 movs r0, #1 + 2186 .LVL113: + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2187 .loc 1 586 1 view .LVU720 + 2188 01be 7047 bx lr + 2189 .L117: + 2190 .align 2 + 2191 .L116: + 2192 01c0 10000240 .word 1073872912 + 2193 01c4 28000240 .word 1073872936 + 2194 01c8 08540258 .word 1476547592 + 2195 01cc 1C540258 .word 1476547612 + 2196 01d0 30540258 .word 1476547632 + 2197 .cfi_endproc + 2198 .LFE142: + 2200 .section .text.HAL_DMA_Start,"ax",%progbits + 2201 .align 1 + 2202 .global HAL_DMA_Start + 2203 .syntax unified + 2204 .thumb + 2205 .thumb_func + 2206 .fpu fpv5-d16 + 2208 HAL_DMA_Start: + 2209 .LVL114: + 2210 .LFB143: + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 2211 .loc 1 621 1 is_stmt 1 view -0 + 2212 .cfi_startproc + 2213 @ args = 0, pretend = 0, frame = 0 + 2214 @ frame_needed = 0, uses_anonymous_args = 0 + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2215 .loc 1 622 3 view .LVU722 + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2216 .loc 1 625 3 view .LVU723 + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2217 .loc 1 628 3 view .LVU724 + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2218 .loc 1 628 5 is_stmt 0 view .LVU725 + 2219 0000 0028 cmp r0, #0 + 2220 0002 00F09880 beq .L126 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 2221 .loc 1 621 1 view .LVU726 + 2222 0006 70B5 push {r4, r5, r6, lr} + 2223 .LCFI11: + 2224 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccXv4DVv.s page 85 + + + 2225 .cfi_offset 4, -16 + 2226 .cfi_offset 5, -12 + 2227 .cfi_offset 6, -8 + 2228 .cfi_offset 14, -4 + 2229 0008 0446 mov r4, r0 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2230 .loc 1 634 3 is_stmt 1 view .LVU727 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2231 .loc 1 634 3 view .LVU728 + 2232 000a 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 2233 .LVL115: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2234 .loc 1 634 3 is_stmt 0 view .LVU729 + 2235 000e 0128 cmp r0, #1 + 2236 0010 00F09380 beq .L127 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2237 .loc 1 634 3 is_stmt 1 discriminator 2 view .LVU730 + 2238 0014 0120 movs r0, #1 + 2239 0016 84F83400 strb r0, [r4, #52] + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2240 .loc 1 634 3 discriminator 2 view .LVU731 + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2241 .loc 1 636 3 discriminator 2 view .LVU732 + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2242 .loc 1 636 33 is_stmt 0 discriminator 2 view .LVU733 + 2243 001a 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 2244 001e C0B2 uxtb r0, r0 + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2245 .loc 1 636 5 discriminator 2 view .LVU734 + 2246 0020 0128 cmp r0, #1 + 2247 0022 07D0 beq .L132 + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2248 .loc 1 656 5 is_stmt 1 view .LVU735 + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2249 .loc 1 656 5 view .LVU736 + 2250 0024 0023 movs r3, #0 + 2251 .LVL116: + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2252 .loc 1 656 5 is_stmt 0 view .LVU737 + 2253 0026 84F83430 strb r3, [r4, #52] + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2254 .loc 1 656 5 is_stmt 1 view .LVU738 + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2255 .loc 1 659 5 view .LVU739 + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2256 .loc 1 659 21 is_stmt 0 view .LVU740 + 2257 002a 4FF40063 mov r3, #2048 + 2258 002e 6365 str r3, [r4, #84] + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2259 .loc 1 662 5 is_stmt 1 view .LVU741 + 2260 .LVL117: + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2261 .loc 1 662 12 is_stmt 0 view .LVU742 + 2262 0030 0120 movs r0, #1 + 2263 .LVL118: + 2264 .L119: + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 86 + + + 2265 .loc 1 665 1 view .LVU743 + 2266 0032 70BD pop {r4, r5, r6, pc} + 2267 .LVL119: + 2268 .L132: + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2269 .loc 1 639 5 is_stmt 1 view .LVU744 + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2270 .loc 1 639 17 is_stmt 0 view .LVU745 + 2271 0034 0220 movs r0, #2 + 2272 0036 84F83500 strb r0, [r4, #53] + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2273 .loc 1 642 5 is_stmt 1 view .LVU746 + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2274 .loc 1 642 21 is_stmt 0 view .LVU747 + 2275 003a 0020 movs r0, #0 + 2276 003c 6065 str r0, [r4, #84] + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2277 .loc 1 645 5 is_stmt 1 view .LVU748 + 2278 003e 2068 ldr r0, [r4] + 2279 0040 3F4E ldr r6, .L133 + 2280 0042 404D ldr r5, .L133+4 + 2281 0044 A842 cmp r0, r5 + 2282 0046 18BF it ne + 2283 0048 B042 cmpne r0, r6 + 2284 004a 2FD0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2285 .loc 1 645 5 is_stmt 0 discriminator 2 view .LVU749 + 2286 004c 1835 adds r5, r5, #24 + 2287 004e A842 cmp r0, r5 + 2288 0050 2CD0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2289 .loc 1 645 5 discriminator 4 view .LVU750 + 2290 0052 1835 adds r5, r5, #24 + 2291 0054 A842 cmp r0, r5 + 2292 0056 29D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2293 .loc 1 645 5 discriminator 6 view .LVU751 + 2294 0058 1835 adds r5, r5, #24 + 2295 005a A842 cmp r0, r5 + 2296 005c 26D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2297 .loc 1 645 5 discriminator 8 view .LVU752 + 2298 005e 1835 adds r5, r5, #24 + 2299 0060 A842 cmp r0, r5 + 2300 0062 23D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2301 .loc 1 645 5 discriminator 10 view .LVU753 + 2302 0064 1835 adds r5, r5, #24 + 2303 0066 A842 cmp r0, r5 + 2304 0068 20D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2305 .loc 1 645 5 discriminator 12 view .LVU754 + 2306 006a 1835 adds r5, r5, #24 + 2307 006c A842 cmp r0, r5 + 2308 006e 1DD0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2309 .loc 1 645 5 discriminator 14 view .LVU755 + ARM GAS /tmp/ccXv4DVv.s page 87 + + + 2310 0070 05F55675 add r5, r5, #856 + 2311 0074 A842 cmp r0, r5 + 2312 0076 19D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2313 .loc 1 645 5 discriminator 16 view .LVU756 + 2314 0078 1835 adds r5, r5, #24 + 2315 007a A842 cmp r0, r5 + 2316 007c 16D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2317 .loc 1 645 5 discriminator 18 view .LVU757 + 2318 007e 1835 adds r5, r5, #24 + 2319 0080 A842 cmp r0, r5 + 2320 0082 13D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2321 .loc 1 645 5 discriminator 20 view .LVU758 + 2322 0084 1835 adds r5, r5, #24 + 2323 0086 A842 cmp r0, r5 + 2324 0088 10D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2325 .loc 1 645 5 discriminator 22 view .LVU759 + 2326 008a 1835 adds r5, r5, #24 + 2327 008c A842 cmp r0, r5 + 2328 008e 0DD0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2329 .loc 1 645 5 discriminator 24 view .LVU760 + 2330 0090 1835 adds r5, r5, #24 + 2331 0092 A842 cmp r0, r5 + 2332 0094 0AD0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2333 .loc 1 645 5 discriminator 26 view .LVU761 + 2334 0096 1835 adds r5, r5, #24 + 2335 0098 A842 cmp r0, r5 + 2336 009a 07D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2337 .loc 1 645 5 discriminator 28 view .LVU762 + 2338 009c 1835 adds r5, r5, #24 + 2339 009e A842 cmp r0, r5 + 2340 00a0 04D0 beq .L121 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2341 .loc 1 645 5 discriminator 30 view .LVU763 + 2342 00a2 0568 ldr r5, [r0] + 2343 00a4 25F00105 bic r5, r5, #1 + 2344 00a8 0560 str r5, [r0] + 2345 00aa 03E0 b .L123 + 2346 .L121: + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2347 .loc 1 645 5 discriminator 29 view .LVU764 + 2348 00ac 0568 ldr r5, [r0] + 2349 00ae 25F00105 bic r5, r5, #1 + 2350 00b2 0560 str r5, [r0] + 2351 .L123: + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2352 .loc 1 648 5 is_stmt 1 view .LVU765 + 2353 00b4 2046 mov r0, r4 + 2354 00b6 FFF7FEFF bl DMA_SetConfig + 2355 .LVL120: + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 88 + + + 2356 .loc 1 651 5 view .LVU766 + 2357 00ba 2368 ldr r3, [r4] + 2358 00bc 2049 ldr r1, .L133 + 2359 00be 214A ldr r2, .L133+4 + 2360 00c0 9342 cmp r3, r2 + 2361 00c2 18BF it ne + 2362 00c4 8B42 cmpne r3, r1 + 2363 00c6 30D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2364 .loc 1 651 5 is_stmt 0 discriminator 2 view .LVU767 + 2365 00c8 1832 adds r2, r2, #24 + 2366 00ca 9342 cmp r3, r2 + 2367 00cc 2DD0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2368 .loc 1 651 5 discriminator 4 view .LVU768 + 2369 00ce 1832 adds r2, r2, #24 + 2370 00d0 9342 cmp r3, r2 + 2371 00d2 2AD0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2372 .loc 1 651 5 discriminator 6 view .LVU769 + 2373 00d4 1832 adds r2, r2, #24 + 2374 00d6 9342 cmp r3, r2 + 2375 00d8 27D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2376 .loc 1 651 5 discriminator 8 view .LVU770 + 2377 00da 1832 adds r2, r2, #24 + 2378 00dc 9342 cmp r3, r2 + 2379 00de 24D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2380 .loc 1 651 5 discriminator 10 view .LVU771 + 2381 00e0 1832 adds r2, r2, #24 + 2382 00e2 9342 cmp r3, r2 + 2383 00e4 21D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2384 .loc 1 651 5 discriminator 12 view .LVU772 + 2385 00e6 1832 adds r2, r2, #24 + 2386 00e8 9342 cmp r3, r2 + 2387 00ea 1ED0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2388 .loc 1 651 5 discriminator 14 view .LVU773 + 2389 00ec 02F55672 add r2, r2, #856 + 2390 00f0 9342 cmp r3, r2 + 2391 00f2 1AD0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2392 .loc 1 651 5 discriminator 16 view .LVU774 + 2393 00f4 1832 adds r2, r2, #24 + 2394 00f6 9342 cmp r3, r2 + 2395 00f8 17D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2396 .loc 1 651 5 discriminator 18 view .LVU775 + 2397 00fa 1832 adds r2, r2, #24 + 2398 00fc 9342 cmp r3, r2 + 2399 00fe 14D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2400 .loc 1 651 5 discriminator 20 view .LVU776 + 2401 0100 1832 adds r2, r2, #24 + 2402 0102 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 89 + + + 2403 0104 11D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2404 .loc 1 651 5 discriminator 22 view .LVU777 + 2405 0106 1832 adds r2, r2, #24 + 2406 0108 9342 cmp r3, r2 + 2407 010a 0ED0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2408 .loc 1 651 5 discriminator 24 view .LVU778 + 2409 010c 1832 adds r2, r2, #24 + 2410 010e 9342 cmp r3, r2 + 2411 0110 0BD0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2412 .loc 1 651 5 discriminator 26 view .LVU779 + 2413 0112 1832 adds r2, r2, #24 + 2414 0114 9342 cmp r3, r2 + 2415 0116 08D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2416 .loc 1 651 5 discriminator 28 view .LVU780 + 2417 0118 1832 adds r2, r2, #24 + 2418 011a 9342 cmp r3, r2 + 2419 011c 05D0 beq .L124 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2420 .loc 1 651 5 discriminator 30 view .LVU781 + 2421 011e 1A68 ldr r2, [r3] + 2422 0120 42F00102 orr r2, r2, #1 + 2423 0124 1A60 str r2, [r3] + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2424 .loc 1 622 21 discriminator 30 view .LVU782 + 2425 0126 0020 movs r0, #0 + 2426 0128 83E7 b .L119 + 2427 .L124: + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2428 .loc 1 651 5 discriminator 29 view .LVU783 + 2429 012a 1A68 ldr r2, [r3] + 2430 012c 42F00102 orr r2, r2, #1 + 2431 0130 1A60 str r2, [r3] + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2432 .loc 1 622 21 discriminator 29 view .LVU784 + 2433 0132 0020 movs r0, #0 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2434 .loc 1 651 5 discriminator 29 view .LVU785 + 2435 0134 7DE7 b .L119 + 2436 .LVL121: + 2437 .L126: + 2438 .LCFI12: + 2439 .cfi_def_cfa_offset 0 + 2440 .cfi_restore 4 + 2441 .cfi_restore 5 + 2442 .cfi_restore 6 + 2443 .cfi_restore 14 + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2444 .loc 1 630 12 view .LVU786 + 2445 0136 0120 movs r0, #1 + 2446 .LVL122: + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2447 .loc 1 665 1 view .LVU787 + 2448 0138 7047 bx lr + ARM GAS /tmp/ccXv4DVv.s page 90 + + + 2449 .LVL123: + 2450 .L127: + 2451 .LCFI13: + 2452 .cfi_def_cfa_offset 16 + 2453 .cfi_offset 4, -16 + 2454 .cfi_offset 5, -12 + 2455 .cfi_offset 6, -8 + 2456 .cfi_offset 14, -4 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2457 .loc 1 634 3 view .LVU788 + 2458 013a 0220 movs r0, #2 + 2459 013c 79E7 b .L119 + 2460 .L134: + 2461 013e 00BF .align 2 + 2462 .L133: + 2463 0140 10000240 .word 1073872912 + 2464 0144 28000240 .word 1073872936 + 2465 .cfi_endproc + 2466 .LFE143: + 2468 .section .text.HAL_DMA_Start_IT,"ax",%progbits + 2469 .align 1 + 2470 .global HAL_DMA_Start_IT + 2471 .syntax unified + 2472 .thumb + 2473 .thumb_func + 2474 .fpu fpv5-d16 + 2476 HAL_DMA_Start_IT: + 2477 .LVL124: + 2478 .LFB144: + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 2479 .loc 1 677 1 is_stmt 1 view -0 + 2480 .cfi_startproc + 2481 @ args = 0, pretend = 0, frame = 0 + 2482 @ frame_needed = 0, uses_anonymous_args = 0 + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2483 .loc 1 678 3 view .LVU790 + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2484 .loc 1 681 3 view .LVU791 + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2485 .loc 1 684 3 view .LVU792 + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2486 .loc 1 684 5 is_stmt 0 view .LVU793 + 2487 0000 0028 cmp r0, #0 + 2488 0002 00F03E81 beq .L149 + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 2489 .loc 1 677 1 view .LVU794 + 2490 0006 70B5 push {r4, r5, r6, lr} + 2491 .LCFI14: + 2492 .cfi_def_cfa_offset 16 + 2493 .cfi_offset 4, -16 + 2494 .cfi_offset 5, -12 + 2495 .cfi_offset 6, -8 + 2496 .cfi_offset 14, -4 + 2497 0008 0446 mov r4, r0 + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2498 .loc 1 690 3 is_stmt 1 view .LVU795 + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 91 + + + 2499 .loc 1 690 3 view .LVU796 + 2500 000a 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 2501 .LVL125: + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2502 .loc 1 690 3 is_stmt 0 view .LVU797 + 2503 000e 0128 cmp r0, #1 + 2504 0010 00F03981 beq .L150 + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2505 .loc 1 690 3 is_stmt 1 discriminator 2 view .LVU798 + 2506 0014 0120 movs r0, #1 + 2507 0016 84F83400 strb r0, [r4, #52] + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2508 .loc 1 690 3 discriminator 2 view .LVU799 + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2509 .loc 1 692 3 discriminator 2 view .LVU800 + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2510 .loc 1 692 33 is_stmt 0 discriminator 2 view .LVU801 + 2511 001a 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 2512 001e C0B2 uxtb r0, r0 + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2513 .loc 1 692 5 discriminator 2 view .LVU802 + 2514 0020 0128 cmp r0, #1 + 2515 0022 07D0 beq .L155 + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2516 .loc 1 752 5 is_stmt 1 view .LVU803 + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2517 .loc 1 752 5 view .LVU804 + 2518 0024 0023 movs r3, #0 + 2519 .LVL126: + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2520 .loc 1 752 5 is_stmt 0 view .LVU805 + 2521 0026 84F83430 strb r3, [r4, #52] + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2522 .loc 1 752 5 is_stmt 1 view .LVU806 + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2523 .loc 1 755 5 view .LVU807 + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2524 .loc 1 755 21 is_stmt 0 view .LVU808 + 2525 002a 4FF40063 mov r3, #2048 + 2526 002e 6365 str r3, [r4, #84] + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2527 .loc 1 758 5 is_stmt 1 view .LVU809 + 2528 .LVL127: + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2529 .loc 1 758 12 is_stmt 0 view .LVU810 + 2530 0030 0120 movs r0, #1 + 2531 .LVL128: + 2532 .L136: + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2533 .loc 1 762 1 view .LVU811 + 2534 0032 70BD pop {r4, r5, r6, pc} + 2535 .LVL129: + 2536 .L155: + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2537 .loc 1 695 5 is_stmt 1 view .LVU812 + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2538 .loc 1 695 17 is_stmt 0 view .LVU813 + ARM GAS /tmp/ccXv4DVv.s page 92 + + + 2539 0034 0220 movs r0, #2 + 2540 0036 84F83500 strb r0, [r4, #53] + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2541 .loc 1 698 5 is_stmt 1 view .LVU814 + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2542 .loc 1 698 21 is_stmt 0 view .LVU815 + 2543 003a 0020 movs r0, #0 + 2544 003c 6065 str r0, [r4, #84] + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2545 .loc 1 701 5 is_stmt 1 view .LVU816 + 2546 003e 2068 ldr r0, [r4] + 2547 0040 924E ldr r6, .L156 + 2548 0042 934D ldr r5, .L156+4 + 2549 0044 A842 cmp r0, r5 + 2550 0046 18BF it ne + 2551 0048 B042 cmpne r0, r6 + 2552 004a 2FD0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2553 .loc 1 701 5 is_stmt 0 discriminator 2 view .LVU817 + 2554 004c 1835 adds r5, r5, #24 + 2555 004e A842 cmp r0, r5 + 2556 0050 2CD0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2557 .loc 1 701 5 discriminator 4 view .LVU818 + 2558 0052 1835 adds r5, r5, #24 + 2559 0054 A842 cmp r0, r5 + 2560 0056 29D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2561 .loc 1 701 5 discriminator 6 view .LVU819 + 2562 0058 1835 adds r5, r5, #24 + 2563 005a A842 cmp r0, r5 + 2564 005c 26D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2565 .loc 1 701 5 discriminator 8 view .LVU820 + 2566 005e 1835 adds r5, r5, #24 + 2567 0060 A842 cmp r0, r5 + 2568 0062 23D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2569 .loc 1 701 5 discriminator 10 view .LVU821 + 2570 0064 1835 adds r5, r5, #24 + 2571 0066 A842 cmp r0, r5 + 2572 0068 20D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2573 .loc 1 701 5 discriminator 12 view .LVU822 + 2574 006a 1835 adds r5, r5, #24 + 2575 006c A842 cmp r0, r5 + 2576 006e 1DD0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2577 .loc 1 701 5 discriminator 14 view .LVU823 + 2578 0070 05F55675 add r5, r5, #856 + 2579 0074 A842 cmp r0, r5 + 2580 0076 19D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2581 .loc 1 701 5 discriminator 16 view .LVU824 + 2582 0078 1835 adds r5, r5, #24 + 2583 007a A842 cmp r0, r5 + 2584 007c 16D0 beq .L138 + ARM GAS /tmp/ccXv4DVv.s page 93 + + + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2585 .loc 1 701 5 discriminator 18 view .LVU825 + 2586 007e 1835 adds r5, r5, #24 + 2587 0080 A842 cmp r0, r5 + 2588 0082 13D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2589 .loc 1 701 5 discriminator 20 view .LVU826 + 2590 0084 1835 adds r5, r5, #24 + 2591 0086 A842 cmp r0, r5 + 2592 0088 10D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2593 .loc 1 701 5 discriminator 22 view .LVU827 + 2594 008a 1835 adds r5, r5, #24 + 2595 008c A842 cmp r0, r5 + 2596 008e 0DD0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2597 .loc 1 701 5 discriminator 24 view .LVU828 + 2598 0090 1835 adds r5, r5, #24 + 2599 0092 A842 cmp r0, r5 + 2600 0094 0AD0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2601 .loc 1 701 5 discriminator 26 view .LVU829 + 2602 0096 1835 adds r5, r5, #24 + 2603 0098 A842 cmp r0, r5 + 2604 009a 07D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2605 .loc 1 701 5 discriminator 28 view .LVU830 + 2606 009c 1835 adds r5, r5, #24 + 2607 009e A842 cmp r0, r5 + 2608 00a0 04D0 beq .L138 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2609 .loc 1 701 5 discriminator 30 view .LVU831 + 2610 00a2 0568 ldr r5, [r0] + 2611 00a4 25F00105 bic r5, r5, #1 + 2612 00a8 0560 str r5, [r0] + 2613 00aa 03E0 b .L140 + 2614 .L138: + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2615 .loc 1 701 5 discriminator 29 view .LVU832 + 2616 00ac 0568 ldr r5, [r0] + 2617 00ae 25F00105 bic r5, r5, #1 + 2618 00b2 0560 str r5, [r0] + 2619 .L140: + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2620 .loc 1 704 5 is_stmt 1 view .LVU833 + 2621 00b4 2046 mov r0, r4 + 2622 00b6 FFF7FEFF bl DMA_SetConfig + 2623 .LVL130: + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2624 .loc 1 706 5 view .LVU834 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2625 .loc 1 706 8 is_stmt 0 view .LVU835 + 2626 00ba 2368 ldr r3, [r4] + 2627 00bc 7349 ldr r1, .L156 + 2628 00be 744A ldr r2, .L156+4 + 2629 00c0 9342 cmp r3, r2 + 2630 00c2 18BF it ne + ARM GAS /tmp/ccXv4DVv.s page 94 + + + 2631 00c4 8B42 cmpne r3, r1 + 2632 00c6 38D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2633 .loc 1 706 8 discriminator 2 view .LVU836 + 2634 00c8 1832 adds r2, r2, #24 + 2635 00ca 9342 cmp r3, r2 + 2636 00cc 35D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2637 .loc 1 706 8 discriminator 4 view .LVU837 + 2638 00ce 1832 adds r2, r2, #24 + 2639 00d0 9342 cmp r3, r2 + 2640 00d2 32D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2641 .loc 1 706 8 discriminator 6 view .LVU838 + 2642 00d4 1832 adds r2, r2, #24 + 2643 00d6 9342 cmp r3, r2 + 2644 00d8 2FD0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2645 .loc 1 706 8 discriminator 8 view .LVU839 + 2646 00da 1832 adds r2, r2, #24 + 2647 00dc 9342 cmp r3, r2 + 2648 00de 2CD0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2649 .loc 1 706 8 discriminator 10 view .LVU840 + 2650 00e0 1832 adds r2, r2, #24 + 2651 00e2 9342 cmp r3, r2 + 2652 00e4 29D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2653 .loc 1 706 8 discriminator 12 view .LVU841 + 2654 00e6 1832 adds r2, r2, #24 + 2655 00e8 9342 cmp r3, r2 + 2656 00ea 26D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2657 .loc 1 706 8 discriminator 14 view .LVU842 + 2658 00ec 02F55672 add r2, r2, #856 + 2659 00f0 9342 cmp r3, r2 + 2660 00f2 22D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2661 .loc 1 706 8 discriminator 16 view .LVU843 + 2662 00f4 1832 adds r2, r2, #24 + 2663 00f6 9342 cmp r3, r2 + 2664 00f8 1FD0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2665 .loc 1 706 8 discriminator 18 view .LVU844 + 2666 00fa 1832 adds r2, r2, #24 + 2667 00fc 9342 cmp r3, r2 + 2668 00fe 1CD0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2669 .loc 1 706 8 discriminator 20 view .LVU845 + 2670 0100 1832 adds r2, r2, #24 + 2671 0102 9342 cmp r3, r2 + 2672 0104 19D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2673 .loc 1 706 8 discriminator 22 view .LVU846 + 2674 0106 1832 adds r2, r2, #24 + 2675 0108 9342 cmp r3, r2 + 2676 010a 16D0 beq .L141 + ARM GAS /tmp/ccXv4DVv.s page 95 + + + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2677 .loc 1 706 8 discriminator 24 view .LVU847 + 2678 010c 1832 adds r2, r2, #24 + 2679 010e 9342 cmp r3, r2 + 2680 0110 13D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2681 .loc 1 706 8 discriminator 26 view .LVU848 + 2682 0112 1832 adds r2, r2, #24 + 2683 0114 9342 cmp r3, r2 + 2684 0116 10D0 beq .L141 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2685 .loc 1 706 8 discriminator 28 view .LVU849 + 2686 0118 1832 adds r2, r2, #24 + 2687 011a 9342 cmp r3, r2 + 2688 011c 0DD0 beq .L141 + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2689 .loc 1 720 7 is_stmt 1 view .LVU850 + 2690 011e 1A68 ldr r2, [r3] + 2691 0120 22F00E02 bic r2, r2, #14 + 2692 0124 42F00A02 orr r2, r2, #10 + 2693 0128 1A60 str r2, [r3] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2694 .loc 1 722 7 view .LVU851 + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2695 .loc 1 722 14 is_stmt 0 view .LVU852 + 2696 012a 236C ldr r3, [r4, #64] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2697 .loc 1 722 9 view .LVU853 + 2698 012c 93B1 cbz r3, .L143 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2699 .loc 1 725 9 is_stmt 1 view .LVU854 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2700 .loc 1 725 40 is_stmt 0 view .LVU855 + 2701 012e 2268 ldr r2, [r4] + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2702 .loc 1 725 58 view .LVU856 + 2703 0130 1368 ldr r3, [r2] + 2704 0132 43F00403 orr r3, r3, #4 + 2705 0136 1360 str r3, [r2] + 2706 0138 0CE0 b .L143 + 2707 .L141: + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2708 .loc 1 709 7 is_stmt 1 view .LVU857 + 2709 013a 1A68 ldr r2, [r3] + 2710 013c 22F01E02 bic r2, r2, #30 + 2711 0140 42F01602 orr r2, r2, #22 + 2712 0144 1A60 str r2, [r3] + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2713 .loc 1 711 7 view .LVU858 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2714 .loc 1 711 14 is_stmt 0 view .LVU859 + 2715 0146 236C ldr r3, [r4, #64] + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2716 .loc 1 711 9 view .LVU860 + 2717 0148 23B1 cbz r3, .L143 + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2718 .loc 1 714 9 is_stmt 1 view .LVU861 + ARM GAS /tmp/ccXv4DVv.s page 96 + + + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2719 .loc 1 714 38 is_stmt 0 view .LVU862 + 2720 014a 2268 ldr r2, [r4] + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2721 .loc 1 714 55 view .LVU863 + 2722 014c 1368 ldr r3, [r2] + 2723 014e 43F00803 orr r3, r3, #8 + 2724 0152 1360 str r3, [r2] + 2725 .L143: + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2726 .loc 1 729 5 is_stmt 1 view .LVU864 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2727 .loc 1 729 8 is_stmt 0 view .LVU865 + 2728 0154 2368 ldr r3, [r4] + 2729 0156 4D49 ldr r1, .L156 + 2730 0158 4D4A ldr r2, .L156+4 + 2731 015a 9342 cmp r3, r2 + 2732 015c 18BF it ne + 2733 015e 8B42 cmpne r3, r1 + 2734 0160 42D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2735 .loc 1 729 8 discriminator 2 view .LVU866 + 2736 0162 1832 adds r2, r2, #24 + 2737 0164 9342 cmp r3, r2 + 2738 0166 3FD0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2739 .loc 1 729 8 discriminator 4 view .LVU867 + 2740 0168 1832 adds r2, r2, #24 + 2741 016a 9342 cmp r3, r2 + 2742 016c 3CD0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2743 .loc 1 729 8 discriminator 6 view .LVU868 + 2744 016e 1832 adds r2, r2, #24 + 2745 0170 9342 cmp r3, r2 + 2746 0172 39D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2747 .loc 1 729 8 discriminator 8 view .LVU869 + 2748 0174 1832 adds r2, r2, #24 + 2749 0176 9342 cmp r3, r2 + 2750 0178 36D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2751 .loc 1 729 8 discriminator 10 view .LVU870 + 2752 017a 1832 adds r2, r2, #24 + 2753 017c 9342 cmp r3, r2 + 2754 017e 33D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2755 .loc 1 729 8 discriminator 12 view .LVU871 + 2756 0180 1832 adds r2, r2, #24 + 2757 0182 9342 cmp r3, r2 + 2758 0184 30D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2759 .loc 1 729 8 discriminator 14 view .LVU872 + 2760 0186 02F55672 add r2, r2, #856 + 2761 018a 9342 cmp r3, r2 + 2762 018c 2CD0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2763 .loc 1 729 8 discriminator 16 view .LVU873 + ARM GAS /tmp/ccXv4DVv.s page 97 + + + 2764 018e 1832 adds r2, r2, #24 + 2765 0190 9342 cmp r3, r2 + 2766 0192 29D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2767 .loc 1 729 8 discriminator 18 view .LVU874 + 2768 0194 1832 adds r2, r2, #24 + 2769 0196 9342 cmp r3, r2 + 2770 0198 26D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2771 .loc 1 729 8 discriminator 20 view .LVU875 + 2772 019a 1832 adds r2, r2, #24 + 2773 019c 9342 cmp r3, r2 + 2774 019e 23D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2775 .loc 1 729 8 discriminator 22 view .LVU876 + 2776 01a0 1832 adds r2, r2, #24 + 2777 01a2 9342 cmp r3, r2 + 2778 01a4 20D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2779 .loc 1 729 8 discriminator 24 view .LVU877 + 2780 01a6 1832 adds r2, r2, #24 + 2781 01a8 9342 cmp r3, r2 + 2782 01aa 1DD0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2783 .loc 1 729 8 discriminator 26 view .LVU878 + 2784 01ac 1832 adds r2, r2, #24 + 2785 01ae 9342 cmp r3, r2 + 2786 01b0 1AD0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2787 .loc 1 729 8 discriminator 28 view .LVU879 + 2788 01b2 1832 adds r2, r2, #24 + 2789 01b4 9342 cmp r3, r2 + 2790 01b6 17D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2791 .loc 1 729 8 discriminator 30 view .LVU880 + 2792 01b8 364A ldr r2, .L156+8 + 2793 01ba 9342 cmp r3, r2 + 2794 01bc 14D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2795 .loc 1 729 8 discriminator 32 view .LVU881 + 2796 01be 1432 adds r2, r2, #20 + 2797 01c0 9342 cmp r3, r2 + 2798 01c2 11D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2799 .loc 1 729 8 discriminator 34 view .LVU882 + 2800 01c4 1432 adds r2, r2, #20 + 2801 01c6 9342 cmp r3, r2 + 2802 01c8 0ED0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2803 .loc 1 729 8 discriminator 36 view .LVU883 + 2804 01ca 1432 adds r2, r2, #20 + 2805 01cc 9342 cmp r3, r2 + 2806 01ce 0BD0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2807 .loc 1 729 8 discriminator 38 view .LVU884 + 2808 01d0 1432 adds r2, r2, #20 + 2809 01d2 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 98 + + + 2810 01d4 08D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2811 .loc 1 729 8 discriminator 40 view .LVU885 + 2812 01d6 1432 adds r2, r2, #20 + 2813 01d8 9342 cmp r3, r2 + 2814 01da 05D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2815 .loc 1 729 8 discriminator 42 view .LVU886 + 2816 01dc 1432 adds r2, r2, #20 + 2817 01de 9342 cmp r3, r2 + 2818 01e0 02D0 beq .L144 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2819 .loc 1 729 8 discriminator 44 view .LVU887 + 2820 01e2 1432 adds r2, r2, #20 + 2821 01e4 9342 cmp r3, r2 + 2822 01e6 0ED1 bne .L145 + 2823 .L144: + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2824 .loc 1 732 7 is_stmt 1 view .LVU888 + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2825 .loc 1 732 15 is_stmt 0 view .LVU889 + 2826 01e8 236E ldr r3, [r4, #96] + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2827 .loc 1 732 30 view .LVU890 + 2828 01ea 1A68 ldr r2, [r3] + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2829 .loc 1 732 9 view .LVU891 + 2830 01ec 12F4803F tst r2, #65536 + 2831 01f0 03D0 beq .L146 + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2832 .loc 1 735 9 is_stmt 1 view .LVU892 + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2833 .loc 1 735 34 is_stmt 0 view .LVU893 + 2834 01f2 1A68 ldr r2, [r3] + 2835 01f4 42F48072 orr r2, r2, #256 + 2836 01f8 1A60 str r2, [r3] + 2837 .L146: + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2838 .loc 1 738 7 is_stmt 1 view .LVU894 + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2839 .loc 1 738 14 is_stmt 0 view .LVU895 + 2840 01fa E36E ldr r3, [r4, #108] + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2841 .loc 1 738 9 view .LVU896 + 2842 01fc 1BB1 cbz r3, .L145 + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2843 .loc 1 742 9 is_stmt 1 view .LVU897 + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2844 .loc 1 742 38 is_stmt 0 view .LVU898 + 2845 01fe 1A68 ldr r2, [r3] + 2846 0200 42F48072 orr r2, r2, #256 + 2847 0204 1A60 str r2, [r3] + 2848 .L145: + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2849 .loc 1 747 5 is_stmt 1 view .LVU899 + 2850 0206 2368 ldr r3, [r4] + 2851 0208 2049 ldr r1, .L156 + ARM GAS /tmp/ccXv4DVv.s page 99 + + + 2852 020a 214A ldr r2, .L156+4 + 2853 020c 9342 cmp r3, r2 + 2854 020e 18BF it ne + 2855 0210 8B42 cmpne r3, r1 + 2856 0212 30D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2857 .loc 1 747 5 is_stmt 0 discriminator 2 view .LVU900 + 2858 0214 1832 adds r2, r2, #24 + 2859 0216 9342 cmp r3, r2 + 2860 0218 2DD0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2861 .loc 1 747 5 discriminator 4 view .LVU901 + 2862 021a 1832 adds r2, r2, #24 + 2863 021c 9342 cmp r3, r2 + 2864 021e 2AD0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2865 .loc 1 747 5 discriminator 6 view .LVU902 + 2866 0220 1832 adds r2, r2, #24 + 2867 0222 9342 cmp r3, r2 + 2868 0224 27D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2869 .loc 1 747 5 discriminator 8 view .LVU903 + 2870 0226 1832 adds r2, r2, #24 + 2871 0228 9342 cmp r3, r2 + 2872 022a 24D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2873 .loc 1 747 5 discriminator 10 view .LVU904 + 2874 022c 1832 adds r2, r2, #24 + 2875 022e 9342 cmp r3, r2 + 2876 0230 21D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2877 .loc 1 747 5 discriminator 12 view .LVU905 + 2878 0232 1832 adds r2, r2, #24 + 2879 0234 9342 cmp r3, r2 + 2880 0236 1ED0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2881 .loc 1 747 5 discriminator 14 view .LVU906 + 2882 0238 02F55672 add r2, r2, #856 + 2883 023c 9342 cmp r3, r2 + 2884 023e 1AD0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2885 .loc 1 747 5 discriminator 16 view .LVU907 + 2886 0240 1832 adds r2, r2, #24 + 2887 0242 9342 cmp r3, r2 + 2888 0244 17D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2889 .loc 1 747 5 discriminator 18 view .LVU908 + 2890 0246 1832 adds r2, r2, #24 + 2891 0248 9342 cmp r3, r2 + 2892 024a 14D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2893 .loc 1 747 5 discriminator 20 view .LVU909 + 2894 024c 1832 adds r2, r2, #24 + 2895 024e 9342 cmp r3, r2 + 2896 0250 11D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2897 .loc 1 747 5 discriminator 22 view .LVU910 + ARM GAS /tmp/ccXv4DVv.s page 100 + + + 2898 0252 1832 adds r2, r2, #24 + 2899 0254 9342 cmp r3, r2 + 2900 0256 0ED0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2901 .loc 1 747 5 discriminator 24 view .LVU911 + 2902 0258 1832 adds r2, r2, #24 + 2903 025a 9342 cmp r3, r2 + 2904 025c 0BD0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2905 .loc 1 747 5 discriminator 26 view .LVU912 + 2906 025e 1832 adds r2, r2, #24 + 2907 0260 9342 cmp r3, r2 + 2908 0262 08D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2909 .loc 1 747 5 discriminator 28 view .LVU913 + 2910 0264 1832 adds r2, r2, #24 + 2911 0266 9342 cmp r3, r2 + 2912 0268 05D0 beq .L147 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2913 .loc 1 747 5 discriminator 30 view .LVU914 + 2914 026a 1A68 ldr r2, [r3] + 2915 026c 42F00102 orr r2, r2, #1 + 2916 0270 1A60 str r2, [r3] + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2917 .loc 1 678 21 discriminator 30 view .LVU915 + 2918 0272 0020 movs r0, #0 + 2919 0274 DDE6 b .L136 + 2920 .L147: + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2921 .loc 1 747 5 discriminator 29 view .LVU916 + 2922 0276 1A68 ldr r2, [r3] + 2923 0278 42F00102 orr r2, r2, #1 + 2924 027c 1A60 str r2, [r3] + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2925 .loc 1 678 21 discriminator 29 view .LVU917 + 2926 027e 0020 movs r0, #0 + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2927 .loc 1 747 5 discriminator 29 view .LVU918 + 2928 0280 D7E6 b .L136 + 2929 .LVL131: + 2930 .L149: + 2931 .LCFI15: + 2932 .cfi_def_cfa_offset 0 + 2933 .cfi_restore 4 + 2934 .cfi_restore 5 + 2935 .cfi_restore 6 + 2936 .cfi_restore 14 + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 2937 .loc 1 686 12 view .LVU919 + 2938 0282 0120 movs r0, #1 + 2939 .LVL132: + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2940 .loc 1 762 1 view .LVU920 + 2941 0284 7047 bx lr + 2942 .LVL133: + 2943 .L150: + 2944 .LCFI16: + ARM GAS /tmp/ccXv4DVv.s page 101 + + + 2945 .cfi_def_cfa_offset 16 + 2946 .cfi_offset 4, -16 + 2947 .cfi_offset 5, -12 + 2948 .cfi_offset 6, -8 + 2949 .cfi_offset 14, -4 + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2950 .loc 1 690 3 view .LVU921 + 2951 0286 0220 movs r0, #2 + 2952 0288 D3E6 b .L136 + 2953 .L157: + 2954 028a 00BF .align 2 + 2955 .L156: + 2956 028c 10000240 .word 1073872912 + 2957 0290 28000240 .word 1073872936 + 2958 0294 08540258 .word 1476547592 + 2959 .cfi_endproc + 2960 .LFE144: + 2962 .section .text.HAL_DMA_Abort,"ax",%progbits + 2963 .align 1 + 2964 .global HAL_DMA_Abort + 2965 .syntax unified + 2966 .thumb + 2967 .thumb_func + 2968 .fpu fpv5-d16 + 2970 HAL_DMA_Abort: + 2971 .LVL134: + 2972 .LFB145: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 2973 .loc 1 777 1 is_stmt 1 view -0 + 2974 .cfi_startproc + 2975 @ args = 0, pretend = 0, frame = 0 + 2976 @ frame_needed = 0, uses_anonymous_args = 0 + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 2977 .loc 1 777 1 is_stmt 0 view .LVU923 + 2978 0000 70B5 push {r4, r5, r6, lr} + 2979 .LCFI17: + 2980 .cfi_def_cfa_offset 16 + 2981 .cfi_offset 4, -16 + 2982 .cfi_offset 5, -12 + 2983 .cfi_offset 6, -8 + 2984 .cfi_offset 14, -4 + 2985 0002 0446 mov r4, r0 + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 2986 .loc 1 779 3 is_stmt 1 view .LVU924 + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** const __IO uint32_t *enableRegister; + 2987 .loc 1 780 3 view .LVU925 + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2988 .loc 1 781 3 view .LVU926 + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2989 .loc 1 783 3 view .LVU927 + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 2990 .loc 1 783 24 is_stmt 0 view .LVU928 + 2991 0004 FFF7FEFF bl HAL_GetTick + 2992 .LVL135: + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2993 .loc 1 786 3 is_stmt 1 view .LVU929 + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 102 + + + 2994 .loc 1 786 5 is_stmt 0 view .LVU930 + 2995 0008 002C cmp r4, #0 + 2996 000a 00F09181 beq .L174 + 2997 000e 0546 mov r5, r0 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2998 .loc 1 792 3 is_stmt 1 view .LVU931 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 2999 .loc 1 792 10 is_stmt 0 view .LVU932 + 3000 0010 94F83530 ldrb r3, [r4, #53] @ zero_extendqisi2 + 3001 0014 DBB2 uxtb r3, r3 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3002 .loc 1 792 5 view .LVU933 + 3003 0016 022B cmp r3, #2 + 3004 0018 06D0 beq .L160 + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3005 .loc 1 794 5 is_stmt 1 view .LVU934 + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3006 .loc 1 794 21 is_stmt 0 view .LVU935 + 3007 001a 8023 movs r3, #128 + 3008 001c 6365 str r3, [r4, #84] + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3009 .loc 1 797 5 is_stmt 1 view .LVU936 + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3010 .loc 1 797 5 view .LVU937 + 3011 001e 0023 movs r3, #0 + 3012 0020 84F83430 strb r3, [r4, #52] + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3013 .loc 1 797 5 view .LVU938 + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3014 .loc 1 799 5 view .LVU939 + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3015 .loc 1 799 12 is_stmt 0 view .LVU940 + 3016 0024 0120 movs r0, #1 + 3017 .LVL136: + 3018 .L159: + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3019 .loc 1 884 1 view .LVU941 + 3020 0026 70BD pop {r4, r5, r6, pc} + 3021 .LVL137: + 3022 .L160: + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3023 .loc 1 804 5 is_stmt 1 view .LVU942 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3024 .loc 1 804 8 is_stmt 0 view .LVU943 + 3025 0028 2368 ldr r3, [r4] + 3026 002a 8C49 ldr r1, .L177 + 3027 002c 8C4A ldr r2, .L177+4 + 3028 002e 9342 cmp r3, r2 + 3029 0030 18BF it ne + 3030 0032 8B42 cmpne r3, r1 + 3031 0034 30D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3032 .loc 1 804 8 discriminator 2 view .LVU944 + 3033 0036 1832 adds r2, r2, #24 + 3034 0038 9342 cmp r3, r2 + 3035 003a 2DD0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 103 + + + 3036 .loc 1 804 8 discriminator 4 view .LVU945 + 3037 003c 1832 adds r2, r2, #24 + 3038 003e 9342 cmp r3, r2 + 3039 0040 2AD0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3040 .loc 1 804 8 discriminator 6 view .LVU946 + 3041 0042 1832 adds r2, r2, #24 + 3042 0044 9342 cmp r3, r2 + 3043 0046 27D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3044 .loc 1 804 8 discriminator 8 view .LVU947 + 3045 0048 1832 adds r2, r2, #24 + 3046 004a 9342 cmp r3, r2 + 3047 004c 24D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3048 .loc 1 804 8 discriminator 10 view .LVU948 + 3049 004e 1832 adds r2, r2, #24 + 3050 0050 9342 cmp r3, r2 + 3051 0052 21D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3052 .loc 1 804 8 discriminator 12 view .LVU949 + 3053 0054 1832 adds r2, r2, #24 + 3054 0056 9342 cmp r3, r2 + 3055 0058 1ED0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3056 .loc 1 804 8 discriminator 14 view .LVU950 + 3057 005a 02F55672 add r2, r2, #856 + 3058 005e 9342 cmp r3, r2 + 3059 0060 1AD0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3060 .loc 1 804 8 discriminator 16 view .LVU951 + 3061 0062 1832 adds r2, r2, #24 + 3062 0064 9342 cmp r3, r2 + 3063 0066 17D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3064 .loc 1 804 8 discriminator 18 view .LVU952 + 3065 0068 1832 adds r2, r2, #24 + 3066 006a 9342 cmp r3, r2 + 3067 006c 14D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3068 .loc 1 804 8 discriminator 20 view .LVU953 + 3069 006e 1832 adds r2, r2, #24 + 3070 0070 9342 cmp r3, r2 + 3071 0072 11D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3072 .loc 1 804 8 discriminator 22 view .LVU954 + 3073 0074 1832 adds r2, r2, #24 + 3074 0076 9342 cmp r3, r2 + 3075 0078 0ED0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3076 .loc 1 804 8 discriminator 24 view .LVU955 + 3077 007a 1832 adds r2, r2, #24 + 3078 007c 9342 cmp r3, r2 + 3079 007e 0BD0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3080 .loc 1 804 8 discriminator 26 view .LVU956 + 3081 0080 1832 adds r2, r2, #24 + ARM GAS /tmp/ccXv4DVv.s page 104 + + + 3082 0082 9342 cmp r3, r2 + 3083 0084 08D0 beq .L161 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3084 .loc 1 804 8 discriminator 28 view .LVU957 + 3085 0086 1832 adds r2, r2, #24 + 3086 0088 9342 cmp r3, r2 + 3087 008a 05D0 beq .L161 + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3088 .loc 1 815 7 is_stmt 1 view .LVU958 + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3089 .loc 1 815 56 is_stmt 0 view .LVU959 + 3090 008c 1A68 ldr r2, [r3] + 3091 008e 22F00E02 bic r2, r2, #14 + 3092 0092 1A60 str r2, [r3] + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3093 .loc 1 817 7 is_stmt 1 view .LVU960 + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3094 .loc 1 817 75 is_stmt 0 view .LVU961 + 3095 0094 2668 ldr r6, [r4] + 3096 .LVL138: + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3097 .loc 1 817 75 view .LVU962 + 3098 0096 09E0 b .L162 + 3099 .LVL139: + 3100 .L161: + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + 3101 .loc 1 807 7 is_stmt 1 view .LVU963 + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + 3102 .loc 1 807 53 is_stmt 0 view .LVU964 + 3103 0098 1A68 ldr r2, [r3] + 3104 009a 22F01E02 bic r2, r2, #30 + 3105 009e 1A60 str r2, [r3] + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3106 .loc 1 808 7 is_stmt 1 view .LVU965 + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3107 .loc 1 808 36 is_stmt 0 view .LVU966 + 3108 00a0 2268 ldr r2, [r4] + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3109 .loc 1 808 53 view .LVU967 + 3110 00a2 5369 ldr r3, [r2, #20] + 3111 00a4 23F08003 bic r3, r3, #128 + 3112 00a8 5361 str r3, [r2, #20] + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3113 .loc 1 810 7 is_stmt 1 view .LVU968 + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3114 .loc 1 810 73 is_stmt 0 view .LVU969 + 3115 00aa 2668 ldr r6, [r4] + 3116 .LVL140: + 3117 .L162: + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3118 .loc 1 820 5 is_stmt 1 view .LVU970 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3119 .loc 1 820 8 is_stmt 0 view .LVU971 + 3120 00ac 2368 ldr r3, [r4] + 3121 00ae 6B49 ldr r1, .L177 + 3122 00b0 6B4A ldr r2, .L177+4 + 3123 00b2 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 105 + + + 3124 00b4 18BF it ne + 3125 00b6 8B42 cmpne r3, r1 + 3126 00b8 42D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3127 .loc 1 820 8 discriminator 2 view .LVU972 + 3128 00ba 1832 adds r2, r2, #24 + 3129 00bc 9342 cmp r3, r2 + 3130 00be 3FD0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3131 .loc 1 820 8 discriminator 4 view .LVU973 + 3132 00c0 1832 adds r2, r2, #24 + 3133 00c2 9342 cmp r3, r2 + 3134 00c4 3CD0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3135 .loc 1 820 8 discriminator 6 view .LVU974 + 3136 00c6 1832 adds r2, r2, #24 + 3137 00c8 9342 cmp r3, r2 + 3138 00ca 39D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3139 .loc 1 820 8 discriminator 8 view .LVU975 + 3140 00cc 1832 adds r2, r2, #24 + 3141 00ce 9342 cmp r3, r2 + 3142 00d0 36D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3143 .loc 1 820 8 discriminator 10 view .LVU976 + 3144 00d2 1832 adds r2, r2, #24 + 3145 00d4 9342 cmp r3, r2 + 3146 00d6 33D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3147 .loc 1 820 8 discriminator 12 view .LVU977 + 3148 00d8 1832 adds r2, r2, #24 + 3149 00da 9342 cmp r3, r2 + 3150 00dc 30D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3151 .loc 1 820 8 discriminator 14 view .LVU978 + 3152 00de 02F55672 add r2, r2, #856 + 3153 00e2 9342 cmp r3, r2 + 3154 00e4 2CD0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3155 .loc 1 820 8 discriminator 16 view .LVU979 + 3156 00e6 1832 adds r2, r2, #24 + 3157 00e8 9342 cmp r3, r2 + 3158 00ea 29D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3159 .loc 1 820 8 discriminator 18 view .LVU980 + 3160 00ec 1832 adds r2, r2, #24 + 3161 00ee 9342 cmp r3, r2 + 3162 00f0 26D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3163 .loc 1 820 8 discriminator 20 view .LVU981 + 3164 00f2 1832 adds r2, r2, #24 + 3165 00f4 9342 cmp r3, r2 + 3166 00f6 23D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3167 .loc 1 820 8 discriminator 22 view .LVU982 + 3168 00f8 1832 adds r2, r2, #24 + 3169 00fa 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 106 + + + 3170 00fc 20D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3171 .loc 1 820 8 discriminator 24 view .LVU983 + 3172 00fe 1832 adds r2, r2, #24 + 3173 0100 9342 cmp r3, r2 + 3174 0102 1DD0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3175 .loc 1 820 8 discriminator 26 view .LVU984 + 3176 0104 1832 adds r2, r2, #24 + 3177 0106 9342 cmp r3, r2 + 3178 0108 1AD0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3179 .loc 1 820 8 discriminator 28 view .LVU985 + 3180 010a 1832 adds r2, r2, #24 + 3181 010c 9342 cmp r3, r2 + 3182 010e 17D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3183 .loc 1 820 8 discriminator 30 view .LVU986 + 3184 0110 544A ldr r2, .L177+8 + 3185 0112 9342 cmp r3, r2 + 3186 0114 14D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3187 .loc 1 820 8 discriminator 32 view .LVU987 + 3188 0116 1432 adds r2, r2, #20 + 3189 0118 9342 cmp r3, r2 + 3190 011a 11D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3191 .loc 1 820 8 discriminator 34 view .LVU988 + 3192 011c 1432 adds r2, r2, #20 + 3193 011e 9342 cmp r3, r2 + 3194 0120 0ED0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3195 .loc 1 820 8 discriminator 36 view .LVU989 + 3196 0122 1432 adds r2, r2, #20 + 3197 0124 9342 cmp r3, r2 + 3198 0126 0BD0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3199 .loc 1 820 8 discriminator 38 view .LVU990 + 3200 0128 1432 adds r2, r2, #20 + 3201 012a 9342 cmp r3, r2 + 3202 012c 08D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3203 .loc 1 820 8 discriminator 40 view .LVU991 + 3204 012e 1432 adds r2, r2, #20 + 3205 0130 9342 cmp r3, r2 + 3206 0132 05D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3207 .loc 1 820 8 discriminator 42 view .LVU992 + 3208 0134 1432 adds r2, r2, #20 + 3209 0136 9342 cmp r3, r2 + 3210 0138 02D0 beq .L163 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3211 .loc 1 820 8 discriminator 44 view .LVU993 + 3212 013a 1432 adds r2, r2, #20 + 3213 013c 9342 cmp r3, r2 + 3214 013e 04D1 bne .L164 + 3215 .L163: + ARM GAS /tmp/ccXv4DVv.s page 107 + + + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3216 .loc 1 823 7 is_stmt 1 view .LVU994 + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3217 .loc 1 823 11 is_stmt 0 view .LVU995 + 3218 0140 226E ldr r2, [r4, #96] + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3219 .loc 1 823 32 view .LVU996 + 3220 0142 1368 ldr r3, [r2] + 3221 0144 23F48073 bic r3, r3, #256 + 3222 0148 1360 str r3, [r2] + 3223 .L164: + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3224 .loc 1 827 5 is_stmt 1 view .LVU997 + 3225 014a 2368 ldr r3, [r4] + 3226 014c 4349 ldr r1, .L177 + 3227 014e 444A ldr r2, .L177+4 + 3228 0150 9342 cmp r3, r2 + 3229 0152 18BF it ne + 3230 0154 8B42 cmpne r3, r1 + 3231 0156 2FD0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3232 .loc 1 827 5 is_stmt 0 discriminator 2 view .LVU998 + 3233 0158 1832 adds r2, r2, #24 + 3234 015a 9342 cmp r3, r2 + 3235 015c 2CD0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3236 .loc 1 827 5 discriminator 4 view .LVU999 + 3237 015e 1832 adds r2, r2, #24 + 3238 0160 9342 cmp r3, r2 + 3239 0162 29D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3240 .loc 1 827 5 discriminator 6 view .LVU1000 + 3241 0164 1832 adds r2, r2, #24 + 3242 0166 9342 cmp r3, r2 + 3243 0168 26D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3244 .loc 1 827 5 discriminator 8 view .LVU1001 + 3245 016a 1832 adds r2, r2, #24 + 3246 016c 9342 cmp r3, r2 + 3247 016e 23D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3248 .loc 1 827 5 discriminator 10 view .LVU1002 + 3249 0170 1832 adds r2, r2, #24 + 3250 0172 9342 cmp r3, r2 + 3251 0174 20D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3252 .loc 1 827 5 discriminator 12 view .LVU1003 + 3253 0176 1832 adds r2, r2, #24 + 3254 0178 9342 cmp r3, r2 + 3255 017a 1DD0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3256 .loc 1 827 5 discriminator 14 view .LVU1004 + 3257 017c 02F55672 add r2, r2, #856 + 3258 0180 9342 cmp r3, r2 + 3259 0182 19D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3260 .loc 1 827 5 discriminator 16 view .LVU1005 + ARM GAS /tmp/ccXv4DVv.s page 108 + + + 3261 0184 1832 adds r2, r2, #24 + 3262 0186 9342 cmp r3, r2 + 3263 0188 16D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3264 .loc 1 827 5 discriminator 18 view .LVU1006 + 3265 018a 1832 adds r2, r2, #24 + 3266 018c 9342 cmp r3, r2 + 3267 018e 13D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3268 .loc 1 827 5 discriminator 20 view .LVU1007 + 3269 0190 1832 adds r2, r2, #24 + 3270 0192 9342 cmp r3, r2 + 3271 0194 10D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3272 .loc 1 827 5 discriminator 22 view .LVU1008 + 3273 0196 1832 adds r2, r2, #24 + 3274 0198 9342 cmp r3, r2 + 3275 019a 0DD0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3276 .loc 1 827 5 discriminator 24 view .LVU1009 + 3277 019c 1832 adds r2, r2, #24 + 3278 019e 9342 cmp r3, r2 + 3279 01a0 0AD0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3280 .loc 1 827 5 discriminator 26 view .LVU1010 + 3281 01a2 1832 adds r2, r2, #24 + 3282 01a4 9342 cmp r3, r2 + 3283 01a6 07D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3284 .loc 1 827 5 discriminator 28 view .LVU1011 + 3285 01a8 1832 adds r2, r2, #24 + 3286 01aa 9342 cmp r3, r2 + 3287 01ac 04D0 beq .L165 + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3288 .loc 1 827 5 discriminator 30 view .LVU1012 + 3289 01ae 1A68 ldr r2, [r3] + 3290 01b0 22F00102 bic r2, r2, #1 + 3291 01b4 1A60 str r2, [r3] + 3292 01b6 03E0 b .L168 + 3293 .L165: + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3294 .loc 1 827 5 discriminator 29 view .LVU1013 + 3295 01b8 1A68 ldr r2, [r3] + 3296 01ba 22F00102 bic r2, r2, #1 + 3297 01be 1A60 str r2, [r3] + 3298 .LVL141: + 3299 .L168: + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3300 .loc 1 830 10 is_stmt 1 view .LVU1014 + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3301 .loc 1 830 13 is_stmt 0 view .LVU1015 + 3302 01c0 3368 ldr r3, [r6] + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3303 .loc 1 830 10 view .LVU1016 + 3304 01c2 13F0010F tst r3, #1 + 3305 01c6 0ED0 beq .L176 + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 109 + + + 3306 .loc 1 833 7 is_stmt 1 view .LVU1017 + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3307 .loc 1 833 11 is_stmt 0 view .LVU1018 + 3308 01c8 FFF7FEFF bl HAL_GetTick + 3309 .LVL142: + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3310 .loc 1 833 25 view .LVU1019 + 3311 01cc 431B subs r3, r0, r5 + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3312 .loc 1 833 9 view .LVU1020 + 3313 01ce 052B cmp r3, #5 + 3314 01d0 F6D9 bls .L168 + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3315 .loc 1 836 9 is_stmt 1 view .LVU1021 + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3316 .loc 1 836 25 is_stmt 0 view .LVU1022 + 3317 01d2 2023 movs r3, #32 + 3318 01d4 6365 str r3, [r4, #84] + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3319 .loc 1 839 9 is_stmt 1 view .LVU1023 + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3320 .loc 1 839 9 view .LVU1024 + 3321 01d6 0023 movs r3, #0 + 3322 01d8 84F83430 strb r3, [r4, #52] + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3323 .loc 1 839 9 view .LVU1025 + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3324 .loc 1 842 9 view .LVU1026 + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3325 .loc 1 842 21 is_stmt 0 view .LVU1027 + 3326 01dc 0323 movs r3, #3 + 3327 01de 84F83530 strb r3, [r4, #53] + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3328 .loc 1 844 9 is_stmt 1 view .LVU1028 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3329 .loc 1 844 16 is_stmt 0 view .LVU1029 + 3330 01e2 0120 movs r0, #1 + 3331 01e4 1FE7 b .L159 + 3332 .L176: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3333 .loc 1 849 5 is_stmt 1 view .LVU1030 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3334 .loc 1 849 8 is_stmt 0 view .LVU1031 + 3335 01e6 2368 ldr r3, [r4] + 3336 01e8 1C49 ldr r1, .L177 + 3337 01ea 1D4A ldr r2, .L177+4 + 3338 01ec 9342 cmp r3, r2 + 3339 01ee 18BF it ne + 3340 01f0 8B42 cmpne r3, r1 + 3341 01f2 39D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3342 .loc 1 849 8 discriminator 2 view .LVU1032 + 3343 01f4 1832 adds r2, r2, #24 + 3344 01f6 9342 cmp r3, r2 + 3345 01f8 36D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3346 .loc 1 849 8 discriminator 4 view .LVU1033 + ARM GAS /tmp/ccXv4DVv.s page 110 + + + 3347 01fa 1832 adds r2, r2, #24 + 3348 01fc 9342 cmp r3, r2 + 3349 01fe 33D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3350 .loc 1 849 8 discriminator 6 view .LVU1034 + 3351 0200 1832 adds r2, r2, #24 + 3352 0202 9342 cmp r3, r2 + 3353 0204 30D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3354 .loc 1 849 8 discriminator 8 view .LVU1035 + 3355 0206 1832 adds r2, r2, #24 + 3356 0208 9342 cmp r3, r2 + 3357 020a 2DD0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3358 .loc 1 849 8 discriminator 10 view .LVU1036 + 3359 020c 1832 adds r2, r2, #24 + 3360 020e 9342 cmp r3, r2 + 3361 0210 2AD0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3362 .loc 1 849 8 discriminator 12 view .LVU1037 + 3363 0212 1832 adds r2, r2, #24 + 3364 0214 9342 cmp r3, r2 + 3365 0216 27D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3366 .loc 1 849 8 discriminator 14 view .LVU1038 + 3367 0218 02F55672 add r2, r2, #856 + 3368 021c 9342 cmp r3, r2 + 3369 021e 23D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3370 .loc 1 849 8 discriminator 16 view .LVU1039 + 3371 0220 1832 adds r2, r2, #24 + 3372 0222 9342 cmp r3, r2 + 3373 0224 20D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3374 .loc 1 849 8 discriminator 18 view .LVU1040 + 3375 0226 1832 adds r2, r2, #24 + 3376 0228 9342 cmp r3, r2 + 3377 022a 1DD0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3378 .loc 1 849 8 discriminator 20 view .LVU1041 + 3379 022c 1832 adds r2, r2, #24 + 3380 022e 9342 cmp r3, r2 + 3381 0230 1AD0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3382 .loc 1 849 8 discriminator 22 view .LVU1042 + 3383 0232 1832 adds r2, r2, #24 + 3384 0234 9342 cmp r3, r2 + 3385 0236 17D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3386 .loc 1 849 8 discriminator 24 view .LVU1043 + 3387 0238 1832 adds r2, r2, #24 + 3388 023a 9342 cmp r3, r2 + 3389 023c 14D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3390 .loc 1 849 8 discriminator 26 view .LVU1044 + 3391 023e 1832 adds r2, r2, #24 + 3392 0240 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 111 + + + 3393 0242 11D0 beq .L170 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3394 .loc 1 849 8 discriminator 28 view .LVU1045 + 3395 0244 1832 adds r2, r2, #24 + 3396 0246 9342 cmp r3, r2 + 3397 0248 0ED0 beq .L170 + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 3398 .loc 1 856 7 is_stmt 1 view .LVU1046 + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 3399 .loc 1 856 46 is_stmt 0 view .LVU1047 + 3400 024a A16D ldr r1, [r4, #88] + 3401 .LVL143: + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3402 .loc 1 857 7 is_stmt 1 view .LVU1048 + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3403 .loc 1 857 52 is_stmt 0 view .LVU1049 + 3404 024c E36D ldr r3, [r4, #92] + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3405 .loc 1 857 66 view .LVU1050 + 3406 024e 03F01F02 and r2, r3, #31 + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3407 .loc 1 857 44 view .LVU1051 + 3408 0252 0123 movs r3, #1 + 3409 0254 9340 lsls r3, r3, r2 + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3410 .loc 1 857 23 view .LVU1052 + 3411 0256 4B60 str r3, [r1, #4] + 3412 0258 0DE0 b .L171 + 3413 .L178: + 3414 025a 00BF .align 2 + 3415 .L177: + 3416 025c 10000240 .word 1073872912 + 3417 0260 28000240 .word 1073872936 + 3418 0264 08540258 .word 1476547592 + 3419 .LVL144: + 3420 .L170: + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 3421 .loc 1 851 7 is_stmt 1 view .LVU1053 + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 3422 .loc 1 851 44 is_stmt 0 view .LVU1054 + 3423 0268 A16D ldr r1, [r4, #88] + 3424 .LVL145: + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3425 .loc 1 852 7 is_stmt 1 view .LVU1055 + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3426 .loc 1 852 39 is_stmt 0 view .LVU1056 + 3427 026a E36D ldr r3, [r4, #92] + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3428 .loc 1 852 53 view .LVU1057 + 3429 026c 03F01F02 and r2, r3, #31 + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3430 .loc 1 852 31 view .LVU1058 + 3431 0270 3F23 movs r3, #63 + 3432 0272 9340 lsls r3, r3, r2 + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3433 .loc 1 852 22 view .LVU1059 + 3434 0274 8B60 str r3, [r1, #8] + ARM GAS /tmp/ccXv4DVv.s page 112 + + + 3435 .LVL146: + 3436 .L171: + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3437 .loc 1 860 5 is_stmt 1 view .LVU1060 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3438 .loc 1 860 8 is_stmt 0 view .LVU1061 + 3439 0276 2368 ldr r3, [r4] + 3440 0278 2E49 ldr r1, .L179 + 3441 027a 2F4A ldr r2, .L179+4 + 3442 027c 9342 cmp r3, r2 + 3443 027e 18BF it ne + 3444 0280 8B42 cmpne r3, r1 + 3445 0282 42D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3446 .loc 1 860 8 discriminator 2 view .LVU1062 + 3447 0284 1832 adds r2, r2, #24 + 3448 0286 9342 cmp r3, r2 + 3449 0288 3FD0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3450 .loc 1 860 8 discriminator 4 view .LVU1063 + 3451 028a 1832 adds r2, r2, #24 + 3452 028c 9342 cmp r3, r2 + 3453 028e 3CD0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3454 .loc 1 860 8 discriminator 6 view .LVU1064 + 3455 0290 1832 adds r2, r2, #24 + 3456 0292 9342 cmp r3, r2 + 3457 0294 39D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3458 .loc 1 860 8 discriminator 8 view .LVU1065 + 3459 0296 1832 adds r2, r2, #24 + 3460 0298 9342 cmp r3, r2 + 3461 029a 36D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3462 .loc 1 860 8 discriminator 10 view .LVU1066 + 3463 029c 1832 adds r2, r2, #24 + 3464 029e 9342 cmp r3, r2 + 3465 02a0 33D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3466 .loc 1 860 8 discriminator 12 view .LVU1067 + 3467 02a2 1832 adds r2, r2, #24 + 3468 02a4 9342 cmp r3, r2 + 3469 02a6 30D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3470 .loc 1 860 8 discriminator 14 view .LVU1068 + 3471 02a8 02F55672 add r2, r2, #856 + 3472 02ac 9342 cmp r3, r2 + 3473 02ae 2CD0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3474 .loc 1 860 8 discriminator 16 view .LVU1069 + 3475 02b0 1832 adds r2, r2, #24 + 3476 02b2 9342 cmp r3, r2 + 3477 02b4 29D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3478 .loc 1 860 8 discriminator 18 view .LVU1070 + 3479 02b6 1832 adds r2, r2, #24 + 3480 02b8 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 113 + + + 3481 02ba 26D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3482 .loc 1 860 8 discriminator 20 view .LVU1071 + 3483 02bc 1832 adds r2, r2, #24 + 3484 02be 9342 cmp r3, r2 + 3485 02c0 23D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3486 .loc 1 860 8 discriminator 22 view .LVU1072 + 3487 02c2 1832 adds r2, r2, #24 + 3488 02c4 9342 cmp r3, r2 + 3489 02c6 20D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3490 .loc 1 860 8 discriminator 24 view .LVU1073 + 3491 02c8 1832 adds r2, r2, #24 + 3492 02ca 9342 cmp r3, r2 + 3493 02cc 1DD0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3494 .loc 1 860 8 discriminator 26 view .LVU1074 + 3495 02ce 1832 adds r2, r2, #24 + 3496 02d0 9342 cmp r3, r2 + 3497 02d2 1AD0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3498 .loc 1 860 8 discriminator 28 view .LVU1075 + 3499 02d4 1832 adds r2, r2, #24 + 3500 02d6 9342 cmp r3, r2 + 3501 02d8 17D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3502 .loc 1 860 8 discriminator 30 view .LVU1076 + 3503 02da 184A ldr r2, .L179+8 + 3504 02dc 9342 cmp r3, r2 + 3505 02de 14D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3506 .loc 1 860 8 discriminator 32 view .LVU1077 + 3507 02e0 1432 adds r2, r2, #20 + 3508 02e2 9342 cmp r3, r2 + 3509 02e4 11D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3510 .loc 1 860 8 discriminator 34 view .LVU1078 + 3511 02e6 1432 adds r2, r2, #20 + 3512 02e8 9342 cmp r3, r2 + 3513 02ea 0ED0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3514 .loc 1 860 8 discriminator 36 view .LVU1079 + 3515 02ec 1432 adds r2, r2, #20 + 3516 02ee 9342 cmp r3, r2 + 3517 02f0 0BD0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3518 .loc 1 860 8 discriminator 38 view .LVU1080 + 3519 02f2 1432 adds r2, r2, #20 + 3520 02f4 9342 cmp r3, r2 + 3521 02f6 08D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3522 .loc 1 860 8 discriminator 40 view .LVU1081 + 3523 02f8 1432 adds r2, r2, #20 + 3524 02fa 9342 cmp r3, r2 + 3525 02fc 05D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 114 + + + 3526 .loc 1 860 8 discriminator 42 view .LVU1082 + 3527 02fe 1432 adds r2, r2, #20 + 3528 0300 9342 cmp r3, r2 + 3529 0302 02D0 beq .L172 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3530 .loc 1 860 8 discriminator 44 view .LVU1083 + 3531 0304 1432 adds r2, r2, #20 + 3532 0306 9342 cmp r3, r2 + 3533 0308 0BD1 bne .L173 + 3534 .L172: + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3535 .loc 1 863 7 is_stmt 1 view .LVU1084 + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3536 .loc 1 863 11 is_stmt 0 view .LVU1085 + 3537 030a 636E ldr r3, [r4, #100] + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3538 .loc 1 863 44 view .LVU1086 + 3539 030c A26E ldr r2, [r4, #104] + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3540 .loc 1 863 38 view .LVU1087 + 3541 030e 5A60 str r2, [r3, #4] + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3542 .loc 1 865 7 is_stmt 1 view .LVU1088 + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3543 .loc 1 865 14 is_stmt 0 view .LVU1089 + 3544 0310 E36E ldr r3, [r4, #108] + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3545 .loc 1 865 9 view .LVU1090 + 3546 0312 33B1 cbz r3, .L173 + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3547 .loc 1 869 9 is_stmt 1 view .LVU1091 + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3548 .loc 1 869 38 is_stmt 0 view .LVU1092 + 3549 0314 1A68 ldr r2, [r3] + 3550 0316 22F48072 bic r2, r2, #256 + 3551 031a 1A60 str r2, [r3] + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3552 .loc 1 872 9 is_stmt 1 view .LVU1093 + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3553 .loc 1 872 13 is_stmt 0 view .LVU1094 + 3554 031c 236F ldr r3, [r4, #112] + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3555 .loc 1 872 51 view .LVU1095 + 3556 031e 626F ldr r2, [r4, #116] + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3557 .loc 1 872 45 view .LVU1096 + 3558 0320 5A60 str r2, [r3, #4] + 3559 .L173: + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3560 .loc 1 877 5 is_stmt 1 view .LVU1097 + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3561 .loc 1 877 5 view .LVU1098 + 3562 0322 0020 movs r0, #0 + 3563 0324 84F83400 strb r0, [r4, #52] + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3564 .loc 1 877 5 view .LVU1099 + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 115 + + + 3565 .loc 1 880 5 view .LVU1100 + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3566 .loc 1 880 17 is_stmt 0 view .LVU1101 + 3567 0328 0123 movs r3, #1 + 3568 032a 84F83530 strb r3, [r4, #53] + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3569 .loc 1 883 3 is_stmt 1 view .LVU1102 + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3570 .loc 1 883 10 is_stmt 0 view .LVU1103 + 3571 032e 7AE6 b .L159 + 3572 .LVL147: + 3573 .L174: + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3574 .loc 1 788 12 view .LVU1104 + 3575 0330 0120 movs r0, #1 + 3576 .LVL148: + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3577 .loc 1 788 12 view .LVU1105 + 3578 0332 78E6 b .L159 + 3579 .L180: + 3580 .align 2 + 3581 .L179: + 3582 0334 10000240 .word 1073872912 + 3583 0338 28000240 .word 1073872936 + 3584 033c 08540258 .word 1476547592 + 3585 .cfi_endproc + 3586 .LFE145: + 3588 .section .text.HAL_DMA_Abort_IT,"ax",%progbits + 3589 .align 1 + 3590 .global HAL_DMA_Abort_IT + 3591 .syntax unified + 3592 .thumb + 3593 .thumb_func + 3594 .fpu fpv5-d16 + 3596 HAL_DMA_Abort_IT: + 3597 .LVL149: + 3598 .LFB146: + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 3599 .loc 1 893 1 is_stmt 1 view -0 + 3600 .cfi_startproc + 3601 @ args = 0, pretend = 0, frame = 0 + 3602 @ frame_needed = 0, uses_anonymous_args = 0 + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3603 .loc 1 894 3 view .LVU1107 + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3604 .loc 1 897 3 view .LVU1108 + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3605 .loc 1 897 5 is_stmt 0 view .LVU1109 + 3606 0000 0028 cmp r0, #0 + 3607 0002 00F02981 beq .L193 + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma; + 3608 .loc 1 893 1 view .LVU1110 + 3609 0006 08B5 push {r3, lr} + 3610 .LCFI18: + 3611 .cfi_def_cfa_offset 8 + 3612 .cfi_offset 3, -8 + 3613 .cfi_offset 14, -4 + ARM GAS /tmp/ccXv4DVv.s page 116 + + + 3614 0008 0246 mov r2, r0 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3615 .loc 1 902 3 is_stmt 1 view .LVU1111 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3616 .loc 1 902 10 is_stmt 0 view .LVU1112 + 3617 000a 90F83530 ldrb r3, [r0, #53] @ zero_extendqisi2 + 3618 000e DBB2 uxtb r3, r3 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3619 .loc 1 902 5 view .LVU1113 + 3620 0010 022B cmp r3, #2 + 3621 0012 03D0 beq .L183 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 3622 .loc 1 904 5 is_stmt 1 view .LVU1114 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 3623 .loc 1 904 21 is_stmt 0 view .LVU1115 + 3624 0014 8023 movs r3, #128 + 3625 0016 4365 str r3, [r0, #84] + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3626 .loc 1 905 5 is_stmt 1 view .LVU1116 + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3627 .loc 1 905 12 is_stmt 0 view .LVU1117 + 3628 0018 0120 movs r0, #1 + 3629 .LVL150: + 3630 .L182: + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3631 .loc 1 963 1 view .LVU1118 + 3632 001a 08BD pop {r3, pc} + 3633 .LVL151: + 3634 .L183: + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3635 .loc 1 909 5 is_stmt 1 view .LVU1119 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3636 .loc 1 909 8 is_stmt 0 view .LVU1120 + 3637 001c 0368 ldr r3, [r0] + 3638 001e 9048 ldr r0, .L200 + 3639 .LVL152: + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3640 .loc 1 909 8 view .LVU1121 + 3641 0020 9049 ldr r1, .L200+4 + 3642 0022 8B42 cmp r3, r1 + 3643 0024 18BF it ne + 3644 0026 8342 cmpne r3, r0 + 3645 0028 0CBF ite eq + 3646 002a 0121 moveq r1, #1 + 3647 002c 0021 movne r1, #0 + 3648 002e 66D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3649 .loc 1 909 8 discriminator 2 view .LVU1122 + 3650 0030 3030 adds r0, r0, #48 + 3651 0032 8342 cmp r3, r0 + 3652 0034 63D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3653 .loc 1 909 8 discriminator 4 view .LVU1123 + 3654 0036 1830 adds r0, r0, #24 + 3655 0038 8342 cmp r3, r0 + 3656 003a 60D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 117 + + + 3657 .loc 1 909 8 discriminator 6 view .LVU1124 + 3658 003c 1830 adds r0, r0, #24 + 3659 003e 8342 cmp r3, r0 + 3660 0040 5DD0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3661 .loc 1 909 8 discriminator 8 view .LVU1125 + 3662 0042 1830 adds r0, r0, #24 + 3663 0044 8342 cmp r3, r0 + 3664 0046 5AD0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3665 .loc 1 909 8 discriminator 10 view .LVU1126 + 3666 0048 1830 adds r0, r0, #24 + 3667 004a 8342 cmp r3, r0 + 3668 004c 57D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3669 .loc 1 909 8 discriminator 12 view .LVU1127 + 3670 004e 1830 adds r0, r0, #24 + 3671 0050 8342 cmp r3, r0 + 3672 0052 54D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3673 .loc 1 909 8 discriminator 14 view .LVU1128 + 3674 0054 00F55670 add r0, r0, #856 + 3675 0058 8342 cmp r3, r0 + 3676 005a 50D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3677 .loc 1 909 8 discriminator 16 view .LVU1129 + 3678 005c 1830 adds r0, r0, #24 + 3679 005e 8342 cmp r3, r0 + 3680 0060 4DD0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3681 .loc 1 909 8 discriminator 18 view .LVU1130 + 3682 0062 1830 adds r0, r0, #24 + 3683 0064 8342 cmp r3, r0 + 3684 0066 4AD0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3685 .loc 1 909 8 discriminator 20 view .LVU1131 + 3686 0068 1830 adds r0, r0, #24 + 3687 006a 8342 cmp r3, r0 + 3688 006c 47D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3689 .loc 1 909 8 discriminator 22 view .LVU1132 + 3690 006e 1830 adds r0, r0, #24 + 3691 0070 8342 cmp r3, r0 + 3692 0072 44D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3693 .loc 1 909 8 discriminator 24 view .LVU1133 + 3694 0074 1830 adds r0, r0, #24 + 3695 0076 8342 cmp r3, r0 + 3696 0078 41D0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3697 .loc 1 909 8 discriminator 26 view .LVU1134 + 3698 007a 1830 adds r0, r0, #24 + 3699 007c 8342 cmp r3, r0 + 3700 007e 3ED0 beq .L184 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3701 .loc 1 909 8 discriminator 28 view .LVU1135 + 3702 0080 1830 adds r0, r0, #24 + ARM GAS /tmp/ccXv4DVv.s page 118 + + + 3703 0082 8342 cmp r3, r0 + 3704 0084 3BD0 beq .L184 + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3705 .loc 1 920 7 is_stmt 1 view .LVU1136 + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3706 .loc 1 920 56 is_stmt 0 view .LVU1137 + 3707 0086 1968 ldr r1, [r3] + 3708 0088 21F00E01 bic r1, r1, #14 + 3709 008c 1960 str r1, [r3] + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3710 .loc 1 923 7 is_stmt 1 view .LVU1138 + 3711 008e 1368 ldr r3, [r2] + 3712 0090 A0F59560 sub r0, r0, #1192 + 3713 0094 7349 ldr r1, .L200+4 + 3714 0096 8B42 cmp r3, r1 + 3715 0098 18BF it ne + 3716 009a 8342 cmpne r3, r0 + 3717 009c 6AD0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3718 .loc 1 923 7 is_stmt 0 discriminator 2 view .LVU1139 + 3719 009e 7249 ldr r1, .L200+8 + 3720 00a0 8B42 cmp r3, r1 + 3721 00a2 67D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3722 .loc 1 923 7 discriminator 4 view .LVU1140 + 3723 00a4 1831 adds r1, r1, #24 + 3724 00a6 8B42 cmp r3, r1 + 3725 00a8 64D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3726 .loc 1 923 7 discriminator 6 view .LVU1141 + 3727 00aa 1831 adds r1, r1, #24 + 3728 00ac 8B42 cmp r3, r1 + 3729 00ae 61D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3730 .loc 1 923 7 discriminator 8 view .LVU1142 + 3731 00b0 1831 adds r1, r1, #24 + 3732 00b2 8B42 cmp r3, r1 + 3733 00b4 5ED0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3734 .loc 1 923 7 discriminator 10 view .LVU1143 + 3735 00b6 1831 adds r1, r1, #24 + 3736 00b8 8B42 cmp r3, r1 + 3737 00ba 5BD0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3738 .loc 1 923 7 discriminator 12 view .LVU1144 + 3739 00bc 1831 adds r1, r1, #24 + 3740 00be 8B42 cmp r3, r1 + 3741 00c0 58D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3742 .loc 1 923 7 discriminator 14 view .LVU1145 + 3743 00c2 01F55671 add r1, r1, #856 + 3744 00c6 8B42 cmp r3, r1 + 3745 00c8 54D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3746 .loc 1 923 7 discriminator 16 view .LVU1146 + 3747 00ca 1831 adds r1, r1, #24 + 3748 00cc 8B42 cmp r3, r1 + ARM GAS /tmp/ccXv4DVv.s page 119 + + + 3749 00ce 51D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3750 .loc 1 923 7 discriminator 18 view .LVU1147 + 3751 00d0 1831 adds r1, r1, #24 + 3752 00d2 8B42 cmp r3, r1 + 3753 00d4 4ED0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3754 .loc 1 923 7 discriminator 20 view .LVU1148 + 3755 00d6 1831 adds r1, r1, #24 + 3756 00d8 8B42 cmp r3, r1 + 3757 00da 4BD0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3758 .loc 1 923 7 discriminator 22 view .LVU1149 + 3759 00dc 1831 adds r1, r1, #24 + 3760 00de 8B42 cmp r3, r1 + 3761 00e0 48D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3762 .loc 1 923 7 discriminator 24 view .LVU1150 + 3763 00e2 1831 adds r1, r1, #24 + 3764 00e4 8B42 cmp r3, r1 + 3765 00e6 45D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3766 .loc 1 923 7 discriminator 26 view .LVU1151 + 3767 00e8 1831 adds r1, r1, #24 + 3768 00ea 8B42 cmp r3, r1 + 3769 00ec 42D0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3770 .loc 1 923 7 discriminator 28 view .LVU1152 + 3771 00ee 1831 adds r1, r1, #24 + 3772 00f0 8B42 cmp r3, r1 + 3773 00f2 3FD0 beq .L185 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3774 .loc 1 923 7 discriminator 30 view .LVU1153 + 3775 00f4 1968 ldr r1, [r3] + 3776 00f6 21F00101 bic r1, r1, #1 + 3777 00fa 1960 str r1, [r3] + 3778 00fc 3EE0 b .L190 + 3779 .L184: + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3780 .loc 1 912 7 is_stmt 1 view .LVU1154 + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3781 .loc 1 912 19 is_stmt 0 view .LVU1155 + 3782 00fe 0420 movs r0, #4 + 3783 0100 82F83500 strb r0, [r2, #53] + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3784 .loc 1 915 7 is_stmt 1 view .LVU1156 + 3785 0104 81BB cbnz r1, .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3786 .loc 1 915 7 is_stmt 0 discriminator 2 view .LVU1157 + 3787 0106 584A ldr r2, .L200+8 + 3788 .LVL153: + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3789 .loc 1 915 7 discriminator 2 view .LVU1158 + 3790 0108 9342 cmp r3, r2 + 3791 010a 2DD0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3792 .loc 1 915 7 discriminator 4 view .LVU1159 + ARM GAS /tmp/ccXv4DVv.s page 120 + + + 3793 010c 1832 adds r2, r2, #24 + 3794 010e 9342 cmp r3, r2 + 3795 0110 2AD0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3796 .loc 1 915 7 discriminator 6 view .LVU1160 + 3797 0112 1832 adds r2, r2, #24 + 3798 0114 9342 cmp r3, r2 + 3799 0116 27D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3800 .loc 1 915 7 discriminator 8 view .LVU1161 + 3801 0118 1832 adds r2, r2, #24 + 3802 011a 9342 cmp r3, r2 + 3803 011c 24D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3804 .loc 1 915 7 discriminator 10 view .LVU1162 + 3805 011e 1832 adds r2, r2, #24 + 3806 0120 9342 cmp r3, r2 + 3807 0122 21D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3808 .loc 1 915 7 discriminator 12 view .LVU1163 + 3809 0124 1832 adds r2, r2, #24 + 3810 0126 9342 cmp r3, r2 + 3811 0128 1ED0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3812 .loc 1 915 7 discriminator 14 view .LVU1164 + 3813 012a 02F55672 add r2, r2, #856 + 3814 012e 9342 cmp r3, r2 + 3815 0130 1AD0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3816 .loc 1 915 7 discriminator 16 view .LVU1165 + 3817 0132 1832 adds r2, r2, #24 + 3818 0134 9342 cmp r3, r2 + 3819 0136 17D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3820 .loc 1 915 7 discriminator 18 view .LVU1166 + 3821 0138 1832 adds r2, r2, #24 + 3822 013a 9342 cmp r3, r2 + 3823 013c 14D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3824 .loc 1 915 7 discriminator 20 view .LVU1167 + 3825 013e 1832 adds r2, r2, #24 + 3826 0140 9342 cmp r3, r2 + 3827 0142 11D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3828 .loc 1 915 7 discriminator 22 view .LVU1168 + 3829 0144 1832 adds r2, r2, #24 + 3830 0146 9342 cmp r3, r2 + 3831 0148 0ED0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3832 .loc 1 915 7 discriminator 24 view .LVU1169 + 3833 014a 1832 adds r2, r2, #24 + 3834 014c 9342 cmp r3, r2 + 3835 014e 0BD0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3836 .loc 1 915 7 discriminator 26 view .LVU1170 + 3837 0150 1832 adds r2, r2, #24 + 3838 0152 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 121 + + + 3839 0154 08D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3840 .loc 1 915 7 discriminator 28 view .LVU1171 + 3841 0156 1832 adds r2, r2, #24 + 3842 0158 9342 cmp r3, r2 + 3843 015a 05D0 beq .L187 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3844 .loc 1 915 7 discriminator 30 view .LVU1172 + 3845 015c 1A68 ldr r2, [r3] + 3846 015e 22F00102 bic r2, r2, #1 + 3847 0162 1A60 str r2, [r3] + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3848 .loc 1 962 10 discriminator 30 view .LVU1173 + 3849 0164 0020 movs r0, #0 + 3850 0166 58E7 b .L182 + 3851 .L187: + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3852 .loc 1 915 7 discriminator 29 view .LVU1174 + 3853 0168 1A68 ldr r2, [r3] + 3854 016a 22F00102 bic r2, r2, #1 + 3855 016e 1A60 str r2, [r3] + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3856 .loc 1 962 10 discriminator 29 view .LVU1175 + 3857 0170 0020 movs r0, #0 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 3858 .loc 1 915 7 discriminator 29 view .LVU1176 + 3859 0172 52E7 b .L182 + 3860 .LVL154: + 3861 .L185: + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3862 .loc 1 923 7 discriminator 29 view .LVU1177 + 3863 0174 1968 ldr r1, [r3] + 3864 0176 21F00101 bic r1, r1, #1 + 3865 017a 1960 str r1, [r3] + 3866 .L190: + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3867 .loc 1 925 7 is_stmt 1 view .LVU1178 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3868 .loc 1 925 10 is_stmt 0 view .LVU1179 + 3869 017c 1368 ldr r3, [r2] + 3870 017e 3848 ldr r0, .L200 + 3871 0180 3849 ldr r1, .L200+4 + 3872 0182 8B42 cmp r3, r1 + 3873 0184 18BF it ne + 3874 0186 8342 cmpne r3, r0 + 3875 0188 42D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3876 .loc 1 925 10 discriminator 2 view .LVU1180 + 3877 018a 1831 adds r1, r1, #24 + 3878 018c 8B42 cmp r3, r1 + 3879 018e 3FD0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3880 .loc 1 925 10 discriminator 4 view .LVU1181 + 3881 0190 1831 adds r1, r1, #24 + 3882 0192 8B42 cmp r3, r1 + 3883 0194 3CD0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 122 + + + 3884 .loc 1 925 10 discriminator 6 view .LVU1182 + 3885 0196 1831 adds r1, r1, #24 + 3886 0198 8B42 cmp r3, r1 + 3887 019a 39D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3888 .loc 1 925 10 discriminator 8 view .LVU1183 + 3889 019c 1831 adds r1, r1, #24 + 3890 019e 8B42 cmp r3, r1 + 3891 01a0 36D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3892 .loc 1 925 10 discriminator 10 view .LVU1184 + 3893 01a2 1831 adds r1, r1, #24 + 3894 01a4 8B42 cmp r3, r1 + 3895 01a6 33D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3896 .loc 1 925 10 discriminator 12 view .LVU1185 + 3897 01a8 1831 adds r1, r1, #24 + 3898 01aa 8B42 cmp r3, r1 + 3899 01ac 30D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3900 .loc 1 925 10 discriminator 14 view .LVU1186 + 3901 01ae 01F55671 add r1, r1, #856 + 3902 01b2 8B42 cmp r3, r1 + 3903 01b4 2CD0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3904 .loc 1 925 10 discriminator 16 view .LVU1187 + 3905 01b6 1831 adds r1, r1, #24 + 3906 01b8 8B42 cmp r3, r1 + 3907 01ba 29D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3908 .loc 1 925 10 discriminator 18 view .LVU1188 + 3909 01bc 1831 adds r1, r1, #24 + 3910 01be 8B42 cmp r3, r1 + 3911 01c0 26D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3912 .loc 1 925 10 discriminator 20 view .LVU1189 + 3913 01c2 1831 adds r1, r1, #24 + 3914 01c4 8B42 cmp r3, r1 + 3915 01c6 23D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3916 .loc 1 925 10 discriminator 22 view .LVU1190 + 3917 01c8 1831 adds r1, r1, #24 + 3918 01ca 8B42 cmp r3, r1 + 3919 01cc 20D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3920 .loc 1 925 10 discriminator 24 view .LVU1191 + 3921 01ce 1831 adds r1, r1, #24 + 3922 01d0 8B42 cmp r3, r1 + 3923 01d2 1DD0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3924 .loc 1 925 10 discriminator 26 view .LVU1192 + 3925 01d4 1831 adds r1, r1, #24 + 3926 01d6 8B42 cmp r3, r1 + 3927 01d8 1AD0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3928 .loc 1 925 10 discriminator 28 view .LVU1193 + 3929 01da 1831 adds r1, r1, #24 + ARM GAS /tmp/ccXv4DVv.s page 123 + + + 3930 01dc 8B42 cmp r3, r1 + 3931 01de 17D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3932 .loc 1 925 10 discriminator 30 view .LVU1194 + 3933 01e0 2249 ldr r1, .L200+12 + 3934 01e2 8B42 cmp r3, r1 + 3935 01e4 14D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3936 .loc 1 925 10 discriminator 32 view .LVU1195 + 3937 01e6 1431 adds r1, r1, #20 + 3938 01e8 8B42 cmp r3, r1 + 3939 01ea 11D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3940 .loc 1 925 10 discriminator 34 view .LVU1196 + 3941 01ec 1431 adds r1, r1, #20 + 3942 01ee 8B42 cmp r3, r1 + 3943 01f0 0ED0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3944 .loc 1 925 10 discriminator 36 view .LVU1197 + 3945 01f2 1431 adds r1, r1, #20 + 3946 01f4 8B42 cmp r3, r1 + 3947 01f6 0BD0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3948 .loc 1 925 10 discriminator 38 view .LVU1198 + 3949 01f8 1431 adds r1, r1, #20 + 3950 01fa 8B42 cmp r3, r1 + 3951 01fc 08D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3952 .loc 1 925 10 discriminator 40 view .LVU1199 + 3953 01fe 1431 adds r1, r1, #20 + 3954 0200 8B42 cmp r3, r1 + 3955 0202 05D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3956 .loc 1 925 10 discriminator 42 view .LVU1200 + 3957 0204 1431 adds r1, r1, #20 + 3958 0206 8B42 cmp r3, r1 + 3959 0208 02D0 beq .L191 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3960 .loc 1 925 10 discriminator 44 view .LVU1201 + 3961 020a 1431 adds r1, r1, #20 + 3962 020c 8B42 cmp r3, r1 + 3963 020e 17D1 bne .L192 + 3964 .L191: + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3965 .loc 1 928 9 is_stmt 1 view .LVU1202 + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3966 .loc 1 928 13 is_stmt 0 view .LVU1203 + 3967 0210 116E ldr r1, [r2, #96] + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3968 .loc 1 928 34 view .LVU1204 + 3969 0212 0B68 ldr r3, [r1] + 3970 0214 23F48073 bic r3, r3, #256 + 3971 0218 0B60 str r3, [r1] + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 3972 .loc 1 931 9 is_stmt 1 view .LVU1205 + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + 3973 .loc 1 931 48 is_stmt 0 view .LVU1206 + ARM GAS /tmp/ccXv4DVv.s page 124 + + + 3974 021a 906D ldr r0, [r2, #88] + 3975 .LVL155: + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3976 .loc 1 932 9 is_stmt 1 view .LVU1207 + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3977 .loc 1 932 54 is_stmt 0 view .LVU1208 + 3978 021c D36D ldr r3, [r2, #92] + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3979 .loc 1 932 68 view .LVU1209 + 3980 021e 03F01F01 and r1, r3, #31 + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3981 .loc 1 932 46 view .LVU1210 + 3982 0222 0123 movs r3, #1 + 3983 0224 8B40 lsls r3, r3, r1 + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3984 .loc 1 932 25 view .LVU1211 + 3985 0226 4360 str r3, [r0, #4] + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3986 .loc 1 935 9 is_stmt 1 view .LVU1212 + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3987 .loc 1 935 13 is_stmt 0 view .LVU1213 + 3988 0228 536E ldr r3, [r2, #100] + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3989 .loc 1 935 46 view .LVU1214 + 3990 022a 916E ldr r1, [r2, #104] + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3991 .loc 1 935 40 view .LVU1215 + 3992 022c 5960 str r1, [r3, #4] + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3993 .loc 1 937 9 is_stmt 1 view .LVU1216 + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3994 .loc 1 937 16 is_stmt 0 view .LVU1217 + 3995 022e D36E ldr r3, [r2, #108] + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 3996 .loc 1 937 11 view .LVU1218 + 3997 0230 33B1 cbz r3, .L192 + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3998 .loc 1 941 11 is_stmt 1 view .LVU1219 + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 3999 .loc 1 941 40 is_stmt 0 view .LVU1220 + 4000 0232 1968 ldr r1, [r3] + 4001 0234 21F48071 bic r1, r1, #256 + 4002 0238 1960 str r1, [r3] + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4003 .loc 1 944 11 is_stmt 1 view .LVU1221 + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4004 .loc 1 944 15 is_stmt 0 view .LVU1222 + 4005 023a 136F ldr r3, [r2, #112] + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4006 .loc 1 944 53 view .LVU1223 + 4007 023c 516F ldr r1, [r2, #116] + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4008 .loc 1 944 47 view .LVU1224 + 4009 023e 5960 str r1, [r3, #4] + 4010 .LVL156: + 4011 .L192: + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 125 + + + 4012 .loc 1 949 7 is_stmt 1 view .LVU1225 + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4013 .loc 1 949 7 view .LVU1226 + 4014 0240 0023 movs r3, #0 + 4015 0242 82F83430 strb r3, [r2, #52] + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4016 .loc 1 949 7 view .LVU1227 + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4017 .loc 1 952 7 view .LVU1228 + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4018 .loc 1 952 19 is_stmt 0 view .LVU1229 + 4019 0246 0123 movs r3, #1 + 4020 0248 82F83530 strb r3, [r2, #53] + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4021 .loc 1 955 7 is_stmt 1 view .LVU1230 + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4022 .loc 1 955 14 is_stmt 0 view .LVU1231 + 4023 024c 136D ldr r3, [r2, #80] + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4024 .loc 1 955 9 view .LVU1232 + 4025 024e 2BB1 cbz r3, .L194 + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4026 .loc 1 957 9 is_stmt 1 view .LVU1233 + 4027 0250 1046 mov r0, r2 + 4028 0252 9847 blx r3 + 4029 .LVL157: + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4030 .loc 1 962 10 is_stmt 0 view .LVU1234 + 4031 0254 0020 movs r0, #0 + 4032 0256 E0E6 b .L182 + 4033 .LVL158: + 4034 .L193: + 4035 .LCFI19: + 4036 .cfi_def_cfa_offset 0 + 4037 .cfi_restore 3 + 4038 .cfi_restore 14 + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4039 .loc 1 899 12 view .LVU1235 + 4040 0258 0120 movs r0, #1 + 4041 .LVL159: + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4042 .loc 1 963 1 view .LVU1236 + 4043 025a 7047 bx lr + 4044 .LVL160: + 4045 .L194: + 4046 .LCFI20: + 4047 .cfi_def_cfa_offset 8 + 4048 .cfi_offset 3, -8 + 4049 .cfi_offset 14, -4 + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4050 .loc 1 962 10 view .LVU1237 + 4051 025c 0020 movs r0, #0 + 4052 025e DCE6 b .L182 + 4053 .L201: + 4054 .align 2 + 4055 .L200: + 4056 0260 10000240 .word 1073872912 + ARM GAS /tmp/ccXv4DVv.s page 126 + + + 4057 0264 28000240 .word 1073872936 + 4058 0268 40000240 .word 1073872960 + 4059 026c 08540258 .word 1476547592 + 4060 .cfi_endproc + 4061 .LFE146: + 4063 .section .text.HAL_DMA_PollForTransfer,"ax",%progbits + 4064 .align 1 + 4065 .global HAL_DMA_PollForTransfer + 4066 .syntax unified + 4067 .thumb + 4068 .thumb_func + 4069 .fpu fpv5-d16 + 4071 HAL_DMA_PollForTransfer: + 4072 .LVL161: + 4073 .LFB147: + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 4074 .loc 1 977 1 is_stmt 1 view -0 + 4075 .cfi_startproc + 4076 @ args = 0, pretend = 0, frame = 0 + 4077 @ frame_needed = 0, uses_anonymous_args = 0 + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 4078 .loc 1 977 1 is_stmt 0 view .LVU1239 + 4079 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 4080 .LCFI21: + 4081 .cfi_def_cfa_offset 32 + 4082 .cfi_offset 4, -32 + 4083 .cfi_offset 5, -28 + 4084 .cfi_offset 6, -24 + 4085 .cfi_offset 7, -20 + 4086 .cfi_offset 8, -16 + 4087 .cfi_offset 9, -12 + 4088 .cfi_offset 10, -8 + 4089 .cfi_offset 14, -4 + 4090 0004 0446 mov r4, r0 + 4091 0006 0F46 mov r7, r1 + 4092 0008 1646 mov r6, r2 + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t cpltlevel_mask; + 4093 .loc 1 978 3 is_stmt 1 view .LVU1240 + 4094 .LVL162: + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 4095 .loc 1 979 3 view .LVU1241 + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4096 .loc 1 980 3 view .LVU1242 + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4097 .loc 1 980 24 is_stmt 0 view .LVU1243 + 4098 000a FFF7FEFF bl HAL_GetTick + 4099 .LVL163: + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* IT clear flag register */ + 4100 .loc 1 983 3 is_stmt 1 view .LVU1244 + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4101 .loc 1 985 3 view .LVU1245 + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4102 .loc 1 988 3 view .LVU1246 + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4103 .loc 1 988 5 is_stmt 0 view .LVU1247 + 4104 000e 002C cmp r4, #0 + 4105 0010 00F01882 beq .L230 + ARM GAS /tmp/ccXv4DVv.s page 127 + + + 4106 0014 8246 mov r10, r0 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4107 .loc 1 993 3 is_stmt 1 view .LVU1248 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4108 .loc 1 993 32 is_stmt 0 view .LVU1249 + 4109 0016 94F83530 ldrb r3, [r4, #53] @ zero_extendqisi2 + 4110 001a DBB2 uxtb r3, r3 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4111 .loc 1 993 5 view .LVU1250 + 4112 001c 022B cmp r3, #2 + 4113 001e 07D0 beq .L204 + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 4114 .loc 1 996 5 is_stmt 1 view .LVU1251 + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 4115 .loc 1 996 21 is_stmt 0 view .LVU1252 + 4116 0020 8023 movs r3, #128 + 4117 0022 6365 str r3, [r4, #84] + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4118 .loc 1 997 5 is_stmt 1 view .LVU1253 + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4119 .loc 1 997 5 view .LVU1254 + 4120 0024 0023 movs r3, #0 + 4121 0026 84F83430 strb r3, [r4, #52] + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4122 .loc 1 997 5 view .LVU1255 + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4123 .loc 1 999 5 view .LVU1256 + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4124 .loc 1 999 12 is_stmt 0 view .LVU1257 + 4125 002a 0120 movs r0, #1 + 4126 .LVL164: + 4127 .L203: +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4128 .loc 1 1195 1 view .LVU1258 + 4129 002c BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 4130 .LVL165: + 4131 .L204: +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4132 .loc 1 1002 3 is_stmt 1 view .LVU1259 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4133 .loc 1 1002 6 is_stmt 0 view .LVU1260 + 4134 0030 2368 ldr r3, [r4] + 4135 0032 3649 ldr r1, .L238 + 4136 0034 364A ldr r2, .L238+4 + 4137 0036 9342 cmp r3, r2 + 4138 0038 18BF it ne + 4139 003a 8B42 cmpne r3, r1 + 4140 003c 3BD0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4141 .loc 1 1002 6 discriminator 2 view .LVU1261 + 4142 003e 1832 adds r2, r2, #24 + 4143 0040 9342 cmp r3, r2 + 4144 0042 38D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4145 .loc 1 1002 6 discriminator 4 view .LVU1262 + 4146 0044 1832 adds r2, r2, #24 + 4147 0046 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 128 + + + 4148 0048 35D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4149 .loc 1 1002 6 discriminator 6 view .LVU1263 + 4150 004a 1832 adds r2, r2, #24 + 4151 004c 9342 cmp r3, r2 + 4152 004e 32D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4153 .loc 1 1002 6 discriminator 8 view .LVU1264 + 4154 0050 1832 adds r2, r2, #24 + 4155 0052 9342 cmp r3, r2 + 4156 0054 2FD0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4157 .loc 1 1002 6 discriminator 10 view .LVU1265 + 4158 0056 1832 adds r2, r2, #24 + 4159 0058 9342 cmp r3, r2 + 4160 005a 2CD0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4161 .loc 1 1002 6 discriminator 12 view .LVU1266 + 4162 005c 1832 adds r2, r2, #24 + 4163 005e 9342 cmp r3, r2 + 4164 0060 29D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4165 .loc 1 1002 6 discriminator 14 view .LVU1267 + 4166 0062 02F55672 add r2, r2, #856 + 4167 0066 9342 cmp r3, r2 + 4168 0068 25D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4169 .loc 1 1002 6 discriminator 16 view .LVU1268 + 4170 006a 1832 adds r2, r2, #24 + 4171 006c 9342 cmp r3, r2 + 4172 006e 22D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4173 .loc 1 1002 6 discriminator 18 view .LVU1269 + 4174 0070 1832 adds r2, r2, #24 + 4175 0072 9342 cmp r3, r2 + 4176 0074 1FD0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4177 .loc 1 1002 6 discriminator 20 view .LVU1270 + 4178 0076 1832 adds r2, r2, #24 + 4179 0078 9342 cmp r3, r2 + 4180 007a 1CD0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4181 .loc 1 1002 6 discriminator 22 view .LVU1271 + 4182 007c 1832 adds r2, r2, #24 + 4183 007e 9342 cmp r3, r2 + 4184 0080 19D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4185 .loc 1 1002 6 discriminator 24 view .LVU1272 + 4186 0082 1832 adds r2, r2, #24 + 4187 0084 9342 cmp r3, r2 + 4188 0086 16D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4189 .loc 1 1002 6 discriminator 26 view .LVU1273 + 4190 0088 1832 adds r2, r2, #24 + 4191 008a 9342 cmp r3, r2 + 4192 008c 13D0 beq .L205 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 129 + + + 4193 .loc 1 1002 6 discriminator 28 view .LVU1274 + 4194 008e 1832 adds r2, r2, #24 + 4195 0090 9342 cmp r3, r2 + 4196 0092 10D0 beq .L205 +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4197 .loc 1 1029 5 is_stmt 1 view .LVU1275 +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4198 .loc 1 1029 52 is_stmt 0 view .LVU1276 + 4199 0094 1B68 ldr r3, [r3] +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4200 .loc 1 1029 8 view .LVU1277 + 4201 0096 13F0200F tst r3, #32 + 4202 009a 2AD1 bne .L233 +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4203 .loc 1 1036 5 is_stmt 1 view .LVU1278 +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4204 .loc 1 1036 7 is_stmt 0 view .LVU1279 + 4205 009c 77BB cbnz r7, .L212 +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4206 .loc 1 1039 7 is_stmt 1 view .LVU1280 +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4207 .loc 1 1039 46 is_stmt 0 view .LVU1281 + 4208 009e E36D ldr r3, [r4, #92] +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4209 .loc 1 1039 60 view .LVU1282 + 4210 00a0 03F01F03 and r3, r3, #31 +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4211 .loc 1 1039 22 view .LVU1283 + 4212 00a4 4FF00209 mov r9, #2 + 4213 00a8 09FA03F9 lsl r9, r9, r3 + 4214 .LVL166: + 4215 .L213: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + 4216 .loc 1 1047 5 is_stmt 1 view .LVU1284 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + 4217 .loc 1 1047 46 is_stmt 0 view .LVU1285 + 4218 00ac A36D ldr r3, [r4, #88] +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + 4219 .loc 1 1047 14 view .LVU1286 + 4220 00ae 1D46 mov r5, r3 + 4221 .LVL167: +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4222 .loc 1 1048 5 is_stmt 1 view .LVU1287 +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4223 .loc 1 1048 14 is_stmt 0 view .LVU1288 + 4224 00b0 03F10408 add r8, r3, #4 + 4225 .LVL168: +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4226 .loc 1 1048 14 view .LVU1289 + 4227 00b4 BAE0 b .L214 + 4228 .LVL169: + 4229 .L205: +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4230 .loc 1 1005 5 is_stmt 1 view .LVU1290 +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4231 .loc 1 1005 50 is_stmt 0 view .LVU1291 + 4232 00b6 1B68 ldr r3, [r3] + ARM GAS /tmp/ccXv4DVv.s page 130 + + +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4233 .loc 1 1005 8 view .LVU1292 + 4234 00b8 13F4807F tst r3, #256 + 4235 00bc 0CD1 bne .L234 +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4236 .loc 1 1012 5 is_stmt 1 view .LVU1293 +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4237 .loc 1 1012 7 is_stmt 0 view .LVU1294 + 4238 00be 87B9 cbnz r7, .L209 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4239 .loc 1 1015 7 is_stmt 1 view .LVU1295 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4240 .loc 1 1015 49 is_stmt 0 view .LVU1296 + 4241 00c0 E36D ldr r3, [r4, #92] +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4242 .loc 1 1015 63 view .LVU1297 + 4243 00c2 03F01F03 and r3, r3, #31 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4244 .loc 1 1015 22 view .LVU1298 + 4245 00c6 4FF02009 mov r9, #32 + 4246 00ca 09FA03F9 lsl r9, r9, r3 + 4247 .LVL170: + 4248 .L210: +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + 4249 .loc 1 1023 5 is_stmt 1 view .LVU1299 +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + 4250 .loc 1 1023 45 is_stmt 0 view .LVU1300 + 4251 00ce A36D ldr r3, [r4, #88] +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + 4252 .loc 1 1023 14 view .LVU1301 + 4253 00d0 1D46 mov r5, r3 + 4254 .LVL171: +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4255 .loc 1 1024 5 is_stmt 1 view .LVU1302 +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4256 .loc 1 1024 14 is_stmt 0 view .LVU1303 + 4257 00d2 03F10808 add r8, r3, #8 + 4258 .LVL172: +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4259 .loc 1 1024 14 view .LVU1304 + 4260 00d6 A9E0 b .L214 + 4261 .LVL173: + 4262 .L234: +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 4263 .loc 1 1007 7 is_stmt 1 view .LVU1305 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 4264 .loc 1 1007 23 is_stmt 0 view .LVU1306 + 4265 00d8 4FF48073 mov r3, #256 + 4266 00dc 6365 str r3, [r4, #84] +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4267 .loc 1 1008 7 is_stmt 1 view .LVU1307 +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4268 .loc 1 1008 14 is_stmt 0 view .LVU1308 + 4269 00de 0120 movs r0, #1 + 4270 .LVL174: +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4271 .loc 1 1008 14 view .LVU1309 + ARM GAS /tmp/ccXv4DVv.s page 131 + + + 4272 00e0 A4E7 b .L203 + 4273 .LVL175: + 4274 .L209: +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4275 .loc 1 1020 7 is_stmt 1 view .LVU1310 +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4276 .loc 1 1020 49 is_stmt 0 view .LVU1311 + 4277 00e2 E36D ldr r3, [r4, #92] +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4278 .loc 1 1020 63 view .LVU1312 + 4279 00e4 03F01F03 and r3, r3, #31 +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4280 .loc 1 1020 22 view .LVU1313 + 4281 00e8 4FF01009 mov r9, #16 + 4282 00ec 09FA03F9 lsl r9, r9, r3 + 4283 .LVL176: +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4284 .loc 1 1020 22 view .LVU1314 + 4285 00f0 EDE7 b .L210 + 4286 .LVL177: + 4287 .L233: +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 4288 .loc 1 1031 7 is_stmt 1 view .LVU1315 +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return HAL_ERROR; + 4289 .loc 1 1031 23 is_stmt 0 view .LVU1316 + 4290 00f2 4FF48073 mov r3, #256 + 4291 00f6 6365 str r3, [r4, #84] +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4292 .loc 1 1032 7 is_stmt 1 view .LVU1317 +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4293 .loc 1 1032 14 is_stmt 0 view .LVU1318 + 4294 00f8 0120 movs r0, #1 + 4295 .LVL178: +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4296 .loc 1 1032 14 view .LVU1319 + 4297 00fa 97E7 b .L203 + 4298 .LVL179: + 4299 .L212: +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4300 .loc 1 1044 7 is_stmt 1 view .LVU1320 +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4301 .loc 1 1044 46 is_stmt 0 view .LVU1321 + 4302 00fc E36D ldr r3, [r4, #92] +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4303 .loc 1 1044 60 view .LVU1322 + 4304 00fe 03F01F03 and r3, r3, #31 +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4305 .loc 1 1044 22 view .LVU1323 + 4306 0102 4FF00409 mov r9, #4 + 4307 0106 09FA03F9 lsl r9, r9, r3 + 4308 .LVL180: +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4309 .loc 1 1044 22 view .LVU1324 + 4310 010a CFE7 b .L213 + 4311 .L239: + 4312 .align 2 + 4313 .L238: + ARM GAS /tmp/ccXv4DVv.s page 132 + + + 4314 010c 10000240 .word 1073872912 + 4315 0110 28000240 .word 1073872936 + 4316 .LVL181: + 4317 .L215: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4318 .loc 1 1055 7 is_stmt 1 view .LVU1325 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4319 .loc 1 1055 12 is_stmt 0 view .LVU1326 + 4320 0114 2A68 ldr r2, [r5] +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4321 .loc 1 1055 50 view .LVU1327 + 4322 0116 E36D ldr r3, [r4, #92] +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4323 .loc 1 1055 64 view .LVU1328 + 4324 0118 03F01F03 and r3, r3, #31 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4325 .loc 1 1055 75 view .LVU1329 + 4326 011c DA40 lsrs r2, r2, r3 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4327 .loc 1 1055 9 view .LVU1330 + 4328 011e 12F0010F tst r2, #1 + 4329 0122 08D0 beq .L218 +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4330 .loc 1 1058 9 is_stmt 1 view .LVU1331 +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4331 .loc 1 1058 25 is_stmt 0 view .LVU1332 + 4332 0124 626D ldr r2, [r4, #84] + 4333 0126 42F00202 orr r2, r2, #2 + 4334 012a 6265 str r2, [r4, #84] +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4335 .loc 1 1061 9 is_stmt 1 view .LVU1333 +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4336 .loc 1 1061 40 is_stmt 0 view .LVU1334 + 4337 012c 0122 movs r2, #1 + 4338 012e 02FA03F3 lsl r3, r2, r3 +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4339 .loc 1 1061 21 view .LVU1335 + 4340 0132 C8F80030 str r3, [r8] + 4341 .L218: +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4342 .loc 1 1064 7 is_stmt 1 view .LVU1336 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4343 .loc 1 1064 12 is_stmt 0 view .LVU1337 + 4344 0136 2968 ldr r1, [r5] +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4345 .loc 1 1064 51 view .LVU1338 + 4346 0138 E36D ldr r3, [r4, #92] +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4347 .loc 1 1064 65 view .LVU1339 + 4348 013a 03F01F02 and r2, r3, #31 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4349 .loc 1 1064 43 view .LVU1340 + 4350 013e 0423 movs r3, #4 + 4351 0140 9340 lsls r3, r3, r2 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4352 .loc 1 1064 9 view .LVU1341 + 4353 0142 1942 tst r1, r3 + ARM GAS /tmp/ccXv4DVv.s page 133 + + + 4354 0144 05D0 beq .L219 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4355 .loc 1 1067 9 is_stmt 1 view .LVU1342 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4356 .loc 1 1067 25 is_stmt 0 view .LVU1343 + 4357 0146 626D ldr r2, [r4, #84] + 4358 0148 42F00402 orr r2, r2, #4 + 4359 014c 6265 str r2, [r4, #84] +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4360 .loc 1 1070 9 is_stmt 1 view .LVU1344 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4361 .loc 1 1070 21 is_stmt 0 view .LVU1345 + 4362 014e C8F80030 str r3, [r8] + 4363 .L219: +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4364 .loc 1 1073 7 is_stmt 1 view .LVU1346 +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4365 .loc 1 1073 12 is_stmt 0 view .LVU1347 + 4366 0152 2968 ldr r1, [r5] +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4367 .loc 1 1073 50 view .LVU1348 + 4368 0154 E36D ldr r3, [r4, #92] +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4369 .loc 1 1073 64 view .LVU1349 + 4370 0156 03F01F02 and r2, r3, #31 +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4371 .loc 1 1073 42 view .LVU1350 + 4372 015a 0823 movs r3, #8 + 4373 015c 9340 lsls r3, r3, r2 +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4374 .loc 1 1073 9 view .LVU1351 + 4375 015e 1942 tst r1, r3 + 4376 0160 40F0BD80 bne .L235 + 4377 .L217: +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4378 .loc 1 1113 5 is_stmt 1 view .LVU1352 +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4379 .loc 1 1113 7 is_stmt 0 view .LVU1353 + 4380 0164 B6F1FF3F cmp r6, #-1 + 4381 0168 40F0C680 bne .L236 + 4382 .L220: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4383 .loc 1 1134 5 is_stmt 1 view .LVU1354 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4384 .loc 1 1134 8 is_stmt 0 view .LVU1355 + 4385 016c 2368 ldr r3, [r4] + 4386 016e 9049 ldr r1, .L240 + 4387 0170 904A ldr r2, .L240+4 + 4388 0172 9342 cmp r3, r2 + 4389 0174 18BF it ne + 4390 0176 8B42 cmpne r3, r1 + 4391 0178 42D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4392 .loc 1 1134 8 discriminator 2 view .LVU1356 + 4393 017a 1832 adds r2, r2, #24 + 4394 017c 9342 cmp r3, r2 + 4395 017e 3FD0 beq .L222 + ARM GAS /tmp/ccXv4DVv.s page 134 + + +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4396 .loc 1 1134 8 discriminator 4 view .LVU1357 + 4397 0180 1832 adds r2, r2, #24 + 4398 0182 9342 cmp r3, r2 + 4399 0184 3CD0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4400 .loc 1 1134 8 discriminator 6 view .LVU1358 + 4401 0186 1832 adds r2, r2, #24 + 4402 0188 9342 cmp r3, r2 + 4403 018a 39D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4404 .loc 1 1134 8 discriminator 8 view .LVU1359 + 4405 018c 1832 adds r2, r2, #24 + 4406 018e 9342 cmp r3, r2 + 4407 0190 36D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4408 .loc 1 1134 8 discriminator 10 view .LVU1360 + 4409 0192 1832 adds r2, r2, #24 + 4410 0194 9342 cmp r3, r2 + 4411 0196 33D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4412 .loc 1 1134 8 discriminator 12 view .LVU1361 + 4413 0198 1832 adds r2, r2, #24 + 4414 019a 9342 cmp r3, r2 + 4415 019c 30D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4416 .loc 1 1134 8 discriminator 14 view .LVU1362 + 4417 019e 02F55672 add r2, r2, #856 + 4418 01a2 9342 cmp r3, r2 + 4419 01a4 2CD0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4420 .loc 1 1134 8 discriminator 16 view .LVU1363 + 4421 01a6 1832 adds r2, r2, #24 + 4422 01a8 9342 cmp r3, r2 + 4423 01aa 29D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4424 .loc 1 1134 8 discriminator 18 view .LVU1364 + 4425 01ac 1832 adds r2, r2, #24 + 4426 01ae 9342 cmp r3, r2 + 4427 01b0 26D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4428 .loc 1 1134 8 discriminator 20 view .LVU1365 + 4429 01b2 1832 adds r2, r2, #24 + 4430 01b4 9342 cmp r3, r2 + 4431 01b6 23D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4432 .loc 1 1134 8 discriminator 22 view .LVU1366 + 4433 01b8 1832 adds r2, r2, #24 + 4434 01ba 9342 cmp r3, r2 + 4435 01bc 20D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4436 .loc 1 1134 8 discriminator 24 view .LVU1367 + 4437 01be 1832 adds r2, r2, #24 + 4438 01c0 9342 cmp r3, r2 + 4439 01c2 1DD0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4440 .loc 1 1134 8 discriminator 26 view .LVU1368 + ARM GAS /tmp/ccXv4DVv.s page 135 + + + 4441 01c4 1832 adds r2, r2, #24 + 4442 01c6 9342 cmp r3, r2 + 4443 01c8 1AD0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4444 .loc 1 1134 8 discriminator 28 view .LVU1369 + 4445 01ca 1832 adds r2, r2, #24 + 4446 01cc 9342 cmp r3, r2 + 4447 01ce 17D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4448 .loc 1 1134 8 discriminator 30 view .LVU1370 + 4449 01d0 794A ldr r2, .L240+8 + 4450 01d2 9342 cmp r3, r2 + 4451 01d4 14D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4452 .loc 1 1134 8 discriminator 32 view .LVU1371 + 4453 01d6 1432 adds r2, r2, #20 + 4454 01d8 9342 cmp r3, r2 + 4455 01da 11D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4456 .loc 1 1134 8 discriminator 34 view .LVU1372 + 4457 01dc 1432 adds r2, r2, #20 + 4458 01de 9342 cmp r3, r2 + 4459 01e0 0ED0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4460 .loc 1 1134 8 discriminator 36 view .LVU1373 + 4461 01e2 1432 adds r2, r2, #20 + 4462 01e4 9342 cmp r3, r2 + 4463 01e6 0BD0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4464 .loc 1 1134 8 discriminator 38 view .LVU1374 + 4465 01e8 1432 adds r2, r2, #20 + 4466 01ea 9342 cmp r3, r2 + 4467 01ec 08D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4468 .loc 1 1134 8 discriminator 40 view .LVU1375 + 4469 01ee 1432 adds r2, r2, #20 + 4470 01f0 9342 cmp r3, r2 + 4471 01f2 05D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4472 .loc 1 1134 8 discriminator 42 view .LVU1376 + 4473 01f4 1432 adds r2, r2, #20 + 4474 01f6 9342 cmp r3, r2 + 4475 01f8 02D0 beq .L222 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4476 .loc 1 1134 8 discriminator 44 view .LVU1377 + 4477 01fa 1432 adds r2, r2, #20 + 4478 01fc 9342 cmp r3, r2 + 4479 01fe 15D1 bne .L214 + 4480 .L222: +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4481 .loc 1 1137 7 is_stmt 1 view .LVU1378 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4482 .loc 1 1137 14 is_stmt 0 view .LVU1379 + 4483 0200 E36E ldr r3, [r4, #108] +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4484 .loc 1 1137 9 view .LVU1380 + 4485 0202 4BB1 cbz r3, .L224 + ARM GAS /tmp/ccXv4DVv.s page 136 + + +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4486 .loc 1 1140 9 is_stmt 1 view .LVU1381 +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4487 .loc 1 1140 17 is_stmt 0 view .LVU1382 + 4488 0204 236F ldr r3, [r4, #112] +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4489 .loc 1 1140 41 view .LVU1383 + 4490 0206 1968 ldr r1, [r3] +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4491 .loc 1 1140 54 view .LVU1384 + 4492 0208 626F ldr r2, [r4, #116] +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4493 .loc 1 1140 11 view .LVU1385 + 4494 020a 1142 tst r1, r2 + 4495 020c 04D0 beq .L224 +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4496 .loc 1 1143 11 is_stmt 1 view .LVU1386 +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4497 .loc 1 1143 47 is_stmt 0 view .LVU1387 + 4498 020e 5A60 str r2, [r3, #4] +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4499 .loc 1 1146 11 is_stmt 1 view .LVU1388 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4500 .loc 1 1146 27 is_stmt 0 view .LVU1389 + 4501 0210 636D ldr r3, [r4, #84] + 4502 0212 43F48063 orr r3, r3, #1024 + 4503 0216 6365 str r3, [r4, #84] + 4504 .L224: +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4505 .loc 1 1151 7 is_stmt 1 view .LVU1390 +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4506 .loc 1 1151 15 is_stmt 0 view .LVU1391 + 4507 0218 636E ldr r3, [r4, #100] +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4508 .loc 1 1151 36 view .LVU1392 + 4509 021a 1968 ldr r1, [r3] +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4510 .loc 1 1151 48 view .LVU1393 + 4511 021c A26E ldr r2, [r4, #104] +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4512 .loc 1 1151 9 view .LVU1394 + 4513 021e 1142 tst r1, r2 + 4514 0220 04D0 beq .L214 +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4515 .loc 1 1154 9 is_stmt 1 view .LVU1395 +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4516 .loc 1 1154 40 is_stmt 0 view .LVU1396 + 4517 0222 5A60 str r2, [r3, #4] +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4518 .loc 1 1157 9 is_stmt 1 view .LVU1397 +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4519 .loc 1 1157 25 is_stmt 0 view .LVU1398 + 4520 0224 636D ldr r3, [r4, #84] + 4521 0226 43F40073 orr r3, r3, #512 + 4522 022a 6365 str r3, [r4, #84] + 4523 .L214: +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 137 + + + 4524 .loc 1 1051 8 is_stmt 1 view .LVU1399 +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4525 .loc 1 1051 11 is_stmt 0 view .LVU1400 + 4526 022c 2B68 ldr r3, [r5] +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4527 .loc 1 1051 8 view .LVU1401 + 4528 022e 13EA090F tst r3, r9 + 4529 0232 71D1 bne .L237 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4530 .loc 1 1053 5 is_stmt 1 view .LVU1402 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4531 .loc 1 1053 8 is_stmt 0 view .LVU1403 + 4532 0234 2368 ldr r3, [r4] + 4533 0236 5E49 ldr r1, .L240 + 4534 0238 5E4A ldr r2, .L240+4 + 4535 023a 9342 cmp r3, r2 + 4536 023c 18BF it ne + 4537 023e 8B42 cmpne r3, r1 + 4538 0240 3FF468AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4539 .loc 1 1053 8 discriminator 2 view .LVU1404 + 4540 0244 1832 adds r2, r2, #24 + 4541 0246 9342 cmp r3, r2 + 4542 0248 3FF464AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4543 .loc 1 1053 8 discriminator 4 view .LVU1405 + 4544 024c 1832 adds r2, r2, #24 + 4545 024e 9342 cmp r3, r2 + 4546 0250 3FF460AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4547 .loc 1 1053 8 discriminator 6 view .LVU1406 + 4548 0254 1832 adds r2, r2, #24 + 4549 0256 9342 cmp r3, r2 + 4550 0258 3FF45CAF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4551 .loc 1 1053 8 discriminator 8 view .LVU1407 + 4552 025c 1832 adds r2, r2, #24 + 4553 025e 9342 cmp r3, r2 + 4554 0260 3FF458AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4555 .loc 1 1053 8 discriminator 10 view .LVU1408 + 4556 0264 1832 adds r2, r2, #24 + 4557 0266 9342 cmp r3, r2 + 4558 0268 3FF454AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4559 .loc 1 1053 8 discriminator 12 view .LVU1409 + 4560 026c 1832 adds r2, r2, #24 + 4561 026e 9342 cmp r3, r2 + 4562 0270 3FF450AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4563 .loc 1 1053 8 discriminator 14 view .LVU1410 + 4564 0274 02F55672 add r2, r2, #856 + 4565 0278 9342 cmp r3, r2 + 4566 027a 3FF44BAF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4567 .loc 1 1053 8 discriminator 16 view .LVU1411 + 4568 027e 1832 adds r2, r2, #24 + ARM GAS /tmp/ccXv4DVv.s page 138 + + + 4569 0280 9342 cmp r3, r2 + 4570 0282 3FF447AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4571 .loc 1 1053 8 discriminator 18 view .LVU1412 + 4572 0286 1832 adds r2, r2, #24 + 4573 0288 9342 cmp r3, r2 + 4574 028a 3FF443AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4575 .loc 1 1053 8 discriminator 20 view .LVU1413 + 4576 028e 1832 adds r2, r2, #24 + 4577 0290 9342 cmp r3, r2 + 4578 0292 3FF43FAF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4579 .loc 1 1053 8 discriminator 22 view .LVU1414 + 4580 0296 1832 adds r2, r2, #24 + 4581 0298 9342 cmp r3, r2 + 4582 029a 3FF43BAF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4583 .loc 1 1053 8 discriminator 24 view .LVU1415 + 4584 029e 1832 adds r2, r2, #24 + 4585 02a0 9342 cmp r3, r2 + 4586 02a2 3FF437AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4587 .loc 1 1053 8 discriminator 26 view .LVU1416 + 4588 02a6 1832 adds r2, r2, #24 + 4589 02a8 9342 cmp r3, r2 + 4590 02aa 3FF433AF beq .L215 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4591 .loc 1 1053 8 discriminator 28 view .LVU1417 + 4592 02ae 1832 adds r2, r2, #24 + 4593 02b0 9342 cmp r3, r2 + 4594 02b2 3FF42FAF beq .L215 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4595 .loc 1 1092 7 is_stmt 1 view .LVU1418 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4596 .loc 1 1092 12 is_stmt 0 view .LVU1419 + 4597 02b6 2968 ldr r1, [r5] +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4598 .loc 1 1092 47 view .LVU1420 + 4599 02b8 E36D ldr r3, [r4, #92] +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4600 .loc 1 1092 61 view .LVU1421 + 4601 02ba 03F01F03 and r3, r3, #31 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4602 .loc 1 1092 39 view .LVU1422 + 4603 02be 0822 movs r2, #8 + 4604 02c0 9A40 lsls r2, r2, r3 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4605 .loc 1 1092 9 view .LVU1423 + 4606 02c2 1142 tst r1, r2 + 4607 02c4 3FF44EAF beq .L217 +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4608 .loc 1 1097 9 is_stmt 1 view .LVU1424 +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4609 .loc 1 1097 39 is_stmt 0 view .LVU1425 + 4610 02c8 0120 movs r0, #1 + 4611 02ca 00FA03F3 lsl r3, r0, r3 + ARM GAS /tmp/ccXv4DVv.s page 139 + + +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4612 .loc 1 1097 20 view .LVU1426 + 4613 02ce 2B60 str r3, [r5] +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4614 .loc 1 1100 9 is_stmt 1 view .LVU1427 +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4615 .loc 1 1100 25 is_stmt 0 view .LVU1428 + 4616 02d0 6065 str r0, [r4, #84] +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4617 .loc 1 1103 9 is_stmt 1 view .LVU1429 +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4618 .loc 1 1103 21 is_stmt 0 view .LVU1430 + 4619 02d2 84F83500 strb r0, [r4, #53] +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4620 .loc 1 1106 9 is_stmt 1 view .LVU1431 +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4621 .loc 1 1106 9 view .LVU1432 + 4622 02d6 0023 movs r3, #0 + 4623 02d8 84F83430 strb r3, [r4, #52] +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4624 .loc 1 1106 9 view .LVU1433 +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4625 .loc 1 1108 9 view .LVU1434 +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4626 .loc 1 1108 16 is_stmt 0 view .LVU1435 + 4627 02dc A6E6 b .L203 + 4628 .L235: +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4629 .loc 1 1076 9 is_stmt 1 view .LVU1436 +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4630 .loc 1 1076 25 is_stmt 0 view .LVU1437 + 4631 02de 626D ldr r2, [r4, #84] + 4632 02e0 42F00102 orr r2, r2, #1 + 4633 02e4 6265 str r2, [r4, #84] +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4634 .loc 1 1079 9 is_stmt 1 view .LVU1438 +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4635 .loc 1 1079 21 is_stmt 0 view .LVU1439 + 4636 02e6 C8F80030 str r3, [r8] +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4637 .loc 1 1082 9 is_stmt 1 view .LVU1440 +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4638 .loc 1 1082 21 is_stmt 0 view .LVU1441 + 4639 02ea 0120 movs r0, #1 + 4640 02ec 84F83500 strb r0, [r4, #53] +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4641 .loc 1 1085 9 is_stmt 1 view .LVU1442 +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4642 .loc 1 1085 9 view .LVU1443 + 4643 02f0 0023 movs r3, #0 + 4644 02f2 84F83430 strb r3, [r4, #52] +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4645 .loc 1 1085 9 view .LVU1444 +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4646 .loc 1 1087 9 view .LVU1445 +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4647 .loc 1 1087 16 is_stmt 0 view .LVU1446 + ARM GAS /tmp/ccXv4DVv.s page 140 + + + 4648 02f6 99E6 b .L203 + 4649 .L236: +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4650 .loc 1 1115 7 is_stmt 1 view .LVU1447 +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4651 .loc 1 1115 12 is_stmt 0 view .LVU1448 + 4652 02f8 FFF7FEFF bl HAL_GetTick + 4653 .LVL182: +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4654 .loc 1 1115 26 view .LVU1449 + 4655 02fc A0EB0A00 sub r0, r0, r10 +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4656 .loc 1 1115 9 view .LVU1450 + 4657 0300 B042 cmp r0, r6 + 4658 0302 02D8 bhi .L221 +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4659 .loc 1 1115 50 discriminator 1 view .LVU1451 + 4660 0304 002E cmp r6, #0 + 4661 0306 7FF431AF bne .L220 + 4662 .L221: +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4663 .loc 1 1118 9 is_stmt 1 view .LVU1452 +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4664 .loc 1 1118 25 is_stmt 0 view .LVU1453 + 4665 030a 2023 movs r3, #32 + 4666 030c 6365 str r3, [r4, #84] +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* + 4667 .loc 1 1122 9 is_stmt 1 view .LVU1454 +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** /* + 4668 .loc 1 1122 16 is_stmt 0 view .LVU1455 + 4669 030e 2046 mov r0, r4 + 4670 0310 FFF7FEFF bl HAL_DMA_Abort + 4671 .LVL183: +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4672 .loc 1 1130 9 is_stmt 1 view .LVU1456 +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4673 .loc 1 1130 16 is_stmt 0 view .LVU1457 + 4674 0314 0120 movs r0, #1 + 4675 0316 89E6 b .L203 + 4676 .L237: +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4677 .loc 1 1164 3 is_stmt 1 view .LVU1458 +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4678 .loc 1 1164 5 is_stmt 0 view .LVU1459 + 4679 0318 002F cmp r7, #0 + 4680 031a 4FD1 bne .L226 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4681 .loc 1 1167 5 is_stmt 1 view .LVU1460 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4682 .loc 1 1167 8 is_stmt 0 view .LVU1461 + 4683 031c 2368 ldr r3, [r4] + 4684 031e 2449 ldr r1, .L240 + 4685 0320 244A ldr r2, .L240+4 + 4686 0322 9342 cmp r3, r2 + 4687 0324 18BF it ne + 4688 0326 8B42 cmpne r3, r1 + 4689 0328 32D0 beq .L227 + ARM GAS /tmp/ccXv4DVv.s page 141 + + +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4690 .loc 1 1167 8 discriminator 2 view .LVU1462 + 4691 032a 1832 adds r2, r2, #24 + 4692 032c 9342 cmp r3, r2 + 4693 032e 2FD0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4694 .loc 1 1167 8 discriminator 4 view .LVU1463 + 4695 0330 1832 adds r2, r2, #24 + 4696 0332 9342 cmp r3, r2 + 4697 0334 2CD0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4698 .loc 1 1167 8 discriminator 6 view .LVU1464 + 4699 0336 1832 adds r2, r2, #24 + 4700 0338 9342 cmp r3, r2 + 4701 033a 29D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4702 .loc 1 1167 8 discriminator 8 view .LVU1465 + 4703 033c 1832 adds r2, r2, #24 + 4704 033e 9342 cmp r3, r2 + 4705 0340 26D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4706 .loc 1 1167 8 discriminator 10 view .LVU1466 + 4707 0342 1832 adds r2, r2, #24 + 4708 0344 9342 cmp r3, r2 + 4709 0346 23D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4710 .loc 1 1167 8 discriminator 12 view .LVU1467 + 4711 0348 1832 adds r2, r2, #24 + 4712 034a 9342 cmp r3, r2 + 4713 034c 20D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4714 .loc 1 1167 8 discriminator 14 view .LVU1468 + 4715 034e 02F55672 add r2, r2, #856 + 4716 0352 9342 cmp r3, r2 + 4717 0354 1CD0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4718 .loc 1 1167 8 discriminator 16 view .LVU1469 + 4719 0356 1832 adds r2, r2, #24 + 4720 0358 9342 cmp r3, r2 + 4721 035a 19D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4722 .loc 1 1167 8 discriminator 18 view .LVU1470 + 4723 035c 1832 adds r2, r2, #24 + 4724 035e 9342 cmp r3, r2 + 4725 0360 16D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4726 .loc 1 1167 8 discriminator 20 view .LVU1471 + 4727 0362 1832 adds r2, r2, #24 + 4728 0364 9342 cmp r3, r2 + 4729 0366 13D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4730 .loc 1 1167 8 discriminator 22 view .LVU1472 + 4731 0368 1832 adds r2, r2, #24 + 4732 036a 9342 cmp r3, r2 + 4733 036c 10D0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4734 .loc 1 1167 8 discriminator 24 view .LVU1473 + ARM GAS /tmp/ccXv4DVv.s page 142 + + + 4735 036e 1832 adds r2, r2, #24 + 4736 0370 9342 cmp r3, r2 + 4737 0372 0DD0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4738 .loc 1 1167 8 discriminator 26 view .LVU1474 + 4739 0374 1832 adds r2, r2, #24 + 4740 0376 9342 cmp r3, r2 + 4741 0378 0AD0 beq .L227 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4742 .loc 1 1167 8 discriminator 28 view .LVU1475 + 4743 037a 1832 adds r2, r2, #24 + 4744 037c 9342 cmp r3, r2 + 4745 037e 07D0 beq .L227 +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4746 .loc 1 1173 7 is_stmt 1 view .LVU1476 +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4747 .loc 1 1173 44 is_stmt 0 view .LVU1477 + 4748 0380 E36D ldr r3, [r4, #92] +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4749 .loc 1 1173 58 view .LVU1478 + 4750 0382 03F01F02 and r2, r3, #31 +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4751 .loc 1 1173 36 view .LVU1479 + 4752 0386 0223 movs r3, #2 + 4753 0388 9340 lsls r3, r3, r2 +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4754 .loc 1 1173 19 view .LVU1480 + 4755 038a C8F80030 str r3, [r8] + 4756 038e 06E0 b .L228 + 4757 .L227: +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4758 .loc 1 1169 7 is_stmt 1 view .LVU1481 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4759 .loc 1 1169 67 is_stmt 0 view .LVU1482 + 4760 0390 E36D ldr r3, [r4, #92] +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4761 .loc 1 1169 81 view .LVU1483 + 4762 0392 03F01F02 and r2, r3, #31 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4763 .loc 1 1169 59 view .LVU1484 + 4764 0396 3023 movs r3, #48 + 4765 0398 9340 lsls r3, r3, r2 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4766 .loc 1 1169 19 view .LVU1485 + 4767 039a C8F80030 str r3, [r8] + 4768 .L228: +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4769 .loc 1 1177 5 is_stmt 1 view .LVU1486 +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4770 .loc 1 1177 5 view .LVU1487 + 4771 039e 0023 movs r3, #0 + 4772 03a0 84F83430 strb r3, [r4, #52] +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4773 .loc 1 1177 5 view .LVU1488 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4774 .loc 1 1179 5 view .LVU1489 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 143 + + + 4775 .loc 1 1179 17 is_stmt 0 view .LVU1490 + 4776 03a4 0123 movs r3, #1 + 4777 03a6 84F83530 strb r3, [r4, #53] +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4778 .loc 1 1194 10 view .LVU1491 + 4779 03aa 3846 mov r0, r7 + 4780 03ac 3EE6 b .L203 + 4781 .L241: + 4782 03ae 00BF .align 2 + 4783 .L240: + 4784 03b0 10000240 .word 1073872912 + 4785 03b4 28000240 .word 1073872936 + 4786 03b8 08540258 .word 1476547592 + 4787 .L226: +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4788 .loc 1 1184 5 is_stmt 1 view .LVU1492 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4789 .loc 1 1184 8 is_stmt 0 view .LVU1493 + 4790 03bc 2368 ldr r3, [r4] + 4791 03be 2249 ldr r1, .L242 + 4792 03c0 224A ldr r2, .L242+4 + 4793 03c2 9342 cmp r3, r2 + 4794 03c4 18BF it ne + 4795 03c6 8B42 cmpne r3, r1 + 4796 03c8 33D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4797 .loc 1 1184 8 discriminator 2 view .LVU1494 + 4798 03ca 1832 adds r2, r2, #24 + 4799 03cc 9342 cmp r3, r2 + 4800 03ce 30D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4801 .loc 1 1184 8 discriminator 4 view .LVU1495 + 4802 03d0 1832 adds r2, r2, #24 + 4803 03d2 9342 cmp r3, r2 + 4804 03d4 2DD0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4805 .loc 1 1184 8 discriminator 6 view .LVU1496 + 4806 03d6 1832 adds r2, r2, #24 + 4807 03d8 9342 cmp r3, r2 + 4808 03da 2AD0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4809 .loc 1 1184 8 discriminator 8 view .LVU1497 + 4810 03dc 1832 adds r2, r2, #24 + 4811 03de 9342 cmp r3, r2 + 4812 03e0 27D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4813 .loc 1 1184 8 discriminator 10 view .LVU1498 + 4814 03e2 1832 adds r2, r2, #24 + 4815 03e4 9342 cmp r3, r2 + 4816 03e6 24D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4817 .loc 1 1184 8 discriminator 12 view .LVU1499 + 4818 03e8 1832 adds r2, r2, #24 + 4819 03ea 9342 cmp r3, r2 + 4820 03ec 21D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4821 .loc 1 1184 8 discriminator 14 view .LVU1500 + ARM GAS /tmp/ccXv4DVv.s page 144 + + + 4822 03ee 02F55672 add r2, r2, #856 + 4823 03f2 9342 cmp r3, r2 + 4824 03f4 1DD0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4825 .loc 1 1184 8 discriminator 16 view .LVU1501 + 4826 03f6 1832 adds r2, r2, #24 + 4827 03f8 9342 cmp r3, r2 + 4828 03fa 1AD0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4829 .loc 1 1184 8 discriminator 18 view .LVU1502 + 4830 03fc 1832 adds r2, r2, #24 + 4831 03fe 9342 cmp r3, r2 + 4832 0400 17D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4833 .loc 1 1184 8 discriminator 20 view .LVU1503 + 4834 0402 1832 adds r2, r2, #24 + 4835 0404 9342 cmp r3, r2 + 4836 0406 14D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4837 .loc 1 1184 8 discriminator 22 view .LVU1504 + 4838 0408 1832 adds r2, r2, #24 + 4839 040a 9342 cmp r3, r2 + 4840 040c 11D0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4841 .loc 1 1184 8 discriminator 24 view .LVU1505 + 4842 040e 1832 adds r2, r2, #24 + 4843 0410 9342 cmp r3, r2 + 4844 0412 0ED0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4845 .loc 1 1184 8 discriminator 26 view .LVU1506 + 4846 0414 1832 adds r2, r2, #24 + 4847 0416 9342 cmp r3, r2 + 4848 0418 0BD0 beq .L229 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4849 .loc 1 1184 8 discriminator 28 view .LVU1507 + 4850 041a 1832 adds r2, r2, #24 + 4851 041c 9342 cmp r3, r2 + 4852 041e 08D0 beq .L229 +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4853 .loc 1 1190 7 is_stmt 1 view .LVU1508 +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4854 .loc 1 1190 44 is_stmt 0 view .LVU1509 + 4855 0420 E26D ldr r2, [r4, #92] +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4856 .loc 1 1190 58 view .LVU1510 + 4857 0422 02F01F02 and r2, r2, #31 +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4858 .loc 1 1190 36 view .LVU1511 + 4859 0426 0423 movs r3, #4 + 4860 0428 9340 lsls r3, r3, r2 +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4861 .loc 1 1190 19 view .LVU1512 + 4862 042a C8F80030 str r3, [r8] +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4863 .loc 1 1194 10 view .LVU1513 + 4864 042e 0020 movs r0, #0 + 4865 0430 FCE5 b .L203 + ARM GAS /tmp/ccXv4DVv.s page 145 + + + 4866 .L229: +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4867 .loc 1 1186 7 is_stmt 1 view .LVU1514 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4868 .loc 1 1186 48 is_stmt 0 view .LVU1515 + 4869 0432 E26D ldr r2, [r4, #92] +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4870 .loc 1 1186 62 view .LVU1516 + 4871 0434 02F01F02 and r2, r2, #31 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4872 .loc 1 1186 40 view .LVU1517 + 4873 0438 1023 movs r3, #16 + 4874 043a 9340 lsls r3, r3, r2 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4875 .loc 1 1186 19 view .LVU1518 + 4876 043c C8F80030 str r3, [r8] +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4877 .loc 1 1194 10 view .LVU1519 + 4878 0440 0020 movs r0, #0 + 4879 0442 F3E5 b .L203 + 4880 .LVL184: + 4881 .L230: + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4882 .loc 1 990 12 view .LVU1520 + 4883 0444 0120 movs r0, #1 + 4884 .LVL185: + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 4885 .loc 1 990 12 view .LVU1521 + 4886 0446 F1E5 b .L203 + 4887 .L243: + 4888 .align 2 + 4889 .L242: + 4890 0448 10000240 .word 1073872912 + 4891 044c 28000240 .word 1073872936 + 4892 .cfi_endproc + 4893 .LFE147: + 4895 .section .text.HAL_DMA_IRQHandler,"ax",%progbits + 4896 .align 1 + 4897 .global HAL_DMA_IRQHandler + 4898 .syntax unified + 4899 .thumb + 4900 .thumb_func + 4901 .fpu fpv5-d16 + 4903 HAL_DMA_IRQHandler: + 4904 .LVL186: + 4905 .LFB148: +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tmpisr_dma, tmpisr_bdma; + 4906 .loc 1 1204 1 is_stmt 1 view -0 + 4907 .cfi_startproc + 4908 @ args = 0, pretend = 0, frame = 8 + 4909 @ frame_needed = 0, uses_anonymous_args = 0 +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t tmpisr_dma, tmpisr_bdma; + 4910 .loc 1 1204 1 is_stmt 0 view .LVU1523 + 4911 0000 F0B5 push {r4, r5, r6, r7, lr} + 4912 .LCFI22: + 4913 .cfi_def_cfa_offset 20 + 4914 .cfi_offset 4, -20 + ARM GAS /tmp/ccXv4DVv.s page 146 + + + 4915 .cfi_offset 5, -16 + 4916 .cfi_offset 6, -12 + 4917 .cfi_offset 7, -8 + 4918 .cfi_offset 14, -4 + 4919 0002 83B0 sub sp, sp, #12 + 4920 .LCFI23: + 4921 .cfi_def_cfa_offset 32 + 4922 0004 0446 mov r4, r0 +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t ccr_reg; + 4923 .loc 1 1205 3 is_stmt 1 view .LVU1524 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** __IO uint32_t count = 0U; + 4924 .loc 1 1206 3 view .LVU1525 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t timeout = SystemCoreClock / 9600U; + 4925 .loc 1 1207 3 view .LVU1526 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** uint32_t timeout = SystemCoreClock / 9600U; + 4926 .loc 1 1207 17 is_stmt 0 view .LVU1527 + 4927 0006 0023 movs r3, #0 + 4928 0008 0193 str r3, [sp, #4] +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4929 .loc 1 1208 3 is_stmt 1 view .LVU1528 +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4930 .loc 1 1208 38 is_stmt 0 view .LVU1529 + 4931 000a 7D4B ldr r3, .L303 + 4932 000c 1D68 ldr r5, [r3] +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4933 .loc 1 1208 12 view .LVU1530 + 4934 000e 7D4B ldr r3, .L303+4 + 4935 0010 A3FB0535 umull r3, r5, r3, r5 + 4936 0014 AD0A lsrs r5, r5, #10 + 4937 .LVL187: +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + 4938 .loc 1 1211 3 is_stmt 1 view .LVU1531 +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + 4939 .loc 1 1211 62 is_stmt 0 view .LVU1532 + 4940 0016 876D ldr r7, [r0, #88] + 4941 .LVL188: +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4942 .loc 1 1212 3 is_stmt 1 view .LVU1533 +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** tmpisr_bdma = regs_bdma->ISR; + 4943 .loc 1 1214 3 view .LVU1534 +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** tmpisr_bdma = regs_bdma->ISR; + 4944 .loc 1 1214 15 is_stmt 0 view .LVU1535 + 4945 0018 3E68 ldr r6, [r7] + 4946 .LVL189: +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4947 .loc 1 1215 3 is_stmt 1 view .LVU1536 +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 4948 .loc 1 1215 15 is_stmt 0 view .LVU1537 + 4949 001a D7F800C0 ldr ip, [r7] + 4950 .LVL190: +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4951 .loc 1 1217 3 is_stmt 1 view .LVU1538 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4952 .loc 1 1217 6 is_stmt 0 view .LVU1539 + 4953 001e 0368 ldr r3, [r0] + 4954 0020 7949 ldr r1, .L303+8 + 4955 0022 7A48 ldr r0, .L303+12 + ARM GAS /tmp/ccXv4DVv.s page 147 + + + 4956 .LVL191: +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4957 .loc 1 1217 6 view .LVU1540 + 4958 0024 8342 cmp r3, r0 + 4959 0026 18BF it ne + 4960 0028 8B42 cmpne r3, r1 + 4961 002a 0CBF ite eq + 4962 002c 0120 moveq r0, #1 + 4963 002e 0020 movne r0, #0 + 4964 0030 61D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4965 .loc 1 1217 6 discriminator 2 view .LVU1541 + 4966 0032 774A ldr r2, .L303+16 + 4967 0034 9342 cmp r3, r2 + 4968 0036 5ED0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4969 .loc 1 1217 6 discriminator 4 view .LVU1542 + 4970 0038 1832 adds r2, r2, #24 + 4971 003a 9342 cmp r3, r2 + 4972 003c 5BD0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4973 .loc 1 1217 6 discriminator 6 view .LVU1543 + 4974 003e 1832 adds r2, r2, #24 + 4975 0040 9342 cmp r3, r2 + 4976 0042 58D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4977 .loc 1 1217 6 discriminator 8 view .LVU1544 + 4978 0044 1832 adds r2, r2, #24 + 4979 0046 9342 cmp r3, r2 + 4980 0048 55D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4981 .loc 1 1217 6 discriminator 10 view .LVU1545 + 4982 004a 1832 adds r2, r2, #24 + 4983 004c 9342 cmp r3, r2 + 4984 004e 52D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4985 .loc 1 1217 6 discriminator 12 view .LVU1546 + 4986 0050 1832 adds r2, r2, #24 + 4987 0052 9342 cmp r3, r2 + 4988 0054 4FD0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4989 .loc 1 1217 6 discriminator 14 view .LVU1547 + 4990 0056 02F55672 add r2, r2, #856 + 4991 005a 9342 cmp r3, r2 + 4992 005c 4BD0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4993 .loc 1 1217 6 discriminator 16 view .LVU1548 + 4994 005e 1832 adds r2, r2, #24 + 4995 0060 9342 cmp r3, r2 + 4996 0062 48D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 4997 .loc 1 1217 6 discriminator 18 view .LVU1549 + 4998 0064 1832 adds r2, r2, #24 + 4999 0066 9342 cmp r3, r2 + 5000 0068 45D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5001 .loc 1 1217 6 discriminator 20 view .LVU1550 + ARM GAS /tmp/ccXv4DVv.s page 148 + + + 5002 006a 1832 adds r2, r2, #24 + 5003 006c 9342 cmp r3, r2 + 5004 006e 42D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5005 .loc 1 1217 6 discriminator 22 view .LVU1551 + 5006 0070 1832 adds r2, r2, #24 + 5007 0072 9342 cmp r3, r2 + 5008 0074 3FD0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5009 .loc 1 1217 6 discriminator 24 view .LVU1552 + 5010 0076 1832 adds r2, r2, #24 + 5011 0078 9342 cmp r3, r2 + 5012 007a 3CD0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5013 .loc 1 1217 6 discriminator 26 view .LVU1553 + 5014 007c 1832 adds r2, r2, #24 + 5015 007e 9342 cmp r3, r2 + 5016 0080 39D0 beq .L245 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5017 .loc 1 1217 6 discriminator 28 view .LVU1554 + 5018 0082 1832 adds r2, r2, #24 + 5019 0084 9342 cmp r3, r2 + 5020 0086 36D0 beq .L245 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5021 .loc 1 1426 8 is_stmt 1 view .LVU1555 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5022 .loc 1 1426 11 is_stmt 0 view .LVU1556 + 5023 0088 6249 ldr r1, .L303+20 + 5024 008a 634A ldr r2, .L303+24 + 5025 008c 9342 cmp r3, r2 + 5026 008e 18BF it ne + 5027 0090 8B42 cmpne r3, r1 + 5028 0092 12D0 beq .L246 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5029 .loc 1 1426 11 discriminator 2 view .LVU1557 + 5030 0094 614A ldr r2, .L303+28 + 5031 0096 9342 cmp r3, r2 + 5032 0098 0FD0 beq .L246 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5033 .loc 1 1426 11 discriminator 4 view .LVU1558 + 5034 009a 1432 adds r2, r2, #20 + 5035 009c 9342 cmp r3, r2 + 5036 009e 0CD0 beq .L246 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5037 .loc 1 1426 11 discriminator 6 view .LVU1559 + 5038 00a0 1432 adds r2, r2, #20 + 5039 00a2 9342 cmp r3, r2 + 5040 00a4 09D0 beq .L246 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5041 .loc 1 1426 11 discriminator 8 view .LVU1560 + 5042 00a6 1432 adds r2, r2, #20 + 5043 00a8 9342 cmp r3, r2 + 5044 00aa 06D0 beq .L246 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5045 .loc 1 1426 11 discriminator 10 view .LVU1561 + 5046 00ac 1432 adds r2, r2, #20 + 5047 00ae 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 149 + + + 5048 00b0 03D0 beq .L246 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5049 .loc 1 1426 11 discriminator 12 view .LVU1562 + 5050 00b2 1432 adds r2, r2, #20 + 5051 00b4 9342 cmp r3, r2 + 5052 00b6 40F06182 bne .L244 + 5053 .L246: +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5054 .loc 1 1428 5 is_stmt 1 view .LVU1563 +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5055 .loc 1 1428 13 is_stmt 0 view .LVU1564 + 5056 00ba 1A68 ldr r2, [r3] + 5057 .LVL192: +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5058 .loc 1 1431 5 is_stmt 1 view .LVU1565 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5059 .loc 1 1431 48 is_stmt 0 view .LVU1566 + 5060 00bc E16D ldr r1, [r4, #92] +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5061 .loc 1 1431 62 view .LVU1567 + 5062 00be 01F01F01 and r1, r1, #31 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5063 .loc 1 1431 40 view .LVU1568 + 5064 00c2 0420 movs r0, #4 + 5065 00c4 8840 lsls r0, r0, r1 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5066 .loc 1 1431 8 view .LVU1569 + 5067 00c6 10EA0C0F tst r0, ip + 5068 00ca 00F0A782 beq .L286 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5069 .loc 1 1431 80 discriminator 1 view .LVU1570 + 5070 00ce 12F0040F tst r2, #4 + 5071 00d2 00F0A382 beq .L286 +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5072 .loc 1 1434 7 is_stmt 1 view .LVU1571 +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5073 .loc 1 1434 23 is_stmt 0 view .LVU1572 + 5074 00d6 7860 str r0, [r7, #4] +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5075 .loc 1 1437 7 is_stmt 1 view .LVU1573 +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5076 .loc 1 1437 9 is_stmt 0 view .LVU1574 + 5077 00d8 12F4004F tst r2, #32768 + 5078 00dc 00F05A82 beq .L287 +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5079 .loc 1 1440 9 is_stmt 1 view .LVU1575 +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5080 .loc 1 1440 11 is_stmt 0 view .LVU1576 + 5081 00e0 12F4803F tst r2, #65536 + 5082 00e4 40F05082 bne .L288 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5083 .loc 1 1442 11 is_stmt 1 view .LVU1577 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5084 .loc 1 1442 18 is_stmt 0 view .LVU1578 + 5085 00e8 A36C ldr r3, [r4, #72] +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5086 .loc 1 1442 13 view .LVU1579 + ARM GAS /tmp/ccXv4DVv.s page 150 + + + 5087 00ea 002B cmp r3, #0 + 5088 00ec 00F04682 beq .L244 +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5089 .loc 1 1445 13 is_stmt 1 view .LVU1580 + 5090 00f0 2046 mov r0, r4 + 5091 00f2 9847 blx r3 + 5092 .LVL193: +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5093 .loc 1 1445 13 is_stmt 0 view .LVU1581 + 5094 00f4 42E2 b .L244 + 5095 .LVL194: + 5096 .L245: +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5097 .loc 1 1220 5 is_stmt 1 view .LVU1582 +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5098 .loc 1 1220 49 is_stmt 0 view .LVU1583 + 5099 00f6 E26D ldr r2, [r4, #92] +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5100 .loc 1 1220 63 view .LVU1584 + 5101 00f8 02F01F01 and r1, r2, #31 +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5102 .loc 1 1220 41 view .LVU1585 + 5103 00fc 0822 movs r2, #8 + 5104 00fe 8A40 lsls r2, r2, r1 +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5105 .loc 1 1220 8 view .LVU1586 + 5106 0100 3242 tst r2, r6 + 5107 0102 41D0 beq .L248 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5108 .loc 1 1222 7 is_stmt 1 view .LVU1587 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5109 .loc 1 1222 51 is_stmt 0 view .LVU1588 + 5110 0104 70BB cbnz r0, .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5111 .loc 1 1222 10 discriminator 2 view .LVU1589 + 5112 0106 424A ldr r2, .L303+16 + 5113 0108 9342 cmp r3, r2 + 5114 010a 2BD0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5115 .loc 1 1222 10 discriminator 4 view .LVU1590 + 5116 010c 1832 adds r2, r2, #24 + 5117 010e 9342 cmp r3, r2 + 5118 0110 28D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5119 .loc 1 1222 10 discriminator 6 view .LVU1591 + 5120 0112 1832 adds r2, r2, #24 + 5121 0114 9342 cmp r3, r2 + 5122 0116 25D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5123 .loc 1 1222 10 discriminator 8 view .LVU1592 + 5124 0118 1832 adds r2, r2, #24 + 5125 011a 9342 cmp r3, r2 + 5126 011c 22D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5127 .loc 1 1222 10 discriminator 10 view .LVU1593 + 5128 011e 1832 adds r2, r2, #24 + 5129 0120 9342 cmp r3, r2 + ARM GAS /tmp/ccXv4DVv.s page 151 + + + 5130 0122 1FD0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5131 .loc 1 1222 10 discriminator 12 view .LVU1594 + 5132 0124 1832 adds r2, r2, #24 + 5133 0126 9342 cmp r3, r2 + 5134 0128 1CD0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5135 .loc 1 1222 10 discriminator 14 view .LVU1595 + 5136 012a 02F55672 add r2, r2, #856 + 5137 012e 9342 cmp r3, r2 + 5138 0130 18D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5139 .loc 1 1222 10 discriminator 16 view .LVU1596 + 5140 0132 1832 adds r2, r2, #24 + 5141 0134 9342 cmp r3, r2 + 5142 0136 15D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5143 .loc 1 1222 10 discriminator 18 view .LVU1597 + 5144 0138 1832 adds r2, r2, #24 + 5145 013a 9342 cmp r3, r2 + 5146 013c 12D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5147 .loc 1 1222 10 discriminator 20 view .LVU1598 + 5148 013e 1832 adds r2, r2, #24 + 5149 0140 9342 cmp r3, r2 + 5150 0142 0FD0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5151 .loc 1 1222 10 discriminator 22 view .LVU1599 + 5152 0144 1832 adds r2, r2, #24 + 5153 0146 9342 cmp r3, r2 + 5154 0148 0CD0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5155 .loc 1 1222 10 discriminator 24 view .LVU1600 + 5156 014a 1832 adds r2, r2, #24 + 5157 014c 9342 cmp r3, r2 + 5158 014e 09D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5159 .loc 1 1222 10 discriminator 26 view .LVU1601 + 5160 0150 1832 adds r2, r2, #24 + 5161 0152 9342 cmp r3, r2 + 5162 0154 06D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5163 .loc 1 1222 10 discriminator 28 view .LVU1602 + 5164 0156 1832 adds r2, r2, #24 + 5165 0158 9342 cmp r3, r2 + 5166 015a 03D0 beq .L249 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5167 .loc 1 1222 10 discriminator 30 view .LVU1603 + 5168 015c 1A68 ldr r2, [r3] +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5169 .loc 1 1222 51 discriminator 30 view .LVU1604 + 5170 015e C2F3C002 ubfx r2, r2, #3, #1 + 5171 0162 02E0 b .L251 + 5172 .L249: +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5173 .loc 1 1222 10 discriminator 29 view .LVU1605 + 5174 0164 1A68 ldr r2, [r3] + ARM GAS /tmp/ccXv4DVv.s page 152 + + +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5175 .loc 1 1222 51 discriminator 29 view .LVU1606 + 5176 0166 C2F38002 ubfx r2, r2, #2, #1 + 5177 .L251: +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5178 .loc 1 1222 9 discriminator 32 view .LVU1607 + 5179 016a 6AB1 cbz r2, .L248 +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5180 .loc 1 1225 9 is_stmt 1 view .LVU1608 +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5181 .loc 1 1225 55 is_stmt 0 view .LVU1609 + 5182 016c 1A68 ldr r2, [r3] + 5183 016e 22F00402 bic r2, r2, #4 + 5184 0172 1A60 str r2, [r3] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5185 .loc 1 1228 9 is_stmt 1 view .LVU1610 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5186 .loc 1 1228 51 is_stmt 0 view .LVU1611 + 5187 0174 E36D ldr r3, [r4, #92] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5188 .loc 1 1228 65 view .LVU1612 + 5189 0176 03F01F02 and r2, r3, #31 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5190 .loc 1 1228 43 view .LVU1613 + 5191 017a 0823 movs r3, #8 + 5192 017c 9340 lsls r3, r3, r2 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5193 .loc 1 1228 24 view .LVU1614 + 5194 017e BB60 str r3, [r7, #8] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5195 .loc 1 1231 9 is_stmt 1 view .LVU1615 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5196 .loc 1 1231 25 is_stmt 0 view .LVU1616 + 5197 0180 636D ldr r3, [r4, #84] + 5198 0182 43F00103 orr r3, r3, #1 + 5199 0186 6365 str r3, [r4, #84] + 5200 .L248: +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5201 .loc 1 1235 5 is_stmt 1 view .LVU1617 +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5202 .loc 1 1235 49 is_stmt 0 view .LVU1618 + 5203 0188 E26D ldr r2, [r4, #92] +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5204 .loc 1 1235 63 view .LVU1619 + 5205 018a 02F01F02 and r2, r2, #31 +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5206 .loc 1 1235 74 view .LVU1620 + 5207 018e 26FA02F3 lsr r3, r6, r2 +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5208 .loc 1 1235 8 view .LVU1621 + 5209 0192 13F0010F tst r3, #1 + 5210 0196 47D0 beq .L252 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5211 .loc 1 1237 7 is_stmt 1 view .LVU1622 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5212 .loc 1 1237 10 is_stmt 0 view .LVU1623 + 5213 0198 2368 ldr r3, [r4] + ARM GAS /tmp/ccXv4DVv.s page 153 + + +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5214 .loc 1 1237 51 view .LVU1624 + 5215 019a 1B48 ldr r0, .L303+8 + 5216 019c 1B49 ldr r1, .L303+12 + 5217 019e 8B42 cmp r3, r1 + 5218 01a0 18BF it ne + 5219 01a2 8342 cmpne r3, r0 + 5220 01a4 3CD0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5221 .loc 1 1237 10 discriminator 2 view .LVU1625 + 5222 01a6 1831 adds r1, r1, #24 + 5223 01a8 8B42 cmp r3, r1 + 5224 01aa 39D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5225 .loc 1 1237 10 discriminator 4 view .LVU1626 + 5226 01ac 1831 adds r1, r1, #24 + 5227 01ae 8B42 cmp r3, r1 + 5228 01b0 36D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5229 .loc 1 1237 10 discriminator 6 view .LVU1627 + 5230 01b2 1831 adds r1, r1, #24 + 5231 01b4 8B42 cmp r3, r1 + 5232 01b6 33D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5233 .loc 1 1237 10 discriminator 8 view .LVU1628 + 5234 01b8 1831 adds r1, r1, #24 + 5235 01ba 8B42 cmp r3, r1 + 5236 01bc 30D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5237 .loc 1 1237 10 discriminator 10 view .LVU1629 + 5238 01be 1831 adds r1, r1, #24 + 5239 01c0 8B42 cmp r3, r1 + 5240 01c2 2DD0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5241 .loc 1 1237 10 discriminator 12 view .LVU1630 + 5242 01c4 1831 adds r1, r1, #24 + 5243 01c6 8B42 cmp r3, r1 + 5244 01c8 2AD0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5245 .loc 1 1237 10 discriminator 14 view .LVU1631 + 5246 01ca 01F55671 add r1, r1, #856 + 5247 01ce 8B42 cmp r3, r1 + 5248 01d0 26D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5249 .loc 1 1237 10 discriminator 16 view .LVU1632 + 5250 01d2 1831 adds r1, r1, #24 + 5251 01d4 8B42 cmp r3, r1 + 5252 01d6 23D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5253 .loc 1 1237 10 discriminator 18 view .LVU1633 + 5254 01d8 1831 adds r1, r1, #24 + 5255 01da 8B42 cmp r3, r1 + 5256 01dc 20D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5257 .loc 1 1237 10 discriminator 20 view .LVU1634 + 5258 01de 1831 adds r1, r1, #24 + 5259 01e0 8B42 cmp r3, r1 + ARM GAS /tmp/ccXv4DVv.s page 154 + + + 5260 01e2 1DD0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5261 .loc 1 1237 10 discriminator 22 view .LVU1635 + 5262 01e4 1831 adds r1, r1, #24 + 5263 01e6 8B42 cmp r3, r1 + 5264 01e8 1AD0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5265 .loc 1 1237 10 discriminator 24 view .LVU1636 + 5266 01ea 1831 adds r1, r1, #24 + 5267 01ec 8B42 cmp r3, r1 + 5268 01ee 17D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5269 .loc 1 1237 10 discriminator 26 view .LVU1637 + 5270 01f0 1831 adds r1, r1, #24 + 5271 01f2 8B42 cmp r3, r1 + 5272 01f4 14D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5273 .loc 1 1237 10 discriminator 28 view .LVU1638 + 5274 01f6 1831 adds r1, r1, #24 + 5275 01f8 8B42 cmp r3, r1 + 5276 01fa 11D0 beq .L253 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5277 .loc 1 1237 10 discriminator 30 view .LVU1639 + 5278 01fc 1B68 ldr r3, [r3] + 5279 01fe 13E0 b .L252 + 5280 .L304: + 5281 .align 2 + 5282 .L303: + 5283 0200 00000000 .word SystemCoreClock + 5284 0204 B5814E1B .word 458129845 + 5285 0208 10000240 .word 1073872912 + 5286 020c 28000240 .word 1073872936 + 5287 0210 40000240 .word 1073872960 + 5288 0214 08540258 .word 1476547592 + 5289 0218 1C540258 .word 1476547612 + 5290 021c 30540258 .word 1476547632 + 5291 .L253: +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5292 .loc 1 1237 10 discriminator 29 view .LVU1640 + 5293 0220 5B69 ldr r3, [r3, #20] +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5294 .loc 1 1237 9 discriminator 29 view .LVU1641 + 5295 0222 13F0800F tst r3, #128 + 5296 0226 3BD1 bne .L255 + 5297 .L252: +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5298 .loc 1 1247 5 is_stmt 1 view .LVU1642 +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5299 .loc 1 1247 50 is_stmt 0 view .LVU1643 + 5300 0228 E36D ldr r3, [r4, #92] +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5301 .loc 1 1247 64 view .LVU1644 + 5302 022a 03F01F03 and r3, r3, #31 +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5303 .loc 1 1247 42 view .LVU1645 + 5304 022e 0422 movs r2, #4 + 5305 0230 02FA03F3 lsl r3, r2, r3 + ARM GAS /tmp/ccXv4DVv.s page 155 + + +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5306 .loc 1 1247 8 view .LVU1646 + 5307 0234 3342 tst r3, r6 + 5308 0236 40D0 beq .L256 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5309 .loc 1 1249 7 is_stmt 1 view .LVU1647 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5310 .loc 1 1249 10 is_stmt 0 view .LVU1648 + 5311 0238 2268 ldr r2, [r4] +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5312 .loc 1 1249 52 view .LVU1649 + 5313 023a 9648 ldr r0, .L305 + 5314 023c 9649 ldr r1, .L305+4 + 5315 023e 8A42 cmp r2, r1 + 5316 0240 18BF it ne + 5317 0242 8242 cmpne r2, r0 + 5318 0244 35D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5319 .loc 1 1249 10 discriminator 2 view .LVU1650 + 5320 0246 1831 adds r1, r1, #24 + 5321 0248 8A42 cmp r2, r1 + 5322 024a 32D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5323 .loc 1 1249 10 discriminator 4 view .LVU1651 + 5324 024c 1831 adds r1, r1, #24 + 5325 024e 8A42 cmp r2, r1 + 5326 0250 2FD0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5327 .loc 1 1249 10 discriminator 6 view .LVU1652 + 5328 0252 1831 adds r1, r1, #24 + 5329 0254 8A42 cmp r2, r1 + 5330 0256 2CD0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5331 .loc 1 1249 10 discriminator 8 view .LVU1653 + 5332 0258 1831 adds r1, r1, #24 + 5333 025a 8A42 cmp r2, r1 + 5334 025c 29D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5335 .loc 1 1249 10 discriminator 10 view .LVU1654 + 5336 025e 1831 adds r1, r1, #24 + 5337 0260 8A42 cmp r2, r1 + 5338 0262 26D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5339 .loc 1 1249 10 discriminator 12 view .LVU1655 + 5340 0264 1831 adds r1, r1, #24 + 5341 0266 8A42 cmp r2, r1 + 5342 0268 23D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5343 .loc 1 1249 10 discriminator 14 view .LVU1656 + 5344 026a 01F55671 add r1, r1, #856 + 5345 026e 8A42 cmp r2, r1 + 5346 0270 1FD0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5347 .loc 1 1249 10 discriminator 16 view .LVU1657 + 5348 0272 1831 adds r1, r1, #24 + 5349 0274 8A42 cmp r2, r1 + 5350 0276 1CD0 beq .L257 + ARM GAS /tmp/ccXv4DVv.s page 156 + + +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5351 .loc 1 1249 10 discriminator 18 view .LVU1658 + 5352 0278 1831 adds r1, r1, #24 + 5353 027a 8A42 cmp r2, r1 + 5354 027c 19D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5355 .loc 1 1249 10 discriminator 20 view .LVU1659 + 5356 027e 1831 adds r1, r1, #24 + 5357 0280 8A42 cmp r2, r1 + 5358 0282 16D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5359 .loc 1 1249 10 discriminator 22 view .LVU1660 + 5360 0284 1831 adds r1, r1, #24 + 5361 0286 8A42 cmp r2, r1 + 5362 0288 13D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5363 .loc 1 1249 10 discriminator 24 view .LVU1661 + 5364 028a 1831 adds r1, r1, #24 + 5365 028c 8A42 cmp r2, r1 + 5366 028e 10D0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5367 .loc 1 1249 10 discriminator 26 view .LVU1662 + 5368 0290 1831 adds r1, r1, #24 + 5369 0292 8A42 cmp r2, r1 + 5370 0294 0DD0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5371 .loc 1 1249 10 discriminator 28 view .LVU1663 + 5372 0296 1831 adds r1, r1, #24 + 5373 0298 8A42 cmp r2, r1 + 5374 029a 0AD0 beq .L257 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5375 .loc 1 1249 10 discriminator 30 view .LVU1664 + 5376 029c 1368 ldr r3, [r2] + 5377 029e 0CE0 b .L256 + 5378 .L255: +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5379 .loc 1 1240 9 is_stmt 1 view .LVU1665 +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5380 .loc 1 1240 43 is_stmt 0 view .LVU1666 + 5381 02a0 0123 movs r3, #1 + 5382 02a2 03FA02F2 lsl r2, r3, r2 +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5383 .loc 1 1240 24 view .LVU1667 + 5384 02a6 BA60 str r2, [r7, #8] +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5385 .loc 1 1243 9 is_stmt 1 view .LVU1668 +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5386 .loc 1 1243 25 is_stmt 0 view .LVU1669 + 5387 02a8 636D ldr r3, [r4, #84] + 5388 02aa 43F00203 orr r3, r3, #2 + 5389 02ae 6365 str r3, [r4, #84] + 5390 02b0 BAE7 b .L252 + 5391 .L257: +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5392 .loc 1 1249 10 discriminator 29 view .LVU1670 + 5393 02b2 1268 ldr r2, [r2] +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 157 + + + 5394 .loc 1 1249 9 discriminator 29 view .LVU1671 + 5395 02b4 12F0020F tst r2, #2 + 5396 02b8 3DD1 bne .L259 + 5397 .L256: +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5398 .loc 1 1259 5 is_stmt 1 view .LVU1672 +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5399 .loc 1 1259 49 is_stmt 0 view .LVU1673 + 5400 02ba E36D ldr r3, [r4, #92] +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5401 .loc 1 1259 63 view .LVU1674 + 5402 02bc 03F01F03 and r3, r3, #31 +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5403 .loc 1 1259 41 view .LVU1675 + 5404 02c0 1022 movs r2, #16 + 5405 02c2 02FA03F3 lsl r3, r2, r3 +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5406 .loc 1 1259 8 view .LVU1676 + 5407 02c6 3342 tst r3, r6 + 5408 02c8 5FD0 beq .L260 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5409 .loc 1 1261 7 is_stmt 1 view .LVU1677 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5410 .loc 1 1261 10 is_stmt 0 view .LVU1678 + 5411 02ca 2268 ldr r2, [r4] +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5412 .loc 1 1261 51 view .LVU1679 + 5413 02cc 7148 ldr r0, .L305 + 5414 02ce 7249 ldr r1, .L305+4 + 5415 02d0 8A42 cmp r2, r1 + 5416 02d2 18BF it ne + 5417 02d4 8242 cmpne r2, r0 + 5418 02d6 34D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5419 .loc 1 1261 10 discriminator 2 view .LVU1680 + 5420 02d8 1831 adds r1, r1, #24 + 5421 02da 8A42 cmp r2, r1 + 5422 02dc 31D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5423 .loc 1 1261 10 discriminator 4 view .LVU1681 + 5424 02de 1831 adds r1, r1, #24 + 5425 02e0 8A42 cmp r2, r1 + 5426 02e2 2ED0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5427 .loc 1 1261 10 discriminator 6 view .LVU1682 + 5428 02e4 1831 adds r1, r1, #24 + 5429 02e6 8A42 cmp r2, r1 + 5430 02e8 2BD0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5431 .loc 1 1261 10 discriminator 8 view .LVU1683 + 5432 02ea 1831 adds r1, r1, #24 + 5433 02ec 8A42 cmp r2, r1 + 5434 02ee 28D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5435 .loc 1 1261 10 discriminator 10 view .LVU1684 + 5436 02f0 1831 adds r1, r1, #24 + 5437 02f2 8A42 cmp r2, r1 + ARM GAS /tmp/ccXv4DVv.s page 158 + + + 5438 02f4 25D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5439 .loc 1 1261 10 discriminator 12 view .LVU1685 + 5440 02f6 1831 adds r1, r1, #24 + 5441 02f8 8A42 cmp r2, r1 + 5442 02fa 22D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5443 .loc 1 1261 10 discriminator 14 view .LVU1686 + 5444 02fc 01F55671 add r1, r1, #856 + 5445 0300 8A42 cmp r2, r1 + 5446 0302 1ED0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5447 .loc 1 1261 10 discriminator 16 view .LVU1687 + 5448 0304 1831 adds r1, r1, #24 + 5449 0306 8A42 cmp r2, r1 + 5450 0308 1BD0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5451 .loc 1 1261 10 discriminator 18 view .LVU1688 + 5452 030a 1831 adds r1, r1, #24 + 5453 030c 8A42 cmp r2, r1 + 5454 030e 18D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5455 .loc 1 1261 10 discriminator 20 view .LVU1689 + 5456 0310 1831 adds r1, r1, #24 + 5457 0312 8A42 cmp r2, r1 + 5458 0314 15D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5459 .loc 1 1261 10 discriminator 22 view .LVU1690 + 5460 0316 1831 adds r1, r1, #24 + 5461 0318 8A42 cmp r2, r1 + 5462 031a 12D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5463 .loc 1 1261 10 discriminator 24 view .LVU1691 + 5464 031c 1831 adds r1, r1, #24 + 5465 031e 8A42 cmp r2, r1 + 5466 0320 0FD0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5467 .loc 1 1261 10 discriminator 26 view .LVU1692 + 5468 0322 1831 adds r1, r1, #24 + 5469 0324 8A42 cmp r2, r1 + 5470 0326 0CD0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5471 .loc 1 1261 10 discriminator 28 view .LVU1693 + 5472 0328 1831 adds r1, r1, #24 + 5473 032a 8A42 cmp r2, r1 + 5474 032c 09D0 beq .L261 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5475 .loc 1 1261 10 discriminator 30 view .LVU1694 + 5476 032e 1268 ldr r2, [r2] +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5477 .loc 1 1261 51 discriminator 30 view .LVU1695 + 5478 0330 C2F38002 ubfx r2, r2, #2, #1 + 5479 0334 08E0 b .L263 + 5480 .L259: +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5481 .loc 1 1252 9 is_stmt 1 view .LVU1696 +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 159 + + + 5482 .loc 1 1252 24 is_stmt 0 view .LVU1697 + 5483 0336 BB60 str r3, [r7, #8] +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5484 .loc 1 1255 9 is_stmt 1 view .LVU1698 +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5485 .loc 1 1255 25 is_stmt 0 view .LVU1699 + 5486 0338 636D ldr r3, [r4, #84] + 5487 033a 43F00403 orr r3, r3, #4 + 5488 033e 6365 str r3, [r4, #84] + 5489 0340 BBE7 b .L256 + 5490 .L261: +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5491 .loc 1 1261 10 discriminator 29 view .LVU1700 + 5492 0342 1268 ldr r2, [r2] +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5493 .loc 1 1261 51 discriminator 29 view .LVU1701 + 5494 0344 C2F3C002 ubfx r2, r2, #3, #1 + 5495 .L263: +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5496 .loc 1 1261 9 discriminator 32 view .LVU1702 + 5497 0348 FAB1 cbz r2, .L260 +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5498 .loc 1 1264 9 is_stmt 1 view .LVU1703 +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5499 .loc 1 1264 24 is_stmt 0 view .LVU1704 + 5500 034a BB60 str r3, [r7, #8] +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5501 .loc 1 1267 9 is_stmt 1 view .LVU1705 +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5502 .loc 1 1267 43 is_stmt 0 view .LVU1706 + 5503 034c 2368 ldr r3, [r4] +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5504 .loc 1 1267 54 view .LVU1707 + 5505 034e 1A68 ldr r2, [r3] +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5506 .loc 1 1267 11 view .LVU1708 + 5507 0350 12F4802F tst r2, #262144 + 5508 0354 0DD0 beq .L264 +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5509 .loc 1 1270 11 is_stmt 1 view .LVU1709 +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5510 .loc 1 1270 55 is_stmt 0 view .LVU1710 + 5511 0356 1B68 ldr r3, [r3] +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5512 .loc 1 1270 13 view .LVU1711 + 5513 0358 13F4002F tst r3, #524288 + 5514 035c 04D1 bne .L265 +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5515 .loc 1 1272 13 is_stmt 1 view .LVU1712 +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5516 .loc 1 1272 20 is_stmt 0 view .LVU1713 + 5517 035e 236C ldr r3, [r4, #64] +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5518 .loc 1 1272 15 view .LVU1714 + 5519 0360 9BB1 cbz r3, .L260 +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5520 .loc 1 1275 15 is_stmt 1 view .LVU1715 + ARM GAS /tmp/ccXv4DVv.s page 160 + + + 5521 0362 2046 mov r0, r4 + 5522 0364 9847 blx r3 + 5523 .LVL195: +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5524 .loc 1 1275 15 is_stmt 0 view .LVU1716 + 5525 0366 10E0 b .L260 + 5526 .LVL196: + 5527 .L265: +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5528 .loc 1 1281 13 is_stmt 1 view .LVU1717 +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5529 .loc 1 1281 20 is_stmt 0 view .LVU1718 + 5530 0368 A36C ldr r3, [r4, #72] +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5531 .loc 1 1281 15 view .LVU1719 + 5532 036a 73B1 cbz r3, .L260 +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5533 .loc 1 1284 15 is_stmt 1 view .LVU1720 + 5534 036c 2046 mov r0, r4 + 5535 036e 9847 blx r3 + 5536 .LVL197: +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5537 .loc 1 1284 15 is_stmt 0 view .LVU1721 + 5538 0370 0BE0 b .L260 + 5539 .LVL198: + 5540 .L264: +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5541 .loc 1 1291 11 is_stmt 1 view .LVU1722 +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5542 .loc 1 1291 55 is_stmt 0 view .LVU1723 + 5543 0372 1A68 ldr r2, [r3] +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5544 .loc 1 1291 13 view .LVU1724 + 5545 0374 12F4807F tst r2, #256 + 5546 0378 03D1 bne .L266 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5547 .loc 1 1294 13 is_stmt 1 view .LVU1725 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5548 .loc 1 1294 59 is_stmt 0 view .LVU1726 + 5549 037a 1A68 ldr r2, [r3] + 5550 037c 22F00802 bic r2, r2, #8 + 5551 0380 1A60 str r2, [r3] + 5552 .L266: +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5553 .loc 1 1297 11 is_stmt 1 view .LVU1727 +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5554 .loc 1 1297 18 is_stmt 0 view .LVU1728 + 5555 0382 236C ldr r3, [r4, #64] +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5556 .loc 1 1297 13 view .LVU1729 + 5557 0384 0BB1 cbz r3, .L260 +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5558 .loc 1 1300 13 is_stmt 1 view .LVU1730 + 5559 0386 2046 mov r0, r4 + 5560 0388 9847 blx r3 + 5561 .LVL199: + 5562 .L260: + ARM GAS /tmp/ccXv4DVv.s page 161 + + +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5563 .loc 1 1306 5 view .LVU1731 +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5564 .loc 1 1306 49 is_stmt 0 view .LVU1732 + 5565 038a E36D ldr r3, [r4, #92] +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5566 .loc 1 1306 63 view .LVU1733 + 5567 038c 03F01F03 and r3, r3, #31 +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5568 .loc 1 1306 41 view .LVU1734 + 5569 0390 2022 movs r2, #32 + 5570 0392 02FA03F3 lsl r3, r2, r3 +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5571 .loc 1 1306 8 view .LVU1735 + 5572 0396 3342 tst r3, r6 + 5573 0398 00F09280 beq .L267 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5574 .loc 1 1308 7 is_stmt 1 view .LVU1736 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5575 .loc 1 1308 10 is_stmt 0 view .LVU1737 + 5576 039c 2268 ldr r2, [r4] +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5577 .loc 1 1308 51 view .LVU1738 + 5578 039e 3D48 ldr r0, .L305 + 5579 03a0 3D49 ldr r1, .L305+4 + 5580 03a2 8A42 cmp r2, r1 + 5581 03a4 18BF it ne + 5582 03a6 8242 cmpne r2, r0 + 5583 03a8 2ED0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5584 .loc 1 1308 10 discriminator 2 view .LVU1739 + 5585 03aa 1831 adds r1, r1, #24 + 5586 03ac 8A42 cmp r2, r1 + 5587 03ae 2BD0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5588 .loc 1 1308 10 discriminator 4 view .LVU1740 + 5589 03b0 1831 adds r1, r1, #24 + 5590 03b2 8A42 cmp r2, r1 + 5591 03b4 28D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5592 .loc 1 1308 10 discriminator 6 view .LVU1741 + 5593 03b6 1831 adds r1, r1, #24 + 5594 03b8 8A42 cmp r2, r1 + 5595 03ba 25D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5596 .loc 1 1308 10 discriminator 8 view .LVU1742 + 5597 03bc 1831 adds r1, r1, #24 + 5598 03be 8A42 cmp r2, r1 + 5599 03c0 22D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5600 .loc 1 1308 10 discriminator 10 view .LVU1743 + 5601 03c2 1831 adds r1, r1, #24 + 5602 03c4 8A42 cmp r2, r1 + 5603 03c6 1FD0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5604 .loc 1 1308 10 discriminator 12 view .LVU1744 + 5605 03c8 1831 adds r1, r1, #24 + ARM GAS /tmp/ccXv4DVv.s page 162 + + + 5606 03ca 8A42 cmp r2, r1 + 5607 03cc 1CD0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5608 .loc 1 1308 10 discriminator 14 view .LVU1745 + 5609 03ce 01F55671 add r1, r1, #856 + 5610 03d2 8A42 cmp r2, r1 + 5611 03d4 18D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5612 .loc 1 1308 10 discriminator 16 view .LVU1746 + 5613 03d6 1831 adds r1, r1, #24 + 5614 03d8 8A42 cmp r2, r1 + 5615 03da 15D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5616 .loc 1 1308 10 discriminator 18 view .LVU1747 + 5617 03dc 1831 adds r1, r1, #24 + 5618 03de 8A42 cmp r2, r1 + 5619 03e0 12D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5620 .loc 1 1308 10 discriminator 20 view .LVU1748 + 5621 03e2 1831 adds r1, r1, #24 + 5622 03e4 8A42 cmp r2, r1 + 5623 03e6 0FD0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5624 .loc 1 1308 10 discriminator 22 view .LVU1749 + 5625 03e8 1831 adds r1, r1, #24 + 5626 03ea 8A42 cmp r2, r1 + 5627 03ec 0CD0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5628 .loc 1 1308 10 discriminator 24 view .LVU1750 + 5629 03ee 1831 adds r1, r1, #24 + 5630 03f0 8A42 cmp r2, r1 + 5631 03f2 09D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5632 .loc 1 1308 10 discriminator 26 view .LVU1751 + 5633 03f4 1831 adds r1, r1, #24 + 5634 03f6 8A42 cmp r2, r1 + 5635 03f8 06D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5636 .loc 1 1308 10 discriminator 28 view .LVU1752 + 5637 03fa 1831 adds r1, r1, #24 + 5638 03fc 8A42 cmp r2, r1 + 5639 03fe 03D0 beq .L268 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5640 .loc 1 1308 10 discriminator 30 view .LVU1753 + 5641 0400 1268 ldr r2, [r2] +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5642 .loc 1 1308 51 discriminator 30 view .LVU1754 + 5643 0402 C2F34002 ubfx r2, r2, #1, #1 + 5644 0406 02E0 b .L270 + 5645 .L268: +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5646 .loc 1 1308 10 discriminator 29 view .LVU1755 + 5647 0408 1268 ldr r2, [r2] +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5648 .loc 1 1308 51 discriminator 29 view .LVU1756 + 5649 040a C2F30012 ubfx r2, r2, #4, #1 + 5650 .L270: + ARM GAS /tmp/ccXv4DVv.s page 163 + + +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5651 .loc 1 1308 9 discriminator 32 view .LVU1757 + 5652 040e 002A cmp r2, #0 + 5653 0410 56D0 beq .L267 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5654 .loc 1 1311 9 is_stmt 1 view .LVU1758 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5655 .loc 1 1311 24 is_stmt 0 view .LVU1759 + 5656 0412 BB60 str r3, [r7, #8] +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5657 .loc 1 1313 9 is_stmt 1 view .LVU1760 +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5658 .loc 1 1313 39 is_stmt 0 view .LVU1761 + 5659 0414 94F83530 ldrb r3, [r4, #53] @ zero_extendqisi2 + 5660 0418 DBB2 uxtb r3, r3 +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5661 .loc 1 1313 11 view .LVU1762 + 5662 041a 042B cmp r3, #4 + 5663 041c 0ED0 beq .L301 +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5664 .loc 1 1340 9 is_stmt 1 view .LVU1763 +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5665 .loc 1 1340 43 is_stmt 0 view .LVU1764 + 5666 041e 2368 ldr r3, [r4] +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5667 .loc 1 1340 54 view .LVU1765 + 5668 0420 1A68 ldr r2, [r3] +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5669 .loc 1 1340 11 view .LVU1766 + 5670 0422 12F4802F tst r2, #262144 + 5671 0426 39D0 beq .L276 +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5672 .loc 1 1343 11 is_stmt 1 view .LVU1767 +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5673 .loc 1 1343 55 is_stmt 0 view .LVU1768 + 5674 0428 1B68 ldr r3, [r3] +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5675 .loc 1 1343 13 view .LVU1769 + 5676 042a 13F4002F tst r3, #524288 + 5677 042e 2CD1 bne .L277 +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5678 .loc 1 1345 13 is_stmt 1 view .LVU1770 +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5679 .loc 1 1345 20 is_stmt 0 view .LVU1771 + 5680 0430 636C ldr r3, [r4, #68] +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5681 .loc 1 1345 15 view .LVU1772 + 5682 0432 002B cmp r3, #0 + 5683 0434 44D0 beq .L267 +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5684 .loc 1 1348 15 is_stmt 1 view .LVU1773 + 5685 0436 2046 mov r0, r4 + 5686 0438 9847 blx r3 + 5687 .LVL200: + 5688 043a 41E0 b .L267 + 5689 .L301: +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + ARM GAS /tmp/ccXv4DVv.s page 164 + + + 5690 .loc 1 1316 11 view .LVU1774 +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + 5691 .loc 1 1316 40 is_stmt 0 view .LVU1775 + 5692 043c 2268 ldr r2, [r4] +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + 5693 .loc 1 1316 57 view .LVU1776 + 5694 043e 1368 ldr r3, [r2] + 5695 0440 23F01603 bic r3, r3, #22 + 5696 0444 1360 str r3, [r2] +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5697 .loc 1 1317 11 is_stmt 1 view .LVU1777 +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5698 .loc 1 1317 40 is_stmt 0 view .LVU1778 + 5699 0446 2268 ldr r2, [r4] +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5700 .loc 1 1317 57 view .LVU1779 + 5701 0448 5369 ldr r3, [r2, #20] + 5702 044a 23F08003 bic r3, r3, #128 + 5703 044e 5361 str r3, [r2, #20] +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5704 .loc 1 1319 11 is_stmt 1 view .LVU1780 +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5705 .loc 1 1319 19 is_stmt 0 view .LVU1781 + 5706 0450 236C ldr r3, [r4, #64] +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5707 .loc 1 1319 13 view .LVU1782 + 5708 0452 B3B1 cbz r3, .L302 + 5709 .L272: +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5710 .loc 1 1321 13 is_stmt 1 view .LVU1783 +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5711 .loc 1 1321 42 is_stmt 0 view .LVU1784 + 5712 0454 2268 ldr r2, [r4] +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5713 .loc 1 1321 59 view .LVU1785 + 5714 0456 1368 ldr r3, [r2] + 5715 0458 23F00803 bic r3, r3, #8 + 5716 045c 1360 str r3, [r2] + 5717 .L273: +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5718 .loc 1 1325 11 is_stmt 1 view .LVU1786 +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5719 .loc 1 1325 43 is_stmt 0 view .LVU1787 + 5720 045e E36D ldr r3, [r4, #92] +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5721 .loc 1 1325 57 view .LVU1788 + 5722 0460 03F01F02 and r2, r3, #31 +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5723 .loc 1 1325 35 view .LVU1789 + 5724 0464 3F23 movs r3, #63 + 5725 0466 9340 lsls r3, r3, r2 +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5726 .loc 1 1325 26 view .LVU1790 + 5727 0468 BB60 str r3, [r7, #8] +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5728 .loc 1 1328 11 is_stmt 1 view .LVU1791 +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 165 + + + 5729 .loc 1 1328 11 view .LVU1792 + 5730 046a 0023 movs r3, #0 + 5731 046c 84F83430 strb r3, [r4, #52] +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5732 .loc 1 1328 11 view .LVU1793 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5733 .loc 1 1331 11 view .LVU1794 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5734 .loc 1 1331 23 is_stmt 0 view .LVU1795 + 5735 0470 0123 movs r3, #1 + 5736 0472 84F83530 strb r3, [r4, #53] +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5737 .loc 1 1333 11 is_stmt 1 view .LVU1796 +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5738 .loc 1 1333 18 is_stmt 0 view .LVU1797 + 5739 0476 236D ldr r3, [r4, #80] +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5740 .loc 1 1333 13 view .LVU1798 + 5741 0478 002B cmp r3, #0 + 5742 047a 7FD0 beq .L244 +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5743 .loc 1 1335 13 is_stmt 1 view .LVU1799 + 5744 047c 2046 mov r0, r4 + 5745 047e 9847 blx r3 + 5746 .LVL201: +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5747 .loc 1 1337 11 view .LVU1800 + 5748 0480 7CE0 b .L244 + 5749 .L302: +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5750 .loc 1 1319 59 is_stmt 0 discriminator 1 view .LVU1801 + 5751 0482 A36C ldr r3, [r4, #72] +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5752 .loc 1 1319 51 discriminator 1 view .LVU1802 + 5753 0484 002B cmp r3, #0 + 5754 0486 E5D1 bne .L272 + 5755 0488 E9E7 b .L273 + 5756 .L277: +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5757 .loc 1 1354 13 is_stmt 1 view .LVU1803 +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5758 .loc 1 1354 20 is_stmt 0 view .LVU1804 + 5759 048a E36B ldr r3, [r4, #60] +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5760 .loc 1 1354 15 view .LVU1805 + 5761 048c C3B1 cbz r3, .L267 +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5762 .loc 1 1357 15 is_stmt 1 view .LVU1806 + 5763 048e 2046 mov r0, r4 + 5764 0490 9847 blx r3 + 5765 .LVL202: + 5766 0492 15E0 b .L267 + 5767 .L306: + 5768 .align 2 + 5769 .L305: + 5770 0494 10000240 .word 1073872912 + 5771 0498 28000240 .word 1073872936 + ARM GAS /tmp/ccXv4DVv.s page 166 + + + 5772 .L276: +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5773 .loc 1 1364 11 view .LVU1807 +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5774 .loc 1 1364 55 is_stmt 0 view .LVU1808 + 5775 049c 1A68 ldr r2, [r3] +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5776 .loc 1 1364 13 view .LVU1809 + 5777 049e 12F4807F tst r2, #256 + 5778 04a2 09D1 bne .L278 +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5779 .loc 1 1367 13 is_stmt 1 view .LVU1810 +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5780 .loc 1 1367 59 is_stmt 0 view .LVU1811 + 5781 04a4 1A68 ldr r2, [r3] + 5782 04a6 22F01002 bic r2, r2, #16 + 5783 04aa 1A60 str r2, [r3] +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5784 .loc 1 1370 13 is_stmt 1 view .LVU1812 +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5785 .loc 1 1370 13 view .LVU1813 + 5786 04ac 0023 movs r3, #0 + 5787 04ae 84F83430 strb r3, [r4, #52] +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5788 .loc 1 1370 13 view .LVU1814 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5789 .loc 1 1373 13 view .LVU1815 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5790 .loc 1 1373 25 is_stmt 0 view .LVU1816 + 5791 04b2 0123 movs r3, #1 + 5792 04b4 84F83530 strb r3, [r4, #53] + 5793 .L278: +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5794 .loc 1 1376 11 is_stmt 1 view .LVU1817 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5795 .loc 1 1376 18 is_stmt 0 view .LVU1818 + 5796 04b8 E36B ldr r3, [r4, #60] +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5797 .loc 1 1376 13 view .LVU1819 + 5798 04ba 0BB1 cbz r3, .L267 +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5799 .loc 1 1379 13 is_stmt 1 view .LVU1820 + 5800 04bc 2046 mov r0, r4 + 5801 04be 9847 blx r3 + 5802 .LVL203: + 5803 .L267: +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5804 .loc 1 1386 5 view .LVU1821 +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5805 .loc 1 1386 12 is_stmt 0 view .LVU1822 + 5806 04c0 636D ldr r3, [r4, #84] +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5807 .loc 1 1386 7 view .LVU1823 + 5808 04c2 002B cmp r3, #0 + 5809 04c4 5AD0 beq .L244 +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5810 .loc 1 1388 7 is_stmt 1 view .LVU1824 + ARM GAS /tmp/ccXv4DVv.s page 167 + + +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5811 .loc 1 1388 15 is_stmt 0 view .LVU1825 + 5812 04c6 636D ldr r3, [r4, #84] +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5813 .loc 1 1388 9 view .LVU1826 + 5814 04c8 13F0010F tst r3, #1 + 5815 04cc 52D0 beq .L279 +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5816 .loc 1 1390 9 is_stmt 1 view .LVU1827 +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5817 .loc 1 1390 21 is_stmt 0 view .LVU1828 + 5818 04ce 0423 movs r3, #4 + 5819 04d0 84F83530 strb r3, [r4, #53] +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5820 .loc 1 1393 9 is_stmt 1 view .LVU1829 + 5821 04d4 2368 ldr r3, [r4] + 5822 04d6 9649 ldr r1, .L307 + 5823 04d8 964A ldr r2, .L307+4 + 5824 04da 9342 cmp r3, r2 + 5825 04dc 18BF it ne + 5826 04de 8B42 cmpne r3, r1 + 5827 04e0 2FD0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5828 .loc 1 1393 9 is_stmt 0 discriminator 2 view .LVU1830 + 5829 04e2 1832 adds r2, r2, #24 + 5830 04e4 9342 cmp r3, r2 + 5831 04e6 2CD0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5832 .loc 1 1393 9 discriminator 4 view .LVU1831 + 5833 04e8 1832 adds r2, r2, #24 + 5834 04ea 9342 cmp r3, r2 + 5835 04ec 29D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5836 .loc 1 1393 9 discriminator 6 view .LVU1832 + 5837 04ee 1832 adds r2, r2, #24 + 5838 04f0 9342 cmp r3, r2 + 5839 04f2 26D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5840 .loc 1 1393 9 discriminator 8 view .LVU1833 + 5841 04f4 1832 adds r2, r2, #24 + 5842 04f6 9342 cmp r3, r2 + 5843 04f8 23D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5844 .loc 1 1393 9 discriminator 10 view .LVU1834 + 5845 04fa 1832 adds r2, r2, #24 + 5846 04fc 9342 cmp r3, r2 + 5847 04fe 20D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5848 .loc 1 1393 9 discriminator 12 view .LVU1835 + 5849 0500 1832 adds r2, r2, #24 + 5850 0502 9342 cmp r3, r2 + 5851 0504 1DD0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5852 .loc 1 1393 9 discriminator 14 view .LVU1836 + 5853 0506 02F55672 add r2, r2, #856 + 5854 050a 9342 cmp r3, r2 + 5855 050c 19D0 beq .L280 + ARM GAS /tmp/ccXv4DVv.s page 168 + + +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5856 .loc 1 1393 9 discriminator 16 view .LVU1837 + 5857 050e 1832 adds r2, r2, #24 + 5858 0510 9342 cmp r3, r2 + 5859 0512 16D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5860 .loc 1 1393 9 discriminator 18 view .LVU1838 + 5861 0514 1832 adds r2, r2, #24 + 5862 0516 9342 cmp r3, r2 + 5863 0518 13D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5864 .loc 1 1393 9 discriminator 20 view .LVU1839 + 5865 051a 1832 adds r2, r2, #24 + 5866 051c 9342 cmp r3, r2 + 5867 051e 10D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5868 .loc 1 1393 9 discriminator 22 view .LVU1840 + 5869 0520 1832 adds r2, r2, #24 + 5870 0522 9342 cmp r3, r2 + 5871 0524 0DD0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5872 .loc 1 1393 9 discriminator 24 view .LVU1841 + 5873 0526 1832 adds r2, r2, #24 + 5874 0528 9342 cmp r3, r2 + 5875 052a 0AD0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5876 .loc 1 1393 9 discriminator 26 view .LVU1842 + 5877 052c 1832 adds r2, r2, #24 + 5878 052e 9342 cmp r3, r2 + 5879 0530 07D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5880 .loc 1 1393 9 discriminator 28 view .LVU1843 + 5881 0532 1832 adds r2, r2, #24 + 5882 0534 9342 cmp r3, r2 + 5883 0536 04D0 beq .L280 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5884 .loc 1 1393 9 discriminator 30 view .LVU1844 + 5885 0538 1A68 ldr r2, [r3] + 5886 053a 22F00102 bic r2, r2, #1 + 5887 053e 1A60 str r2, [r3] + 5888 0540 03E0 b .L284 + 5889 .L280: +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5890 .loc 1 1393 9 discriminator 29 view .LVU1845 + 5891 0542 1A68 ldr r2, [r3] + 5892 0544 22F00102 bic r2, r2, #1 + 5893 0548 1A60 str r2, [r3] + 5894 .L284: +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5895 .loc 1 1395 9 is_stmt 1 view .LVU1846 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5896 .loc 1 1397 11 view .LVU1847 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5897 .loc 1 1397 15 is_stmt 0 view .LVU1848 + 5898 054a 019B ldr r3, [sp, #4] + 5899 054c 0133 adds r3, r3, #1 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + ARM GAS /tmp/ccXv4DVv.s page 169 + + + 5900 .loc 1 1397 14 view .LVU1849 + 5901 054e 0193 str r3, [sp, #4] + 5902 0550 AB42 cmp r3, r5 + 5903 0552 04D8 bhi .L283 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5904 .loc 1 1402 14 is_stmt 1 view .LVU1850 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5905 .loc 1 1402 45 is_stmt 0 view .LVU1851 + 5906 0554 2368 ldr r3, [r4] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5907 .loc 1 1402 56 view .LVU1852 + 5908 0556 1B68 ldr r3, [r3] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5909 .loc 1 1402 9 view .LVU1853 + 5910 0558 13F0010F tst r3, #1 + 5911 055c F5D1 bne .L284 + 5912 .L283: +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5913 .loc 1 1405 9 is_stmt 1 view .LVU1854 +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5914 .loc 1 1405 9 view .LVU1855 + 5915 055e 0023 movs r3, #0 + 5916 0560 84F83430 strb r3, [r4, #52] +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5917 .loc 1 1405 9 view .LVU1856 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5918 .loc 1 1407 9 view .LVU1857 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5919 .loc 1 1407 42 is_stmt 0 view .LVU1858 + 5920 0564 2368 ldr r3, [r4] +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5921 .loc 1 1407 53 view .LVU1859 + 5922 0566 1B68 ldr r3, [r3] +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5923 .loc 1 1407 11 view .LVU1860 + 5924 0568 13F0010F tst r3, #1 + 5925 056c 08D0 beq .L285 +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5926 .loc 1 1410 11 is_stmt 1 view .LVU1861 +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5927 .loc 1 1410 23 is_stmt 0 view .LVU1862 + 5928 056e 0323 movs r3, #3 + 5929 0570 84F83530 strb r3, [r4, #53] + 5930 .L279: +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5931 .loc 1 1419 7 is_stmt 1 view .LVU1863 +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5932 .loc 1 1419 14 is_stmt 0 view .LVU1864 + 5933 0574 E36C ldr r3, [r4, #76] +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5934 .loc 1 1419 9 view .LVU1865 + 5935 0576 0BB1 cbz r3, .L244 +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5936 .loc 1 1422 9 is_stmt 1 view .LVU1866 + 5937 0578 2046 mov r0, r4 + 5938 057a 9847 blx r3 + 5939 .LVL204: + ARM GAS /tmp/ccXv4DVv.s page 170 + + + 5940 .L244: +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 5941 .loc 1 1561 1 is_stmt 0 view .LVU1867 + 5942 057c 03B0 add sp, sp, #12 + 5943 .LCFI24: + 5944 .cfi_remember_state + 5945 .cfi_def_cfa_offset 20 + 5946 @ sp needed + 5947 057e F0BD pop {r4, r5, r6, r7, pc} + 5948 .LVL205: + 5949 .L285: + 5950 .LCFI25: + 5951 .cfi_restore_state +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5952 .loc 1 1415 11 is_stmt 1 view .LVU1868 +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5953 .loc 1 1415 23 is_stmt 0 view .LVU1869 + 5954 0580 0123 movs r3, #1 + 5955 0582 84F83530 strb r3, [r4, #53] + 5956 0586 F5E7 b .L279 + 5957 .LVL206: + 5958 .L288: +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5959 .loc 1 1451 11 is_stmt 1 view .LVU1870 +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5960 .loc 1 1451 18 is_stmt 0 view .LVU1871 + 5961 0588 236C ldr r3, [r4, #64] +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5962 .loc 1 1451 13 view .LVU1872 + 5963 058a 002B cmp r3, #0 + 5964 058c F6D0 beq .L244 +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5965 .loc 1 1454 13 is_stmt 1 view .LVU1873 + 5966 058e 2046 mov r0, r4 + 5967 0590 9847 blx r3 + 5968 .LVL207: +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5969 .loc 1 1454 13 is_stmt 0 view .LVU1874 + 5970 0592 F3E7 b .L244 + 5971 .LVL208: + 5972 .L287: +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5973 .loc 1 1460 9 is_stmt 1 view .LVU1875 +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 5974 .loc 1 1460 11 is_stmt 0 view .LVU1876 + 5975 0594 12F0200F tst r2, #32 + 5976 0598 3AD1 bne .L289 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5977 .loc 1 1463 11 is_stmt 1 view .LVU1877 + 5978 059a 2368 ldr r3, [r4] + 5979 059c 6449 ldr r1, .L307 + 5980 059e 654A ldr r2, .L307+4 + 5981 .LVL209: +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5982 .loc 1 1463 11 is_stmt 0 view .LVU1878 + 5983 05a0 9342 cmp r3, r2 + 5984 05a2 18BF it ne + ARM GAS /tmp/ccXv4DVv.s page 171 + + + 5985 05a4 8B42 cmpne r3, r1 + 5986 05a6 2FD0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5987 .loc 1 1463 11 discriminator 2 view .LVU1879 + 5988 05a8 1832 adds r2, r2, #24 + 5989 05aa 9342 cmp r3, r2 + 5990 05ac 2CD0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5991 .loc 1 1463 11 discriminator 4 view .LVU1880 + 5992 05ae 1832 adds r2, r2, #24 + 5993 05b0 9342 cmp r3, r2 + 5994 05b2 29D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5995 .loc 1 1463 11 discriminator 6 view .LVU1881 + 5996 05b4 1832 adds r2, r2, #24 + 5997 05b6 9342 cmp r3, r2 + 5998 05b8 26D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 5999 .loc 1 1463 11 discriminator 8 view .LVU1882 + 6000 05ba 1832 adds r2, r2, #24 + 6001 05bc 9342 cmp r3, r2 + 6002 05be 23D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6003 .loc 1 1463 11 discriminator 10 view .LVU1883 + 6004 05c0 1832 adds r2, r2, #24 + 6005 05c2 9342 cmp r3, r2 + 6006 05c4 20D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6007 .loc 1 1463 11 discriminator 12 view .LVU1884 + 6008 05c6 1832 adds r2, r2, #24 + 6009 05c8 9342 cmp r3, r2 + 6010 05ca 1DD0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6011 .loc 1 1463 11 discriminator 14 view .LVU1885 + 6012 05cc 02F55672 add r2, r2, #856 + 6013 05d0 9342 cmp r3, r2 + 6014 05d2 19D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6015 .loc 1 1463 11 discriminator 16 view .LVU1886 + 6016 05d4 1832 adds r2, r2, #24 + 6017 05d6 9342 cmp r3, r2 + 6018 05d8 16D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6019 .loc 1 1463 11 discriminator 18 view .LVU1887 + 6020 05da 1832 adds r2, r2, #24 + 6021 05dc 9342 cmp r3, r2 + 6022 05de 13D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6023 .loc 1 1463 11 discriminator 20 view .LVU1888 + 6024 05e0 1832 adds r2, r2, #24 + 6025 05e2 9342 cmp r3, r2 + 6026 05e4 10D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6027 .loc 1 1463 11 discriminator 22 view .LVU1889 + 6028 05e6 1832 adds r2, r2, #24 + 6029 05e8 9342 cmp r3, r2 + 6030 05ea 0DD0 beq .L290 + ARM GAS /tmp/ccXv4DVv.s page 172 + + +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6031 .loc 1 1463 11 discriminator 24 view .LVU1890 + 6032 05ec 1832 adds r2, r2, #24 + 6033 05ee 9342 cmp r3, r2 + 6034 05f0 0AD0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6035 .loc 1 1463 11 discriminator 26 view .LVU1891 + 6036 05f2 1832 adds r2, r2, #24 + 6037 05f4 9342 cmp r3, r2 + 6038 05f6 07D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6039 .loc 1 1463 11 discriminator 28 view .LVU1892 + 6040 05f8 1832 adds r2, r2, #24 + 6041 05fa 9342 cmp r3, r2 + 6042 05fc 04D0 beq .L290 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6043 .loc 1 1463 11 discriminator 30 view .LVU1893 + 6044 05fe 1A68 ldr r2, [r3] + 6045 0600 22F00402 bic r2, r2, #4 + 6046 0604 1A60 str r2, [r3] + 6047 0606 03E0 b .L289 + 6048 .L290: +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6049 .loc 1 1463 11 discriminator 29 view .LVU1894 + 6050 0608 1A68 ldr r2, [r3] + 6051 060a 22F00802 bic r2, r2, #8 + 6052 060e 1A60 str r2, [r3] + 6053 .L289: +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6054 .loc 1 1469 8 is_stmt 1 view .LVU1895 +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6055 .loc 1 1469 15 is_stmt 0 view .LVU1896 + 6056 0610 236C ldr r3, [r4, #64] +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6057 .loc 1 1469 10 view .LVU1897 + 6058 0612 002B cmp r3, #0 + 6059 0614 B2D0 beq .L244 +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6060 .loc 1 1472 11 is_stmt 1 view .LVU1898 + 6061 0616 2046 mov r0, r4 + 6062 0618 9847 blx r3 + 6063 .LVL210: +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6064 .loc 1 1472 11 is_stmt 0 view .LVU1899 + 6065 061a AFE7 b .L244 + 6066 .LVL211: + 6067 .L286: +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6068 .loc 1 1478 10 is_stmt 1 view .LVU1900 +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6069 .loc 1 1478 45 is_stmt 0 view .LVU1901 + 6070 061c 0220 movs r0, #2 + 6071 061e 8840 lsls r0, r0, r1 +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6072 .loc 1 1478 13 view .LVU1902 + 6073 0620 10EA0C0F tst r0, ip + 6074 0624 60D0 beq .L292 + ARM GAS /tmp/ccXv4DVv.s page 173 + + +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6075 .loc 1 1478 85 discriminator 1 view .LVU1903 + 6076 0626 12F0020F tst r2, #2 + 6077 062a 5DD0 beq .L292 +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6078 .loc 1 1481 7 is_stmt 1 view .LVU1904 +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6079 .loc 1 1481 23 is_stmt 0 view .LVU1905 + 6080 062c 7860 str r0, [r7, #4] +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6081 .loc 1 1484 7 is_stmt 1 view .LVU1906 +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6082 .loc 1 1484 9 is_stmt 0 view .LVU1907 + 6083 062e 12F4004F tst r2, #32768 + 6084 0632 0ED0 beq .L293 +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6085 .loc 1 1487 9 is_stmt 1 view .LVU1908 +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6086 .loc 1 1487 11 is_stmt 0 view .LVU1909 + 6087 0634 12F4803F tst r2, #65536 + 6088 0638 05D1 bne .L294 +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6089 .loc 1 1489 11 is_stmt 1 view .LVU1910 +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6090 .loc 1 1489 18 is_stmt 0 view .LVU1911 + 6091 063a 636C ldr r3, [r4, #68] +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6092 .loc 1 1489 13 view .LVU1912 + 6093 063c 002B cmp r3, #0 + 6094 063e 9DD0 beq .L244 +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6095 .loc 1 1492 13 is_stmt 1 view .LVU1913 + 6096 0640 2046 mov r0, r4 + 6097 0642 9847 blx r3 + 6098 .LVL212: +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6099 .loc 1 1492 13 is_stmt 0 view .LVU1914 + 6100 0644 9AE7 b .L244 + 6101 .LVL213: + 6102 .L294: +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6103 .loc 1 1498 11 is_stmt 1 view .LVU1915 +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6104 .loc 1 1498 18 is_stmt 0 view .LVU1916 + 6105 0646 E36B ldr r3, [r4, #60] +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6106 .loc 1 1498 13 view .LVU1917 + 6107 0648 002B cmp r3, #0 + 6108 064a 97D0 beq .L244 +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6109 .loc 1 1501 13 is_stmt 1 view .LVU1918 + 6110 064c 2046 mov r0, r4 + 6111 064e 9847 blx r3 + 6112 .LVL214: +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6113 .loc 1 1501 13 is_stmt 0 view .LVU1919 + 6114 0650 94E7 b .L244 + ARM GAS /tmp/ccXv4DVv.s page 174 + + + 6115 .LVL215: + 6116 .L293: +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6117 .loc 1 1507 9 is_stmt 1 view .LVU1920 +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6118 .loc 1 1507 11 is_stmt 0 view .LVU1921 + 6119 0652 12F0200F tst r2, #32 + 6120 0656 40D1 bne .L295 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6121 .loc 1 1510 11 is_stmt 1 view .LVU1922 + 6122 0658 2368 ldr r3, [r4] + 6123 065a 3549 ldr r1, .L307 + 6124 065c 354A ldr r2, .L307+4 + 6125 .LVL216: +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6126 .loc 1 1510 11 is_stmt 0 view .LVU1923 + 6127 065e 9342 cmp r3, r2 + 6128 0660 18BF it ne + 6129 0662 8B42 cmpne r3, r1 + 6130 0664 2FD0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6131 .loc 1 1510 11 discriminator 2 view .LVU1924 + 6132 0666 1832 adds r2, r2, #24 + 6133 0668 9342 cmp r3, r2 + 6134 066a 2CD0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6135 .loc 1 1510 11 discriminator 4 view .LVU1925 + 6136 066c 1832 adds r2, r2, #24 + 6137 066e 9342 cmp r3, r2 + 6138 0670 29D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6139 .loc 1 1510 11 discriminator 6 view .LVU1926 + 6140 0672 1832 adds r2, r2, #24 + 6141 0674 9342 cmp r3, r2 + 6142 0676 26D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6143 .loc 1 1510 11 discriminator 8 view .LVU1927 + 6144 0678 1832 adds r2, r2, #24 + 6145 067a 9342 cmp r3, r2 + 6146 067c 23D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6147 .loc 1 1510 11 discriminator 10 view .LVU1928 + 6148 067e 1832 adds r2, r2, #24 + 6149 0680 9342 cmp r3, r2 + 6150 0682 20D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6151 .loc 1 1510 11 discriminator 12 view .LVU1929 + 6152 0684 1832 adds r2, r2, #24 + 6153 0686 9342 cmp r3, r2 + 6154 0688 1DD0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6155 .loc 1 1510 11 discriminator 14 view .LVU1930 + 6156 068a 02F55672 add r2, r2, #856 + 6157 068e 9342 cmp r3, r2 + 6158 0690 19D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6159 .loc 1 1510 11 discriminator 16 view .LVU1931 + ARM GAS /tmp/ccXv4DVv.s page 175 + + + 6160 0692 1832 adds r2, r2, #24 + 6161 0694 9342 cmp r3, r2 + 6162 0696 16D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6163 .loc 1 1510 11 discriminator 18 view .LVU1932 + 6164 0698 1832 adds r2, r2, #24 + 6165 069a 9342 cmp r3, r2 + 6166 069c 13D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6167 .loc 1 1510 11 discriminator 20 view .LVU1933 + 6168 069e 1832 adds r2, r2, #24 + 6169 06a0 9342 cmp r3, r2 + 6170 06a2 10D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6171 .loc 1 1510 11 discriminator 22 view .LVU1934 + 6172 06a4 1832 adds r2, r2, #24 + 6173 06a6 9342 cmp r3, r2 + 6174 06a8 0DD0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6175 .loc 1 1510 11 discriminator 24 view .LVU1935 + 6176 06aa 1832 adds r2, r2, #24 + 6177 06ac 9342 cmp r3, r2 + 6178 06ae 0AD0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6179 .loc 1 1510 11 discriminator 26 view .LVU1936 + 6180 06b0 1832 adds r2, r2, #24 + 6181 06b2 9342 cmp r3, r2 + 6182 06b4 07D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6183 .loc 1 1510 11 discriminator 28 view .LVU1937 + 6184 06b6 1832 adds r2, r2, #24 + 6185 06b8 9342 cmp r3, r2 + 6186 06ba 04D0 beq .L296 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6187 .loc 1 1510 11 discriminator 30 view .LVU1938 + 6188 06bc 1A68 ldr r2, [r3] + 6189 06be 22F00A02 bic r2, r2, #10 + 6190 06c2 1A60 str r2, [r3] + 6191 06c4 03E0 b .L298 + 6192 .L296: +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6193 .loc 1 1510 11 discriminator 29 view .LVU1939 + 6194 06c6 1A68 ldr r2, [r3] + 6195 06c8 22F01402 bic r2, r2, #20 + 6196 06cc 1A60 str r2, [r3] + 6197 .L298: +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6198 .loc 1 1513 11 is_stmt 1 view .LVU1940 +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6199 .loc 1 1513 11 view .LVU1941 + 6200 06ce 0023 movs r3, #0 + 6201 06d0 84F83430 strb r3, [r4, #52] +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6202 .loc 1 1513 11 view .LVU1942 +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6203 .loc 1 1516 11 view .LVU1943 +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 176 + + + 6204 .loc 1 1516 23 is_stmt 0 view .LVU1944 + 6205 06d4 0123 movs r3, #1 + 6206 06d6 84F83530 strb r3, [r4, #53] + 6207 .L295: +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6208 .loc 1 1519 9 is_stmt 1 view .LVU1945 +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6209 .loc 1 1519 16 is_stmt 0 view .LVU1946 + 6210 06da E36B ldr r3, [r4, #60] +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6211 .loc 1 1519 11 view .LVU1947 + 6212 06dc 002B cmp r3, #0 + 6213 06de 3FF44DAF beq .L244 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6214 .loc 1 1522 11 is_stmt 1 view .LVU1948 + 6215 06e2 2046 mov r0, r4 + 6216 06e4 9847 blx r3 + 6217 .LVL217: +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6218 .loc 1 1522 11 is_stmt 0 view .LVU1949 + 6219 06e6 49E7 b .L244 + 6220 .LVL218: + 6221 .L292: +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6222 .loc 1 1527 10 is_stmt 1 view .LVU1950 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6223 .loc 1 1527 45 is_stmt 0 view .LVU1951 + 6224 06e8 0820 movs r0, #8 + 6225 06ea 00FA01F1 lsl r1, r0, r1 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6226 .loc 1 1527 13 view .LVU1952 + 6227 06ee 11EA0C0F tst r1, ip + 6228 06f2 3FF443AF beq .L244 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6229 .loc 1 1527 85 discriminator 1 view .LVU1953 + 6230 06f6 12F0080F tst r2, #8 + 6231 06fa 3FF43FAF beq .L244 +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6232 .loc 1 1532 7 is_stmt 1 discriminator 30 view .LVU1954 + 6233 06fe 1A68 ldr r2, [r3] + 6234 .LVL219: +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6235 .loc 1 1532 7 is_stmt 0 discriminator 30 view .LVU1955 + 6236 0700 22F00E02 bic r2, r2, #14 + 6237 0704 1A60 str r2, [r3] +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6238 .loc 1 1535 7 is_stmt 1 discriminator 30 view .LVU1956 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6239 .loc 1 1535 49 is_stmt 0 discriminator 30 view .LVU1957 + 6240 0706 E36D ldr r3, [r4, #92] +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6241 .loc 1 1535 63 discriminator 30 view .LVU1958 + 6242 0708 03F01F03 and r3, r3, #31 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6243 .loc 1 1535 41 discriminator 30 view .LVU1959 + 6244 070c 0122 movs r2, #1 + 6245 070e 02FA03F3 lsl r3, r2, r3 + ARM GAS /tmp/ccXv4DVv.s page 177 + + +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6246 .loc 1 1535 23 discriminator 30 view .LVU1960 + 6247 0712 7B60 str r3, [r7, #4] +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6248 .loc 1 1538 7 is_stmt 1 discriminator 30 view .LVU1961 +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6249 .loc 1 1538 23 is_stmt 0 discriminator 30 view .LVU1962 + 6250 0714 6265 str r2, [r4, #84] +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6251 .loc 1 1541 7 is_stmt 1 discriminator 30 view .LVU1963 +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6252 .loc 1 1541 7 discriminator 30 view .LVU1964 + 6253 0716 0023 movs r3, #0 + 6254 0718 84F83430 strb r3, [r4, #52] +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6255 .loc 1 1541 7 discriminator 30 view .LVU1965 +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6256 .loc 1 1544 7 discriminator 30 view .LVU1966 +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6257 .loc 1 1544 19 is_stmt 0 discriminator 30 view .LVU1967 + 6258 071c 84F83520 strb r2, [r4, #53] +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6259 .loc 1 1546 7 is_stmt 1 discriminator 30 view .LVU1968 +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6260 .loc 1 1546 15 is_stmt 0 discriminator 30 view .LVU1969 + 6261 0720 E36C ldr r3, [r4, #76] +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6262 .loc 1 1546 10 discriminator 30 view .LVU1970 + 6263 0722 002B cmp r3, #0 + 6264 0724 3FF42AAF beq .L244 +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6265 .loc 1 1549 9 is_stmt 1 view .LVU1971 + 6266 0728 2046 mov r0, r4 + 6267 072a 9847 blx r3 + 6268 .LVL220: +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6269 .loc 1 1560 3 view .LVU1972 + 6270 072c 26E7 b .L244 + 6271 .L308: + 6272 072e 00BF .align 2 + 6273 .L307: + 6274 0730 10000240 .word 1073872912 + 6275 0734 28000240 .word 1073872936 + 6276 .cfi_endproc + 6277 .LFE148: + 6279 .section .text.HAL_DMA_RegisterCallback,"ax",%progbits + 6280 .align 1 + 6281 .global HAL_DMA_RegisterCallback + 6282 .syntax unified + 6283 .thumb + 6284 .thumb_func + 6285 .fpu fpv5-d16 + 6287 HAL_DMA_RegisterCallback: + 6288 .LVL221: + 6289 .LFB149: +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6290 .loc 1 1574 1 view -0 + ARM GAS /tmp/ccXv4DVv.s page 178 + + + 6291 .cfi_startproc + 6292 @ args = 0, pretend = 0, frame = 0 + 6293 @ frame_needed = 0, uses_anonymous_args = 0 + 6294 @ link register save eliminated. +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6295 .loc 1 1576 3 view .LVU1974 +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6296 .loc 1 1579 3 view .LVU1975 +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6297 .loc 1 1579 5 is_stmt 0 view .LVU1976 + 6298 0000 0346 mov r3, r0 + 6299 0002 58B3 cbz r0, .L319 +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6300 .loc 1 1585 3 is_stmt 1 view .LVU1977 +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6301 .loc 1 1585 3 view .LVU1978 + 6302 0004 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 6303 .LVL222: +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6304 .loc 1 1585 3 is_stmt 0 view .LVU1979 + 6305 0008 0128 cmp r0, #1 + 6306 000a 29D0 beq .L320 +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6307 .loc 1 1585 3 is_stmt 1 discriminator 2 view .LVU1980 + 6308 000c 0120 movs r0, #1 + 6309 000e 83F83400 strb r0, [r3, #52] +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6310 .loc 1 1585 3 discriminator 2 view .LVU1981 +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6311 .loc 1 1587 3 discriminator 2 view .LVU1982 +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6312 .loc 1 1587 33 is_stmt 0 discriminator 2 view .LVU1983 + 6313 0012 93F83500 ldrb r0, [r3, #53] @ zero_extendqisi2 + 6314 0016 C0B2 uxtb r0, r0 +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6315 .loc 1 1587 5 discriminator 2 view .LVU1984 + 6316 0018 0128 cmp r0, #1 + 6317 001a 04D0 beq .L323 +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6318 .loc 1 1622 12 view .LVU1985 + 6319 001c 0120 movs r0, #1 + 6320 .L311: + 6321 .LVL223: +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6322 .loc 1 1626 3 is_stmt 1 view .LVU1986 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6323 .loc 1 1626 3 view .LVU1987 + 6324 001e 0022 movs r2, #0 + 6325 .LVL224: +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6326 .loc 1 1626 3 is_stmt 0 view .LVU1988 + 6327 0020 83F83420 strb r2, [r3, #52] +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6328 .loc 1 1626 3 is_stmt 1 view .LVU1989 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6329 .loc 1 1628 3 view .LVU1990 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + ARM GAS /tmp/ccXv4DVv.s page 179 + + + 6330 .loc 1 1628 10 is_stmt 0 view .LVU1991 + 6331 0024 7047 bx lr + 6332 .LVL225: + 6333 .L323: +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6334 .loc 1 1589 5 is_stmt 1 view .LVU1992 + 6335 0026 0529 cmp r1, #5 + 6336 0028 16D8 bhi .L322 + 6337 002a DFE801F0 tbb [pc, r1] + 6338 .L313: + 6339 002e 03 .byte (.L318-.L313)/2 + 6340 002f 06 .byte (.L317-.L313)/2 + 6341 0030 09 .byte (.L316-.L313)/2 + 6342 0031 0C .byte (.L315-.L313)/2 + 6343 0032 0F .byte (.L314-.L313)/2 + 6344 0033 12 .byte (.L312-.L313)/2 + 6345 .p2align 1 + 6346 .L318: +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6347 .loc 1 1592 7 view .LVU1993 +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6348 .loc 1 1592 30 is_stmt 0 view .LVU1994 + 6349 0034 DA63 str r2, [r3, #60] +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6350 .loc 1 1593 7 is_stmt 1 view .LVU1995 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6351 .loc 1 1576 21 is_stmt 0 view .LVU1996 + 6352 0036 0846 mov r0, r1 +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6353 .loc 1 1593 7 view .LVU1997 + 6354 0038 F1E7 b .L311 + 6355 .L317: +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6356 .loc 1 1596 7 is_stmt 1 view .LVU1998 +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6357 .loc 1 1596 34 is_stmt 0 view .LVU1999 + 6358 003a 1A64 str r2, [r3, #64] +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6359 .loc 1 1597 7 is_stmt 1 view .LVU2000 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6360 .loc 1 1576 21 is_stmt 0 view .LVU2001 + 6361 003c 0020 movs r0, #0 +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6362 .loc 1 1597 7 view .LVU2002 + 6363 003e EEE7 b .L311 + 6364 .L316: +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6365 .loc 1 1600 7 is_stmt 1 view .LVU2003 +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6366 .loc 1 1600 32 is_stmt 0 view .LVU2004 + 6367 0040 5A64 str r2, [r3, #68] +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6368 .loc 1 1601 7 is_stmt 1 view .LVU2005 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6369 .loc 1 1576 21 is_stmt 0 view .LVU2006 + 6370 0042 0020 movs r0, #0 +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + ARM GAS /tmp/ccXv4DVv.s page 180 + + + 6371 .loc 1 1601 7 view .LVU2007 + 6372 0044 EBE7 b .L311 + 6373 .L315: +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6374 .loc 1 1604 7 is_stmt 1 view .LVU2008 +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6375 .loc 1 1604 36 is_stmt 0 view .LVU2009 + 6376 0046 9A64 str r2, [r3, #72] +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6377 .loc 1 1605 7 is_stmt 1 view .LVU2010 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6378 .loc 1 1576 21 is_stmt 0 view .LVU2011 + 6379 0048 0020 movs r0, #0 +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6380 .loc 1 1605 7 view .LVU2012 + 6381 004a E8E7 b .L311 + 6382 .L314: +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6383 .loc 1 1608 7 is_stmt 1 view .LVU2013 +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6384 .loc 1 1608 31 is_stmt 0 view .LVU2014 + 6385 004c DA64 str r2, [r3, #76] +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6386 .loc 1 1609 7 is_stmt 1 view .LVU2015 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6387 .loc 1 1576 21 is_stmt 0 view .LVU2016 + 6388 004e 0020 movs r0, #0 +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6389 .loc 1 1609 7 view .LVU2017 + 6390 0050 E5E7 b .L311 + 6391 .L312: +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6392 .loc 1 1612 7 is_stmt 1 view .LVU2018 +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6393 .loc 1 1612 31 is_stmt 0 view .LVU2019 + 6394 0052 1A65 str r2, [r3, #80] +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6395 .loc 1 1613 7 is_stmt 1 view .LVU2020 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6396 .loc 1 1576 21 is_stmt 0 view .LVU2021 + 6397 0054 0020 movs r0, #0 +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6398 .loc 1 1613 7 view .LVU2022 + 6399 0056 E2E7 b .L311 + 6400 .L322: +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6401 .loc 1 1587 5 view .LVU2023 + 6402 0058 0020 movs r0, #0 + 6403 005a E0E7 b .L311 + 6404 .LVL226: + 6405 .L319: +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6406 .loc 1 1581 12 view .LVU2024 + 6407 005c 0120 movs r0, #1 + 6408 .LVL227: +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6409 .loc 1 1581 12 view .LVU2025 + ARM GAS /tmp/ccXv4DVv.s page 181 + + + 6410 005e 7047 bx lr + 6411 .L320: +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6412 .loc 1 1585 3 view .LVU2026 + 6413 0060 0220 movs r0, #2 +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6414 .loc 1 1629 1 view .LVU2027 + 6415 0062 7047 bx lr + 6416 .cfi_endproc + 6417 .LFE149: + 6419 .section .text.HAL_DMA_UnRegisterCallback,"ax",%progbits + 6420 .align 1 + 6421 .global HAL_DMA_UnRegisterCallback + 6422 .syntax unified + 6423 .thumb + 6424 .thumb_func + 6425 .fpu fpv5-d16 + 6427 HAL_DMA_UnRegisterCallback: + 6428 .LVL228: + 6429 .LFB150: +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 6430 .loc 1 1640 1 is_stmt 1 view -0 + 6431 .cfi_startproc + 6432 @ args = 0, pretend = 0, frame = 0 + 6433 @ frame_needed = 0, uses_anonymous_args = 0 + 6434 @ link register save eliminated. +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6435 .loc 1 1641 3 view .LVU2029 +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6436 .loc 1 1644 3 view .LVU2030 +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6437 .loc 1 1644 5 is_stmt 0 view .LVU2031 + 6438 0000 0346 mov r3, r0 + 6439 0002 0028 cmp r0, #0 + 6440 0004 33D0 beq .L335 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6441 .loc 1 1650 3 is_stmt 1 view .LVU2032 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6442 .loc 1 1650 3 view .LVU2033 + 6443 0006 90F83420 ldrb r2, [r0, #52] @ zero_extendqisi2 + 6444 000a 012A cmp r2, #1 + 6445 000c 31D0 beq .L336 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6446 .loc 1 1650 3 discriminator 2 view .LVU2034 + 6447 000e 0122 movs r2, #1 + 6448 0010 80F83420 strb r2, [r0, #52] +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6449 .loc 1 1650 3 discriminator 2 view .LVU2035 +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6450 .loc 1 1652 3 discriminator 2 view .LVU2036 +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6451 .loc 1 1652 33 is_stmt 0 discriminator 2 view .LVU2037 + 6452 0014 90F83500 ldrb r0, [r0, #53] @ zero_extendqisi2 + 6453 .LVL229: +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6454 .loc 1 1652 33 discriminator 2 view .LVU2038 + 6455 0018 C0B2 uxtb r0, r0 + ARM GAS /tmp/ccXv4DVv.s page 182 + + +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6456 .loc 1 1652 5 discriminator 2 view .LVU2039 + 6457 001a 9042 cmp r0, r2 + 6458 001c 04D0 beq .L338 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6459 .loc 1 1696 12 view .LVU2040 + 6460 001e 0120 movs r0, #1 + 6461 .L326: + 6462 .LVL230: +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6463 .loc 1 1700 3 is_stmt 1 view .LVU2041 +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6464 .loc 1 1700 3 view .LVU2042 + 6465 0020 0022 movs r2, #0 + 6466 0022 83F83420 strb r2, [r3, #52] +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6467 .loc 1 1700 3 view .LVU2043 +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6468 .loc 1 1702 3 view .LVU2044 +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6469 .loc 1 1702 10 is_stmt 0 view .LVU2045 + 6470 0026 7047 bx lr + 6471 .LVL231: + 6472 .L338: +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** { + 6473 .loc 1 1654 5 is_stmt 1 view .LVU2046 + 6474 0028 0629 cmp r1, #6 + 6475 002a F9D8 bhi .L326 + 6476 002c DFE801F0 tbb [pc, r1] + 6477 .L328: + 6478 0030 04 .byte (.L334-.L328)/2 + 6479 0031 08 .byte (.L333-.L328)/2 + 6480 0032 0B .byte (.L332-.L328)/2 + 6481 0033 0E .byte (.L331-.L328)/2 + 6482 0034 11 .byte (.L330-.L328)/2 + 6483 0035 14 .byte (.L329-.L328)/2 + 6484 0036 17 .byte (.L327-.L328)/2 + 6485 0037 00 .p2align 1 + 6486 .L334: +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6487 .loc 1 1657 7 view .LVU2047 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6488 .loc 1 1657 30 is_stmt 0 view .LVU2048 + 6489 0038 0022 movs r2, #0 + 6490 003a DA63 str r2, [r3, #60] +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6491 .loc 1 1658 7 is_stmt 1 view .LVU2049 +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6492 .loc 1 1641 21 is_stmt 0 view .LVU2050 + 6493 003c 0846 mov r0, r1 +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6494 .loc 1 1658 7 view .LVU2051 + 6495 003e EFE7 b .L326 + 6496 .L333: +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6497 .loc 1 1661 7 is_stmt 1 view .LVU2052 +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + ARM GAS /tmp/ccXv4DVv.s page 183 + + + 6498 .loc 1 1661 34 is_stmt 0 view .LVU2053 + 6499 0040 0020 movs r0, #0 + 6500 0042 1864 str r0, [r3, #64] +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6501 .loc 1 1662 7 is_stmt 1 view .LVU2054 + 6502 0044 ECE7 b .L326 + 6503 .L332: +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6504 .loc 1 1665 7 view .LVU2055 +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6505 .loc 1 1665 32 is_stmt 0 view .LVU2056 + 6506 0046 0020 movs r0, #0 + 6507 0048 5864 str r0, [r3, #68] +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6508 .loc 1 1666 7 is_stmt 1 view .LVU2057 + 6509 004a E9E7 b .L326 + 6510 .L331: +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6511 .loc 1 1669 7 view .LVU2058 +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6512 .loc 1 1669 36 is_stmt 0 view .LVU2059 + 6513 004c 0020 movs r0, #0 + 6514 004e 9864 str r0, [r3, #72] +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6515 .loc 1 1670 7 is_stmt 1 view .LVU2060 + 6516 0050 E6E7 b .L326 + 6517 .L330: +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6518 .loc 1 1673 7 view .LVU2061 +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6519 .loc 1 1673 31 is_stmt 0 view .LVU2062 + 6520 0052 0020 movs r0, #0 + 6521 0054 D864 str r0, [r3, #76] +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6522 .loc 1 1674 7 is_stmt 1 view .LVU2063 + 6523 0056 E3E7 b .L326 + 6524 .L329: +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6525 .loc 1 1677 7 view .LVU2064 +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6526 .loc 1 1677 31 is_stmt 0 view .LVU2065 + 6527 0058 0020 movs r0, #0 + 6528 005a 1865 str r0, [r3, #80] +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6529 .loc 1 1678 7 is_stmt 1 view .LVU2066 + 6530 005c E0E7 b .L326 + 6531 .L327: +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 6532 .loc 1 1681 7 view .LVU2067 +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 6533 .loc 1 1681 30 is_stmt 0 view .LVU2068 + 6534 005e 0020 movs r0, #0 + 6535 0060 D863 str r0, [r3, #60] +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 6536 .loc 1 1682 7 is_stmt 1 view .LVU2069 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 6537 .loc 1 1682 34 is_stmt 0 view .LVU2070 + ARM GAS /tmp/ccXv4DVv.s page 184 + + + 6538 0062 1864 str r0, [r3, #64] +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 6539 .loc 1 1683 7 is_stmt 1 view .LVU2071 +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 6540 .loc 1 1683 32 is_stmt 0 view .LVU2072 + 6541 0064 5864 str r0, [r3, #68] +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 6542 .loc 1 1684 7 is_stmt 1 view .LVU2073 +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 6543 .loc 1 1684 36 is_stmt 0 view .LVU2074 + 6544 0066 9864 str r0, [r3, #72] +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 6545 .loc 1 1685 7 is_stmt 1 view .LVU2075 +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 6546 .loc 1 1685 31 is_stmt 0 view .LVU2076 + 6547 0068 D864 str r0, [r3, #76] +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6548 .loc 1 1686 7 is_stmt 1 view .LVU2077 +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** break; + 6549 .loc 1 1686 31 is_stmt 0 view .LVU2078 + 6550 006a 1865 str r0, [r3, #80] +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6551 .loc 1 1687 7 is_stmt 1 view .LVU2079 + 6552 006c D8E7 b .L326 + 6553 .LVL232: + 6554 .L335: +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6555 .loc 1 1646 12 is_stmt 0 view .LVU2080 + 6556 006e 0120 movs r0, #1 + 6557 .LVL233: +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6558 .loc 1 1646 12 view .LVU2081 + 6559 0070 7047 bx lr + 6560 .LVL234: + 6561 .L336: +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6562 .loc 1 1650 3 view .LVU2082 + 6563 0072 0220 movs r0, #2 + 6564 .LVL235: +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6565 .loc 1 1703 1 view .LVU2083 + 6566 0074 7047 bx lr + 6567 .cfi_endproc + 6568 .LFE150: + 6570 .section .text.HAL_DMA_GetState,"ax",%progbits + 6571 .align 1 + 6572 .global HAL_DMA_GetState + 6573 .syntax unified + 6574 .thumb + 6575 .thumb_func + 6576 .fpu fpv5-d16 + 6578 HAL_DMA_GetState: + 6579 .LVL236: + 6580 .LFB151: +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return hdma->State; + 6581 .loc 1 1731 1 is_stmt 1 view -0 + 6582 .cfi_startproc + ARM GAS /tmp/ccXv4DVv.s page 185 + + + 6583 @ args = 0, pretend = 0, frame = 0 + 6584 @ frame_needed = 0, uses_anonymous_args = 0 + 6585 @ link register save eliminated. +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6586 .loc 1 1732 3 view .LVU2085 +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6587 .loc 1 1732 14 is_stmt 0 view .LVU2086 + 6588 0000 90F83500 ldrb r0, [r0, #53] @ zero_extendqisi2 + 6589 .LVL237: +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6590 .loc 1 1733 1 view .LVU2087 + 6591 0004 7047 bx lr + 6592 .cfi_endproc + 6593 .LFE151: + 6595 .section .text.HAL_DMA_GetError,"ax",%progbits + 6596 .align 1 + 6597 .global HAL_DMA_GetError + 6598 .syntax unified + 6599 .thumb + 6600 .thumb_func + 6601 .fpu fpv5-d16 + 6603 HAL_DMA_GetError: + 6604 .LVL238: + 6605 .LFB152: +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** return hdma->ErrorCode; + 6606 .loc 1 1742 1 is_stmt 1 view -0 + 6607 .cfi_startproc + 6608 @ args = 0, pretend = 0, frame = 0 + 6609 @ frame_needed = 0, uses_anonymous_args = 0 + 6610 @ link register save eliminated. +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6611 .loc 1 1743 3 view .LVU2089 +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** } + 6612 .loc 1 1743 14 is_stmt 0 view .LVU2090 + 6613 0000 406D ldr r0, [r0, #84] + 6614 .LVL239: +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c **** + 6615 .loc 1 1744 1 view .LVU2091 + 6616 0002 7047 bx lr + 6617 .cfi_endproc + 6618 .LFE152: + 6620 .section .rodata.flagBitshiftOffset.0,"a" + 6621 .align 2 + 6622 .set .LANCHOR0,. + 0 + 6625 flagBitshiftOffset.0: + 6626 0000 00061016 .ascii "\000\006\020\026\000\006\020\026" + 6626 00061016 + 6627 .text + 6628 .Letext0: + 6629 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 6630 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 6631 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 6632 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 6633 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 6634 .file 7 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + 6635 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccXv4DVv.s page 186 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_dma.c + /tmp/ccXv4DVv.s:17 .text.DMA_SetConfig:0000000000000000 $t + /tmp/ccXv4DVv.s:24 .text.DMA_SetConfig:0000000000000000 DMA_SetConfig + /tmp/ccXv4DVv.s:386 .text.DMA_SetConfig:00000000000001a0 $d + /tmp/ccXv4DVv.s:395 .text.DMA_CalcBaseAndBitshift:0000000000000000 $t + /tmp/ccXv4DVv.s:401 .text.DMA_CalcBaseAndBitshift:0000000000000000 DMA_CalcBaseAndBitshift + /tmp/ccXv4DVv.s:552 .text.DMA_CalcBaseAndBitshift:00000000000000a0 $d + /tmp/ccXv4DVv.s:562 .text.DMA_CheckFifoParam:0000000000000000 $t + /tmp/ccXv4DVv.s:568 .text.DMA_CheckFifoParam:0000000000000000 DMA_CheckFifoParam + /tmp/ccXv4DVv.s:655 .text.DMA_CheckFifoParam:0000000000000052 $d + /tmp/ccXv4DVv.s:659 .text.DMA_CheckFifoParam:0000000000000056 $t + /tmp/ccXv4DVv.s:752 .text.DMA_CalcDMAMUXChannelBaseAndMask:0000000000000000 $t + /tmp/ccXv4DVv.s:758 .text.DMA_CalcDMAMUXChannelBaseAndMask:0000000000000000 DMA_CalcDMAMUXChannelBaseAndMask + /tmp/ccXv4DVv.s:889 .text.DMA_CalcDMAMUXChannelBaseAndMask:000000000000008c $d + /tmp/ccXv4DVv.s:902 .text.DMA_CalcDMAMUXRequestGenBaseAndMask:0000000000000000 $t + /tmp/ccXv4DVv.s:908 .text.DMA_CalcDMAMUXRequestGenBaseAndMask:0000000000000000 DMA_CalcDMAMUXRequestGenBaseAndMask + /tmp/ccXv4DVv.s:1009 .text.DMA_CalcDMAMUXRequestGenBaseAndMask:0000000000000064 $d + /tmp/ccXv4DVv.s:1019 .text.HAL_DMA_Init:0000000000000000 $t + /tmp/ccXv4DVv.s:1026 .text.HAL_DMA_Init:0000000000000000 HAL_DMA_Init + /tmp/ccXv4DVv.s:1300 .text.HAL_DMA_Init:0000000000000160 $d + /tmp/ccXv4DVv.s:1310 .text.HAL_DMA_Init:0000000000000178 $t + /tmp/ccXv4DVv.s:1774 .text.HAL_DMA_Init:0000000000000380 $d + /tmp/ccXv4DVv.s:1787 .text.HAL_DMA_DeInit:0000000000000000 $t + /tmp/ccXv4DVv.s:1794 .text.HAL_DMA_DeInit:0000000000000000 HAL_DMA_DeInit + /tmp/ccXv4DVv.s:2192 .text.HAL_DMA_DeInit:00000000000001c0 $d + /tmp/ccXv4DVv.s:2201 .text.HAL_DMA_Start:0000000000000000 $t + /tmp/ccXv4DVv.s:2208 .text.HAL_DMA_Start:0000000000000000 HAL_DMA_Start + /tmp/ccXv4DVv.s:2463 .text.HAL_DMA_Start:0000000000000140 $d + /tmp/ccXv4DVv.s:2469 .text.HAL_DMA_Start_IT:0000000000000000 $t + /tmp/ccXv4DVv.s:2476 .text.HAL_DMA_Start_IT:0000000000000000 HAL_DMA_Start_IT + /tmp/ccXv4DVv.s:2956 .text.HAL_DMA_Start_IT:000000000000028c $d + /tmp/ccXv4DVv.s:2963 .text.HAL_DMA_Abort:0000000000000000 $t + /tmp/ccXv4DVv.s:2970 .text.HAL_DMA_Abort:0000000000000000 HAL_DMA_Abort + /tmp/ccXv4DVv.s:3416 .text.HAL_DMA_Abort:000000000000025c $d + /tmp/ccXv4DVv.s:3423 .text.HAL_DMA_Abort:0000000000000268 $t + /tmp/ccXv4DVv.s:3582 .text.HAL_DMA_Abort:0000000000000334 $d + /tmp/ccXv4DVv.s:3589 .text.HAL_DMA_Abort_IT:0000000000000000 $t + /tmp/ccXv4DVv.s:3596 .text.HAL_DMA_Abort_IT:0000000000000000 HAL_DMA_Abort_IT + /tmp/ccXv4DVv.s:4056 .text.HAL_DMA_Abort_IT:0000000000000260 $d + /tmp/ccXv4DVv.s:4064 .text.HAL_DMA_PollForTransfer:0000000000000000 $t + /tmp/ccXv4DVv.s:4071 .text.HAL_DMA_PollForTransfer:0000000000000000 HAL_DMA_PollForTransfer + /tmp/ccXv4DVv.s:4314 .text.HAL_DMA_PollForTransfer:000000000000010c $d + /tmp/ccXv4DVv.s:4320 .text.HAL_DMA_PollForTransfer:0000000000000114 $t + /tmp/ccXv4DVv.s:4784 .text.HAL_DMA_PollForTransfer:00000000000003b0 $d + /tmp/ccXv4DVv.s:4790 .text.HAL_DMA_PollForTransfer:00000000000003bc $t + /tmp/ccXv4DVv.s:4890 .text.HAL_DMA_PollForTransfer:0000000000000448 $d + /tmp/ccXv4DVv.s:4896 .text.HAL_DMA_IRQHandler:0000000000000000 $t + /tmp/ccXv4DVv.s:4903 .text.HAL_DMA_IRQHandler:0000000000000000 HAL_DMA_IRQHandler + /tmp/ccXv4DVv.s:5283 .text.HAL_DMA_IRQHandler:0000000000000200 $d + /tmp/ccXv4DVv.s:5293 .text.HAL_DMA_IRQHandler:0000000000000220 $t + /tmp/ccXv4DVv.s:5770 .text.HAL_DMA_IRQHandler:0000000000000494 $d + /tmp/ccXv4DVv.s:5775 .text.HAL_DMA_IRQHandler:000000000000049c $t + /tmp/ccXv4DVv.s:6274 .text.HAL_DMA_IRQHandler:0000000000000730 $d + /tmp/ccXv4DVv.s:6280 .text.HAL_DMA_RegisterCallback:0000000000000000 $t + /tmp/ccXv4DVv.s:6287 .text.HAL_DMA_RegisterCallback:0000000000000000 HAL_DMA_RegisterCallback + /tmp/ccXv4DVv.s:6339 .text.HAL_DMA_RegisterCallback:000000000000002e $d + ARM GAS /tmp/ccXv4DVv.s page 187 + + + /tmp/ccXv4DVv.s:6345 .text.HAL_DMA_RegisterCallback:0000000000000034 $t + /tmp/ccXv4DVv.s:6420 .text.HAL_DMA_UnRegisterCallback:0000000000000000 $t + /tmp/ccXv4DVv.s:6427 .text.HAL_DMA_UnRegisterCallback:0000000000000000 HAL_DMA_UnRegisterCallback + /tmp/ccXv4DVv.s:6478 .text.HAL_DMA_UnRegisterCallback:0000000000000030 $d + /tmp/ccXv4DVv.s:6571 .text.HAL_DMA_GetState:0000000000000000 $t + /tmp/ccXv4DVv.s:6578 .text.HAL_DMA_GetState:0000000000000000 HAL_DMA_GetState + /tmp/ccXv4DVv.s:6596 .text.HAL_DMA_GetError:0000000000000000 $t + /tmp/ccXv4DVv.s:6603 .text.HAL_DMA_GetError:0000000000000000 HAL_DMA_GetError + /tmp/ccXv4DVv.s:6621 .rodata.flagBitshiftOffset.0:0000000000000000 $d + /tmp/ccXv4DVv.s:6625 .rodata.flagBitshiftOffset.0:0000000000000000 flagBitshiftOffset.0 + /tmp/ccXv4DVv.s:6485 .text.HAL_DMA_UnRegisterCallback:0000000000000037 $d + /tmp/ccXv4DVv.s:6485 .text.HAL_DMA_UnRegisterCallback:0000000000000038 $t + +UNDEFINED SYMBOLS +HAL_GetTick +SystemCoreClock diff --git a/build/stm32h7xx_hal_dma.o b/build/stm32h7xx_hal_dma.o new file mode 100644 index 0000000..0a41cd2 Binary files /dev/null and b/build/stm32h7xx_hal_dma.o differ diff --git a/build/stm32h7xx_hal_dma_ex.d b/build/stm32h7xx_hal_dma_ex.d new file mode 100644 index 0000000..162d08a --- /dev/null +++ b/build/stm32h7xx_hal_dma_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_dma_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_dma_ex.lst b/build/stm32h7xx_hal_dma_ex.lst new file mode 100644 index 0000000..5866b4f --- /dev/null +++ b/build/stm32h7xx_hal_dma_ex.lst @@ -0,0 +1,3376 @@ +ARM GAS /tmp/ccAxWhFC.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_dma_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.DMA_MultiBufferSetConfig,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 DMA_MultiBufferSetConfig: + 25 .LVL0: + 26 .LFB149: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @file stm32h7xx_hal_dma_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief DMA Extension HAL module driver + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * functionalities of the DMA Extension peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + Extended features functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** @verbatim + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ============================================================================== + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ##### How to use this driver ##### + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** [..] + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** The DMA Extension HAL driver can be used as follows: + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator func + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can t + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** to respectively enable/disable the request generator. + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called fro + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler . + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** As only one interrupt line is available for all DMAMUX channels and request generators , HAL + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** called with, as parameter, the appropriate DMA handle as many as used DMAs in the user proje + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + ARM GAS /tmp/ccAxWhFC.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** -@- In Multi (Double) buffer mode, it is possible to update the base address for + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** -@- Multi (Double) buffer mode is possible with DMA and BDMA instances. + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** @endverbatim + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ****************************************************************************** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @attention + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * All rights reserved.

+ 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the "License"; You may not use this file except in compliance with the + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * License. You may obtain a copy of the License at: + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * opensource.org/licenses/BSD-3-Clause + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ****************************************************************************** + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Includes ------------------------------------------------------------------*/ + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** #include "stm32h7xx_hal.h" + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @{ + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** @defgroup DMAEx DMAEx + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief DMA Extended HAL module driver + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @{ + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** #ifdef HAL_DMA_MODULE_ENABLED + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Private types -------------------------------------------------------------*/ + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Private variables ---------------------------------------------------------*/ + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Private Constants ---------------------------------------------------------*/ + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Private macros ------------------------------------------------------------*/ + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Private functions ---------------------------------------------------------*/ + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Private_Functions + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @{ + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddr + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @} + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Exported_Functions + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @{ + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Exported_Functions_Group1 + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + ARM GAS /tmp/ccAxWhFC.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** @verbatim + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** =============================================================================== + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ##### Extended features functions ##### + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** =============================================================================== + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** [..] This section provides functions allowing to: + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Configure the source, destination address and data length and + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** Start MultiBuffer DMA transfer + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Configure the source, destination address and data length and + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** Start MultiBuffer DMA transfer with interrupt + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Change on the fly the memory0 or memory1 address. + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator f + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator ca + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** to respectively enable/disable the request generator. + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** @endverbatim + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @{ + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Starts the multi_buffer DMA Transfer. + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param SrcAddress: The source memory Buffer address + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param DstAddress: The destination memory Buffer address + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param DataLength: The length of data to be transferred from source to destination + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Memory-to-memory transfer not supported in double buffering mode */ + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process Locked */ + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(HAL_DMA_STATE_READY == hdma->State) + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Change DMA peripheral state */ + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->State = HAL_DMA_STATE_BUSY; + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Initialize the error code */ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the Double buffer mode */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Calculate the interrupt clear flag register (IFCR) base address */ + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear all flags */ + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else /* BDMA instance(s) */ + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the Double buffer mode */ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Calculate the interrupt clear flag register (IFCR) base address */ + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear all flags */ + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure the source, destination address and the data length */ + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear the DMAMUX synchro overrun flag */ + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->DMAmuxRequestGen != 0U) + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear the DMAMUX request generator overrun flag */ + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the peripheral */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_DMA_ENABLE(hdma); + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the error code to busy */ + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Return error status */ + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + ARM GAS /tmp/ccAxWhFC.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return status; + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param SrcAddress: The source memory Buffer address + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param DstAddress: The destination memory Buffer address + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param DataLength: The length of data to be transferred from source to destination + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint3 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Memory-to-memory transfer not supported in double buffering mode */ + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process locked */ + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(HAL_DMA_STATE_READY == hdma->State) + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Change DMA peripheral state */ + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->State = HAL_DMA_STATE_BUSY; + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Initialize the error code */ + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the Double buffer mode */ + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Calculate the interrupt clear flag register (IFCR) base address */ + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear all flags */ + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else /* BDMA instance(s) */ + ARM GAS /tmp/ccAxWhFC.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the Double buffer mode */ + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Calculate the interrupt clear flag register (IFCR) base address */ + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear all flags */ + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure the source, destination address and the data length */ + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear the DMAMUX synchro overrun flag */ + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->DMAmuxRequestGen != 0U) + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear the DMAMUX request generator overrun flag */ + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable Common interrupts*/ + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /*Enable Half Transfer IT if corresponding Callback is set*/ + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else /* BDMA instance(s) */ + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable Common interrupts*/ + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /*Enable Half Transfer IT if corresponding Callback is set*/ + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check if DMAMUX Synchronization is enabled*/ + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + ARM GAS /tmp/ccAxWhFC.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable DMAMUX sync overrun IT*/ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->DMAmuxRequestGen != 0U) + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* enable the request gen overrun IT*/ + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the peripheral */ + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_DMA_ENABLE(hdma); + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the error code to busy */ + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Return error status */ + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return status; + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Change the memory0 or memory1 address on the fly. + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param Address: The new address + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param memory: the memory to be changed, This parameter can be one of + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the following values: + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * MEMORY0 / + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * MEMORY1 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @note The MEMORY0 address can be changed only when the current transfer use + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * MEMORY1 and the MEMORY1 address can be changed only when the current + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * transfer use MEMORY0. + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryT + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(memory == MEMORY0) + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* change the memory0 address */ + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address; + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* change the memory1 address */ + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address; + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else /* BDMA instance(s) */ + ARM GAS /tmp/ccAxWhFC.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(memory == MEMORY0) + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* change the memory0 address */ + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address; + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* change the memory1 address */ + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address; + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_OK; + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance). + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchroniza + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pS + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** uint32_t syncSignalID = 0; + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** uint32_t syncPolarity = 0; + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(pSyncConfig->SyncEnable == ENABLE) + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity)); + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** syncSignalID = pSyncConfig->SyncSignalID; + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** syncPolarity = pSyncConfig->SyncPolarity; + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /*Check if the DMA state is ready */ + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->State == HAL_DMA_STATE_READY) + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process Locked */ + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Disable the synchronization and event generation before applying a new config */ + ARM GAS /tmp/ccAxWhFC.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE)); + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** MODIFY_REG( hdma->DMAmuxChannel->CCR, \ + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (~DMAMUX_CxCR_DMAREQ_ID) , \ + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \ + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process Locked */ + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_UNLOCK(hdma); + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_OK; + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the error code to busy */ + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Return error status */ + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance). + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * contains the request generator parameters. + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestG + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status; + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_DMA_StateTypeDef temp_state = hdma->State; + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* check if the DMA state is ready + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** and DMA is using a DMAMUX request generator block + ARM GAS /tmp/ccAxWhFC.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->DMAmuxRequestGen == 0U) + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the error code to busy */ + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* error status */ + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_ + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process Locked */ + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the request generator new parameters */ + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GN + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process Locked */ + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __HAL_UNLOCK(hdma); + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_OK; + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Set the error code to busy */ + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* error status */ + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return status; + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance). + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* check if the DMA state is ready + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** and DMA is using a DMAMUX request generator block */ + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Enable the request generator*/ + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_OK; + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + ARM GAS /tmp/ccAxWhFC.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance). + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* check if the DMA state is ready + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** and DMA is using a DMAMUX request generator block */ + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Disable the request generator*/ + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_OK; + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Handles DMAMUX interrupt request. + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval None + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check for DMAMUX Synchronization overrun */ + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Disable the synchro overrun interrupt */ + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear the DMAMUX synchro overrun flag */ + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Update error code */ + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->XferErrorCallback != NULL) + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Transfer error callback */ + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->XferErrorCallback(hdma); + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + ARM GAS /tmp/ccAxWhFC.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->DMAmuxRequestGen != 0) + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Disable the request gen overrun interrupt */ + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Clear the DMAMUX request generator overrun flag */ + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Update error code */ + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(hdma->XferErrorCallback != NULL) + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Transfer error callback */ + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** hdma->XferErrorCallback(hdma); + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @} + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @} + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Private_Functions + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @{ + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /** + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @brief Set the DMA Transfer parameter. + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param SrcAddress: The source memory Buffer address + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param DstAddress: The destination memory Buffer address + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @param DataLength: The length of data to be transferred from source to destination + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** * @retval HAL status + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** */ + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddr + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 28 .loc 1 650 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 650 1 is_stmt 0 view .LVU1 + 34 0000 70B4 push {r4, r5, r6} + 35 .LCFI0: + ARM GAS /tmp/ccAxWhFC.s page 13 + + + 36 .cfi_def_cfa_offset 12 + 37 .cfi_offset 4, -12 + 38 .cfi_offset 5, -8 + 39 .cfi_offset 6, -4 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 40 .loc 1 651 3 is_stmt 1 view .LVU2 + 41 .loc 1 651 6 is_stmt 0 view .LVU3 + 42 0002 0468 ldr r4, [r0] + 43 0004 264E ldr r6, .L11 + 44 0006 274D ldr r5, .L11+4 + 45 0008 AC42 cmp r4, r5 + 46 000a 18BF it ne + 47 000c B442 cmpne r4, r6 + 48 000e 33D0 beq .L2 + 49 .loc 1 651 6 discriminator 2 view .LVU4 + 50 0010 1835 adds r5, r5, #24 + 51 0012 AC42 cmp r4, r5 + 52 0014 30D0 beq .L2 + 53 .loc 1 651 6 discriminator 4 view .LVU5 + 54 0016 1835 adds r5, r5, #24 + 55 0018 AC42 cmp r4, r5 + 56 001a 2DD0 beq .L2 + 57 .loc 1 651 6 discriminator 6 view .LVU6 + 58 001c 1835 adds r5, r5, #24 + 59 001e AC42 cmp r4, r5 + 60 0020 2AD0 beq .L2 + 61 .loc 1 651 6 discriminator 8 view .LVU7 + 62 0022 1835 adds r5, r5, #24 + 63 0024 AC42 cmp r4, r5 + 64 0026 27D0 beq .L2 + 65 .loc 1 651 6 discriminator 10 view .LVU8 + 66 0028 1835 adds r5, r5, #24 + 67 002a AC42 cmp r4, r5 + 68 002c 24D0 beq .L2 + 69 .loc 1 651 6 discriminator 12 view .LVU9 + 70 002e 1835 adds r5, r5, #24 + 71 0030 AC42 cmp r4, r5 + 72 0032 21D0 beq .L2 + 73 .loc 1 651 6 discriminator 14 view .LVU10 + 74 0034 05F55675 add r5, r5, #856 + 75 0038 AC42 cmp r4, r5 + 76 003a 1DD0 beq .L2 + 77 .loc 1 651 6 discriminator 16 view .LVU11 + 78 003c 1835 adds r5, r5, #24 + 79 003e AC42 cmp r4, r5 + 80 0040 1AD0 beq .L2 + 81 .loc 1 651 6 discriminator 18 view .LVU12 + 82 0042 1835 adds r5, r5, #24 + 83 0044 AC42 cmp r4, r5 + 84 0046 17D0 beq .L2 + 85 .loc 1 651 6 discriminator 20 view .LVU13 + 86 0048 1835 adds r5, r5, #24 + 87 004a AC42 cmp r4, r5 + 88 004c 14D0 beq .L2 + 89 .loc 1 651 6 discriminator 22 view .LVU14 + 90 004e 1835 adds r5, r5, #24 + 91 0050 AC42 cmp r4, r5 + ARM GAS /tmp/ccAxWhFC.s page 14 + + + 92 0052 11D0 beq .L2 + 93 .loc 1 651 6 discriminator 24 view .LVU15 + 94 0054 1835 adds r5, r5, #24 + 95 0056 AC42 cmp r4, r5 + 96 0058 0ED0 beq .L2 + 97 .loc 1 651 6 discriminator 26 view .LVU16 + 98 005a 1835 adds r5, r5, #24 + 99 005c AC42 cmp r4, r5 + 100 005e 0BD0 beq .L2 + 101 .loc 1 651 6 discriminator 28 view .LVU17 + 102 0060 1835 adds r5, r5, #24 + 103 0062 AC42 cmp r4, r5 + 104 0064 08D0 beq .L2 + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream data length */ + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Peripheral to Memory */ + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream source address */ + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Memory to Peripheral */ + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream source address */ + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else /* BDMA instance(s) */ + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream data length */ + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + 105 .loc 1 678 5 is_stmt 1 view .LVU18 + 106 .loc 1 678 55 is_stmt 0 view .LVU19 + 107 0066 6360 str r3, [r4, #4] + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Peripheral to Memory */ + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 108 .loc 1 681 5 is_stmt 1 view .LVU20 + 109 .loc 1 681 19 is_stmt 0 view .LVU21 + 110 0068 8368 ldr r3, [r0, #8] + 111 .LVL1: + 112 .loc 1 681 7 view .LVU22 + 113 006a 402B cmp r3, #64 + 114 006c 13D0 beq .L9 + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 15 + + + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream source address */ + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Memory to Peripheral */ + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** else + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream source address */ + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + 115 .loc 1 693 7 is_stmt 1 view .LVU23 + 116 .loc 1 693 38 is_stmt 0 view .LVU24 + 117 006e 0368 ldr r3, [r0] + 118 .loc 1 693 56 view .LVU25 + 119 0070 9960 str r1, [r3, #8] + 120 .LVL2: + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + 121 .loc 1 696 7 is_stmt 1 view .LVU26 + 122 .loc 1 696 38 is_stmt 0 view .LVU27 + 123 0072 0368 ldr r3, [r0] + 124 .loc 1 696 57 view .LVU28 + 125 0074 DA60 str r2, [r3, #12] + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 126 .loc 1 699 1 view .LVU29 + 127 0076 07E0 b .L1 + 128 .LVL3: + 129 .L2: + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 130 .loc 1 654 5 is_stmt 1 view .LVU30 + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 131 .loc 1 654 52 is_stmt 0 view .LVU31 + 132 0078 6360 str r3, [r4, #4] + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 133 .loc 1 657 5 is_stmt 1 view .LVU32 + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 134 .loc 1 657 19 is_stmt 0 view .LVU33 + 135 007a 8368 ldr r3, [r0, #8] + 136 .LVL4: + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 137 .loc 1 657 7 view .LVU34 + 138 007c 402B cmp r3, #64 + 139 007e 05D0 beq .L10 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 140 .loc 1 669 7 is_stmt 1 view .LVU35 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 141 .loc 1 669 36 is_stmt 0 view .LVU36 + 142 0080 0368 ldr r3, [r0] + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 143 .loc 1 669 53 view .LVU37 + 144 0082 9960 str r1, [r3, #8] + 145 .LVL5: + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 146 .loc 1 672 7 is_stmt 1 view .LVU38 + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 147 .loc 1 672 36 is_stmt 0 view .LVU39 + ARM GAS /tmp/ccAxWhFC.s page 16 + + + 148 0084 0368 ldr r3, [r0] + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 149 .loc 1 672 54 view .LVU40 + 150 0086 DA60 str r2, [r3, #12] + 151 .L1: + 152 .loc 1 699 1 view .LVU41 + 153 0088 70BC pop {r4, r5, r6} + 154 .LCFI1: + 155 .cfi_remember_state + 156 .cfi_restore 6 + 157 .cfi_restore 5 + 158 .cfi_restore 4 + 159 .cfi_def_cfa_offset 0 + 160 008a 7047 bx lr + 161 .LVL6: + 162 .L10: + 163 .LCFI2: + 164 .cfi_restore_state + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 165 .loc 1 660 7 is_stmt 1 view .LVU42 + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 166 .loc 1 660 36 is_stmt 0 view .LVU43 + 167 008c 0368 ldr r3, [r0] + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 168 .loc 1 660 53 view .LVU44 + 169 008e 9A60 str r2, [r3, #8] + 170 .LVL7: + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 171 .loc 1 663 7 is_stmt 1 view .LVU45 + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 172 .loc 1 663 36 is_stmt 0 view .LVU46 + 173 0090 0368 ldr r3, [r0] + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 174 .loc 1 663 54 view .LVU47 + 175 0092 D960 str r1, [r3, #12] + 176 0094 F8E7 b .L1 + 177 .LVL8: + 178 .L9: + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 179 .loc 1 684 7 is_stmt 1 view .LVU48 + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 180 .loc 1 684 38 is_stmt 0 view .LVU49 + 181 0096 0368 ldr r3, [r0] + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 182 .loc 1 684 56 view .LVU50 + 183 0098 9A60 str r2, [r3, #8] + 184 .LVL9: + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 185 .loc 1 687 7 is_stmt 1 view .LVU51 + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 186 .loc 1 687 38 is_stmt 0 view .LVU52 + 187 009a 0368 ldr r3, [r0] + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 188 .loc 1 687 57 view .LVU53 + 189 009c D960 str r1, [r3, #12] + 190 009e F3E7 b .L1 + 191 .L12: + ARM GAS /tmp/ccAxWhFC.s page 17 + + + 192 .align 2 + 193 .L11: + 194 00a0 10000240 .word 1073872912 + 195 00a4 28000240 .word 1073872936 + 196 .cfi_endproc + 197 .LFE149: + 199 .section .text.HAL_DMAEx_MultiBufferStart,"ax",%progbits + 200 .align 1 + 201 .global HAL_DMAEx_MultiBufferStart + 202 .syntax unified + 203 .thumb + 204 .thumb_func + 205 .fpu fpv5-d16 + 207 HAL_DMAEx_MultiBufferStart: + 208 .LVL10: + 209 .LFB141: + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 210 .loc 1 122 1 is_stmt 1 view -0 + 211 .cfi_startproc + 212 @ args = 4, pretend = 0, frame = 0 + 213 @ frame_needed = 0, uses_anonymous_args = 0 + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 214 .loc 1 122 1 is_stmt 0 view .LVU55 + 215 0000 70B5 push {r4, r5, r6, lr} + 216 .LCFI3: + 217 .cfi_def_cfa_offset 16 + 218 .cfi_offset 4, -16 + 219 .cfi_offset 5, -12 + 220 .cfi_offset 6, -8 + 221 .cfi_offset 14, -4 + 222 0002 0446 mov r4, r0 + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 223 .loc 1 123 3 is_stmt 1 view .LVU56 + 224 .LVL11: + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 225 .loc 1 124 3 view .LVU57 + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 226 .loc 1 127 3 view .LVU58 + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 227 .loc 1 128 3 view .LVU59 + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 228 .loc 1 131 3 view .LVU60 + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 229 .loc 1 131 17 is_stmt 0 view .LVU61 + 230 0004 8068 ldr r0, [r0, #8] + 231 .LVL12: + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 232 .loc 1 131 6 view .LVU62 + 233 0006 8028 cmp r0, #128 + 234 0008 11D0 beq .L25 + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 235 .loc 1 139 5 is_stmt 1 view .LVU63 + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 236 .loc 1 139 5 view .LVU64 + 237 000a 94F83400 ldrb r0, [r4, #52] @ zero_extendqisi2 + 238 000e 0128 cmp r0, #1 + 239 0010 00F0F980 beq .L23 + ARM GAS /tmp/ccAxWhFC.s page 18 + + + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 240 .loc 1 139 5 discriminator 2 view .LVU65 + 241 0014 0120 movs r0, #1 + 242 0016 84F83400 strb r0, [r4, #52] + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 243 .loc 1 139 5 discriminator 2 view .LVU66 + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 244 .loc 1 141 5 discriminator 2 view .LVU67 + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 245 .loc 1 141 35 is_stmt 0 discriminator 2 view .LVU68 + 246 001a 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 247 001e C0B2 uxtb r0, r0 + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 248 .loc 1 141 7 discriminator 2 view .LVU69 + 249 0020 0128 cmp r0, #1 + 250 0022 09D0 beq .L26 + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 251 .loc 1 199 7 is_stmt 1 view .LVU70 + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 252 .loc 1 199 23 is_stmt 0 view .LVU71 + 253 0024 4FF40063 mov r3, #2048 + 254 .LVL13: + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 255 .loc 1 199 23 view .LVU72 + 256 0028 6365 str r3, [r4, #84] + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 257 .loc 1 202 7 is_stmt 1 view .LVU73 + 258 .LVL14: + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 259 .loc 1 202 14 is_stmt 0 view .LVU74 + 260 002a 0120 movs r0, #1 + 261 .LVL15: + 262 .L15: + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 263 .loc 1 206 1 view .LVU75 + 264 002c 70BD pop {r4, r5, r6, pc} + 265 .LVL16: + 266 .L25: + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 267 .loc 1 133 5 is_stmt 1 view .LVU76 + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 268 .loc 1 133 21 is_stmt 0 view .LVU77 + 269 002e 4FF48073 mov r3, #256 + 270 .LVL17: + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** status = HAL_ERROR; + 271 .loc 1 133 21 view .LVU78 + 272 0032 6365 str r3, [r4, #84] + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 273 .loc 1 134 5 is_stmt 1 view .LVU79 + 274 .LVL18: + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 275 .loc 1 134 12 is_stmt 0 view .LVU80 + 276 0034 0120 movs r0, #1 + 277 0036 F9E7 b .L15 + 278 .LVL19: + 279 .L26: + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 19 + + + 280 .loc 1 144 7 is_stmt 1 view .LVU81 + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 281 .loc 1 144 19 is_stmt 0 view .LVU82 + 282 0038 0220 movs r0, #2 + 283 003a 84F83500 strb r0, [r4, #53] + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 284 .loc 1 147 7 is_stmt 1 view .LVU83 + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 285 .loc 1 147 23 is_stmt 0 view .LVU84 + 286 003e 0020 movs r0, #0 + 287 0040 6065 str r0, [r4, #84] + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 288 .loc 1 149 7 is_stmt 1 view .LVU85 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 289 .loc 1 149 10 is_stmt 0 view .LVU86 + 290 0042 2068 ldr r0, [r4] + 291 0044 714E ldr r6, .L27 + 292 0046 724D ldr r5, .L27+4 + 293 0048 A842 cmp r0, r5 + 294 004a 18BF it ne + 295 004c B042 cmpne r0, r6 + 296 004e 39D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 297 .loc 1 149 10 discriminator 2 view .LVU87 + 298 0050 1835 adds r5, r5, #24 + 299 0052 A842 cmp r0, r5 + 300 0054 36D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 301 .loc 1 149 10 discriminator 4 view .LVU88 + 302 0056 1835 adds r5, r5, #24 + 303 0058 A842 cmp r0, r5 + 304 005a 33D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 305 .loc 1 149 10 discriminator 6 view .LVU89 + 306 005c 1835 adds r5, r5, #24 + 307 005e A842 cmp r0, r5 + 308 0060 30D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 309 .loc 1 149 10 discriminator 8 view .LVU90 + 310 0062 1835 adds r5, r5, #24 + 311 0064 A842 cmp r0, r5 + 312 0066 2DD0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 313 .loc 1 149 10 discriminator 10 view .LVU91 + 314 0068 1835 adds r5, r5, #24 + 315 006a A842 cmp r0, r5 + 316 006c 2AD0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 317 .loc 1 149 10 discriminator 12 view .LVU92 + 318 006e 1835 adds r5, r5, #24 + 319 0070 A842 cmp r0, r5 + 320 0072 27D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 321 .loc 1 149 10 discriminator 14 view .LVU93 + 322 0074 05F55675 add r5, r5, #856 + 323 0078 A842 cmp r0, r5 + 324 007a 23D0 beq .L17 + ARM GAS /tmp/ccAxWhFC.s page 20 + + + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 325 .loc 1 149 10 discriminator 16 view .LVU94 + 326 007c 1835 adds r5, r5, #24 + 327 007e A842 cmp r0, r5 + 328 0080 20D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 329 .loc 1 149 10 discriminator 18 view .LVU95 + 330 0082 1835 adds r5, r5, #24 + 331 0084 A842 cmp r0, r5 + 332 0086 1DD0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 333 .loc 1 149 10 discriminator 20 view .LVU96 + 334 0088 1835 adds r5, r5, #24 + 335 008a A842 cmp r0, r5 + 336 008c 1AD0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 337 .loc 1 149 10 discriminator 22 view .LVU97 + 338 008e 1835 adds r5, r5, #24 + 339 0090 A842 cmp r0, r5 + 340 0092 17D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 341 .loc 1 149 10 discriminator 24 view .LVU98 + 342 0094 1835 adds r5, r5, #24 + 343 0096 A842 cmp r0, r5 + 344 0098 14D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 345 .loc 1 149 10 discriminator 26 view .LVU99 + 346 009a 1835 adds r5, r5, #24 + 347 009c A842 cmp r0, r5 + 348 009e 11D0 beq .L17 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 349 .loc 1 149 10 discriminator 28 view .LVU100 + 350 00a0 1835 adds r5, r5, #24 + 351 00a2 A842 cmp r0, r5 + 352 00a4 0ED0 beq .L17 + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 353 .loc 1 166 9 is_stmt 1 view .LVU101 + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 354 .loc 1 166 57 is_stmt 0 view .LVU102 + 355 00a6 0668 ldr r6, [r0] + 356 00a8 48F22005 movw r5, #32800 + 357 00ac 3543 orrs r5, r5, r6 + 358 00ae 0560 str r5, [r0] + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 359 .loc 1 169 9 is_stmt 1 view .LVU103 + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 360 .loc 1 169 40 is_stmt 0 view .LVU104 + 361 00b0 2068 ldr r0, [r4] + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 362 .loc 1 169 59 view .LVU105 + 363 00b2 0361 str r3, [r0, #16] + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 364 .loc 1 172 9 is_stmt 1 view .LVU106 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 365 .loc 1 172 56 is_stmt 0 view .LVU107 + 366 00b4 A56D ldr r5, [r4, #88] + 367 .LVL20: + ARM GAS /tmp/ccAxWhFC.s page 21 + + + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 368 .loc 1 175 9 is_stmt 1 view .LVU108 + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 369 .loc 1 175 53 is_stmt 0 view .LVU109 + 370 00b6 E36D ldr r3, [r4, #92] + 371 .LVL21: + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 372 .loc 1 175 67 view .LVU110 + 373 00b8 03F01F00 and r0, r3, #31 + 374 .LVL22: + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 375 .loc 1 175 45 view .LVU111 + 376 00bc 0123 movs r3, #1 + 377 00be 8340 lsls r3, r3, r0 + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 378 .loc 1 175 27 view .LVU112 + 379 00c0 6B60 str r3, [r5, #4] + 380 00c2 0CE0 b .L18 + 381 .LVL23: + 382 .L17: + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 383 .loc 1 152 9 is_stmt 1 view .LVU113 + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 384 .loc 1 152 54 is_stmt 0 view .LVU114 + 385 00c4 0568 ldr r5, [r0] + 386 00c6 45F48025 orr r5, r5, #262144 + 387 00ca 0560 str r5, [r0] + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 388 .loc 1 155 9 is_stmt 1 view .LVU115 + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 389 .loc 1 155 38 is_stmt 0 view .LVU116 + 390 00cc 2068 ldr r0, [r4] + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 391 .loc 1 155 56 view .LVU117 + 392 00ce 0361 str r3, [r0, #16] + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 393 .loc 1 158 9 is_stmt 1 view .LVU118 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 394 .loc 1 158 56 is_stmt 0 view .LVU119 + 395 00d0 A56D ldr r5, [r4, #88] + 396 .LVL24: + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 397 .loc 1 161 9 is_stmt 1 view .LVU120 + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 398 .loc 1 161 44 is_stmt 0 view .LVU121 + 399 00d2 E36D ldr r3, [r4, #92] + 400 .LVL25: + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 401 .loc 1 161 58 view .LVU122 + 402 00d4 03F01F00 and r0, r3, #31 + 403 .LVL26: + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 404 .loc 1 161 36 view .LVU123 + 405 00d8 3F23 movs r3, #63 + 406 00da 8340 lsls r3, r3, r0 + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 407 .loc 1 161 27 view .LVU124 + ARM GAS /tmp/ccAxWhFC.s page 22 + + + 408 00dc AB60 str r3, [r5, #8] + 409 .LVL27: + 410 .L18: + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 411 .loc 1 178 7 is_stmt 1 view .LVU125 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 412 .loc 1 178 10 is_stmt 0 view .LVU126 + 413 00de 2368 ldr r3, [r4] + 414 00e0 4A4D ldr r5, .L27 + 415 00e2 4B48 ldr r0, .L27+4 + 416 00e4 8342 cmp r3, r0 + 417 00e6 18BF it ne + 418 00e8 AB42 cmpne r3, r5 + 419 00ea 42D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 420 .loc 1 178 10 discriminator 2 view .LVU127 + 421 00ec 1830 adds r0, r0, #24 + 422 00ee 8342 cmp r3, r0 + 423 00f0 3FD0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 424 .loc 1 178 10 discriminator 4 view .LVU128 + 425 00f2 1830 adds r0, r0, #24 + 426 00f4 8342 cmp r3, r0 + 427 00f6 3CD0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 428 .loc 1 178 10 discriminator 6 view .LVU129 + 429 00f8 1830 adds r0, r0, #24 + 430 00fa 8342 cmp r3, r0 + 431 00fc 39D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 432 .loc 1 178 10 discriminator 8 view .LVU130 + 433 00fe 1830 adds r0, r0, #24 + 434 0100 8342 cmp r3, r0 + 435 0102 36D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 436 .loc 1 178 10 discriminator 10 view .LVU131 + 437 0104 1830 adds r0, r0, #24 + 438 0106 8342 cmp r3, r0 + 439 0108 33D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 440 .loc 1 178 10 discriminator 12 view .LVU132 + 441 010a 1830 adds r0, r0, #24 + 442 010c 8342 cmp r3, r0 + 443 010e 30D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 444 .loc 1 178 10 discriminator 14 view .LVU133 + 445 0110 00F55670 add r0, r0, #856 + 446 0114 8342 cmp r3, r0 + 447 0116 2CD0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 448 .loc 1 178 10 discriminator 16 view .LVU134 + 449 0118 1830 adds r0, r0, #24 + 450 011a 8342 cmp r3, r0 + 451 011c 29D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 452 .loc 1 178 10 discriminator 18 view .LVU135 + 453 011e 1830 adds r0, r0, #24 + ARM GAS /tmp/ccAxWhFC.s page 23 + + + 454 0120 8342 cmp r3, r0 + 455 0122 26D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 456 .loc 1 178 10 discriminator 20 view .LVU136 + 457 0124 1830 adds r0, r0, #24 + 458 0126 8342 cmp r3, r0 + 459 0128 23D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 460 .loc 1 178 10 discriminator 22 view .LVU137 + 461 012a 1830 adds r0, r0, #24 + 462 012c 8342 cmp r3, r0 + 463 012e 20D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 464 .loc 1 178 10 discriminator 24 view .LVU138 + 465 0130 1830 adds r0, r0, #24 + 466 0132 8342 cmp r3, r0 + 467 0134 1DD0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 468 .loc 1 178 10 discriminator 26 view .LVU139 + 469 0136 1830 adds r0, r0, #24 + 470 0138 8342 cmp r3, r0 + 471 013a 1AD0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 472 .loc 1 178 10 discriminator 28 view .LVU140 + 473 013c 1830 adds r0, r0, #24 + 474 013e 8342 cmp r3, r0 + 475 0140 17D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 476 .loc 1 178 10 discriminator 30 view .LVU141 + 477 0142 3448 ldr r0, .L27+8 + 478 0144 8342 cmp r3, r0 + 479 0146 14D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 480 .loc 1 178 10 discriminator 32 view .LVU142 + 481 0148 1430 adds r0, r0, #20 + 482 014a 8342 cmp r3, r0 + 483 014c 11D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 484 .loc 1 178 10 discriminator 34 view .LVU143 + 485 014e 1430 adds r0, r0, #20 + 486 0150 8342 cmp r3, r0 + 487 0152 0ED0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 488 .loc 1 178 10 discriminator 36 view .LVU144 + 489 0154 1430 adds r0, r0, #20 + 490 0156 8342 cmp r3, r0 + 491 0158 0BD0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 492 .loc 1 178 10 discriminator 38 view .LVU145 + 493 015a 1430 adds r0, r0, #20 + 494 015c 8342 cmp r3, r0 + 495 015e 08D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 496 .loc 1 178 10 discriminator 40 view .LVU146 + 497 0160 1430 adds r0, r0, #20 + 498 0162 8342 cmp r3, r0 + 499 0164 05D0 beq .L19 + ARM GAS /tmp/ccAxWhFC.s page 24 + + + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 500 .loc 1 178 10 discriminator 42 view .LVU147 + 501 0166 1430 adds r0, r0, #20 + 502 0168 8342 cmp r3, r0 + 503 016a 02D0 beq .L19 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 504 .loc 1 178 10 discriminator 44 view .LVU148 + 505 016c 1430 adds r0, r0, #20 + 506 016e 8342 cmp r3, r0 + 507 0170 0BD1 bne .L20 + 508 .L19: + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 509 .loc 1 181 9 is_stmt 1 view .LVU149 + 510 0172 049B ldr r3, [sp, #16] + 511 0174 2046 mov r0, r4 + 512 0176 FFF7FEFF bl DMA_MultiBufferSetConfig + 513 .LVL28: + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 514 .loc 1 184 9 view .LVU150 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 515 .loc 1 184 13 is_stmt 0 view .LVU151 + 516 017a 636E ldr r3, [r4, #100] + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 517 .loc 1 184 46 view .LVU152 + 518 017c A26E ldr r2, [r4, #104] + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 519 .loc 1 184 40 view .LVU153 + 520 017e 5A60 str r2, [r3, #4] + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 521 .loc 1 186 9 is_stmt 1 view .LVU154 + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 522 .loc 1 186 16 is_stmt 0 view .LVU155 + 523 0180 E36E ldr r3, [r4, #108] + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 524 .loc 1 186 11 view .LVU156 + 525 0182 13B1 cbz r3, .L20 + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 526 .loc 1 189 11 is_stmt 1 view .LVU157 + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 527 .loc 1 189 15 is_stmt 0 view .LVU158 + 528 0184 236F ldr r3, [r4, #112] + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 529 .loc 1 189 53 view .LVU159 + 530 0186 626F ldr r2, [r4, #116] + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 531 .loc 1 189 47 view .LVU160 + 532 0188 5A60 str r2, [r3, #4] + 533 .L20: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 534 .loc 1 194 7 is_stmt 1 view .LVU161 + 535 018a 2368 ldr r3, [r4] + 536 018c 1F49 ldr r1, .L27 + 537 018e 204A ldr r2, .L27+4 + 538 0190 9342 cmp r3, r2 + 539 0192 18BF it ne + 540 0194 8B42 cmpne r3, r1 + 541 0196 30D0 beq .L21 + ARM GAS /tmp/ccAxWhFC.s page 25 + + + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 542 .loc 1 194 7 is_stmt 0 discriminator 2 view .LVU162 + 543 0198 1832 adds r2, r2, #24 + 544 019a 9342 cmp r3, r2 + 545 019c 2DD0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 546 .loc 1 194 7 discriminator 4 view .LVU163 + 547 019e 1832 adds r2, r2, #24 + 548 01a0 9342 cmp r3, r2 + 549 01a2 2AD0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 550 .loc 1 194 7 discriminator 6 view .LVU164 + 551 01a4 1832 adds r2, r2, #24 + 552 01a6 9342 cmp r3, r2 + 553 01a8 27D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 554 .loc 1 194 7 discriminator 8 view .LVU165 + 555 01aa 1832 adds r2, r2, #24 + 556 01ac 9342 cmp r3, r2 + 557 01ae 24D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 558 .loc 1 194 7 discriminator 10 view .LVU166 + 559 01b0 1832 adds r2, r2, #24 + 560 01b2 9342 cmp r3, r2 + 561 01b4 21D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 562 .loc 1 194 7 discriminator 12 view .LVU167 + 563 01b6 1832 adds r2, r2, #24 + 564 01b8 9342 cmp r3, r2 + 565 01ba 1ED0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 566 .loc 1 194 7 discriminator 14 view .LVU168 + 567 01bc 02F55672 add r2, r2, #856 + 568 01c0 9342 cmp r3, r2 + 569 01c2 1AD0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 570 .loc 1 194 7 discriminator 16 view .LVU169 + 571 01c4 1832 adds r2, r2, #24 + 572 01c6 9342 cmp r3, r2 + 573 01c8 17D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 574 .loc 1 194 7 discriminator 18 view .LVU170 + 575 01ca 1832 adds r2, r2, #24 + 576 01cc 9342 cmp r3, r2 + 577 01ce 14D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 578 .loc 1 194 7 discriminator 20 view .LVU171 + 579 01d0 1832 adds r2, r2, #24 + 580 01d2 9342 cmp r3, r2 + 581 01d4 11D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 582 .loc 1 194 7 discriminator 22 view .LVU172 + 583 01d6 1832 adds r2, r2, #24 + 584 01d8 9342 cmp r3, r2 + 585 01da 0ED0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 586 .loc 1 194 7 discriminator 24 view .LVU173 + ARM GAS /tmp/ccAxWhFC.s page 26 + + + 587 01dc 1832 adds r2, r2, #24 + 588 01de 9342 cmp r3, r2 + 589 01e0 0BD0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 590 .loc 1 194 7 discriminator 26 view .LVU174 + 591 01e2 1832 adds r2, r2, #24 + 592 01e4 9342 cmp r3, r2 + 593 01e6 08D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 594 .loc 1 194 7 discriminator 28 view .LVU175 + 595 01e8 1832 adds r2, r2, #24 + 596 01ea 9342 cmp r3, r2 + 597 01ec 05D0 beq .L21 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 598 .loc 1 194 7 discriminator 30 view .LVU176 + 599 01ee 1A68 ldr r2, [r3] + 600 01f0 42F00102 orr r2, r2, #1 + 601 01f4 1A60 str r2, [r3] + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 602 .loc 1 123 21 discriminator 30 view .LVU177 + 603 01f6 0020 movs r0, #0 + 604 01f8 18E7 b .L15 + 605 .L21: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 606 .loc 1 194 7 discriminator 29 view .LVU178 + 607 01fa 1A68 ldr r2, [r3] + 608 01fc 42F00102 orr r2, r2, #1 + 609 0200 1A60 str r2, [r3] + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 610 .loc 1 123 21 discriminator 29 view .LVU179 + 611 0202 0020 movs r0, #0 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 612 .loc 1 194 7 discriminator 29 view .LVU180 + 613 0204 12E7 b .L15 + 614 .LVL29: + 615 .L23: + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 616 .loc 1 139 5 view .LVU181 + 617 0206 0220 movs r0, #2 + 618 0208 10E7 b .L15 + 619 .L28: + 620 020a 00BF .align 2 + 621 .L27: + 622 020c 10000240 .word 1073872912 + 623 0210 28000240 .word 1073872936 + 624 0214 08540258 .word 1476547592 + 625 .cfi_endproc + 626 .LFE141: + 628 .section .text.HAL_DMAEx_MultiBufferStart_IT,"ax",%progbits + 629 .align 1 + 630 .global HAL_DMAEx_MultiBufferStart_IT + 631 .syntax unified + 632 .thumb + 633 .thumb_func + 634 .fpu fpv5-d16 + 636 HAL_DMAEx_MultiBufferStart_IT: + 637 .LVL30: + ARM GAS /tmp/ccAxWhFC.s page 27 + + + 638 .LFB142: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 639 .loc 1 219 1 is_stmt 1 view -0 + 640 .cfi_startproc + 641 @ args = 4, pretend = 0, frame = 0 + 642 @ frame_needed = 0, uses_anonymous_args = 0 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 643 .loc 1 219 1 is_stmt 0 view .LVU183 + 644 0000 70B5 push {r4, r5, r6, lr} + 645 .LCFI4: + 646 .cfi_def_cfa_offset 16 + 647 .cfi_offset 4, -16 + 648 .cfi_offset 5, -12 + 649 .cfi_offset 6, -8 + 650 .cfi_offset 14, -4 + 651 0002 0446 mov r4, r0 + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 652 .loc 1 220 3 is_stmt 1 view .LVU184 + 653 .LVL31: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 654 .loc 1 221 3 view .LVU185 + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 655 .loc 1 224 3 view .LVU186 + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 656 .loc 1 225 3 view .LVU187 + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 657 .loc 1 228 3 view .LVU188 + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 658 .loc 1 228 16 is_stmt 0 view .LVU189 + 659 0004 8068 ldr r0, [r0, #8] + 660 .LVL32: + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 661 .loc 1 228 5 view .LVU190 + 662 0006 8028 cmp r0, #128 + 663 0008 11D0 beq .L50 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 664 .loc 1 235 3 is_stmt 1 view .LVU191 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 665 .loc 1 235 3 view .LVU192 + 666 000a 94F83400 ldrb r0, [r4, #52] @ zero_extendqisi2 + 667 000e 0128 cmp r0, #1 + 668 0010 00F0B981 beq .L47 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 669 .loc 1 235 3 discriminator 2 view .LVU193 + 670 0014 0120 movs r0, #1 + 671 0016 84F83400 strb r0, [r4, #52] + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 672 .loc 1 235 3 discriminator 2 view .LVU194 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 673 .loc 1 237 3 discriminator 2 view .LVU195 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 674 .loc 1 237 33 is_stmt 0 discriminator 2 view .LVU196 + 675 001a 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 676 001e C0B2 uxtb r0, r0 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 677 .loc 1 237 5 discriminator 2 view .LVU197 + 678 0020 0128 cmp r0, #1 + ARM GAS /tmp/ccAxWhFC.s page 28 + + + 679 0022 09D0 beq .L51 + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 680 .loc 1 336 5 is_stmt 1 view .LVU198 + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 681 .loc 1 336 21 is_stmt 0 view .LVU199 + 682 0024 4FF40063 mov r3, #2048 + 683 .LVL33: + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 684 .loc 1 336 21 view .LVU200 + 685 0028 6365 str r3, [r4, #84] + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 686 .loc 1 339 5 is_stmt 1 view .LVU201 + 687 .LVL34: + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 688 .loc 1 339 12 is_stmt 0 view .LVU202 + 689 002a 0120 movs r0, #1 + 690 .LVL35: + 691 .L31: + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 692 .loc 1 342 1 view .LVU203 + 693 002c 70BD pop {r4, r5, r6, pc} + 694 .LVL36: + 695 .L50: + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 696 .loc 1 230 5 is_stmt 1 view .LVU204 + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 697 .loc 1 230 21 is_stmt 0 view .LVU205 + 698 002e 4FF48073 mov r3, #256 + 699 .LVL37: + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** return HAL_ERROR; + 700 .loc 1 230 21 view .LVU206 + 701 0032 6365 str r3, [r4, #84] + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 702 .loc 1 231 5 is_stmt 1 view .LVU207 + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 703 .loc 1 231 12 is_stmt 0 view .LVU208 + 704 0034 0120 movs r0, #1 + 705 0036 F9E7 b .L31 + 706 .LVL38: + 707 .L51: + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 708 .loc 1 240 5 is_stmt 1 view .LVU209 + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 709 .loc 1 240 17 is_stmt 0 view .LVU210 + 710 0038 0220 movs r0, #2 + 711 003a 84F83500 strb r0, [r4, #53] + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 712 .loc 1 243 5 is_stmt 1 view .LVU211 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 713 .loc 1 243 21 is_stmt 0 view .LVU212 + 714 003e 0020 movs r0, #0 + 715 0040 6065 str r0, [r4, #84] + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 716 .loc 1 245 5 is_stmt 1 view .LVU213 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 717 .loc 1 245 8 is_stmt 0 view .LVU214 + 718 0042 2068 ldr r0, [r4] + ARM GAS /tmp/ccAxWhFC.s page 29 + + + 719 0044 724E ldr r6, .L54 + 720 0046 734D ldr r5, .L54+4 + 721 0048 A842 cmp r0, r5 + 722 004a 18BF it ne + 723 004c B042 cmpne r0, r6 + 724 004e 39D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 725 .loc 1 245 8 discriminator 2 view .LVU215 + 726 0050 1835 adds r5, r5, #24 + 727 0052 A842 cmp r0, r5 + 728 0054 36D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 729 .loc 1 245 8 discriminator 4 view .LVU216 + 730 0056 1835 adds r5, r5, #24 + 731 0058 A842 cmp r0, r5 + 732 005a 33D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 733 .loc 1 245 8 discriminator 6 view .LVU217 + 734 005c 1835 adds r5, r5, #24 + 735 005e A842 cmp r0, r5 + 736 0060 30D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 737 .loc 1 245 8 discriminator 8 view .LVU218 + 738 0062 1835 adds r5, r5, #24 + 739 0064 A842 cmp r0, r5 + 740 0066 2DD0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 741 .loc 1 245 8 discriminator 10 view .LVU219 + 742 0068 1835 adds r5, r5, #24 + 743 006a A842 cmp r0, r5 + 744 006c 2AD0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 745 .loc 1 245 8 discriminator 12 view .LVU220 + 746 006e 1835 adds r5, r5, #24 + 747 0070 A842 cmp r0, r5 + 748 0072 27D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 749 .loc 1 245 8 discriminator 14 view .LVU221 + 750 0074 05F55675 add r5, r5, #856 + 751 0078 A842 cmp r0, r5 + 752 007a 23D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 753 .loc 1 245 8 discriminator 16 view .LVU222 + 754 007c 1835 adds r5, r5, #24 + 755 007e A842 cmp r0, r5 + 756 0080 20D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 757 .loc 1 245 8 discriminator 18 view .LVU223 + 758 0082 1835 adds r5, r5, #24 + 759 0084 A842 cmp r0, r5 + 760 0086 1DD0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 761 .loc 1 245 8 discriminator 20 view .LVU224 + 762 0088 1835 adds r5, r5, #24 + 763 008a A842 cmp r0, r5 + 764 008c 1AD0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + ARM GAS /tmp/ccAxWhFC.s page 30 + + + 765 .loc 1 245 8 discriminator 22 view .LVU225 + 766 008e 1835 adds r5, r5, #24 + 767 0090 A842 cmp r0, r5 + 768 0092 17D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 769 .loc 1 245 8 discriminator 24 view .LVU226 + 770 0094 1835 adds r5, r5, #24 + 771 0096 A842 cmp r0, r5 + 772 0098 14D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 773 .loc 1 245 8 discriminator 26 view .LVU227 + 774 009a 1835 adds r5, r5, #24 + 775 009c A842 cmp r0, r5 + 776 009e 11D0 beq .L33 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 777 .loc 1 245 8 discriminator 28 view .LVU228 + 778 00a0 1835 adds r5, r5, #24 + 779 00a2 A842 cmp r0, r5 + 780 00a4 0ED0 beq .L33 + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 781 .loc 1 262 7 is_stmt 1 view .LVU229 + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 782 .loc 1 262 55 is_stmt 0 view .LVU230 + 783 00a6 0668 ldr r6, [r0] + 784 00a8 48F22005 movw r5, #32800 + 785 00ac 3543 orrs r5, r5, r6 + 786 00ae 0560 str r5, [r0] + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 787 .loc 1 265 7 is_stmt 1 view .LVU231 + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 788 .loc 1 265 38 is_stmt 0 view .LVU232 + 789 00b0 2068 ldr r0, [r4] + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 790 .loc 1 265 57 view .LVU233 + 791 00b2 0361 str r3, [r0, #16] + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 792 .loc 1 268 7 is_stmt 1 view .LVU234 + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 793 .loc 1 268 54 is_stmt 0 view .LVU235 + 794 00b4 A56D ldr r5, [r4, #88] + 795 .LVL39: + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 796 .loc 1 271 7 is_stmt 1 view .LVU236 + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 797 .loc 1 271 51 is_stmt 0 view .LVU237 + 798 00b6 E36D ldr r3, [r4, #92] + 799 .LVL40: + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 800 .loc 1 271 65 view .LVU238 + 801 00b8 03F01F00 and r0, r3, #31 + 802 .LVL41: + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 803 .loc 1 271 43 view .LVU239 + 804 00bc 0123 movs r3, #1 + 805 00be 8340 lsls r3, r3, r0 + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 806 .loc 1 271 25 view .LVU240 + ARM GAS /tmp/ccAxWhFC.s page 31 + + + 807 00c0 6B60 str r3, [r5, #4] + 808 00c2 0CE0 b .L34 + 809 .LVL42: + 810 .L33: + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 811 .loc 1 248 7 is_stmt 1 view .LVU241 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 812 .loc 1 248 52 is_stmt 0 view .LVU242 + 813 00c4 0568 ldr r5, [r0] + 814 00c6 45F48025 orr r5, r5, #262144 + 815 00ca 0560 str r5, [r0] + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 816 .loc 1 251 7 is_stmt 1 view .LVU243 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 817 .loc 1 251 36 is_stmt 0 view .LVU244 + 818 00cc 2068 ldr r0, [r4] + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 819 .loc 1 251 54 view .LVU245 + 820 00ce 0361 str r3, [r0, #16] + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 821 .loc 1 254 7 is_stmt 1 view .LVU246 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 822 .loc 1 254 54 is_stmt 0 view .LVU247 + 823 00d0 A56D ldr r5, [r4, #88] + 824 .LVL43: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 825 .loc 1 257 7 is_stmt 1 view .LVU248 + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 826 .loc 1 257 42 is_stmt 0 view .LVU249 + 827 00d2 E36D ldr r3, [r4, #92] + 828 .LVL44: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 829 .loc 1 257 56 view .LVU250 + 830 00d4 03F01F00 and r0, r3, #31 + 831 .LVL45: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 832 .loc 1 257 34 view .LVU251 + 833 00d8 3F23 movs r3, #63 + 834 00da 8340 lsls r3, r3, r0 + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 835 .loc 1 257 25 view .LVU252 + 836 00dc AB60 str r3, [r5, #8] + 837 .LVL46: + 838 .L34: + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 839 .loc 1 275 5 is_stmt 1 view .LVU253 + 840 00de 049B ldr r3, [sp, #16] + 841 00e0 2046 mov r0, r4 + 842 00e2 FFF7FEFF bl DMA_MultiBufferSetConfig + 843 .LVL47: + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 844 .loc 1 277 5 view .LVU254 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 845 .loc 1 277 8 is_stmt 0 view .LVU255 + 846 00e6 2368 ldr r3, [r4] + 847 00e8 4949 ldr r1, .L54 + 848 00ea 4A4A ldr r2, .L54+4 + ARM GAS /tmp/ccAxWhFC.s page 32 + + + 849 00ec 9342 cmp r3, r2 + 850 00ee 18BF it ne + 851 00f0 8B42 cmpne r3, r1 + 852 00f2 42D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 853 .loc 1 277 8 discriminator 2 view .LVU256 + 854 00f4 1832 adds r2, r2, #24 + 855 00f6 9342 cmp r3, r2 + 856 00f8 3FD0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 857 .loc 1 277 8 discriminator 4 view .LVU257 + 858 00fa 1832 adds r2, r2, #24 + 859 00fc 9342 cmp r3, r2 + 860 00fe 3CD0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 861 .loc 1 277 8 discriminator 6 view .LVU258 + 862 0100 1832 adds r2, r2, #24 + 863 0102 9342 cmp r3, r2 + 864 0104 39D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 865 .loc 1 277 8 discriminator 8 view .LVU259 + 866 0106 1832 adds r2, r2, #24 + 867 0108 9342 cmp r3, r2 + 868 010a 36D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 869 .loc 1 277 8 discriminator 10 view .LVU260 + 870 010c 1832 adds r2, r2, #24 + 871 010e 9342 cmp r3, r2 + 872 0110 33D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 873 .loc 1 277 8 discriminator 12 view .LVU261 + 874 0112 1832 adds r2, r2, #24 + 875 0114 9342 cmp r3, r2 + 876 0116 30D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 877 .loc 1 277 8 discriminator 14 view .LVU262 + 878 0118 02F55672 add r2, r2, #856 + 879 011c 9342 cmp r3, r2 + 880 011e 2CD0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 881 .loc 1 277 8 discriminator 16 view .LVU263 + 882 0120 1832 adds r2, r2, #24 + 883 0122 9342 cmp r3, r2 + 884 0124 29D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 885 .loc 1 277 8 discriminator 18 view .LVU264 + 886 0126 1832 adds r2, r2, #24 + 887 0128 9342 cmp r3, r2 + 888 012a 26D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 889 .loc 1 277 8 discriminator 20 view .LVU265 + 890 012c 1832 adds r2, r2, #24 + 891 012e 9342 cmp r3, r2 + 892 0130 23D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 893 .loc 1 277 8 discriminator 22 view .LVU266 + 894 0132 1832 adds r2, r2, #24 + ARM GAS /tmp/ccAxWhFC.s page 33 + + + 895 0134 9342 cmp r3, r2 + 896 0136 20D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 897 .loc 1 277 8 discriminator 24 view .LVU267 + 898 0138 1832 adds r2, r2, #24 + 899 013a 9342 cmp r3, r2 + 900 013c 1DD0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 901 .loc 1 277 8 discriminator 26 view .LVU268 + 902 013e 1832 adds r2, r2, #24 + 903 0140 9342 cmp r3, r2 + 904 0142 1AD0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 905 .loc 1 277 8 discriminator 28 view .LVU269 + 906 0144 1832 adds r2, r2, #24 + 907 0146 9342 cmp r3, r2 + 908 0148 17D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 909 .loc 1 277 8 discriminator 30 view .LVU270 + 910 014a 334A ldr r2, .L54+8 + 911 014c 9342 cmp r3, r2 + 912 014e 14D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 913 .loc 1 277 8 discriminator 32 view .LVU271 + 914 0150 1432 adds r2, r2, #20 + 915 0152 9342 cmp r3, r2 + 916 0154 11D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 917 .loc 1 277 8 discriminator 34 view .LVU272 + 918 0156 1432 adds r2, r2, #20 + 919 0158 9342 cmp r3, r2 + 920 015a 0ED0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 921 .loc 1 277 8 discriminator 36 view .LVU273 + 922 015c 1432 adds r2, r2, #20 + 923 015e 9342 cmp r3, r2 + 924 0160 0BD0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 925 .loc 1 277 8 discriminator 38 view .LVU274 + 926 0162 1432 adds r2, r2, #20 + 927 0164 9342 cmp r3, r2 + 928 0166 08D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 929 .loc 1 277 8 discriminator 40 view .LVU275 + 930 0168 1432 adds r2, r2, #20 + 931 016a 9342 cmp r3, r2 + 932 016c 05D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 933 .loc 1 277 8 discriminator 42 view .LVU276 + 934 016e 1432 adds r2, r2, #20 + 935 0170 9342 cmp r3, r2 + 936 0172 02D0 beq .L35 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 937 .loc 1 277 8 discriminator 44 view .LVU277 + 938 0174 1432 adds r2, r2, #20 + 939 0176 9342 cmp r3, r2 + 940 0178 07D1 bne .L36 + ARM GAS /tmp/ccAxWhFC.s page 34 + + + 941 .L35: + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 942 .loc 1 280 7 is_stmt 1 view .LVU278 + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 943 .loc 1 280 11 is_stmt 0 view .LVU279 + 944 017a 636E ldr r3, [r4, #100] + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 945 .loc 1 280 44 view .LVU280 + 946 017c A26E ldr r2, [r4, #104] + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 947 .loc 1 280 38 view .LVU281 + 948 017e 5A60 str r2, [r3, #4] + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 949 .loc 1 282 7 is_stmt 1 view .LVU282 + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 950 .loc 1 282 14 is_stmt 0 view .LVU283 + 951 0180 E36E ldr r3, [r4, #108] + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 952 .loc 1 282 9 view .LVU284 + 953 0182 13B1 cbz r3, .L36 + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 954 .loc 1 285 9 is_stmt 1 view .LVU285 + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 955 .loc 1 285 13 is_stmt 0 view .LVU286 + 956 0184 236F ldr r3, [r4, #112] + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 957 .loc 1 285 51 view .LVU287 + 958 0186 626F ldr r2, [r4, #116] + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 959 .loc 1 285 45 view .LVU288 + 960 0188 5A60 str r2, [r3, #4] + 961 .L36: + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 962 .loc 1 289 5 is_stmt 1 view .LVU289 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 963 .loc 1 289 8 is_stmt 0 view .LVU290 + 964 018a 2368 ldr r3, [r4] + 965 018c 2049 ldr r1, .L54 + 966 018e 214A ldr r2, .L54+4 + 967 0190 9342 cmp r3, r2 + 968 0192 18BF it ne + 969 0194 8B42 cmpne r3, r1 + 970 0196 41D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 971 .loc 1 289 8 discriminator 2 view .LVU291 + 972 0198 1832 adds r2, r2, #24 + 973 019a 9342 cmp r3, r2 + 974 019c 3ED0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 975 .loc 1 289 8 discriminator 4 view .LVU292 + 976 019e 1832 adds r2, r2, #24 + 977 01a0 9342 cmp r3, r2 + 978 01a2 3BD0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 979 .loc 1 289 8 discriminator 6 view .LVU293 + 980 01a4 1832 adds r2, r2, #24 + 981 01a6 9342 cmp r3, r2 + ARM GAS /tmp/ccAxWhFC.s page 35 + + + 982 01a8 38D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 983 .loc 1 289 8 discriminator 8 view .LVU294 + 984 01aa 1832 adds r2, r2, #24 + 985 01ac 9342 cmp r3, r2 + 986 01ae 35D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 987 .loc 1 289 8 discriminator 10 view .LVU295 + 988 01b0 1832 adds r2, r2, #24 + 989 01b2 9342 cmp r3, r2 + 990 01b4 32D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 991 .loc 1 289 8 discriminator 12 view .LVU296 + 992 01b6 1832 adds r2, r2, #24 + 993 01b8 9342 cmp r3, r2 + 994 01ba 2FD0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 995 .loc 1 289 8 discriminator 14 view .LVU297 + 996 01bc 02F55672 add r2, r2, #856 + 997 01c0 9342 cmp r3, r2 + 998 01c2 2BD0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 999 .loc 1 289 8 discriminator 16 view .LVU298 + 1000 01c4 1832 adds r2, r2, #24 + 1001 01c6 9342 cmp r3, r2 + 1002 01c8 28D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1003 .loc 1 289 8 discriminator 18 view .LVU299 + 1004 01ca 1832 adds r2, r2, #24 + 1005 01cc 9342 cmp r3, r2 + 1006 01ce 25D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1007 .loc 1 289 8 discriminator 20 view .LVU300 + 1008 01d0 1832 adds r2, r2, #24 + 1009 01d2 9342 cmp r3, r2 + 1010 01d4 22D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1011 .loc 1 289 8 discriminator 22 view .LVU301 + 1012 01d6 1832 adds r2, r2, #24 + 1013 01d8 9342 cmp r3, r2 + 1014 01da 1FD0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1015 .loc 1 289 8 discriminator 24 view .LVU302 + 1016 01dc 1832 adds r2, r2, #24 + 1017 01de 9342 cmp r3, r2 + 1018 01e0 1CD0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1019 .loc 1 289 8 discriminator 26 view .LVU303 + 1020 01e2 1832 adds r2, r2, #24 + 1021 01e4 9342 cmp r3, r2 + 1022 01e6 19D0 beq .L37 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1023 .loc 1 289 8 discriminator 28 view .LVU304 + 1024 01e8 1832 adds r2, r2, #24 + 1025 01ea 9342 cmp r3, r2 + 1026 01ec 16D0 beq .L37 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 36 + + + 1027 .loc 1 304 7 is_stmt 1 view .LVU305 + 1028 01ee 1A68 ldr r2, [r3] + 1029 01f0 22F00E02 bic r2, r2, #14 + 1030 01f4 42F00A02 orr r2, r2, #10 + 1031 01f8 1A60 str r2, [r3] + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1032 .loc 1 306 7 view .LVU306 + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1033 .loc 1 306 15 is_stmt 0 view .LVU307 + 1034 01fa 236C ldr r3, [r4, #64] + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1035 .loc 1 306 9 view .LVU308 + 1036 01fc 002B cmp r3, #0 + 1037 01fe 00F0B780 beq .L52 + 1038 .L38: + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1039 .loc 1 309 9 is_stmt 1 view .LVU309 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1040 .loc 1 309 40 is_stmt 0 view .LVU310 + 1041 0202 2268 ldr r2, [r4] + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1042 .loc 1 309 58 view .LVU311 + 1043 0204 1368 ldr r3, [r2] + 1044 0206 43F00403 orr r3, r3, #4 + 1045 020a 1360 str r3, [r2] + 1046 020c 1AE0 b .L41 + 1047 .L55: + 1048 020e 00BF .align 2 + 1049 .L54: + 1050 0210 10000240 .word 1073872912 + 1051 0214 28000240 .word 1073872936 + 1052 0218 08540258 .word 1476547592 + 1053 .L37: + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; + 1054 .loc 1 292 7 is_stmt 1 view .LVU312 + 1055 021c 1A68 ldr r2, [r3] + 1056 021e 22F01E02 bic r2, r2, #30 + 1057 0222 42F01602 orr r2, r2, #22 + 1058 0226 1A60 str r2, [r3] + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1059 .loc 1 293 7 view .LVU313 + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1060 .loc 1 293 36 is_stmt 0 view .LVU314 + 1061 0228 2268 ldr r2, [r4] + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1062 .loc 1 293 53 view .LVU315 + 1063 022a 5369 ldr r3, [r2, #20] + 1064 022c 43F08003 orr r3, r3, #128 + 1065 0230 5361 str r3, [r2, #20] + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1066 .loc 1 295 7 is_stmt 1 view .LVU316 + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1067 .loc 1 295 15 is_stmt 0 view .LVU317 + 1068 0232 236C ldr r3, [r4, #64] + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1069 .loc 1 295 9 view .LVU318 + 1070 0234 002B cmp r3, #0 + ARM GAS /tmp/ccAxWhFC.s page 37 + + + 1071 0236 00F09680 beq .L53 + 1072 .L40: + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1073 .loc 1 298 9 is_stmt 1 view .LVU319 + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1074 .loc 1 298 38 is_stmt 0 view .LVU320 + 1075 023a 2268 ldr r2, [r4] + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1076 .loc 1 298 55 view .LVU321 + 1077 023c 1368 ldr r3, [r2] + 1078 023e 43F00803 orr r3, r3, #8 + 1079 0242 1360 str r3, [r2] + 1080 .L41: + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1081 .loc 1 313 5 is_stmt 1 view .LVU322 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1082 .loc 1 313 8 is_stmt 0 view .LVU323 + 1083 0244 2368 ldr r3, [r4] + 1084 0246 5149 ldr r1, .L56 + 1085 0248 514A ldr r2, .L56+4 + 1086 024a 9342 cmp r3, r2 + 1087 024c 18BF it ne + 1088 024e 8B42 cmpne r3, r1 + 1089 0250 42D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1090 .loc 1 313 8 discriminator 2 view .LVU324 + 1091 0252 1832 adds r2, r2, #24 + 1092 0254 9342 cmp r3, r2 + 1093 0256 3FD0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1094 .loc 1 313 8 discriminator 4 view .LVU325 + 1095 0258 1832 adds r2, r2, #24 + 1096 025a 9342 cmp r3, r2 + 1097 025c 3CD0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1098 .loc 1 313 8 discriminator 6 view .LVU326 + 1099 025e 1832 adds r2, r2, #24 + 1100 0260 9342 cmp r3, r2 + 1101 0262 39D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1102 .loc 1 313 8 discriminator 8 view .LVU327 + 1103 0264 1832 adds r2, r2, #24 + 1104 0266 9342 cmp r3, r2 + 1105 0268 36D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1106 .loc 1 313 8 discriminator 10 view .LVU328 + 1107 026a 1832 adds r2, r2, #24 + 1108 026c 9342 cmp r3, r2 + 1109 026e 33D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1110 .loc 1 313 8 discriminator 12 view .LVU329 + 1111 0270 1832 adds r2, r2, #24 + 1112 0272 9342 cmp r3, r2 + 1113 0274 30D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1114 .loc 1 313 8 discriminator 14 view .LVU330 + 1115 0276 02F55672 add r2, r2, #856 + ARM GAS /tmp/ccAxWhFC.s page 38 + + + 1116 027a 9342 cmp r3, r2 + 1117 027c 2CD0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1118 .loc 1 313 8 discriminator 16 view .LVU331 + 1119 027e 1832 adds r2, r2, #24 + 1120 0280 9342 cmp r3, r2 + 1121 0282 29D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1122 .loc 1 313 8 discriminator 18 view .LVU332 + 1123 0284 1832 adds r2, r2, #24 + 1124 0286 9342 cmp r3, r2 + 1125 0288 26D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1126 .loc 1 313 8 discriminator 20 view .LVU333 + 1127 028a 1832 adds r2, r2, #24 + 1128 028c 9342 cmp r3, r2 + 1129 028e 23D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1130 .loc 1 313 8 discriminator 22 view .LVU334 + 1131 0290 1832 adds r2, r2, #24 + 1132 0292 9342 cmp r3, r2 + 1133 0294 20D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1134 .loc 1 313 8 discriminator 24 view .LVU335 + 1135 0296 1832 adds r2, r2, #24 + 1136 0298 9342 cmp r3, r2 + 1137 029a 1DD0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1138 .loc 1 313 8 discriminator 26 view .LVU336 + 1139 029c 1832 adds r2, r2, #24 + 1140 029e 9342 cmp r3, r2 + 1141 02a0 1AD0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1142 .loc 1 313 8 discriminator 28 view .LVU337 + 1143 02a2 1832 adds r2, r2, #24 + 1144 02a4 9342 cmp r3, r2 + 1145 02a6 17D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1146 .loc 1 313 8 discriminator 30 view .LVU338 + 1147 02a8 3A4A ldr r2, .L56+8 + 1148 02aa 9342 cmp r3, r2 + 1149 02ac 14D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1150 .loc 1 313 8 discriminator 32 view .LVU339 + 1151 02ae 1432 adds r2, r2, #20 + 1152 02b0 9342 cmp r3, r2 + 1153 02b2 11D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1154 .loc 1 313 8 discriminator 34 view .LVU340 + 1155 02b4 1432 adds r2, r2, #20 + 1156 02b6 9342 cmp r3, r2 + 1157 02b8 0ED0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1158 .loc 1 313 8 discriminator 36 view .LVU341 + 1159 02ba 1432 adds r2, r2, #20 + 1160 02bc 9342 cmp r3, r2 + 1161 02be 0BD0 beq .L42 + ARM GAS /tmp/ccAxWhFC.s page 39 + + + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1162 .loc 1 313 8 discriminator 38 view .LVU342 + 1163 02c0 1432 adds r2, r2, #20 + 1164 02c2 9342 cmp r3, r2 + 1165 02c4 08D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1166 .loc 1 313 8 discriminator 40 view .LVU343 + 1167 02c6 1432 adds r2, r2, #20 + 1168 02c8 9342 cmp r3, r2 + 1169 02ca 05D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1170 .loc 1 313 8 discriminator 42 view .LVU344 + 1171 02cc 1432 adds r2, r2, #20 + 1172 02ce 9342 cmp r3, r2 + 1173 02d0 02D0 beq .L42 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1174 .loc 1 313 8 discriminator 44 view .LVU345 + 1175 02d2 1432 adds r2, r2, #20 + 1176 02d4 9342 cmp r3, r2 + 1177 02d6 0ED1 bne .L43 + 1178 .L42: + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1179 .loc 1 316 7 is_stmt 1 view .LVU346 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1180 .loc 1 316 15 is_stmt 0 view .LVU347 + 1181 02d8 236E ldr r3, [r4, #96] + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1182 .loc 1 316 30 view .LVU348 + 1183 02da 1A68 ldr r2, [r3] + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1184 .loc 1 316 9 view .LVU349 + 1185 02dc 12F4803F tst r2, #65536 + 1186 02e0 03D0 beq .L44 + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1187 .loc 1 319 9 is_stmt 1 view .LVU350 + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1188 .loc 1 319 34 is_stmt 0 view .LVU351 + 1189 02e2 1A68 ldr r2, [r3] + 1190 02e4 42F48072 orr r2, r2, #256 + 1191 02e8 1A60 str r2, [r3] + 1192 .L44: + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1193 .loc 1 322 7 is_stmt 1 view .LVU352 + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1194 .loc 1 322 14 is_stmt 0 view .LVU353 + 1195 02ea E36E ldr r3, [r4, #108] + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1196 .loc 1 322 9 view .LVU354 + 1197 02ec 1BB1 cbz r3, .L43 + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1198 .loc 1 326 9 is_stmt 1 view .LVU355 + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1199 .loc 1 326 38 is_stmt 0 view .LVU356 + 1200 02ee 1A68 ldr r2, [r3] + 1201 02f0 42F48072 orr r2, r2, #256 + 1202 02f4 1A60 str r2, [r3] + 1203 .L43: + ARM GAS /tmp/ccAxWhFC.s page 40 + + + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1204 .loc 1 331 5 is_stmt 1 view .LVU357 + 1205 02f6 2368 ldr r3, [r4] + 1206 02f8 2449 ldr r1, .L56 + 1207 02fa 254A ldr r2, .L56+4 + 1208 02fc 9342 cmp r3, r2 + 1209 02fe 18BF it ne + 1210 0300 8B42 cmpne r3, r1 + 1211 0302 3AD0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1212 .loc 1 331 5 is_stmt 0 discriminator 2 view .LVU358 + 1213 0304 1832 adds r2, r2, #24 + 1214 0306 9342 cmp r3, r2 + 1215 0308 37D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1216 .loc 1 331 5 discriminator 4 view .LVU359 + 1217 030a 1832 adds r2, r2, #24 + 1218 030c 9342 cmp r3, r2 + 1219 030e 34D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1220 .loc 1 331 5 discriminator 6 view .LVU360 + 1221 0310 1832 adds r2, r2, #24 + 1222 0312 9342 cmp r3, r2 + 1223 0314 31D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1224 .loc 1 331 5 discriminator 8 view .LVU361 + 1225 0316 1832 adds r2, r2, #24 + 1226 0318 9342 cmp r3, r2 + 1227 031a 2ED0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1228 .loc 1 331 5 discriminator 10 view .LVU362 + 1229 031c 1832 adds r2, r2, #24 + 1230 031e 9342 cmp r3, r2 + 1231 0320 2BD0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1232 .loc 1 331 5 discriminator 12 view .LVU363 + 1233 0322 1832 adds r2, r2, #24 + 1234 0324 9342 cmp r3, r2 + 1235 0326 28D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1236 .loc 1 331 5 discriminator 14 view .LVU364 + 1237 0328 02F55672 add r2, r2, #856 + 1238 032c 9342 cmp r3, r2 + 1239 032e 24D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1240 .loc 1 331 5 discriminator 16 view .LVU365 + 1241 0330 1832 adds r2, r2, #24 + 1242 0332 9342 cmp r3, r2 + 1243 0334 21D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1244 .loc 1 331 5 discriminator 18 view .LVU366 + 1245 0336 1832 adds r2, r2, #24 + 1246 0338 9342 cmp r3, r2 + 1247 033a 1ED0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1248 .loc 1 331 5 discriminator 20 view .LVU367 + 1249 033c 1832 adds r2, r2, #24 + ARM GAS /tmp/ccAxWhFC.s page 41 + + + 1250 033e 9342 cmp r3, r2 + 1251 0340 1BD0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1252 .loc 1 331 5 discriminator 22 view .LVU368 + 1253 0342 1832 adds r2, r2, #24 + 1254 0344 9342 cmp r3, r2 + 1255 0346 18D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1256 .loc 1 331 5 discriminator 24 view .LVU369 + 1257 0348 1832 adds r2, r2, #24 + 1258 034a 9342 cmp r3, r2 + 1259 034c 15D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1260 .loc 1 331 5 discriminator 26 view .LVU370 + 1261 034e 1832 adds r2, r2, #24 + 1262 0350 9342 cmp r3, r2 + 1263 0352 12D0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1264 .loc 1 331 5 discriminator 28 view .LVU371 + 1265 0354 1832 adds r2, r2, #24 + 1266 0356 9342 cmp r3, r2 + 1267 0358 0FD0 beq .L45 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1268 .loc 1 331 5 discriminator 30 view .LVU372 + 1269 035a 1A68 ldr r2, [r3] + 1270 035c 42F00102 orr r2, r2, #1 + 1271 0360 1A60 str r2, [r3] + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 1272 .loc 1 220 21 discriminator 30 view .LVU373 + 1273 0362 0020 movs r0, #0 + 1274 0364 62E6 b .L31 + 1275 .L53: + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1276 .loc 1 295 55 discriminator 1 view .LVU374 + 1277 0366 A36C ldr r3, [r4, #72] + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1278 .loc 1 295 47 discriminator 1 view .LVU375 + 1279 0368 002B cmp r3, #0 + 1280 036a 7FF466AF bne .L40 + 1281 036e 69E7 b .L41 + 1282 .L52: + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1283 .loc 1 306 55 discriminator 1 view .LVU376 + 1284 0370 A36C ldr r3, [r4, #72] + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1285 .loc 1 306 47 discriminator 1 view .LVU377 + 1286 0372 002B cmp r3, #0 + 1287 0374 7FF445AF bne .L38 + 1288 0378 64E7 b .L41 + 1289 .L45: + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1290 .loc 1 331 5 discriminator 29 view .LVU378 + 1291 037a 1A68 ldr r2, [r3] + 1292 037c 42F00102 orr r2, r2, #1 + 1293 0380 1A60 str r2, [r3] + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + 1294 .loc 1 220 21 discriminator 29 view .LVU379 + ARM GAS /tmp/ccAxWhFC.s page 42 + + + 1295 0382 0020 movs r0, #0 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1296 .loc 1 331 5 discriminator 29 view .LVU380 + 1297 0384 52E6 b .L31 + 1298 .LVL48: + 1299 .L47: + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1300 .loc 1 235 3 view .LVU381 + 1301 0386 0220 movs r0, #2 + 1302 0388 50E6 b .L31 + 1303 .L57: + 1304 038a 00BF .align 2 + 1305 .L56: + 1306 038c 10000240 .word 1073872912 + 1307 0390 28000240 .word 1073872936 + 1308 0394 08540258 .word 1476547592 + 1309 .cfi_endproc + 1310 .LFE142: + 1312 .section .text.HAL_DMAEx_ChangeMemory,"ax",%progbits + 1313 .align 1 + 1314 .global HAL_DMAEx_ChangeMemory + 1315 .syntax unified + 1316 .thumb + 1317 .thumb_func + 1318 .fpu fpv5-d16 + 1320 HAL_DMAEx_ChangeMemory: + 1321 .LVL49: + 1322 .LFB143: + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 1323 .loc 1 359 1 is_stmt 1 view -0 + 1324 .cfi_startproc + 1325 @ args = 0, pretend = 0, frame = 0 + 1326 @ frame_needed = 0, uses_anonymous_args = 0 + 1327 @ link register save eliminated. + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + 1328 .loc 1 359 1 is_stmt 0 view .LVU383 + 1329 0000 10B4 push {r4} + 1330 .LCFI5: + 1331 .cfi_def_cfa_offset 4 + 1332 .cfi_offset 4, -4 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1333 .loc 1 360 3 is_stmt 1 view .LVU384 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1334 .loc 1 360 6 is_stmt 0 view .LVU385 + 1335 0002 0368 ldr r3, [r0] + 1336 0004 1E4C ldr r4, .L66 + 1337 0006 1F48 ldr r0, .L66+4 + 1338 .LVL50: + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1339 .loc 1 360 6 view .LVU386 + 1340 0008 8342 cmp r3, r0 + 1341 000a 18BF it ne + 1342 000c A342 cmpne r3, r4 + 1343 000e 2DD0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1344 .loc 1 360 6 discriminator 2 view .LVU387 + 1345 0010 1830 adds r0, r0, #24 + ARM GAS /tmp/ccAxWhFC.s page 43 + + + 1346 0012 8342 cmp r3, r0 + 1347 0014 2AD0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1348 .loc 1 360 6 discriminator 4 view .LVU388 + 1349 0016 1830 adds r0, r0, #24 + 1350 0018 8342 cmp r3, r0 + 1351 001a 27D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1352 .loc 1 360 6 discriminator 6 view .LVU389 + 1353 001c 1830 adds r0, r0, #24 + 1354 001e 8342 cmp r3, r0 + 1355 0020 24D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1356 .loc 1 360 6 discriminator 8 view .LVU390 + 1357 0022 1830 adds r0, r0, #24 + 1358 0024 8342 cmp r3, r0 + 1359 0026 21D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1360 .loc 1 360 6 discriminator 10 view .LVU391 + 1361 0028 1830 adds r0, r0, #24 + 1362 002a 8342 cmp r3, r0 + 1363 002c 1ED0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1364 .loc 1 360 6 discriminator 12 view .LVU392 + 1365 002e 1830 adds r0, r0, #24 + 1366 0030 8342 cmp r3, r0 + 1367 0032 1BD0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1368 .loc 1 360 6 discriminator 14 view .LVU393 + 1369 0034 00F55670 add r0, r0, #856 + 1370 0038 8342 cmp r3, r0 + 1371 003a 17D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1372 .loc 1 360 6 discriminator 16 view .LVU394 + 1373 003c 1830 adds r0, r0, #24 + 1374 003e 8342 cmp r3, r0 + 1375 0040 14D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1376 .loc 1 360 6 discriminator 18 view .LVU395 + 1377 0042 1830 adds r0, r0, #24 + 1378 0044 8342 cmp r3, r0 + 1379 0046 11D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1380 .loc 1 360 6 discriminator 20 view .LVU396 + 1381 0048 1830 adds r0, r0, #24 + 1382 004a 8342 cmp r3, r0 + 1383 004c 0ED0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1384 .loc 1 360 6 discriminator 22 view .LVU397 + 1385 004e 1830 adds r0, r0, #24 + 1386 0050 8342 cmp r3, r0 + 1387 0052 0BD0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1388 .loc 1 360 6 discriminator 24 view .LVU398 + 1389 0054 1830 adds r0, r0, #24 + 1390 0056 8342 cmp r3, r0 + 1391 0058 08D0 beq .L59 + ARM GAS /tmp/ccAxWhFC.s page 44 + + + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1392 .loc 1 360 6 discriminator 26 view .LVU399 + 1393 005a 1830 adds r0, r0, #24 + 1394 005c 8342 cmp r3, r0 + 1395 005e 05D0 beq .L59 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1396 .loc 1 360 6 discriminator 28 view .LVU400 + 1397 0060 1830 adds r0, r0, #24 + 1398 0062 8342 cmp r3, r0 + 1399 0064 02D0 beq .L59 + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1400 .loc 1 375 5 is_stmt 1 view .LVU401 + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1401 .loc 1 375 7 is_stmt 0 view .LVU402 + 1402 0066 4AB1 cbz r2, .L60 + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1403 .loc 1 383 7 is_stmt 1 view .LVU403 + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1404 .loc 1 383 57 is_stmt 0 view .LVU404 + 1405 0068 1961 str r1, [r3, #16] + 1406 006a 01E0 b .L63 + 1407 .L59: + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1408 .loc 1 362 5 is_stmt 1 view .LVU405 + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1409 .loc 1 362 7 is_stmt 0 view .LVU406 + 1410 006c 22B9 cbnz r2, .L62 + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1411 .loc 1 365 7 is_stmt 1 view .LVU407 + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1412 .loc 1 365 54 is_stmt 0 view .LVU408 + 1413 006e D960 str r1, [r3, #12] + 1414 .L63: + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1415 .loc 1 387 3 is_stmt 1 view .LVU409 + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1416 .loc 1 388 1 is_stmt 0 view .LVU410 + 1417 0070 0020 movs r0, #0 + 1418 0072 5DF8044B ldr r4, [sp], #4 + 1419 .LCFI6: + 1420 .cfi_remember_state + 1421 .cfi_restore 4 + 1422 .cfi_def_cfa_offset 0 + 1423 0076 7047 bx lr + 1424 .L62: + 1425 .LCFI7: + 1426 .cfi_restore_state + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1427 .loc 1 370 7 is_stmt 1 view .LVU411 + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1428 .loc 1 370 54 is_stmt 0 view .LVU412 + 1429 0078 1961 str r1, [r3, #16] + 1430 007a F9E7 b .L63 + 1431 .L60: + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1432 .loc 1 378 7 is_stmt 1 view .LVU413 + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + ARM GAS /tmp/ccAxWhFC.s page 45 + + + 1433 .loc 1 378 57 is_stmt 0 view .LVU414 + 1434 007c D960 str r1, [r3, #12] + 1435 007e F7E7 b .L63 + 1436 .L67: + 1437 .align 2 + 1438 .L66: + 1439 0080 10000240 .word 1073872912 + 1440 0084 28000240 .word 1073872936 + 1441 .cfi_endproc + 1442 .LFE143: + 1444 .section .text.HAL_DMAEx_ConfigMuxSync,"ax",%progbits + 1445 .align 1 + 1446 .global HAL_DMAEx_ConfigMuxSync + 1447 .syntax unified + 1448 .thumb + 1449 .thumb_func + 1450 .fpu fpv5-d16 + 1452 HAL_DMAEx_ConfigMuxSync: + 1453 .LVL51: + 1454 .LFB144: + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** uint32_t syncSignalID = 0; + 1455 .loc 1 398 1 is_stmt 1 view -0 + 1456 .cfi_startproc + 1457 @ args = 0, pretend = 0, frame = 0 + 1458 @ frame_needed = 0, uses_anonymous_args = 0 + 1459 @ link register save eliminated. + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** uint32_t syncSignalID = 0; + 1460 .loc 1 398 1 is_stmt 0 view .LVU416 + 1461 0000 70B4 push {r4, r5, r6} + 1462 .LCFI8: + 1463 .cfi_def_cfa_offset 12 + 1464 .cfi_offset 4, -12 + 1465 .cfi_offset 5, -8 + 1466 .cfi_offset 6, -4 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** uint32_t syncPolarity = 0; + 1467 .loc 1 399 3 is_stmt 1 view .LVU417 + 1468 .LVL52: + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1469 .loc 1 400 3 view .LVU418 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + 1470 .loc 1 403 3 view .LVU419 + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + 1471 .loc 1 404 3 view .LVU420 + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + 1472 .loc 1 405 3 view .LVU421 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1473 .loc 1 406 3 view .LVU422 + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1474 .loc 1 408 3 view .LVU423 + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1475 .loc 1 408 17 is_stmt 0 view .LVU424 + 1476 0002 0B7A ldrb r3, [r1, #8] @ zero_extendqisi2 + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1477 .loc 1 408 5 view .LVU425 + 1478 0004 012B cmp r3, #1 + 1479 0006 28D0 beq .L75 + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 46 + + + 1480 .loc 1 400 12 view .LVU426 + 1481 0008 0024 movs r4, #0 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** uint32_t syncPolarity = 0; + 1482 .loc 1 399 12 view .LVU427 + 1483 000a 2546 mov r5, r4 + 1484 .LVL53: + 1485 .L69: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1486 .loc 1 425 3 is_stmt 1 view .LVU428 + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1487 .loc 1 425 10 is_stmt 0 view .LVU429 + 1488 000c 90F83520 ldrb r2, [r0, #53] @ zero_extendqisi2 + 1489 0010 D2B2 uxtb r2, r2 + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1490 .loc 1 425 5 view .LVU430 + 1491 0012 012A cmp r2, #1 + 1492 0014 24D1 bne .L70 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1493 .loc 1 428 5 is_stmt 1 view .LVU431 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1494 .loc 1 428 5 view .LVU432 + 1495 0016 90F83430 ldrb r3, [r0, #52] @ zero_extendqisi2 + 1496 001a 012B cmp r3, #1 + 1497 001c 26D0 beq .L73 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1498 .loc 1 428 5 discriminator 2 view .LVU433 + 1499 001e 0123 movs r3, #1 + 1500 0020 80F83430 strb r3, [r0, #52] + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1501 .loc 1 428 5 discriminator 2 view .LVU434 + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1502 .loc 1 431 5 discriminator 2 view .LVU435 + 1503 0024 036E ldr r3, [r0, #96] + 1504 0026 1A68 ldr r2, [r3] + 1505 0028 22F48132 bic r2, r2, #66048 + 1506 002c 1A60 str r2, [r3] + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (~DMAMUX_CxCR_DMAREQ_ID) , \ + 1507 .loc 1 434 5 discriminator 2 view .LVU436 + 1508 002e 066E ldr r6, [r0, #96] + 1509 0030 3268 ldr r2, [r6] + 1510 0032 D2B2 uxtb r2, r2 + 1511 0034 CB68 ldr r3, [r1, #12] + 1512 0036 013B subs r3, r3, #1 + 1513 0038 DB04 lsls r3, r3, #19 + 1514 003a 43EA0563 orr r3, r3, r5, lsl #24 + 1515 003e 2343 orrs r3, r3, r4 + 1516 0040 0C7A ldrb r4, [r1, #8] @ zero_extendqisi2 + 1517 .LVL54: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (~DMAMUX_CxCR_DMAREQ_ID) , \ + 1518 .loc 1 434 5 is_stmt 0 discriminator 2 view .LVU437 + 1519 0042 43EA0443 orr r3, r3, r4, lsl #16 + 1520 0046 497A ldrb r1, [r1, #9] @ zero_extendqisi2 + 1521 .LVL55: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** (~DMAMUX_CxCR_DMAREQ_ID) , \ + 1522 .loc 1 434 5 discriminator 2 view .LVU438 + 1523 0048 43EA4123 orr r3, r3, r1, lsl #9 + 1524 004c 1343 orrs r3, r3, r2 + ARM GAS /tmp/ccAxWhFC.s page 47 + + + 1525 004e 3360 str r3, [r6] + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1526 .loc 1 442 5 is_stmt 1 discriminator 2 view .LVU439 + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1527 .loc 1 442 5 discriminator 2 view .LVU440 + 1528 0050 0023 movs r3, #0 + 1529 0052 80F83430 strb r3, [r0, #52] + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1530 .loc 1 442 5 discriminator 2 view .LVU441 + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1531 .loc 1 444 5 discriminator 2 view .LVU442 + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1532 .loc 1 444 12 is_stmt 0 discriminator 2 view .LVU443 + 1533 0056 1846 mov r0, r3 + 1534 .LVL56: + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1535 .loc 1 444 12 discriminator 2 view .LVU444 + 1536 0058 06E0 b .L71 + 1537 .LVL57: + 1538 .L75: + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1539 .loc 1 410 5 is_stmt 1 view .LVU445 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1540 .loc 1 412 5 view .LVU446 + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1541 .loc 1 418 7 view .LVU447 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** syncPolarity = pSyncConfig->SyncPolarity; + 1542 .loc 1 420 5 view .LVU448 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** syncPolarity = pSyncConfig->SyncPolarity; + 1543 .loc 1 420 18 is_stmt 0 view .LVU449 + 1544 005a 0D68 ldr r5, [r1] + 1545 .LVL58: + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1546 .loc 1 421 5 is_stmt 1 view .LVU450 + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1547 .loc 1 421 18 is_stmt 0 view .LVU451 + 1548 005c 4C68 ldr r4, [r1, #4] + 1549 .LVL59: + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1550 .loc 1 421 18 view .LVU452 + 1551 005e D5E7 b .L69 + 1552 .L70: + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1553 .loc 1 449 5 is_stmt 1 view .LVU453 + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1554 .loc 1 449 21 is_stmt 0 view .LVU454 + 1555 0060 4FF40063 mov r3, #2048 + 1556 0064 4365 str r3, [r0, #84] + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1557 .loc 1 452 5 is_stmt 1 view .LVU455 + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1558 .loc 1 452 12 is_stmt 0 view .LVU456 + 1559 0066 0120 movs r0, #1 + 1560 .LVL60: + 1561 .L71: + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1562 .loc 1 454 1 view .LVU457 + ARM GAS /tmp/ccAxWhFC.s page 48 + + + 1563 0068 70BC pop {r4, r5, r6} + 1564 .LCFI9: + 1565 .cfi_remember_state + 1566 .cfi_restore 6 + 1567 .cfi_restore 5 + 1568 .cfi_restore 4 + 1569 .cfi_def_cfa_offset 0 + 1570 .LVL61: + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1571 .loc 1 454 1 view .LVU458 + 1572 006a 7047 bx lr + 1573 .LVL62: + 1574 .L73: + 1575 .LCFI10: + 1576 .cfi_restore_state + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1577 .loc 1 428 5 view .LVU459 + 1578 006c 0220 movs r0, #2 + 1579 .LVL63: + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1580 .loc 1 428 5 view .LVU460 + 1581 006e FBE7 b .L71 + 1582 .cfi_endproc + 1583 .LFE144: + 1585 .section .text.HAL_DMAEx_ConfigMuxRequestGenerator,"ax",%progbits + 1586 .align 1 + 1587 .global HAL_DMAEx_ConfigMuxRequestGenerator + 1588 .syntax unified + 1589 .thumb + 1590 .thumb_func + 1591 .fpu fpv5-d16 + 1593 HAL_DMAEx_ConfigMuxRequestGenerator: + 1594 .LVL64: + 1595 .LFB145: + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status; + 1596 .loc 1 466 1 is_stmt 1 view -0 + 1597 .cfi_startproc + 1598 @ args = 0, pretend = 0, frame = 0 + 1599 @ frame_needed = 0, uses_anonymous_args = 0 + 1600 @ link register save eliminated. + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_DMA_StateTypeDef temp_state = hdma->State; + 1601 .loc 1 467 3 view .LVU462 + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1602 .loc 1 468 3 view .LVU463 + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1603 .loc 1 468 24 is_stmt 0 view .LVU464 + 1604 0000 90F83530 ldrb r3, [r0, #53] @ zero_extendqisi2 + 1605 .LVL65: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1606 .loc 1 471 3 is_stmt 1 view .LVU465 + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1607 .loc 1 473 3 view .LVU466 + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1608 .loc 1 479 5 view .LVU467 + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + 1609 .loc 1 483 3 view .LVU468 + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 49 + + + 1610 .loc 1 484 3 view .LVU469 + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1611 .loc 1 489 3 view .LVU470 + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1612 .loc 1 489 10 is_stmt 0 view .LVU471 + 1613 0004 C26E ldr r2, [r0, #108] + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1614 .loc 1 489 5 view .LVU472 + 1615 0006 72B1 cbz r2, .L84 + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** HAL_StatusTypeDef status; + 1616 .loc 1 466 1 view .LVU473 + 1617 0008 10B4 push {r4} + 1618 .LCFI11: + 1619 .cfi_def_cfa_offset 4 + 1620 .cfi_offset 4, -4 + 1621 000a DBB2 uxtb r3, r3 + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1622 .loc 1 497 8 is_stmt 1 view .LVU474 + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1623 .loc 1 497 35 is_stmt 0 view .LVU475 + 1624 000c 1468 ldr r4, [r2] + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1625 .loc 1 497 10 view .LVU476 + 1626 000e 14F4803F tst r4, #65536 + 1627 0012 01D1 bne .L79 + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1628 .loc 1 497 68 discriminator 1 view .LVU477 + 1629 0014 012B cmp r3, #1 + 1630 0016 0AD0 beq .L85 + 1631 .L79: + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1632 .loc 1 516 5 is_stmt 1 view .LVU478 + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1633 .loc 1 516 21 is_stmt 0 view .LVU479 + 1634 0018 4FF40063 mov r3, #2048 + 1635 .LVL66: + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1636 .loc 1 516 21 view .LVU480 + 1637 001c 4365 str r3, [r0, #84] + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1638 .loc 1 519 5 is_stmt 1 view .LVU481 + 1639 .LVL67: + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1640 .loc 1 522 10 is_stmt 0 view .LVU482 + 1641 001e 0120 movs r0, #1 + 1642 .LVL68: + 1643 .L78: + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1644 .loc 1 523 1 view .LVU483 + 1645 0020 5DF8044B ldr r4, [sp], #4 + 1646 .LCFI12: + 1647 .cfi_restore 4 + 1648 .cfi_def_cfa_offset 0 + 1649 0024 7047 bx lr + 1650 .LVL69: + 1651 .L84: + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 50 + + + 1652 .loc 1 492 5 is_stmt 1 view .LVU484 + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1653 .loc 1 492 21 is_stmt 0 view .LVU485 + 1654 0026 4023 movs r3, #64 + 1655 .LVL70: + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1656 .loc 1 492 21 view .LVU486 + 1657 0028 4365 str r3, [r0, #84] + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1658 .loc 1 495 5 is_stmt 1 view .LVU487 + 1659 .LVL71: + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1660 .loc 1 522 10 is_stmt 0 view .LVU488 + 1661 002a 0120 movs r0, #1 + 1662 .LVL72: + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1663 .loc 1 523 1 view .LVU489 + 1664 002c 7047 bx lr + 1665 .LVL73: + 1666 .L85: + 1667 .LCFI13: + 1668 .cfi_def_cfa_offset 4 + 1669 .cfi_offset 4, -4 + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1670 .loc 1 502 5 is_stmt 1 view .LVU490 + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1671 .loc 1 502 5 view .LVU491 + 1672 002e 90F83430 ldrb r3, [r0, #52] @ zero_extendqisi2 + 1673 .LVL74: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1674 .loc 1 502 5 is_stmt 0 view .LVU492 + 1675 0032 012B cmp r3, #1 + 1676 0034 0FD0 beq .L80 + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1677 .loc 1 502 5 is_stmt 1 discriminator 2 view .LVU493 + 1678 0036 0123 movs r3, #1 + 1679 0038 80F83430 strb r3, [r0, #52] + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1680 .loc 1 502 5 discriminator 2 view .LVU494 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GN + 1681 .loc 1 505 5 discriminator 2 view .LVU495 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GN + 1682 .loc 1 505 59 is_stmt 0 discriminator 2 view .LVU496 + 1683 003c 0B68 ldr r3, [r1] + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 1684 .loc 1 506 60 discriminator 2 view .LVU497 + 1685 003e 8C68 ldr r4, [r1, #8] + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 1686 .loc 1 506 76 discriminator 2 view .LVU498 + 1687 0040 013C subs r4, r4, #1 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GN + 1688 .loc 1 505 70 discriminator 2 view .LVU499 + 1689 0042 43EAC443 orr r3, r3, r4, lsl #19 + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Process Locked */ + 1690 .loc 1 507 58 discriminator 2 view .LVU500 + 1691 0046 4968 ldr r1, [r1, #4] + 1692 .LVL75: + ARM GAS /tmp/ccAxWhFC.s page 51 + + + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 1693 .loc 1 506 109 discriminator 2 view .LVU501 + 1694 0048 0B43 orrs r3, r3, r1 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GN + 1695 .loc 1 505 34 discriminator 2 view .LVU502 + 1696 004a 1360 str r3, [r2] + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1697 .loc 1 509 5 is_stmt 1 discriminator 2 view .LVU503 + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1698 .loc 1 509 5 discriminator 2 view .LVU504 + 1699 004c 0023 movs r3, #0 + 1700 004e 80F83430 strb r3, [r0, #52] + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1701 .loc 1 509 5 discriminator 2 view .LVU505 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1702 .loc 1 511 5 discriminator 2 view .LVU506 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1703 .loc 1 511 12 is_stmt 0 discriminator 2 view .LVU507 + 1704 0052 1846 mov r0, r3 + 1705 .LVL76: + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1706 .loc 1 511 12 discriminator 2 view .LVU508 + 1707 0054 E4E7 b .L78 + 1708 .LVL77: + 1709 .L80: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1710 .loc 1 502 5 view .LVU509 + 1711 0056 0220 movs r0, #2 + 1712 .LVL78: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1713 .loc 1 502 5 view .LVU510 + 1714 0058 E2E7 b .L78 + 1715 .cfi_endproc + 1716 .LFE145: + 1718 .section .text.HAL_DMAEx_EnableMuxRequestGenerator,"ax",%progbits + 1719 .align 1 + 1720 .global HAL_DMAEx_EnableMuxRequestGenerator + 1721 .syntax unified + 1722 .thumb + 1723 .thumb_func + 1724 .fpu fpv5-d16 + 1726 HAL_DMAEx_EnableMuxRequestGenerator: + 1727 .LVL79: + 1728 .LFB146: + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 1729 .loc 1 532 1 is_stmt 1 view -0 + 1730 .cfi_startproc + 1731 @ args = 0, pretend = 0, frame = 0 + 1732 @ frame_needed = 0, uses_anonymous_args = 0 + 1733 @ link register save eliminated. + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1734 .loc 1 534 3 view .LVU512 + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1735 .loc 1 538 3 view .LVU513 + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1736 .loc 1 538 11 is_stmt 0 view .LVU514 + 1737 0000 90F83530 ldrb r3, [r0, #53] @ zero_extendqisi2 + ARM GAS /tmp/ccAxWhFC.s page 52 + + + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1738 .loc 1 538 5 view .LVU515 + 1739 0004 3BB1 cbz r3, .L88 + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1740 .loc 1 538 51 discriminator 1 view .LVU516 + 1741 0006 C36E ldr r3, [r0, #108] + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1742 .loc 1 538 43 discriminator 1 view .LVU517 + 1743 0008 3BB1 cbz r3, .L89 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1744 .loc 1 541 5 is_stmt 1 view .LVU518 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1745 .loc 1 541 34 is_stmt 0 view .LVU519 + 1746 000a 1A68 ldr r2, [r3] + 1747 000c 42F48032 orr r2, r2, #65536 + 1748 0010 1A60 str r2, [r3] + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1749 .loc 1 543 4 is_stmt 1 view .LVU520 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1750 .loc 1 543 11 is_stmt 0 view .LVU521 + 1751 0012 0020 movs r0, #0 + 1752 .LVL80: + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1753 .loc 1 543 11 view .LVU522 + 1754 0014 7047 bx lr + 1755 .LVL81: + 1756 .L88: + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1757 .loc 1 547 11 view .LVU523 + 1758 0016 0120 movs r0, #1 + 1759 .LVL82: + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1760 .loc 1 547 11 view .LVU524 + 1761 0018 7047 bx lr + 1762 .LVL83: + 1763 .L89: + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1764 .loc 1 547 11 view .LVU525 + 1765 001a 0120 movs r0, #1 + 1766 .LVL84: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1767 .loc 1 549 1 view .LVU526 + 1768 001c 7047 bx lr + 1769 .cfi_endproc + 1770 .LFE146: + 1772 .section .text.HAL_DMAEx_DisableMuxRequestGenerator,"ax",%progbits + 1773 .align 1 + 1774 .global HAL_DMAEx_DisableMuxRequestGenerator + 1775 .syntax unified + 1776 .thumb + 1777 .thumb_func + 1778 .fpu fpv5-d16 + 1780 HAL_DMAEx_DisableMuxRequestGenerator: + 1781 .LVL85: + 1782 .LFB147: + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check the parameters */ + 1783 .loc 1 558 1 is_stmt 1 view -0 + ARM GAS /tmp/ccAxWhFC.s page 53 + + + 1784 .cfi_startproc + 1785 @ args = 0, pretend = 0, frame = 0 + 1786 @ frame_needed = 0, uses_anonymous_args = 0 + 1787 @ link register save eliminated. + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1788 .loc 1 560 3 view .LVU528 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1789 .loc 1 564 3 view .LVU529 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1790 .loc 1 564 11 is_stmt 0 view .LVU530 + 1791 0000 90F83530 ldrb r3, [r0, #53] @ zero_extendqisi2 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1792 .loc 1 564 5 view .LVU531 + 1793 0004 3BB1 cbz r3, .L92 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1794 .loc 1 564 51 discriminator 1 view .LVU532 + 1795 0006 C36E ldr r3, [r0, #108] + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1796 .loc 1 564 43 discriminator 1 view .LVU533 + 1797 0008 3BB1 cbz r3, .L93 + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1798 .loc 1 567 5 is_stmt 1 view .LVU534 + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1799 .loc 1 567 34 is_stmt 0 view .LVU535 + 1800 000a 1A68 ldr r2, [r3] + 1801 000c 22F48032 bic r2, r2, #65536 + 1802 0010 1A60 str r2, [r3] + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1803 .loc 1 569 4 is_stmt 1 view .LVU536 + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1804 .loc 1 569 11 is_stmt 0 view .LVU537 + 1805 0012 0020 movs r0, #0 + 1806 .LVL86: + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1807 .loc 1 569 11 view .LVU538 + 1808 0014 7047 bx lr + 1809 .LVL87: + 1810 .L92: + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1811 .loc 1 573 11 view .LVU539 + 1812 0016 0120 movs r0, #1 + 1813 .LVL88: + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1814 .loc 1 573 11 view .LVU540 + 1815 0018 7047 bx lr + 1816 .LVL89: + 1817 .L93: + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1818 .loc 1 573 11 view .LVU541 + 1819 001a 0120 movs r0, #1 + 1820 .LVL90: + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1821 .loc 1 575 1 view .LVU542 + 1822 001c 7047 bx lr + 1823 .cfi_endproc + 1824 .LFE147: + 1826 .section .text.HAL_DMAEx_MUX_IRQHandler,"ax",%progbits + ARM GAS /tmp/ccAxWhFC.s page 54 + + + 1827 .align 1 + 1828 .global HAL_DMAEx_MUX_IRQHandler + 1829 .syntax unified + 1830 .thumb + 1831 .thumb_func + 1832 .fpu fpv5-d16 + 1834 HAL_DMAEx_MUX_IRQHandler: + 1835 .LVL91: + 1836 .LFB148: + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check for DMAMUX Synchronization overrun */ + 1837 .loc 1 584 1 is_stmt 1 view -0 + 1838 .cfi_startproc + 1839 @ args = 0, pretend = 0, frame = 0 + 1840 @ frame_needed = 0, uses_anonymous_args = 0 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** /* Check for DMAMUX Synchronization overrun */ + 1841 .loc 1 584 1 is_stmt 0 view .LVU544 + 1842 0000 10B5 push {r4, lr} + 1843 .LCFI14: + 1844 .cfi_def_cfa_offset 8 + 1845 .cfi_offset 4, -8 + 1846 .cfi_offset 14, -4 + 1847 0002 0446 mov r4, r0 + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1848 .loc 1 586 3 is_stmt 1 view .LVU545 + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1849 .loc 1 586 11 is_stmt 0 view .LVU546 + 1850 0004 436E ldr r3, [r0, #100] + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1851 .loc 1 586 32 view .LVU547 + 1852 0006 1A68 ldr r2, [r3] + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1853 .loc 1 586 44 view .LVU548 + 1854 0008 836E ldr r3, [r0, #104] + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1855 .loc 1 586 5 view .LVU549 + 1856 000a 1A42 tst r2, r3 + 1857 000c 0ED0 beq .L95 + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1858 .loc 1 589 5 is_stmt 1 view .LVU550 + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1859 .loc 1 589 9 is_stmt 0 view .LVU551 + 1860 000e 026E ldr r2, [r0, #96] + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1861 .loc 1 589 30 view .LVU552 + 1862 0010 1368 ldr r3, [r2] + 1863 0012 23F48073 bic r3, r3, #256 + 1864 0016 1360 str r3, [r2] + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1865 .loc 1 592 5 is_stmt 1 view .LVU553 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1866 .loc 1 592 9 is_stmt 0 view .LVU554 + 1867 0018 436E ldr r3, [r0, #100] + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1868 .loc 1 592 42 view .LVU555 + 1869 001a 826E ldr r2, [r0, #104] + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1870 .loc 1 592 36 view .LVU556 + ARM GAS /tmp/ccAxWhFC.s page 55 + + + 1871 001c 5A60 str r2, [r3, #4] + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1872 .loc 1 595 5 is_stmt 1 view .LVU557 + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1873 .loc 1 595 21 is_stmt 0 view .LVU558 + 1874 001e 436D ldr r3, [r0, #84] + 1875 0020 43F40073 orr r3, r3, #512 + 1876 0024 4365 str r3, [r0, #84] + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1877 .loc 1 597 5 is_stmt 1 view .LVU559 + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1878 .loc 1 597 12 is_stmt 0 view .LVU560 + 1879 0026 C36C ldr r3, [r0, #76] + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1880 .loc 1 597 7 view .LVU561 + 1881 0028 03B1 cbz r3, .L95 + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1882 .loc 1 600 7 is_stmt 1 view .LVU562 + 1883 002a 9847 blx r3 + 1884 .LVL92: + 1885 .L95: + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1886 .loc 1 604 3 view .LVU563 + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1887 .loc 1 604 10 is_stmt 0 view .LVU564 + 1888 002c E36E ldr r3, [r4, #108] + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1889 .loc 1 604 5 view .LVU565 + 1890 002e 9BB1 cbz r3, .L94 + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1891 .loc 1 607 5 is_stmt 1 view .LVU566 + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1892 .loc 1 607 13 is_stmt 0 view .LVU567 + 1893 0030 226F ldr r2, [r4, #112] + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1894 .loc 1 607 37 view .LVU568 + 1895 0032 1168 ldr r1, [r2] + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1896 .loc 1 607 50 view .LVU569 + 1897 0034 626F ldr r2, [r4, #116] + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1898 .loc 1 607 7 view .LVU570 + 1899 0036 1142 tst r1, r2 + 1900 0038 0ED0 beq .L94 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1901 .loc 1 610 7 is_stmt 1 view .LVU571 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1902 .loc 1 610 36 is_stmt 0 view .LVU572 + 1903 003a 1A68 ldr r2, [r3] + 1904 003c 22F48072 bic r2, r2, #256 + 1905 0040 1A60 str r2, [r3] + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1906 .loc 1 613 7 is_stmt 1 view .LVU573 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1907 .loc 1 613 11 is_stmt 0 view .LVU574 + 1908 0042 236F ldr r3, [r4, #112] + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccAxWhFC.s page 56 + + + 1909 .loc 1 613 49 view .LVU575 + 1910 0044 626F ldr r2, [r4, #116] + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1911 .loc 1 613 43 view .LVU576 + 1912 0046 5A60 str r2, [r3, #4] + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1913 .loc 1 616 7 is_stmt 1 view .LVU577 + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1914 .loc 1 616 23 is_stmt 0 view .LVU578 + 1915 0048 636D ldr r3, [r4, #84] + 1916 004a 43F48063 orr r3, r3, #1024 + 1917 004e 6365 str r3, [r4, #84] + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1918 .loc 1 618 7 is_stmt 1 view .LVU579 + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1919 .loc 1 618 14 is_stmt 0 view .LVU580 + 1920 0050 E36C ldr r3, [r4, #76] + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** { + 1921 .loc 1 618 9 view .LVU581 + 1922 0052 0BB1 cbz r3, .L94 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** } + 1923 .loc 1 621 9 is_stmt 1 view .LVU582 + 1924 0054 2046 mov r0, r4 + 1925 0056 9847 blx r3 + 1926 .LVL93: + 1927 .L94: + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1928 .loc 1 625 1 is_stmt 0 view .LVU583 + 1929 0058 10BD pop {r4, pc} + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c **** + 1930 .loc 1 625 1 view .LVU584 + 1931 .cfi_endproc + 1932 .LFE148: + 1934 .text + 1935 .Letext0: + 1936 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1937 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1938 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1939 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 1940 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1941 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 1942 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h" + ARM GAS /tmp/ccAxWhFC.s page 57 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_dma_ex.c + /tmp/ccAxWhFC.s:17 .text.DMA_MultiBufferSetConfig:0000000000000000 $t + /tmp/ccAxWhFC.s:24 .text.DMA_MultiBufferSetConfig:0000000000000000 DMA_MultiBufferSetConfig + /tmp/ccAxWhFC.s:194 .text.DMA_MultiBufferSetConfig:00000000000000a0 $d + /tmp/ccAxWhFC.s:200 .text.HAL_DMAEx_MultiBufferStart:0000000000000000 $t + /tmp/ccAxWhFC.s:207 .text.HAL_DMAEx_MultiBufferStart:0000000000000000 HAL_DMAEx_MultiBufferStart + /tmp/ccAxWhFC.s:622 .text.HAL_DMAEx_MultiBufferStart:000000000000020c $d + /tmp/ccAxWhFC.s:629 .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000000 $t + /tmp/ccAxWhFC.s:636 .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000000 HAL_DMAEx_MultiBufferStart_IT + /tmp/ccAxWhFC.s:1050 .text.HAL_DMAEx_MultiBufferStart_IT:0000000000000210 $d + /tmp/ccAxWhFC.s:1055 .text.HAL_DMAEx_MultiBufferStart_IT:000000000000021c $t + /tmp/ccAxWhFC.s:1306 .text.HAL_DMAEx_MultiBufferStart_IT:000000000000038c $d + /tmp/ccAxWhFC.s:1313 .text.HAL_DMAEx_ChangeMemory:0000000000000000 $t + /tmp/ccAxWhFC.s:1320 .text.HAL_DMAEx_ChangeMemory:0000000000000000 HAL_DMAEx_ChangeMemory + /tmp/ccAxWhFC.s:1439 .text.HAL_DMAEx_ChangeMemory:0000000000000080 $d + /tmp/ccAxWhFC.s:1445 .text.HAL_DMAEx_ConfigMuxSync:0000000000000000 $t + /tmp/ccAxWhFC.s:1452 .text.HAL_DMAEx_ConfigMuxSync:0000000000000000 HAL_DMAEx_ConfigMuxSync + /tmp/ccAxWhFC.s:1586 .text.HAL_DMAEx_ConfigMuxRequestGenerator:0000000000000000 $t + /tmp/ccAxWhFC.s:1593 .text.HAL_DMAEx_ConfigMuxRequestGenerator:0000000000000000 HAL_DMAEx_ConfigMuxRequestGenerator + /tmp/ccAxWhFC.s:1719 .text.HAL_DMAEx_EnableMuxRequestGenerator:0000000000000000 $t + /tmp/ccAxWhFC.s:1726 .text.HAL_DMAEx_EnableMuxRequestGenerator:0000000000000000 HAL_DMAEx_EnableMuxRequestGenerator + /tmp/ccAxWhFC.s:1773 .text.HAL_DMAEx_DisableMuxRequestGenerator:0000000000000000 $t + /tmp/ccAxWhFC.s:1780 .text.HAL_DMAEx_DisableMuxRequestGenerator:0000000000000000 HAL_DMAEx_DisableMuxRequestGenerator + /tmp/ccAxWhFC.s:1827 .text.HAL_DMAEx_MUX_IRQHandler:0000000000000000 $t + /tmp/ccAxWhFC.s:1834 .text.HAL_DMAEx_MUX_IRQHandler:0000000000000000 HAL_DMAEx_MUX_IRQHandler + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_dma_ex.o b/build/stm32h7xx_hal_dma_ex.o new file mode 100644 index 0000000..946766a Binary files /dev/null and b/build/stm32h7xx_hal_dma_ex.o differ diff --git a/build/stm32h7xx_hal_exti.d b/build/stm32h7xx_hal_exti.d new file mode 100644 index 0000000..1139d5e --- /dev/null +++ b/build/stm32h7xx_hal_exti.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_exti.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_exti.lst b/build/stm32h7xx_hal_exti.lst new file mode 100644 index 0000000..1438de7 --- /dev/null +++ b/build/stm32h7xx_hal_exti.lst @@ -0,0 +1,2486 @@ +ARM GAS /tmp/cckOoBBj.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_exti.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_EXTI_SetConfigLine,"ax",%progbits + 17 .align 1 + 18 .global HAL_EXTI_SetConfigLine + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_EXTI_SetConfigLine: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @file stm32h7xx_hal_exti.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief EXTI HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * functionalities of the General Purpose Input/Output (EXTI) peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + IO operation functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** @verbatim + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ##### EXTI Peripheral features ##### + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** [..] + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+) Each Exti line can be configured within this driver. + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+) Exti line can be configured in 3 different modes + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Interrupt (CORE1 or CORE2 in case of dual core line ) + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Event (CORE1 or CORE2 in case of dual core line ) + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) a combination of the previous + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+) Configurable Exti lines can be configured with 3 different triggers + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Rising + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Falling + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Both of them + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+) When set in interrupt mode, configurable Exti lines have two diffenrents + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** interrupt pending registers which allow to distinguish which transition + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** occurs: + ARM GAS /tmp/cckOoBBj.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Rising edge pending interrupt + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Falling + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** be selected throught multiplexer. + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure. + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain). + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** Value can be one of the following: + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted : + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** In this case corresponding bit of D2PMRx register is set to 0 + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+++) On a configurable Line : the D3 domain wakeup signal is + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** automatically cleared after after the Delay + Rising Edge detect + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (+++) On a direct Line : the D3 domain wakeup signal is + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** cleared after the direct event input signal is cleared + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted : + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** In this case corresponding bit of D2PMRx register is set to 1 + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** and corresponding bits(2) of D3PCRxL/H is set to b00 : + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** DMA ch6 event selected as D3 domain pendclear source + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted : + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** In this case corresponding bit of D2PMRx register is set to 1 + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** and corresponding bits(2) of D3PCRxL/H is set to b01 : + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** DMA ch7 event selected as D3 domain pendclear source + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted : + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** In this case corresponding bit of D2PMRx register is set to 1 + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** and corresponding bits(2) of D3PCRxL/H is set to b10 : + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** LPTIM4 out selected as D3 domain pendclear source + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted : + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** In this case corresponding bit of D2PMRx register is set to 1 + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** and corresponding bits(2) of D3PCRxL/H is set to b11 : + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** LPTIM5 out selected as D3 domain pendclear source + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ##### How to use this driver ##### + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ============================================================================== + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** [..] + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Choose the interrupt line number by setting "Line" member from + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** EXTI_ConfigTypeDef structure. + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Configure the interrupt and/or event mode using "Mode" member from + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** EXTI_ConfigTypeDef structure. + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) For configurable lines, configure rising and/or falling trigger + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** "Trigger" member from EXTI_ConfigTypeDef structure. + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** member from GPIO_InitTypeDef structure. + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain), + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** choose gpio D3 PendClearSource using PendClearSource + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** member from EXTI_PendClear_Source structure. + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Get current Exti configuration of a dedicated line using + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_EXTI_GetConfigLine(). + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Provide exiting handle as parameter. + ARM GAS /tmp/cckOoBBj.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Provide exiting handle as parameter. + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Provide exiting handle as first parameter. + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Provide which callback will be registered using one value from + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** EXTI_CallbackIDTypeDef. + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (++) Provide callback function pointer. + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** @endverbatim + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ****************************************************************************** + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @attention + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *

© Copyright (c) 2017 STMicroelectronics. + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * All rights reserved.

+ 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This software component is licensed by ST under BSD 3-Clause license, + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * the "License"; You may not use this file except in compliance with the + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * License. You may obtain a copy of the License at: + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * opensource.org/licenses/BSD-3-Clause + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ****************************************************************************** + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/ + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #include "stm32h7xx_hal.h" + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** @addtogroup STM32H7xx_HAL_Driver + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @{ + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** @addtogroup EXTI + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @{ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #ifdef HAL_EXTI_MODULE_ENABLED + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Private typedef -----------------------------------------------------------*/ + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Private defines ------------------------------------------------------------*/ + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** @defgroup EXTI_Private_Constants EXTI Private Constants + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @{ + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers * + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling conf + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @} + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Private macros ------------------------------------------------------------*/ + ARM GAS /tmp/cckOoBBj.s page 4 + + + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Private variables ---------------------------------------------------------*/ + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Exported functions --------------------------------------------------------*/ + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @{ + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group1 + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Configuration functions + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** @verbatim + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** =============================================================================== + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ##### Configuration functions ##### + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** =============================================================================== + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** @endverbatim + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @{ + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Set configuration of a dedicated Exti line. + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param pExtiConfig Pointer on EXTI configuration to be set. + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval HAL Status. + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 29 .loc 1 172 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 33 .loc 1 173 3 view .LVU1 + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t regval; + 34 .loc 1 174 3 view .LVU2 + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t linepos; + 35 .loc 1 175 3 view .LVU3 + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 36 .loc 1 176 3 view .LVU4 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 37 .loc 1 177 3 view .LVU5 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t pcrlinepos; + 38 .loc 1 178 3 view .LVU6 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check null pointer */ + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 39 .loc 1 181 3 view .LVU7 + 40 .loc 1 181 6 is_stmt 0 view .LVU8 + 41 0000 0029 cmp r1, #0 + 42 0002 18BF it ne + 43 0004 0028 cmpne r0, #0 + 44 0006 00F08C80 beq .L15 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 45 .loc 1 172 1 view .LVU9 + 46 000a F0B5 push {r4, r5, r6, r7, lr} + 47 .LCFI0: + ARM GAS /tmp/cckOoBBj.s page 5 + + + 48 .cfi_def_cfa_offset 20 + 49 .cfi_offset 4, -20 + 50 .cfi_offset 5, -16 + 51 .cfi_offset 6, -12 + 52 .cfi_offset 7, -8 + 53 .cfi_offset 14, -4 + 54 000c 0A46 mov r2, r1 + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_ERROR; + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check the parameters */ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + 55 .loc 1 187 3 is_stmt 1 view .LVU10 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + 56 .loc 1 188 3 view .LVU11 + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Assign line number to handle */ + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** hexti->Line = pExtiConfig->Line; + 57 .loc 1 191 3 view .LVU12 + 58 .loc 1 191 28 is_stmt 0 view .LVU13 + 59 000e 0968 ldr r1, [r1] + 60 .LVL1: + 61 .loc 1 191 15 view .LVU14 + 62 0010 0160 str r1, [r0] + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* compute line register offset and line mask */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 63 .loc 1 194 3 is_stmt 1 view .LVU15 + 64 .loc 1 194 10 is_stmt 0 view .LVU16 + 65 0012 C1F3014C ubfx ip, r1, #16, #2 + 66 .LVL2: + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 67 .loc 1 195 3 is_stmt 1 view .LVU17 + 68 .loc 1 195 11 is_stmt 0 view .LVU18 + 69 0016 01F01F0E and lr, r1, #31 + 70 .LVL3: + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << linepos); + 71 .loc 1 196 3 is_stmt 1 view .LVU19 + 72 .loc 1 196 12 is_stmt 0 view .LVU20 + 73 001a 0123 movs r3, #1 + 74 001c 03FA0EF3 lsl r3, r3, lr + 75 .LVL4: + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure triggers for configurable lines */ + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + 76 .loc 1 199 3 is_stmt 1 view .LVU21 + 77 .loc 1 199 6 is_stmt 0 view .LVU22 + 78 0020 11F0007F tst r1, #33554432 + 79 0024 18D0 beq .L3 + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + 80 .loc 1 201 5 is_stmt 1 view .LVU23 + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure rising trigger */ + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 81 .loc 1 204 5 view .LVU24 + ARM GAS /tmp/cckOoBBj.s page 6 + + + 82 .loc 1 204 15 is_stmt 0 view .LVU25 + 83 0026 4FEA4C10 lsl r0, ip, #5 + 84 .LVL5: + 85 .loc 1 204 13 view .LVU26 + 86 002a 00F1B046 add r6, r0, #1476395008 + 87 .LVL6: + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 88 .loc 1 205 5 is_stmt 1 view .LVU27 + 89 .loc 1 205 12 is_stmt 0 view .LVU28 + 90 002e 3468 ldr r4, [r6] + 91 .LVL7: + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Mask or set line */ + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U) + 92 .loc 1 208 5 is_stmt 1 view .LVU29 + 93 .loc 1 208 21 is_stmt 0 view .LVU30 + 94 0030 9568 ldr r5, [r2, #8] + 95 .loc 1 208 8 view .LVU31 + 96 0032 15F0010F tst r5, #1 + 97 0036 29D0 beq .L4 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 98 .loc 1 210 7 is_stmt 1 view .LVU32 + 99 .loc 1 210 14 is_stmt 0 view .LVU33 + 100 0038 1C43 orrs r4, r4, r3 + 101 .LVL8: + 102 .L5: + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store rising trigger mode */ + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 103 .loc 1 218 5 is_stmt 1 view .LVU34 + 104 .loc 1 218 14 is_stmt 0 view .LVU35 + 105 003a 3460 str r4, [r6] + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure falling trigger */ + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 106 .loc 1 221 5 is_stmt 1 view .LVU36 + 107 .loc 1 221 13 is_stmt 0 view .LVU37 + 108 003c 3A4E ldr r6, .L23 + 109 .LVL9: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 110 .loc 1 222 5 is_stmt 1 view .LVU38 + 111 .loc 1 222 12 is_stmt 0 view .LVU39 + 112 003e 8459 ldr r4, [r0, r6] + 113 .LVL10: + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Mask or set line */ + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U) + 114 .loc 1 225 5 is_stmt 1 view .LVU40 + 115 .loc 1 225 21 is_stmt 0 view .LVU41 + 116 0040 9568 ldr r5, [r2, #8] + 117 .loc 1 225 8 view .LVU42 + ARM GAS /tmp/cckOoBBj.s page 7 + + + 118 0042 15F0020F tst r5, #2 + 119 0046 24D0 beq .L6 + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 120 .loc 1 227 7 is_stmt 1 view .LVU43 + 121 .loc 1 227 14 is_stmt 0 view .LVU44 + 122 0048 1C43 orrs r4, r4, r3 + 123 .LVL11: + 124 .L7: + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store falling trigger mode */ + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 125 .loc 1 235 5 is_stmt 1 view .LVU45 + 126 .loc 1 235 14 is_stmt 0 view .LVU46 + 127 004a 8451 str r4, [r0, r6] + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure gpio port selection in case of gpio exti line */ + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 128 .loc 1 238 5 is_stmt 1 view .LVU47 + 129 .loc 1 238 21 is_stmt 0 view .LVU48 + 130 004c 1068 ldr r0, [r2] + 131 .LVL12: + 132 .loc 1 238 28 view .LVU49 + 133 004e 00F0C060 and r0, r0, #100663296 + 134 .loc 1 238 8 view .LVU50 + 135 0052 B0F1C06F cmp r0, #100663296 + 136 0056 1FD0 beq .L21 + 137 .LVL13: + 138 .L3: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure interrupt mode : read current mode */ + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + 139 .loc 1 251 3 is_stmt 1 view .LVU51 + 140 .loc 1 251 13 is_stmt 0 view .LVU52 + 141 0058 4FEA0C10 lsl r0, ip, #4 + 142 .loc 1 251 11 view .LVU53 + 143 005c 334E ldr r6, .L23+4 + 144 .LVL14: + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 145 .loc 1 252 3 is_stmt 1 view .LVU54 + 146 .loc 1 252 10 is_stmt 0 view .LVU55 + 147 005e 8459 ldr r4, [r0, r6] + ARM GAS /tmp/cckOoBBj.s page 8 + + + 148 .LVL15: + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Mask or set line */ + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U) + 149 .loc 1 255 3 is_stmt 1 view .LVU56 + 150 .loc 1 255 19 is_stmt 0 view .LVU57 + 151 0060 5568 ldr r5, [r2, #4] + 152 .loc 1 255 6 view .LVU58 + 153 0062 15F0010F tst r5, #1 + 154 0066 2AD0 beq .L8 + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 155 .loc 1 257 5 is_stmt 1 view .LVU59 + 156 .loc 1 257 12 is_stmt 0 view .LVU60 + 157 0068 1C43 orrs r4, r4, r3 + 158 .LVL16: + 159 .L9: + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store interrupt mode */ + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 160 .loc 1 265 3 is_stmt 1 view .LVU61 + 161 .loc 1 265 12 is_stmt 0 view .LVU62 + 162 006a 8451 str r4, [r0, r6] + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* The event mode cannot be configured if the line does not support it */ + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_ + 163 .loc 1 268 3 is_stmt 1 view .LVU63 + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure event mode : read current mode */ + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + 164 .loc 1 271 3 view .LVU64 + 165 .loc 1 271 11 is_stmt 0 view .LVU65 + 166 006c 304D ldr r5, .L23+8 + 167 .LVL17: + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 168 .loc 1 272 3 is_stmt 1 view .LVU66 + 169 .loc 1 272 10 is_stmt 0 view .LVU67 + 170 006e 4459 ldr r4, [r0, r5] + 171 .LVL18: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Mask or set line */ + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U) + 172 .loc 1 275 3 is_stmt 1 view .LVU68 + 173 .loc 1 275 6 is_stmt 0 view .LVU69 + 174 0070 5668 ldr r6, [r2, #4] + 175 0072 16F0020F tst r6, #2 + 176 0076 25D0 beq .L10 + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 177 .loc 1 277 5 is_stmt 1 view .LVU70 + 178 .loc 1 277 12 is_stmt 0 view .LVU71 + 179 0078 1C43 orrs r4, r4, r3 + ARM GAS /tmp/cckOoBBj.s page 9 + + + 180 .LVL19: + 181 .L11: + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store event mode */ + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 182 .loc 1 285 3 is_stmt 1 view .LVU72 + 183 .loc 1 285 12 is_stmt 0 view .LVU73 + 184 007a 4451 str r4, [r0, r5] + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #if defined (DUAL_CORE) + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure interrupt mode for Core2 : read current mode */ + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Mask or set line */ + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U) + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store interrupt mode */ + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* The event mode cannot be configured if the line does not support it */ + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_ + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure event mode : read current mode */ + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Mask or set line */ + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U) + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store event mode */ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #endif /* DUAL_CORE */ + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Configure the D3 PendClear source in case of Wakeup target is Any */ + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + 185 .loc 1 327 3 is_stmt 1 view .LVU74 + 186 .loc 1 327 19 is_stmt 0 view .LVU75 + ARM GAS /tmp/cckOoBBj.s page 10 + + + 187 007c 1068 ldr r0, [r2] + 188 .LVL20: + 189 .loc 1 327 26 view .LVU76 + 190 007e 00F44010 and r0, r0, #3145728 + 191 .loc 1 327 6 view .LVU77 + 192 0082 B0F5401F cmp r0, #3145728 + 193 0086 20D0 beq .L22 + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource)); + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /*Calc the PMR register address for the given line */ + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE) + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Clear D3PMRx register for the given line */ + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~maskline; + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store D3PMRx register value */ + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Set D3PMRx register to 1 for the given line */ + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= maskline; + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store D3PMRx register value */ + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(linepos < 16UL) + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiC + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_OK; + 194 .loc 1 365 10 view .LVU78 + 195 0088 0020 movs r0, #0 + 196 .LVL21: + 197 .L2: + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 198 .loc 1 366 1 view .LVU79 + 199 008a F0BD pop {r4, r5, r6, r7, pc} + 200 .LVL22: + 201 .L4: + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 202 .loc 1 214 7 is_stmt 1 view .LVU80 + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + ARM GAS /tmp/cckOoBBj.s page 11 + + + 203 .loc 1 214 14 is_stmt 0 view .LVU81 + 204 008c 24EA0304 bic r4, r4, r3 + 205 .LVL23: + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 206 .loc 1 214 14 view .LVU82 + 207 0090 D3E7 b .L5 + 208 .LVL24: + 209 .L6: + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 210 .loc 1 231 7 is_stmt 1 view .LVU83 + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 211 .loc 1 231 14 is_stmt 0 view .LVU84 + 212 0092 24EA0304 bic r4, r4, r3 + 213 .LVL25: + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 214 .loc 1 231 14 view .LVU85 + 215 0096 D8E7 b .L7 + 216 .LVL26: + 217 .L21: + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 218 .loc 1 240 7 is_stmt 1 view .LVU86 + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 219 .loc 1 241 7 view .LVU87 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 220 .loc 1 243 7 view .LVU88 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 221 .loc 1 243 47 is_stmt 0 view .LVU89 + 222 0098 CEF38100 ubfx r0, lr, #2, #2 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 223 .loc 1 243 14 view .LVU90 + 224 009c 254F ldr r7, .L23+12 + 225 009e 0230 adds r0, r0, #2 + 226 00a0 57F82060 ldr r6, [r7, r0, lsl #2] + 227 .LVL27: + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 228 .loc 1 244 7 is_stmt 1 view .LVU91 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 229 .loc 1 244 80 is_stmt 0 view .LVU92 + 230 00a4 01F00304 and r4, r1, #3 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 231 .loc 1 244 69 view .LVU93 + 232 00a8 A500 lsls r5, r4, #2 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 233 .loc 1 244 40 view .LVU94 + 234 00aa 0F24 movs r4, #15 + 235 00ac AC40 lsls r4, r4, r5 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + 236 .loc 1 244 14 view .LVU95 + 237 00ae 26EA0406 bic r6, r6, r4 + 238 .LVL28: + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 239 .loc 1 245 7 is_stmt 1 view .LVU96 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 240 .loc 1 245 29 is_stmt 0 view .LVU97 + 241 00b2 D468 ldr r4, [r2, #12] + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 242 .loc 1 245 39 view .LVU98 + ARM GAS /tmp/cckOoBBj.s page 12 + + + 243 00b4 AC40 lsls r4, r4, r5 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 244 .loc 1 245 14 view .LVU99 + 245 00b6 3443 orrs r4, r4, r6 + 246 .LVL29: + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 247 .loc 1 246 7 is_stmt 1 view .LVU100 + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 248 .loc 1 246 48 is_stmt 0 view .LVU101 + 249 00b8 47F82040 str r4, [r7, r0, lsl #2] + 250 00bc CCE7 b .L3 + 251 .LVL30: + 252 .L8: + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 253 .loc 1 261 5 is_stmt 1 view .LVU102 + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 254 .loc 1 261 12 is_stmt 0 view .LVU103 + 255 00be 24EA0304 bic r4, r4, r3 + 256 .LVL31: + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 257 .loc 1 261 12 view .LVU104 + 258 00c2 D2E7 b .L9 + 259 .LVL32: + 260 .L10: + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 261 .loc 1 281 5 is_stmt 1 view .LVU105 + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 262 .loc 1 281 12 is_stmt 0 view .LVU106 + 263 00c4 24EA0304 bic r4, r4, r3 + 264 .LVL33: + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 265 .loc 1 281 12 view .LVU107 + 266 00c8 D7E7 b .L11 + 267 .LVL34: + 268 .L22: + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 269 .loc 1 329 5 is_stmt 1 view .LVU108 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 270 .loc 1 332 5 view .LVU109 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 271 .loc 1 332 15 is_stmt 0 view .LVU110 + 272 00ca 4FEA4C1C lsl ip, ip, #5 + 273 .LVL35: + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 274 .loc 1 332 13 view .LVU111 + 275 00ce 1A4C ldr r4, .L23+16 + 276 .LVL36: + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 277 .loc 1 333 5 is_stmt 1 view .LVU112 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 278 .loc 1 333 12 is_stmt 0 view .LVU113 + 279 00d0 5CF80400 ldr r0, [ip, r4] + 280 .LVL37: + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 281 .loc 1 335 5 is_stmt 1 view .LVU114 + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 282 .loc 1 335 19 is_stmt 0 view .LVU115 + ARM GAS /tmp/cckOoBBj.s page 13 + + + 283 00d4 1569 ldr r5, [r2, #16] + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 284 .loc 1 335 7 view .LVU116 + 285 00d6 2DB9 cbnz r5, .L12 + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store D3PMRx register value */ + 286 .loc 1 338 7 is_stmt 1 view .LVU117 + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store D3PMRx register value */ + 287 .loc 1 338 14 is_stmt 0 view .LVU118 + 288 00d8 20EA0303 bic r3, r0, r3 + 289 .LVL38: + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 290 .loc 1 340 7 is_stmt 1 view .LVU119 + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 291 .loc 1 340 16 is_stmt 0 view .LVU120 + 292 00dc 4CF80430 str r3, [ip, r4] + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 293 .loc 1 365 10 view .LVU121 + 294 00e0 0020 movs r0, #0 + 295 00e2 D2E7 b .L2 + 296 .LVL39: + 297 .L12: + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store D3PMRx register value */ + 298 .loc 1 345 7 is_stmt 1 view .LVU122 + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store D3PMRx register value */ + 299 .loc 1 345 14 is_stmt 0 view .LVU123 + 300 00e4 1843 orrs r0, r0, r3 + 301 .LVL40: + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 302 .loc 1 347 7 is_stmt 1 view .LVU124 + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 303 .loc 1 347 16 is_stmt 0 view .LVU125 + 304 00e6 4CF80400 str r0, [ip, r4] + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 305 .loc 1 349 7 is_stmt 1 view .LVU126 + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 306 .loc 1 349 9 is_stmt 0 view .LVU127 + 307 00ea 11F0100F tst r1, #16 + 308 00ee 10D1 bne .L13 + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 309 .loc 1 351 9 is_stmt 1 view .LVU128 + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 310 .loc 1 351 17 is_stmt 0 view .LVU129 + 311 00f0 1248 ldr r0, .L23+20 + 312 .LVL41: + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 313 .loc 1 351 17 view .LVU130 + 314 00f2 6044 add r0, r0, ip + 315 .LVL42: + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 316 .loc 1 352 9 is_stmt 1 view .LVU131 + 317 .L14: + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 318 .loc 1 360 7 view .LVU132 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 319 .loc 1 360 17 is_stmt 0 view .LVU133 + 320 00f4 0168 ldr r1, [r0] + 321 .LVL43: + ARM GAS /tmp/cckOoBBj.s page 14 + + + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 322 .loc 1 360 42 view .LVU134 + 323 00f6 03FB03F3 mul r3, r3, r3 + 324 .LVL44: + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 325 .loc 1 360 55 view .LVU135 + 326 00fa 03EB4304 add r4, r3, r3, lsl #1 + 327 .LVL45: + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 328 .loc 1 360 26 view .LVU136 + 329 00fe 21EA0401 bic r1, r1, r4 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 330 .loc 1 360 105 view .LVU137 + 331 0102 1269 ldr r2, [r2, #16] + 332 .LVL46: + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 333 .loc 1 360 123 view .LVU138 + 334 0104 013A subs r2, r2, #1 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 335 .loc 1 360 91 view .LVU139 + 336 0106 02FB03F3 mul r3, r2, r3 + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 337 .loc 1 360 14 view .LVU140 + 338 010a 0B43 orrs r3, r3, r1 + 339 .LVL47: + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 340 .loc 1 361 7 is_stmt 1 view .LVU141 + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 341 .loc 1 361 16 is_stmt 0 view .LVU142 + 342 010c 0360 str r3, [r0] + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 343 .loc 1 365 10 view .LVU143 + 344 010e 0020 movs r0, #0 + 345 .LVL48: + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 346 .loc 1 365 10 view .LVU144 + 347 0110 BBE7 b .L2 + 348 .LVL49: + 349 .L13: + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 350 .loc 1 356 9 is_stmt 1 view .LVU145 + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 351 .loc 1 356 17 is_stmt 0 view .LVU146 + 352 0112 0B48 ldr r0, .L23+24 + 353 .LVL50: + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 354 .loc 1 356 17 view .LVU147 + 355 0114 6044 add r0, r0, ip + 356 .LVL51: + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 357 .loc 1 357 9 is_stmt 1 view .LVU148 + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 358 .loc 1 357 38 is_stmt 0 view .LVU149 + 359 0116 AEF1100E sub lr, lr, #16 + 360 .LVL52: + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 361 .loc 1 357 20 view .LVU150 + ARM GAS /tmp/cckOoBBj.s page 15 + + + 362 011a 0123 movs r3, #1 + 363 .LVL53: + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 364 .loc 1 357 20 view .LVU151 + 365 011c 03FA0EF3 lsl r3, r3, lr + 366 .LVL54: + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 367 .loc 1 357 20 view .LVU152 + 368 0120 E8E7 b .L14 + 369 .LVL55: + 370 .L15: + 371 .LCFI1: + 372 .cfi_def_cfa_offset 0 + 373 .cfi_restore 4 + 374 .cfi_restore 5 + 375 .cfi_restore 6 + 376 .cfi_restore 7 + 377 .cfi_restore 14 + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 378 .loc 1 183 12 view .LVU153 + 379 0122 0120 movs r0, #1 + 380 .LVL56: + 381 .loc 1 366 1 view .LVU154 + 382 0124 7047 bx lr + 383 .L24: + 384 0126 00BF .align 2 + 385 .L23: + 386 0128 04000058 .word 1476395012 + 387 012c 80000058 .word 1476395136 + 388 0130 84000058 .word 1476395140 + 389 0134 00040058 .word 1476396032 + 390 0138 0C000058 .word 1476395020 + 391 013c 10000058 .word 1476395024 + 392 0140 14000058 .word 1476395028 + 393 .cfi_endproc + 394 .LFE141: + 396 .section .text.HAL_EXTI_GetConfigLine,"ax",%progbits + 397 .align 1 + 398 .global HAL_EXTI_GetConfigLine + 399 .syntax unified + 400 .thumb + 401 .thumb_func + 402 .fpu fpv5-d16 + 404 HAL_EXTI_GetConfigLine: + 405 .LVL57: + 406 .LFB142: + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Get configuration of a dedicated Exti line. + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param pExtiConfig Pointer on structure to store Exti configuration. + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval HAL Status. + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 407 .loc 1 376 1 is_stmt 1 view -0 + ARM GAS /tmp/cckOoBBj.s page 16 + + + 408 .cfi_startproc + 409 @ args = 0, pretend = 0, frame = 0 + 410 @ frame_needed = 0, uses_anonymous_args = 0 + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 411 .loc 1 377 3 view .LVU156 + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t regval; + 412 .loc 1 378 3 view .LVU157 + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t linepos; + 413 .loc 1 379 3 view .LVU158 + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 414 .loc 1 380 3 view .LVU159 + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 415 .loc 1 381 3 view .LVU160 + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t pcrlinepos; + 416 .loc 1 382 3 view .LVU161 + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check null pointer */ + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 417 .loc 1 385 3 view .LVU162 + 418 .loc 1 385 6 is_stmt 0 view .LVU163 + 419 0000 0029 cmp r1, #0 + 420 0002 18BF it ne + 421 0004 0028 cmpne r0, #0 + 422 0006 78D0 beq .L39 + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 423 .loc 1 376 1 view .LVU164 + 424 0008 30B5 push {r4, r5, lr} + 425 .LCFI2: + 426 .cfi_def_cfa_offset 12 + 427 .cfi_offset 4, -12 + 428 .cfi_offset 5, -8 + 429 .cfi_offset 14, -4 + 430 000a 0B46 mov r3, r1 + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_ERROR; + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check the parameter */ + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 431 .loc 1 391 3 is_stmt 1 view .LVU165 + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store handle line number to configuration structure */ + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Line = hexti->Line; + 432 .loc 1 394 3 view .LVU166 + 433 .loc 1 394 28 is_stmt 0 view .LVU167 + 434 000c 0168 ldr r1, [r0] + 435 .LVL58: + 436 .loc 1 394 21 view .LVU168 + 437 000e 1960 str r1, [r3] + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* compute line register offset and line mask */ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 438 .loc 1 397 3 is_stmt 1 view .LVU169 + 439 .loc 1 397 10 is_stmt 0 view .LVU170 + 440 0010 C1F30140 ubfx r0, r1, #16, #2 + 441 .LVL59: + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + ARM GAS /tmp/cckOoBBj.s page 17 + + + 442 .loc 1 398 3 is_stmt 1 view .LVU171 + 443 .loc 1 398 11 is_stmt 0 view .LVU172 + 444 0014 01F01F0E and lr, r1, #31 + 445 .LVL60: + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << linepos); + 446 .loc 1 399 3 is_stmt 1 view .LVU173 + 447 .loc 1 399 12 is_stmt 0 view .LVU174 + 448 0018 0122 movs r2, #1 + 449 001a 02FA0EF2 lsl r2, r2, lr + 450 .LVL61: + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 1] Get core mode : interrupt */ + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + 451 .loc 1 402 3 is_stmt 1 view .LVU175 + 452 .loc 1 402 13 is_stmt 0 view .LVU176 + 453 001e 4FEA001C lsl ip, r0, #4 + 454 .loc 1 402 11 view .LVU177 + 455 0022 374C ldr r4, .L46 + 456 .LVL62: + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 457 .loc 1 403 3 is_stmt 1 view .LVU178 + 458 .loc 1 403 10 is_stmt 0 view .LVU179 + 459 0024 5CF80440 ldr r4, [ip, r4] + 460 .LVL63: + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_NONE; + 461 .loc 1 405 3 is_stmt 1 view .LVU180 + 462 .loc 1 405 21 is_stmt 0 view .LVU181 + 463 0028 0025 movs r5, #0 + 464 002a 5D60 str r5, [r3, #4] + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check if selected line is enable */ + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((regval & maskline) != 0x00U) + 465 .loc 1 408 3 is_stmt 1 view .LVU182 + 466 .loc 1 408 6 is_stmt 0 view .LVU183 + 467 002c 2242 tst r2, r4 + 468 002e 01D0 beq .L27 + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + 469 .loc 1 410 5 is_stmt 1 view .LVU184 + 470 .loc 1 410 23 is_stmt 0 view .LVU185 + 471 0030 0124 movs r4, #1 + 472 .LVL64: + 473 .loc 1 410 23 view .LVU186 + 474 0032 5C60 str r4, [r3, #4] + 475 .L27: + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get event mode */ + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + 476 .loc 1 414 3 is_stmt 1 view .LVU187 + 477 .loc 1 414 11 is_stmt 0 view .LVU188 + 478 0034 334C ldr r4, .L46+4 + 479 .LVL65: + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 480 .loc 1 415 3 is_stmt 1 view .LVU189 + 481 .loc 1 415 10 is_stmt 0 view .LVU190 + ARM GAS /tmp/cckOoBBj.s page 18 + + + 482 0036 5CF80440 ldr r4, [ip, r4] + 483 .LVL66: + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check if selected line is enable */ + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((regval & maskline) != 0x00U) + 484 .loc 1 418 3 is_stmt 1 view .LVU191 + 485 .loc 1 418 6 is_stmt 0 view .LVU192 + 486 003a 2242 tst r2, r4 + 487 003c 03D0 beq .L28 + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Mode |= EXTI_MODE_EVENT; + 488 .loc 1 420 5 is_stmt 1 view .LVU193 + 489 .loc 1 420 23 is_stmt 0 view .LVU194 + 490 003e 5C68 ldr r4, [r3, #4] + 491 .LVL67: + 492 .loc 1 420 23 view .LVU195 + 493 0040 44F00204 orr r4, r4, #2 + 494 0044 5C60 str r4, [r3, #4] + 495 .L28: + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #if defined (DUAL_CORE) + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check if selected line is enable */ + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((regval & maskline) != 0x00U) + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT; + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get event mode */ + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check if selected line is enable */ + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((regval & maskline) != 0x00U) + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT; + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #endif /*DUAL_CORE*/ + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 2] Get trigger for configurable lines : rising */ + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + 496 .loc 1 444 3 is_stmt 1 view .LVU196 + 497 .loc 1 444 6 is_stmt 0 view .LVU197 + 498 0046 11F0007F tst r1, #33554432 + 499 004a 29D0 beq .L29 + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 500 .loc 1 446 5 is_stmt 1 view .LVU198 + 501 .loc 1 446 15 is_stmt 0 view .LVU199 + 502 004c 4401 lsls r4, r0, #5 + 503 .loc 1 446 13 view .LVU200 + 504 004e 04F1B045 add r5, r4, #1476395008 + 505 .LVL68: + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 506 .loc 1 447 5 is_stmt 1 view .LVU201 + ARM GAS /tmp/cckOoBBj.s page 19 + + + 507 .loc 1 447 12 is_stmt 0 view .LVU202 + 508 0052 2D68 ldr r5, [r5] + 509 .LVL69: + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((regval & maskline) != 0x00U) + 510 .loc 1 450 5 is_stmt 1 view .LVU203 + 511 .loc 1 450 8 is_stmt 0 view .LVU204 + 512 0054 2A42 tst r2, r5 + 513 0056 11D0 beq .L30 + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + 514 .loc 1 452 7 is_stmt 1 view .LVU205 + 515 .loc 1 452 28 is_stmt 0 view .LVU206 + 516 0058 0125 movs r5, #1 + 517 .LVL70: + 518 .loc 1 452 28 view .LVU207 + 519 005a 9D60 str r5, [r3, #8] + 520 .L31: + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get falling configuration */ + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 521 .loc 1 460 5 is_stmt 1 view .LVU208 + 522 .loc 1 460 13 is_stmt 0 view .LVU209 + 523 005c 2A4D ldr r5, .L46+8 + 524 .LVL71: + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = *regaddr; + 525 .loc 1 461 5 is_stmt 1 view .LVU210 + 526 .loc 1 461 12 is_stmt 0 view .LVU211 + 527 005e 6459 ldr r4, [r4, r5] + 528 .LVL72: + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((regval & maskline) != 0x00U) + 529 .loc 1 464 5 is_stmt 1 view .LVU212 + 530 .loc 1 464 8 is_stmt 0 view .LVU213 + 531 0060 2242 tst r2, r4 + 532 0062 03D0 beq .L32 + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + 533 .loc 1 466 7 is_stmt 1 view .LVU214 + 534 .loc 1 466 28 is_stmt 0 view .LVU215 + 535 0064 9C68 ldr r4, [r3, #8] + 536 .LVL73: + 537 .loc 1 466 28 view .LVU216 + 538 0066 44F00204 orr r4, r4, #2 + 539 006a 9C60 str r4, [r3, #8] + 540 .L32: + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + ARM GAS /tmp/cckOoBBj.s page 20 + + + 541 .loc 1 470 5 is_stmt 1 view .LVU217 + 542 .loc 1 470 28 is_stmt 0 view .LVU218 + 543 006c 01F0C064 and r4, r1, #100663296 + 544 .loc 1 470 8 view .LVU219 + 545 0070 B4F1C06F cmp r4, #100663296 + 546 0074 05D0 beq .L44 + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) > + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00U; + 547 .loc 1 479 7 is_stmt 1 view .LVU220 + 548 .loc 1 479 28 is_stmt 0 view .LVU221 + 549 0076 0024 movs r4, #0 + 550 0078 DC60 str r4, [r3, #12] + 551 007a 14E0 b .L34 + 552 .LVL74: + 553 .L30: + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 554 .loc 1 456 7 is_stmt 1 view .LVU222 + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 555 .loc 1 456 28 is_stmt 0 view .LVU223 + 556 007c 0025 movs r5, #0 + 557 .LVL75: + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 558 .loc 1 456 28 view .LVU224 + 559 007e 9D60 str r5, [r3, #8] + 560 0080 ECE7 b .L31 + 561 .LVL76: + 562 .L44: + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 563 .loc 1 472 7 is_stmt 1 view .LVU225 + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) > + 564 .loc 1 474 7 view .LVU226 + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) > + 565 .loc 1 474 47 is_stmt 0 view .LVU227 + 566 0082 CEF38104 ubfx r4, lr, #2, #2 + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) > + 567 .loc 1 474 14 view .LVU228 + 568 0086 0234 adds r4, r4, #2 + 569 0088 204D ldr r5, .L46+12 + 570 .LVL77: + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) > + 571 .loc 1 474 14 view .LVU229 + 572 008a 55F82440 ldr r4, [r5, r4, lsl #2] + 573 .LVL78: + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 574 .loc 1 475 7 is_stmt 1 view .LVU230 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 575 .loc 1 475 75 is_stmt 0 view .LVU231 + 576 008e 6FEA0E05 mvn r5, lr + 577 0092 05F00305 and r5, r5, #3 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + ARM GAS /tmp/cckOoBBj.s page 21 + + + 578 .loc 1 475 68 view .LVU232 + 579 0096 AD00 lsls r5, r5, #2 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 580 .loc 1 475 39 view .LVU233 + 581 0098 AC40 lsls r4, r4, r5 + 582 .LVL79: + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 583 .loc 1 475 99 view .LVU234 + 584 009a 240E lsrs r4, r4, #24 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 585 .loc 1 475 28 view .LVU235 + 586 009c DC60 str r4, [r3, #12] + 587 009e 02E0 b .L34 + 588 .LVL80: + 589 .L29: + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + 590 .loc 1 484 5 is_stmt 1 view .LVU236 + 591 .loc 1 484 26 is_stmt 0 view .LVU237 + 592 00a0 0024 movs r4, #0 + 593 00a2 9C60 str r4, [r3, #8] + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00U; + 594 .loc 1 485 5 is_stmt 1 view .LVU238 + 595 .loc 1 485 26 is_stmt 0 view .LVU239 + 596 00a4 DC60 str r4, [r3, #12] + 597 .LVL81: + 598 .L34: + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 3] Get D3 Pend Clear source */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + 599 .loc 1 489 3 is_stmt 1 view .LVU240 + 600 .loc 1 489 26 is_stmt 0 view .LVU241 + 601 00a6 01F4401C and ip, r1, #3145728 + 602 .loc 1 489 6 view .LVU242 + 603 00aa BCF5401F cmp ip, #3145728 + 604 00ae 02D0 beq .L45 + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(((*regaddr) & linepos) == 0UL) + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* if PMR unset, then no pend clear source is used */ + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */ + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(linepos < 16UL) + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + ARM GAS /tmp/cckOoBBj.s page 22 + + + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrline + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* if line wakeup target is not any, then no pend clear source is used */ + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; + 605 .loc 1 517 5 is_stmt 1 view .LVU243 + 606 .loc 1 517 34 is_stmt 0 view .LVU244 + 607 00b0 0020 movs r0, #0 + 608 .LVL82: + 609 .loc 1 517 34 view .LVU245 + 610 00b2 1861 str r0, [r3, #16] + 611 .LVL83: + 612 .L26: + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_OK; + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 613 .loc 1 521 1 view .LVU246 + 614 00b4 30BD pop {r4, r5, pc} + 615 .LVL84: + 616 .L45: + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(((*regaddr) & linepos) == 0UL) + 617 .loc 1 491 5 is_stmt 1 view .LVU247 + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(((*regaddr) & linepos) == 0UL) + 618 .loc 1 491 15 is_stmt 0 view .LVU248 + 619 00b6 4001 lsls r0, r0, #5 + 620 .LVL85: + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(((*regaddr) & linepos) == 0UL) + 621 .loc 1 491 13 view .LVU249 + 622 00b8 154C ldr r4, .L46+16 + 623 .LVL86: + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 624 .loc 1 492 5 is_stmt 1 view .LVU250 + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 625 .loc 1 492 10 is_stmt 0 view .LVU251 + 626 00ba 0459 ldr r4, [r0, r4] + 627 .LVL87: + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 628 .loc 1 492 7 view .LVU252 + 629 00bc 14EA0E0F tst r4, lr + 630 00c0 02D1 bne .L36 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 631 .loc 1 495 7 is_stmt 1 view .LVU253 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 632 .loc 1 495 36 is_stmt 0 view .LVU254 + 633 00c2 0020 movs r0, #0 + 634 .LVL88: + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 635 .loc 1 495 36 view .LVU255 + 636 00c4 1861 str r0, [r3, #16] + 637 00c6 F5E7 b .L26 + ARM GAS /tmp/cckOoBBj.s page 23 + + + 638 .LVL89: + 639 .L36: + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 640 .loc 1 500 7 is_stmt 1 view .LVU256 + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 641 .loc 1 500 9 is_stmt 0 view .LVU257 + 642 00c8 11F0100F tst r1, #16 + 643 00cc 0DD1 bne .L37 + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 644 .loc 1 502 9 is_stmt 1 view .LVU258 + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 645 .loc 1 502 17 is_stmt 0 view .LVU259 + 646 00ce 1149 ldr r1, .L46+20 + 647 .LVL90: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 648 .loc 1 502 17 view .LVU260 + 649 00d0 0144 add r1, r1, r0 + 650 .LVL91: + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 651 .loc 1 503 9 is_stmt 1 view .LVU261 + 652 .L38: + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 653 .loc 1 511 7 view .LVU262 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 654 .loc 1 511 46 is_stmt 0 view .LVU263 + 655 00d2 0968 ldr r1, [r1] + 656 .LVL92: + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 657 .loc 1 511 69 view .LVU264 + 658 00d4 02FB02F2 mul r2, r2, r2 + 659 .LVL93: + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 660 .loc 1 511 82 view .LVU265 + 661 00d8 02EB4200 add r0, r2, r2, lsl #1 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 662 .loc 1 511 55 view .LVU266 + 663 00dc 0140 ands r1, r1, r0 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 664 .loc 1 511 90 view .LVU267 + 665 00de B1FBF2F2 udiv r2, r1, r2 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 666 .loc 1 511 42 view .LVU268 + 667 00e2 0132 adds r2, r2, #1 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 668 .loc 1 511 36 view .LVU269 + 669 00e4 1A61 str r2, [r3, #16] + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 670 .loc 1 520 10 view .LVU270 + 671 00e6 0020 movs r0, #0 + 672 00e8 E4E7 b .L26 + 673 .LVL94: + 674 .L37: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 675 .loc 1 507 9 is_stmt 1 view .LVU271 + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 676 .loc 1 507 17 is_stmt 0 view .LVU272 + 677 00ea 0B49 ldr r1, .L46+24 + ARM GAS /tmp/cckOoBBj.s page 24 + + + 678 .LVL95: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 679 .loc 1 507 17 view .LVU273 + 680 00ec 0144 add r1, r1, r0 + 681 .LVL96: + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 682 .loc 1 508 9 is_stmt 1 view .LVU274 + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 683 .loc 1 508 38 is_stmt 0 view .LVU275 + 684 00ee AEF1100E sub lr, lr, #16 + 685 .LVL97: + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 686 .loc 1 508 20 view .LVU276 + 687 00f2 0122 movs r2, #1 + 688 .LVL98: + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 689 .loc 1 508 20 view .LVU277 + 690 00f4 02FA0EF2 lsl r2, r2, lr + 691 .LVL99: + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 692 .loc 1 508 20 view .LVU278 + 693 00f8 EBE7 b .L38 + 694 .LVL100: + 695 .L39: + 696 .LCFI3: + 697 .cfi_def_cfa_offset 0 + 698 .cfi_restore 4 + 699 .cfi_restore 5 + 700 .cfi_restore 14 + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 701 .loc 1 387 12 view .LVU279 + 702 00fa 0120 movs r0, #1 + 703 .LVL101: + 704 .loc 1 521 1 view .LVU280 + 705 00fc 7047 bx lr + 706 .L47: + 707 00fe 00BF .align 2 + 708 .L46: + 709 0100 80000058 .word 1476395136 + 710 0104 84000058 .word 1476395140 + 711 0108 04000058 .word 1476395012 + 712 010c 00040058 .word 1476396032 + 713 0110 0C000058 .word 1476395020 + 714 0114 10000058 .word 1476395024 + 715 0118 14000058 .word 1476395028 + 716 .cfi_endproc + 717 .LFE142: + 719 .section .text.HAL_EXTI_ClearConfigLine,"ax",%progbits + 720 .align 1 + 721 .global HAL_EXTI_ClearConfigLine + 722 .syntax unified + 723 .thumb + 724 .thumb_func + 725 .fpu fpv5-d16 + 727 HAL_EXTI_ClearConfigLine: + 728 .LVL102: + 729 .LFB143: + ARM GAS /tmp/cckOoBBj.s page 25 + + + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Clear whole configuration of a dedicated Exti line. + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval HAL Status. + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 730 .loc 1 530 1 is_stmt 1 view -0 + 731 .cfi_startproc + 732 @ args = 0, pretend = 0, frame = 0 + 733 @ frame_needed = 0, uses_anonymous_args = 0 + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 734 .loc 1 531 3 view .LVU282 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t regval; + 735 .loc 1 532 3 view .LVU283 + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t linepos; + 736 .loc 1 533 3 view .LVU284 + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 737 .loc 1 534 3 view .LVU285 + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 738 .loc 1 535 3 view .LVU286 + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t pcrlinepos; + 739 .loc 1 536 3 view .LVU287 + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check null pointer */ + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (hexti == NULL) + 740 .loc 1 539 3 view .LVU288 + 741 .loc 1 539 6 is_stmt 0 view .LVU289 + 742 0000 0028 cmp r0, #0 + 743 0002 65D0 beq .L53 + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 744 .loc 1 530 1 view .LVU290 + 745 0004 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 746 .LCFI4: + 747 .cfi_def_cfa_offset 24 + 748 .cfi_offset 4, -24 + 749 .cfi_offset 5, -20 + 750 .cfi_offset 6, -16 + 751 .cfi_offset 7, -12 + 752 .cfi_offset 8, -8 + 753 .cfi_offset 14, -4 + 754 0008 0146 mov r1, r0 + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_ERROR; + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check the parameter */ + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 755 .loc 1 545 3 is_stmt 1 view .LVU291 + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* compute line register offset and line mask */ + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 756 .loc 1 548 3 view .LVU292 + 757 .loc 1 548 19 is_stmt 0 view .LVU293 + 758 000a 0568 ldr r5, [r0] + ARM GAS /tmp/cckOoBBj.s page 26 + + + 759 .loc 1 548 10 view .LVU294 + 760 000c C5F30140 ubfx r0, r5, #16, #2 + 761 .LVL103: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 762 .loc 1 549 3 is_stmt 1 view .LVU295 + 763 .loc 1 549 11 is_stmt 0 view .LVU296 + 764 0010 05F01F0E and lr, r5, #31 + 765 .LVL104: + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << linepos); + 766 .loc 1 550 3 is_stmt 1 view .LVU297 + 767 .loc 1 550 12 is_stmt 0 view .LVU298 + 768 0014 0123 movs r3, #1 + 769 0016 03FA0EF3 lsl r3, r3, lr + 770 .LVL105: + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 1] Clear interrupt mode */ + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + 771 .loc 1 553 3 is_stmt 1 view .LVU299 + 772 .loc 1 553 13 is_stmt 0 view .LVU300 + 773 001a 0201 lsls r2, r0, #4 + 774 .loc 1 553 11 view .LVU301 + 775 001c 2D4E ldr r6, .L61 + 776 .LVL106: + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 777 .loc 1 554 3 is_stmt 1 view .LVU302 + 778 .loc 1 554 13 is_stmt 0 view .LVU303 + 779 001e 9459 ldr r4, [r2, r6] + 780 .loc 1 554 24 view .LVU304 + 781 0020 6FEA030C mvn ip, r3 + 782 .loc 1 554 10 view .LVU305 + 783 0024 24EA0304 bic r4, r4, r3 + 784 .LVL107: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 785 .loc 1 555 3 is_stmt 1 view .LVU306 + 786 .loc 1 555 12 is_stmt 0 view .LVU307 + 787 0028 9451 str r4, [r2, r6] + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 2] Clear event mode */ + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + 788 .loc 1 558 3 is_stmt 1 view .LVU308 + 789 .loc 1 558 11 is_stmt 0 view .LVU309 + 790 002a 0436 adds r6, r6, #4 + 791 .LVL108: + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 792 .loc 1 559 3 is_stmt 1 view .LVU310 + 793 .loc 1 559 13 is_stmt 0 view .LVU311 + 794 002c 9459 ldr r4, [r2, r6] + 795 .LVL109: + 796 .loc 1 559 10 view .LVU312 + 797 002e 24EA0304 bic r4, r4, r3 + 798 .LVL110: + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 799 .loc 1 560 3 is_stmt 1 view .LVU313 + 800 .loc 1 560 12 is_stmt 0 view .LVU314 + 801 0032 9451 str r4, [r2, r6] + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #if defined (DUAL_CORE) + ARM GAS /tmp/cckOoBBj.s page 27 + + + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 1] Clear CM4 interrupt mode */ + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 2] Clear CM4 event mode */ + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #endif /* DUAL_CORE */ + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 3] Clear triggers in case of configurable lines */ + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((hexti->Line & EXTI_CONFIG) != 0x00U) + 802 .loc 1 575 3 is_stmt 1 view .LVU315 + 803 .loc 1 575 13 is_stmt 0 view .LVU316 + 804 0034 0A68 ldr r2, [r1] + 805 .LVL111: + 806 .loc 1 575 6 view .LVU317 + 807 0036 12F0007F tst r2, #33554432 + 808 003a 11D0 beq .L50 + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 809 .loc 1 577 5 is_stmt 1 view .LVU318 + 810 .loc 1 577 15 is_stmt 0 view .LVU319 + 811 003c 4201 lsls r2, r0, #5 + 812 .loc 1 577 13 view .LVU320 + 813 003e 02F1B046 add r6, r2, #1476395008 + 814 .LVL112: + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 815 .loc 1 578 5 is_stmt 1 view .LVU321 + 816 .loc 1 578 15 is_stmt 0 view .LVU322 + 817 0042 3468 ldr r4, [r6] + 818 .LVL113: + 819 .loc 1 578 12 view .LVU323 + 820 0044 0CEA0404 and r4, ip, r4 + 821 .LVL114: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 822 .loc 1 579 5 is_stmt 1 view .LVU324 + 823 .loc 1 579 14 is_stmt 0 view .LVU325 + 824 0048 3460 str r4, [r6] + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 825 .loc 1 581 5 is_stmt 1 view .LVU326 + 826 .loc 1 581 13 is_stmt 0 view .LVU327 + 827 004a 234E ldr r6, .L61+4 + 828 .LVL115: + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 829 .loc 1 582 5 is_stmt 1 view .LVU328 + 830 .loc 1 582 15 is_stmt 0 view .LVU329 + 831 004c 9459 ldr r4, [r2, r6] + 832 .LVL116: + 833 .loc 1 582 12 view .LVU330 + 834 004e 0CEA0404 and r4, ip, r4 + 835 .LVL117: + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = regval; + 836 .loc 1 583 5 is_stmt 1 view .LVU331 + 837 .loc 1 583 14 is_stmt 0 view .LVU332 + ARM GAS /tmp/cckOoBBj.s page 28 + + + 838 0052 9451 str r4, [r2, r6] + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + 839 .loc 1 586 5 is_stmt 1 view .LVU333 + 840 .loc 1 586 15 is_stmt 0 view .LVU334 + 841 0054 0A68 ldr r2, [r1] + 842 .LVL118: + 843 .loc 1 586 22 view .LVU335 + 844 0056 02F0C062 and r2, r2, #100663296 + 845 .loc 1 586 8 view .LVU336 + 846 005a B2F1C06F cmp r2, #100663296 + 847 005e 08D0 beq .L59 + 848 .LVL119: + 849 .L50: + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* 4] Clear D3 Config lines */ + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + 850 .loc 1 597 3 is_stmt 1 view .LVU337 + 851 .loc 1 597 13 is_stmt 0 view .LVU338 + 852 0060 0A68 ldr r2, [r1] + 853 .loc 1 597 20 view .LVU339 + 854 0062 02F44012 and r2, r2, #3145728 + 855 .loc 1 597 6 view .LVU340 + 856 0066 B2F5401F cmp r2, #3145728 + 857 006a 14D0 beq .L60 + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = (*regaddr & ~maskline); + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if(linepos < 16UL) + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /*Clear D3 PendClear source */ + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL)); + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_OK; + 858 .loc 1 617 10 view .LVU341 + 859 006c 0020 movs r0, #0 + 860 .LVL120: + ARM GAS /tmp/cckOoBBj.s page 29 + + + 861 .L49: + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 862 .loc 1 618 1 view .LVU342 + 863 006e BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 864 .LVL121: + 865 .L59: + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 866 .loc 1 588 7 is_stmt 1 view .LVU343 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + 867 .loc 1 590 7 view .LVU344 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + 868 .loc 1 590 47 is_stmt 0 view .LVU345 + 869 0072 CEF38102 ubfx r2, lr, #2, #2 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + 870 .loc 1 590 14 view .LVU346 + 871 0076 194F ldr r7, .L61+8 + 872 0078 0232 adds r2, r2, #2 + 873 007a 57F82240 ldr r4, [r7, r2, lsl #2] + 874 .LVL122: + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 875 .loc 1 591 7 is_stmt 1 view .LVU347 + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 876 .loc 1 591 80 is_stmt 0 view .LVU348 + 877 007e 05F00306 and r6, r5, #3 + 878 .LVL123: + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 879 .loc 1 591 69 view .LVU349 + 880 0082 4FEA8608 lsl r8, r6, #2 + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 881 .loc 1 591 40 view .LVU350 + 882 0086 0F26 movs r6, #15 + 883 0088 06FA08F6 lsl r6, r6, r8 + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + 884 .loc 1 591 14 view .LVU351 + 885 008c 24EA0604 bic r4, r4, r6 + 886 .LVL124: + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 887 .loc 1 592 7 is_stmt 1 view .LVU352 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 888 .loc 1 592 48 is_stmt 0 view .LVU353 + 889 0090 47F82240 str r4, [r7, r2, lsl #2] + 890 0094 E4E7 b .L50 + 891 .LVL125: + 892 .L60: + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = (*regaddr & ~maskline); + 893 .loc 1 599 5 is_stmt 1 view .LVU354 + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = (*regaddr & ~maskline); + 894 .loc 1 599 15 is_stmt 0 view .LVU355 + 895 0096 4001 lsls r0, r0, #5 + 896 .LVL126: + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = (*regaddr & ~maskline); + 897 .loc 1 599 13 view .LVU356 + 898 0098 1149 ldr r1, .L61+12 + 899 .LVL127: + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 900 .loc 1 600 5 is_stmt 1 view .LVU357 + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + ARM GAS /tmp/cckOoBBj.s page 30 + + + 901 .loc 1 600 17 is_stmt 0 view .LVU358 + 902 009a 4258 ldr r2, [r0, r1] + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 903 .loc 1 600 26 view .LVU359 + 904 009c 0CEA0202 and r2, ip, r2 + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 905 .loc 1 600 14 view .LVU360 + 906 00a0 4250 str r2, [r0, r1] + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 907 .loc 1 602 5 is_stmt 1 view .LVU361 + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 908 .loc 1 602 7 is_stmt 0 view .LVU362 + 909 00a2 15F0100F tst r5, #16 + 910 00a6 0BD1 bne .L51 + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 911 .loc 1 604 7 is_stmt 1 view .LVU363 + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << linepos; + 912 .loc 1 604 15 is_stmt 0 view .LVU364 + 913 00a8 0E4A ldr r2, .L61+16 + 914 00aa 0244 add r2, r2, r0 + 915 .LVL128: + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 916 .loc 1 605 7 is_stmt 1 view .LVU365 + 917 .L52: + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 918 .loc 1 614 5 view .LVU366 + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 919 .loc 1 614 14 is_stmt 0 view .LVU367 + 920 00ac 1168 ldr r1, [r2] + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 921 .loc 1 614 31 view .LVU368 + 922 00ae 03FB03F3 mul r3, r3, r3 + 923 .LVL129: + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 924 .loc 1 614 44 view .LVU369 + 925 00b2 03EB4303 add r3, r3, r3, lsl #1 + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 926 .loc 1 614 14 view .LVU370 + 927 00b6 21EA0303 bic r3, r1, r3 + 928 00ba 1360 str r3, [r2] + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 929 .loc 1 617 10 view .LVU371 + 930 00bc 0020 movs r0, #0 + 931 00be D6E7 b .L49 + 932 .LVL130: + 933 .L51: + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 934 .loc 1 609 7 is_stmt 1 view .LVU372 + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** pcrlinepos = 1UL << (linepos - 16UL); + 935 .loc 1 609 15 is_stmt 0 view .LVU373 + 936 00c0 094A ldr r2, .L61+20 + 937 00c2 0244 add r2, r2, r0 + 938 .LVL131: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 939 .loc 1 610 7 is_stmt 1 view .LVU374 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 940 .loc 1 610 36 is_stmt 0 view .LVU375 + ARM GAS /tmp/cckOoBBj.s page 31 + + + 941 00c4 AEF1100E sub lr, lr, #16 + 942 .LVL132: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 943 .loc 1 610 18 view .LVU376 + 944 00c8 0123 movs r3, #1 + 945 .LVL133: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 946 .loc 1 610 18 view .LVU377 + 947 00ca 03FA0EF3 lsl r3, r3, lr + 948 .LVL134: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 949 .loc 1 610 18 view .LVU378 + 950 00ce EDE7 b .L52 + 951 .LVL135: + 952 .L53: + 953 .LCFI5: + 954 .cfi_def_cfa_offset 0 + 955 .cfi_restore 4 + 956 .cfi_restore 5 + 957 .cfi_restore 6 + 958 .cfi_restore 7 + 959 .cfi_restore 8 + 960 .cfi_restore 14 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 961 .loc 1 541 12 view .LVU379 + 962 00d0 0120 movs r0, #1 + 963 .LVL136: + 964 .loc 1 618 1 view .LVU380 + 965 00d2 7047 bx lr + 966 .L62: + 967 .align 2 + 968 .L61: + 969 00d4 80000058 .word 1476395136 + 970 00d8 04000058 .word 1476395012 + 971 00dc 00040058 .word 1476396032 + 972 00e0 0C000058 .word 1476395020 + 973 00e4 10000058 .word 1476395024 + 974 00e8 14000058 .word 1476395028 + 975 .cfi_endproc + 976 .LFE143: + 978 .section .text.HAL_EXTI_RegisterCallback,"ax",%progbits + 979 .align 1 + 980 .global HAL_EXTI_RegisterCallback + 981 .syntax unified + 982 .thumb + 983 .thumb_func + 984 .fpu fpv5-d16 + 986 HAL_EXTI_RegisterCallback: + 987 .LVL137: + 988 .LFB144: + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Register callback for a dedicated Exti line. + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param CallbackID User callback identifier. + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + ARM GAS /tmp/cckOoBBj.s page 32 + + + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param pPendingCbfn function pointer to be stored as callback. + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval HAL Status. + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 989 .loc 1 630 1 is_stmt 1 view -0 + 990 .cfi_startproc + 991 @ args = 0, pretend = 0, frame = 0 + 992 @ frame_needed = 0, uses_anonymous_args = 0 + 993 @ link register save eliminated. + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_StatusTypeDef status = HAL_OK; + 994 .loc 1 631 3 view .LVU382 + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check null pointer */ + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (hexti == NULL) + 995 .loc 1 634 3 view .LVU383 + 996 .loc 1 634 6 is_stmt 0 view .LVU384 + 997 0000 18B1 cbz r0, .L65 + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_ERROR; + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** switch (CallbackID) + 998 .loc 1 639 3 is_stmt 1 view .LVU385 + 999 0002 21B9 cbnz r1, .L66 + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** case HAL_EXTI_COMMON_CB_ID: + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** hexti->PendingCallback = pPendingCbfn; + 1000 .loc 1 642 7 view .LVU386 + 1001 .loc 1 642 30 is_stmt 0 view .LVU387 + 1002 0004 4260 str r2, [r0, #4] + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** break; + 1003 .loc 1 643 7 is_stmt 1 view .LVU388 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 1004 .loc 1 631 21 is_stmt 0 view .LVU389 + 1005 0006 0846 mov r0, r1 + 1006 .LVL138: + 1007 .loc 1 643 7 view .LVU390 + 1008 0008 7047 bx lr + 1009 .LVL139: + 1010 .L65: + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1011 .loc 1 636 12 view .LVU391 + 1012 000a 0120 movs r0, #1 + 1013 .LVL140: + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1014 .loc 1 636 12 view .LVU392 + 1015 000c 7047 bx lr + 1016 .LVL141: + 1017 .L66: + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** default: + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** status = HAL_ERROR; + 1018 .loc 1 646 14 view .LVU393 + 1019 000e 0120 movs r0, #1 + 1020 .LVL142: + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** break; + ARM GAS /tmp/cckOoBBj.s page 33 + + + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return status; + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1021 .loc 1 651 1 view .LVU394 + 1022 0010 7047 bx lr + 1023 .cfi_endproc + 1024 .LFE144: + 1026 .section .text.HAL_EXTI_GetHandle,"ax",%progbits + 1027 .align 1 + 1028 .global HAL_EXTI_GetHandle + 1029 .syntax unified + 1030 .thumb + 1031 .thumb_func + 1032 .fpu fpv5-d16 + 1034 HAL_EXTI_GetHandle: + 1035 .LVL143: + 1036 .LFB145: + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Store line number as handle private field. + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param ExtiLine Exti line number. + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This parameter can be from 0 to @ref EXTI_LINE_NB. + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval HAL Status. + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 1037 .loc 1 662 1 is_stmt 1 view -0 + 1038 .cfi_startproc + 1039 @ args = 0, pretend = 0, frame = 0 + 1040 @ frame_needed = 0, uses_anonymous_args = 0 + 1041 @ link register save eliminated. + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check the parameters */ + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(ExtiLine)); + 1042 .loc 1 664 3 view .LVU396 + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check null pointer */ + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (hexti == NULL) + 1043 .loc 1 667 3 view .LVU397 + 1044 .loc 1 667 6 is_stmt 0 view .LVU398 + 1045 0000 10B1 cbz r0, .L69 + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_ERROR; + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Store line number as handle private field */ + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** hexti->Line = ExtiLine; + 1046 .loc 1 674 5 is_stmt 1 view .LVU399 + 1047 .loc 1 674 17 is_stmt 0 view .LVU400 + 1048 0002 0160 str r1, [r0] + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return HAL_OK; + 1049 .loc 1 676 5 is_stmt 1 view .LVU401 + 1050 .loc 1 676 12 is_stmt 0 view .LVU402 + ARM GAS /tmp/cckOoBBj.s page 34 + + + 1051 0004 0020 movs r0, #0 + 1052 .LVL144: + 1053 .loc 1 676 12 view .LVU403 + 1054 0006 7047 bx lr + 1055 .LVL145: + 1056 .L69: + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1057 .loc 1 669 12 view .LVU404 + 1058 0008 0120 movs r0, #1 + 1059 .LVL146: + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1060 .loc 1 678 1 view .LVU405 + 1061 000a 7047 bx lr + 1062 .cfi_endproc + 1063 .LFE145: + 1065 .section .text.HAL_EXTI_IRQHandler,"ax",%progbits + 1066 .align 1 + 1067 .global HAL_EXTI_IRQHandler + 1068 .syntax unified + 1069 .thumb + 1070 .thumb_func + 1071 .fpu fpv5-d16 + 1073 HAL_EXTI_IRQHandler: + 1074 .LVL147: + 1075 .LFB146: + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @} + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2 + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief EXTI IO functions. + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** @verbatim + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** =============================================================================== + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** ##### IO operation functions ##### + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** =============================================================================== + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** @endverbatim + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @{ + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Handle EXTI interrupt request. + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval none. + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 1076 .loc 1 703 1 is_stmt 1 view -0 + 1077 .cfi_startproc + 1078 @ args = 0, pretend = 0, frame = 0 + 1079 @ frame_needed = 0, uses_anonymous_args = 0 + 1080 .loc 1 703 1 is_stmt 0 view .LVU407 + 1081 0000 10B5 push {r4, lr} + ARM GAS /tmp/cckOoBBj.s page 35 + + + 1082 .LCFI6: + 1083 .cfi_def_cfa_offset 8 + 1084 .cfi_offset 4, -8 + 1085 .cfi_offset 14, -4 + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 1086 .loc 1 704 3 is_stmt 1 view .LVU408 + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t regval; + 1087 .loc 1 705 3 view .LVU409 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 1088 .loc 1 706 3 view .LVU410 + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 1089 .loc 1 707 3 view .LVU411 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Compute line register offset and line mask */ + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1090 .loc 1 710 3 view .LVU412 + 1091 .loc 1 710 19 is_stmt 0 view .LVU413 + 1092 0002 0368 ldr r3, [r0] + 1093 .loc 1 710 10 view .LVU414 + 1094 0004 C3F30142 ubfx r2, r3, #16, #2 + 1095 .LVL148: + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + 1096 .loc 1 711 3 is_stmt 1 view .LVU415 + 1097 .loc 1 711 35 is_stmt 0 view .LVU416 + 1098 0008 03F01F03 and r3, r3, #31 + 1099 .loc 1 711 12 view .LVU417 + 1100 000c 0121 movs r1, #1 + 1101 000e 01FA03F3 lsl r3, r1, r3 + 1102 .LVL149: + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #if defined(DUAL_CORE) + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (HAL_GetCurrentCPUID() == CM7_CPUID) + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending register address */ + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else /* Cortex-M4*/ + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending register address */ + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #else + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + 1103 .loc 1 725 3 is_stmt 1 view .LVU418 + 1104 .loc 1 725 13 is_stmt 0 view .LVU419 + 1105 0012 1201 lsls r2, r2, #4 + 1106 .LVL150: + 1107 .loc 1 725 11 view .LVU420 + 1108 0014 0449 ldr r1, .L73 + 1109 .LVL151: + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #endif /* DUAL_CORE */ + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending bit */ + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = (*regaddr & maskline); + 1110 .loc 1 729 3 is_stmt 1 view .LVU421 + 1111 .loc 1 729 13 is_stmt 0 view .LVU422 + 1112 0016 5458 ldr r4, [r2, r1] + ARM GAS /tmp/cckOoBBj.s page 36 + + + 1113 .LVL152: + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (regval != 0x00U) + 1114 .loc 1 731 3 is_stmt 1 view .LVU423 + 1115 .loc 1 731 6 is_stmt 0 view .LVU424 + 1116 0018 1C42 tst r4, r3 + 1117 001a 03D0 beq .L70 + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Clear pending bit */ + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = maskline; + 1118 .loc 1 734 5 is_stmt 1 view .LVU425 + 1119 .loc 1 734 14 is_stmt 0 view .LVU426 + 1120 001c 5350 str r3, [r2, r1] + 1121 .LVL153: + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Call callback */ + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (hexti->PendingCallback != NULL) + 1122 .loc 1 737 5 is_stmt 1 view .LVU427 + 1123 .loc 1 737 14 is_stmt 0 view .LVU428 + 1124 001e 4368 ldr r3, [r0, #4] + 1125 .LVL154: + 1126 .loc 1 737 8 view .LVU429 + 1127 0020 03B1 cbz r3, .L70 + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** hexti->PendingCallback(); + 1128 .loc 1 739 7 is_stmt 1 view .LVU430 + 1129 0022 9847 blx r3 + 1130 .LVL155: + 1131 .L70: + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1132 .loc 1 742 1 is_stmt 0 view .LVU431 + 1133 0024 10BD pop {r4, pc} + 1134 .L74: + 1135 .loc 1 742 1 view .LVU432 + 1136 0026 00BF .align 2 + 1137 .L73: + 1138 0028 88000058 .word 1476395144 + 1139 .cfi_endproc + 1140 .LFE146: + 1142 .section .text.HAL_EXTI_GetPending,"ax",%progbits + 1143 .align 1 + 1144 .global HAL_EXTI_GetPending + 1145 .syntax unified + 1146 .thumb + 1147 .thumb_func + 1148 .fpu fpv5-d16 + 1150 HAL_EXTI_GetPending: + 1151 .LVL156: + 1152 .LFB147: + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Get interrupt pending bit of a dedicated line. + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param Edge Specify which pending edge as to be checked. + ARM GAS /tmp/cckOoBBj.s page 37 + + + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This parameter can be one of the following values: + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval 1 if interrupt is pending else 0. + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 1153 .loc 1 755 1 is_stmt 1 view -0 + 1154 .cfi_startproc + 1155 @ args = 0, pretend = 0, frame = 0 + 1156 @ frame_needed = 0, uses_anonymous_args = 0 + 1157 @ link register save eliminated. + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 1158 .loc 1 756 3 view .LVU434 + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t regval; + 1159 .loc 1 757 3 view .LVU435 + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t linepos; + 1160 .loc 1 758 3 view .LVU436 + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 1161 .loc 1 759 3 view .LVU437 + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 1162 .loc 1 760 3 view .LVU438 + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check parameters */ + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1163 .loc 1 763 3 view .LVU439 + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1164 .loc 1 764 3 view .LVU440 + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 1165 .loc 1 765 3 view .LVU441 + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* compute line register offset and line mask */ + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1166 .loc 1 768 3 view .LVU442 + 1167 .loc 1 768 19 is_stmt 0 view .LVU443 + 1168 0000 0368 ldr r3, [r0] + 1169 .loc 1 768 10 view .LVU444 + 1170 0002 C3F30141 ubfx r1, r3, #16, #2 + 1171 .LVL157: + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 1172 .loc 1 769 3 is_stmt 1 view .LVU445 + 1173 .loc 1 769 11 is_stmt 0 view .LVU446 + 1174 0006 03F01F03 and r3, r3, #31 + 1175 .LVL158: + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << linepos); + 1176 .loc 1 770 3 is_stmt 1 view .LVU447 + 1177 .loc 1 770 12 is_stmt 0 view .LVU448 + 1178 000a 0120 movs r0, #1 + 1179 .LVL159: + 1180 .loc 1 770 12 view .LVU449 + 1181 000c 00FA03F2 lsl r2, r0, r3 + 1182 .LVL160: + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #if defined(DUAL_CORE) + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (HAL_GetCurrentCPUID() == CM7_CPUID) + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending register address */ + ARM GAS /tmp/cckOoBBj.s page 38 + + + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else /* Cortex-M4 */ + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending register address */ + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #else + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + 1183 .loc 1 784 3 is_stmt 1 view .LVU450 + 1184 .loc 1 784 13 is_stmt 0 view .LVU451 + 1185 0010 0901 lsls r1, r1, #4 + 1186 .LVL161: + 1187 .loc 1 784 11 view .LVU452 + 1188 0012 0248 ldr r0, .L76 + 1189 .LVL162: + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #endif /* DUAL_CORE */ + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* return 1 if bit is set else 0 */ + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regval = ((*regaddr & maskline) >> linepos); + 1190 .loc 1 788 3 is_stmt 1 view .LVU453 + 1191 .loc 1 788 14 is_stmt 0 view .LVU454 + 1192 0014 0858 ldr r0, [r1, r0] + 1193 .LVL163: + 1194 .loc 1 788 23 view .LVU455 + 1195 0016 1040 ands r0, r0, r2 + 1196 .LVL164: + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** return regval; + 1197 .loc 1 789 3 is_stmt 1 view .LVU456 + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1198 .loc 1 790 1 is_stmt 0 view .LVU457 + 1199 0018 D840 lsrs r0, r0, r3 + 1200 .LVL165: + 1201 .loc 1 790 1 view .LVU458 + 1202 001a 7047 bx lr + 1203 .L77: + 1204 .align 2 + 1205 .L76: + 1206 001c 88000058 .word 1476395144 + 1207 .cfi_endproc + 1208 .LFE147: + 1210 .section .text.HAL_EXTI_ClearPending,"ax",%progbits + 1211 .align 1 + 1212 .global HAL_EXTI_ClearPending + 1213 .syntax unified + 1214 .thumb + 1215 .thumb_func + 1216 .fpu fpv5-d16 + 1218 HAL_EXTI_ClearPending: + 1219 .LVL166: + 1220 .LFB148: + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Clear interrupt pending bit of a dedicated line. + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param Edge Specify which pending edge as to be clear. + ARM GAS /tmp/cckOoBBj.s page 39 + + + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This parameter can be one of the following values: + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval None. + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 1221 .loc 1 803 1 is_stmt 1 view -0 + 1222 .cfi_startproc + 1223 @ args = 0, pretend = 0, frame = 0 + 1224 @ frame_needed = 0, uses_anonymous_args = 0 + 1225 @ link register save eliminated. + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 1226 .loc 1 804 3 view .LVU460 + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 1227 .loc 1 805 3 view .LVU461 + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 1228 .loc 1 806 3 view .LVU462 + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check parameters */ + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1229 .loc 1 809 3 view .LVU463 + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1230 .loc 1 810 3 view .LVU464 + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 1231 .loc 1 811 3 view .LVU465 + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* compute line register offset and line mask */ + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1232 .loc 1 814 3 view .LVU466 + 1233 .loc 1 814 19 is_stmt 0 view .LVU467 + 1234 0000 0368 ldr r3, [r0] + 1235 .loc 1 814 10 view .LVU468 + 1236 0002 C3F30142 ubfx r2, r3, #16, #2 + 1237 .LVL167: + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + 1238 .loc 1 815 3 is_stmt 1 view .LVU469 + 1239 .loc 1 815 35 is_stmt 0 view .LVU470 + 1240 0006 03F01F03 and r3, r3, #31 + 1241 .loc 1 815 12 view .LVU471 + 1242 000a 0121 movs r1, #1 + 1243 .LVL168: + 1244 .loc 1 815 12 view .LVU472 + 1245 000c 01FA03F3 lsl r3, r1, r3 + 1246 .LVL169: + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #if defined(DUAL_CORE) + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** if (HAL_GetCurrentCPUID() == CM7_CPUID) + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending register address */ + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** else /* Cortex-M4 */ + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Get pending register address */ + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + ARM GAS /tmp/cckOoBBj.s page 40 + + + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #else + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + 1247 .loc 1 829 3 is_stmt 1 view .LVU473 + 1248 .loc 1 829 13 is_stmt 0 view .LVU474 + 1249 0010 1201 lsls r2, r2, #4 + 1250 .LVL170: + 1251 .loc 1 829 11 view .LVU475 + 1252 0012 0149 ldr r1, .L79 + 1253 .LVL171: + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** #endif /* DUAL_CORE */ + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Clear Pending bit */ + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = maskline; + 1254 .loc 1 833 3 is_stmt 1 view .LVU476 + 1255 .loc 1 833 12 is_stmt 0 view .LVU477 + 1256 0014 5350 str r3, [r2, r1] + 1257 .LVL172: + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1258 .loc 1 834 1 view .LVU478 + 1259 0016 7047 bx lr + 1260 .L80: + 1261 .align 2 + 1262 .L79: + 1263 0018 88000058 .word 1476395144 + 1264 .cfi_endproc + 1265 .LFE148: + 1267 .section .text.HAL_EXTI_GenerateSWI,"ax",%progbits + 1268 .align 1 + 1269 .global HAL_EXTI_GenerateSWI + 1270 .syntax unified + 1271 .thumb + 1272 .thumb_func + 1273 .fpu fpv5-d16 + 1275 HAL_EXTI_GenerateSWI: + 1276 .LVL173: + 1277 .LFB149: + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /** + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @brief Generate a software interrupt for a dedicated line. + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @param hexti Exti handle. + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** * @retval None. + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** */ + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** { + 1278 .loc 1 842 1 is_stmt 1 view -0 + 1279 .cfi_startproc + 1280 @ args = 0, pretend = 0, frame = 0 + 1281 @ frame_needed = 0, uses_anonymous_args = 0 + 1282 @ link register save eliminated. + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** __IO uint32_t *regaddr; + 1283 .loc 1 843 3 view .LVU480 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t maskline; + 1284 .loc 1 844 3 view .LVU481 + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** uint32_t offset; + 1285 .loc 1 845 3 view .LVU482 + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* Check parameters */ + ARM GAS /tmp/cckOoBBj.s page 41 + + + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1286 .loc 1 848 3 view .LVU483 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1287 .loc 1 849 3 view .LVU484 + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** /* compute line register offset and line mask */ + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1288 .loc 1 852 3 view .LVU485 + 1289 .loc 1 852 19 is_stmt 0 view .LVU486 + 1290 0000 0368 ldr r3, [r0] + 1291 .loc 1 852 10 view .LVU487 + 1292 0002 C3F30142 ubfx r2, r3, #16, #2 + 1293 .LVL174: + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + 1294 .loc 1 853 3 is_stmt 1 view .LVU488 + 1295 .loc 1 853 35 is_stmt 0 view .LVU489 + 1296 0006 03F01F03 and r3, r3, #31 + 1297 .loc 1 853 12 view .LVU490 + 1298 000a 0121 movs r1, #1 + 1299 000c 01FA03F3 lsl r3, r1, r3 + 1300 .LVL175: + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + 1301 .loc 1 855 3 is_stmt 1 view .LVU491 + 1302 .loc 1 855 13 is_stmt 0 view .LVU492 + 1303 0010 5201 lsls r2, r2, #5 + 1304 .LVL176: + 1305 .loc 1 855 11 view .LVU493 + 1306 0012 0149 ldr r1, .L82 + 1307 .LVL177: + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** *regaddr = maskline; + 1308 .loc 1 856 3 is_stmt 1 view .LVU494 + 1309 .loc 1 856 12 is_stmt 0 view .LVU495 + 1310 0014 5350 str r3, [r2, r1] + 1311 .LVL178: + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c **** } + 1312 .loc 1 857 1 view .LVU496 + 1313 0016 7047 bx lr + 1314 .L83: + 1315 .align 2 + 1316 .L82: + 1317 0018 08000058 .word 1476395016 + 1318 .cfi_endproc + 1319 .LFE149: + 1321 .text + 1322 .Letext0: + 1323 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1324 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1325 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1326 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1327 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h" + ARM GAS /tmp/cckOoBBj.s page 42 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_exti.c + /tmp/cckOoBBj.s:17 .text.HAL_EXTI_SetConfigLine:0000000000000000 $t + /tmp/cckOoBBj.s:25 .text.HAL_EXTI_SetConfigLine:0000000000000000 HAL_EXTI_SetConfigLine + /tmp/cckOoBBj.s:386 .text.HAL_EXTI_SetConfigLine:0000000000000128 $d + /tmp/cckOoBBj.s:397 .text.HAL_EXTI_GetConfigLine:0000000000000000 $t + /tmp/cckOoBBj.s:404 .text.HAL_EXTI_GetConfigLine:0000000000000000 HAL_EXTI_GetConfigLine + /tmp/cckOoBBj.s:709 .text.HAL_EXTI_GetConfigLine:0000000000000100 $d + /tmp/cckOoBBj.s:720 .text.HAL_EXTI_ClearConfigLine:0000000000000000 $t + /tmp/cckOoBBj.s:727 .text.HAL_EXTI_ClearConfigLine:0000000000000000 HAL_EXTI_ClearConfigLine + /tmp/cckOoBBj.s:969 .text.HAL_EXTI_ClearConfigLine:00000000000000d4 $d + /tmp/cckOoBBj.s:979 .text.HAL_EXTI_RegisterCallback:0000000000000000 $t + /tmp/cckOoBBj.s:986 .text.HAL_EXTI_RegisterCallback:0000000000000000 HAL_EXTI_RegisterCallback + /tmp/cckOoBBj.s:1027 .text.HAL_EXTI_GetHandle:0000000000000000 $t + /tmp/cckOoBBj.s:1034 .text.HAL_EXTI_GetHandle:0000000000000000 HAL_EXTI_GetHandle + /tmp/cckOoBBj.s:1066 .text.HAL_EXTI_IRQHandler:0000000000000000 $t + /tmp/cckOoBBj.s:1073 .text.HAL_EXTI_IRQHandler:0000000000000000 HAL_EXTI_IRQHandler + /tmp/cckOoBBj.s:1138 .text.HAL_EXTI_IRQHandler:0000000000000028 $d + /tmp/cckOoBBj.s:1143 .text.HAL_EXTI_GetPending:0000000000000000 $t + /tmp/cckOoBBj.s:1150 .text.HAL_EXTI_GetPending:0000000000000000 HAL_EXTI_GetPending + /tmp/cckOoBBj.s:1206 .text.HAL_EXTI_GetPending:000000000000001c $d + /tmp/cckOoBBj.s:1211 .text.HAL_EXTI_ClearPending:0000000000000000 $t + /tmp/cckOoBBj.s:1218 .text.HAL_EXTI_ClearPending:0000000000000000 HAL_EXTI_ClearPending + /tmp/cckOoBBj.s:1263 .text.HAL_EXTI_ClearPending:0000000000000018 $d + /tmp/cckOoBBj.s:1268 .text.HAL_EXTI_GenerateSWI:0000000000000000 $t + /tmp/cckOoBBj.s:1275 .text.HAL_EXTI_GenerateSWI:0000000000000000 HAL_EXTI_GenerateSWI + /tmp/cckOoBBj.s:1317 .text.HAL_EXTI_GenerateSWI:0000000000000018 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_exti.o b/build/stm32h7xx_hal_exti.o new file mode 100644 index 0000000..dc2587c Binary files /dev/null and b/build/stm32h7xx_hal_exti.o differ diff --git a/build/stm32h7xx_hal_flash.d b/build/stm32h7xx_hal_flash.d new file mode 100644 index 0000000..1f06d0e --- /dev/null +++ b/build/stm32h7xx_hal_flash.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_flash.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_flash.lst b/build/stm32h7xx_hal_flash.lst new file mode 100644 index 0000000..87dda27 --- /dev/null +++ b/build/stm32h7xx_hal_flash.lst @@ -0,0 +1,3886 @@ +ARM GAS /tmp/ccCw6Rev.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_flash.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits + 17 .align 1 + 18 .weak HAL_FLASH_EndOfOperationCallback + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_FLASH_EndOfOperationCallback: + 26 .LVL0: + 27 .LFB144: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @file stm32h7xx_hal_flash.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief FLASH HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * functionalities of the internal FLASH memory: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + Program operations functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + Memory Control functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + Peripheral Errors functions + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @verbatim + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ##### FLASH peripheral features ##### + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ============================================================================== + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** to the Flash memory. It implements the erase and program Flash memory operations + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** and the read and write protection mechanisms. + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] The FLASH main features are: + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Flash memory read operations + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Flash memory program/erase operations + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Read / write protections + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Option bytes programming + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Error code correction (ECC) : Data in flash are 266-bits word + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (10 bits added per flash word) + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ##### How to use this driver ##### + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ============================================================================== + ARM GAS /tmp/ccCw6Rev.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** This driver provides functions and macros to configure and program the FLASH + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** memory of all STM32H7xx devices. + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (#) FLASH Memory IO Programming functions: + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_Lock() functions + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Program functions: 256-bit word only + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) There Two modes of programming : + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+++) Polling mode using HAL_FLASH_Program() function + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+++) Interrupt mode using HAL_FLASH_Program_IT() function + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (#) Interrupts and flags management functions : + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Callback functions are called when the flash operations are finished : + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback() + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Get error flag status by calling HAL_FLASH_GetError() + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (#) Option bytes management functions : + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_OB_Lock() functions + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** In this case, a reset is generated + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** In addition to these functions, this driver includes a set of macros allowing + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** to handle the following operations: + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Set the latency + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Enable/Disable the FLASH interrupts + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (+) Monitor the FLASH flags status + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (@) For any Flash memory program operation (erase or program), the CPU clock frequency + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (HCLK) must be at least 1MHz. + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** a Flash memory operation. + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (@) The application can simultaneously request a read and a write operation through each AXI + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** interface. + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** As the Flash memory is divided into two independent banks, the embedded Flash + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** memory interface can drive different operations at the same time on each bank. For + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** example a read, write or erase operation can be executed on bank 1 while another read, + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** write or erase operation is executed on bank 2. + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @endverbatim + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ****************************************************************************** + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @attention + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * All rights reserved.

+ 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * This software component is licensed by ST under BSD 3-Clause license, + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * the "License"; You may not use this file except in compliance with the + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * License. You may obtain a copy of the License at: + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * opensource.org/licenses/BSD-3-Clause + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ****************************************************************************** + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + ARM GAS /tmp/ccCw6Rev.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/ + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #include "stm32h7xx_hal.h" + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @addtogroup STM32H7xx_HAL_Driver + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @defgroup FLASH FLASH + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief FLASH HAL module driver + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Private define ------------------------------------------------------------*/ + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Constants + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @} + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Private macro -------------------------------------------------------------*/ + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/ + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash; + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/ + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Exported functions ---------------------------------------------------------*/ + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported functions + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Programming operation functions + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @verbatim + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** =============================================================================== + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ##### Programming operation functions ##### + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** =============================================================================== + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** This subsection provides a set of functions allowing to manage the FLASH + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** program operations. + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @endverbatim + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Program flash word at a specified address + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param FlashAddress specifies the address to be programmed. + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param DataAddress specifies the address of data to be programmed + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + ARM GAS /tmp/ccCw6Rev.s page 4 + + + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddre + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress; + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t bank; + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check the parameters */ + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Process Locked */ + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)) + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bank = FLASH_BANK_1; + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bank = FLASH_BANK_2; + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Reset error code */ + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for last operation to be completed */ + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(status == HAL_OK) + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(bank == FLASH_BANK_1) + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set OTP_PG bit */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set PG bit */ + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR1, FLASH_CR_PG); + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + ARM GAS /tmp/ccCw6Rev.s page 5 + + + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set PG bit */ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR2, FLASH_CR_PG); + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else /* Single Bank */ + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set OTP_PG bit */ + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set PG bit */ + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR1, FLASH_CR_PG); + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __ISB(); + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Program an OTP word (16 bits) */ + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Program the flash word */ + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** do + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** *dest_addr = *src_addr; + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** src_addr++; + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** row_index--; + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } while (row_index != 0U); + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __ISB(); + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for last operation to be completed */ + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If the program operation is completed, disable the OTP_PG */ + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + ARM GAS /tmp/ccCw6Rev.s page 6 + + + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(bank == FLASH_BANK_1) + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If the program operation is completed, disable the PG */ + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If the program operation is completed, disable the PG */ + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else /* Single Bank */ + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If the program operation is completed, disable the OTP_PG */ + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If the program operation is completed, disable the PG */ + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Process Unlocked */ + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return status; + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Program flash words of 256 bits at a specified address with interrupt enabled. + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param FlashAddress specifies the address to be programmed. + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param DataAddress specifies the address of data (256 bits) to be programmed + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL Status + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAd + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress; + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t bank; + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check the parameters */ + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Process Locked */ + ARM GAS /tmp/ccCw6Rev.s page 7 + + + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Reset error code */ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)) + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bank = FLASH_BANK_1; + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bank = FLASH_BANK_2; + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for last operation to be completed */ + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (status != HAL_OK) + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Process Unlocked */ + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Address = FlashAddress; + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(bank == FLASH_BANK_1) + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set internal variables used by the IRQ handler */ + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set OTP_PG bit */ + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set PG bit */ + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR1, FLASH_CR_PG); + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Enable End of Operation and Error interrupts for Bank 1 */ + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_CR_OPERRIE) + ARM GAS /tmp/ccCw6Rev.s page 8 + + + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_ + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_B + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_ + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_CR_OPERRIE */ + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set internal variables used by the IRQ handler */ + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2; + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set PG bit */ + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR2, FLASH_CR_PG); + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Enable End of Operation and Error interrupts for Bank2 */ + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_CR_OPERRIE) + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_ + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_B + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_ + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_CR_OPERRIE */ + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else /* Single Bank */ + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set internal variables used by the IRQ handler */ + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set OTP_PG bit */ + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set PG bit */ + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR1, FLASH_CR_PG); + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Enable End of Operation and Error interrupts for Bank 1 */ + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_CR_OPERRIE) + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_ + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_B + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_ + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_CR_OPERRIE */ + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __ISB(); + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_OPTCR_PG_OTP) + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + ARM GAS /tmp/ccCw6Rev.s page 9 + + + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Program an OTP word (16 bits) */ + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Program the flash word */ + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** do + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** *dest_addr = *src_addr; + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** src_addr++; + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** row_index--; + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } while (row_index != 0U); + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __ISB(); + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return status; + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief This function handles FLASH interrupt request. + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval None + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void) + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t temp; + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t errorflag; + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_ProcedureTypeDef procedure; + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check FLASH Bank1 End of Operation flag */ + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET) + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1) + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Nb of sector to erased can be decreased */ + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.NbSectorsToErase--; + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check if there are still sectors to erase */ + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(pFlash.NbSectorsToErase != 0U) + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Indicate user which sector has been erased */ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear bank 1 End of Operation pending bit */ + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Increment sector number */ + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector++; + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + ARM GAS /tmp/ccCw6Rev.s page 10 + + + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* No more sectors to Erase, user callback can be called */ + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Reset Sector and stop Erase sectors procedure */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** procedure = pFlash.ProcedureOnGoing; + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* MassErase ended. Return the selected bank */ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1); + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if(procedure == FLASH_PROC_PROGRAM_BANK1) + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Program ended. Return the selected address */ + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address); + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Nothing to do */ + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((procedure != FLASH_PROC_SECTERASE_BANK2) && \ + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_MASSERASE_BANK2) && \ + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_PROGRAM_BANK2)) + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check FLASH Bank2 End of Operation flag */ + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET) + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2) + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*Nb of sector to erased can be decreased*/ + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.NbSectorsToErase--; + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check if there are still sectors to erase*/ + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(pFlash.NbSectorsToErase != 0U) + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*Indicate user which sector has been erased*/ + ARM GAS /tmp/ccCw6Rev.s page 11 + + + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear bank 2 End of Operation pending bit */ + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*Increment sector number*/ + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector++; + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase); + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* No more sectors to Erase, user callback can be called */ + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Reset Sector and stop Erase sectors procedure */ + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** procedure = pFlash.ProcedureOnGoing; + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*MassErase ended. Return the selected bank*/ + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2); + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if(procedure == FLASH_PROC_PROGRAM_BANK2) + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Program ended. Return the selected address */ + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address); + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Nothing to do */ + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((procedure != FLASH_PROC_SECTERASE_BANK1) && \ + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_MASSERASE_BANK1) && \ + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_PROGRAM_BANK1)) + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + ARM GAS /tmp/ccCw6Rev.s page 12 + + + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check FLASH Bank1 operation error flags */ + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_SR_OPERR) + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_ + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_FLAG_INCERR_BANK1); + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_SR_OPERR */ + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(errorflag != 0U) + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Save the error code */ + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode |= errorflag; + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear error programming flags */ + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag); + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** procedure = pFlash.ProcedureOnGoing; + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(procedure == FLASH_PROC_SECTERASE_BANK1) + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Return the faulty sector */ + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Return the faulty bank */ + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = FLASH_BANK_1; + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Return the faulty address */ + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Address; + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Stop the procedure ongoing*/ + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH error interrupt user callback */ + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(temp); + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check FLASH Bank2 operation error flags */ + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_SR_OPERR) + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU); + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU); + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_SR_OPERR */ + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(errorflag != 0U) + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Save the error code */ + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode |= (errorflag | 0x80000000U); + ARM GAS /tmp/ccCw6Rev.s page 13 + + + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear error programming flags */ + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag); + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** procedure = pFlash.ProcedureOnGoing; + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(procedure== FLASH_PROC_SECTERASE_BANK2) + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*return the faulty sector*/ + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*return the faulty bank*/ + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = FLASH_BANK_2; + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*return the faulty address*/ + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Address; + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*Stop the procedure ongoing*/ + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* FLASH error interrupt user callback */ + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(temp); + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (FLASH_CR_OPERRIE) + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Disable Bank1 Operation and Error source interrupt */ + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BA + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BA + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Disable Bank2 Operation and Error source interrupt */ + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BA + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BA + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #else + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Disable Bank1 Operation and Error source interrupt */ + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BA + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Disable Bank2 Operation and Error source interrupt */ + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BA + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_CR_OPERRIE */ + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Process Unlocked */ + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + ARM GAS /tmp/ccCw6Rev.s page 14 + + + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief FLASH end of operation interrupt callback + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * Mass Erase: Bank number which has been requested to erase + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * Sectors Erase: Sector which has been erased + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * Program: Address which was selected for data program + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval None + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 29 .loc 1 728 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** UNUSED(ReturnValue); + 34 .loc 1 730 3 view .LVU1 + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 35 .loc 1 735 1 is_stmt 0 view .LVU2 + 36 0000 7047 bx lr + 37 .cfi_endproc + 38 .LFE144: + 40 .section .text.HAL_FLASH_OperationErrorCallback,"ax",%progbits + 41 .align 1 + 42 .weak HAL_FLASH_OperationErrorCallback + 43 .syntax unified + 44 .thumb + 45 .thumb_func + 46 .fpu fpv5-d16 + 48 HAL_FLASH_OperationErrorCallback: + 49 .LVL1: + 50 .LFB145: + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief FLASH operation error interrupt callback + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * Mass Erase: Bank number which has been requested to erase + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * Sectors Erase: Sector number which returned an error + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * Program: Address which was selected for data program + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval None + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 51 .loc 1 746 1 is_stmt 1 view -0 + 52 .cfi_startproc + 53 @ args = 0, pretend = 0, frame = 0 + 54 @ frame_needed = 0, uses_anonymous_args = 0 + 55 @ link register save eliminated. + ARM GAS /tmp/ccCw6Rev.s page 15 + + + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** UNUSED(ReturnValue); + 56 .loc 1 748 3 view .LVU4 + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** the HAL_FLASH_OperationErrorCallback could be implemented in the user file + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 57 .loc 1 753 1 is_stmt 0 view .LVU5 + 58 0000 7047 bx lr + 59 .cfi_endproc + 60 .LFE145: + 62 .section .text.HAL_FLASH_IRQHandler,"ax",%progbits + 63 .align 1 + 64 .global HAL_FLASH_IRQHandler + 65 .syntax unified + 66 .thumb + 67 .thumb_func + 68 .fpu fpv5-d16 + 70 HAL_FLASH_IRQHandler: + 71 .LFB143: + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t temp; + 72 .loc 1 458 1 is_stmt 1 view -0 + 73 .cfi_startproc + 74 @ args = 0, pretend = 0, frame = 0 + 75 @ frame_needed = 0, uses_anonymous_args = 0 + 76 0000 10B5 push {r4, lr} + 77 .LCFI0: + 78 .cfi_def_cfa_offset 8 + 79 .cfi_offset 4, -8 + 80 .cfi_offset 14, -4 + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t errorflag; + 81 .loc 1 459 3 view .LVU7 + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_ProcedureTypeDef procedure; + 82 .loc 1 460 3 view .LVU8 + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 83 .loc 1 461 3 view .LVU9 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 84 .loc 1 464 3 view .LVU10 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 85 .loc 1 464 6 is_stmt 0 view .LVU11 + 86 0002 3D4B ldr r3, .L19 + 87 0004 1B69 ldr r3, [r3, #16] + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 88 .loc 1 464 5 view .LVU12 + 89 0006 13F4803F tst r3, #65536 + 90 000a 18D0 beq .L4 + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 91 .loc 1 466 5 is_stmt 1 view .LVU13 + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 92 .loc 1 466 14 is_stmt 0 view .LVU14 + 93 000c 3B4B ldr r3, .L19+4 + 94 000e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 95 0010 DBB2 uxtb r3, r3 + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 96 .loc 1 466 7 view .LVU15 + 97 0012 012B cmp r3, #1 + ARM GAS /tmp/ccCw6Rev.s page 16 + + + 98 0014 29D0 beq .L15 + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 99 .loc 1 501 7 is_stmt 1 view .LVU16 + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 100 .loc 1 501 17 is_stmt 0 view .LVU17 + 101 0016 394B ldr r3, .L19+4 + 102 0018 1C78 ldrb r4, [r3] @ zero_extendqisi2 + 103 001a E4B2 uxtb r4, r4 + 104 .LVL2: + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 105 .loc 1 503 7 is_stmt 1 view .LVU18 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 106 .loc 1 503 9 is_stmt 0 view .LVU19 + 107 001c 072C cmp r4, #7 + 108 001e 18BF it ne + 109 0020 022C cmpne r4, #2 + 110 0022 47D0 beq .L16 + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 111 .loc 1 509 12 is_stmt 1 view .LVU20 + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 112 .loc 1 509 14 is_stmt 0 view .LVU21 + 113 0024 032C cmp r4, #3 + 114 0026 49D0 beq .L17 + 115 .L8: + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 116 .loc 1 518 7 is_stmt 1 view .LVU22 + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_MASSERASE_BANK2) && \ + 117 .loc 1 520 7 view .LVU23 + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_PROGRAM_BANK2)) + 118 .loc 1 521 52 is_stmt 0 view .LVU24 + 119 0028 043C subs r4, r4, #4 + 120 .LVL3: + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_PROGRAM_BANK2)) + 121 .loc 1 521 52 view .LVU25 + 122 002a E4B2 uxtb r4, r4 + 123 .LVL4: + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** (procedure != FLASH_PROC_MASSERASE_BANK2) && \ + 124 .loc 1 520 9 view .LVU26 + 125 002c 022C cmp r4, #2 + 126 002e 06D9 bls .L4 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 127 .loc 1 524 9 is_stmt 1 view .LVU27 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 128 .loc 1 524 33 is_stmt 0 view .LVU28 + 129 0030 324B ldr r3, .L19+4 + 130 0032 0022 movs r2, #0 + 131 0034 1A70 strb r2, [r3] + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 132 .loc 1 526 9 is_stmt 1 view .LVU29 + 133 0036 304B ldr r3, .L19 + 134 0038 4FF48032 mov r2, #65536 + 135 003c 5A61 str r2, [r3, #20] + 136 .L4: + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); + 137 .loc 1 603 3 view .LVU30 + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); + 138 .loc 1 603 20 is_stmt 0 view .LVU31 + ARM GAS /tmp/ccCw6Rev.s page 17 + + + 139 003e 2E4B ldr r3, .L19 + 140 0040 1B69 ldr r3, [r3, #16] + 141 .LVL5: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 142 .loc 1 610 3 is_stmt 1 view .LVU32 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 143 .loc 1 610 5 is_stmt 0 view .LVU33 + 144 0042 13F4DC03 ands r3, r3, #7208960 + 145 .LVL6: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 146 .loc 1 610 5 view .LVU34 + 147 0046 48D0 beq .L9 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 148 .loc 1 613 5 is_stmt 1 view .LVU35 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 149 .loc 1 613 22 is_stmt 0 view .LVU36 + 150 0048 2C4A ldr r2, .L19+4 + 151 004a 9169 ldr r1, [r2, #24] + 152 004c 1943 orrs r1, r1, r3 + 153 004e 9161 str r1, [r2, #24] + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 154 .loc 1 616 5 is_stmt 1 view .LVU37 + 155 0050 2949 ldr r1, .L19 + 156 0052 4B61 str r3, [r1, #20] + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 157 .loc 1 618 5 view .LVU38 + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 158 .loc 1 618 15 is_stmt 0 view .LVU39 + 159 0054 1378 ldrb r3, [r2] @ zero_extendqisi2 + 160 .LVL7: + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 161 .loc 1 618 15 view .LVU40 + 162 0056 DBB2 uxtb r3, r3 + 163 .LVL8: + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 164 .loc 1 620 5 is_stmt 1 view .LVU41 + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 165 .loc 1 620 7 is_stmt 0 view .LVU42 + 166 0058 012B cmp r3, #1 + 167 005a 34D0 beq .L18 + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 168 .loc 1 626 10 is_stmt 1 view .LVU43 + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 169 .loc 1 626 12 is_stmt 0 view .LVU44 + 170 005c 072B cmp r3, #7 + 171 005e 18BF it ne + 172 0060 022B cmpne r3, #2 + 173 0062 46D0 beq .L13 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 174 .loc 1 634 7 is_stmt 1 view .LVU45 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 175 .loc 1 634 12 is_stmt 0 view .LVU46 + 176 0064 254B ldr r3, .L19+4 + 177 .LVL9: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 178 .loc 1 634 12 view .LVU47 + 179 0066 1869 ldr r0, [r3, #16] + ARM GAS /tmp/ccCw6Rev.s page 18 + + + 180 .LVL10: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 181 .loc 1 634 12 view .LVU48 + 182 0068 32E0 b .L11 + 183 .LVL11: + 184 .L15: + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 185 .loc 1 469 7 is_stmt 1 view .LVU49 + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 186 .loc 1 469 13 is_stmt 0 view .LVU50 + 187 006a 244B ldr r3, .L19+4 + 188 006c 5A68 ldr r2, [r3, #4] + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 189 .loc 1 469 30 view .LVU51 + 190 006e 013A subs r2, r2, #1 + 191 0070 5A60 str r2, [r3, #4] + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 192 .loc 1 472 7 is_stmt 1 view .LVU52 + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 193 .loc 1 472 16 is_stmt 0 view .LVU53 + 194 0072 5B68 ldr r3, [r3, #4] + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 195 .loc 1 472 9 view .LVU54 + 196 0074 83B1 cbz r3, .L6 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 197 .loc 1 475 9 is_stmt 1 view .LVU55 + 198 0076 214C ldr r4, .L19+4 + 199 0078 E068 ldr r0, [r4, #12] + 200 007a FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 201 .LVL12: + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 202 .loc 1 478 9 view .LVU56 + 203 007e 1E4B ldr r3, .L19 + 204 0080 4FF48032 mov r2, #65536 + 205 0084 5A61 str r2, [r3, #20] + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 206 .loc 1 481 9 view .LVU57 + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 207 .loc 1 481 15 is_stmt 0 view .LVU58 + 208 0086 E368 ldr r3, [r4, #12] + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** temp = pFlash.Sector; + 209 .loc 1 481 22 view .LVU59 + 210 0088 0133 adds r3, r3, #1 + 211 008a E360 str r3, [r4, #12] + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); + 212 .loc 1 482 9 is_stmt 1 view .LVU60 + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); + 213 .loc 1 482 14 is_stmt 0 view .LVU61 + 214 008c E068 ldr r0, [r4, #12] + 215 .LVL13: + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 216 .loc 1 483 9 is_stmt 1 view .LVU62 + 217 008e A268 ldr r2, [r4, #8] + 218 0090 0121 movs r1, #1 + 219 0092 FFF7FEFF bl FLASH_Erase_Sector + 220 .LVL14: + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + ARM GAS /tmp/ccCw6Rev.s page 19 + + + 221 .loc 1 483 9 is_stmt 0 view .LVU63 + 222 0096 D2E7 b .L4 + 223 .L6: + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 224 .loc 1 489 9 is_stmt 1 view .LVU64 + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 225 .loc 1 489 23 is_stmt 0 view .LVU65 + 226 0098 184B ldr r3, .L19+4 + 227 009a 4FF0FF32 mov r2, #-1 + 228 009e DA60 str r2, [r3, #12] + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 229 .loc 1 490 9 is_stmt 1 view .LVU66 + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 230 .loc 1 490 33 is_stmt 0 view .LVU67 + 231 00a0 0022 movs r2, #0 + 232 00a2 1A70 strb r2, [r3] + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 233 .loc 1 493 9 is_stmt 1 view .LVU68 + 234 00a4 D868 ldr r0, [r3, #12] + 235 00a6 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 236 .LVL15: + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 237 .loc 1 496 9 view .LVU69 + 238 00aa 134B ldr r3, .L19 + 239 00ac 4FF48032 mov r2, #65536 + 240 00b0 5A61 str r2, [r3, #20] + 241 00b2 C4E7 b .L4 + 242 .LVL16: + 243 .L16: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 244 .loc 1 507 9 view .LVU70 + 245 00b4 0120 movs r0, #1 + 246 00b6 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 247 .LVL17: + 248 00ba B5E7 b .L8 + 249 .L17: + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 250 .loc 1 513 9 view .LVU71 + 251 00bc 0F4B ldr r3, .L19+4 + 252 00be 1869 ldr r0, [r3, #16] + 253 00c0 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 254 .LVL18: + 255 00c4 B0E7 b .L8 + 256 .LVL19: + 257 .L18: + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 258 .loc 1 623 7 view .LVU72 + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 259 .loc 1 623 12 is_stmt 0 view .LVU73 + 260 00c6 1346 mov r3, r2 + 261 .LVL20: + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 262 .loc 1 623 12 view .LVU74 + 263 00c8 D068 ldr r0, [r2, #12] + 264 .LVL21: + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 265 .loc 1 624 7 is_stmt 1 view .LVU75 + ARM GAS /tmp/ccCw6Rev.s page 20 + + + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 266 .loc 1 624 21 is_stmt 0 view .LVU76 + 267 00ca 4FF0FF32 mov r2, #-1 + 268 00ce DA60 str r2, [r3, #12] + 269 .LVL22: + 270 .L11: + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 271 .loc 1 638 5 is_stmt 1 view .LVU77 + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 272 .loc 1 638 29 is_stmt 0 view .LVU78 + 273 00d0 0A4B ldr r3, .L19+4 + 274 00d2 0022 movs r2, #0 + 275 00d4 1A70 strb r2, [r3] + 276 .LVL23: + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 277 .loc 1 641 5 is_stmt 1 view .LVU79 + 278 00d6 FFF7FEFF bl HAL_FLASH_OperationErrorCallback + 279 .LVL24: + 280 .L9: + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 281 .loc 1 689 3 view .LVU80 + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 282 .loc 1 689 12 is_stmt 0 view .LVU81 + 283 00da 084B ldr r3, .L19+4 + 284 00dc 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 285 .loc 1 689 5 view .LVU82 + 286 00de 3BB9 cbnz r3, .L3 + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BA + 287 .loc 1 693 5 is_stmt 1 view .LVU83 + 288 00e0 054A ldr r2, .L19 + 289 00e2 D368 ldr r3, [r2, #12] + 290 00e4 23F4DE03 bic r3, r3, #7274496 + 291 00e8 D360 str r3, [r2, #12] + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 292 .loc 1 714 5 view .LVU84 + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 293 .loc 1 714 5 view .LVU85 + 294 00ea 044B ldr r3, .L19+4 + 295 00ec 0022 movs r2, #0 + 296 00ee 1A75 strb r2, [r3, #20] + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 297 .loc 1 714 5 view .LVU86 + 298 .L3: + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 299 .loc 1 716 1 is_stmt 0 view .LVU87 + 300 00f0 10BD pop {r4, pc} + 301 .LVL25: + 302 .L13: + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 303 .loc 1 629 12 view .LVU88 + 304 00f2 0120 movs r0, #1 + 305 00f4 ECE7 b .L11 + 306 .L20: + 307 00f6 00BF .align 2 + 308 .L19: + 309 00f8 00200052 .word 1375739904 + ARM GAS /tmp/ccCw6Rev.s page 21 + + + 310 00fc 00000000 .word .LANCHOR0 + 311 .cfi_endproc + 312 .LFE143: + 314 .section .text.HAL_FLASH_Unlock,"ax",%progbits + 315 .align 1 + 316 .global HAL_FLASH_Unlock + 317 .syntax unified + 318 .thumb + 319 .thumb_func + 320 .fpu fpv5-d16 + 322 HAL_FLASH_Unlock: + 323 .LFB146: + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @} + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Management functions + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @verbatim + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** =============================================================================== + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ##### Peripheral Control functions ##### + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** =============================================================================== + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** This subsection provides a set of functions allowing to control the FLASH + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** memory operations. + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @endverbatim + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Unlock the FLASH control registers access + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL Status + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void) + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 324 .loc 1 779 1 is_stmt 1 view -0 + 325 .cfi_startproc + 326 @ args = 0, pretend = 0, frame = 0 + 327 @ frame_needed = 0, uses_anonymous_args = 0 + 328 @ link register save eliminated. + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + 329 .loc 1 780 3 view .LVU90 + 330 .loc 1 780 6 is_stmt 0 view .LVU91 + 331 0000 0A4B ldr r3, .L25 + 332 0002 DB68 ldr r3, [r3, #12] + 333 .loc 1 780 5 view .LVU92 + 334 0004 13F0010F tst r3, #1 + 335 0008 0BD0 beq .L23 + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Authorize the FLASH Bank1 Registers access */ + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + 336 .loc 1 783 5 is_stmt 1 view .LVU93 + 337 000a 084B ldr r3, .L25 + 338 000c 084A ldr r2, .L25+4 + ARM GAS /tmp/ccCw6Rev.s page 22 + + + 339 000e 5A60 str r2, [r3, #4] + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + 340 .loc 1 784 5 view .LVU94 + 341 0010 02F18832 add r2, r2, #-2004318072 + 342 0014 5A60 str r2, [r3, #4] + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Verify Flash Bank1 is unlocked */ + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + 343 .loc 1 787 5 view .LVU95 + 344 .loc 1 787 9 is_stmt 0 view .LVU96 + 345 0016 DB68 ldr r3, [r3, #12] + 346 .loc 1 787 8 view .LVU97 + 347 0018 13F0010F tst r3, #1 + 348 001c 03D1 bne .L24 + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Authorize the FLASH Bank2 Registers access */ + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Verify Flash Bank2 is unlocked */ + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 349 .loc 1 808 10 view .LVU98 + 350 001e 0020 movs r0, #0 + 351 0020 7047 bx lr + 352 .L23: + 353 0022 0020 movs r0, #0 + 354 0024 7047 bx lr + 355 .L24: + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 356 .loc 1 789 14 view .LVU99 + 357 0026 0120 movs r0, #1 + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 358 .loc 1 809 1 view .LVU100 + 359 0028 7047 bx lr + 360 .L26: + 361 002a 00BF .align 2 + 362 .L25: + 363 002c 00200052 .word 1375739904 + 364 0030 23016745 .word 1164378403 + 365 .cfi_endproc + 366 .LFE146: + 368 .section .text.HAL_FLASH_Lock,"ax",%progbits + 369 .align 1 + ARM GAS /tmp/ccCw6Rev.s page 23 + + + 370 .global HAL_FLASH_Lock + 371 .syntax unified + 372 .thumb + 373 .thumb_func + 374 .fpu fpv5-d16 + 376 HAL_FLASH_Lock: + 377 .LFB147: + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Locks the FLASH control registers access + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL Status + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void) + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 378 .loc 1 816 1 is_stmt 1 view -0 + 379 .cfi_startproc + 380 @ args = 0, pretend = 0, frame = 0 + 381 @ frame_needed = 0, uses_anonymous_args = 0 + 382 @ link register save eliminated. + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */ + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + 383 .loc 1 818 3 view .LVU102 + 384 0000 064B ldr r3, .L30 + 385 0002 DA68 ldr r2, [r3, #12] + 386 0004 42F00102 orr r2, r2, #1 + 387 0008 DA60 str r2, [r3, #12] + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Verify Flash Bank1 is locked */ + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U) + 388 .loc 1 821 3 view .LVU103 + 389 .loc 1 821 7 is_stmt 0 view .LVU104 + 390 000a DB68 ldr r3, [r3, #12] + 391 .loc 1 821 6 view .LVU105 + 392 000c 13F0010F tst r3, #1 + 393 0010 01D0 beq .L29 + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */ + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Verify Flash Bank2 is locked */ + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U) + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 394 .loc 1 837 10 view .LVU106 + 395 0012 0020 movs r0, #0 + 396 0014 7047 bx lr + 397 .L29: + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 398 .loc 1 823 12 view .LVU107 + ARM GAS /tmp/ccCw6Rev.s page 24 + + + 399 0016 0120 movs r0, #1 + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 400 .loc 1 838 1 view .LVU108 + 401 0018 7047 bx lr + 402 .L31: + 403 001a 00BF .align 2 + 404 .L30: + 405 001c 00200052 .word 1375739904 + 406 .cfi_endproc + 407 .LFE147: + 409 .section .text.HAL_FLASH_OB_Unlock,"ax",%progbits + 410 .align 1 + 411 .global HAL_FLASH_OB_Unlock + 412 .syntax unified + 413 .thumb + 414 .thumb_func + 415 .fpu fpv5-d16 + 417 HAL_FLASH_OB_Unlock: + 418 .LFB148: + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Unlock the FLASH Option Control Registers access. + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL Status + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 419 .loc 1 845 1 is_stmt 1 view -0 + 420 .cfi_startproc + 421 @ args = 0, pretend = 0, frame = 0 + 422 @ frame_needed = 0, uses_anonymous_args = 0 + 423 @ link register save eliminated. + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + 424 .loc 1 846 3 view .LVU110 + 425 .loc 1 846 6 is_stmt 0 view .LVU111 + 426 0000 0A4B ldr r3, .L36 + 427 0002 9B69 ldr r3, [r3, #24] + 428 .loc 1 846 5 view .LVU112 + 429 0004 13F0010F tst r3, #1 + 430 0008 0BD0 beq .L34 + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Authorizes the Option Byte registers programming */ + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1); + 431 .loc 1 849 5 is_stmt 1 view .LVU113 + 432 000a 084B ldr r3, .L36 + 433 000c 084A ldr r2, .L36+4 + 434 000e 9A60 str r2, [r3, #8] + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2); + 435 .loc 1 850 5 view .LVU114 + 436 0010 02F14432 add r2, r2, #1145324612 + 437 0014 9A60 str r2, [r3, #8] + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Verify that the Option Bytes are unlocked */ + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + 438 .loc 1 853 5 view .LVU115 + 439 .loc 1 853 9 is_stmt 0 view .LVU116 + 440 0016 9B69 ldr r3, [r3, #24] + 441 .loc 1 853 8 view .LVU117 + ARM GAS /tmp/ccCw6Rev.s page 25 + + + 442 0018 13F0010F tst r3, #1 + 443 001c 03D1 bne .L35 + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 444 .loc 1 859 10 view .LVU118 + 445 001e 0020 movs r0, #0 + 446 0020 7047 bx lr + 447 .L34: + 448 0022 0020 movs r0, #0 + 449 0024 7047 bx lr + 450 .L35: + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 451 .loc 1 855 14 view .LVU119 + 452 0026 0120 movs r0, #1 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 453 .loc 1 860 1 view .LVU120 + 454 0028 7047 bx lr + 455 .L37: + 456 002a 00BF .align 2 + 457 .L36: + 458 002c 00200052 .word 1375739904 + 459 0030 3B2A1908 .word 135866939 + 460 .cfi_endproc + 461 .LFE148: + 463 .section .text.HAL_FLASH_OB_Lock,"ax",%progbits + 464 .align 1 + 465 .global HAL_FLASH_OB_Lock + 466 .syntax unified + 467 .thumb + 468 .thumb_func + 469 .fpu fpv5-d16 + 471 HAL_FLASH_OB_Lock: + 472 .LFB149: + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Lock the FLASH Option Control Registers access. + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL Status + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 473 .loc 1 867 1 is_stmt 1 view -0 + 474 .cfi_startproc + 475 @ args = 0, pretend = 0, frame = 0 + 476 @ frame_needed = 0, uses_anonymous_args = 0 + 477 @ link register save eliminated. + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); + 478 .loc 1 869 3 view .LVU122 + 479 0000 064B ldr r3, .L41 + 480 0002 9A69 ldr r2, [r3, #24] + 481 0004 42F00102 orr r2, r2, #1 + 482 0008 9A61 str r2, [r3, #24] + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + ARM GAS /tmp/ccCw6Rev.s page 26 + + + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Verify that the Option Bytes are locked */ + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U) + 483 .loc 1 872 3 view .LVU123 + 484 .loc 1 872 7 is_stmt 0 view .LVU124 + 485 000a 9B69 ldr r3, [r3, #24] + 486 .loc 1 872 6 view .LVU125 + 487 000c 13F0010F tst r3, #1 + 488 0010 01D0 beq .L40 + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 489 .loc 1 877 10 view .LVU126 + 490 0012 0020 movs r0, #0 + 491 0014 7047 bx lr + 492 .L40: + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 493 .loc 1 874 12 view .LVU127 + 494 0016 0120 movs r0, #1 + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 495 .loc 1 878 1 view .LVU128 + 496 0018 7047 bx lr + 497 .L42: + 498 001a 00BF .align 2 + 499 .L41: + 500 001c 00200052 .word 1375739904 + 501 .cfi_endproc + 502 .LFE149: + 504 .section .text.HAL_FLASH_GetError,"ax",%progbits + 505 .align 1 + 506 .global HAL_FLASH_GetError + 507 .syntax unified + 508 .thumb + 509 .thumb_func + 510 .fpu fpv5-d16 + 512 HAL_FLASH_GetError: + 513 .LFB151: + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Launch the option bytes loading. + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL Status + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for CRC computation to be completed */ + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = HAL_ERROR; + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = HAL_ERROR; + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + ARM GAS /tmp/ccCw6Rev.s page 27 + + + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = HAL_OK; + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (status == HAL_OK) + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Set OPTSTRT Bit */ + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for OB change operation to be completed */ + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return status; + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @} + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Peripheral Errors functions + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @verbatim + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** =============================================================================== + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** ##### Peripheral Errors functions ##### + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** =============================================================================== + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** [..] + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** This subsection permits to get in run-time Errors of the FLASH peripheral. + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** @endverbatim + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Get the specific FLASH error flag. + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL_FLASH_ERRORCode The returned value can be: + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_NONE : No error set + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_WRP_BANK1 : Write Protection Error on Bank 1 + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1 + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1 + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1 + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1 + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1 + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1 + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1 + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1 + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1 + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2 + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2 + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2 + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2 + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2 + ARM GAS /tmp/ccCw6Rev.s page 28 + + + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2 + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2 + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2 + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2 + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2 + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void) + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 514 .loc 1 963 1 is_stmt 1 view -0 + 515 .cfi_startproc + 516 @ args = 0, pretend = 0, frame = 0 + 517 @ frame_needed = 0, uses_anonymous_args = 0 + 518 @ link register save eliminated. + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return pFlash.ErrorCode; + 519 .loc 1 964 4 view .LVU130 + 520 .loc 1 964 17 is_stmt 0 view .LVU131 + 521 0000 014B ldr r3, .L44 + 522 0002 9869 ldr r0, [r3, #24] + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 523 .loc 1 965 1 view .LVU132 + 524 0004 7047 bx lr + 525 .L45: + 526 0006 00BF .align 2 + 527 .L44: + 528 0008 00000000 .word .LANCHOR0 + 529 .cfi_endproc + 530 .LFE151: + 532 .section .text.FLASH_WaitForLastOperation,"ax",%progbits + 533 .align 1 + 534 .global FLASH_WaitForLastOperation + 535 .syntax unified + 536 .thumb + 537 .thumb_func + 538 .fpu fpv5-d16 + 540 FLASH_WaitForLastOperation: + 541 .LVL26: + 542 .LFB152: + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @} + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @} + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Private functions ---------------------------------------------------------*/ + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @{ + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Wait for a FLASH operation to complete. + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param Timeout maximum flash operation timeout + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + ARM GAS /tmp/ccCw6Rev.s page 29 + + + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 543 .loc 1 988 1 is_stmt 1 view -0 + 544 .cfi_startproc + 545 @ args = 0, pretend = 0, frame = 0 + 546 @ frame_needed = 0, uses_anonymous_args = 0 + 547 .loc 1 988 1 is_stmt 0 view .LVU134 + 548 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 549 .LCFI1: + 550 .cfi_def_cfa_offset 24 + 551 .cfi_offset 3, -24 + 552 .cfi_offset 4, -20 + 553 .cfi_offset 5, -16 + 554 .cfi_offset 6, -12 + 555 .cfi_offset 7, -8 + 556 .cfi_offset 14, -4 + 557 0002 0446 mov r4, r0 + 558 0004 0F46 mov r7, r1 + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on QW flag to be reset. + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** Even if the FLASH operation fails, the QW flag will be reset and an error + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** flag will be set */ + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t bsyflag = FLASH_FLAG_QW_BANK1; + 559 .loc 1 993 3 is_stmt 1 view .LVU135 + 560 .LVL27: + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; + 561 .loc 1 994 3 view .LVU136 + 562 .loc 1 994 29 is_stmt 0 view .LVU137 + 563 0006 1C4B ldr r3, .L60 + 564 0008 1D69 ldr r5, [r3, #16] + 565 .loc 1 994 12 view .LVU138 + 566 000a 25F06845 bic r5, r5, #-402653184 + 567 000e 25F48015 bic r5, r5, #1048576 + 568 0012 6D0C lsrs r5, r5, #17 + 569 0014 6D04 lsls r5, r5, #17 + 570 .LVL28: + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t tickstart = HAL_GetTick(); + 571 .loc 1 995 3 is_stmt 1 view .LVU139 + 572 .loc 1 995 24 is_stmt 0 view .LVU140 + 573 0016 FFF7FEFF bl HAL_GetTick + 574 .LVL29: + 575 .loc 1 995 24 view .LVU141 + 576 001a 0646 mov r6, r0 + 577 .LVL30: + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + 578 .loc 1 997 3 is_stmt 1 view .LVU142 + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (Bank == FLASH_BANK_2) +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Get Error Flags */ +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Select bsyflag depending on Bank */ + ARM GAS /tmp/ccCw6Rev.s page 30 + + +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bsyflag = FLASH_FLAG_QW_BANK2; +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** while(__HAL_FLASH_GET_FLAG(bsyflag)) + 579 .loc 1 1010 3 view .LVU143 + 580 .L48: + 581 .loc 1 1010 8 view .LVU144 + 582 .loc 1 1010 9 is_stmt 0 view .LVU145 + 583 001c 164B ldr r3, .L60 + 584 001e 1B69 ldr r3, [r3, #16] + 585 .loc 1 1010 8 view .LVU146 + 586 0020 13F0040F tst r3, #4 + 587 0024 0BD0 beq .L57 +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(Timeout != HAL_MAX_DELAY) + 588 .loc 1 1012 5 is_stmt 1 view .LVU147 + 589 .loc 1 1012 7 is_stmt 0 view .LVU148 + 590 0026 B4F1FF3F cmp r4, #-1 + 591 002a F7D0 beq .L48 +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 592 .loc 1 1014 7 is_stmt 1 view .LVU149 + 593 .loc 1 1014 12 is_stmt 0 view .LVU150 + 594 002c FFF7FEFF bl HAL_GetTick + 595 .LVL31: + 596 .loc 1 1014 26 view .LVU151 + 597 0030 801B subs r0, r0, r6 + 598 .loc 1 1014 9 view .LVU152 + 599 0032 A042 cmp r0, r4 + 600 0034 1BD8 bhi .L52 + 601 .loc 1 1014 50 discriminator 1 view .LVU153 + 602 0036 002C cmp r4, #0 + 603 0038 F0D1 bne .L48 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_TIMEOUT; + 604 .loc 1 1016 16 view .LVU154 + 605 003a 0320 movs r0, #3 + 606 003c 03E0 b .L49 + 607 .L57: +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* In case of error reported in Flash SR1 or SR2 register */ +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if((errorflag & 0x7FFFFFFFU) != 0U) + 608 .loc 1 1022 3 is_stmt 1 view .LVU155 + 609 .loc 1 1022 5 is_stmt 0 view .LVU156 + 610 003e 1DB9 cbnz r5, .L58 +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /*Save the error code*/ +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode |= errorflag; +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear error programming flags */ +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(errorflag); +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; + ARM GAS /tmp/ccCw6Rev.s page 31 + + +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check FLASH End of Operation flag */ +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(Bank == FLASH_BANK_1) + 611 .loc 1 1034 3 is_stmt 1 view .LVU157 + 612 .loc 1 1034 5 is_stmt 0 view .LVU158 + 613 0040 012F cmp r7, #1 + 614 0042 09D0 beq .L59 +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1)) +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2)) +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 615 .loc 1 1053 10 view .LVU159 + 616 0044 0020 movs r0, #0 + 617 .L49: +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 618 .loc 1 1054 1 view .LVU160 + 619 0046 F8BD pop {r3, r4, r5, r6, r7, pc} + 620 .LVL32: + 621 .L58: +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 622 .loc 1 1025 5 is_stmt 1 view .LVU161 +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 623 .loc 1 1025 22 is_stmt 0 view .LVU162 + 624 0048 0C4A ldr r2, .L60+4 + 625 004a 9369 ldr r3, [r2, #24] + 626 004c 2B43 orrs r3, r3, r5 + 627 004e 9361 str r3, [r2, #24] +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 628 .loc 1 1028 5 is_stmt 1 view .LVU163 + 629 0050 094B ldr r3, .L60 + 630 0052 5D61 str r5, [r3, #20] +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 631 .loc 1 1030 5 view .LVU164 +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 632 .loc 1 1030 12 is_stmt 0 view .LVU165 + 633 0054 0120 movs r0, #1 + 634 0056 F6E7 b .L49 + 635 .L59: +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 636 .loc 1 1036 5 is_stmt 1 view .LVU166 +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + ARM GAS /tmp/ccCw6Rev.s page 32 + + + 637 .loc 1 1036 9 is_stmt 0 view .LVU167 + 638 0058 074B ldr r3, .L60 + 639 005a 1B69 ldr r3, [r3, #16] +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 640 .loc 1 1036 8 view .LVU168 + 641 005c 13F4803F tst r3, #65536 + 642 0060 07D0 beq .L55 +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 643 .loc 1 1039 7 is_stmt 1 view .LVU169 + 644 0062 054B ldr r3, .L60 + 645 0064 4FF48032 mov r2, #65536 + 646 0068 5A61 str r2, [r3, #20] +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 647 .loc 1 1053 10 is_stmt 0 view .LVU170 + 648 006a 0020 movs r0, #0 + 649 006c EBE7 b .L49 + 650 .L52: +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 651 .loc 1 1016 16 view .LVU171 + 652 006e 0320 movs r0, #3 + 653 0070 E9E7 b .L49 + 654 .L55: +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 655 .loc 1 1053 10 view .LVU172 + 656 0072 0020 movs r0, #0 + 657 0074 E7E7 b .L49 + 658 .L61: + 659 0076 00BF .align 2 + 660 .L60: + 661 0078 00200052 .word 1375739904 + 662 007c 00000000 .word .LANCHOR0 + 663 .cfi_endproc + 664 .LFE152: + 666 .section .text.HAL_FLASH_Program,"ax",%progbits + 667 .align 1 + 668 .global HAL_FLASH_Program + 669 .syntax unified + 670 .thumb + 671 .thumb_func + 672 .fpu fpv5-d16 + 674 HAL_FLASH_Program: + 675 .LVL33: + 676 .LFB141: + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 677 .loc 1 146 1 is_stmt 1 view -0 + 678 .cfi_startproc + 679 @ args = 0, pretend = 0, frame = 0 + 680 @ frame_needed = 0, uses_anonymous_args = 0 + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 681 .loc 1 146 1 is_stmt 0 view .LVU174 + 682 0000 38B5 push {r3, r4, r5, lr} + 683 .LCFI2: + 684 .cfi_def_cfa_offset 16 + 685 .cfi_offset 3, -16 + 686 .cfi_offset 4, -12 + 687 .cfi_offset 5, -8 + 688 .cfi_offset 14, -4 + ARM GAS /tmp/ccCw6Rev.s page 33 + + + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress; + 689 .loc 1 147 3 is_stmt 1 view .LVU175 + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + 690 .loc 1 148 3 view .LVU176 + 691 .LVL34: + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t bank; + 692 .loc 1 149 3 view .LVU177 + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + 693 .loc 1 150 3 view .LVU178 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 694 .loc 1 151 3 view .LVU179 + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + 695 .loc 1 154 3 view .LVU180 + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 696 .loc 1 155 3 view .LVU181 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 697 .loc 1 158 3 view .LVU182 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 698 .loc 1 158 3 view .LVU183 + 699 0002 1F4B ldr r3, .L70 + 700 0004 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 701 0006 012B cmp r3, #1 + 702 0008 37D0 beq .L66 + 703 000a 0D46 mov r5, r1 + 704 000c 1446 mov r4, r2 + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 705 .loc 1 158 3 discriminator 2 view .LVU184 + 706 000e 1C4B ldr r3, .L70 + 707 0010 0122 movs r2, #1 + 708 .LVL35: + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 709 .loc 1 158 3 is_stmt 0 discriminator 2 view .LVU185 + 710 0012 1A75 strb r2, [r3, #20] + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 711 .loc 1 158 3 is_stmt 1 discriminator 2 view .LVU186 + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 712 .loc 1 163 3 discriminator 2 view .LVU187 + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 713 .loc 1 163 6 is_stmt 0 discriminator 2 view .LVU188 + 714 0014 01F17841 add r1, r1, #-134217728 + 715 .LVL36: + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 716 .loc 1 163 5 discriminator 2 view .LVU189 + 717 0018 B1F5003F cmp r1, #131072 + 718 001c 01D3 bcc .L69 + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 719 .loc 1 176 12 view .LVU190 + 720 001e 0120 movs r0, #1 + 721 .LVL37: + 722 .L63: + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 723 .loc 1 292 1 view .LVU191 + 724 0020 38BD pop {r3, r4, r5, pc} + 725 .LVL38: + 726 .L69: + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 727 .loc 1 166 5 is_stmt 1 view .LVU192 + ARM GAS /tmp/ccCw6Rev.s page 34 + + + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 728 .loc 1 180 3 view .LVU193 + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 729 .loc 1 180 20 is_stmt 0 view .LVU194 + 730 0022 0022 movs r2, #0 + 731 0024 9A61 str r2, [r3, #24] + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 732 .loc 1 183 3 is_stmt 1 view .LVU195 + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 733 .loc 1 183 12 is_stmt 0 view .LVU196 + 734 0026 0121 movs r1, #1 + 735 0028 4CF25030 movw r0, #50000 + 736 .LVL39: + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 737 .loc 1 183 12 view .LVU197 + 738 002c FFF7FEFF bl FLASH_WaitForLastOperation + 739 .LVL40: + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 740 .loc 1 185 3 is_stmt 1 view .LVU198 + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 741 .loc 1 185 5 is_stmt 0 view .LVU199 + 742 0030 F8B9 cbnz r0, .L64 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 743 .loc 1 219 9 is_stmt 1 view .LVU200 + 744 0032 144A ldr r2, .L70+4 + 745 0034 D368 ldr r3, [r2, #12] + 746 0036 43F00203 orr r3, r3, #2 + 747 003a D360 str r3, [r2, #12] + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 748 .loc 1 223 5 view .LVU201 + 749 .LBB18: + 750 .LBI18: + 751 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccCw6Rev.s page 35 + + + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + ARM GAS /tmp/ccCw6Rev.s page 36 + + + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + ARM GAS /tmp/ccCw6Rev.s page 37 + + + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + ARM GAS /tmp/ccCw6Rev.s page 38 + + + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccCw6Rev.s page 39 + + + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccCw6Rev.s page 40 + + + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + ARM GAS /tmp/ccCw6Rev.s page 41 + + + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccCw6Rev.s page 42 + + + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + ARM GAS /tmp/ccCw6Rev.s page 43 + + + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccCw6Rev.s page 44 + + + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + ARM GAS /tmp/ccCw6Rev.s page 45 + + + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + ARM GAS /tmp/ccCw6Rev.s page 46 + + + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccCw6Rev.s page 47 + + + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccCw6Rev.s page 48 + + + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + ARM GAS /tmp/ccCw6Rev.s page 49 + + + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 752 .loc 2 866 27 view .LVU202 + 753 .LBB19: + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 754 .loc 2 868 3 view .LVU203 + 755 .syntax unified + 756 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 757 003c BFF36F8F isb 0xF + 758 @ 0 "" 2 + 759 .thumb + 760 .syntax unified + 761 .LBE19: + 762 .LBE18: + ARM GAS /tmp/ccCw6Rev.s page 50 + + + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 763 .loc 1 224 5 view .LVU204 + 764 .LBB20: + 765 .LBI20: + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 766 .loc 2 877 27 view .LVU205 + 767 .LBB21: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 768 .loc 2 879 3 view .LVU206 + 769 .syntax unified + 770 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 771 0040 BFF34F8F dsb 0xF + 772 @ 0 "" 2 + 773 .thumb + 774 .syntax unified + 775 .LBE21: + 776 .LBE20: + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 777 .loc 1 151 11 is_stmt 0 view .LVU207 + 778 0044 0823 movs r3, #8 + 779 .LVL41: + 780 .L65: + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 781 .loc 1 236 7 is_stmt 1 discriminator 1 view .LVU208 + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 782 .loc 1 238 9 discriminator 1 view .LVU209 + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 783 .loc 1 238 22 is_stmt 0 discriminator 1 view .LVU210 + 784 0046 54F8042B ldr r2, [r4], #4 + 785 .LVL42: + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 786 .loc 1 238 20 discriminator 1 view .LVU211 + 787 004a 45F8042B str r2, [r5], #4 + 788 .LVL43: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** src_addr++; + 789 .loc 1 239 9 is_stmt 1 discriminator 1 view .LVU212 + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** row_index--; + 790 .loc 1 240 9 discriminator 1 view .LVU213 + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } while (row_index != 0U); + 791 .loc 1 241 9 discriminator 1 view .LVU214 + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } while (row_index != 0U); + 792 .loc 1 241 18 is_stmt 0 discriminator 1 view .LVU215 + 793 004e 013B subs r3, r3, #1 + 794 .LVL44: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 795 .loc 1 242 14 is_stmt 1 discriminator 1 view .LVU216 + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 796 .loc 1 242 6 is_stmt 0 discriminator 1 view .LVU217 + ARM GAS /tmp/ccCw6Rev.s page 51 + + + 797 0050 13F0FF03 ands r3, r3, #255 + 798 .LVL45: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 799 .loc 1 242 6 discriminator 1 view .LVU218 + 800 0054 F7D1 bne .L65 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 801 .loc 1 245 5 is_stmt 1 view .LVU219 + 802 .LBB22: + 803 .LBI22: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 804 .loc 2 866 27 view .LVU220 + 805 .LBB23: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 806 .loc 2 868 3 view .LVU221 + 807 .syntax unified + 808 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 809 0056 BFF36F8F isb 0xF + 810 @ 0 "" 2 + 811 .thumb + 812 .syntax unified + 813 .LBE23: + 814 .LBE22: + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 815 .loc 1 246 5 view .LVU222 + 816 .LBB24: + 817 .LBI24: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 818 .loc 2 877 27 view .LVU223 + 819 .LBB25: + 820 .loc 2 879 3 view .LVU224 + 821 .syntax unified + 822 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 823 005a BFF34F8F dsb 0xF + 824 @ 0 "" 2 + 825 .thumb + 826 .syntax unified + 827 .LBE25: + 828 .LBE24: + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 829 .loc 1 249 5 view .LVU225 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 830 .loc 1 249 14 is_stmt 0 view .LVU226 + 831 005e 0121 movs r1, #1 + 832 0060 4CF25030 movw r0, #50000 + 833 .LVL46: + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 834 .loc 1 249 14 view .LVU227 + 835 0064 FFF7FEFF bl FLASH_WaitForLastOperation + 836 .LVL47: + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 837 .loc 1 283 7 is_stmt 1 view .LVU228 + 838 0068 064A ldr r2, .L70+4 + 839 006a D368 ldr r3, [r2, #12] + 840 006c 23F00203 bic r3, r3, #2 + 841 0070 D360 str r3, [r2, #12] + 842 .LVL48: + 843 .L64: + ARM GAS /tmp/ccCw6Rev.s page 52 + + + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 844 .loc 1 289 3 view .LVU229 + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 845 .loc 1 289 3 view .LVU230 + 846 0072 034B ldr r3, .L70 + 847 0074 0022 movs r2, #0 + 848 0076 1A75 strb r2, [r3, #20] + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 849 .loc 1 289 3 view .LVU231 + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 850 .loc 1 291 3 view .LVU232 + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 851 .loc 1 291 10 is_stmt 0 view .LVU233 + 852 0078 D2E7 b .L63 + 853 .LVL49: + 854 .L66: + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 855 .loc 1 158 3 view .LVU234 + 856 007a 0220 movs r0, #2 + 857 .LVL50: + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 858 .loc 1 158 3 view .LVU235 + 859 007c D0E7 b .L63 + 860 .L71: + 861 007e 00BF .align 2 + 862 .L70: + 863 0080 00000000 .word .LANCHOR0 + 864 0084 00200052 .word 1375739904 + 865 .cfi_endproc + 866 .LFE141: + 868 .section .text.HAL_FLASH_Program_IT,"ax",%progbits + 869 .align 1 + 870 .global HAL_FLASH_Program_IT + 871 .syntax unified + 872 .thumb + 873 .thumb_func + 874 .fpu fpv5-d16 + 876 HAL_FLASH_Program_IT: + 877 .LVL51: + 878 .LFB142: + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 879 .loc 1 304 1 is_stmt 1 view -0 + 880 .cfi_startproc + 881 @ args = 0, pretend = 0, frame = 0 + 882 @ frame_needed = 0, uses_anonymous_args = 0 + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress; + 883 .loc 1 305 3 view .LVU237 + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + 884 .loc 1 306 3 view .LVU238 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t bank; + 885 .loc 1 307 3 view .LVU239 + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + 886 .loc 1 308 3 view .LVU240 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 887 .loc 1 309 3 view .LVU241 + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + 888 .loc 1 312 3 view .LVU242 + ARM GAS /tmp/ccCw6Rev.s page 53 + + + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 889 .loc 1 313 3 view .LVU243 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 890 .loc 1 316 3 view .LVU244 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 891 .loc 1 316 3 view .LVU245 + 892 0000 1F4B ldr r3, .L83 + 893 0002 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 894 0004 012B cmp r3, #1 + 895 0006 38D0 beq .L76 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 896 .loc 1 304 1 is_stmt 0 discriminator 2 view .LVU246 + 897 0008 70B5 push {r4, r5, r6, lr} + 898 .LCFI3: + 899 .cfi_def_cfa_offset 16 + 900 .cfi_offset 4, -16 + 901 .cfi_offset 5, -12 + 902 .cfi_offset 6, -8 + 903 .cfi_offset 14, -4 + 904 000a 0D46 mov r5, r1 + 905 000c 0E46 mov r6, r1 + 906 000e 1446 mov r4, r2 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 907 .loc 1 316 3 is_stmt 1 discriminator 2 view .LVU247 + 908 0010 1B4B ldr r3, .L83 + 909 0012 0122 movs r2, #1 + 910 .LVL52: + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 911 .loc 1 316 3 is_stmt 0 discriminator 2 view .LVU248 + 912 0014 1A75 strb r2, [r3, #20] + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 913 .loc 1 316 3 is_stmt 1 discriminator 2 view .LVU249 + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 914 .loc 1 319 3 discriminator 2 view .LVU250 + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 915 .loc 1 319 20 is_stmt 0 discriminator 2 view .LVU251 + 916 0016 0022 movs r2, #0 + 917 0018 9A61 str r2, [r3, #24] + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 918 .loc 1 324 3 is_stmt 1 discriminator 2 view .LVU252 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 919 .loc 1 324 6 is_stmt 0 discriminator 2 view .LVU253 + 920 001a 01F17843 add r3, r1, #-134217728 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* FLASH_OPTCR_PG_OTP */ + 921 .loc 1 324 5 discriminator 2 view .LVU254 + 922 001e B3F5003F cmp r3, #131072 + 923 0022 01D3 bcc .L82 + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 924 .loc 1 337 12 view .LVU255 + 925 0024 0120 movs r0, #1 + 926 .LVL53: + 927 .L73: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 928 .loc 1 451 1 view .LVU256 + 929 0026 70BD pop {r4, r5, r6, pc} + 930 .LVL54: + 931 .L82: + ARM GAS /tmp/ccCw6Rev.s page 54 + + + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 932 .loc 1 327 5 is_stmt 1 view .LVU257 + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 933 .loc 1 341 3 view .LVU258 + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 934 .loc 1 341 12 is_stmt 0 view .LVU259 + 935 0028 0121 movs r1, #1 + 936 .LVL55: + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 937 .loc 1 341 12 view .LVU260 + 938 002a 4CF25030 movw r0, #50000 + 939 .LVL56: + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 940 .loc 1 341 12 view .LVU261 + 941 002e FFF7FEFF bl FLASH_WaitForLastOperation + 942 .LVL57: + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 943 .loc 1 343 3 is_stmt 1 view .LVU262 + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 944 .loc 1 343 6 is_stmt 0 view .LVU263 + 945 0032 18B1 cbz r0, .L74 + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 946 .loc 1 346 5 is_stmt 1 view .LVU264 + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 947 .loc 1 346 5 view .LVU265 + 948 0034 124B ldr r3, .L83 + 949 0036 0022 movs r2, #0 + 950 0038 1A75 strb r2, [r3, #20] + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 951 .loc 1 346 5 view .LVU266 + 952 003a F4E7 b .L73 + 953 .L74: + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 954 .loc 1 350 5 view .LVU267 + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 955 .loc 1 350 20 is_stmt 0 view .LVU268 + 956 003c 104B ldr r3, .L83 + 957 003e 1D61 str r5, [r3, #16] + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 958 .loc 1 399 5 is_stmt 1 view .LVU269 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 959 .loc 1 399 29 is_stmt 0 view .LVU270 + 960 0040 0322 movs r2, #3 + 961 0042 1A70 strb r2, [r3] + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 962 .loc 1 411 7 is_stmt 1 view .LVU271 + 963 0044 0F4B ldr r3, .L83+4 + 964 0046 DA68 ldr r2, [r3, #12] + 965 0048 42F00202 orr r2, r2, #2 + 966 004c DA60 str r2, [r3, #12] + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_B + 967 .loc 1 416 7 view .LVU272 + 968 004e DA68 ldr r2, [r3, #12] + 969 0050 42F4DE02 orr r2, r2, #7274496 + 970 0054 DA60 str r2, [r3, #12] + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 971 .loc 1 424 5 view .LVU273 + ARM GAS /tmp/ccCw6Rev.s page 55 + + + 972 .LBB26: + 973 .LBI26: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 974 .loc 2 866 27 view .LVU274 + 975 .LBB27: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 976 .loc 2 868 3 view .LVU275 + 977 .syntax unified + 978 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 979 0056 BFF36F8F isb 0xF + 980 @ 0 "" 2 + 981 .thumb + 982 .syntax unified + 983 .LBE27: + 984 .LBE26: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 985 .loc 1 425 5 view .LVU276 + 986 .LBB28: + 987 .LBI28: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 988 .loc 2 877 27 view .LVU277 + 989 .LBB29: + 990 .loc 2 879 3 view .LVU278 + 991 .syntax unified + 992 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 993 005a BFF34F8F dsb 0xF + 994 @ 0 "" 2 + 995 .thumb + 996 .syntax unified + 997 .LBE29: + 998 .LBE28: + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 999 .loc 1 309 11 is_stmt 0 view .LVU279 + 1000 005e 0823 movs r3, #8 + 1001 .LVL58: + 1002 .L75: + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1003 .loc 1 437 7 is_stmt 1 discriminator 1 view .LVU280 + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 1004 .loc 1 439 9 discriminator 1 view .LVU281 + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 1005 .loc 1 439 22 is_stmt 0 discriminator 1 view .LVU282 + 1006 0060 54F8042B ldr r2, [r4], #4 + 1007 .LVL59: + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** dest_addr++; + 1008 .loc 1 439 20 discriminator 1 view .LVU283 + 1009 0064 46F8042B str r2, [r6], #4 + 1010 .LVL60: + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** src_addr++; + 1011 .loc 1 440 9 is_stmt 1 discriminator 1 view .LVU284 + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** row_index--; + 1012 .loc 1 441 9 discriminator 1 view .LVU285 + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } while (row_index != 0U); + 1013 .loc 1 442 9 discriminator 1 view .LVU286 + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } while (row_index != 0U); + 1014 .loc 1 442 18 is_stmt 0 discriminator 1 view .LVU287 + 1015 0068 013B subs r3, r3, #1 + ARM GAS /tmp/ccCw6Rev.s page 56 + + + 1016 .LVL61: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1017 .loc 1 443 15 is_stmt 1 discriminator 1 view .LVU288 + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1018 .loc 1 443 7 is_stmt 0 discriminator 1 view .LVU289 + 1019 006a 13F0FF03 ands r3, r3, #255 + 1020 .LVL62: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1021 .loc 1 443 7 discriminator 1 view .LVU290 + 1022 006e F7D1 bne .L75 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __DSB(); + 1023 .loc 1 446 5 is_stmt 1 view .LVU291 + 1024 .LBB30: + 1025 .LBI30: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1026 .loc 2 866 27 view .LVU292 + 1027 .LBB31: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1028 .loc 2 868 3 view .LVU293 + 1029 .syntax unified + 1030 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1031 0070 BFF36F8F isb 0xF + 1032 @ 0 "" 2 + 1033 .thumb + 1034 .syntax unified + 1035 .LBE31: + 1036 .LBE30: + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1037 .loc 1 447 5 view .LVU294 + 1038 .LBB32: + 1039 .LBI32: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1040 .loc 2 877 27 view .LVU295 + 1041 .LBB33: + 1042 .loc 2 879 3 view .LVU296 + 1043 .syntax unified + 1044 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1045 0074 BFF34F8F dsb 0xF + 1046 @ 0 "" 2 + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1047 .loc 2 880 1 is_stmt 0 view .LVU297 + 1048 .thumb + 1049 .syntax unified + 1050 0078 D5E7 b .L73 + 1051 .LVL63: + 1052 .L76: + 1053 .LCFI4: + 1054 .cfi_def_cfa_offset 0 + 1055 .cfi_restore 4 + 1056 .cfi_restore 5 + 1057 .cfi_restore 6 + 1058 .cfi_restore 14 + 1059 .loc 2 880 1 view .LVU298 + 1060 .LBE33: + 1061 .LBE32: + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1062 .loc 1 316 3 view .LVU299 + ARM GAS /tmp/ccCw6Rev.s page 57 + + + 1063 007a 0220 movs r0, #2 + 1064 .LVL64: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1065 .loc 1 451 1 view .LVU300 + 1066 007c 7047 bx lr + 1067 .L84: + 1068 007e 00BF .align 2 + 1069 .L83: + 1070 0080 00000000 .word .LANCHOR0 + 1071 0084 00200052 .word 1375739904 + 1072 .cfi_endproc + 1073 .LFE142: + 1075 .section .text.FLASH_OB_WaitForLastOperation,"ax",%progbits + 1076 .align 1 + 1077 .global FLASH_OB_WaitForLastOperation + 1078 .syntax unified + 1079 .thumb + 1080 .thumb_func + 1081 .fpu fpv5-d16 + 1083 FLASH_OB_WaitForLastOperation: + 1084 .LVL65: + 1085 .LFB153: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Wait for a FLASH Option Bytes change operation to complete. +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param Timeout maximum flash operation timeout +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout) +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1086 .loc 1 1062 1 is_stmt 1 view -0 + 1087 .cfi_startproc + 1088 @ args = 0, pretend = 0, frame = 0 + 1089 @ frame_needed = 0, uses_anonymous_args = 0 + 1090 .loc 1 1062 1 is_stmt 0 view .LVU302 + 1091 0000 38B5 push {r3, r4, r5, lr} + 1092 .LCFI5: + 1093 .cfi_def_cfa_offset 16 + 1094 .cfi_offset 3, -16 + 1095 .cfi_offset 4, -12 + 1096 .cfi_offset 5, -8 + 1097 .cfi_offset 14, -4 + 1098 0002 0446 mov r4, r0 +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Get timeout */ +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t tickstart = HAL_GetTick(); + 1099 .loc 1 1064 3 is_stmt 1 view .LVU303 + 1100 .loc 1 1064 24 is_stmt 0 view .LVU304 + 1101 0004 FFF7FEFF bl HAL_GetTick + 1102 .LVL66: + 1103 .loc 1 1064 24 view .LVU305 + 1104 0008 0546 mov r5, r0 + 1105 .LVL67: +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U) + 1106 .loc 1 1067 3 is_stmt 1 view .LVU306 + 1107 .L87: + ARM GAS /tmp/ccCw6Rev.s page 58 + + + 1108 .loc 1 1067 8 view .LVU307 + 1109 .loc 1 1067 9 is_stmt 0 view .LVU308 + 1110 000a 134B ldr r3, .L96 + 1111 000c DB69 ldr r3, [r3, #28] + 1112 .loc 1 1067 8 view .LVU309 + 1113 000e 13F0010F tst r3, #1 + 1114 0012 0BD0 beq .L94 +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(Timeout != HAL_MAX_DELAY) + 1115 .loc 1 1069 5 is_stmt 1 view .LVU310 + 1116 .loc 1 1069 7 is_stmt 0 view .LVU311 + 1117 0014 B4F1FF3F cmp r4, #-1 + 1118 0018 F7D0 beq .L87 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 1119 .loc 1 1071 7 is_stmt 1 view .LVU312 + 1120 .loc 1 1071 12 is_stmt 0 view .LVU313 + 1121 001a FFF7FEFF bl HAL_GetTick + 1122 .LVL68: + 1123 .loc 1 1071 26 view .LVU314 + 1124 001e 401B subs r0, r0, r5 + 1125 .loc 1 1071 9 view .LVU315 + 1126 0020 A042 cmp r0, r4 + 1127 0022 16D8 bhi .L90 + 1128 .loc 1 1071 50 discriminator 1 view .LVU316 + 1129 0024 002C cmp r4, #0 + 1130 0026 F0D1 bne .L87 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_TIMEOUT; + 1131 .loc 1 1073 16 view .LVU317 + 1132 0028 0320 movs r0, #3 + 1133 002a 05E0 b .L88 + 1134 .L94: +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check option byte change error */ +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U) + 1135 .loc 1 1079 3 is_stmt 1 view .LVU318 + 1136 .loc 1 1079 6 is_stmt 0 view .LVU319 + 1137 002c 0A4B ldr r3, .L96 + 1138 002e DB69 ldr r3, [r3, #28] + 1139 .loc 1 1079 5 view .LVU320 + 1140 0030 13F0804F tst r3, #1073741824 + 1141 0034 01D1 bne .L95 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Save the error code */ +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE; +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear the OB error flag */ +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR; +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If there is no error flag set */ + ARM GAS /tmp/ccCw6Rev.s page 59 + + +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 1142 .loc 1 1091 10 view .LVU321 + 1143 0036 0020 movs r0, #0 + 1144 .L88: +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1145 .loc 1 1092 1 view .LVU322 + 1146 0038 38BD pop {r3, r4, r5, pc} + 1147 .LVL69: + 1148 .L95: +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1149 .loc 1 1082 5 is_stmt 1 view .LVU323 +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1150 .loc 1 1082 22 is_stmt 0 view .LVU324 + 1151 003a 084A ldr r2, .L96+4 + 1152 003c 9369 ldr r3, [r2, #24] + 1153 003e 43F08043 orr r3, r3, #1073741824 + 1154 0042 9361 str r3, [r2, #24] +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1155 .loc 1 1085 5 is_stmt 1 view .LVU325 +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1156 .loc 1 1085 19 is_stmt 0 view .LVU326 + 1157 0044 044A ldr r2, .L96 + 1158 0046 536A ldr r3, [r2, #36] + 1159 0048 43F08043 orr r3, r3, #1073741824 + 1160 004c 5362 str r3, [r2, #36] +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1161 .loc 1 1087 5 is_stmt 1 view .LVU327 +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1162 .loc 1 1087 12 is_stmt 0 view .LVU328 + 1163 004e 0120 movs r0, #1 + 1164 0050 F2E7 b .L88 + 1165 .L90: +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1166 .loc 1 1073 16 view .LVU329 + 1167 0052 0320 movs r0, #3 + 1168 0054 F0E7 b .L88 + 1169 .L97: + 1170 0056 00BF .align 2 + 1171 .L96: + 1172 0058 00200052 .word 1375739904 + 1173 005c 00000000 .word .LANCHOR0 + 1174 .cfi_endproc + 1175 .LFE153: + 1177 .section .text.FLASH_CRC_WaitForLastOperation,"ax",%progbits + 1178 .align 1 + 1179 .global FLASH_CRC_WaitForLastOperation + 1180 .syntax unified + 1181 .thumb + 1182 .thumb_func + 1183 .fpu fpv5-d16 + 1185 FLASH_CRC_WaitForLastOperation: + 1186 .LVL70: + 1187 .LFB154: +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /** +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @brief Wait for a FLASH CRC computation to complete. +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param Timeout maximum flash operation timeout + ARM GAS /tmp/ccCw6Rev.s page 60 + + +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** */ +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1188 .loc 1 1101 1 is_stmt 1 view -0 + 1189 .cfi_startproc + 1190 @ args = 0, pretend = 0, frame = 0 + 1191 @ frame_needed = 0, uses_anonymous_args = 0 + 1192 .loc 1 1101 1 is_stmt 0 view .LVU331 + 1193 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1194 .LCFI6: + 1195 .cfi_def_cfa_offset 24 + 1196 .cfi_offset 3, -24 + 1197 .cfi_offset 4, -20 + 1198 .cfi_offset 5, -16 + 1199 .cfi_offset 6, -12 + 1200 .cfi_offset 7, -8 + 1201 .cfi_offset 14, -4 + 1202 0002 0446 mov r4, r0 + 1203 0004 0E46 mov r6, r1 +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t bsyflag; + 1204 .loc 1 1102 3 is_stmt 1 view .LVU332 +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** uint32_t tickstart = HAL_GetTick(); + 1205 .loc 1 1103 3 view .LVU333 + 1206 .loc 1 1103 24 is_stmt 0 view .LVU334 + 1207 0006 FFF7FEFF bl HAL_GetTick + 1208 .LVL71: + 1209 .loc 1 1103 24 view .LVU335 + 1210 000a 0746 mov r7, r0 + 1211 .LVL72: +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + 1212 .loc 1 1105 3 is_stmt 1 view .LVU336 +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Select bsyflag depending on Bank */ +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(Bank == FLASH_BANK_1) + 1213 .loc 1 1108 3 view .LVU337 + 1214 .loc 1 1108 5 is_stmt 0 view .LVU338 + 1215 000c 012E cmp r6, #1 + 1216 000e 11D0 beq .L99 +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bsyflag = FLASH_FLAG_CRC_BUSY_BANK1; +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** bsyflag = FLASH_FLAG_CRC_BUSY_BANK2; + 1217 .loc 1 1114 13 view .LVU339 + 1218 0010 154D ldr r5, .L113 + 1219 .LVL73: + 1220 .L101: +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */ +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** while(__HAL_FLASH_GET_FLAG(bsyflag)) + 1221 .loc 1 1118 8 is_stmt 1 view .LVU340 + 1222 .loc 1 1118 9 is_stmt 0 view .LVU341 + ARM GAS /tmp/ccCw6Rev.s page 61 + + + 1223 0012 164B ldr r3, .L113+4 + 1224 0014 1B69 ldr r3, [r3, #16] + 1225 .loc 1 1118 8 view .LVU342 + 1226 0016 35EA0303 bics r3, r5, r3 + 1227 001a 0DD1 bne .L110 +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(Timeout != HAL_MAX_DELAY) + 1228 .loc 1 1120 5 is_stmt 1 view .LVU343 + 1229 .loc 1 1120 7 is_stmt 0 view .LVU344 + 1230 001c B4F1FF3F cmp r4, #-1 + 1231 0020 F7D0 beq .L101 +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 1232 .loc 1 1122 7 is_stmt 1 view .LVU345 + 1233 .loc 1 1122 12 is_stmt 0 view .LVU346 + 1234 0022 FFF7FEFF bl HAL_GetTick + 1235 .LVL74: + 1236 .loc 1 1122 26 view .LVU347 + 1237 0026 C01B subs r0, r0, r7 + 1238 .loc 1 1122 9 view .LVU348 + 1239 0028 A042 cmp r0, r4 + 1240 002a 1BD8 bhi .L105 + 1241 .loc 1 1122 50 discriminator 1 view .LVU349 + 1242 002c 002C cmp r4, #0 + 1243 002e F0D1 bne .L101 +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_TIMEOUT; + 1244 .loc 1 1124 16 view .LVU350 + 1245 0030 0320 movs r0, #3 + 1246 0032 04E0 b .L102 + 1247 .LVL75: + 1248 .L99: +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1249 .loc 1 1110 13 view .LVU351 + 1250 0034 0825 movs r5, #8 + 1251 0036 ECE7 b .L101 + 1252 .LVL76: + 1253 .L110: +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Check FLASH CRC read error flag */ +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if(Bank == FLASH_BANK_1) + 1254 .loc 1 1130 3 is_stmt 1 view .LVU352 + 1255 .loc 1 1130 5 is_stmt 0 view .LVU353 + 1256 0038 012E cmp r6, #1 + 1257 003a 01D0 beq .L111 +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1)) +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Save the error code */ +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1; +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH CRC read error pending bit */ +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1); +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + ARM GAS /tmp/ccCw6Rev.s page 62 + + +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #if defined (DUAL_BANK) +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** else +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2)) +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Save the error code */ +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2; +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* Clear FLASH CRC read error pending bit */ +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2); +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_ERROR; +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** #endif /* DUAL_BANK */ +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** /* If there is no error flag set */ +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** return HAL_OK; + 1258 .loc 1 1160 10 view .LVU354 + 1259 003c 0020 movs r0, #0 + 1260 .L102: +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1261 .loc 1 1161 1 view .LVU355 + 1262 003e F8BD pop {r3, r4, r5, r6, r7, pc} + 1263 .LVL77: + 1264 .L111: +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1265 .loc 1 1132 5 is_stmt 1 view .LVU356 +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1266 .loc 1 1132 9 is_stmt 0 view .LVU357 + 1267 0040 0A4B ldr r3, .L113+4 + 1268 0042 1B69 ldr r3, [r3, #16] +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1269 .loc 1 1132 8 view .LVU358 + 1270 0044 13F0805F tst r3, #268435456 + 1271 0048 01D1 bne .L112 +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1272 .loc 1 1160 10 view .LVU359 + 1273 004a 0020 movs r0, #0 + 1274 004c F7E7 b .L102 + 1275 .L112: +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1276 .loc 1 1135 7 is_stmt 1 view .LVU360 +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1277 .loc 1 1135 24 is_stmt 0 view .LVU361 + 1278 004e 084A ldr r2, .L113+8 + 1279 0050 9369 ldr r3, [r2, #24] + 1280 0052 43F08053 orr r3, r3, #268435456 + 1281 0056 9361 str r3, [r2, #24] +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1282 .loc 1 1138 7 is_stmt 1 view .LVU362 + 1283 0058 044B ldr r3, .L113+4 + 1284 005a 4FF08052 mov r2, #268435456 + 1285 005e 5A61 str r2, [r3, #20] + ARM GAS /tmp/ccCw6Rev.s page 63 + + +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1286 .loc 1 1140 7 view .LVU363 +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1287 .loc 1 1140 14 is_stmt 0 view .LVU364 + 1288 0060 0120 movs r0, #1 + 1289 0062 ECE7 b .L102 + 1290 .L105: +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1291 .loc 1 1124 16 view .LVU365 + 1292 0064 0320 movs r0, #3 + 1293 0066 EAE7 b .L102 + 1294 .L114: + 1295 .align 2 + 1296 .L113: + 1297 0068 08000080 .word -2147483640 + 1298 006c 00200052 .word 1375739904 + 1299 0070 00000000 .word .LANCHOR0 + 1300 .cfi_endproc + 1301 .LFE154: + 1303 .section .text.HAL_FLASH_OB_Launch,"ax",%progbits + 1304 .align 1 + 1305 .global HAL_FLASH_OB_Launch + 1306 .syntax unified + 1307 .thumb + 1308 .thumb_func + 1309 .fpu fpv5-d16 + 1311 HAL_FLASH_OB_Launch: + 1312 .LFB150: + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** HAL_StatusTypeDef status; + 1313 .loc 1 885 1 is_stmt 1 view -0 + 1314 .cfi_startproc + 1315 @ args = 0, pretend = 0, frame = 0 + 1316 @ frame_needed = 0, uses_anonymous_args = 0 + 1317 0000 08B5 push {r3, lr} + 1318 .LCFI7: + 1319 .cfi_def_cfa_offset 8 + 1320 .cfi_offset 3, -8 + 1321 .cfi_offset 14, -4 + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1322 .loc 1 886 3 view .LVU367 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1323 .loc 1 889 3 view .LVU368 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1324 .loc 1 889 7 is_stmt 0 view .LVU369 + 1325 0002 0121 movs r1, #1 + 1326 0004 4CF25030 movw r0, #50000 + 1327 0008 FFF7FEFF bl FLASH_CRC_WaitForLastOperation + 1328 .LVL78: + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1329 .loc 1 889 6 view .LVU370 + 1330 000c 08B1 cbz r0, .L119 + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1331 .loc 1 891 12 view .LVU371 + 1332 000e 0120 movs r0, #1 + 1333 .L116: + 1334 .LVL79: + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + ARM GAS /tmp/ccCw6Rev.s page 64 + + + 1335 .loc 1 913 3 is_stmt 1 view .LVU372 + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1336 .loc 1 914 1 is_stmt 0 view .LVU373 + 1337 0010 08BD pop {r3, pc} + 1338 .LVL80: + 1339 .L119: + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1340 .loc 1 901 5 is_stmt 1 view .LVU374 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** { + 1341 .loc 1 904 3 view .LVU375 + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** + 1342 .loc 1 907 5 view .LVU376 + 1343 0012 054A ldr r2, .L120 + 1344 0014 9369 ldr r3, [r2, #24] + 1345 0016 43F00203 orr r3, r3, #2 + 1346 001a 9361 str r3, [r2, #24] + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1347 .loc 1 910 5 view .LVU377 + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1348 .loc 1 910 14 is_stmt 0 view .LVU378 + 1349 001c 4CF25030 movw r0, #50000 + 1350 0020 FFF7FEFF bl FLASH_OB_WaitForLastOperation + 1351 .LVL81: + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c **** } + 1352 .loc 1 910 14 view .LVU379 + 1353 0024 F4E7 b .L116 + 1354 .L121: + 1355 0026 00BF .align 2 + 1356 .L120: + 1357 0028 00200052 .word 1375739904 + 1358 .cfi_endproc + 1359 .LFE150: + 1361 .global pFlash + 1362 .section .bss.pFlash,"aw",%nobits + 1363 .align 2 + 1364 .set .LANCHOR0,. + 0 + 1367 pFlash: + 1368 0000 00000000 .space 28 + 1368 00000000 + 1368 00000000 + 1368 00000000 + 1368 00000000 + 1369 .text + 1370 .Letext0: + 1371 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1372 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1373 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1374 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 1375 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1376 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h" + 1377 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 1378 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h" + ARM GAS /tmp/ccCw6Rev.s page 65 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_flash.c + /tmp/ccCw6Rev.s:17 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 $t + /tmp/ccCw6Rev.s:25 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 HAL_FLASH_EndOfOperationCallback + /tmp/ccCw6Rev.s:41 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 $t + /tmp/ccCw6Rev.s:48 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 HAL_FLASH_OperationErrorCallback + /tmp/ccCw6Rev.s:63 .text.HAL_FLASH_IRQHandler:0000000000000000 $t + /tmp/ccCw6Rev.s:70 .text.HAL_FLASH_IRQHandler:0000000000000000 HAL_FLASH_IRQHandler + /tmp/ccCw6Rev.s:309 .text.HAL_FLASH_IRQHandler:00000000000000f8 $d + /tmp/ccCw6Rev.s:315 .text.HAL_FLASH_Unlock:0000000000000000 $t + /tmp/ccCw6Rev.s:322 .text.HAL_FLASH_Unlock:0000000000000000 HAL_FLASH_Unlock + /tmp/ccCw6Rev.s:363 .text.HAL_FLASH_Unlock:000000000000002c $d + /tmp/ccCw6Rev.s:369 .text.HAL_FLASH_Lock:0000000000000000 $t + /tmp/ccCw6Rev.s:376 .text.HAL_FLASH_Lock:0000000000000000 HAL_FLASH_Lock + /tmp/ccCw6Rev.s:405 .text.HAL_FLASH_Lock:000000000000001c $d + /tmp/ccCw6Rev.s:410 .text.HAL_FLASH_OB_Unlock:0000000000000000 $t + /tmp/ccCw6Rev.s:417 .text.HAL_FLASH_OB_Unlock:0000000000000000 HAL_FLASH_OB_Unlock + /tmp/ccCw6Rev.s:458 .text.HAL_FLASH_OB_Unlock:000000000000002c $d + /tmp/ccCw6Rev.s:464 .text.HAL_FLASH_OB_Lock:0000000000000000 $t + /tmp/ccCw6Rev.s:471 .text.HAL_FLASH_OB_Lock:0000000000000000 HAL_FLASH_OB_Lock + /tmp/ccCw6Rev.s:500 .text.HAL_FLASH_OB_Lock:000000000000001c $d + /tmp/ccCw6Rev.s:505 .text.HAL_FLASH_GetError:0000000000000000 $t + /tmp/ccCw6Rev.s:512 .text.HAL_FLASH_GetError:0000000000000000 HAL_FLASH_GetError + /tmp/ccCw6Rev.s:528 .text.HAL_FLASH_GetError:0000000000000008 $d + /tmp/ccCw6Rev.s:533 .text.FLASH_WaitForLastOperation:0000000000000000 $t + /tmp/ccCw6Rev.s:540 .text.FLASH_WaitForLastOperation:0000000000000000 FLASH_WaitForLastOperation + /tmp/ccCw6Rev.s:661 .text.FLASH_WaitForLastOperation:0000000000000078 $d + /tmp/ccCw6Rev.s:667 .text.HAL_FLASH_Program:0000000000000000 $t + /tmp/ccCw6Rev.s:674 .text.HAL_FLASH_Program:0000000000000000 HAL_FLASH_Program + /tmp/ccCw6Rev.s:863 .text.HAL_FLASH_Program:0000000000000080 $d + /tmp/ccCw6Rev.s:869 .text.HAL_FLASH_Program_IT:0000000000000000 $t + /tmp/ccCw6Rev.s:876 .text.HAL_FLASH_Program_IT:0000000000000000 HAL_FLASH_Program_IT + /tmp/ccCw6Rev.s:1070 .text.HAL_FLASH_Program_IT:0000000000000080 $d + /tmp/ccCw6Rev.s:1076 .text.FLASH_OB_WaitForLastOperation:0000000000000000 $t + /tmp/ccCw6Rev.s:1083 .text.FLASH_OB_WaitForLastOperation:0000000000000000 FLASH_OB_WaitForLastOperation + /tmp/ccCw6Rev.s:1172 .text.FLASH_OB_WaitForLastOperation:0000000000000058 $d + /tmp/ccCw6Rev.s:1178 .text.FLASH_CRC_WaitForLastOperation:0000000000000000 $t + /tmp/ccCw6Rev.s:1185 .text.FLASH_CRC_WaitForLastOperation:0000000000000000 FLASH_CRC_WaitForLastOperation + /tmp/ccCw6Rev.s:1297 .text.FLASH_CRC_WaitForLastOperation:0000000000000068 $d + /tmp/ccCw6Rev.s:1304 .text.HAL_FLASH_OB_Launch:0000000000000000 $t + /tmp/ccCw6Rev.s:1311 .text.HAL_FLASH_OB_Launch:0000000000000000 HAL_FLASH_OB_Launch + /tmp/ccCw6Rev.s:1357 .text.HAL_FLASH_OB_Launch:0000000000000028 $d + /tmp/ccCw6Rev.s:1367 .bss.pFlash:0000000000000000 pFlash + /tmp/ccCw6Rev.s:1363 .bss.pFlash:0000000000000000 $d + +UNDEFINED SYMBOLS +FLASH_Erase_Sector +HAL_GetTick diff --git a/build/stm32h7xx_hal_flash.o b/build/stm32h7xx_hal_flash.o new file mode 100644 index 0000000..4270dac Binary files /dev/null and b/build/stm32h7xx_hal_flash.o differ diff --git a/build/stm32h7xx_hal_flash_ex.d b/build/stm32h7xx_hal_flash_ex.d new file mode 100644 index 0000000..fc7c49c --- /dev/null +++ b/build/stm32h7xx_hal_flash_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_flash_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_flash_ex.lst b/build/stm32h7xx_hal_flash_ex.lst new file mode 100644 index 0000000..40ead71 --- /dev/null +++ b/build/stm32h7xx_hal_flash_ex.lst @@ -0,0 +1,4374 @@ +ARM GAS /tmp/ccM28uwG.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_flash_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.FLASH_MassErase,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 FLASH_MassErase: + 25 .LVL0: + 26 .LFB148: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @file stm32h7xx_hal_flash_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Extended FLASH HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * functionalities of the FLASH extension peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + Extended programming operations functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** @verbatim + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ============================================================================== + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ##### Flash Extension features ##### + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** [..] Comparing to other previous devices, the FLASH interface for STM32H7xx + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** devices contains the following additional features + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** capability (RWW) + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Dual bank memory organization + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) PCROP protection for all banks + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Global readout protection (RDP) + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Write protection + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Secure access only protection + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Bank / register swapping + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+) Cyclic Redundancy Check (CRC) + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ##### How to use this driver ##### + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ============================================================================== + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** [..] This driver provides functions to configure and program the FLASH memory + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** of all STM32H7xx devices. It includes + ARM GAS /tmp/ccM28uwG.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (#) FLASH Memory Erase functions: + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_FLASH_Lock() functions + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Erase function: Sector erase, bank erase and dual-bank mass erase + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) There are two modes of erase : + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+++) Polling Mode using HAL_FLASHEx_Erase() + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to: + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Set/Reset the write protection per bank + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Set the Read protection Level + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Set the BOR level + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Program the user Option Bytes + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) PCROP protection configuration and control per bank + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Secure area configuration and control per bank + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Core Boot address configuration + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) TCM / AXI shared RAM configuration + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) CPU Frequency Boost configuration + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1 + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to: + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Enable CRC feature + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Program the desired burst size + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Define the user Flash Area on which the CRC has be computed + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Perform the CRC computation + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (++) Disable CRC feature + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** @endverbatim + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ****************************************************************************** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @attention + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * All rights reserved.

+ 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * the "License"; You may not use this file except in compliance with the + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * License. You may obtain a copy of the License at: + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * opensource.org/licenses/BSD-3-Clause + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ****************************************************************************** + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/ + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #include "stm32h7xx_hal.h" + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief FLASH HAL Extension module driver + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED + ARM GAS /tmp/ccM28uwG.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/ + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Constants + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @} + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/ + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/ + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks); + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank); + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank); + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_RDPConfig(uint32_t RDPLevel); + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void); + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEnd + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAdd + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_BOR_LevelConfig(uint32_t Level); + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBOR(void); + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void); + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint3 + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank); + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank); + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_CORE) + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddr + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OTPBL_LOCKBL) + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_OTP_GetLock(void); + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OTPBL_LOCKBL */ + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig); + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_SharedRAM_GetConfig(void); + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost); + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_CPUFreq_GetBoost(void); + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @} + ARM GAS /tmp/ccM28uwG.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Extended IO operation functions + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** @verbatim + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** =============================================================================== + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** ##### Extended programming operation functions ##### + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** =============================================================================== + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** [..] + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** This subsection provides a set of functions allowing to manage the Extension FLASH + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** programming operations Operations. + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** @endverbatim + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory sectors + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param[out] SectorError pointer to variable that contains the configuration + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * information on faulty sector in case of error (0xFFFFFFFF means that all + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * the sectors have been correctly erased) + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t sector_index; + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Process Locked */ + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset error code */ + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed on Bank1 */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + ARM GAS /tmp/ccM28uwG.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed on Bank2 */ + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(status == HAL_OK) + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Mass erase to be done */ + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed on Bank 1 */ + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* if the erase operation is completed, disable the Bank1 BER Bit */ + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= (~FLASH_CR_BER); + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed on Bank 2 */ + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* if the erase operation is completed, disable the Bank2 BER Bit */ + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= (~FLASH_CR_BER); + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Initialization of SectorError variable*/ + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** *SectorError = 0xFFFFFFFFU; + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Erase by sector by sector to be done*/ + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Se + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange); + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the SER Bit */ + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + ARM GAS /tmp/ccM28uwG.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the SER Bit */ + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(status != HAL_OK) + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* In case of error, stop erase procedure and return the faulty sector */ + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** *SectorError = sector_index; + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** break; + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Process Unlocked */ + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return status; + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Process Locked */ + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset error code */ + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed on Bank 1 */ + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccM28uwG.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed on Bank 2 */ + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (status != HAL_OK) + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Process Unlocked */ + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable End of Operation and Error interrupts for Bank 1 */ + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_OPERRIE) + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_ + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_B + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_OPERRIE */ + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable End of Operation and Error interrupts for Bank 2 */ + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_OPERRIE) + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_ + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_B + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_ + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_OPERRIE */ + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(pEraseInit->Banks == FLASH_BANK_1) + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1; + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else if(pEraseInit->Banks == FLASH_BANK_2) + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2; + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + ARM GAS /tmp/ccM28uwG.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE; + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Erase by sector to be done */ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(pEraseInit->Banks == FLASH_BANK_1) + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2; + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.NbSectorsToErase = pEraseInit->NbSectors; + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.VoltageForErase = pEraseInit->VoltageRange; + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Erase first sector and wait for IT */ + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange); + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return status; + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Program option bytes + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Process Locked */ + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset Error Code */ + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + ARM GAS /tmp/ccM28uwG.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_ERROR; + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = HAL_OK; + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(status == HAL_OK) + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Write protection configuration*/ + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_WRPSTATE(pOBInit->WRPState)); + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Enable of Write protection on the selected Sector*/ + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks); + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Disable of Write protection on the selected Sector*/ + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Read protection configuration */ + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the Read protection level */ + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_RDPConfig(pOBInit->RDPLevel); + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* User Configuration */ + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the user option bytes */ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* PCROP Configuration */ + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(pOBInit->Banks)); + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Configure the Proprietary code readout protection */ + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pO + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* BOR Level configuration */ + ARM GAS /tmp/ccM28uwG.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* CM7 Boot Address configuration */ + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD) + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* CM4 Boot Address configuration */ + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD) + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else /* Single Core*/ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Boot Address configuration */ + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD) + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Secure area configuration */ + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA) + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->S + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(FLASH_OTPBL_LOCKBL) + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* OTP Block Lock configuration */ + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK) + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OTPBL_LOCKBL */ + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(FLASH_OPTSR2_TCM_AXI_SHARED) + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* TCM / AXI Shared RAM configuration */ + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM) + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig); + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(FLASH_OPTSR2_CPUFREQ_BOOST) + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* CPU Frequency Boost configuration */ + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST) + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState); + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Process Unlocked */ + ARM GAS /tmp/ccM28uwG.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return status; + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get the Option byte configuration + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * as this parameter is use to get the given Bank WRP, PCROP and secured area configuratio + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR); + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get Read protection level */ + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->RDPLevel = FLASH_OB_GetRDP(); + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get the user option bytes */ + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->USERConfig = FLASH_OB_GetUser(); + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Get BOR Level*/ + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->BORLevel = FLASH_OB_GetBOR(); + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (pOBInit->Banks == FLASH_BANK_1) + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA); + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get write protection on the selected area */ + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks); + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get the Proprietary code readout protection */ + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr) + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Get Bank Secure area*/ + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Get Boot Address*/ + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1)); + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD; + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /*Get CM4 Boot Address*/ + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1)); + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType |= OPTIONBYTE_BOOTADD; + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OTPBL_LOCKBL) + ARM GAS /tmp/ccM28uwG.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK; + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get OTP Block Lock */ + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OTPBL_LOCKBL */ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM; + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get TCM / AXI Shared RAM */ + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig(); + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST; + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get CPU Frequency Boost */ + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost(); + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Unlock the FLASH Bank1 control registers access + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void) + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Authorize the FLASH Bank1 Registers access */ + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Verify Flash Bank1 is unlocked */ + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_ERROR; + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_OK; + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Locks the FLASH Bank1 control registers access + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void) + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */ + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_OK; + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Unlock the FLASH Bank2 control registers access + ARM GAS /tmp/ccM28uwG.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void) + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Authorize the FLASH Bank2 Registers access */ + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Verify Flash Bank1 is unlocked */ + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_ERROR; + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_OK; + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Locks the FLASH Bank2 control registers access + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void) + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */ + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_OK; + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Perform a CRC computation on the specified FLASH memory area + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param pCRCInit pointer to an FLASH_CRCInitTypeDef structure that + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * contains the configuration information for the CRC computation. + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7 + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note The application should avoid running a CRC on PCROP or secure-only + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * user Flash memory area since it may alter the expected CRC value. + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * A special error flag (CRC read error: CRCRDERR) can be used to + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * detect such a case. + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t sector_index; + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank)); + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC)); + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait for OB change operation to be completed */ + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (status == HAL_OK) + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccM28uwG.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (pCRCInit->Bank == FLASH_BANK_1) + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable CRC feature */ + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 |= FLASH_CR_CRC_EN; + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear current CRC result, program burst size and define memory area on which CRC has to be + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear sectors list */ + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT; + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Select CRC sectors */ + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_CRC_AddSector(sector_index, FLASH_BANK_1); + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable Bank 1 CRC select bit */ + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK; + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Select CRC start and end addresses */ + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1); + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Start the CRC calculation */ + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC; + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait on CRC busy flag */ + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Return CRC result */ + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*CRC_Result) = FLASH->CRCDATA; + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Disable CRC feature */ + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= (~FLASH_CR_CRC_EN); + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear CRC flags */ + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1); + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable CRC feature */ + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 |= FLASH_CR_CRC_EN; + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + ARM GAS /tmp/ccM28uwG.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear current CRC result, program burst size and define memory area on which CRC has to be + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear sectors list */ + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT; + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Add CRC sectors */ + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_CRC_AddSector(sector_index, FLASH_BANK_2); + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable Bank 2 CRC select bit */ + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK; + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Select CRC start and end addresses */ + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2); + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Start the CRC calculation */ + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC; + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Wait on CRC busy flag */ + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Return CRC result */ + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*CRC_Result) = FLASH->CRCDATA; + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Disable CRC feature */ + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= (~FLASH_CR_CRC_EN); + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear CRC flags */ + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2); + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return status; + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @} + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @} + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Private functions ---------------------------------------------------------*/ + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions + ARM GAS /tmp/ccM28uwG.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @{ + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Mass erase of FLASH memory + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param VoltageRange The device program/erase parallelism. + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Banks Banks to be erased + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Bank1 to be erased + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Bank2 to be erased + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 28 .loc 1 851 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + 33 .loc 1 854 3 view .LVU1 + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** UNUSED(VoltageRange); + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 34 .loc 1 858 3 view .LVU2 + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Flash Mass Erase */ + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset Program/erase VoltageRange for Bank1 and Bank2 */ + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= (~FLASH_CR_PSIZE); + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= (~FLASH_CR_PSIZE); + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set voltage range */ + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 |= VoltageRange; + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 |= VoltageRange; + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set Mass Erase Bit */ + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->OPTCR |= FLASH_OPTCR_MER; + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccM28uwG.s page 17 + + + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Proceed to erase Flash Bank */ + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + 35 .loc 1 881 5 view .LVU3 + 36 .loc 1 881 7 is_stmt 0 view .LVU4 + 37 0000 11F0010F tst r1, #1 + 38 0004 0BD0 beq .L1 + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set Program/erase VoltageRange for Bank1 */ + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= (~FLASH_CR_PSIZE); + 39 .loc 1 885 7 is_stmt 1 view .LVU5 + 40 .loc 1 885 18 is_stmt 0 view .LVU6 + 41 0006 064B ldr r3, .L3 + 42 0008 DA68 ldr r2, [r3, #12] + 43 000a 22F03002 bic r2, r2, #48 + 44 000e DA60 str r2, [r3, #12] + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 |= VoltageRange; + 45 .loc 1 886 7 is_stmt 1 view .LVU7 + 46 .loc 1 886 18 is_stmt 0 view .LVU8 + 47 0010 DA68 ldr r2, [r3, #12] + 48 0012 1043 orrs r0, r0, r2 + 49 .LVL1: + 50 .loc 1 886 18 view .LVU9 + 51 0014 D860 str r0, [r3, #12] + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Erase Bank1 */ + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); + 52 .loc 1 890 7 is_stmt 1 view .LVU10 + 53 .loc 1 890 18 is_stmt 0 view .LVU11 + 54 0016 DA68 ldr r2, [r3, #12] + 55 0018 42F08802 orr r2, r2, #136 + 56 001c DA60 str r2, [r3, #12] + 57 .L1: + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set Program/erase VoltageRange for Bank2 */ + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= (~FLASH_CR_PSIZE); + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 |= VoltageRange; + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Erase Bank2 */ + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 58 .loc 1 907 1 view .LVU12 + 59 001e 7047 bx lr + 60 .L4: + 61 .align 2 + 62 .L3: + 63 0020 00200052 .word 1375739904 + ARM GAS /tmp/ccM28uwG.s page 18 + + + 64 .cfi_endproc + 65 .LFE148: + 67 .section .text.FLASH_OB_EnableWRP,"ax",%progbits + 68 .align 1 + 69 .syntax unified + 70 .thumb + 71 .thumb_func + 72 .fpu fpv5-d16 + 74 FLASH_OB_EnableWRP: + 75 .LVL2: + 76 .LFB150: + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory sector + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Sector FLASH sector to erase + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be a value of @ref FLASH_Sectors + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Banks Banks to be erased + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Bank1 to be erased + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Bank2 to be erased + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param VoltageRange The device program/erase parallelism. + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_SECTOR(Sector)); + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** UNUSED(VoltageRange); + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset Program/erase VoltageRange and Sector Number for Bank1 */ + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset Sector Number for Bank1 */ + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 &= ~(FLASH_CR_SNB); + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + ARM GAS /tmp/ccM28uwG.s page 19 + + + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset Program/erase VoltageRange and Sector Number for Bank2 */ + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Reset Sector Number for Bank2 */ + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 &= ~(FLASH_CR_SNB); + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_CR_PSIZE */ + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Enable the write protection of the desired bank1 or bank 2 sectors + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param WRPSector specifies the sector(s) to be write protected. + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTO + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Banks the specific bank to apply WRP sectors + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL FLASH State + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 77 .loc 1 985 1 is_stmt 1 view -0 + 78 .cfi_startproc + 79 @ args = 0, pretend = 0, frame = 0 + 80 @ frame_needed = 0, uses_anonymous_args = 0 + 81 @ link register save eliminated. + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_WRP_SECTOR(WRPSector)); + 82 .loc 1 987 3 view .LVU14 + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 83 .loc 1 988 3 view .LVU15 + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + 84 .loc 1 990 3 view .LVU16 + 85 .loc 1 990 5 is_stmt 0 view .LVU17 + 86 0000 11F0010F tst r1, #1 + 87 0004 05D0 beq .L5 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable Write Protection for bank 1 */ + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + 88 .loc 1 993 5 is_stmt 1 view .LVU18 + 89 .loc 1 993 22 is_stmt 0 view .LVU19 + 90 0006 034A ldr r2, .L7 + 91 0008 D36B ldr r3, [r2, #60] + 92 .loc 1 993 38 view .LVU20 + 93 000a C0B2 uxtb r0, r0 + ARM GAS /tmp/ccM28uwG.s page 20 + + + 94 .LVL3: + 95 .loc 1 993 22 view .LVU21 + 96 000c 23EA0000 bic r0, r3, r0 + 97 0010 D063 str r0, [r2, #60] + 98 .L5: + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Enable Write Protection for bank 2 */ +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN)); +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 99 .loc 1 1003 1 view .LVU22 + 100 0012 7047 bx lr + 101 .L8: + 102 .align 2 + 103 .L7: + 104 0014 00200052 .word 1375739904 + 105 .cfi_endproc + 106 .LFE150: + 108 .section .text.FLASH_OB_DisableWRP,"ax",%progbits + 109 .align 1 + 110 .syntax unified + 111 .thumb + 112 .thumb_func + 113 .fpu fpv5-d16 + 115 FLASH_OB_DisableWRP: + 116 .LVL4: + 117 .LFB151: +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Disable the write protection of the desired bank1 or bank 2 sectors +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param WRPSector specifies the sector(s) to disable write protection. +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Banks the specific bank to apply WRP sectors +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL FLASH State +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 118 .loc 1 1020 1 is_stmt 1 view -0 + 119 .cfi_startproc + 120 @ args = 0, pretend = 0, frame = 0 + 121 @ frame_needed = 0, uses_anonymous_args = 0 + 122 @ link register save eliminated. +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_WRP_SECTOR(WRPSector)); + 123 .loc 1 1022 3 view .LVU24 + ARM GAS /tmp/ccM28uwG.s page 21 + + +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 124 .loc 1 1023 3 view .LVU25 +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + 125 .loc 1 1025 3 view .LVU26 + 126 .loc 1 1025 5 is_stmt 0 view .LVU27 + 127 0000 11F0010F tst r1, #1 + 128 0004 04D0 beq .L9 +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Disable Write Protection for bank 1 */ +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN); + 129 .loc 1 1028 5 is_stmt 1 view .LVU28 + 130 .loc 1 1028 22 is_stmt 0 view .LVU29 + 131 0006 034A ldr r2, .L11 + 132 0008 D36B ldr r3, [r2, #60] + 133 .loc 1 1028 36 view .LVU30 + 134 000a C0B2 uxtb r0, r0 + 135 .LVL5: + 136 .loc 1 1028 22 view .LVU31 + 137 000c 1843 orrs r0, r0, r3 + 138 000e D063 str r0, [r2, #60] + 139 .L9: +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_2) == FLASH_BANK_2) +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Disable Write Protection for bank 2 */ +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN); +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 140 .loc 1 1038 1 view .LVU32 + 141 0010 7047 bx lr + 142 .L12: + 143 0012 00BF .align 2 + 144 .L11: + 145 0014 00200052 .word 1375739904 + 146 .cfi_endproc + 147 .LFE151: + 149 .section .text.FLASH_OB_GetWRP,"ax",%progbits + 150 .align 1 + 151 .syntax unified + 152 .thumb + 153 .thumb_func + 154 .fpu fpv5-d16 + 156 FLASH_OB_GetWRP: + 157 .LVL6: + 158 .LFB152: +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get the write protection of the given bank 1 or bank 2 sectors +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param WRPState gives the write protection state on the given bank. +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param WRPSector gives the write protected sector(s) on the given bank . + ARM GAS /tmp/ccM28uwG.s page 22 + + +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLA +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Bank the specific bank to apply WRP sectors +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be exclusively one of the following values: +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Get bank1 WRP sectors +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Get bank2 WRP sectors +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: note allowed in this functions +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL FLASH State +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank) +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 159 .loc 1 1059 1 is_stmt 1 view -0 + 160 .cfi_startproc + 161 @ args = 0, pretend = 0, frame = 0 + 162 @ frame_needed = 0, uses_anonymous_args = 0 + 163 @ link register save eliminated. +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t regvalue = 0U; + 164 .loc 1 1060 3 view .LVU34 +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(Bank == FLASH_BANK_1) + 165 .loc 1 1062 3 view .LVU35 + 166 .loc 1 1062 5 is_stmt 0 view .LVU36 + 167 0000 012A cmp r2, #1 + 168 0002 06D0 beq .L18 +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t regvalue = 0U; + 169 .loc 1 1060 12 view .LVU37 + 170 0004 0023 movs r3, #0 + 171 .LVL7: + 172 .L14: +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->WPSN_CUR1; +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(Bank == FLASH_BANK_2) +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->WPSN_CUR2; +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN; + 173 .loc 1 1074 3 is_stmt 1 view .LVU38 + 174 .loc 1 1074 19 is_stmt 0 view .LVU39 + 175 0006 DB43 mvns r3, r3 + 176 .LVL8: + 177 .loc 1 1074 30 view .LVU40 + 178 0008 DBB2 uxtb r3, r3 + 179 .LVL9: + 180 .loc 1 1074 16 view .LVU41 + 181 000a 0B60 str r3, [r1] +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(*WRPSector == 0U) + 182 .loc 1 1076 3 is_stmt 1 view .LVU42 + 183 .loc 1 1076 5 is_stmt 0 view .LVU43 + 184 000c 23B9 cbnz r3, .L15 + ARM GAS /tmp/ccM28uwG.s page 23 + + +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*WRPState) = OB_WRPSTATE_DISABLE; + 185 .loc 1 1078 5 is_stmt 1 view .LVU44 + 186 .loc 1 1078 17 is_stmt 0 view .LVU45 + 187 000e 0360 str r3, [r0] + 188 0010 7047 bx lr + 189 .LVL10: + 190 .L18: +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 191 .loc 1 1064 5 is_stmt 1 view .LVU46 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 192 .loc 1 1064 14 is_stmt 0 view .LVU47 + 193 0012 034B ldr r3, .L19 + 194 0014 9B6B ldr r3, [r3, #56] + 195 .LVL11: +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 196 .loc 1 1064 14 view .LVU48 + 197 0016 F6E7 b .L14 + 198 .LVL12: + 199 .L15: +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*WRPState) = OB_WRPSTATE_ENABLE; + 200 .loc 1 1082 5 is_stmt 1 view .LVU49 + 201 .loc 1 1082 17 is_stmt 0 view .LVU50 + 202 0018 0123 movs r3, #1 + 203 001a 0360 str r3, [r0] +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 204 .loc 1 1084 1 view .LVU51 + 205 001c 7047 bx lr + 206 .L20: + 207 001e 00BF .align 2 + 208 .L19: + 209 0020 00200052 .word 1375739904 + 210 .cfi_endproc + 211 .LFE152: + 213 .section .text.FLASH_OB_RDPConfig,"ax",%progbits + 214 .align 1 + 215 .syntax unified + 216 .thumb + 217 .thumb_func + 218 .fpu fpv5-d16 + 220 FLASH_OB_RDPConfig: + 221 .LVL13: + 222 .LFB153: +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Set the read protection level. +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To configure the RDP level, the option lock bit OPTLOCK must be +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * cleared with the call of the HAL_FLASH_OB_Unlock() function. +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To validate the RDP level, the option bytes must be reloaded +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * through the call of the HAL_FLASH_OB_Launch() function. +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * to go back to level 1 or 0 !!! + ARM GAS /tmp/ccM28uwG.s page 24 + + +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param RDPLevel specifies the read protection level. +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_0: No protection +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_1: Read protection of the memory +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_2: Full chip protection +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL status +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_RDPConfig(uint32_t RDPLevel) +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 223 .loc 1 1105 1 is_stmt 1 view -0 + 224 .cfi_startproc + 225 @ args = 0, pretend = 0, frame = 0 + 226 @ frame_needed = 0, uses_anonymous_args = 0 + 227 @ link register save eliminated. +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + 228 .loc 1 1107 3 view .LVU53 +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the RDP level in the option bytes register */ +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel); + 229 .loc 1 1110 3 view .LVU54 + 230 0000 034A ldr r2, .L22 + 231 0002 136A ldr r3, [r2, #32] + 232 0004 23F47F43 bic r3, r3, #65280 + 233 0008 0343 orrs r3, r3, r0 + 234 000a 1362 str r3, [r2, #32] +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 235 .loc 1 1111 1 is_stmt 0 view .LVU55 + 236 000c 7047 bx lr + 237 .L23: + 238 000e 00BF .align 2 + 239 .L22: + 240 0010 00200052 .word 1375739904 + 241 .cfi_endproc + 242 .LFE153: + 244 .section .text.FLASH_OB_GetRDP,"ax",%progbits + 245 .align 1 + 246 .syntax unified + 247 .thumb + 248 .thumb_func + 249 .fpu fpv5-d16 + 251 FLASH_OB_GetRDP: + 252 .LFB154: +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get the read protection level. +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval RDPLevel specifies the read protection level. +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This return value can be one of the following values: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_0: No protection +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_1: Read protection of the memory +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_2: Full chip protection +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void) +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 253 .loc 1 1122 1 is_stmt 1 view -0 + ARM GAS /tmp/ccM28uwG.s page 25 + + + 254 .cfi_startproc + 255 @ args = 0, pretend = 0, frame = 0 + 256 @ frame_needed = 0, uses_anonymous_args = 0 + 257 @ link register save eliminated. +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP); + 258 .loc 1 1123 3 view .LVU57 + 259 .loc 1 1123 24 is_stmt 0 view .LVU58 + 260 0000 064B ldr r3, .L27 + 261 0002 D869 ldr r0, [r3, #28] + 262 .loc 1 1123 12 view .LVU59 + 263 0004 00F47F40 and r0, r0, #65280 + 264 .LVL14: +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) + 265 .loc 1 1125 3 is_stmt 1 view .LVU60 + 266 .loc 1 1125 6 is_stmt 0 view .LVU61 + 267 0008 B0F52A4F cmp r0, #43520 + 268 000c 18BF it ne + 269 000e B0F54C4F cmpne r0, #52224 + 270 0012 00D1 bne .L26 + 271 .LVL15: + 272 .L24: +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return (OB_RDP_LEVEL_1); +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return rdp_level; +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 273 .loc 1 1133 1 view .LVU62 + 274 0014 7047 bx lr + 275 .LVL16: + 276 .L26: +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 277 .loc 1 1127 12 view .LVU63 + 278 0016 4FF4AA40 mov r0, #21760 + 279 .LVL17: +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 280 .loc 1 1127 12 view .LVU64 + 281 001a FBE7 b .L24 + 282 .L28: + 283 .align 2 + 284 .L27: + 285 001c 00200052 .word 1375739904 + 286 .cfi_endproc + 287 .LFE154: + 289 .section .text.FLASH_OB_UserConfig,"ax",%progbits + 290 .align 1 + 291 .syntax unified + 292 .thumb + 293 .thumb_func + 294 .fpu fpv5-d16 + 296 FLASH_OB_UserConfig: + 297 .LVL18: + 298 .LFB155: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + ARM GAS /tmp/ccM28uwG.s page 26 + + +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Program the FLASH User Option Byte. +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To configure the user option bytes, the option lock bit OPTLOCK must +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * be cleared with the call of the HAL_FLASH_OB_Unlock() function. +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To validate the user option bytes, the option bytes must be reloaded +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * through the call of the HAL_FLASH_OB_Launch() function. +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param UserType The FLASH User Option Bytes to be modified : +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * a combination of @ref FLASHEx_OB_USER_Type +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param UserConfig The FLASH User Option Bytes values: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL status +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Program the FLASH User Option Byte. +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To configure the user option bytes, the option lock bit OPTLOCK must +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * be cleared with the call of the HAL_FLASH_OB_Unlock() function. +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To validate the user option bytes, the option bytes must be reloaded +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * through the call of the HAL_FLASH_OB_Launch() function. +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param UserType The FLASH User Option Bytes to be modified : +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * a combination of @arg FLASHEx_OB_USER_Type +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param UserConfig The FLASH User Option Bytes values: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL status +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 299 .loc 1 1178 1 is_stmt 1 view -0 + 300 .cfi_startproc + 301 @ args = 0, pretend = 0, frame = 0 + 302 @ frame_needed = 0, uses_anonymous_args = 0 + 303 @ link register save eliminated. +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t optr_reg_val = 0; + 304 .loc 1 1179 3 view .LVU66 +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t optr_reg_mask = 0; + 305 .loc 1 1180 3 view .LVU67 +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_TYPE(UserType)); + 306 .loc 1 1183 3 view .LVU68 + ARM GAS /tmp/ccM28uwG.s page 27 + + +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_IWDG1_SW) != 0U) + 307 .loc 1 1185 3 view .LVU69 + 308 .loc 1 1185 5 is_stmt 0 view .LVU70 + 309 0000 10F00103 ands r3, r0, #1 + 310 0004 47D0 beq .L38 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* IWDG_HW option byte should be modified */ +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW)); + 311 .loc 1 1188 5 is_stmt 1 view .LVU71 +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for IWDG_HW option byte */ +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW); + 312 .loc 1 1191 5 view .LVU72 + 313 .loc 1 1191 33 is_stmt 0 view .LVU73 + 314 0006 01F01003 and r3, r1, #16 + 315 .LVL19: +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_IWDG1_SW; + 316 .loc 1 1192 5 is_stmt 1 view .LVU74 + 317 .loc 1 1192 19 is_stmt 0 view .LVU75 + 318 000a 1022 movs r2, #16 + 319 .LVL20: + 320 .L30: +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_IWDG2_SW) != 0U) +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* IWDG2_SW option byte should be modified */ +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW)); +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for IWDG2_SW option byte */ +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW); +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_IWDG2_SW; +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_NRST_STOP_D1) != 0U) + 321 .loc 1 1205 3 is_stmt 1 view .LVU76 + 322 .loc 1 1205 5 is_stmt 0 view .LVU77 + 323 000c 10F0020F tst r0, #2 + 324 0010 05D0 beq .L31 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* NRST_STOP option byte should be modified */ +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1)); + 325 .loc 1 1208 5 is_stmt 1 view .LVU78 +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for NRST_STOP option byte */ +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1); + 326 .loc 1 1211 5 view .LVU79 + 327 .loc 1 1211 33 is_stmt 0 view .LVU80 + 328 0012 01F0400C and ip, r1, #64 + 329 .loc 1 1211 18 view .LVU81 + 330 0016 43EA0C03 orr r3, r3, ip + 331 .LVL21: +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1; + 332 .loc 1 1212 5 is_stmt 1 view .LVU82 + 333 .loc 1 1212 19 is_stmt 0 view .LVU83 + 334 001a 42F04002 orr r2, r2, #64 + ARM GAS /tmp/ccM28uwG.s page 28 + + + 335 .LVL22: + 336 .L31: +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_NRST_STDBY_D1) != 0U) + 337 .loc 1 1215 3 is_stmt 1 view .LVU84 + 338 .loc 1 1215 5 is_stmt 0 view .LVU85 + 339 001e 10F0040F tst r0, #4 + 340 0022 05D0 beq .L32 +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* NRST_STDBY option byte should be modified */ +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1)); + 341 .loc 1 1218 5 is_stmt 1 view .LVU86 +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for NRST_STDBY option byte */ +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1); + 342 .loc 1 1221 5 view .LVU87 + 343 .loc 1 1221 33 is_stmt 0 view .LVU88 + 344 0024 01F0800C and ip, r1, #128 + 345 .loc 1 1221 18 view .LVU89 + 346 0028 43EA0C03 orr r3, r3, ip + 347 .LVL23: +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1; + 348 .loc 1 1222 5 is_stmt 1 view .LVU90 + 349 .loc 1 1222 19 is_stmt 0 view .LVU91 + 350 002c 42F08002 orr r2, r2, #128 + 351 .LVL24: + 352 .L32: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_IWDG_STOP) != 0U) + 353 .loc 1 1225 3 is_stmt 1 view .LVU92 + 354 .loc 1 1225 5 is_stmt 0 view .LVU93 + 355 0030 10F0080F tst r0, #8 + 356 0034 05D0 beq .L33 +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* IWDG_STOP option byte should be modified */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP)); + 357 .loc 1 1228 5 is_stmt 1 view .LVU94 +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for IWDG_STOP option byte */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP); + 358 .loc 1 1231 5 view .LVU95 + 359 .loc 1 1231 33 is_stmt 0 view .LVU96 + 360 0036 01F4003C and ip, r1, #131072 + 361 .loc 1 1231 18 view .LVU97 + 362 003a 43EA0C03 orr r3, r3, ip + 363 .LVL25: +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP; + 364 .loc 1 1232 5 is_stmt 1 view .LVU98 + 365 .loc 1 1232 19 is_stmt 0 view .LVU99 + 366 003e 42F40032 orr r2, r2, #131072 + 367 .LVL26: + 368 .L33: +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_IWDG_STDBY) != 0U) + ARM GAS /tmp/ccM28uwG.s page 29 + + + 369 .loc 1 1235 3 is_stmt 1 view .LVU100 + 370 .loc 1 1235 5 is_stmt 0 view .LVU101 + 371 0042 10F0100F tst r0, #16 + 372 0046 05D0 beq .L34 +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* IWDG_STDBY option byte should be modified */ +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY)); + 373 .loc 1 1238 5 is_stmt 1 view .LVU102 +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for IWDG_STDBY option byte */ +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY); + 374 .loc 1 1241 5 view .LVU103 + 375 .loc 1 1241 33 is_stmt 0 view .LVU104 + 376 0048 01F4802C and ip, r1, #262144 + 377 .loc 1 1241 18 view .LVU105 + 378 004c 43EA0C03 orr r3, r3, ip + 379 .LVL27: +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY; + 380 .loc 1 1242 5 is_stmt 1 view .LVU106 + 381 .loc 1 1242 19 is_stmt 0 view .LVU107 + 382 0050 42F48022 orr r2, r2, #262144 + 383 .LVL28: + 384 .L34: +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_ST_RAM_SIZE) != 0U) + 385 .loc 1 1245 3 is_stmt 1 view .LVU108 + 386 .loc 1 1245 5 is_stmt 0 view .LVU109 + 387 0054 10F0200F tst r0, #32 + 388 0058 05D0 beq .L35 +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* ST_RAM_SIZE option byte should be modified */ +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE)); + 389 .loc 1 1248 5 is_stmt 1 view .LVU110 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for ST_RAM_SIZE option byte */ +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE); + 390 .loc 1 1251 5 view .LVU111 + 391 .loc 1 1251 33 is_stmt 0 view .LVU112 + 392 005a 01F4C01C and ip, r1, #1572864 + 393 .loc 1 1251 18 view .LVU113 + 394 005e 43EA0C03 orr r3, r3, ip + 395 .LVL29: +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE; + 396 .loc 1 1252 5 is_stmt 1 view .LVU114 + 397 .loc 1 1252 19 is_stmt 0 view .LVU115 + 398 0062 42F4C012 orr r2, r2, #1572864 + 399 .LVL30: + 400 .L35: +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_SECURITY) != 0U) + 401 .loc 1 1255 3 is_stmt 1 view .LVU116 + 402 .loc 1 1255 5 is_stmt 0 view .LVU117 + 403 0066 10F0400F tst r0, #64 + 404 006a 05D0 beq .L36 +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccM28uwG.s page 30 + + +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* SECURITY option byte should be modified */ +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY)); + 405 .loc 1 1258 5 is_stmt 1 view .LVU118 +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for SECURITY option byte */ +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY); + 406 .loc 1 1261 5 view .LVU119 + 407 .loc 1 1261 33 is_stmt 0 view .LVU120 + 408 006c 01F4001C and ip, r1, #2097152 + 409 .loc 1 1261 18 view .LVU121 + 410 0070 43EA0C03 orr r3, r3, ip + 411 .LVL31: +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_SECURITY; + 412 .loc 1 1262 5 is_stmt 1 view .LVU122 + 413 .loc 1 1262 19 is_stmt 0 view .LVU123 + 414 0074 42F40012 orr r2, r2, #2097152 + 415 .LVL32: + 416 .L36: +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_BCM4) != 0U) +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* BCM4 option byte should be modified */ +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4)); +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for BCM4 option byte */ +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4); +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_BCM4; +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_BCM7) != 0U) +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* BCM7 option byte should be modified */ +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7)); +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for BCM7 option byte */ +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7); +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_BCM7; +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_CORE */ +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OPTSR_NRST_STOP_D2) +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_NRST_STOP_D2) != 0U) +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* NRST_STOP option byte should be modified */ +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2)); +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for NRST_STOP option byte */ +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2); +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2; +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_NRST_STDBY_D2) != 0U) +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* NRST_STDBY option byte should be modified */ +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2)); + ARM GAS /tmp/ccM28uwG.s page 31 + + +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for NRST_STDBY option byte */ +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2); +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2; +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR_NRST_STOP_D2 */ +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_SWAP_BANK) != 0U) +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* SWAP_BANK_OPT option byte should be modified */ +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT)); +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for SWAP_BANK_OPT option byte */ +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT); +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT; +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_IOHSLV) != 0U) + 417 .loc 1 1321 3 is_stmt 1 view .LVU124 + 418 .loc 1 1321 5 is_stmt 0 view .LVU125 + 419 0078 10F0800F tst r0, #128 + 420 007c 04D0 beq .L37 +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* IOHSLV_OPT option byte should be modified */ +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV)); + 421 .loc 1 1324 5 is_stmt 1 view .LVU126 +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for IOHSLV_OPT option byte */ +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV); + 422 .loc 1 1327 5 view .LVU127 + 423 .loc 1 1327 33 is_stmt 0 view .LVU128 + 424 007e 01F00051 and r1, r1, #536870912 + 425 .LVL33: + 426 .loc 1 1327 18 view .LVU129 + 427 0082 0B43 orrs r3, r3, r1 + 428 .LVL34: +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_IO_HSLV; + 429 .loc 1 1328 5 is_stmt 1 view .LVU130 + 430 .loc 1 1328 19 is_stmt 0 view .LVU131 + 431 0084 42F00052 orr r2, r2, #536870912 + 432 .LVL35: + 433 .L37: +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_OPTSR_VDDMMC_HSLV) +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((UserType & OB_USER_VDDMMC_HSLV) != 0U) +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* VDDMMC_HSLV option byte should be modified */ +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV)); +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set value and mask for VDDMMC_HSLV option byte */ +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV); +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV; +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* FLASH_OPTSR_VDDMMC_HSLV */ + ARM GAS /tmp/ccM28uwG.s page 32 + + +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the option bytes register */ +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val); + 434 .loc 1 1344 3 is_stmt 1 view .LVU132 + 435 0088 0448 ldr r0, .L39 + 436 .LVL36: + 437 .loc 1 1344 3 is_stmt 0 view .LVU133 + 438 008a 016A ldr r1, [r0, #32] + 439 008c 21EA0202 bic r2, r1, r2 + 440 .LVL37: + 441 .loc 1 1344 3 view .LVU134 + 442 0090 1343 orrs r3, r3, r2 + 443 .LVL38: + 444 .loc 1 1344 3 view .LVU135 + 445 0092 0362 str r3, [r0, #32] +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 446 .loc 1 1345 1 view .LVU136 + 447 0094 7047 bx lr + 448 .LVL39: + 449 .L38: +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 450 .loc 1 1180 12 view .LVU137 + 451 0096 1A46 mov r2, r3 + 452 0098 B8E7 b .L30 + 453 .L40: + 454 009a 00BF .align 2 + 455 .L39: + 456 009c 00200052 .word 1375739904 + 457 .cfi_endproc + 458 .LFE155: + 460 .section .text.FLASH_OB_GetUser,"ax",%progbits + 461 .align 1 + 462 .syntax unified + 463 .thumb + 464 .thumb_func + 465 .fpu fpv5-d16 + 467 FLASH_OB_GetUser: + 468 .LFB156: +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes values +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes values +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ + ARM GAS /tmp/ccM28uwG.s page 33 + + +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void) +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 469 .loc 1 1366 1 is_stmt 1 view -0 + 470 .cfi_startproc + 471 @ args = 0, pretend = 0, frame = 0 + 472 @ frame_needed = 0, uses_anonymous_args = 0 + 473 @ link register save eliminated. +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR); + 474 .loc 1 1367 3 view .LVU139 + 475 .loc 1 1367 12 is_stmt 0 view .LVU140 + 476 0000 024B ldr r3, .L42 + 477 0002 DB69 ldr r3, [r3, #28] + 478 .LVL40: +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP)); + 479 .loc 1 1368 3 is_stmt 1 view .LVU141 +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return userConfig; + 480 .loc 1 1370 3 view .LVU142 +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 481 .loc 1 1371 1 is_stmt 0 view .LVU143 + 482 0004 0248 ldr r0, .L42+4 + 483 0006 1840 ands r0, r0, r3 + 484 .LVL41: + 485 .loc 1 1371 1 view .LVU144 + 486 0008 7047 bx lr + 487 .L43: + 488 000a 00BF .align 2 + 489 .L42: + 490 000c 00200052 .word 1375739904 + 491 0010 F300FFFF .word -65293 + 492 .cfi_endproc + 493 .LFE156: + 495 .section .text.FLASH_OB_PCROPConfig,"ax",%progbits + 496 .align 1 + 497 .syntax unified + 498 .thumb + 499 .thumb_func + 500 .fpu fpv5-d16 + 502 FLASH_OB_PCROPConfig: + 503 .LVL42: + 504 .LFB157: +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Configure the Proprietary code readout protection of the desired addresses +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To configure the PCROP options, the option lock bit OPTLOCK must be +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * cleared with the call of the HAL_FLASH_OB_Unlock() function. +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @note To validate the PCROP options, the option bytes must be reloaded +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * through the call of the HAL_FLASH_OB_Launch() function. +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be an address between begin and end of the bank +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * + ARM GAS /tmp/ccM28uwG.s page 34 + + +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be an address between PCROPStartAddr and end of the bank +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Banks the specific bank to apply PCROP protection +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: PCROP on specified bank1 area +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: PCROP on specified bank2 area +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be a +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAd +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 505 .loc 1 1400 1 is_stmt 1 view -0 + 506 .cfi_startproc + 507 @ args = 0, pretend = 0, frame = 0 + 508 @ frame_needed = 0, uses_anonymous_args = 0 + 509 @ link register save eliminated. +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 510 .loc 1 1402 3 view .LVU146 +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_PCROP_RDP(PCROPConfig)); + 511 .loc 1 1403 3 view .LVU147 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + 512 .loc 1 1405 3 view .LVU148 + 513 .loc 1 1405 5 is_stmt 0 view .LVU149 + 514 0000 13F0010F tst r3, #1 + 515 0004 0AD0 beq .L44 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr)); + 516 .loc 1 1407 5 is_stmt 1 view .LVU150 +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr)); + 517 .loc 1 1408 5 view .LVU151 +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the Proprietary code readout protection */ +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8) | + 518 .loc 1 1411 5 view .LVU152 + 519 .loc 1 1411 41 is_stmt 0 view .LVU153 + 520 0006 01F17841 add r1, r1, #-134217728 + 521 .LVL43: +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | + 522 .loc 1 1412 40 view .LVU154 + 523 000a 02F17842 add r2, r2, #-134217728 + 524 .LVL44: + 525 .loc 1 1412 60 view .LVU155 + 526 000e 120A lsrs r2, r2, #8 + 527 .LVL45: + 528 .loc 1 1412 66 view .LVU156 + 529 0010 1204 lsls r2, r2, #16 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | + 530 .loc 1 1411 99 view .LVU157 + 531 0012 42EA1122 orr r2, r2, r1, lsr #8 + 532 .loc 1 1412 99 view .LVU158 + 533 0016 1043 orrs r0, r0, r2 + 534 .LVL46: +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | + ARM GAS /tmp/ccM28uwG.s page 35 + + + 535 .loc 1 1411 22 view .LVU159 + 536 0018 014B ldr r3, .L46 + 537 .LVL47: +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | + 538 .loc 1 1411 22 view .LVU160 + 539 001a D862 str r0, [r3, #44] + 540 .LVL48: + 541 .L44: +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** PCROPConfig; +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_2) == FLASH_BANK_2) +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr)); +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr)); +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the Proprietary code readout protection */ +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8) | +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** PCROPConfig; +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 542 .loc 1 1428 1 view .LVU161 + 543 001c 7047 bx lr + 544 .L47: + 545 001e 00BF .align 2 + 546 .L46: + 547 0020 00200052 .word 1375739904 + 548 .cfi_endproc + 549 .LFE157: + 551 .section .text.FLASH_OB_GetPCROP,"ax",%progbits + 552 .align 1 + 553 .syntax unified + 554 .thumb + 555 .thumb_func + 556 .fpu fpv5-d16 + 558 FLASH_OB_GetPCROP: + 559 .LVL49: + 560 .LFB158: +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get the Proprietary code readout protection configuration on a given Bank +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param PCROPStartAddr gives the start address of the Proprietary code readout protection of th +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param PCROPEndAddr gives the end address of the Proprietary code readout protection of the ba +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Bank the specific bank to apply PCROP protection +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be exclusively one of the following values: +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: PCROP on specified bank1 area +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: PCROP on specified bank2 area +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: is not allowed here + ARM GAS /tmp/ccM28uwG.s page 36 + + +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAd +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 561 .loc 1 1449 1 is_stmt 1 view -0 + 562 .cfi_startproc + 563 @ args = 0, pretend = 0, frame = 0 + 564 @ frame_needed = 0, uses_anonymous_args = 0 + 565 @ link register save eliminated. + 566 .loc 1 1449 1 is_stmt 0 view .LVU163 + 567 0000 10B4 push {r4} + 568 .LCFI0: + 569 .cfi_def_cfa_offset 4 + 570 .cfi_offset 4, -4 +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t regvalue = 0; + 571 .loc 1 1450 3 is_stmt 1 view .LVU164 + 572 .LVL50: +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t bankBase = 0; + 573 .loc 1 1451 3 view .LVU165 +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(Bank == FLASH_BANK_1) + 574 .loc 1 1453 3 view .LVU166 + 575 .loc 1 1453 5 is_stmt 0 view .LVU167 + 576 0002 012B cmp r3, #1 + 577 0004 13D0 beq .L52 +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t bankBase = 0; + 578 .loc 1 1451 12 view .LVU168 + 579 0006 4FF0000C mov ip, #0 +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t bankBase = 0; + 580 .loc 1 1450 12 view .LVU169 + 581 000a 6346 mov r3, ip + 582 .LVL51: + 583 .L49: +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->PRAR_CUR1; +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(Bank == FLASH_BANK_2) +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->PRAR_CUR2; +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK2_BASE; +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP); + 584 .loc 1 1467 3 is_stmt 1 view .LVU170 + 585 .loc 1 1467 31 is_stmt 0 view .LVU171 + 586 000c 03F00044 and r4, r3, #-2147483648 + 587 .loc 1 1467 18 view .LVU172 + 588 0010 0460 str r4, [r0] +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase; + 589 .loc 1 1469 3 is_stmt 1 view .LVU173 + 590 .loc 1 1469 64 is_stmt 0 view .LVU174 + ARM GAS /tmp/ccM28uwG.s page 37 + + + 591 0012 0948 ldr r0, .L53 + 592 .LVL52: + 593 .loc 1 1469 64 view .LVU175 + 594 0014 00EA0320 and r0, r0, r3, lsl #8 + 595 .loc 1 1469 70 view .LVU176 + 596 0018 6044 add r0, r0, ip + 597 .loc 1 1469 21 view .LVU177 + 598 001a 0860 str r0, [r1] +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos; + 599 .loc 1 1470 3 is_stmt 1 view .LVU178 + 600 .loc 1 1470 59 is_stmt 0 view .LVU179 + 601 001c C3F30B43 ubfx r3, r3, #16, #12 + 602 .LVL53: + 603 .loc 1 1470 19 view .LVU180 + 604 0020 1360 str r3, [r2] +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase; + 605 .loc 1 1471 3 is_stmt 1 view .LVU181 + 606 .loc 1 1471 44 is_stmt 0 view .LVU182 + 607 0022 0CEB0323 add r3, ip, r3, lsl #8 + 608 .loc 1 1471 19 view .LVU183 + 609 0026 1360 str r3, [r2] +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 610 .loc 1 1472 1 view .LVU184 + 611 0028 5DF8044B ldr r4, [sp], #4 + 612 .LCFI1: + 613 .cfi_remember_state + 614 .cfi_restore 4 + 615 .cfi_def_cfa_offset 0 + 616 002c 7047 bx lr + 617 .LVL54: + 618 .L52: + 619 .LCFI2: + 620 .cfi_restore_state +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; + 621 .loc 1 1455 5 is_stmt 1 view .LVU185 +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; + 622 .loc 1 1455 14 is_stmt 0 view .LVU186 + 623 002e 034B ldr r3, .L53+4 + 624 .LVL55: +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; + 625 .loc 1 1455 14 view .LVU187 + 626 0030 9B6A ldr r3, [r3, #40] + 627 .LVL56: +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 628 .loc 1 1456 5 is_stmt 1 view .LVU188 +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 629 .loc 1 1456 14 is_stmt 0 view .LVU189 + 630 0032 4FF0006C mov ip, #134217728 + 631 0036 E9E7 b .L49 + 632 .L54: + 633 .align 2 + 634 .L53: + 635 0038 00FF0F00 .word 1048320 + 636 003c 00200052 .word 1375739904 + 637 .cfi_endproc + 638 .LFE158: + 640 .section .text.FLASH_OB_BOR_LevelConfig,"ax",%progbits + ARM GAS /tmp/ccM28uwG.s page 38 + + + 641 .align 1 + 642 .syntax unified + 643 .thumb + 644 .thumb_func + 645 .fpu fpv5-d16 + 647 FLASH_OB_BOR_LevelConfig: + 648 .LVL57: + 649 .LFB159: +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Set the BOR Level. +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Level specifies the Option Bytes BOR Reset Level. +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_BOR_LevelConfig(uint32_t Level) +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 650 .loc 1 1485 1 is_stmt 1 view -0 + 651 .cfi_startproc + 652 @ args = 0, pretend = 0, frame = 0 + 653 @ frame_needed = 0, uses_anonymous_args = 0 + 654 @ link register save eliminated. +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_BOR_LEVEL(Level)); + 655 .loc 1 1486 3 view .LVU191 +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure BOR_LEV option byte */ +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level); + 656 .loc 1 1489 3 view .LVU192 + 657 0000 034A ldr r2, .L56 + 658 0002 136A ldr r3, [r2, #32] + 659 0004 23F00C03 bic r3, r3, #12 + 660 0008 0343 orrs r3, r3, r0 + 661 000a 1362 str r3, [r2, #32] +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 662 .loc 1 1490 1 is_stmt 0 view .LVU193 + 663 000c 7047 bx lr + 664 .L57: + 665 000e 00BF .align 2 + 666 .L56: + 667 0010 00200052 .word 1375739904 + 668 .cfi_endproc + 669 .LFE159: + 671 .section .text.FLASH_OB_GetBOR,"ax",%progbits + 672 .align 1 + 673 .syntax unified + 674 .thumb + 675 .thumb_func + 676 .fpu fpv5-d16 + 678 FLASH_OB_GetBOR: + 679 .LFB160: +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get the BOR Level. + ARM GAS /tmp/ccM28uwG.s page 39 + + +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval The Option Bytes BOR Reset Level. +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBOR(void) +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 680 .loc 1 1502 1 is_stmt 1 view -0 + 681 .cfi_startproc + 682 @ args = 0, pretend = 0, frame = 0 + 683 @ frame_needed = 0, uses_anonymous_args = 0 + 684 @ link register save eliminated. +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV); + 685 .loc 1 1503 3 view .LVU195 + 686 .loc 1 1503 16 is_stmt 0 view .LVU196 + 687 0000 024B ldr r3, .L59 + 688 0002 D869 ldr r0, [r3, #28] +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 689 .loc 1 1504 1 view .LVU197 + 690 0004 00F00C00 and r0, r0, #12 + 691 0008 7047 bx lr + 692 .L60: + 693 000a 00BF .align 2 + 694 .L59: + 695 000c 00200052 .word 1375739904 + 696 .cfi_endproc + 697 .LFE160: + 699 .section .text.FLASH_OB_BootAddConfig,"ax",%progbits + 700 .align 1 + 701 .syntax unified + 702 .thumb + 703 .thumb_func + 704 .fpu fpv5-d16 + 706 FLASH_OB_BootAddConfig: + 707 .LVL58: + 708 .LFB161: +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Set Boot address +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootOption Boot address option byte to be programmed, +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress0 Specifies the Boot Address 0 +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress1 Specifies the Boot Address 1 +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 709 .loc 1 1517 1 is_stmt 1 view -0 + 710 .cfi_startproc + 711 @ args = 0, pretend = 0, frame = 0 + 712 @ frame_needed = 0, uses_anonymous_args = 0 + 713 @ link register save eliminated. + 714 .loc 1 1517 1 is_stmt 0 view .LVU199 + ARM GAS /tmp/ccM28uwG.s page 40 + + + 715 0000 30B4 push {r4, r5} + 716 .LCFI3: + 717 .cfi_def_cfa_offset 8 + 718 .cfi_offset 4, -8 + 719 .cfi_offset 5, -4 +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + 720 .loc 1 1519 3 is_stmt 1 view .LVU200 +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + 721 .loc 1 1521 3 view .LVU201 + 722 .loc 1 1521 5 is_stmt 0 view .LVU202 + 723 0002 10F0010F tst r0, #1 + 724 0006 06D0 beq .L62 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_BOOT_ADDRESS(BootAddress0)); + 725 .loc 1 1524 5 is_stmt 1 view .LVU203 +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure CM7 BOOT ADD0 */ +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16)); +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else /* Single Core*/ +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16)); + 726 .loc 1 1530 5 view .LVU204 + 727 0008 084C ldr r4, .L65 + 728 000a 656C ldr r5, [r4, #68] + 729 000c 084B ldr r3, .L65+4 + 730 000e 2B40 ands r3, r3, r5 + 731 0010 43EA1141 orr r1, r3, r1, lsr #16 + 732 .LVL59: + 733 .loc 1 1530 5 is_stmt 0 view .LVU205 + 734 0014 6164 str r1, [r4, #68] + 735 .L62: +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_CORE */ +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + 736 .loc 1 1534 3 is_stmt 1 view .LVU206 + 737 .loc 1 1534 5 is_stmt 0 view .LVU207 + 738 0016 10F0020F tst r0, #2 + 739 001a 04D0 beq .L61 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_BOOT_ADDRESS(BootAddress1)); + 740 .loc 1 1537 5 is_stmt 1 view .LVU208 +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure CM7 BOOT ADD1 */ +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1); +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else /* Single Core*/ +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1); + 741 .loc 1 1543 5 view .LVU209 + 742 001c 0349 ldr r1, .L65 + 743 001e 4B6C ldr r3, [r1, #68] + 744 0020 9BB2 uxth r3, r3 + 745 0022 1A43 orrs r2, r2, r3 + ARM GAS /tmp/ccM28uwG.s page 41 + + + 746 .LVL60: + 747 .loc 1 1543 5 is_stmt 0 view .LVU210 + 748 0024 4A64 str r2, [r1, #68] + 749 .L61: +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_CORE */ +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 750 .loc 1 1546 1 view .LVU211 + 751 0026 30BC pop {r4, r5} + 752 .LCFI4: + 753 .cfi_restore 5 + 754 .cfi_restore 4 + 755 .cfi_def_cfa_offset 0 + 756 0028 7047 bx lr + 757 .L66: + 758 002a 00BF .align 2 + 759 .L65: + 760 002c 00200052 .word 1375739904 + 761 0030 0000FFFF .word -65536 + 762 .cfi_endproc + 763 .LFE161: + 765 .section .text.FLASH_OB_GetBootAdd,"ax",%progbits + 766 .align 1 + 767 .syntax unified + 768 .thumb + 769 .thumb_func + 770 .fpu fpv5-d16 + 772 FLASH_OB_GetBootAdd: + 773 .LVL61: + 774 .LFB162: +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get Boot address +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress0 Specifies the Boot Address 0. +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress1 Specifies the Boot Address 1. +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 775 .loc 1 1555 1 is_stmt 1 view -0 + 776 .cfi_startproc + 777 @ args = 0, pretend = 0, frame = 0 + 778 @ frame_needed = 0, uses_anonymous_args = 0 + 779 @ link register save eliminated. +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t regvalue; + 780 .loc 1 1556 3 view .LVU213 +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->BOOT7_CUR; +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16; +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1); +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else /* Single Core */ +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->BOOT_CUR; + 781 .loc 1 1564 3 view .LVU214 + 782 .loc 1 1564 12 is_stmt 0 view .LVU215 + 783 0000 034B ldr r3, .L68 + ARM GAS /tmp/ccM28uwG.s page 42 + + + 784 0002 1A6C ldr r2, [r3, #64] + 785 .LVL62: +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16; + 786 .loc 1 1566 3 is_stmt 1 view .LVU216 + 787 .loc 1 1566 50 is_stmt 0 view .LVU217 + 788 0004 1304 lsls r3, r2, #16 + 789 .loc 1 1566 19 view .LVU218 + 790 0006 0360 str r3, [r0] +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1); + 791 .loc 1 1567 3 is_stmt 1 view .LVU219 + 792 .loc 1 1567 31 is_stmt 0 view .LVU220 + 793 0008 024B ldr r3, .L68+4 + 794 000a 1340 ands r3, r3, r2 + 795 .loc 1 1567 19 view .LVU221 + 796 000c 0B60 str r3, [r1] +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_CORE */ +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 797 .loc 1 1569 1 view .LVU222 + 798 000e 7047 bx lr + 799 .L69: + 800 .align 2 + 801 .L68: + 802 0010 00200052 .word 1375739904 + 803 0014 0000FFFF .word -65536 + 804 .cfi_endproc + 805 .LFE162: + 807 .section .text.FLASH_OB_SecureAreaConfig,"ax",%progbits + 808 .align 1 + 809 .syntax unified + 810 .thumb + 811 .thumb_func + 812 .fpu fpv5-d16 + 814 FLASH_OB_SecureAreaConfig: + 815 .LVL63: + 816 .LFB163: +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Set CM4 Boot address +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootOption Boot address option byte to be programmed, +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress0 Specifies the CM4 Boot Address 0. +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress1 Specifies the CM4 Boot Address 1. +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddr +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_BOOT_ADDRESS(BootAddress0)); + ARM GAS /tmp/ccM28uwG.s page 43 + + +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure CM4 BOOT ADD0 */ +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16)); +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_BOOT_ADDRESS(BootAddress1)); +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure CM4 BOOT ADD1 */ +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1); +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get CM4 Boot address +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress0 Specifies the CM4 Boot Address 0. +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param BootAddress1 Specifies the CM4 Boot Address 1. +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval HAL Status +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t regvalue; +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->BOOT4_CUR; +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16; +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1); +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Set secure area configuration +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param SecureAreaConfig specify if the secure area will be deleted or not +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * when RDP level decreased from Level 1 to Level 0 or during a mass erase. +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param SecureAreaStartAddr Specifies the secure area start address +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param SecureAreaEndAddr Specifies the secure area end address +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Banks the specific bank to apply Security protection +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Secure area on specified bank1 area +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Secure area on specified bank2 area +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config wil +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 817 .loc 1 1639 1 is_stmt 1 view -0 + 818 .cfi_startproc + 819 @ args = 0, pretend = 0, frame = 0 + 820 @ frame_needed = 0, uses_anonymous_args = 0 + 821 @ link register save eliminated. +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 822 .loc 1 1641 3 view .LVU224 + ARM GAS /tmp/ccM28uwG.s page 44 + + +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_OB_SECURE_RDP(SecureAreaConfig)); + 823 .loc 1 1642 3 view .LVU225 +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + 824 .loc 1 1644 3 view .LVU226 + 825 .loc 1 1644 5 is_stmt 0 view .LVU227 + 826 0000 13F0010F tst r3, #1 + 827 0004 0CD0 beq .L70 +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr)); + 828 .loc 1 1647 5 is_stmt 1 view .LVU228 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr)); + 829 .loc 1 1648 5 view .LVU229 +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the secure area */ +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8) + 830 .loc 1 1651 5 view .LVU230 + 831 .loc 1 1651 46 is_stmt 0 view .LVU231 + 832 0006 01F17841 add r1, r1, #-134217728 + 833 .LVL64: +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Po + 834 .loc 1 1652 45 view .LVU232 + 835 000a 02F17842 add r2, r2, #-134217728 + 836 .LVL65: + 837 .loc 1 1652 65 view .LVU233 + 838 000e 120A lsrs r2, r2, #8 + 839 .LVL66: + 840 .loc 1 1652 71 view .LVU234 + 841 0010 1204 lsls r2, r2, #16 +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Po + 842 .loc 1 1651 103 view .LVU235 + 843 0012 42EA1122 orr r2, r2, r1, lsr #8 +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (SecureAreaConfig & FLASH_SCAR_DMES); + 844 .loc 1 1653 42 view .LVU236 + 845 0016 00F00040 and r0, r0, #-2147483648 + 846 .LVL67: +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Po + 847 .loc 1 1652 103 view .LVU237 + 848 001a 1043 orrs r0, r0, r2 +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Po + 849 .loc 1 1651 22 view .LVU238 + 850 001c 014B ldr r3, .L72 + 851 .LVL68: +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Po + 852 .loc 1 1651 22 view .LVU239 + 853 001e 5863 str r0, [r3, #52] + 854 .LVL69: + 855 .L70: +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if((Banks & FLASH_BANK_2) == FLASH_BANK_2) +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr)); +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr)); + ARM GAS /tmp/ccM28uwG.s page 45 + + +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Configure the secure area */ +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8) +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Po +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (SecureAreaConfig & FLASH_SCAR_DMES); +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 856 .loc 1 1669 1 view .LVU240 + 857 0020 7047 bx lr + 858 .L73: + 859 0022 00BF .align 2 + 860 .L72: + 861 0024 00200052 .word 1375739904 + 862 .cfi_endproc + 863 .LFE163: + 865 .section .text.FLASH_OB_GetSecureArea,"ax",%progbits + 866 .align 1 + 867 .syntax unified + 868 .thumb + 869 .thumb_func + 870 .fpu fpv5-d16 + 872 FLASH_OB_GetSecureArea: + 873 .LVL70: + 874 .LFB164: +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Get secure area configuration +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param SecureAreaConfig indicates if the secure area will be deleted or not +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * when RDP level decreased from Level 1 to Level 0 or during a mass erase. +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param SecureAreaStartAddr gives the secure area start address +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param SecureAreaEndAddr gives the secure area end address +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Bank Specifies the Bank +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint3 +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 875 .loc 1 1681 1 is_stmt 1 view -0 + 876 .cfi_startproc + 877 @ args = 0, pretend = 0, frame = 0 + 878 @ frame_needed = 0, uses_anonymous_args = 0 + 879 @ link register save eliminated. + 880 .loc 1 1681 1 is_stmt 0 view .LVU242 + 881 0000 10B4 push {r4} + 882 .LCFI5: + 883 .cfi_def_cfa_offset 4 + 884 .cfi_offset 4, -4 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t regvalue = 0; + 885 .loc 1 1682 3 is_stmt 1 view .LVU243 + 886 .LVL71: +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t bankBase = 0; + 887 .loc 1 1683 3 view .LVU244 +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check Bank parameter value */ +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(Bank == FLASH_BANK_1) + 888 .loc 1 1686 3 view .LVU245 + 889 .loc 1 1686 5 is_stmt 0 view .LVU246 + ARM GAS /tmp/ccM28uwG.s page 46 + + + 890 0002 012B cmp r3, #1 + 891 0004 13D0 beq .L78 +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t bankBase = 0; + 892 .loc 1 1683 12 view .LVU247 + 893 0006 4FF0000C mov ip, #0 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t bankBase = 0; + 894 .loc 1 1682 12 view .LVU248 + 895 000a 6346 mov r3, ip + 896 .LVL72: + 897 .L75: +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->SCAR_CUR1; +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(Bank == FLASH_BANK_2) +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** regvalue = FLASH->SCAR_CUR2; +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK2_BASE; +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Get the secure area settings */ +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES); + 898 .loc 1 1701 3 is_stmt 1 view .LVU249 + 899 .loc 1 1701 35 is_stmt 0 view .LVU250 + 900 000c 03F00044 and r4, r3, #-2147483648 + 901 .loc 1 1701 23 view .LVU251 + 902 0010 0460 str r4, [r0] +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase; + 903 .loc 1 1702 3 is_stmt 1 view .LVU252 + 904 .loc 1 1702 68 is_stmt 0 view .LVU253 + 905 0012 0948 ldr r0, .L79 + 906 .LVL73: + 907 .loc 1 1702 68 view .LVU254 + 908 0014 00EA0320 and r0, r0, r3, lsl #8 + 909 .loc 1 1702 74 view .LVU255 + 910 0018 6044 add r0, r0, ip + 911 .loc 1 1702 26 view .LVU256 + 912 001a 0860 str r0, [r1] +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos; + 913 .loc 1 1703 3 is_stmt 1 view .LVU257 + 914 .loc 1 1703 63 is_stmt 0 view .LVU258 + 915 001c C3F30B43 ubfx r3, r3, #16, #12 + 916 .LVL74: + 917 .loc 1 1703 24 view .LVU259 + 918 0020 1360 str r3, [r2] +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase; + 919 .loc 1 1704 3 is_stmt 1 view .LVU260 + 920 .loc 1 1704 54 is_stmt 0 view .LVU261 + 921 0022 0CEB0323 add r3, ip, r3, lsl #8 + 922 .loc 1 1704 24 view .LVU262 + 923 0026 1360 str r3, [r2] +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 924 .loc 1 1705 1 view .LVU263 + 925 0028 5DF8044B ldr r4, [sp], #4 + ARM GAS /tmp/ccM28uwG.s page 47 + + + 926 .LCFI6: + 927 .cfi_remember_state + 928 .cfi_restore 4 + 929 .cfi_def_cfa_offset 0 + 930 002c 7047 bx lr + 931 .LVL75: + 932 .L78: + 933 .LCFI7: + 934 .cfi_restore_state +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; + 935 .loc 1 1688 5 is_stmt 1 view .LVU264 +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; + 936 .loc 1 1688 14 is_stmt 0 view .LVU265 + 937 002e 034B ldr r3, .L79+4 + 938 .LVL76: +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** bankBase = FLASH_BANK1_BASE; + 939 .loc 1 1688 14 view .LVU266 + 940 0030 1B6B ldr r3, [r3, #48] + 941 .LVL77: +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 942 .loc 1 1689 5 is_stmt 1 view .LVU267 +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 943 .loc 1 1689 14 is_stmt 0 view .LVU268 + 944 0032 4FF0006C mov ip, #134217728 + 945 0036 E9E7 b .L75 + 946 .L80: + 947 .align 2 + 948 .L79: + 949 0038 00FF0F00 .word 1048320 + 950 003c 00200052 .word 1375739904 + 951 .cfi_endproc + 952 .LFE164: + 954 .section .text.FLASH_CRC_AddSector,"ax",%progbits + 955 .align 1 + 956 .syntax unified + 957 .thumb + 958 .thumb_func + 959 .fpu fpv5-d16 + 961 FLASH_CRC_AddSector: + 962 .LVL78: + 963 .LFB165: +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Add a CRC sector to the list of sectors on which the CRC will be calculated +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Sector Specifies the CRC sector number +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Bank Specifies the Bank +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 964 .loc 1 1714 1 is_stmt 1 view -0 + 965 .cfi_startproc + 966 @ args = 0, pretend = 0, frame = 0 + 967 @ frame_needed = 0, uses_anonymous_args = 0 + 968 @ link register save eliminated. +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Check the parameters */ +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_SECTOR(Sector)); + ARM GAS /tmp/ccM28uwG.s page 48 + + + 969 .loc 1 1716 3 view .LVU270 +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (Bank == FLASH_BANK_1) + 970 .loc 1 1718 3 view .LVU271 + 971 .loc 1 1718 6 is_stmt 0 view .LVU272 + 972 0000 0129 cmp r1, #1 + 973 0002 00D0 beq .L83 + 974 .LVL79: + 975 .L81: +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear CRC sector */ +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT); +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Select CRC Sector and activate ADD_SECT bit */ +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT; +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Clear CRC sector */ +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT); +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Select CRC Sector and activate ADD_SECT bit */ +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT; +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 976 .loc 1 1736 1 view .LVU273 + 977 0004 7047 bx lr + 978 .LVL80: + 979 .L83: +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 980 .loc 1 1721 5 is_stmt 1 view .LVU274 +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 981 .loc 1 1721 19 is_stmt 0 view .LVU275 + 982 0006 054A ldr r2, .L84 + 983 0008 136D ldr r3, [r2, #80] + 984 000a 23F00703 bic r3, r3, #7 + 985 000e 1365 str r3, [r2, #80] +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 986 .loc 1 1724 5 is_stmt 1 view .LVU276 +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 987 .loc 1 1724 19 is_stmt 0 view .LVU277 + 988 0010 136D ldr r3, [r2, #80] + 989 0012 1843 orrs r0, r0, r3 + 990 .LVL81: +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 991 .loc 1 1724 19 view .LVU278 + 992 0014 40F40070 orr r0, r0, #512 + 993 0018 1065 str r0, [r2, #80] + 994 .loc 1 1736 1 view .LVU279 + 995 001a F3E7 b .L81 + 996 .L85: + 997 .align 2 + 998 .L84: + 999 001c 00200052 .word 1375739904 + 1000 .cfi_endproc + ARM GAS /tmp/ccM28uwG.s page 49 + + + 1001 .LFE165: + 1003 .section .text.FLASH_CRC_SelectAddress,"ax",%progbits + 1004 .align 1 + 1005 .syntax unified + 1006 .thumb + 1007 .thumb_func + 1008 .fpu fpv5-d16 + 1010 FLASH_CRC_SelectAddress: + 1011 .LVL82: + 1012 .LFB166: +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /** +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @brief Select CRC start and end memory addresses on which the CRC will be calculated +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param CRCStartAddr Specifies the CRC start address +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param CRCEndAddr Specifies the CRC end address +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @param Bank Specifies the Bank +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** * @retval None +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** */ +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank) +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1013 .loc 1 1746 1 is_stmt 1 view -0 + 1014 .cfi_startproc + 1015 @ args = 0, pretend = 0, frame = 0 + 1016 @ frame_needed = 0, uses_anonymous_args = 0 + 1017 @ link register save eliminated. +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if (Bank == FLASH_BANK_1) + 1018 .loc 1 1747 3 view .LVU281 + 1019 .loc 1 1747 6 is_stmt 0 view .LVU282 + 1020 0000 012A cmp r2, #1 + 1021 0002 00D0 beq .L88 + 1022 .L86: +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr)); +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr)); +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Write CRC Start and End addresses */ +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCSADD1 = CRCStartAddr; +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCEADD1 = CRCEndAddr; +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (DUAL_BANK) +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** else +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr)); +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr)); +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Write CRC Start and End addresses */ +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCSADD2 = CRCStartAddr; +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCEADD2 = CRCEndAddr; +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1023 .loc 1 1767 1 view .LVU283 + 1024 0004 7047 bx lr + 1025 .L88: +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr)); + 1026 .loc 1 1749 5 is_stmt 1 view .LVU284 +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + ARM GAS /tmp/ccM28uwG.s page 50 + + + 1027 .loc 1 1750 5 view .LVU285 +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCEADD1 = CRCEndAddr; + 1028 .loc 1 1753 5 view .LVU286 +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH->CRCEADD1 = CRCEndAddr; + 1029 .loc 1 1753 21 is_stmt 0 view .LVU287 + 1030 0006 024B ldr r3, .L89 + 1031 0008 5865 str r0, [r3, #84] +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1032 .loc 1 1754 5 is_stmt 1 view .LVU288 +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1033 .loc 1 1754 21 is_stmt 0 view .LVU289 + 1034 000a 9965 str r1, [r3, #88] + 1035 .loc 1 1767 1 view .LVU290 + 1036 000c FAE7 b .L86 + 1037 .L90: + 1038 000e 00BF .align 2 + 1039 .L89: + 1040 0010 00200052 .word 1375739904 + 1041 .cfi_endproc + 1042 .LFE166: + 1044 .section .text.HAL_FLASHEx_OBProgram,"ax",%progbits + 1045 .align 1 + 1046 .global HAL_FLASHEx_OBProgram + 1047 .syntax unified + 1048 .thumb + 1049 .thumb_func + 1050 .fpu fpv5-d16 + 1052 HAL_FLASHEx_OBProgram: + 1053 .LVL83: + 1054 .LFB143: + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1055 .loc 1 417 1 is_stmt 1 view -0 + 1056 .cfi_startproc + 1057 @ args = 0, pretend = 0, frame = 0 + 1058 @ frame_needed = 0, uses_anonymous_args = 0 + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1059 .loc 1 417 1 is_stmt 0 view .LVU292 + 1060 0000 38B5 push {r3, r4, r5, lr} + 1061 .LCFI8: + 1062 .cfi_def_cfa_offset 16 + 1063 .cfi_offset 3, -16 + 1064 .cfi_offset 4, -12 + 1065 .cfi_offset 5, -8 + 1066 .cfi_offset 14, -4 + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1067 .loc 1 418 3 is_stmt 1 view .LVU293 + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1068 .loc 1 421 3 view .LVU294 + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1069 .loc 1 424 3 view .LVU295 + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1070 .loc 1 424 3 view .LVU296 + 1071 0002 314B ldr r3, .L110 + 1072 0004 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 1073 0006 012B cmp r3, #1 + 1074 0008 5BD0 beq .L101 + 1075 000a 0446 mov r4, r0 + ARM GAS /tmp/ccM28uwG.s page 51 + + + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1076 .loc 1 424 3 discriminator 2 view .LVU297 + 1077 000c 2E4B ldr r3, .L110 + 1078 000e 0121 movs r1, #1 + 1079 0010 1975 strb r1, [r3, #20] + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1080 .loc 1 424 3 discriminator 2 view .LVU298 + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1081 .loc 1 427 3 discriminator 2 view .LVU299 + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1082 .loc 1 427 20 is_stmt 0 discriminator 2 view .LVU300 + 1083 0012 0022 movs r2, #0 + 1084 0014 9A61 str r2, [r3, #24] + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1085 .loc 1 430 3 is_stmt 1 discriminator 2 view .LVU301 + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1086 .loc 1 430 6 is_stmt 0 discriminator 2 view .LVU302 + 1087 0016 4CF25030 movw r0, #50000 + 1088 .LVL84: + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1089 .loc 1 430 6 discriminator 2 view .LVU303 + 1090 001a FFF7FEFF bl FLASH_WaitForLastOperation + 1091 .LVL85: + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1092 .loc 1 430 5 discriminator 2 view .LVU304 + 1093 001e 0546 mov r5, r0 + 1094 0020 0028 cmp r0, #0 + 1095 0022 48D1 bne .L102 + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1096 .loc 1 442 5 is_stmt 1 view .LVU305 + 1097 .LVL86: + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1098 .loc 1 445 3 view .LVU306 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1099 .loc 1 448 5 view .LVU307 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1100 .loc 1 448 16 is_stmt 0 view .LVU308 + 1101 0024 2368 ldr r3, [r4] + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1102 .loc 1 448 7 view .LVU309 + 1103 0026 13F0010F tst r3, #1 + 1104 002a 06D0 beq .L94 + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1105 .loc 1 450 7 is_stmt 1 view .LVU310 + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1106 .loc 1 452 7 view .LVU311 + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1107 .loc 1 452 17 is_stmt 0 view .LVU312 + 1108 002c 6368 ldr r3, [r4, #4] + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1109 .loc 1 452 9 view .LVU313 + 1110 002e 012B cmp r3, #1 + 1111 0030 22D0 beq .L104 + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1112 .loc 1 460 9 is_stmt 1 view .LVU314 + 1113 0032 E169 ldr r1, [r4, #28] + 1114 0034 A068 ldr r0, [r4, #8] + ARM GAS /tmp/ccM28uwG.s page 52 + + + 1115 0036 FFF7FEFF bl FLASH_OB_DisableWRP + 1116 .LVL87: + 1117 .L94: + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1118 .loc 1 465 5 view .LVU315 + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1119 .loc 1 465 16 is_stmt 0 view .LVU316 + 1120 003a 2368 ldr r3, [r4] + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1121 .loc 1 465 7 view .LVU317 + 1122 003c 13F0020F tst r3, #2 + 1123 0040 1FD1 bne .L105 + 1124 .L96: + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1125 .loc 1 472 5 is_stmt 1 view .LVU318 + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1126 .loc 1 472 16 is_stmt 0 view .LVU319 + 1127 0042 2368 ldr r3, [r4] + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1128 .loc 1 472 7 view .LVU320 + 1129 0044 13F0040F tst r3, #4 + 1130 0048 1FD1 bne .L106 + 1131 .L97: + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1132 .loc 1 479 5 is_stmt 1 view .LVU321 + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1133 .loc 1 479 16 is_stmt 0 view .LVU322 + 1134 004a 2368 ldr r3, [r4] + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1135 .loc 1 479 7 view .LVU323 + 1136 004c 13F0080F tst r3, #8 + 1137 0050 20D1 bne .L107 + 1138 .L98: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1139 .loc 1 488 5 is_stmt 1 view .LVU324 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1140 .loc 1 488 16 is_stmt 0 view .LVU325 + 1141 0052 2368 ldr r3, [r4] + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1142 .loc 1 488 7 view .LVU326 + 1143 0054 13F0100F tst r3, #16 + 1144 0058 23D1 bne .L108 + 1145 .L99: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1146 .loc 1 507 5 is_stmt 1 view .LVU327 + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1147 .loc 1 507 16 is_stmt 0 view .LVU328 + 1148 005a 2368 ldr r3, [r4] + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1149 .loc 1 507 7 view .LVU329 + 1150 005c 13F0400F tst r3, #64 + 1151 0060 23D1 bne .L109 + 1152 .L100: + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1153 .loc 1 514 5 is_stmt 1 view .LVU330 + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1154 .loc 1 514 16 is_stmt 0 view .LVU331 + ARM GAS /tmp/ccM28uwG.s page 53 + + + 1155 0062 2368 ldr r3, [r4] + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1156 .loc 1 514 7 view .LVU332 + 1157 0064 13F0200F tst r3, #32 + 1158 0068 26D0 beq .L93 + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1159 .loc 1 516 7 is_stmt 1 view .LVU333 + 1160 006a E369 ldr r3, [r4, #28] + 1161 006c 226C ldr r2, [r4, #64] + 1162 006e E16B ldr r1, [r4, #60] + 1163 0070 A06B ldr r0, [r4, #56] + 1164 0072 FFF7FEFF bl FLASH_OB_SecureAreaConfig + 1165 .LVL88: + 1166 0076 1FE0 b .L93 + 1167 .L104: + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1168 .loc 1 455 9 view .LVU334 + 1169 0078 E169 ldr r1, [r4, #28] + 1170 007a A068 ldr r0, [r4, #8] + 1171 007c FFF7FEFF bl FLASH_OB_EnableWRP + 1172 .LVL89: + 1173 0080 DBE7 b .L94 + 1174 .L105: + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1175 .loc 1 468 7 view .LVU335 + 1176 0082 E068 ldr r0, [r4, #12] + 1177 0084 FFF7FEFF bl FLASH_OB_RDPConfig + 1178 .LVL90: + 1179 0088 DBE7 b .L96 + 1180 .L106: + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1181 .loc 1 475 7 view .LVU336 + 1182 008a A169 ldr r1, [r4, #24] + 1183 008c 6069 ldr r0, [r4, #20] + 1184 008e FFF7FEFF bl FLASH_OB_UserConfig + 1185 .LVL91: + 1186 0092 DAE7 b .L97 + 1187 .L107: + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1188 .loc 1 481 7 view .LVU337 + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1189 .loc 1 484 7 view .LVU338 + 1190 0094 E369 ldr r3, [r4, #28] + 1191 0096 A26A ldr r2, [r4, #40] + 1192 0098 616A ldr r1, [r4, #36] + 1193 009a 206A ldr r0, [r4, #32] + 1194 009c FFF7FEFF bl FLASH_OB_PCROPConfig + 1195 .LVL92: + 1196 00a0 D7E7 b .L98 + 1197 .L108: + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1198 .loc 1 490 7 view .LVU339 + 1199 00a2 2069 ldr r0, [r4, #16] + 1200 00a4 FFF7FEFF bl FLASH_OB_BOR_LevelConfig + 1201 .LVL93: + 1202 00a8 D7E7 b .L99 + 1203 .L109: + ARM GAS /tmp/ccM28uwG.s page 54 + + + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1204 .loc 1 509 7 view .LVU340 + 1205 00aa 626B ldr r2, [r4, #52] + 1206 00ac 216B ldr r1, [r4, #48] + 1207 00ae E06A ldr r0, [r4, #44] + 1208 00b0 FFF7FEFF bl FLASH_OB_BootAddConfig + 1209 .LVL94: + 1210 00b4 D5E7 b .L100 + 1211 .LVL95: + 1212 .L102: + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1213 .loc 1 432 12 is_stmt 0 view .LVU341 + 1214 00b6 0125 movs r5, #1 + 1215 .L93: + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1216 .loc 1 545 3 is_stmt 1 view .LVU342 + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1217 .loc 1 545 3 view .LVU343 + 1218 00b8 034B ldr r3, .L110 + 1219 00ba 0022 movs r2, #0 + 1220 00bc 1A75 strb r2, [r3, #20] + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1221 .loc 1 545 3 view .LVU344 + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1222 .loc 1 547 3 view .LVU345 + 1223 .LVL96: + 1224 .L92: + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1225 .loc 1 548 1 is_stmt 0 view .LVU346 + 1226 00be 2846 mov r0, r5 + 1227 00c0 38BD pop {r3, r4, r5, pc} + 1228 .LVL97: + 1229 .L101: + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1230 .loc 1 424 3 view .LVU347 + 1231 00c2 0225 movs r5, #2 + 1232 00c4 FBE7 b .L92 + 1233 .L111: + 1234 00c6 00BF .align 2 + 1235 .L110: + 1236 00c8 00000000 .word pFlash + 1237 .cfi_endproc + 1238 .LFE143: + 1240 .section .text.HAL_FLASHEx_OBGetConfig,"ax",%progbits + 1241 .align 1 + 1242 .global HAL_FLASHEx_OBGetConfig + 1243 .syntax unified + 1244 .thumb + 1245 .thumb_func + 1246 .fpu fpv5-d16 + 1248 HAL_FLASHEx_OBGetConfig: + 1249 .LVL98: + 1250 .LFB144: + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR); + 1251 .loc 1 560 1 is_stmt 1 view -0 + 1252 .cfi_startproc + 1253 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccM28uwG.s page 55 + + + 1254 @ frame_needed = 0, uses_anonymous_args = 0 + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR); + 1255 .loc 1 560 1 is_stmt 0 view .LVU349 + 1256 0000 10B5 push {r4, lr} + 1257 .LCFI9: + 1258 .cfi_def_cfa_offset 8 + 1259 .cfi_offset 4, -8 + 1260 .cfi_offset 14, -4 + 1261 0002 0446 mov r4, r0 + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1262 .loc 1 561 3 is_stmt 1 view .LVU350 + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1263 .loc 1 561 23 is_stmt 0 view .LVU351 + 1264 0004 1623 movs r3, #22 + 1265 0006 0360 str r3, [r0] + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1266 .loc 1 564 3 is_stmt 1 view .LVU352 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1267 .loc 1 564 23 is_stmt 0 view .LVU353 + 1268 0008 FFF7FEFF bl FLASH_OB_GetRDP + 1269 .LVL99: + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1270 .loc 1 564 21 view .LVU354 + 1271 000c E060 str r0, [r4, #12] + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1272 .loc 1 567 3 is_stmt 1 view .LVU355 + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1273 .loc 1 567 25 is_stmt 0 view .LVU356 + 1274 000e FFF7FEFF bl FLASH_OB_GetUser + 1275 .LVL100: + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1276 .loc 1 567 23 view .LVU357 + 1277 0012 A061 str r0, [r4, #24] + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1278 .loc 1 570 3 is_stmt 1 view .LVU358 + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1279 .loc 1 570 23 is_stmt 0 view .LVU359 + 1280 0014 FFF7FEFF bl FLASH_OB_GetBOR + 1281 .LVL101: + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1282 .loc 1 570 21 view .LVU360 + 1283 0018 2061 str r0, [r4, #16] + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 1284 .loc 1 575 3 is_stmt 1 view .LVU361 + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 1285 .loc 1 575 14 is_stmt 0 view .LVU362 + 1286 001a E269 ldr r2, [r4, #28] + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 1287 .loc 1 575 6 view .LVU363 + 1288 001c 012A cmp r2, #1 + 1289 001e 0AD0 beq .L115 + 1290 .L113: + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined(DUAL_CORE) + 1291 .loc 1 591 3 is_stmt 1 view .LVU364 + 1292 0020 04F13401 add r1, r4, #52 + 1293 0024 04F13000 add r0, r4, #48 + 1294 0028 FFF7FEFF bl FLASH_OB_GetBootAdd + ARM GAS /tmp/ccM28uwG.s page 56 + + + 1295 .LVL102: + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ + 1296 .loc 1 598 3 view .LVU365 + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /*DUAL_CORE*/ + 1297 .loc 1 598 23 is_stmt 0 view .LVU366 + 1298 002c 2368 ldr r3, [r4] + 1299 002e 43F04003 orr r3, r3, #64 + 1300 0032 2360 str r3, [r4] + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1301 .loc 1 621 1 view .LVU367 + 1302 0034 10BD pop {r4, pc} + 1303 .LVL103: + 1304 .L115: + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1305 .loc 1 578 5 is_stmt 1 view .LVU368 + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1306 .loc 1 578 25 is_stmt 0 view .LVU369 + 1307 0036 2368 ldr r3, [r4] + 1308 0038 43F02903 orr r3, r3, #41 + 1309 003c 2146 mov r1, r4 + 1310 003e 41F8083B str r3, [r1], #8 + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1311 .loc 1 581 5 is_stmt 1 view .LVU370 + 1312 0042 201D adds r0, r4, #4 + 1313 0044 FFF7FEFF bl FLASH_OB_GetWRP + 1314 .LVL104: + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1315 .loc 1 584 5 view .LVU371 + 1316 0048 E369 ldr r3, [r4, #28] + 1317 004a 04F12802 add r2, r4, #40 + 1318 004e 04F12401 add r1, r4, #36 + 1319 0052 04F12000 add r0, r4, #32 + 1320 0056 FFF7FEFF bl FLASH_OB_GetPCROP + 1321 .LVL105: + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1322 .loc 1 587 5 view .LVU372 + 1323 005a E369 ldr r3, [r4, #28] + 1324 005c 04F14002 add r2, r4, #64 + 1325 0060 04F13C01 add r1, r4, #60 + 1326 0064 04F13800 add r0, r4, #56 + 1327 0068 FFF7FEFF bl FLASH_OB_GetSecureArea + 1328 .LVL106: + 1329 006c D8E7 b .L113 + 1330 .cfi_endproc + 1331 .LFE144: + 1333 .section .text.HAL_FLASHEx_Unlock_Bank1,"ax",%progbits + 1334 .align 1 + 1335 .global HAL_FLASHEx_Unlock_Bank1 + 1336 .syntax unified + 1337 .thumb + 1338 .thumb_func + 1339 .fpu fpv5-d16 + 1341 HAL_FLASHEx_Unlock_Bank1: + 1342 .LFB145: + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + 1343 .loc 1 628 1 view -0 + 1344 .cfi_startproc + ARM GAS /tmp/ccM28uwG.s page 57 + + + 1345 @ args = 0, pretend = 0, frame = 0 + 1346 @ frame_needed = 0, uses_anonymous_args = 0 + 1347 @ link register save eliminated. + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1348 .loc 1 629 3 view .LVU374 + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1349 .loc 1 629 6 is_stmt 0 view .LVU375 + 1350 0000 0A4B ldr r3, .L120 + 1351 0002 DB68 ldr r3, [r3, #12] + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1352 .loc 1 629 5 view .LVU376 + 1353 0004 13F0010F tst r3, #1 + 1354 0008 0BD0 beq .L118 + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + 1355 .loc 1 632 5 is_stmt 1 view .LVU377 + 1356 000a 084B ldr r3, .L120 + 1357 000c 084A ldr r2, .L120+4 + 1358 000e 5A60 str r2, [r3, #4] + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1359 .loc 1 633 5 view .LVU378 + 1360 0010 02F18832 add r2, r2, #-2004318072 + 1361 0014 5A60 str r2, [r3, #4] + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1362 .loc 1 636 5 view .LVU379 + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1363 .loc 1 636 9 is_stmt 0 view .LVU380 + 1364 0016 DB68 ldr r3, [r3, #12] + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1365 .loc 1 636 8 view .LVU381 + 1366 0018 13F0010F tst r3, #1 + 1367 001c 03D1 bne .L119 + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1368 .loc 1 642 10 view .LVU382 + 1369 001e 0020 movs r0, #0 + 1370 0020 7047 bx lr + 1371 .L118: + 1372 0022 0020 movs r0, #0 + 1373 0024 7047 bx lr + 1374 .L119: + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1375 .loc 1 638 14 view .LVU383 + 1376 0026 0120 movs r0, #1 + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1377 .loc 1 643 1 view .LVU384 + 1378 0028 7047 bx lr + 1379 .L121: + 1380 002a 00BF .align 2 + 1381 .L120: + 1382 002c 00200052 .word 1375739904 + 1383 0030 23016745 .word 1164378403 + 1384 .cfi_endproc + 1385 .LFE145: + 1387 .section .text.HAL_FLASHEx_Lock_Bank1,"ax",%progbits + 1388 .align 1 + 1389 .global HAL_FLASHEx_Lock_Bank1 + 1390 .syntax unified + 1391 .thumb + ARM GAS /tmp/ccM28uwG.s page 58 + + + 1392 .thumb_func + 1393 .fpu fpv5-d16 + 1395 HAL_FLASHEx_Lock_Bank1: + 1396 .LFB146: + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */ + 1397 .loc 1 650 1 is_stmt 1 view -0 + 1398 .cfi_startproc + 1399 @ args = 0, pretend = 0, frame = 0 + 1400 @ frame_needed = 0, uses_anonymous_args = 0 + 1401 @ link register save eliminated. + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** return HAL_OK; + 1402 .loc 1 652 3 view .LVU386 + 1403 0000 034A ldr r2, .L123 + 1404 0002 D368 ldr r3, [r2, #12] + 1405 0004 43F00103 orr r3, r3, #1 + 1406 0008 D360 str r3, [r2, #12] + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1407 .loc 1 653 3 view .LVU387 + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1408 .loc 1 654 1 is_stmt 0 view .LVU388 + 1409 000a 0020 movs r0, #0 + 1410 000c 7047 bx lr + 1411 .L124: + 1412 000e 00BF .align 2 + 1413 .L123: + 1414 0010 00200052 .word 1375739904 + 1415 .cfi_endproc + 1416 .LFE146: + 1418 .section .text.HAL_FLASHEx_ComputeCRC,"ax",%progbits + 1419 .align 1 + 1420 .global HAL_FLASHEx_ComputeCRC + 1421 .syntax unified + 1422 .thumb + 1423 .thumb_func + 1424 .fpu fpv5-d16 + 1426 HAL_FLASHEx_ComputeCRC: + 1427 .LVL107: + 1428 .LFB147: + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1429 .loc 1 703 1 is_stmt 1 view -0 + 1430 .cfi_startproc + 1431 @ args = 0, pretend = 0, frame = 0 + 1432 @ frame_needed = 0, uses_anonymous_args = 0 + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1433 .loc 1 703 1 is_stmt 0 view .LVU390 + 1434 0000 70B5 push {r4, r5, r6, lr} + 1435 .LCFI10: + 1436 .cfi_def_cfa_offset 16 + 1437 .cfi_offset 4, -16 + 1438 .cfi_offset 5, -12 + 1439 .cfi_offset 6, -8 + 1440 .cfi_offset 14, -4 + 1441 0002 0446 mov r4, r0 + 1442 0004 0D46 mov r5, r1 + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t sector_index; + 1443 .loc 1 704 3 is_stmt 1 view .LVU391 + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + ARM GAS /tmp/ccM28uwG.s page 59 + + + 1444 .loc 1 705 3 view .LVU392 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC)); + 1445 .loc 1 708 3 view .LVU393 + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1446 .loc 1 709 3 view .LVU394 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1447 .loc 1 712 3 view .LVU395 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1448 .loc 1 712 12 is_stmt 0 view .LVU396 + 1449 0006 4CF25030 movw r0, #50000 + 1450 .LVL108: + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1451 .loc 1 712 12 view .LVU397 + 1452 000a FFF7FEFF bl FLASH_OB_WaitForLastOperation + 1453 .LVL109: + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1454 .loc 1 714 3 is_stmt 1 view .LVU398 + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1455 .loc 1 714 6 is_stmt 0 view .LVU399 + 1456 000e 10B9 cbnz r0, .L126 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1457 .loc 1 716 5 is_stmt 1 view .LVU400 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1458 .loc 1 716 17 is_stmt 0 view .LVU401 + 1459 0010 A368 ldr r3, [r4, #8] + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1460 .loc 1 716 8 view .LVU402 + 1461 0012 012B cmp r3, #1 + 1462 0014 00D0 beq .L133 + 1463 .LVL110: + 1464 .L126: + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1465 .loc 1 816 3 is_stmt 1 view .LVU403 + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1466 .loc 1 817 1 is_stmt 0 view .LVU404 + 1467 0016 70BD pop {r4, r5, r6, pc} + 1468 .LVL111: + 1469 .L133: + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1470 .loc 1 719 7 is_stmt 1 view .LVU405 + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1471 .loc 1 719 18 is_stmt 0 view .LVU406 + 1472 0018 244B ldr r3, .L135 + 1473 001a DA68 ldr r2, [r3, #12] + 1474 001c 42F40042 orr r2, r2, #32768 + 1475 0020 DA60 str r2, [r3, #12] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1476 .loc 1 722 7 is_stmt 1 view .LVU407 + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1477 .loc 1 722 19 is_stmt 0 view .LVU408 + 1478 0022 5A69 ldr r2, [r3, #20] + 1479 0024 42F0C052 orr r2, r2, #402653184 + 1480 0028 5A61 str r2, [r3, #20] + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1481 .loc 1 725 7 is_stmt 1 view .LVU409 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1482 .loc 1 725 21 is_stmt 0 view .LVU410 + ARM GAS /tmp/ccM28uwG.s page 60 + + + 1483 002a 1A6D ldr r2, [r3, #80] + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1484 .loc 1 725 56 view .LVU411 + 1485 002c 6168 ldr r1, [r4, #4] + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1486 .loc 1 725 78 view .LVU412 + 1487 002e 2068 ldr r0, [r4] + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1488 .loc 1 725 68 view .LVU413 + 1489 0030 0143 orrs r1, r1, r0 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1490 .loc 1 725 21 view .LVU414 + 1491 0032 0A43 orrs r2, r2, r1 + 1492 0034 42F40032 orr r2, r2, #131072 + 1493 0038 1A65 str r2, [r3, #80] + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1494 .loc 1 727 7 is_stmt 1 view .LVU415 + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1495 .loc 1 727 19 is_stmt 0 view .LVU416 + 1496 003a 2368 ldr r3, [r4] + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1497 .loc 1 727 10 view .LVU417 + 1498 003c B3F5807F cmp r3, #256 + 1499 0040 08D0 beq .L134 + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1500 .loc 1 738 12 is_stmt 1 view .LVU418 + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1501 .loc 1 738 15 is_stmt 0 view .LVU419 + 1502 0042 1B4A ldr r2, .L135+4 + 1503 0044 9342 cmp r3, r2 + 1504 0046 2AD1 bne .L131 + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1505 .loc 1 741 9 is_stmt 1 view .LVU420 + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1506 .loc 1 741 23 is_stmt 0 view .LVU421 + 1507 0048 184A ldr r2, .L135 + 1508 004a 136D ldr r3, [r2, #80] + 1509 004c 43F48003 orr r3, r3, #4194304 + 1510 0050 1365 str r3, [r2, #80] + 1511 0052 10E0 b .L130 + 1512 .L134: + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1513 .loc 1 730 9 is_stmt 1 view .LVU422 + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1514 .loc 1 730 23 is_stmt 0 view .LVU423 + 1515 0054 154A ldr r2, .L135 + 1516 0056 136D ldr r3, [r2, #80] + 1517 0058 43F48063 orr r3, r3, #1024 + 1518 005c 1365 str r3, [r2, #80] + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1519 .loc 1 733 9 is_stmt 1 view .LVU424 + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1520 .loc 1 733 26 is_stmt 0 view .LVU425 + 1521 005e E668 ldr r6, [r4, #12] + 1522 .LVL112: + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1523 .loc 1 733 9 view .LVU426 + ARM GAS /tmp/ccM28uwG.s page 61 + + + 1524 0060 04E0 b .L128 + 1525 .L129: + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1526 .loc 1 735 11 is_stmt 1 discriminator 3 view .LVU427 + 1527 0062 0121 movs r1, #1 + 1528 0064 3046 mov r0, r6 + 1529 0066 FFF7FEFF bl FLASH_CRC_AddSector + 1530 .LVL113: + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1531 .loc 1 733 103 discriminator 3 view .LVU428 + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1532 .loc 1 733 115 is_stmt 0 discriminator 3 view .LVU429 + 1533 006a 0136 adds r6, r6, #1 + 1534 .LVL114: + 1535 .L128: + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1536 .loc 1 733 46 is_stmt 1 discriminator 1 view .LVU430 + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1537 .loc 1 733 70 is_stmt 0 discriminator 1 view .LVU431 + 1538 006c 2369 ldr r3, [r4, #16] + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1539 .loc 1 733 92 discriminator 1 view .LVU432 + 1540 006e E268 ldr r2, [r4, #12] + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1541 .loc 1 733 82 discriminator 1 view .LVU433 + 1542 0070 1344 add r3, r3, r2 + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1543 .loc 1 733 9 discriminator 1 view .LVU434 + 1544 0072 B342 cmp r3, r6 + 1545 0074 F5D8 bhi .L129 + 1546 .LVL115: + 1547 .L130: + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1548 .loc 1 750 7 is_stmt 1 view .LVU435 + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1549 .loc 1 750 21 is_stmt 0 view .LVU436 + 1550 0076 0D4C ldr r4, .L135 + 1551 .LVL116: + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1552 .loc 1 750 21 view .LVU437 + 1553 0078 236D ldr r3, [r4, #80] + 1554 007a 43F48033 orr r3, r3, #65536 + 1555 007e 2365 str r3, [r4, #80] + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1556 .loc 1 753 7 is_stmt 1 view .LVU438 + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1557 .loc 1 753 16 is_stmt 0 view .LVU439 + 1558 0080 0121 movs r1, #1 + 1559 0082 4CF25030 movw r0, #50000 + 1560 0086 FFF7FEFF bl FLASH_CRC_WaitForLastOperation + 1561 .LVL117: + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1562 .loc 1 756 7 is_stmt 1 view .LVU440 + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1563 .loc 1 756 28 is_stmt 0 view .LVU441 + 1564 008a E36D ldr r3, [r4, #92] + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + ARM GAS /tmp/ccM28uwG.s page 62 + + + 1565 .loc 1 756 21 view .LVU442 + 1566 008c 2B60 str r3, [r5] + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1567 .loc 1 759 7 is_stmt 1 view .LVU443 + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1568 .loc 1 759 18 is_stmt 0 view .LVU444 + 1569 008e E368 ldr r3, [r4, #12] + 1570 0090 23F40043 bic r3, r3, #32768 + 1571 0094 E360 str r3, [r4, #12] + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1572 .loc 1 762 7 is_stmt 1 view .LVU445 + 1573 0096 4FF0C053 mov r3, #402653184 + 1574 009a 6361 str r3, [r4, #20] + 1575 009c BBE7 b .L126 + 1576 .LVL118: + 1577 .L131: + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1578 .loc 1 746 9 view .LVU446 + 1579 009e 0122 movs r2, #1 + 1580 00a0 A169 ldr r1, [r4, #24] + 1581 00a2 6069 ldr r0, [r4, #20] + 1582 00a4 FFF7FEFF bl FLASH_CRC_SelectAddress + 1583 .LVL119: + 1584 00a8 E5E7 b .L130 + 1585 .L136: + 1586 00aa 00BF .align 2 + 1587 .L135: + 1588 00ac 00200052 .word 1375739904 + 1589 00b0 00014000 .word 4194560 + 1590 .cfi_endproc + 1591 .LFE147: + 1593 .section .text.FLASH_Erase_Sector,"ax",%progbits + 1594 .align 1 + 1595 .global FLASH_Erase_Sector + 1596 .syntax unified + 1597 .thumb + 1598 .thumb_func + 1599 .fpu fpv5-d16 + 1601 FLASH_Erase_Sector: + 1602 .LVL120: + 1603 .LFB149: + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_SECTOR(Sector)); + 1604 .loc 1 928 1 view -0 + 1605 .cfi_startproc + 1606 @ args = 0, pretend = 0, frame = 0 + 1607 @ frame_needed = 0, uses_anonymous_args = 0 + 1608 @ link register save eliminated. + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); + 1609 .loc 1 929 3 view .LVU448 + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #if defined (FLASH_CR_PSIZE) + 1610 .loc 1 930 3 view .LVU449 + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 1611 .loc 1 932 3 view .LVU450 + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1612 .loc 1 937 3 view .LVU451 + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1613 .loc 1 937 5 is_stmt 0 view .LVU452 + ARM GAS /tmp/ccM28uwG.s page 63 + + + 1614 0000 11F0010F tst r1, #1 + 1615 0004 0BD0 beq .L137 + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1616 .loc 1 941 5 is_stmt 1 view .LVU453 + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1617 .loc 1 941 16 is_stmt 0 view .LVU454 + 1618 0006 0649 ldr r1, .L139 + 1619 .LVL121: + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1620 .loc 1 941 16 view .LVU455 + 1621 0008 CB68 ldr r3, [r1, #12] + 1622 000a 23F4E663 bic r3, r3, #1840 + 1623 000e CB60 str r3, [r1, #12] + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 1624 .loc 1 943 5 is_stmt 1 view .LVU456 + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 1625 .loc 1 943 16 is_stmt 0 view .LVU457 + 1626 0010 CB68 ldr r3, [r1, #12] + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 1627 .loc 1 943 48 view .LVU458 + 1628 0012 42EA0022 orr r2, r2, r0, lsl #8 + 1629 .LVL122: + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #else + 1630 .loc 1 943 16 view .LVU459 + 1631 0016 1A43 orrs r2, r2, r3 + 1632 0018 42F08402 orr r2, r2, #132 + 1633 001c CA60 str r2, [r1, #12] + 1634 .L137: + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1635 .loc 1 968 1 view .LVU460 + 1636 001e 7047 bx lr + 1637 .L140: + 1638 .align 2 + 1639 .L139: + 1640 0020 00200052 .word 1375739904 + 1641 .cfi_endproc + 1642 .LFE149: + 1644 .section .text.HAL_FLASHEx_Erase,"ax",%progbits + 1645 .align 1 + 1646 .global HAL_FLASHEx_Erase + 1647 .syntax unified + 1648 .thumb + 1649 .thumb_func + 1650 .fpu fpv5-d16 + 1652 HAL_FLASHEx_Erase: + 1653 .LVL123: + 1654 .LFB141: + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1655 .loc 1 179 1 is_stmt 1 view -0 + 1656 .cfi_startproc + 1657 @ args = 0, pretend = 0, frame = 0 + 1658 @ frame_needed = 0, uses_anonymous_args = 0 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1659 .loc 1 179 1 is_stmt 0 view .LVU462 + 1660 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1661 .LCFI11: + 1662 .cfi_def_cfa_offset 24 + ARM GAS /tmp/ccM28uwG.s page 64 + + + 1663 .cfi_offset 3, -24 + 1664 .cfi_offset 4, -20 + 1665 .cfi_offset 5, -16 + 1666 .cfi_offset 6, -12 + 1667 .cfi_offset 7, -8 + 1668 .cfi_offset 14, -4 + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** uint32_t sector_index; + 1669 .loc 1 180 3 is_stmt 1 view .LVU463 + 1670 .LVL124: + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1671 .loc 1 181 3 view .LVU464 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + 1672 .loc 1 184 3 view .LVU465 + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1673 .loc 1 185 3 view .LVU466 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1674 .loc 1 188 3 view .LVU467 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1675 .loc 1 188 3 view .LVU468 + 1676 0002 2E4B ldr r3, .L160 + 1677 0004 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 1678 0006 012B cmp r3, #1 + 1679 0008 56D0 beq .L151 + 1680 000a 0446 mov r4, r0 + 1681 000c 0F46 mov r7, r1 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1682 .loc 1 188 3 discriminator 2 view .LVU469 + 1683 000e 2B4B ldr r3, .L160 + 1684 0010 0122 movs r2, #1 + 1685 0012 1A75 strb r2, [r3, #20] + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1686 .loc 1 188 3 discriminator 2 view .LVU470 + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1687 .loc 1 191 3 discriminator 2 view .LVU471 + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1688 .loc 1 191 20 is_stmt 0 discriminator 2 view .LVU472 + 1689 0014 0022 movs r2, #0 + 1690 0016 9A61 str r2, [r3, #24] + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1691 .loc 1 194 3 is_stmt 1 discriminator 2 view .LVU473 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1692 .loc 1 194 17 is_stmt 0 discriminator 2 view .LVU474 + 1693 0018 4368 ldr r3, [r0, #4] + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1694 .loc 1 194 5 discriminator 2 view .LVU475 + 1695 001a 13F0010F tst r3, #1 + 1696 001e 08D1 bne .L156 + 1697 .LVL125: + 1698 .L143: + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1699 .loc 1 215 5 is_stmt 1 view .LVU476 + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1700 .loc 1 215 18 is_stmt 0 view .LVU477 + 1701 0020 2368 ldr r3, [r4] + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1702 .loc 1 215 7 view .LVU478 + 1703 0022 012B cmp r3, #1 + ARM GAS /tmp/ccM28uwG.s page 65 + + + 1704 0024 0ED0 beq .L157 + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1705 .loc 1 246 7 is_stmt 1 view .LVU479 + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1706 .loc 1 246 20 is_stmt 0 view .LVU480 + 1707 0026 4FF0FF33 mov r3, #-1 + 1708 002a 3B60 str r3, [r7] + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1709 .loc 1 249 7 is_stmt 1 view .LVU481 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1710 .loc 1 249 24 is_stmt 0 view .LVU482 + 1711 002c A568 ldr r5, [r4, #8] + 1712 .LVL126: + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1713 .loc 1 249 7 view .LVU483 + 1714 002e 0026 movs r6, #0 + 1715 0030 22E0 b .L147 + 1716 .LVL127: + 1717 .L156: + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1718 .loc 1 196 5 is_stmt 1 view .LVU484 + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1719 .loc 1 196 8 is_stmt 0 view .LVU485 + 1720 0032 0121 movs r1, #1 + 1721 .LVL128: + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1722 .loc 1 196 8 view .LVU486 + 1723 0034 4CF25030 movw r0, #50000 + 1724 .LVL129: + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1725 .loc 1 196 8 view .LVU487 + 1726 0038 FFF7FEFF bl FLASH_WaitForLastOperation + 1727 .LVL130: + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1728 .loc 1 196 7 view .LVU488 + 1729 003c 0028 cmp r0, #0 + 1730 003e EFD0 beq .L143 + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1731 .loc 1 198 14 view .LVU489 + 1732 0040 0126 movs r6, #1 + 1733 0042 34E0 b .L144 + 1734 .LVL131: + 1735 .L157: + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1736 .loc 1 218 7 is_stmt 1 view .LVU490 + 1737 0044 6168 ldr r1, [r4, #4] + 1738 0046 2069 ldr r0, [r4, #16] + 1739 0048 FFF7FEFF bl FLASH_MassErase + 1740 .LVL132: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1741 .loc 1 221 7 view .LVU491 + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1742 .loc 1 221 21 is_stmt 0 view .LVU492 + 1743 004c 6368 ldr r3, [r4, #4] + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1744 .loc 1 221 9 view .LVU493 + 1745 004e 13F0010F tst r3, #1 + ARM GAS /tmp/ccM28uwG.s page 66 + + + 1746 0052 01D1 bne .L158 + 1747 0054 0026 movs r6, #0 + 1748 0056 2AE0 b .L144 + 1749 .L158: + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1750 .loc 1 223 9 is_stmt 1 view .LVU494 + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1751 .loc 1 223 12 is_stmt 0 view .LVU495 + 1752 0058 0121 movs r1, #1 + 1753 005a 4CF25030 movw r0, #50000 + 1754 005e FFF7FEFF bl FLASH_WaitForLastOperation + 1755 .LVL133: + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1756 .loc 1 223 11 view .LVU496 + 1757 0062 0646 mov r6, r0 + 1758 0064 00B1 cbz r0, .L146 + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1759 .loc 1 225 18 view .LVU497 + 1760 0066 0126 movs r6, #1 + 1761 .L146: + 1762 .LVL134: + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1763 .loc 1 228 9 is_stmt 1 view .LVU498 + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1764 .loc 1 228 20 is_stmt 0 view .LVU499 + 1765 0068 154A ldr r2, .L160+4 + 1766 006a D368 ldr r3, [r2, #12] + 1767 006c 23F00803 bic r3, r3, #8 + 1768 0070 D360 str r3, [r2, #12] + 1769 0072 1CE0 b .L144 + 1770 .LVL135: + 1771 .L148: + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1772 .loc 1 272 9 is_stmt 1 view .LVU500 + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1773 .loc 1 272 11 is_stmt 0 view .LVU501 + 1774 0074 D6B9 cbnz r6, .L159 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1775 .loc 1 249 107 is_stmt 1 discriminator 2 view .LVU502 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1776 .loc 1 249 119 is_stmt 0 discriminator 2 view .LVU503 + 1777 0076 0135 adds r5, r5, #1 + 1778 .LVL136: + 1779 .L147: + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1780 .loc 1 249 46 is_stmt 1 discriminator 1 view .LVU504 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1781 .loc 1 249 72 is_stmt 0 discriminator 1 view .LVU505 + 1782 0078 E368 ldr r3, [r4, #12] + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1783 .loc 1 249 96 discriminator 1 view .LVU506 + 1784 007a A268 ldr r2, [r4, #8] + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1785 .loc 1 249 84 discriminator 1 view .LVU507 + 1786 007c 1344 add r3, r3, r2 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1787 .loc 1 249 7 discriminator 1 view .LVU508 + ARM GAS /tmp/ccM28uwG.s page 67 + + + 1788 007e AB42 cmp r3, r5 + 1789 0080 15D9 bls .L144 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1790 .loc 1 251 9 is_stmt 1 view .LVU509 + 1791 0082 2269 ldr r2, [r4, #16] + 1792 0084 6168 ldr r1, [r4, #4] + 1793 0086 2846 mov r0, r5 + 1794 0088 FFF7FEFF bl FLASH_Erase_Sector + 1795 .LVL137: + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1796 .loc 1 253 9 view .LVU510 + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1797 .loc 1 253 23 is_stmt 0 view .LVU511 + 1798 008c 6368 ldr r3, [r4, #4] + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1799 .loc 1 253 11 view .LVU512 + 1800 008e 13F0010F tst r3, #1 + 1801 0092 EFD0 beq .L148 + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1802 .loc 1 256 11 is_stmt 1 view .LVU513 + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1803 .loc 1 256 20 is_stmt 0 view .LVU514 + 1804 0094 0121 movs r1, #1 + 1805 0096 4CF25030 movw r0, #50000 + 1806 009a FFF7FEFF bl FLASH_WaitForLastOperation + 1807 .LVL138: + 1808 009e 0646 mov r6, r0 + 1809 .LVL139: + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1810 .loc 1 259 11 is_stmt 1 view .LVU515 + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1811 .loc 1 259 22 is_stmt 0 view .LVU516 + 1812 00a0 074A ldr r2, .L160+4 + 1813 00a2 D168 ldr r1, [r2, #12] + 1814 00a4 074B ldr r3, .L160+8 + 1815 00a6 0B40 ands r3, r3, r1 + 1816 00a8 D360 str r3, [r2, #12] + 1817 00aa E3E7 b .L148 + 1818 .L159: + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** break; + 1819 .loc 1 275 11 is_stmt 1 view .LVU517 + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** break; + 1820 .loc 1 275 24 is_stmt 0 view .LVU518 + 1821 00ac 3D60 str r5, [r7] + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1822 .loc 1 276 11 is_stmt 1 view .LVU519 + 1823 .LVL140: + 1824 .L144: + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1825 .loc 1 283 3 view .LVU520 + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1826 .loc 1 283 3 view .LVU521 + 1827 00ae 034B ldr r3, .L160 + 1828 00b0 0022 movs r2, #0 + 1829 00b2 1A75 strb r2, [r3, #20] + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1830 .loc 1 283 3 view .LVU522 + ARM GAS /tmp/ccM28uwG.s page 68 + + + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1831 .loc 1 285 3 view .LVU523 + 1832 .LVL141: + 1833 .L142: + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1834 .loc 1 286 1 is_stmt 0 view .LVU524 + 1835 00b4 3046 mov r0, r6 + 1836 00b6 F8BD pop {r3, r4, r5, r6, r7, pc} + 1837 .LVL142: + 1838 .L151: + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1839 .loc 1 188 3 view .LVU525 + 1840 00b8 0226 movs r6, #2 + 1841 00ba FBE7 b .L142 + 1842 .L161: + 1843 .align 2 + 1844 .L160: + 1845 00bc 00000000 .word pFlash + 1846 00c0 00200052 .word 1375739904 + 1847 00c4 FBF8FFFF .word -1797 + 1848 .cfi_endproc + 1849 .LFE141: + 1851 .section .text.HAL_FLASHEx_Erase_IT,"ax",%progbits + 1852 .align 1 + 1853 .global HAL_FLASHEx_Erase_IT + 1854 .syntax unified + 1855 .thumb + 1856 .thumb_func + 1857 .fpu fpv5-d16 + 1859 HAL_FLASHEx_Erase_IT: + 1860 .LVL143: + 1861 .LFB142: + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1862 .loc 1 296 1 is_stmt 1 view -0 + 1863 .cfi_startproc + 1864 @ args = 0, pretend = 0, frame = 0 + 1865 @ frame_needed = 0, uses_anonymous_args = 0 + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1866 .loc 1 297 3 view .LVU527 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + 1867 .loc 1 300 3 view .LVU528 + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1868 .loc 1 301 3 view .LVU529 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1869 .loc 1 304 3 view .LVU530 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1870 .loc 1 304 3 view .LVU531 + 1871 0000 234B ldr r3, .L176 + 1872 0002 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 1873 0004 012B cmp r3, #1 + 1874 0006 40D0 beq .L169 + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1875 .loc 1 296 1 is_stmt 0 discriminator 2 view .LVU532 + 1876 0008 10B5 push {r4, lr} + 1877 .LCFI12: + 1878 .cfi_def_cfa_offset 8 + 1879 .cfi_offset 4, -8 + ARM GAS /tmp/ccM28uwG.s page 69 + + + 1880 .cfi_offset 14, -4 + 1881 000a 0446 mov r4, r0 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1882 .loc 1 304 3 is_stmt 1 discriminator 2 view .LVU533 + 1883 000c 204B ldr r3, .L176 + 1884 000e 0122 movs r2, #1 + 1885 0010 1A75 strb r2, [r3, #20] + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1886 .loc 1 304 3 discriminator 2 view .LVU534 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1887 .loc 1 307 3 discriminator 2 view .LVU535 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1888 .loc 1 307 20 is_stmt 0 discriminator 2 view .LVU536 + 1889 0012 0022 movs r2, #0 + 1890 0014 9A61 str r2, [r3, #24] + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1891 .loc 1 310 3 is_stmt 1 discriminator 2 view .LVU537 + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1892 .loc 1 310 17 is_stmt 0 discriminator 2 view .LVU538 + 1893 0016 4368 ldr r3, [r0, #4] + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1894 .loc 1 310 5 discriminator 2 view .LVU539 + 1895 0018 13F0010F tst r3, #1 + 1896 001c 16D1 bne .L174 + 1897 .LVL144: + 1898 .L164: + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1899 .loc 1 336 5 is_stmt 1 view .LVU540 + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1900 .loc 1 336 19 is_stmt 0 view .LVU541 + 1901 001e 6368 ldr r3, [r4, #4] + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1902 .loc 1 336 7 view .LVU542 + 1903 0020 13F0010F tst r3, #1 + 1904 0024 04D0 beq .L165 + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_B + 1905 .loc 1 340 7 is_stmt 1 view .LVU543 + 1906 0026 1B4A ldr r2, .L176+4 + 1907 0028 D368 ldr r3, [r2, #12] + 1908 002a 43F4DE03 orr r3, r3, #7274496 + 1909 002e D360 str r3, [r2, #12] + 1910 .L165: + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1911 .loc 1 361 5 view .LVU544 + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1912 .loc 1 361 18 is_stmt 0 view .LVU545 + 1913 0030 2368 ldr r3, [r4] + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1914 .loc 1 361 7 view .LVU546 + 1915 0032 012B cmp r3, #1 + 1916 0034 1AD1 bne .L166 + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1917 .loc 1 364 7 is_stmt 1 view .LVU547 + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1918 .loc 1 364 20 is_stmt 0 view .LVU548 + 1919 0036 6168 ldr r1, [r4, #4] + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccM28uwG.s page 70 + + + 1920 .loc 1 364 9 view .LVU549 + 1921 0038 0129 cmp r1, #1 + 1922 003a 13D0 beq .L175 + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1923 .loc 1 376 9 is_stmt 1 view .LVU550 + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1924 .loc 1 376 33 is_stmt 0 view .LVU551 + 1925 003c 144B ldr r3, .L176 + 1926 003e 0722 movs r2, #7 + 1927 0040 1A70 strb r2, [r3] + 1928 .L168: + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1929 .loc 1 379 7 is_stmt 1 view .LVU552 + 1930 0042 2069 ldr r0, [r4, #16] + 1931 0044 FFF7FEFF bl FLASH_MassErase + 1932 .LVL145: + 1933 0048 0020 movs r0, #0 + 1934 .L163: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1935 .loc 1 407 1 is_stmt 0 view .LVU553 + 1936 004a 10BD pop {r4, pc} + 1937 .LVL146: + 1938 .L174: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1939 .loc 1 312 5 is_stmt 1 view .LVU554 + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1940 .loc 1 312 8 is_stmt 0 view .LVU555 + 1941 004c 0121 movs r1, #1 + 1942 004e 4CF25030 movw r0, #50000 + 1943 .LVL147: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1944 .loc 1 312 8 view .LVU556 + 1945 0052 FFF7FEFF bl FLASH_WaitForLastOperation + 1946 .LVL148: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1947 .loc 1 312 7 view .LVU557 + 1948 0056 0028 cmp r0, #0 + 1949 0058 E1D0 beq .L164 + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1950 .loc 1 314 7 is_stmt 1 view .LVU558 + 1951 .LVL149: + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** { + 1952 .loc 1 329 3 view .LVU559 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1953 .loc 1 332 5 view .LVU560 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1954 .loc 1 332 5 view .LVU561 + 1955 005a 0D4B ldr r3, .L176 + 1956 005c 0022 movs r2, #0 + 1957 005e 1A75 strb r2, [r3, #20] + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1958 .loc 1 332 5 view .LVU562 + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1959 .loc 1 314 14 is_stmt 0 view .LVU563 + 1960 0060 0120 movs r0, #1 + 1961 0062 F2E7 b .L163 + 1962 .LVL150: + ARM GAS /tmp/ccM28uwG.s page 71 + + + 1963 .L175: + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1964 .loc 1 366 9 is_stmt 1 view .LVU564 + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1965 .loc 1 366 33 is_stmt 0 view .LVU565 + 1966 0064 0A4B ldr r3, .L176 + 1967 0066 0222 movs r2, #2 + 1968 0068 1A70 strb r2, [r3] + 1969 006a EAE7 b .L168 + 1970 .L166: + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 1971 .loc 1 394 7 is_stmt 1 view .LVU566 + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** #endif /* DUAL_BANK */ + 1972 .loc 1 394 31 is_stmt 0 view .LVU567 + 1973 006c 084B ldr r3, .L176 + 1974 006e 0122 movs r2, #1 + 1975 0070 1A70 strb r2, [r3] + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 1976 .loc 1 397 7 is_stmt 1 view .LVU568 + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 1977 .loc 1 397 43 is_stmt 0 view .LVU569 + 1978 0072 E268 ldr r2, [r4, #12] + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 1979 .loc 1 397 31 view .LVU570 + 1980 0074 5A60 str r2, [r3, #4] + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.VoltageForErase = pEraseInit->VoltageRange; + 1981 .loc 1 398 7 is_stmt 1 view .LVU571 + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.VoltageForErase = pEraseInit->VoltageRange; + 1982 .loc 1 398 33 is_stmt 0 view .LVU572 + 1983 0076 A268 ldr r2, [r4, #8] + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** pFlash.VoltageForErase = pEraseInit->VoltageRange; + 1984 .loc 1 398 21 view .LVU573 + 1985 0078 DA60 str r2, [r3, #12] + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1986 .loc 1 399 7 is_stmt 1 view .LVU574 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1987 .loc 1 399 42 is_stmt 0 view .LVU575 + 1988 007a 2269 ldr r2, [r4, #16] + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 1989 .loc 1 399 30 view .LVU576 + 1990 007c 9A60 str r2, [r3, #8] + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** } + 1991 .loc 1 402 7 is_stmt 1 view .LVU577 + 1992 007e 6168 ldr r1, [r4, #4] + 1993 0080 A068 ldr r0, [r4, #8] + 1994 0082 FFF7FEFF bl FLASH_Erase_Sector + 1995 .LVL151: + 1996 0086 0020 movs r0, #0 + 1997 0088 DFE7 b .L163 + 1998 .LVL152: + 1999 .L169: + 2000 .LCFI13: + 2001 .cfi_def_cfa_offset 0 + 2002 .cfi_restore 4 + 2003 .cfi_restore 14 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 2004 .loc 1 304 3 is_stmt 0 view .LVU578 + ARM GAS /tmp/ccM28uwG.s page 72 + + + 2005 008a 0220 movs r0, #2 + 2006 .LVL153: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c **** + 2007 .loc 1 407 1 view .LVU579 + 2008 008c 7047 bx lr + 2009 .L177: + 2010 008e 00BF .align 2 + 2011 .L176: + 2012 0090 00000000 .word pFlash + 2013 0094 00200052 .word 1375739904 + 2014 .cfi_endproc + 2015 .LFE142: + 2017 .text + 2018 .Letext0: + 2019 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2020 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2021 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 2022 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 2023 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h" + 2024 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h" + ARM GAS /tmp/ccM28uwG.s page 73 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_flash_ex.c + /tmp/ccM28uwG.s:17 .text.FLASH_MassErase:0000000000000000 $t + /tmp/ccM28uwG.s:24 .text.FLASH_MassErase:0000000000000000 FLASH_MassErase + /tmp/ccM28uwG.s:63 .text.FLASH_MassErase:0000000000000020 $d + /tmp/ccM28uwG.s:68 .text.FLASH_OB_EnableWRP:0000000000000000 $t + /tmp/ccM28uwG.s:74 .text.FLASH_OB_EnableWRP:0000000000000000 FLASH_OB_EnableWRP + /tmp/ccM28uwG.s:104 .text.FLASH_OB_EnableWRP:0000000000000014 $d + /tmp/ccM28uwG.s:109 .text.FLASH_OB_DisableWRP:0000000000000000 $t + /tmp/ccM28uwG.s:115 .text.FLASH_OB_DisableWRP:0000000000000000 FLASH_OB_DisableWRP + /tmp/ccM28uwG.s:145 .text.FLASH_OB_DisableWRP:0000000000000014 $d + /tmp/ccM28uwG.s:150 .text.FLASH_OB_GetWRP:0000000000000000 $t + /tmp/ccM28uwG.s:156 .text.FLASH_OB_GetWRP:0000000000000000 FLASH_OB_GetWRP + /tmp/ccM28uwG.s:209 .text.FLASH_OB_GetWRP:0000000000000020 $d + /tmp/ccM28uwG.s:214 .text.FLASH_OB_RDPConfig:0000000000000000 $t + /tmp/ccM28uwG.s:220 .text.FLASH_OB_RDPConfig:0000000000000000 FLASH_OB_RDPConfig + /tmp/ccM28uwG.s:240 .text.FLASH_OB_RDPConfig:0000000000000010 $d + /tmp/ccM28uwG.s:245 .text.FLASH_OB_GetRDP:0000000000000000 $t + /tmp/ccM28uwG.s:251 .text.FLASH_OB_GetRDP:0000000000000000 FLASH_OB_GetRDP + /tmp/ccM28uwG.s:285 .text.FLASH_OB_GetRDP:000000000000001c $d + /tmp/ccM28uwG.s:290 .text.FLASH_OB_UserConfig:0000000000000000 $t + /tmp/ccM28uwG.s:296 .text.FLASH_OB_UserConfig:0000000000000000 FLASH_OB_UserConfig + /tmp/ccM28uwG.s:456 .text.FLASH_OB_UserConfig:000000000000009c $d + /tmp/ccM28uwG.s:461 .text.FLASH_OB_GetUser:0000000000000000 $t + /tmp/ccM28uwG.s:467 .text.FLASH_OB_GetUser:0000000000000000 FLASH_OB_GetUser + /tmp/ccM28uwG.s:490 .text.FLASH_OB_GetUser:000000000000000c $d + /tmp/ccM28uwG.s:496 .text.FLASH_OB_PCROPConfig:0000000000000000 $t + /tmp/ccM28uwG.s:502 .text.FLASH_OB_PCROPConfig:0000000000000000 FLASH_OB_PCROPConfig + /tmp/ccM28uwG.s:547 .text.FLASH_OB_PCROPConfig:0000000000000020 $d + /tmp/ccM28uwG.s:552 .text.FLASH_OB_GetPCROP:0000000000000000 $t + /tmp/ccM28uwG.s:558 .text.FLASH_OB_GetPCROP:0000000000000000 FLASH_OB_GetPCROP + /tmp/ccM28uwG.s:635 .text.FLASH_OB_GetPCROP:0000000000000038 $d + /tmp/ccM28uwG.s:641 .text.FLASH_OB_BOR_LevelConfig:0000000000000000 $t + /tmp/ccM28uwG.s:647 .text.FLASH_OB_BOR_LevelConfig:0000000000000000 FLASH_OB_BOR_LevelConfig + /tmp/ccM28uwG.s:667 .text.FLASH_OB_BOR_LevelConfig:0000000000000010 $d + /tmp/ccM28uwG.s:672 .text.FLASH_OB_GetBOR:0000000000000000 $t + /tmp/ccM28uwG.s:678 .text.FLASH_OB_GetBOR:0000000000000000 FLASH_OB_GetBOR + /tmp/ccM28uwG.s:695 .text.FLASH_OB_GetBOR:000000000000000c $d + /tmp/ccM28uwG.s:700 .text.FLASH_OB_BootAddConfig:0000000000000000 $t + /tmp/ccM28uwG.s:706 .text.FLASH_OB_BootAddConfig:0000000000000000 FLASH_OB_BootAddConfig + /tmp/ccM28uwG.s:760 .text.FLASH_OB_BootAddConfig:000000000000002c $d + /tmp/ccM28uwG.s:766 .text.FLASH_OB_GetBootAdd:0000000000000000 $t + /tmp/ccM28uwG.s:772 .text.FLASH_OB_GetBootAdd:0000000000000000 FLASH_OB_GetBootAdd + /tmp/ccM28uwG.s:802 .text.FLASH_OB_GetBootAdd:0000000000000010 $d + /tmp/ccM28uwG.s:808 .text.FLASH_OB_SecureAreaConfig:0000000000000000 $t + /tmp/ccM28uwG.s:814 .text.FLASH_OB_SecureAreaConfig:0000000000000000 FLASH_OB_SecureAreaConfig + /tmp/ccM28uwG.s:861 .text.FLASH_OB_SecureAreaConfig:0000000000000024 $d + /tmp/ccM28uwG.s:866 .text.FLASH_OB_GetSecureArea:0000000000000000 $t + /tmp/ccM28uwG.s:872 .text.FLASH_OB_GetSecureArea:0000000000000000 FLASH_OB_GetSecureArea + /tmp/ccM28uwG.s:949 .text.FLASH_OB_GetSecureArea:0000000000000038 $d + /tmp/ccM28uwG.s:955 .text.FLASH_CRC_AddSector:0000000000000000 $t + /tmp/ccM28uwG.s:961 .text.FLASH_CRC_AddSector:0000000000000000 FLASH_CRC_AddSector + /tmp/ccM28uwG.s:999 .text.FLASH_CRC_AddSector:000000000000001c $d + /tmp/ccM28uwG.s:1004 .text.FLASH_CRC_SelectAddress:0000000000000000 $t + /tmp/ccM28uwG.s:1010 .text.FLASH_CRC_SelectAddress:0000000000000000 FLASH_CRC_SelectAddress + /tmp/ccM28uwG.s:1040 .text.FLASH_CRC_SelectAddress:0000000000000010 $d + /tmp/ccM28uwG.s:1045 .text.HAL_FLASHEx_OBProgram:0000000000000000 $t + ARM GAS /tmp/ccM28uwG.s page 74 + + + /tmp/ccM28uwG.s:1052 .text.HAL_FLASHEx_OBProgram:0000000000000000 HAL_FLASHEx_OBProgram + /tmp/ccM28uwG.s:1236 .text.HAL_FLASHEx_OBProgram:00000000000000c8 $d + /tmp/ccM28uwG.s:1241 .text.HAL_FLASHEx_OBGetConfig:0000000000000000 $t + /tmp/ccM28uwG.s:1248 .text.HAL_FLASHEx_OBGetConfig:0000000000000000 HAL_FLASHEx_OBGetConfig + /tmp/ccM28uwG.s:1334 .text.HAL_FLASHEx_Unlock_Bank1:0000000000000000 $t + /tmp/ccM28uwG.s:1341 .text.HAL_FLASHEx_Unlock_Bank1:0000000000000000 HAL_FLASHEx_Unlock_Bank1 + /tmp/ccM28uwG.s:1382 .text.HAL_FLASHEx_Unlock_Bank1:000000000000002c $d + /tmp/ccM28uwG.s:1388 .text.HAL_FLASHEx_Lock_Bank1:0000000000000000 $t + /tmp/ccM28uwG.s:1395 .text.HAL_FLASHEx_Lock_Bank1:0000000000000000 HAL_FLASHEx_Lock_Bank1 + /tmp/ccM28uwG.s:1414 .text.HAL_FLASHEx_Lock_Bank1:0000000000000010 $d + /tmp/ccM28uwG.s:1419 .text.HAL_FLASHEx_ComputeCRC:0000000000000000 $t + /tmp/ccM28uwG.s:1426 .text.HAL_FLASHEx_ComputeCRC:0000000000000000 HAL_FLASHEx_ComputeCRC + /tmp/ccM28uwG.s:1588 .text.HAL_FLASHEx_ComputeCRC:00000000000000ac $d + /tmp/ccM28uwG.s:1594 .text.FLASH_Erase_Sector:0000000000000000 $t + /tmp/ccM28uwG.s:1601 .text.FLASH_Erase_Sector:0000000000000000 FLASH_Erase_Sector + /tmp/ccM28uwG.s:1640 .text.FLASH_Erase_Sector:0000000000000020 $d + /tmp/ccM28uwG.s:1645 .text.HAL_FLASHEx_Erase:0000000000000000 $t + /tmp/ccM28uwG.s:1652 .text.HAL_FLASHEx_Erase:0000000000000000 HAL_FLASHEx_Erase + /tmp/ccM28uwG.s:1845 .text.HAL_FLASHEx_Erase:00000000000000bc $d + /tmp/ccM28uwG.s:1852 .text.HAL_FLASHEx_Erase_IT:0000000000000000 $t + /tmp/ccM28uwG.s:1859 .text.HAL_FLASHEx_Erase_IT:0000000000000000 HAL_FLASHEx_Erase_IT + /tmp/ccM28uwG.s:2012 .text.HAL_FLASHEx_Erase_IT:0000000000000090 $d + +UNDEFINED SYMBOLS +FLASH_WaitForLastOperation +pFlash +FLASH_OB_WaitForLastOperation +FLASH_CRC_WaitForLastOperation diff --git a/build/stm32h7xx_hal_flash_ex.o b/build/stm32h7xx_hal_flash_ex.o new file mode 100644 index 0000000..36a1451 Binary files /dev/null and b/build/stm32h7xx_hal_flash_ex.o differ diff --git a/build/stm32h7xx_hal_gpio.d b/build/stm32h7xx_hal_gpio.d new file mode 100644 index 0000000..5e1664c --- /dev/null +++ b/build/stm32h7xx_hal_gpio.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_gpio.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_gpio.lst b/build/stm32h7xx_hal_gpio.lst new file mode 100644 index 0000000..2575310 --- /dev/null +++ b/build/stm32h7xx_hal_gpio.lst @@ -0,0 +1,1812 @@ +ARM GAS /tmp/ccBkqRtU.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_gpio.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_GPIO_Init,"ax",%progbits + 17 .align 1 + 18 .global HAL_GPIO_Init + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_GPIO_Init: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @file stm32h7xx_hal_gpio.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief GPIO HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * functionalities of the General Purpose Input/Output (GPIO) peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + IO operation functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** @verbatim + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ##### GPIO Peripheral features ##### + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** [..] + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** configured by software in several modes: + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Input mode + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Analog mode + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Output mode + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Alternate function mode + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) External interrupt/event lines + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (+) During and just after reset, the alternate functions and external interrupt + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** lines are not active and the I/O ports are configured in input floating mode. + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** activated or not. + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + ARM GAS /tmp/ccBkqRtU.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** type and the IO speed can be selected depending on the VDD value. + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** multiplexer that allows only one peripheral alternate function (AF) connected + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** to an IO pin at a time. In this way, there can be no conflict between peripherals + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** sharing the same IO pin. + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (+) All ports have external interrupt/event capability. To use external interrupt + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** lines, the port must be configured in input mode. All available GPIO pins are + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** The external interrupt/event controller consists of up to 23 edge detectors + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (16 lines are connected to GPIO) for generating event/interrupt requests (each + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** input line can be independently configured to select the type (interrupt or event) + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** and the corresponding trigger event (rising or falling or both). Each line can + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** also be masked independently. + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ##### How to use this driver ##### + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ============================================================================== + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** [..] + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** structure. + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) In case of Output or alternate function mode selection: the speed is + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** configured through "Speed" member from GPIO_InitTypeDef structure. + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) In alternate mode is selection, the alternate function connected to the IO + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** is configured through "Alternate" member from GPIO_InitTypeDef structure. + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) Analog mode is required when a pin is to be used as ADC channel + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** or DAC output. + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (++) In case of external interrupt/event selection the "Mode" member from + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIO_InitTypeDef structure select the type (interrupt or event) and + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** the corresponding trigger event (rising or falling or both). + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** HAL_NVIC_EnableIRQ(). + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) To set/reset the level of a pin configured in output mode use + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) During and just after reset, the alternate functions are not + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** active and the GPIO pins are configured in input floating mode (except JTAG + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** pins). + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** priority over the GPIO function. + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + ARM GAS /tmp/ccBkqRtU.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** The HSE has priority over the GPIO function. + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** @endverbatim + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ****************************************************************************** + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @attention + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * All rights reserved.

+ 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This software component is licensed by ST under BSD 3-Clause license, + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * the "License"; You may not use this file except in compliance with the + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * License. You may obtain a copy of the License at: + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * opensource.org/licenses/BSD-3-Clause + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ****************************************************************************** + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #include "stm32h7xx_hal.h" + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** @addtogroup STM32H7xx_HAL_Driver + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @{ + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** @defgroup GPIO GPIO + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief GPIO HAL module driver + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @{ + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/ + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Private defines ------------------------------------------------------------*/ + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants GPIO Private Constants + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @{ + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define GPIO_MODE (0x00000003U) + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define ANALOG_MODE (0x00000008U) + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define EXTI_MODE (0x10000000U) + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define GPIO_MODE_IT (0x00010000U) + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define GPIO_MODE_EVT (0x00020000U) + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define RISING_EDGE (0x00100000U) + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define FALLING_EDGE (0x00200000U) + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define GPIO_OUTPUT_TYPE (0x00000010U) + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #if defined(DUAL_CORE) + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define EXTI_CPU1 (0x01000000U) + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define EXTI_CPU2 (0x02000000U) + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #endif /*DUAL_CORE*/ + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #define GPIO_NUMBER (16U) + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @} + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Private macro -------------------------------------------------------------*/ + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + ARM GAS /tmp/ccBkqRtU.s page 4 + + + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Private functions ---------------------------------------------------------*/ + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions GPIO Exported Functions + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @{ + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Initialization and Configuration functions + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** @verbatim + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** =============================================================================== + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ##### Initialization and de-initialization functions ##### + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** =============================================================================== + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** [..] + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** This section provides functions allowing to initialize and de-initialize the GPIOs + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** to be ready for use. + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** @endverbatim + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @{ + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * the configuration information for the specified GPIO peripheral. + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 29 .loc 1 174 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 174 1 is_stmt 0 view .LVU1 + 34 0000 F0B5 push {r4, r5, r6, r7, lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 20 + 37 .cfi_offset 4, -20 + 38 .cfi_offset 5, -16 + 39 .cfi_offset 6, -12 + 40 .cfi_offset 7, -8 + 41 .cfi_offset 14, -4 + 42 0002 83B0 sub sp, sp, #12 + 43 .LCFI1: + 44 .cfi_def_cfa_offset 32 + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t position = 0x00U; + 45 .loc 1 175 3 is_stmt 1 view .LVU2 + 46 .LVL1: + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t iocurrent; + 47 .loc 1 176 3 view .LVU3 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t temp; + 48 .loc 1 177 3 view .LVU4 + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_Core_TypeDef *EXTI_CurrentCPU; + 49 .loc 1 178 3 view .LVU5 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + ARM GAS /tmp/ccBkqRtU.s page 5 + + + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #else + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ + 50 .loc 1 183 3 view .LVU6 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #endif + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the parameters */ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 51 .loc 1 187 3 view .LVU7 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + 52 .loc 1 188 3 view .LVU8 + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + 53 .loc 1 189 3 view .LVU9 + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 54 .loc 1 190 3 view .LVU10 + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the port pins */ + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** while (((GPIO_Init->Pin) >> position) != 0x00U) + 55 .loc 1 193 3 view .LVU11 + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t iocurrent; + 56 .loc 1 175 12 is_stmt 0 view .LVU12 + 57 0004 0023 movs r3, #0 + 58 .loc 1 193 9 view .LVU13 + 59 0006 40E0 b .L2 + 60 .LVL2: + 61 .L25: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Get current io position */ + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** iocurrent = (GPIO_Init->Pin) & (1UL << position); + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (iocurrent != 0x00U) + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* In case of Output or Alternate function mode selection */ + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the Speed parameter */ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the IO Speed */ + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = GPIOx->OSPEEDR; + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the IO Output Type */ + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = GPIOx->OTYPER; + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT0 << position) ; + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Activate the Pull-up or Pull down resistor for the current IO */ + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = GPIOx->PUPDR; + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + ARM GAS /tmp/ccBkqRtU.s page 6 + + + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* In case of Alternate function mode selection */ + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the Alternate function parameters */ + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure Alternate function mapped with the current IO */ + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = GPIOx->AFR[position >> 3U]; + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = GPIOx->MODER; + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER = temp; + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /*--------------------- EXTI Mode Configuration ------------------------*/ + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Enable SYSCFG Clock */ + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = SYSCFG->EXTICR[position >> 2U]; + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0x0FUL << (4U * (position & 0x03U))); + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 62 .loc 1 255 18 view .LVU14 + 63 0008 0924 movs r4, #9 + 64 000a 00E0 b .L7 + 65 .L13: + 66 000c 0024 movs r4, #0 + 67 .L7: + 68 .loc 1 255 40 discriminator 40 view .LVU15 + 69 000e B440 lsls r4, r4, r6 + 70 .loc 1 255 14 discriminator 40 view .LVU16 + 71 0010 44EA0C04 orr r4, r4, ip + 72 .LVL3: + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 73 .loc 1 256 9 is_stmt 1 discriminator 40 view .LVU17 + 74 .loc 1 256 40 is_stmt 0 discriminator 40 view .LVU18 + 75 0014 0235 adds r5, r5, #2 + 76 0016 764E ldr r6, .L26 + 77 0018 46F82540 str r4, [r6, r5, lsl #2] + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = EXTI_CurrentCPU->IMR1; + 78 .loc 1 259 9 is_stmt 1 discriminator 40 view .LVU19 + 79 .loc 1 259 14 is_stmt 0 discriminator 40 view .LVU20 + 80 001c 4FF0B044 mov r4, #1476395008 + 81 .LVL4: + 82 .loc 1 259 14 discriminator 40 view .LVU21 + 83 0020 D4F88050 ldr r5, [r4, #128] + ARM GAS /tmp/ccBkqRtU.s page 7 + + + 84 .LVL5: + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(iocurrent); + 85 .loc 1 260 9 is_stmt 1 discriminator 40 view .LVU22 + 86 .loc 1 260 17 is_stmt 0 discriminator 40 view .LVU23 + 87 0024 D443 mvns r4, r2 + 88 .loc 1 260 14 discriminator 40 view .LVU24 + 89 0026 25EA0206 bic r6, r5, r2 + 90 .LVL6: + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 91 .loc 1 261 9 is_stmt 1 discriminator 40 view .LVU25 + 92 .loc 1 261 23 is_stmt 0 discriminator 40 view .LVU26 + 93 002a 4F68 ldr r7, [r1, #4] + 94 .loc 1 261 12 discriminator 40 view .LVU27 + 95 002c 17F4803F tst r7, #65536 + 96 0030 01D0 beq .L8 + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= iocurrent; + 97 .loc 1 263 11 is_stmt 1 view .LVU28 + 98 .loc 1 263 16 is_stmt 0 view .LVU29 + 99 0032 42EA0506 orr r6, r2, r5 + 100 .LVL7: + 101 .L8: + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->IMR1 = temp; + 102 .loc 1 265 9 is_stmt 1 view .LVU30 + 103 .loc 1 265 31 is_stmt 0 view .LVU31 + 104 0036 4FF0B045 mov r5, #1476395008 + 105 003a C5F88060 str r6, [r5, #128] + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = EXTI_CurrentCPU->EMR1; + 106 .loc 1 267 9 is_stmt 1 view .LVU32 + 107 .loc 1 267 14 is_stmt 0 view .LVU33 + 108 003e D5F88450 ldr r5, [r5, #132] + 109 .LVL8: + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(iocurrent); + 110 .loc 1 268 9 is_stmt 1 view .LVU34 + 111 .loc 1 268 14 is_stmt 0 view .LVU35 + 112 0042 04EA0506 and r6, r4, r5 + 113 .LVL9: + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 114 .loc 1 269 9 is_stmt 1 view .LVU36 + 115 .loc 1 269 23 is_stmt 0 view .LVU37 + 116 0046 4F68 ldr r7, [r1, #4] + 117 .loc 1 269 12 view .LVU38 + 118 0048 17F4003F tst r7, #131072 + 119 004c 01D0 beq .L9 + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= iocurrent; + 120 .loc 1 271 11 is_stmt 1 view .LVU39 + 121 .loc 1 271 16 is_stmt 0 view .LVU40 + 122 004e 42EA0506 orr r6, r2, r5 + 123 .LVL10: + 124 .L9: + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->EMR1 = temp; + 125 .loc 1 273 9 is_stmt 1 view .LVU41 + 126 .loc 1 273 31 is_stmt 0 view .LVU42 + ARM GAS /tmp/ccBkqRtU.s page 8 + + + 127 0052 4FF0B045 mov r5, #1476395008 + 128 0056 C5F88460 str r6, [r5, #132] + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = EXTI->RTSR1; + 129 .loc 1 276 9 is_stmt 1 view .LVU43 + 130 .loc 1 276 14 is_stmt 0 view .LVU44 + 131 005a 2D68 ldr r5, [r5] + 132 .LVL11: + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(iocurrent); + 133 .loc 1 277 9 is_stmt 1 view .LVU45 + 134 .loc 1 277 14 is_stmt 0 view .LVU46 + 135 005c 04EA0506 and r6, r4, r5 + 136 .LVL12: + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 137 .loc 1 278 9 is_stmt 1 view .LVU47 + 138 .loc 1 278 23 is_stmt 0 view .LVU48 + 139 0060 4F68 ldr r7, [r1, #4] + 140 .loc 1 278 12 view .LVU49 + 141 0062 17F4801F tst r7, #1048576 + 142 0066 01D0 beq .L10 + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= iocurrent; + 143 .loc 1 280 11 is_stmt 1 view .LVU50 + 144 .loc 1 280 16 is_stmt 0 view .LVU51 + 145 0068 42EA0506 orr r6, r2, r5 + 146 .LVL13: + 147 .L10: + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI->RTSR1 = temp; + 148 .loc 1 282 9 is_stmt 1 view .LVU52 + 149 .loc 1 282 21 is_stmt 0 view .LVU53 + 150 006c 4FF0B045 mov r5, #1476395008 + 151 0070 2E60 str r6, [r5] + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp = EXTI->FTSR1; + 152 .loc 1 284 9 is_stmt 1 view .LVU54 + 153 .loc 1 284 14 is_stmt 0 view .LVU55 + 154 0072 6D68 ldr r5, [r5, #4] + 155 .LVL14: + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(iocurrent); + 156 .loc 1 285 9 is_stmt 1 view .LVU56 + 157 .loc 1 285 14 is_stmt 0 view .LVU57 + 158 0074 2C40 ands r4, r4, r5 + 159 .LVL15: + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 160 .loc 1 286 9 is_stmt 1 view .LVU58 + 161 .loc 1 286 23 is_stmt 0 view .LVU59 + 162 0076 4E68 ldr r6, [r1, #4] + 163 .loc 1 286 12 view .LVU60 + 164 0078 16F4001F tst r6, #2097152 + 165 007c 01D0 beq .L11 + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= iocurrent; + 166 .loc 1 288 11 is_stmt 1 view .LVU61 + 167 .loc 1 288 16 is_stmt 0 view .LVU62 + 168 007e 42EA0504 orr r4, r2, r5 + ARM GAS /tmp/ccBkqRtU.s page 9 + + + 169 .LVL16: + 170 .L11: + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI->FTSR1 = temp; + 171 .loc 1 290 9 is_stmt 1 view .LVU63 + 172 .loc 1 290 21 is_stmt 0 view .LVU64 + 173 0082 4FF0B042 mov r2, #1476395008 + 174 .LVL17: + 175 .loc 1 290 21 view .LVU65 + 176 0086 5460 str r4, [r2, #4] + 177 .LVL18: + 178 .L3: + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** position++; + 179 .loc 1 294 5 is_stmt 1 view .LVU66 + 180 .loc 1 294 13 is_stmt 0 view .LVU67 + 181 0088 0133 adds r3, r3, #1 + 182 .LVL19: + 183 .L2: + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 184 .loc 1 193 9 is_stmt 1 view .LVU68 + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 185 .loc 1 193 21 is_stmt 0 view .LVU69 + 186 008a 0A68 ldr r2, [r1] + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 187 .loc 1 193 9 view .LVU70 + 188 008c 32FA03F4 lsrs r4, r2, r3 + 189 0090 00F0AB80 beq .L24 + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 190 .loc 1 196 5 is_stmt 1 view .LVU71 + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 191 .loc 1 196 41 is_stmt 0 view .LVU72 + 192 0094 4FF0010C mov ip, #1 + 193 0098 0CFA03FC lsl ip, ip, r3 + 194 .LVL20: + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 195 .loc 1 198 5 is_stmt 1 view .LVU73 + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 196 .loc 1 198 8 is_stmt 0 view .LVU74 + 197 009c 1CEA0202 ands r2, ip, r2 + 198 .LVL21: + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 199 .loc 1 198 8 view .LVU75 + 200 00a0 F2D0 beq .L3 + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 201 .loc 1 202 7 is_stmt 1 view .LVU76 + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 202 .loc 1 202 21 is_stmt 0 view .LVU77 + 203 00a2 4C68 ldr r4, [r1, #4] + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 204 .loc 1 202 92 view .LVU78 + 205 00a4 651E subs r5, r4, #1 + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 206 .loc 1 202 10 view .LVU79 + 207 00a6 112C cmp r4, #17 + ARM GAS /tmp/ccBkqRtU.s page 10 + + + 208 00a8 18BF it ne + 209 00aa 012D cmpne r5, #1 + 210 00ac 01D9 bls .L4 + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 211 .loc 1 203 52 view .LVU80 + 212 00ae 122C cmp r4, #18 + 213 00b0 13D1 bne .L5 + 214 .L4: + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the IO Speed */ + 215 .loc 1 206 9 is_stmt 1 view .LVU81 + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 216 .loc 1 208 9 view .LVU82 + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 217 .loc 1 208 14 is_stmt 0 view .LVU83 + 218 00b2 8568 ldr r5, [r0, #8] + 219 .LVL22: + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 220 .loc 1 209 9 is_stmt 1 view .LVU84 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 221 .loc 1 209 53 is_stmt 0 view .LVU85 + 222 00b4 5E00 lsls r6, r3, #1 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 223 .loc 1 209 40 view .LVU86 + 224 00b6 0324 movs r4, #3 + 225 00b8 B440 lsls r4, r4, r6 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2U)); + 226 .loc 1 209 14 view .LVU87 + 227 00ba 25EA0405 bic r5, r5, r4 + 228 .LVL23: + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 229 .loc 1 210 9 is_stmt 1 view .LVU88 + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 230 .loc 1 210 27 is_stmt 0 view .LVU89 + 231 00be CC68 ldr r4, [r1, #12] + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 232 .loc 1 210 35 view .LVU90 + 233 00c0 B440 lsls r4, r4, r6 + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 234 .loc 1 210 14 view .LVU91 + 235 00c2 2C43 orrs r4, r4, r5 + 236 .LVL24: + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 237 .loc 1 211 9 is_stmt 1 view .LVU92 + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 238 .loc 1 211 24 is_stmt 0 view .LVU93 + 239 00c4 8460 str r4, [r0, #8] + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT0 << position) ; + 240 .loc 1 214 9 is_stmt 1 view .LVU94 + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT0 << position) ; + 241 .loc 1 214 14 is_stmt 0 view .LVU95 + 242 00c6 4468 ldr r4, [r0, #4] + 243 .LVL25: + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 244 .loc 1 215 9 is_stmt 1 view .LVU96 + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 245 .loc 1 215 14 is_stmt 0 view .LVU97 + 246 00c8 24EA0C0C bic ip, r4, ip + ARM GAS /tmp/ccBkqRtU.s page 11 + + + 247 .LVL26: + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 248 .loc 1 216 9 is_stmt 1 view .LVU98 + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 249 .loc 1 216 29 is_stmt 0 view .LVU99 + 250 00cc 4C68 ldr r4, [r1, #4] + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 251 .loc 1 216 56 view .LVU100 + 252 00ce C4F30014 ubfx r4, r4, #4, #1 + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 253 .loc 1 216 63 view .LVU101 + 254 00d2 9C40 lsls r4, r4, r3 + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 255 .loc 1 216 14 view .LVU102 + 256 00d4 44EA0C04 orr r4, r4, ip + 257 .LVL27: + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 258 .loc 1 217 9 is_stmt 1 view .LVU103 + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 259 .loc 1 217 23 is_stmt 0 view .LVU104 + 260 00d8 4460 str r4, [r0, #4] + 261 .LVL28: + 262 .L5: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 263 .loc 1 221 7 is_stmt 1 view .LVU105 + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 264 .loc 1 221 12 is_stmt 0 view .LVU106 + 265 00da C668 ldr r6, [r0, #12] + 266 .LVL29: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 267 .loc 1 222 7 is_stmt 1 view .LVU107 + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 268 .loc 1 222 47 is_stmt 0 view .LVU108 + 269 00dc 4FEA430C lsl ip, r3, #1 + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 270 .loc 1 222 34 view .LVU109 + 271 00e0 0325 movs r5, #3 + 272 00e2 05FA0CF5 lsl r5, r5, ip + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 273 .loc 1 222 15 view .LVU110 + 274 00e6 EC43 mvns r4, r5 + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2U)); + 275 .loc 1 222 12 view .LVU111 + 276 00e8 26EA050E bic lr, r6, r5 + 277 .LVL30: + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 278 .loc 1 223 7 is_stmt 1 view .LVU112 + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 279 .loc 1 223 26 is_stmt 0 view .LVU113 + 280 00ec 8D68 ldr r5, [r1, #8] + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 281 .loc 1 223 34 view .LVU114 + 282 00ee 05FA0CF5 lsl r5, r5, ip + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 283 .loc 1 223 12 view .LVU115 + 284 00f2 45EA0E05 orr r5, r5, lr + 285 .LVL31: + ARM GAS /tmp/ccBkqRtU.s page 12 + + + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 286 .loc 1 224 7 is_stmt 1 view .LVU116 + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 287 .loc 1 224 20 is_stmt 0 view .LVU117 + 288 00f6 C560 str r5, [r0, #12] + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 289 .loc 1 227 7 is_stmt 1 view .LVU118 + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 290 .loc 1 227 21 is_stmt 0 view .LVU119 + 291 00f8 4D68 ldr r5, [r1, #4] + 292 .LVL32: + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 293 .loc 1 227 10 view .LVU120 + 294 00fa 122D cmp r5, #18 + 295 00fc 18BF it ne + 296 00fe 022D cmpne r5, #2 + 297 0100 12D1 bne .L6 + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 298 .loc 1 230 9 is_stmt 1 view .LVU121 + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 299 .loc 1 231 9 view .LVU122 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 300 .loc 1 234 9 view .LVU123 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 301 .loc 1 234 36 is_stmt 0 view .LVU124 + 302 0102 DE08 lsrs r6, r3, #3 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 303 .loc 1 234 14 view .LVU125 + 304 0104 0836 adds r6, r6, #8 + 305 0106 50F82670 ldr r7, [r0, r6, lsl #2] + 306 .LVL33: + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 307 .loc 1 235 9 is_stmt 1 view .LVU126 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 308 .loc 1 235 38 is_stmt 0 view .LVU127 + 309 010a 03F00705 and r5, r3, #7 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 310 .loc 1 235 47 view .LVU128 + 311 010e 4FEA850E lsl lr, r5, #2 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 312 .loc 1 235 24 view .LVU129 + 313 0112 0F25 movs r5, #15 + 314 0114 05FA0EF5 lsl r5, r5, lr + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 315 .loc 1 235 14 view .LVU130 + 316 0118 27EA0507 bic r7, r7, r5 + 317 .LVL34: + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 318 .loc 1 236 9 is_stmt 1 view .LVU131 + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 319 .loc 1 236 28 is_stmt 0 view .LVU132 + 320 011c 0D69 ldr r5, [r1, #16] + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 321 .loc 1 236 41 view .LVU133 + 322 011e 05FA0EF5 lsl r5, r5, lr + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] = temp; + 323 .loc 1 236 14 view .LVU134 + ARM GAS /tmp/ccBkqRtU.s page 13 + + + 324 0122 3D43 orrs r5, r5, r7 + 325 .LVL35: + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 326 .loc 1 237 9 is_stmt 1 view .LVU135 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 327 .loc 1 237 36 is_stmt 0 view .LVU136 + 328 0124 40F82650 str r5, [r0, r6, lsl #2] + 329 .LVL36: + 330 .L6: + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 331 .loc 1 241 7 is_stmt 1 view .LVU137 + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 332 .loc 1 241 12 is_stmt 0 view .LVU138 + 333 0128 0568 ldr r5, [r0] + 334 .LVL37: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 335 .loc 1 242 7 is_stmt 1 view .LVU139 + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 336 .loc 1 242 12 is_stmt 0 view .LVU140 + 337 012a 2540 ands r5, r5, r4 + 338 .LVL38: + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER = temp; + 339 .loc 1 243 7 is_stmt 1 view .LVU141 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER = temp; + 340 .loc 1 243 26 is_stmt 0 view .LVU142 + 341 012c 4C68 ldr r4, [r1, #4] + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER = temp; + 342 .loc 1 243 33 view .LVU143 + 343 012e 04F00304 and r4, r4, #3 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER = temp; + 344 .loc 1 243 46 view .LVU144 + 345 0132 04FA0CF4 lsl r4, r4, ip + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER = temp; + 346 .loc 1 243 12 view .LVU145 + 347 0136 2C43 orrs r4, r4, r5 + 348 .LVL39: + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 349 .loc 1 244 7 is_stmt 1 view .LVU146 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 350 .loc 1 244 20 is_stmt 0 view .LVU147 + 351 0138 0460 str r4, [r0] + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 352 .loc 1 248 7 is_stmt 1 view .LVU148 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 353 .loc 1 248 21 is_stmt 0 view .LVU149 + 354 013a 4C68 ldr r4, [r1, #4] + 355 .LVL40: + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 356 .loc 1 248 10 view .LVU150 + 357 013c 14F0805F tst r4, #268435456 + 358 0140 A2D0 beq .L3 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 359 .loc 1 251 9 is_stmt 1 view .LVU151 + 360 .LBB2: + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 361 .loc 1 251 9 view .LVU152 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + ARM GAS /tmp/ccBkqRtU.s page 14 + + + 362 .loc 1 251 9 view .LVU153 + 363 0142 2C4C ldr r4, .L26+4 + 364 0144 D4F8F450 ldr r5, [r4, #244] + 365 0148 45F00205 orr r5, r5, #2 + 366 014c C4F8F450 str r5, [r4, #244] + 367 .LVL41: + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 368 .loc 1 251 9 view .LVU154 + 369 0150 D4F8F440 ldr r4, [r4, #244] + 370 0154 04F00204 and r4, r4, #2 + 371 0158 0194 str r4, [sp, #4] + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 372 .loc 1 251 9 view .LVU155 + 373 015a 019C ldr r4, [sp, #4] + 374 .LBE2: + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 375 .loc 1 251 9 view .LVU156 + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0x0FUL << (4U * (position & 0x03U))); + 376 .loc 1 253 9 view .LVU157 + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0x0FUL << (4U * (position & 0x03U))); + 377 .loc 1 253 40 is_stmt 0 view .LVU158 + 378 015c 9D08 lsrs r5, r3, #2 + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp &= ~(0x0FUL << (4U * (position & 0x03U))); + 379 .loc 1 253 14 view .LVU159 + 380 015e AE1C adds r6, r5, #2 + 381 0160 234C ldr r4, .L26 + 382 0162 54F82670 ldr r7, [r4, r6, lsl #2] + 383 .LVL42: + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 384 .loc 1 254 9 is_stmt 1 view .LVU160 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 385 .loc 1 254 45 is_stmt 0 view .LVU161 + 386 0166 03F00304 and r4, r3, #3 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 387 .loc 1 254 33 view .LVU162 + 388 016a A600 lsls r6, r4, #2 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 389 .loc 1 254 26 view .LVU163 + 390 016c 0F24 movs r4, #15 + 391 016e B440 lsls r4, r4, r6 + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 392 .loc 1 254 14 view .LVU164 + 393 0170 27EA040C bic ip, r7, r4 + 394 .LVL43: + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 395 .loc 1 255 9 is_stmt 1 view .LVU165 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 396 .loc 1 255 18 is_stmt 0 view .LVU166 + 397 0174 204C ldr r4, .L26+8 + 398 0176 A042 cmp r0, r4 + 399 0178 3FF448AF beq .L13 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 400 .loc 1 255 18 discriminator 1 view .LVU167 + 401 017c 04F58064 add r4, r4, #1024 + 402 0180 A042 cmp r0, r4 + 403 0182 22D0 beq .L14 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + ARM GAS /tmp/ccBkqRtU.s page 15 + + + 404 .loc 1 255 18 discriminator 3 view .LVU168 + 405 0184 04F58064 add r4, r4, #1024 + 406 0188 A042 cmp r0, r4 + 407 018a 20D0 beq .L15 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 408 .loc 1 255 18 discriminator 5 view .LVU169 + 409 018c 04F58064 add r4, r4, #1024 + 410 0190 A042 cmp r0, r4 + 411 0192 1ED0 beq .L16 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 412 .loc 1 255 18 discriminator 7 view .LVU170 + 413 0194 04F58064 add r4, r4, #1024 + 414 0198 A042 cmp r0, r4 + 415 019a 1CD0 beq .L17 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 416 .loc 1 255 18 discriminator 9 view .LVU171 + 417 019c 04F58064 add r4, r4, #1024 + 418 01a0 A042 cmp r0, r4 + 419 01a2 1AD0 beq .L18 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 420 .loc 1 255 18 discriminator 11 view .LVU172 + 421 01a4 04F58064 add r4, r4, #1024 + 422 01a8 A042 cmp r0, r4 + 423 01aa 18D0 beq .L19 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 424 .loc 1 255 18 discriminator 13 view .LVU173 + 425 01ac 04F58064 add r4, r4, #1024 + 426 01b0 A042 cmp r0, r4 + 427 01b2 16D0 beq .L20 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 428 .loc 1 255 18 discriminator 15 view .LVU174 + 429 01b4 04F58064 add r4, r4, #1024 + 430 01b8 A042 cmp r0, r4 + 431 01ba 14D0 beq .L21 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 432 .loc 1 255 18 discriminator 17 view .LVU175 + 433 01bc 04F58064 add r4, r4, #1024 + 434 01c0 A042 cmp r0, r4 + 435 01c2 3FF421AF beq .L25 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] = temp; + 436 .loc 1 255 18 view .LVU176 + 437 01c6 0A24 movs r4, #10 + 438 01c8 21E7 b .L7 + 439 .L14: + 440 01ca 0124 movs r4, #1 + 441 01cc 1FE7 b .L7 + 442 .L15: + 443 01ce 0224 movs r4, #2 + 444 01d0 1DE7 b .L7 + 445 .L16: + 446 01d2 0324 movs r4, #3 + 447 01d4 1BE7 b .L7 + 448 .L17: + 449 01d6 0424 movs r4, #4 + 450 01d8 19E7 b .L7 + 451 .L18: + 452 01da 0524 movs r4, #5 + ARM GAS /tmp/ccBkqRtU.s page 16 + + + 453 01dc 17E7 b .L7 + 454 .L19: + 455 01de 0624 movs r4, #6 + 456 01e0 15E7 b .L7 + 457 .L20: + 458 01e2 0724 movs r4, #7 + 459 01e4 13E7 b .L7 + 460 .L21: + 461 01e6 0824 movs r4, #8 + 462 01e8 11E7 b .L7 + 463 .LVL44: + 464 .L24: + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 465 .loc 1 296 1 view .LVU177 + 466 01ea 03B0 add sp, sp, #12 + 467 .LCFI2: + 468 .cfi_def_cfa_offset 20 + 469 @ sp needed + 470 01ec F0BD pop {r4, r5, r6, r7, pc} + 471 .L27: + 472 01ee 00BF .align 2 + 473 .L26: + 474 01f0 00040058 .word 1476396032 + 475 01f4 00440258 .word 1476543488 + 476 01f8 00000258 .word 1476526080 + 477 .cfi_endproc + 478 .LFE141: + 480 .section .text.HAL_GPIO_DeInit,"ax",%progbits + 481 .align 1 + 482 .global HAL_GPIO_DeInit + 483 .syntax unified + 484 .thumb + 485 .thumb_func + 486 .fpu fpv5-d16 + 488 HAL_GPIO_DeInit: + 489 .LVL45: + 490 .LFB142: + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief De-initializes the GPIOx peripheral registers to their default reset values. + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 491 .loc 1 306 1 is_stmt 1 view -0 + 492 .cfi_startproc + 493 @ args = 0, pretend = 0, frame = 0 + 494 @ frame_needed = 0, uses_anonymous_args = 0 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t position = 0x00U; + 495 .loc 1 307 3 view .LVU179 + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t iocurrent; + 496 .loc 1 308 3 view .LVU180 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t tmp; + ARM GAS /tmp/ccBkqRtU.s page 17 + + + 497 .loc 1 309 3 view .LVU181 + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_Core_TypeDef *EXTI_CurrentCPU; + 498 .loc 1 310 3 view .LVU182 + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #else + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ + 499 .loc 1 315 3 view .LVU183 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #endif + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the parameters */ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 500 .loc 1 319 3 view .LVU184 + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 501 .loc 1 320 3 view .LVU185 + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the port pins */ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** while ((GPIO_Pin >> position) != 0x00U) + 502 .loc 1 323 3 view .LVU186 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t iocurrent; + 503 .loc 1 307 12 is_stmt 0 view .LVU187 + 504 0000 0023 movs r3, #0 + 505 .LVL46: + 506 .loc 1 323 9 is_stmt 1 view .LVU188 + 507 0002 31FA03F2 lsrs r2, r1, r3 + 508 0006 00F09D80 beq .L47 + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** uint32_t position = 0x00U; + 509 .loc 1 306 1 is_stmt 0 view .LVU189 + 510 000a F0B5 push {r4, r5, r6, r7, lr} + 511 .LCFI3: + 512 .cfi_def_cfa_offset 20 + 513 .cfi_offset 4, -20 + 514 .cfi_offset 5, -16 + 515 .cfi_offset 6, -12 + 516 .cfi_offset 7, -8 + 517 .cfi_offset 14, -4 + 518 000c 2EE0 b .L33 + 519 .LVL47: + 520 .L50: + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Get current io position */ + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** iocurrent = GPIO_Pin & (1UL << position) ; + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (iocurrent != 0x00U) + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /*------------------------- EXTI Mode Configuration --------------------*/ + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Clear the External Interrupt or Event for the current IO */ + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp = SYSCFG->EXTICR[position >> 2U]; + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp &= (0x0FUL << (4U * (position & 0x03U))); + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 521 .loc 1 334 19 view .LVU190 + 522 000e 0925 movs r5, #9 + 523 0010 00E0 b .L31 + 524 .L34: + 525 0012 0025 movs r5, #0 + 526 .L31: + ARM GAS /tmp/ccBkqRtU.s page 18 + + + 527 .loc 1 334 41 discriminator 40 view .LVU191 + 528 0014 05FA0CFC lsl ip, r5, ip + 529 .loc 1 334 10 discriminator 40 view .LVU192 + 530 0018 A445 cmp ip, r4 + 531 001a 72D0 beq .L48 + 532 .LVL48: + 533 .L32: + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Clear EXTI line configuration for Current CPU */ + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->IMR1 &= ~(iocurrent); + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI->RTSR1 &= ~(iocurrent); + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI->FTSR1 &= ~(iocurrent); + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp = 0x0FUL << (4U * (position & 0x03U)); + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] &= ~tmp; + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /*------------------------- GPIO Mode Configuration --------------------*/ + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure IO in Analog Mode */ + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + 534 .loc 1 350 7 is_stmt 1 view .LVU193 + 535 .loc 1 350 20 is_stmt 0 view .LVU194 + 536 001c 0468 ldr r4, [r0] + 537 .loc 1 350 54 view .LVU195 + 538 001e 5D00 lsls r5, r3, #1 + 539 .loc 1 350 41 view .LVU196 + 540 0020 4FF0030C mov ip, #3 + 541 0024 0CFA05FC lsl ip, ip, r5 + 542 .loc 1 350 20 view .LVU197 + 543 0028 44EA0C04 orr r4, r4, ip + 544 002c 0460 str r4, [r0] + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the default Alternate Function in current IO */ + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + 545 .loc 1 353 7 is_stmt 1 view .LVU198 + 546 .loc 1 353 34 is_stmt 0 view .LVU199 + 547 002e 4FEAD30E lsr lr, r3, #3 + 548 .LVL49: + 549 .loc 1 353 34 view .LVU200 + 550 0032 0EF1080E add lr, lr, #8 + 551 0036 50F82E40 ldr r4, [r0, lr, lsl #2] + 552 .loc 1 353 58 view .LVU201 + 553 003a 03F00705 and r5, r3, #7 + 554 .loc 1 353 67 view .LVU202 + 555 003e AE00 lsls r6, r5, #2 + 556 .loc 1 353 44 view .LVU203 + 557 0040 0F25 movs r5, #15 + 558 0042 B540 lsls r5, r5, r6 + 559 .loc 1 353 34 view .LVU204 + 560 0044 24EA0504 bic r4, r4, r5 + 561 0048 40F82E40 str r4, [r0, lr, lsl #2] + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + ARM GAS /tmp/ccBkqRtU.s page 19 + + + 562 .loc 1 356 7 is_stmt 1 view .LVU205 + 563 .loc 1 356 20 is_stmt 0 view .LVU206 + 564 004c C468 ldr r4, [r0, #12] + 565 004e 24EA0C04 bic r4, r4, ip + 566 0052 C460 str r4, [r0, #12] + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the default value IO Output Type */ + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + 567 .loc 1 359 7 is_stmt 1 view .LVU207 + 568 .loc 1 359 22 is_stmt 0 view .LVU208 + 569 0054 4468 ldr r4, [r0, #4] + 570 0056 24EA0202 bic r2, r4, r2 + 571 .LVL50: + 572 .loc 1 359 22 view .LVU209 + 573 005a 4260 str r2, [r0, #4] + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Configure the default value for IO Speed */ + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 574 .loc 1 362 7 is_stmt 1 view .LVU210 + 575 .loc 1 362 22 is_stmt 0 view .LVU211 + 576 005c 8268 ldr r2, [r0, #8] + 577 005e 22EA0C02 bic r2, r2, ip + 578 0062 8260 str r2, [r0, #8] + 579 .L30: + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** position++; + 580 .loc 1 365 5 is_stmt 1 view .LVU212 + 581 .loc 1 365 13 is_stmt 0 view .LVU213 + 582 0064 0133 adds r3, r3, #1 + 583 .LVL51: + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 584 .loc 1 323 9 is_stmt 1 view .LVU214 + 585 0066 31FA03F2 lsrs r2, r1, r3 + 586 006a 6AD0 beq .L49 + 587 .LVL52: + 588 .L33: + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 589 .loc 1 326 5 view .LVU215 + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 590 .loc 1 326 33 is_stmt 0 view .LVU216 + 591 006c 0122 movs r2, #1 + 592 006e 9A40 lsls r2, r2, r3 + 593 .LVL53: + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 594 .loc 1 328 5 is_stmt 1 view .LVU217 + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 595 .loc 1 328 8 is_stmt 0 view .LVU218 + 596 0070 12EA010E ands lr, r2, r1 + 597 .LVL54: + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 598 .loc 1 328 8 view .LVU219 + 599 0074 F6D0 beq .L30 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp &= (0x0FUL << (4U * (position & 0x03U))); + 600 .loc 1 332 7 is_stmt 1 view .LVU220 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp &= (0x0FUL << (4U * (position & 0x03U))); + 601 .loc 1 332 37 is_stmt 0 view .LVU221 + ARM GAS /tmp/ccBkqRtU.s page 20 + + + 602 0076 9E08 lsrs r6, r3, #2 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp &= (0x0FUL << (4U * (position & 0x03U))); + 603 .loc 1 332 11 view .LVU222 + 604 0078 B51C adds r5, r6, #2 + 605 007a 334C ldr r4, .L51 + 606 007c 54F82540 ldr r4, [r4, r5, lsl #2] + 607 .LVL55: + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 608 .loc 1 333 7 is_stmt 1 view .LVU223 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 609 .loc 1 333 41 is_stmt 0 view .LVU224 + 610 0080 03F0030C and ip, r3, #3 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 611 .loc 1 333 29 view .LVU225 + 612 0084 4FEA8C0C lsl ip, ip, #2 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 613 .loc 1 333 22 view .LVU226 + 614 0088 0F25 movs r5, #15 + 615 008a 05FA0CF7 lsl r7, r5, ip + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 616 .loc 1 333 11 view .LVU227 + 617 008e 3C40 ands r4, r4, r7 + 618 .LVL56: + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 619 .loc 1 334 7 is_stmt 1 view .LVU228 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 620 .loc 1 334 19 is_stmt 0 view .LVU229 + 621 0090 2E4D ldr r5, .L51+4 + 622 0092 A842 cmp r0, r5 + 623 0094 BDD0 beq .L34 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 624 .loc 1 334 19 discriminator 1 view .LVU230 + 625 0096 05F58065 add r5, r5, #1024 + 626 009a A842 cmp r0, r5 + 627 009c 21D0 beq .L35 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 628 .loc 1 334 19 discriminator 3 view .LVU231 + 629 009e 05F58065 add r5, r5, #1024 + 630 00a2 A842 cmp r0, r5 + 631 00a4 1FD0 beq .L36 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 632 .loc 1 334 19 discriminator 5 view .LVU232 + 633 00a6 05F58065 add r5, r5, #1024 + 634 00aa A842 cmp r0, r5 + 635 00ac 1DD0 beq .L37 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 636 .loc 1 334 19 discriminator 7 view .LVU233 + 637 00ae 05F58065 add r5, r5, #1024 + 638 00b2 A842 cmp r0, r5 + 639 00b4 1BD0 beq .L38 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 640 .loc 1 334 19 discriminator 9 view .LVU234 + 641 00b6 05F58065 add r5, r5, #1024 + 642 00ba A842 cmp r0, r5 + 643 00bc 19D0 beq .L39 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 644 .loc 1 334 19 discriminator 11 view .LVU235 + ARM GAS /tmp/ccBkqRtU.s page 21 + + + 645 00be 05F58065 add r5, r5, #1024 + 646 00c2 A842 cmp r0, r5 + 647 00c4 17D0 beq .L40 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 648 .loc 1 334 19 discriminator 13 view .LVU236 + 649 00c6 05F58065 add r5, r5, #1024 + 650 00ca A842 cmp r0, r5 + 651 00cc 15D0 beq .L41 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 652 .loc 1 334 19 discriminator 15 view .LVU237 + 653 00ce 05F58065 add r5, r5, #1024 + 654 00d2 A842 cmp r0, r5 + 655 00d4 13D0 beq .L42 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 656 .loc 1 334 19 discriminator 17 view .LVU238 + 657 00d6 05F58065 add r5, r5, #1024 + 658 00da A842 cmp r0, r5 + 659 00dc 97D0 beq .L50 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 660 .loc 1 334 19 view .LVU239 + 661 00de 0A25 movs r5, #10 + 662 00e0 98E7 b .L31 + 663 .L35: + 664 00e2 0125 movs r5, #1 + 665 00e4 96E7 b .L31 + 666 .L36: + 667 00e6 0225 movs r5, #2 + 668 00e8 94E7 b .L31 + 669 .L37: + 670 00ea 0325 movs r5, #3 + 671 00ec 92E7 b .L31 + 672 .L38: + 673 00ee 0425 movs r5, #4 + 674 00f0 90E7 b .L31 + 675 .L39: + 676 00f2 0525 movs r5, #5 + 677 00f4 8EE7 b .L31 + 678 .L40: + 679 00f6 0625 movs r5, #6 + 680 00f8 8CE7 b .L31 + 681 .L41: + 682 00fa 0725 movs r5, #7 + 683 00fc 8AE7 b .L31 + 684 .L42: + 685 00fe 0825 movs r5, #8 + 686 0100 88E7 b .L31 + 687 .L48: + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + 688 .loc 1 337 9 is_stmt 1 view .LVU240 + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + 689 .loc 1 337 31 is_stmt 0 view .LVU241 + 690 0102 4FF0B044 mov r4, #1476395008 + 691 .LVL57: + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + 692 .loc 1 337 31 view .LVU242 + 693 0106 D4F88050 ldr r5, [r4, #128] + 694 010a 25EA0E05 bic r5, r5, lr + ARM GAS /tmp/ccBkqRtU.s page 22 + + + 695 010e C4F88050 str r5, [r4, #128] + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 696 .loc 1 338 9 is_stmt 1 view .LVU243 + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 697 .loc 1 338 31 is_stmt 0 view .LVU244 + 698 0112 D4F88450 ldr r5, [r4, #132] + 699 0116 25EA0E05 bic r5, r5, lr + 700 011a C4F88450 str r5, [r4, #132] + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI->FTSR1 &= ~(iocurrent); + 701 .loc 1 341 9 is_stmt 1 view .LVU245 + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** EXTI->FTSR1 &= ~(iocurrent); + 702 .loc 1 341 21 is_stmt 0 view .LVU246 + 703 011e 2568 ldr r5, [r4] + 704 0120 25EA0E05 bic r5, r5, lr + 705 0124 2560 str r5, [r4] + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 706 .loc 1 342 9 is_stmt 1 view .LVU247 + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 707 .loc 1 342 21 is_stmt 0 view .LVU248 + 708 0126 6568 ldr r5, [r4, #4] + 709 0128 25EA0E05 bic r5, r5, lr + 710 012c 6560 str r5, [r4, #4] + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2U] &= ~tmp; + 711 .loc 1 344 9 is_stmt 1 view .LVU249 + 712 .LVL58: + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 713 .loc 1 345 9 view .LVU250 + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 714 .loc 1 345 40 is_stmt 0 view .LVU251 + 715 012e DFF818C0 ldr ip, .L51 + 716 0132 B41C adds r4, r6, #2 + 717 0134 5CF82450 ldr r5, [ip, r4, lsl #2] + 718 0138 25EA0705 bic r5, r5, r7 + 719 013c 4CF82450 str r5, [ip, r4, lsl #2] + 720 0140 6CE7 b .L32 + 721 .LVL59: + 722 .L49: + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 723 .loc 1 367 1 view .LVU252 + 724 0142 F0BD pop {r4, r5, r6, r7, pc} + 725 .LVL60: + 726 .L47: + 727 .LCFI4: + 728 .cfi_def_cfa_offset 0 + 729 .cfi_restore 4 + 730 .cfi_restore 5 + 731 .cfi_restore 6 + 732 .cfi_restore 7 + 733 .cfi_restore 14 + 734 .loc 1 367 1 view .LVU253 + 735 0144 7047 bx lr + 736 .L52: + 737 0146 00BF .align 2 + 738 .L51: + 739 0148 00040058 .word 1476396032 + 740 014c 00000258 .word 1476526080 + ARM GAS /tmp/ccBkqRtU.s page 23 + + + 741 .cfi_endproc + 742 .LFE142: + 744 .section .text.HAL_GPIO_ReadPin,"ax",%progbits + 745 .align 1 + 746 .global HAL_GPIO_ReadPin + 747 .syntax unified + 748 .thumb + 749 .thumb_func + 750 .fpu fpv5-d16 + 752 HAL_GPIO_ReadPin: + 753 .LVL61: + 754 .LFB143: + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @} + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** @verbatim + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** =============================================================================== + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** ##### IO operation functions ##### + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** =============================================================================== + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** @endverbatim + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @{ + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Reads the specified input port pin. + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to read. + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This parameter can be GPIO_PIN_x where x can be (0..15). + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval The input port pin value. + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 755 .loc 1 393 1 is_stmt 1 view -0 + 756 .cfi_startproc + 757 @ args = 0, pretend = 0, frame = 0 + 758 @ frame_needed = 0, uses_anonymous_args = 0 + 759 @ link register save eliminated. + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIO_PinState bitstatus; + 760 .loc 1 394 3 view .LVU255 + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the parameters */ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 761 .loc 1 397 3 view .LVU256 + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + 762 .loc 1 399 3 view .LVU257 + 763 .loc 1 399 13 is_stmt 0 view .LVU258 + 764 0000 0369 ldr r3, [r0, #16] + 765 .loc 1 399 6 view .LVU259 + 766 0002 1942 tst r1, r3 + 767 0004 01D0 beq .L55 + ARM GAS /tmp/ccBkqRtU.s page 24 + + + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** bitstatus = GPIO_PIN_SET; + 768 .loc 1 401 15 view .LVU260 + 769 0006 0120 movs r0, #1 + 770 .LVL62: + 771 .loc 1 401 15 view .LVU261 + 772 0008 7047 bx lr + 773 .LVL63: + 774 .L55: + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** else + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** bitstatus = GPIO_PIN_RESET; + 775 .loc 1 405 15 view .LVU262 + 776 000a 0020 movs r0, #0 + 777 .LVL64: + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** return bitstatus; + 778 .loc 1 407 3 is_stmt 1 view .LVU263 + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 779 .loc 1 408 1 is_stmt 0 view .LVU264 + 780 000c 7047 bx lr + 781 .cfi_endproc + 782 .LFE143: + 784 .section .text.HAL_GPIO_WritePin,"ax",%progbits + 785 .align 1 + 786 .global HAL_GPIO_WritePin + 787 .syntax unified + 788 .thumb + 789 .thumb_func + 790 .fpu fpv5-d16 + 792 HAL_GPIO_WritePin: + 793 .LVL65: + 794 .LFB144: + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Sets or clears the selected data port bit. + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @note This function uses GPIOx_BSRR register to allow atomic read/modify + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * accesses. In this way, there is no risk of an IRQ occurring between + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * the read and the modify access. + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to be written. + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param PinState: specifies the value to be written to the selected bit. + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This parameter can be one of the GPIO_PinState enum values: + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @arg GPIO_PIN_RESET: to clear the port pin + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @arg GPIO_PIN_SET: to set the port pin + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 795 .loc 1 427 1 is_stmt 1 view -0 + 796 .cfi_startproc + 797 @ args = 0, pretend = 0, frame = 0 + 798 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccBkqRtU.s page 25 + + + 799 @ link register save eliminated. + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the parameters */ + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 800 .loc 1 429 3 view .LVU266 + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_ACTION(PinState)); + 801 .loc 1 430 3 view .LVU267 + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (PinState != GPIO_PIN_RESET) + 802 .loc 1 432 3 view .LVU268 + 803 .loc 1 432 6 is_stmt 0 view .LVU269 + 804 0000 0AB1 cbz r2, .L57 + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->BSRR = GPIO_Pin; + 805 .loc 1 434 5 is_stmt 1 view .LVU270 + 806 .loc 1 434 17 is_stmt 0 view .LVU271 + 807 0002 8161 str r1, [r0, #24] + 808 0004 7047 bx lr + 809 .L57: + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** else + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + 810 .loc 1 438 5 is_stmt 1 view .LVU272 + 811 .loc 1 438 38 is_stmt 0 view .LVU273 + 812 0006 0904 lsls r1, r1, #16 + 813 .LVL66: + 814 .loc 1 438 17 view .LVU274 + 815 0008 8161 str r1, [r0, #24] + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 816 .loc 1 440 1 view .LVU275 + 817 000a 7047 bx lr + 818 .cfi_endproc + 819 .LFE144: + 821 .section .text.HAL_GPIO_TogglePin,"ax",%progbits + 822 .align 1 + 823 .global HAL_GPIO_TogglePin + 824 .syntax unified + 825 .thumb + 826 .thumb_func + 827 .fpu fpv5-d16 + 829 HAL_GPIO_TogglePin: + 830 .LVL67: + 831 .LFB145: + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Toggles the specified GPIO pins. + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: Specifies the pins to be toggled. + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 832 .loc 1 449 1 is_stmt 1 view -0 + 833 .cfi_startproc + 834 @ args = 0, pretend = 0, frame = 0 + 835 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccBkqRtU.s page 26 + + + 836 @ link register save eliminated. + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the parameters */ + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 837 .loc 1 451 3 view .LVU277 + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) + 838 .loc 1 453 3 view .LVU278 + 839 .loc 1 453 13 is_stmt 0 view .LVU279 + 840 0000 4369 ldr r3, [r0, #20] + 841 .loc 1 453 6 view .LVU280 + 842 0002 31EA0303 bics r3, r1, r3 + 843 0006 01D0 beq .L62 + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** else + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->BSRR = GPIO_Pin; + 844 .loc 1 459 5 is_stmt 1 view .LVU281 + 845 .loc 1 459 17 is_stmt 0 view .LVU282 + 846 0008 8161 str r1, [r0, #24] + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 847 .loc 1 461 1 view .LVU283 + 848 000a 7047 bx lr + 849 .L62: + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 850 .loc 1 455 5 is_stmt 1 view .LVU284 + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 851 .loc 1 455 38 is_stmt 0 view .LVU285 + 852 000c 0904 lsls r1, r1, #16 + 853 .LVL68: + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 854 .loc 1 455 17 view .LVU286 + 855 000e 8161 str r1, [r0, #24] + 856 0010 7047 bx lr + 857 .cfi_endproc + 858 .LFE145: + 860 .section .text.HAL_GPIO_LockPin,"ax",%progbits + 861 .align 1 + 862 .global HAL_GPIO_LockPin + 863 .syntax unified + 864 .thumb + 865 .thumb_func + 866 .fpu fpv5-d16 + 868 HAL_GPIO_LockPin: + 869 .LVL69: + 870 .LFB146: + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Locks GPIO Pins configuration registers. + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @note The configuration of the locked GPIO pins can no longer be modified + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * until the next reset. + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: specifies the port bit to be locked. + ARM GAS /tmp/ccBkqRtU.s page 27 + + + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 871 .loc 1 475 1 is_stmt 1 view -0 + 872 .cfi_startproc + 873 @ args = 0, pretend = 0, frame = 8 + 874 @ frame_needed = 0, uses_anonymous_args = 0 + 875 @ link register save eliminated. + 876 .loc 1 475 1 is_stmt 0 view .LVU288 + 877 0000 82B0 sub sp, sp, #8 + 878 .LCFI5: + 879 .cfi_def_cfa_offset 8 + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** __IO uint32_t tmp = GPIO_LCKR_LCKK; + 880 .loc 1 476 3 is_stmt 1 view .LVU289 + 881 .loc 1 476 17 is_stmt 0 view .LVU290 + 882 0002 4FF48033 mov r3, #65536 + 883 0006 0193 str r3, [sp, #4] + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Check the parameters */ + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + 884 .loc 1 479 3 is_stmt 1 view .LVU291 + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 885 .loc 1 480 3 view .LVU292 + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Apply lock key write sequence */ + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp |= GPIO_Pin; + 886 .loc 1 483 3 view .LVU293 + 887 .loc 1 483 7 is_stmt 0 view .LVU294 + 888 0008 019B ldr r3, [sp, #4] + 889 000a 0B43 orrs r3, r3, r1 + 890 000c 0193 str r3, [sp, #4] + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 891 .loc 1 485 3 is_stmt 1 view .LVU295 + 892 .loc 1 485 15 is_stmt 0 view .LVU296 + 893 000e 019B ldr r3, [sp, #4] + 894 0010 C361 str r3, [r0, #28] + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->LCKR = GPIO_Pin; + 895 .loc 1 487 3 is_stmt 1 view .LVU297 + 896 .loc 1 487 15 is_stmt 0 view .LVU298 + 897 0012 C161 str r1, [r0, #28] + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 898 .loc 1 489 3 is_stmt 1 view .LVU299 + 899 .loc 1 489 15 is_stmt 0 view .LVU300 + 900 0014 019B ldr r3, [sp, #4] + 901 0016 C361 str r3, [r0, #28] + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Read LCKK register. This read is mandatory to complete key lock sequence*/ + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** tmp = GPIOx->LCKR; + 902 .loc 1 491 3 is_stmt 1 view .LVU301 + 903 .loc 1 491 14 is_stmt 0 view .LVU302 + 904 0018 C369 ldr r3, [r0, #28] + 905 .loc 1 491 7 view .LVU303 + 906 001a 0193 str r3, [sp, #4] + ARM GAS /tmp/ccBkqRtU.s page 28 + + + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* read again in order to confirm lock is active */ + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) + 907 .loc 1 494 3 is_stmt 1 view .LVU304 + 908 .loc 1 494 13 is_stmt 0 view .LVU305 + 909 001c C369 ldr r3, [r0, #28] + 910 .loc 1 494 6 view .LVU306 + 911 001e 13F4803F tst r3, #65536 + 912 0022 02D0 beq .L65 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** return HAL_OK; + 913 .loc 1 496 12 view .LVU307 + 914 0024 0020 movs r0, #0 + 915 .LVL70: + 916 .L64: + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** else + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** return HAL_ERROR; + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 917 .loc 1 502 1 view .LVU308 + 918 0026 02B0 add sp, sp, #8 + 919 .LCFI6: + 920 .cfi_remember_state + 921 .cfi_def_cfa_offset 0 + 922 @ sp needed + 923 0028 7047 bx lr + 924 .LVL71: + 925 .L65: + 926 .LCFI7: + 927 .cfi_restore_state + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 928 .loc 1 500 12 view .LVU309 + 929 002a 0120 movs r0, #1 + 930 .LVL72: + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 931 .loc 1 500 12 view .LVU310 + 932 002c FBE7 b .L64 + 933 .cfi_endproc + 934 .LFE146: + 936 .section .text.HAL_GPIO_EXTI_Callback,"ax",%progbits + 937 .align 1 + 938 .weak HAL_GPIO_EXTI_Callback + 939 .syntax unified + 940 .thumb + 941 .thumb_func + 942 .fpu fpv5-d16 + 944 HAL_GPIO_EXTI_Callback: + 945 .LVL73: + 946 .LFB148: + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief Handle EXTI interrupt request. + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + ARM GAS /tmp/ccBkqRtU.s page 29 + + + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U) + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #else + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #endif + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /** + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @brief EXTI line detection callback. + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** * @retval None + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 947 .loc 1 533 1 is_stmt 1 view -0 + 948 .cfi_startproc + 949 @ args = 0, pretend = 0, frame = 0 + 950 @ frame_needed = 0, uses_anonymous_args = 0 + 951 @ link register save eliminated. + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 952 .loc 1 535 3 view .LVU312 + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** /* NOTE: This function Should not be modified, when the callback is needed, + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** the HAL_GPIO_EXTI_Callback could be implemented in the user file + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** */ + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 953 .loc 1 540 1 is_stmt 0 view .LVU313 + 954 0000 7047 bx lr + 955 .cfi_endproc + 956 .LFE148: + 958 .section .text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits + 959 .align 1 + 960 .global HAL_GPIO_EXTI_IRQHandler + 961 .syntax unified + 962 .thumb + 963 .thumb_func + 964 .fpu fpv5-d16 + 966 HAL_GPIO_EXTI_IRQHandler: + 967 .LVL74: + 968 .LFB147: + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 969 .loc 1 510 1 is_stmt 1 view -0 + 970 .cfi_startproc + 971 @ args = 0, pretend = 0, frame = 0 + 972 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccBkqRtU.s page 30 + + + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 973 .loc 1 510 1 is_stmt 0 view .LVU315 + 974 0000 08B5 push {r3, lr} + 975 .LCFI8: + 976 .cfi_def_cfa_offset 8 + 977 .cfi_offset 3, -8 + 978 .cfi_offset 14, -4 + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 979 .loc 1 519 3 is_stmt 1 view .LVU316 + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 980 .loc 1 519 7 is_stmt 0 view .LVU317 + 981 0002 4FF0B043 mov r3, #1476395008 + 982 0006 D3F88830 ldr r3, [r3, #136] + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** { + 983 .loc 1 519 6 view .LVU318 + 984 000a 0342 tst r3, r0 + 985 000c 00D1 bne .L71 + 986 .LVL75: + 987 .L68: + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 988 .loc 1 525 1 view .LVU319 + 989 000e 08BD pop {r3, pc} + 990 .LVL76: + 991 .L71: + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 992 .loc 1 521 5 is_stmt 1 view .LVU320 + 993 0010 4FF0B043 mov r3, #1476395008 + 994 0014 C3F88800 str r0, [r3, #136] + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** } + 995 .loc 1 522 5 view .LVU321 + 996 0018 FFF7FEFF bl HAL_GPIO_EXTI_Callback + 997 .LVL77: + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c **** + 998 .loc 1 525 1 is_stmt 0 view .LVU322 + 999 001c F7E7 b .L68 + 1000 .cfi_endproc + 1001 .LFE147: + 1003 .text + 1004 .Letext0: + 1005 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1006 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1007 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1008 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1009 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + ARM GAS /tmp/ccBkqRtU.s page 31 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_gpio.c + /tmp/ccBkqRtU.s:17 .text.HAL_GPIO_Init:0000000000000000 $t + /tmp/ccBkqRtU.s:25 .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init + /tmp/ccBkqRtU.s:474 .text.HAL_GPIO_Init:00000000000001f0 $d + /tmp/ccBkqRtU.s:481 .text.HAL_GPIO_DeInit:0000000000000000 $t + /tmp/ccBkqRtU.s:488 .text.HAL_GPIO_DeInit:0000000000000000 HAL_GPIO_DeInit + /tmp/ccBkqRtU.s:739 .text.HAL_GPIO_DeInit:0000000000000148 $d + /tmp/ccBkqRtU.s:745 .text.HAL_GPIO_ReadPin:0000000000000000 $t + /tmp/ccBkqRtU.s:752 .text.HAL_GPIO_ReadPin:0000000000000000 HAL_GPIO_ReadPin + /tmp/ccBkqRtU.s:785 .text.HAL_GPIO_WritePin:0000000000000000 $t + /tmp/ccBkqRtU.s:792 .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin + /tmp/ccBkqRtU.s:822 .text.HAL_GPIO_TogglePin:0000000000000000 $t + /tmp/ccBkqRtU.s:829 .text.HAL_GPIO_TogglePin:0000000000000000 HAL_GPIO_TogglePin + /tmp/ccBkqRtU.s:861 .text.HAL_GPIO_LockPin:0000000000000000 $t + /tmp/ccBkqRtU.s:868 .text.HAL_GPIO_LockPin:0000000000000000 HAL_GPIO_LockPin + /tmp/ccBkqRtU.s:937 .text.HAL_GPIO_EXTI_Callback:0000000000000000 $t + /tmp/ccBkqRtU.s:944 .text.HAL_GPIO_EXTI_Callback:0000000000000000 HAL_GPIO_EXTI_Callback + /tmp/ccBkqRtU.s:959 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 $t + /tmp/ccBkqRtU.s:966 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 HAL_GPIO_EXTI_IRQHandler + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_gpio.o b/build/stm32h7xx_hal_gpio.o new file mode 100644 index 0000000..2375c32 Binary files /dev/null and b/build/stm32h7xx_hal_gpio.o differ diff --git a/build/stm32h7xx_hal_hsem.d b/build/stm32h7xx_hal_hsem.d new file mode 100644 index 0000000..5e78979 --- /dev/null +++ b/build/stm32h7xx_hal_hsem.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_hsem.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_hsem.lst b/build/stm32h7xx_hal_hsem.lst new file mode 100644 index 0000000..a575b11 --- /dev/null +++ b/build/stm32h7xx_hal_hsem.lst @@ -0,0 +1,927 @@ +ARM GAS /tmp/cc8V8hSh.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_hsem.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_HSEM_Take,"ax",%progbits + 17 .align 1 + 18 .global HAL_HSEM_Take + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_HSEM_Take: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @file stm32h7xx_hal_hsem.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief HSEM HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * functionalities of the semaphore peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + Semaphore Take function (2-Step Procedure) , non blocking + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + Semaphore FastTake function (1-Step Procedure) , non blocking + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + Semaphore Status check + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + Semaphore Clear Key Set and Get + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + Release and release all functions + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + Semaphore notification enabling and disabling and callnack functions + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + IRQ handler management + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @verbatim + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ##### How to use this driver ##### + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as param + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the semaphore ID from 0 to 31 + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the process ID from 0 to 255 + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assu + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the semaphore ID from 0_ID to 31 + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) It returns 1 if the given semaphore is taken otherwise (Free) zero + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameter + ARM GAS /tmp/cc8V8hSh.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the semaphore ID from 0 to 31 + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the process ID from 0 to 255: + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** may be generated when enabled (notification activated). If ProcessID or MasterID does not + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** semaphore remains taken (locked) + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** This function takes as parameters : + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) the Master ID: + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that cor + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** to MasterID will be freed, and an interrupt may be generated when enabled (notification + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** Key or the MasterID doesn't match, semaphores remains taken (locked) + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#)Semaphores Release all key functions: + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) HAL_HSEM_SetClearKey() to set semaphore release all Key + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) HAL_HSEM_GetClearKey() to get release all Key + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (#)Semaphores notification functions : + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) HAL_HSEM_ActivateNotification to activate a notification callback on + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** a given semaphores Mask (bitfield). When one or more semaphores defined by the mask + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of t + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** semaphores (bitfield). + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** Used by the notification functions + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** *** HSEM HAL driver macros list *** + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================= + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] Below the list of most used macros in HSEM HAL driver. + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask. + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] Example of use : + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_T + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed us + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts. + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts. + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not. + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags. + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags. + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @endverbatim + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ****************************************************************************** + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @attention + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** *

© Copyright (c) 2017 STMicroelectronics. + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * All rights reserved.

+ 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * This software component is licensed by ST under BSD 3-Clause license, + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * the "License"; You may not use this file except in compliance with the + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * License. You may obtain a copy of the License at: + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * opensource.org/licenses/BSD-3-Clause + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ****************************************************************************** + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Includes ------------------------------------------------------------------*/ + ARM GAS /tmp/cc8V8hSh.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #include "stm32h7xx_hal.h" + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @addtogroup STM32H7xx_HAL_Driver + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @defgroup HSEM HSEM + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief HSEM HAL module driver + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #ifdef HAL_HSEM_MODULE_ENABLED + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Private typedef -----------------------------------------------------------*/ + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Private define ------------------------------------------------------------*/ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if defined(DUAL_CORE) + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @defgroup HSEM_Private_Constants HSEM Private Constants + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #ifndef HSEM_R_MASTERID + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #define HSEM_R_MASTERID HSEM_R_COREID + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #ifndef HSEM_RLR_MASTERID + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #define HSEM_RLR_MASTERID HSEM_RLR_COREID + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #ifndef HSEM_CR_MASTERID + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #define HSEM_CR_MASTERID HSEM_CR_COREID + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @} + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif /* DUAL_CORE */ + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Private macro -------------------------------------------------------------*/ + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Private variables ---------------------------------------------------------*/ + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Private function prototypes -----------------------------------------------*/ + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Private functions ---------------------------------------------------------*/ + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Exported functions --------------------------------------------------------*/ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @defgroup HSEM_Exported_Functions HSEM Exported Functions + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief HSEM Take and Release functions + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @verbatim + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ##### HSEM Take and Release functions ##### + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] This section provides functions allowing to: + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Take a semaphore with 2 Step method + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Fast Take a semaphore with 1 Step method + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Check semaphore state Taken or not + ARM GAS /tmp/cc8V8hSh.s page 4 + + + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Release a semaphore + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Release all semaphore at once + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @endverbatim + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Take a semaphore in 2 Step mode. + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemID: semaphore ID from 0 to 31 + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param ProcessID: Process ID from 0 to 255 + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval HAL status + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID) + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 29 .loc 1 160 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Check the parameters */ + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_SEMID(SemID)); + 34 .loc 1 162 3 view .LVU1 + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_PROCESSID(ProcessID)); + 35 .loc 1 163 3 view .LVU2 + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* First step write R register with MasterID, processID and take bit=1*/ + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MA + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* second step : read the R register . Take achieved if MasterID and processID match and take bit + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*take success when MasterID and ProcessID match and take bit set*/ + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return HAL_OK; + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #else + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* First step write R register with MasterID, processID and take bit=1*/ + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK); + 36 .loc 1 177 3 view .LVU3 + 37 .loc 1 177 56 is_stmt 0 view .LVU4 + 38 0000 064B ldr r3, .L4 + 39 0002 0B43 orrs r3, r3, r1 + 40 .loc 1 177 18 view .LVU5 + 41 0004 064A ldr r2, .L4+4 + 42 0006 42F82030 str r3, [r2, r0, lsl #2] + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* second step : read the R register . Take achieved if MasterID and processID match and take bit + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK)) + 43 .loc 1 180 3 is_stmt 1 view .LVU6 + 44 .loc 1 180 14 is_stmt 0 view .LVU7 + 45 000a 52F82020 ldr r2, [r2, r0, lsl #2] + 46 .loc 1 180 6 view .LVU8 + 47 000e 9342 cmp r3, r2 + 48 0010 01D0 beq .L3 + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + ARM GAS /tmp/cc8V8hSh.s page 5 + + + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*take success when MasterID and ProcessID match and take bit set*/ + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return HAL_OK; + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Semaphore take fails*/ + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return HAL_ERROR; + 49 .loc 1 188 10 view .LVU9 + 50 0012 0120 movs r0, #1 + 51 .LVL1: + 52 .loc 1 188 10 view .LVU10 + 53 0014 7047 bx lr + 54 .LVL2: + 55 .L3: + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 56 .loc 1 183 12 view .LVU11 + 57 0016 0020 movs r0, #0 + 58 .LVL3: + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 59 .loc 1 189 1 view .LVU12 + 60 0018 7047 bx lr + 61 .L5: + 62 001a 00BF .align 2 + 63 .L4: + 64 001c 00030080 .word -2147482880 + 65 0020 00640258 .word 1476551680 + 66 .cfi_endproc + 67 .LFE141: + 69 .section .text.HAL_HSEM_FastTake,"ax",%progbits + 70 .align 1 + 71 .global HAL_HSEM_FastTake + 72 .syntax unified + 73 .thumb + 74 .thumb_func + 75 .fpu fpv5-d16 + 77 HAL_HSEM_FastTake: + 78 .LVL4: + 79 .LFB142: + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Fast Take a semaphore with 1 Step mode. + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemID: semaphore ID from 0 to 31 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval HAL status + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID) + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 80 .loc 1 197 1 is_stmt 1 view -0 + 81 .cfi_startproc + 82 @ args = 0, pretend = 0, frame = 0 + 83 @ frame_needed = 0, uses_anonymous_args = 0 + 84 @ link register save eliminated. + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Check the parameters */ + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_SEMID(SemID)); + 85 .loc 1 199 3 view .LVU14 + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Read the RLR register to take the semaphore */ + ARM GAS /tmp/cc8V8hSh.s page 6 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MAS + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*take success when MasterID match and take bit set*/ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return HAL_OK; + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #else + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Read the RLR register to take the semaphore */ + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK)) + 86 .loc 1 210 3 view .LVU15 + 87 .loc 1 210 16 is_stmt 0 view .LVU16 + 88 0000 2030 adds r0, r0, #32 + 89 .LVL5: + 90 .loc 1 210 16 view .LVU17 + 91 0002 054B ldr r3, .L9 + 92 0004 53F82020 ldr r2, [r3, r0, lsl #2] + 93 .loc 1 210 6 view .LVU18 + 94 0008 044B ldr r3, .L9+4 + 95 000a 9A42 cmp r2, r3 + 96 000c 01D0 beq .L8 + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*take success when MasterID match and take bit set*/ + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return HAL_OK; + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Semaphore take fails */ + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return HAL_ERROR; + 97 .loc 1 218 10 view .LVU19 + 98 000e 0120 movs r0, #1 + 99 .LVL6: + 100 .loc 1 218 10 view .LVU20 + 101 0010 7047 bx lr + 102 .L8: + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 103 .loc 1 213 12 view .LVU21 + 104 0012 0020 movs r0, #0 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 105 .loc 1 219 1 view .LVU22 + 106 0014 7047 bx lr + 107 .L10: + 108 0016 00BF .align 2 + 109 .L9: + 110 0018 00640258 .word 1476551680 + 111 001c 00030080 .word -2147482880 + 112 .cfi_endproc + 113 .LFE142: + 115 .section .text.HAL_HSEM_IsSemTaken,"ax",%progbits + 116 .align 1 + 117 .global HAL_HSEM_IsSemTaken + 118 .syntax unified + 119 .thumb + 120 .thumb_func + 121 .fpu fpv5-d16 + 123 HAL_HSEM_IsSemTaken: + 124 .LVL7: + 125 .LFB143: + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + ARM GAS /tmp/cc8V8hSh.s page 7 + + + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Check semaphore state Taken or not. + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemID: semaphore ID + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval HAL HSEM state + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID) + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 126 .loc 1 226 1 is_stmt 1 view -0 + 127 .cfi_startproc + 128 @ args = 0, pretend = 0, frame = 0 + 129 @ frame_needed = 0, uses_anonymous_args = 0 + 130 @ link register save eliminated. + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); + 131 .loc 1 227 3 view .LVU24 + 132 .loc 1 227 20 is_stmt 0 view .LVU25 + 133 0000 044B ldr r3, .L15 + 134 0002 53F82030 ldr r3, [r3, r0, lsl #2] + 135 .loc 1 227 56 view .LVU26 + 136 0006 002B cmp r3, #0 + 137 0008 01DB blt .L14 + 138 000a 0020 movs r0, #0 + 139 .LVL8: + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 140 .loc 1 228 1 view .LVU27 + 141 000c 7047 bx lr + 142 .LVL9: + 143 .L14: + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); + 144 .loc 1 227 56 view .LVU28 + 145 000e 0120 movs r0, #1 + 146 .LVL10: + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); + 147 .loc 1 227 56 view .LVU29 + 148 0010 7047 bx lr + 149 .L16: + 150 0012 00BF .align 2 + 151 .L15: + 152 0014 00640258 .word 1476551680 + 153 .cfi_endproc + 154 .LFE143: + 156 .section .text.HAL_HSEM_Release,"ax",%progbits + 157 .align 1 + 158 .global HAL_HSEM_Release + 159 .syntax unified + 160 .thumb + 161 .thumb_func + 162 .fpu fpv5-d16 + 164 HAL_HSEM_Release: + 165 .LVL11: + 166 .LFB144: + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Release a semaphore. + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemID: semaphore ID from 0 to 31 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param ProcessID: Process ID from 0 to 255 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval None + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + ARM GAS /tmp/cc8V8hSh.s page 8 + + + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID) + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 167 .loc 1 238 1 is_stmt 1 view -0 + 168 .cfi_startproc + 169 @ args = 0, pretend = 0, frame = 0 + 170 @ frame_needed = 0, uses_anonymous_args = 0 + 171 @ link register save eliminated. + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Check the parameters */ + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_SEMID(SemID)); + 172 .loc 1 240 3 view .LVU31 + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_PROCESSID(ProcessID)); + 173 .loc 1 241 3 view .LVU32 + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_ + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #else + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT); + 174 .loc 1 247 3 view .LVU33 + 175 .loc 1 247 31 is_stmt 0 view .LVU34 + 176 0000 41F44071 orr r1, r1, #768 + 177 .LVL12: + 178 .loc 1 247 18 view .LVU35 + 179 0004 014B ldr r3, .L18 + 180 0006 43F82010 str r1, [r3, r0, lsl #2] + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 181 .loc 1 250 1 view .LVU36 + 182 000a 7047 bx lr + 183 .L19: + 184 .align 2 + 185 .L18: + 186 000c 00640258 .word 1476551680 + 187 .cfi_endproc + 188 .LFE144: + 190 .section .text.HAL_HSEM_ReleaseAll,"ax",%progbits + 191 .align 1 + 192 .global HAL_HSEM_ReleaseAll + 193 .syntax unified + 194 .thumb + 195 .thumb_func + 196 .fpu fpv5-d16 + 198 HAL_HSEM_ReleaseAll: + 199 .LVL13: + 200 .LFB145: + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Release All semaphore used by a given Master . + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param Key: Semaphore Key , value from 0 to 0xFFFF + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param CoreID: CoreID of the CPU that is using semaphores to be released + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval None + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID) + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 201 .loc 1 259 1 is_stmt 1 view -0 + 202 .cfi_startproc + ARM GAS /tmp/cc8V8hSh.s page 9 + + + 203 @ args = 0, pretend = 0, frame = 0 + 204 @ frame_needed = 0, uses_anonymous_args = 0 + 205 @ link register save eliminated. + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_KEY(Key)); + 206 .loc 1 260 3 view .LVU38 + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_COREID(CoreID)); + 207 .loc 1 261 3 view .LVU39 + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos)); + 208 .loc 1 263 3 view .LVU40 + 209 .loc 1 263 50 is_stmt 0 view .LVU41 + 210 0000 0902 lsls r1, r1, #8 + 211 .LVL14: + 212 .loc 1 263 40 view .LVU42 + 213 0002 41EA0041 orr r1, r1, r0, lsl #16 + 214 .loc 1 263 12 view .LVU43 + 215 0006 024B ldr r3, .L21 + 216 0008 C3F84011 str r1, [r3, #320] + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 217 .loc 1 264 1 view .LVU44 + 218 000c 7047 bx lr + 219 .L22: + 220 000e 00BF .align 2 + 221 .L21: + 222 0010 00640258 .word 1476551680 + 223 .cfi_endproc + 224 .LFE145: + 226 .section .text.HAL_HSEM_SetClearKey,"ax",%progbits + 227 .align 1 + 228 .global HAL_HSEM_SetClearKey + 229 .syntax unified + 230 .thumb + 231 .thumb_func + 232 .fpu fpv5-d16 + 234 HAL_HSEM_SetClearKey: + 235 .LVL15: + 236 .LFB146: + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @} + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief HSEM Set and Get Key functions. + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @verbatim + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ##### HSEM Set and Get Key functions ##### + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] This section provides functions allowing to: + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Set semaphore Key + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** (+) Get semaphore Key + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @endverbatim + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + ARM GAS /tmp/cc8V8hSh.s page 10 + + + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Set semaphore Key . + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param Key: Semaphore Key , value from 0 to 0xFFFF + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval None + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** void HAL_HSEM_SetClearKey(uint32_t Key) + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 237 .loc 1 291 1 is_stmt 1 view -0 + 238 .cfi_startproc + 239 @ args = 0, pretend = 0, frame = 0 + 240 @ frame_needed = 0, uses_anonymous_args = 0 + 241 @ link register save eliminated. + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** assert_param(IS_HSEM_KEY(Key)); + 242 .loc 1 292 3 view .LVU46 + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos)); + 243 .loc 1 294 3 view .LVU47 + 244 0000 044A ldr r2, .L24 + 245 0002 D2F84431 ldr r3, [r2, #324] + 246 0006 9BB2 uxth r3, r3 + 247 0008 43EA0043 orr r3, r3, r0, lsl #16 + 248 000c C2F84431 str r3, [r2, #324] + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 249 .loc 1 296 1 is_stmt 0 view .LVU48 + 250 0010 7047 bx lr + 251 .L25: + 252 0012 00BF .align 2 + 253 .L24: + 254 0014 00640258 .word 1476551680 + 255 .cfi_endproc + 256 .LFE146: + 258 .section .text.HAL_HSEM_GetClearKey,"ax",%progbits + 259 .align 1 + 260 .global HAL_HSEM_GetClearKey + 261 .syntax unified + 262 .thumb + 263 .thumb_func + 264 .fpu fpv5-d16 + 266 HAL_HSEM_GetClearKey: + 267 .LFB147: + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Get semaphore Key . + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval Semaphore Key , value from 0 to 0xFFFF + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** uint32_t HAL_HSEM_GetClearKey(void) + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 268 .loc 1 303 1 is_stmt 1 view -0 + 269 .cfi_startproc + 270 @ args = 0, pretend = 0, frame = 0 + 271 @ frame_needed = 0, uses_anonymous_args = 0 + 272 @ link register save eliminated. + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos); + 273 .loc 1 304 3 view .LVU50 + 274 .loc 1 304 15 is_stmt 0 view .LVU51 + 275 0000 024B ldr r3, .L27 + ARM GAS /tmp/cc8V8hSh.s page 11 + + + 276 0002 D3F84401 ldr r0, [r3, #324] + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 277 .loc 1 305 1 view .LVU52 + 278 0006 000C lsrs r0, r0, #16 + 279 0008 7047 bx lr + 280 .L28: + 281 000a 00BF .align 2 + 282 .L27: + 283 000c 00640258 .word 1476551680 + 284 .cfi_endproc + 285 .LFE147: + 287 .section .text.HAL_HSEM_ActivateNotification,"ax",%progbits + 288 .align 1 + 289 .global HAL_HSEM_ActivateNotification + 290 .syntax unified + 291 .thumb + 292 .thumb_func + 293 .fpu fpv5-d16 + 295 HAL_HSEM_ActivateNotification: + 296 .LVL16: + 297 .LFB148: + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @} + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief HSEM Notification functions. + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @verbatim + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ##### HSEM IRQ handler management and Notification functions ##### + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** ============================================================================== + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** [..] This section provides HSEM IRQ handler and Notification function. + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** @endverbatim + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @{ + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Activate Semaphore release Notification for a given Semaphores Mask . + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemMask: Mask of Released semaphores + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval Semaphore Key + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** void HAL_HSEM_ActivateNotification(uint32_t SemMask) + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 298 .loc 1 330 1 is_stmt 1 view -0 + 299 .cfi_startproc + 300 @ args = 0, pretend = 0, frame = 0 + 301 @ frame_needed = 0, uses_anonymous_args = 0 + 302 @ link register save eliminated. + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*enable the semaphore mask interrupts */ + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Use interrupt line 0 for CPU1 Master */ + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C1IER |= SemMask; + ARM GAS /tmp/cc8V8hSh.s page 12 + + + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** else /* HSEM_CPU2_COREID */ + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Use interrupt line 1 for CPU2 Master*/ + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C2IER |= SemMask; + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #else + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM_COMMON->IER |= SemMask; + 303 .loc 1 344 3 view .LVU54 + 304 .loc 1 344 20 is_stmt 0 view .LVU55 + 305 0000 024A ldr r2, .L30 + 306 0002 1368 ldr r3, [r2] + 307 0004 0343 orrs r3, r3, r0 + 308 0006 1360 str r3, [r2] + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 309 .loc 1 346 1 view .LVU56 + 310 0008 7047 bx lr + 311 .L31: + 312 000a 00BF .align 2 + 313 .L30: + 314 000c 00650258 .word 1476551936 + 315 .cfi_endproc + 316 .LFE148: + 318 .section .text.HAL_HSEM_DeactivateNotification,"ax",%progbits + 319 .align 1 + 320 .global HAL_HSEM_DeactivateNotification + 321 .syntax unified + 322 .thumb + 323 .thumb_func + 324 .fpu fpv5-d16 + 326 HAL_HSEM_DeactivateNotification: + 327 .LVL17: + 328 .LFB149: + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Deactivate Semaphore release Notification for a given Semaphores Mask . + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemMask: Mask of Released semaphores + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval Semaphore Key + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** void HAL_HSEM_DeactivateNotification(uint32_t SemMask) + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 329 .loc 1 354 1 is_stmt 1 view -0 + 330 .cfi_startproc + 331 @ args = 0, pretend = 0, frame = 0 + 332 @ frame_needed = 0, uses_anonymous_args = 0 + 333 @ link register save eliminated. + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*enable the semaphore mask interrupts */ + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Use interrupt line 0 for CPU1 Master */ + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C1IER &= ~SemMask; + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** else /* HSEM_CPU2_COREID */ + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Use interrupt line 1 for CPU2 Master*/ + ARM GAS /tmp/cc8V8hSh.s page 13 + + + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C2IER &= ~SemMask; + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #else + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM_COMMON->IER &= ~SemMask; + 334 .loc 1 368 3 view .LVU58 + 335 .loc 1 368 20 is_stmt 0 view .LVU59 + 336 0000 024A ldr r2, .L33 + 337 0002 1368 ldr r3, [r2] + 338 0004 23EA0003 bic r3, r3, r0 + 339 0008 1360 str r3, [r2] + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 340 .loc 1 370 1 view .LVU60 + 341 000a 7047 bx lr + 342 .L34: + 343 .align 2 + 344 .L33: + 345 000c 00650258 .word 1476551936 + 346 .cfi_endproc + 347 .LFE149: + 349 .section .text.HAL_HSEM_FreeCallback,"ax",%progbits + 350 .align 1 + 351 .weak HAL_HSEM_FreeCallback + 352 .syntax unified + 353 .thumb + 354 .thumb_func + 355 .fpu fpv5-d16 + 357 HAL_HSEM_FreeCallback: + 358 .LVL18: + 359 .LFB151: + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief This function handles HSEM interrupt request + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval None + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** void HAL_HSEM_IRQHandler(void) + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** uint32_t statusreg; + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Get the list of masked freed semaphores*/ + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Disable Interrupts*/ + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C1IER &= ~((uint32_t)statusreg); + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Clear Flags*/ + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C1ICR = ((uint32_t)statusreg); + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** else /* HSEM_CPU2_COREID */ + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Get the list of masked freed semaphores*/ + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/ + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Disable Interrupts*/ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C2IER &= ~((uint32_t)statusreg); + ARM GAS /tmp/cc8V8hSh.s page 14 + + + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Clear Flags*/ + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM->C2ICR = ((uint32_t)statusreg); + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #else + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Get the list of masked freed semaphores*/ + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** statusreg = HSEM_COMMON->MISR; + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Disable Interrupts*/ + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM_COMMON->IER &= ~((uint32_t)statusreg); + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /*Clear Flags*/ + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HSEM_COMMON->ICR = ((uint32_t)statusreg); + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #endif + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Call FreeCallback */ + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** HAL_HSEM_FreeCallback(statusreg); + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /** + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @brief Semaphore Released Callback. + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @param SemMask: Mask of Released semaphores + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** * @retval None + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** __weak void HAL_HSEM_FreeCallback(uint32_t SemMask) + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** { + 360 .loc 1 423 1 is_stmt 1 view -0 + 361 .cfi_startproc + 362 @ args = 0, pretend = 0, frame = 0 + 363 @ frame_needed = 0, uses_anonymous_args = 0 + 364 @ link register save eliminated. + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* Prevent unused argument(s) compilation warning */ + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** UNUSED(SemMask); + 365 .loc 1 425 3 view .LVU62 + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** /* NOTE : This function should not be modified, when the callback is needed, + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** the HAL_HSEM_FreeCallback can be implemented in the user file + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** */ + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 366 .loc 1 430 1 is_stmt 0 view .LVU63 + 367 0000 7047 bx lr + 368 .cfi_endproc + 369 .LFE151: + 371 .section .text.HAL_HSEM_IRQHandler,"ax",%progbits + 372 .align 1 + 373 .global HAL_HSEM_IRQHandler + 374 .syntax unified + 375 .thumb + 376 .thumb_func + 377 .fpu fpv5-d16 + 379 HAL_HSEM_IRQHandler: + 380 .LFB150: + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** uint32_t statusreg; + 381 .loc 1 377 1 is_stmt 1 view -0 + 382 .cfi_startproc + 383 @ args = 0, pretend = 0, frame = 0 + 384 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc8V8hSh.s page 15 + + + 385 0000 08B5 push {r3, lr} + 386 .LCFI0: + 387 .cfi_def_cfa_offset 8 + 388 .cfi_offset 3, -8 + 389 .cfi_offset 14, -4 + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** #if USE_MULTI_CORE_SHARED_CODE != 0U + 390 .loc 1 378 3 view .LVU65 + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 391 .loc 1 404 3 view .LVU66 + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 392 .loc 1 404 13 is_stmt 0 view .LVU67 + 393 0002 054B ldr r3, .L38 + 394 0004 D868 ldr r0, [r3, #12] + 395 .LVL19: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 396 .loc 1 407 3 is_stmt 1 view .LVU68 + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 397 .loc 1 407 20 is_stmt 0 view .LVU69 + 398 0006 1A68 ldr r2, [r3] + 399 0008 22EA0002 bic r2, r2, r0 + 400 000c 1A60 str r2, [r3] + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 401 .loc 1 410 3 is_stmt 1 view .LVU70 + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 402 .loc 1 410 20 is_stmt 0 view .LVU71 + 403 000e 5860 str r0, [r3, #4] + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** } + 404 .loc 1 414 3 is_stmt 1 view .LVU72 + 405 0010 FFF7FEFF bl HAL_HSEM_FreeCallback + 406 .LVL20: + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c **** + 407 .loc 1 415 1 is_stmt 0 view .LVU73 + 408 0014 08BD pop {r3, pc} + 409 .L39: + 410 0016 00BF .align 2 + 411 .L38: + 412 0018 00650258 .word 1476551936 + 413 .cfi_endproc + 414 .LFE150: + 416 .text + 417 .Letext0: + 418 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 419 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 420 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 421 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + ARM GAS /tmp/cc8V8hSh.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_hsem.c + /tmp/cc8V8hSh.s:17 .text.HAL_HSEM_Take:0000000000000000 $t + /tmp/cc8V8hSh.s:25 .text.HAL_HSEM_Take:0000000000000000 HAL_HSEM_Take + /tmp/cc8V8hSh.s:64 .text.HAL_HSEM_Take:000000000000001c $d + /tmp/cc8V8hSh.s:70 .text.HAL_HSEM_FastTake:0000000000000000 $t + /tmp/cc8V8hSh.s:77 .text.HAL_HSEM_FastTake:0000000000000000 HAL_HSEM_FastTake + /tmp/cc8V8hSh.s:110 .text.HAL_HSEM_FastTake:0000000000000018 $d + /tmp/cc8V8hSh.s:116 .text.HAL_HSEM_IsSemTaken:0000000000000000 $t + /tmp/cc8V8hSh.s:123 .text.HAL_HSEM_IsSemTaken:0000000000000000 HAL_HSEM_IsSemTaken + /tmp/cc8V8hSh.s:152 .text.HAL_HSEM_IsSemTaken:0000000000000014 $d + /tmp/cc8V8hSh.s:157 .text.HAL_HSEM_Release:0000000000000000 $t + /tmp/cc8V8hSh.s:164 .text.HAL_HSEM_Release:0000000000000000 HAL_HSEM_Release + /tmp/cc8V8hSh.s:186 .text.HAL_HSEM_Release:000000000000000c $d + /tmp/cc8V8hSh.s:191 .text.HAL_HSEM_ReleaseAll:0000000000000000 $t + /tmp/cc8V8hSh.s:198 .text.HAL_HSEM_ReleaseAll:0000000000000000 HAL_HSEM_ReleaseAll + /tmp/cc8V8hSh.s:222 .text.HAL_HSEM_ReleaseAll:0000000000000010 $d + /tmp/cc8V8hSh.s:227 .text.HAL_HSEM_SetClearKey:0000000000000000 $t + /tmp/cc8V8hSh.s:234 .text.HAL_HSEM_SetClearKey:0000000000000000 HAL_HSEM_SetClearKey + /tmp/cc8V8hSh.s:254 .text.HAL_HSEM_SetClearKey:0000000000000014 $d + /tmp/cc8V8hSh.s:259 .text.HAL_HSEM_GetClearKey:0000000000000000 $t + /tmp/cc8V8hSh.s:266 .text.HAL_HSEM_GetClearKey:0000000000000000 HAL_HSEM_GetClearKey + /tmp/cc8V8hSh.s:283 .text.HAL_HSEM_GetClearKey:000000000000000c $d + /tmp/cc8V8hSh.s:288 .text.HAL_HSEM_ActivateNotification:0000000000000000 $t + /tmp/cc8V8hSh.s:295 .text.HAL_HSEM_ActivateNotification:0000000000000000 HAL_HSEM_ActivateNotification + /tmp/cc8V8hSh.s:314 .text.HAL_HSEM_ActivateNotification:000000000000000c $d + /tmp/cc8V8hSh.s:319 .text.HAL_HSEM_DeactivateNotification:0000000000000000 $t + /tmp/cc8V8hSh.s:326 .text.HAL_HSEM_DeactivateNotification:0000000000000000 HAL_HSEM_DeactivateNotification + /tmp/cc8V8hSh.s:345 .text.HAL_HSEM_DeactivateNotification:000000000000000c $d + /tmp/cc8V8hSh.s:350 .text.HAL_HSEM_FreeCallback:0000000000000000 $t + /tmp/cc8V8hSh.s:357 .text.HAL_HSEM_FreeCallback:0000000000000000 HAL_HSEM_FreeCallback + /tmp/cc8V8hSh.s:372 .text.HAL_HSEM_IRQHandler:0000000000000000 $t + /tmp/cc8V8hSh.s:379 .text.HAL_HSEM_IRQHandler:0000000000000000 HAL_HSEM_IRQHandler + /tmp/cc8V8hSh.s:412 .text.HAL_HSEM_IRQHandler:0000000000000018 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_hsem.o b/build/stm32h7xx_hal_hsem.o new file mode 100644 index 0000000..daeed2b Binary files /dev/null and b/build/stm32h7xx_hal_hsem.o differ diff --git a/build/stm32h7xx_hal_i2c.d b/build/stm32h7xx_hal_i2c.d new file mode 100644 index 0000000..e6d7095 --- /dev/null +++ b/build/stm32h7xx_hal_i2c.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_i2c.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_i2c.lst b/build/stm32h7xx_hal_i2c.lst new file mode 100644 index 0000000..8cba821 --- /dev/null +++ b/build/stm32h7xx_hal_i2c.lst @@ -0,0 +1,25815 @@ +ARM GAS /tmp/ccEimIdZ.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_i2c.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.I2C_Flush_TXDR,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 I2C_Flush_TXDR: + 25 .LVL0: + 26 .LFB204: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @file stm32h7xx_hal_i2c.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * functionalities of the Inter Integrated Circuit (I2C) peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + IO operation functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + Peripheral State and Errors functions + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @verbatim + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ##### How to use this driver ##### + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ============================================================================== + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** The I2C HAL driver can be used as follows: + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) Declare a I2C_HandleTypeDef handle structure, for example: + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef hi2c; + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (##) Enable the I2Cx interface clock + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (##) I2C pins configuration + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Enable the clock for the I2C GPIOs + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Configure I2C pins as alternate function open-drain + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (##) NVIC configuration if you need to use interrupt process + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Configure the I2Cx interrupt priority + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Enable the NVIC I2C IRQ Channel + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (##) DMA Configuration if you need to use DMA process + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream o + ARM GAS /tmp/ccEimIdZ.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Enable the DMAx interface clock using + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Configure the DMA handle parameters + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Configure the DMA Tx or Rx stream or channel depends on Instance + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the DMA Tx or Rx stream or channel depends on Instance + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low le + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDevic + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** Polling mode IO operation *** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ================================= + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Tran + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Recei + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transm + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** Polling mode IO MEM operation *** + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ===================================== + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_ + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** Interrupt mode IO operation *** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =================================== + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_ + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback( + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_R + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user ca + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback( + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Tr + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Rec + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_I + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** Interrupt mode or DMA mode IO sequential operation *** + ARM GAS /tmp/ccEimIdZ.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ========================================================== + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (@) These interfaces allow to manage a sequential transfer with a repeated start condition + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** when a direction change during transfer + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) A specific option field manage the different steps of a sequential transfer + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfa + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and data to transfer without a final stop condition + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and data to transfer without a final stop condition, an then permit a c + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if no direction change and without a final stop condition in both cases + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if no direction change and with a final stop condition in both cases + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_T + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME th + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME the + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit o + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** without stopping the communication and so generate a restart conditio + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** interface. + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Usage can, transfer several bytes one by one with a restart with slave + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHE + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OT + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTH + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Differents sequential I2C interfaces are listed below: + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is e + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback( + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or using @ref HAL_I2C_Master_Seq_Receive_DMA() + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is exec + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback( + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Mas + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code to check the Address Match Code and the transmission direction request + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is ex + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + ARM GAS /tmp/ccEimIdZ.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref H + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is execu + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user ca + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** Interrupt mode IO MEM operation *** + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ======================================= + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Mem_Write_IT() + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user ca + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Mem_Read_IT() + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** DMA mode IO operation *** + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ============================== + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Master_Transmit_DMA() + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback( + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Master_Receive_DMA() + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user ca + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback( + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Slave_Transmit_DMA() + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Slave_Receive_DMA() + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_I + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** DMA mode IO MEM operation *** + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ================================= + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Mem_Write_DMA() + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user ca + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + ARM GAS /tmp/ccEimIdZ.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_Mem_Read_DMA() + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** I2C HAL driver macros list *** + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ================================== + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Below the list of most used macros in I2C HAL driver. + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *** Callback registration *** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ============================================= + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** allows the user to configure dynamically the driver callbacks. + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to register an interrupt callback. + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and a pointer to the user callback function. + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAdd + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** weak function. + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and the Callback ID. + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This function allows to reset following callbacks: + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + ARM GAS /tmp/ccEimIdZ.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallba + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** all callbacks are set to the corresponding weak functions: + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Exception done for MspInit and MspDeInit functions that are + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** these callbacks are null (not registered beforehand). + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or @ref HAL_I2C_Init() function. + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** not defined, the callback registration feature is not available and all callbacks + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** are set to the corresponding weak functions. + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (@) You can refer to the I2C HAL driver header file for more useful macros + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @endverbatim + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ****************************************************************************** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @attention + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *

© Copyright (c) 2017 STMicroelectronics. + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * All rights reserved.

+ 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This software component is licensed by ST under BSD 3-Clause license, + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the "License"; You may not use this file except in compliance with the + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * License. You may obtain a copy of the License at: + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * opensource.org/licenses/BSD-3-Clause + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ****************************************************************************** + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #include "stm32h7xx_hal.h" + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @addtogroup STM32H7xx_HAL_Driver + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C I2C + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C HAL module driver + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ + ARM GAS /tmp/ccEimIdZ.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/ + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define MAX_NBYTE_SIZE 255U + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define SlaveAddr_SHIFT 7U + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define SlaveAddr_MSK 0x06U + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */ + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | ( + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | ( + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | ( + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | ( + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | ( + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | ( + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */ + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_ + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_ + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_ + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of globa + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP eveneme + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NB + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */ + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME (0xFFFF0000U) + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private macro -------------------------------------------------------------*/ + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ + ARM GAS /tmp/ccEimIdZ.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private functions to handle DMA transfer */ + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma); + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint1 + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16 + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint3 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uin + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */ + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_ + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */ + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private function to treat different error callback */ + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private function to flush TXDR register */ + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private function to handle start, restart or stop a transfer */ + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Private function to Convert Specific options */ + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions + ARM GAS /tmp/ccEimIdZ.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Initialization and Configuration functions + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @verbatim + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =============================================================================== + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ##### Initialization and de-initialization functions ##### + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =============================================================================== + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] This subsection provides a set of functions allowing to initialize and + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** deinitialize the I2Cx peripheral: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) User must Implement HAL_I2C_MspInit() function in which he configures + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Call the function HAL_I2C_Init() to configure the selected device with + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the selected configuration: + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Clock Timing + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Own Address 1 + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Addressing mode (Master, Slave) + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Dual Addressing mode + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Own Address 2 + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Own Address 2 Mask + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) General call mode + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Nostretch mode + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (+) Call the function HAL_I2C_DeInit() to restore the default configuration + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** of the selected I2Cx peripheral. + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @endverbatim + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Initializes the I2C according to the specified parameters + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in the I2C_InitTypeDef and initialize the associated handle. + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c == NULL) + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + ARM GAS /tmp/ccEimIdZ.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_RESET) + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Allocate lock resource and initialize it */ + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Lock = HAL_UNLOCKED; + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init the I2C Callback settings */ + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->MspInitCallback == NULL) + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspInitCallback(hi2c); + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MspInit(hi2c); + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable the selected I2C peripheral */ + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Configure I2Cx: Frequency range */ + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Own Address1 before set the Own Address1 configuration */ + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Configure I2Cx: Own Address1 and ack own address1 mode */ + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else /* I2C_ADDRESSINGMODE_10BIT */ + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + ARM GAS /tmp/ccEimIdZ.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Configure I2Cx: Addressing Master mode */ + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Own Address2 before set the Own Address2 configuration */ + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Configure I2Cx: Dual mode and Own Address2 */ + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddr + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Configure I2Cx: Generalcall and NoStretch mode */ + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the selected I2C peripheral */ + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_ENABLE(hi2c); + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DeInitialize the I2C peripheral. + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c == NULL) + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable the I2C Peripheral Clock */ + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->MspDeInitCallback == NULL) + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspDeInitCallback(hi2c); + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MspDeInit(hi2c); + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Release Lock */ + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Initialize the I2C MSP. + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_MspInit could be implemented in the user file + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DeInitialize the I2C MSP. + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_MspDeInit could be implemented in the user file + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Register a User I2C Callback + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * To be used instead of the weak predefined callback + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/ccEimIdZ.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param CallbackID ID of the callback to be registered + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This parameter can be one of the following values: + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pCallback pointer to the Callback function + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (pCallback == NULL) + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process locked */ + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** switch (CallbackID) + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = pCallback; + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = pCallback; + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = pCallback; + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = pCallback; + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ListenCpltCallback = pCallback; + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemTxCpltCallback = pCallback; + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + ARM GAS /tmp/ccEimIdZ.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemRxCpltCallback = pCallback; + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCallback = pCallback; + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AbortCpltCallback = pCallback; + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** default : + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** switch (CallbackID) + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** default : + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + ARM GAS /tmp/ccEimIdZ.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Release Lock */ + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return status; + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Unregister an I2C Callback + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * I2C callback is redirected to the weak predefined callback + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param CallbackID ID of the callback to be unregistered + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This parameter can be one of the following values: + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This parameter can be one of the following values: + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process locked */ + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** switch (CallbackID) + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallba + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallba + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + ARM GAS /tmp/ccEimIdZ.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallbac + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** default : + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** switch (CallbackID) + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** default : + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** break; + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Release Lock */ + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return status; + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Register the Slave Address Match I2C Callback + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pCallback pointer to the Address Match Callback function + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (pCallback == NULL) + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process locked */ + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrCallback = pCallback; + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Release Lock */ + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return status; + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief UnRegister the Slave Address Match I2C Callback + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal + ARM GAS /tmp/ccEimIdZ.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process locked */ + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update the error code */ + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return error status */ + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** status = HAL_ERROR; + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Release Lock */ + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return status; + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Data transfers functions + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @verbatim + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =============================================================================== + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ##### IO operation functions ##### + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =============================================================================== + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This subsection provides a set of functions allowing to manage the I2C data + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** transfers. + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) There are two modes of transfer: + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) Blocking mode : The communication is performed in the polling mode. + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** The status of all data processing is returned by the same function + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** after finishing transfer. + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) No-Blocking mode : The communication is performed using Interrupts + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** or DMA. These functions return the status of the transfer startup. + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** The end of the data processing will be indicated through the + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** using DMA mode. + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) Blocking mode functions are : + ARM GAS /tmp/ccEimIdZ.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit() +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive() +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit() +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive() +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write() +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read() +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_IsDeviceReady() +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) No-Blocking mode functions with Interrupt are : +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_IT() +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_IT() +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_IT() +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_IT() +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_IT() +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_IT() +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_IT() +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_IT() +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_IT() +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_IT() +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_EnableListen_IT() +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_DisableListen_IT() +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Abort_IT() +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) No-Blocking mode functions with DMA are : +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_DMA() +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_DMA() +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_DMA() +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_DMA() +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_DMA() +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_DMA() +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_DMA() +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_DMA() +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_DMA() +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_DMA() +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_MasterTxCpltCallback() +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_MasterRxCpltCallback() +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_SlaveTxCpltCallback() +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_SlaveRxCpltCallback() +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_MemTxCpltCallback() +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_MemRxCpltCallback() +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_AddrCallback() +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_ListenCpltCallback() +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_ErrorCallback() +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (++) HAL_I2C_AbortCpltCallback() +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @endverbatim +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Transmits in master mode an amount of data in blocking mode. +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccEimIdZ.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write data to TXDR */ +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Receives in master mode an amount of data in blocking mode. +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccEimIdZ.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; + ARM GAS /tmp/ccEimIdZ.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Transmits in slave mode an amount of data in blocking mode. +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer + ARM GAS /tmp/ccEimIdZ.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, ui +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag */ +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If 10bit addressing mode is selected */ +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag */ +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + ARM GAS /tmp/ccEimIdZ.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until DIR flag is set Transmitter mode */ +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write data to TXDR */ +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Normal use case for Transmitter mode */ +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* A NACK is generated to confirm the end of transfer */ +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP flag */ +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in blocking mode +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uin +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until ADDR flag is set */ + ARM GAS /tmp/ccEimIdZ.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag */ +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until DIR flag is reset Receiver mode */ +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store Last receive data if any */ +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP flag */ +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRIT +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t * +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/ccEimIdZ.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; + ARM GAS /tmp/ccEimIdZ.s page 33 + + +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 34 + + +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_ +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 35 + + +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with DMA +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 36 + + +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART * +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 37 + + +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_ +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 38 + + +2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + ARM GAS /tmp/ccEimIdZ.s page 39 + + +2141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + ARM GAS /tmp/ccEimIdZ.s page 40 + + +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +2205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +2215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ + ARM GAS /tmp/ccEimIdZ.s page 41 + + +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Write an amount of data in blocking mode to a specific memory address +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre +2284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +2288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/ccEimIdZ.s page 42 + + +2312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +2317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL +2320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST +2331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS +2336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** do +2339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write data to TXDR */ +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +2348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +2351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +2354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + ARM GAS /tmp/ccEimIdZ.s page 43 + + +2369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST +2372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (hi2c->XferCount > 0U); +2377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +2386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Read an amount of data in blocking mode from a specific memory address +2407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +2416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +2421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +2423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + ARM GAS /tmp/ccEimIdZ.s page 44 + + +2426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +2452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_ +2455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +2462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S +2467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +2472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** do +2475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ + ARM GAS /tmp/ccEimIdZ.s page 45 + + +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +2484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +2487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +2490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_ST +2503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (hi2c->XferCount > 0U); +2512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + ARM GAS /tmp/ccEimIdZ.s page 46 + + +2540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory addres +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +2554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +2555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +2557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + ARM GAS /tmp/ccEimIdZ.s page 47 + + +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +2619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory addre +2632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +2646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +2648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 48 + + +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +2692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +2700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +2709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +2710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TX + ARM GAS /tmp/ccEimIdZ.s page 49 + + +2711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +2712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address +2722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA +2733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +2735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +2736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +2739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + ARM GAS /tmp/ccEimIdZ.s page 50 + + +2768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +2794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +2796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +2804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +2823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + ARM GAS /tmp/ccEimIdZ.s page 51 + + +2825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +2839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +2865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. +2866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be read +2874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +2875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +2876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +2879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +2880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 52 + + +2882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +2883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +2896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +2911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +2927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +2937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ + ARM GAS /tmp/ccEimIdZ.s page 53 + + +2939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +2947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +2961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_RE +2967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +2977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +2985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +2986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +2990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +2993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccEimIdZ.s page 54 + + +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +2997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +2998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +2999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Checks if target device is ready for communication. +3008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This function is used with Memory devices +3009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Trials Number of trials +3014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria +3018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; +3020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __IO uint32_t I2C_Trials = 0UL; +3022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** FlagStatus tmp1; +3024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** FlagStatus tmp2; +3025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +3029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** do +3040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Generate Start */ +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +3045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is set or a NACK flag is set*/ +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +3047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while ((tmp1 == RESET) && (tmp2 == RESET)) +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 55 + + +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +3054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) +3056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if the NACKF flag has not been set */ +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) +3076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +3084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Device is ready */ +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +3103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag, auto generated with autoend*/ +3106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if the maximum allowed number of trials has been reached */ + ARM GAS /tmp/ccEimIdZ.s page 56 + + +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_Trials == Trials) +3111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Generate Stop */ +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +3114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Trials */ +3126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Trials++; +3127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (I2C_Trials < Trials); +3129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte +3149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 57 + + +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, do not gene +3195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST +3197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; + ARM GAS /tmp/ccEimIdZ.s page 58 + + +3224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. +3233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin +3244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, do not gene +3280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ + ARM GAS /tmp/ccEimIdZ.s page 59 + + +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST +3282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +3303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +3305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> +3313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ + ARM GAS /tmp/ccEimIdZ.s page 60 + + +3338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +3347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +3348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +3370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +3371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +3372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +3381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_ +3382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +3386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter + ARM GAS /tmp/ccEimIdZ.s page 61 + + +3395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8 +3406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +3408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, do not gene +3441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST +3443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ + ARM GAS /tmp/ccEimIdZ.s page 62 + + +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +3468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +3470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA +3479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +3492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + ARM GAS /tmp/ccEimIdZ.s page 63 + + +3509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, do not gene +3526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST +3528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +3551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +3559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 64 + + +3566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +3581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +3593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Slave Address */ +3616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +3617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ +3618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process + ARM GAS /tmp/ccEimIdZ.s page 65 + + +3623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* possible to enable all of these */ +3627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_ +3628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +3632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +3636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +3650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable associated Interrupts */ +3673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 66 + + +3680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA RX */ +3687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +3697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +3709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +3711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +3713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +3714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* REnable ADDR interrupt */ +3724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +3725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +3727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during + ARM GAS /tmp/ccEimIdZ.s page 67 + + +3737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t +3745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable associated Interrupts */ +3770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA RX */ +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +3793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 68 + + +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +3795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +3797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +3804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA TX */ +3806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +3807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +3810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +3817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +3820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +3832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +3837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +3839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +3846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +3847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ + ARM GAS /tmp/ccEimIdZ.s page 69 + + +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +3866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset XferSize */ +3869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = 0; +3870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +3872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +3874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +3878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +3887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +3889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +3890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +3900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +3901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +3904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +3906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + ARM GAS /tmp/ccEimIdZ.s page 70 + + +3908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +3914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +3915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +3922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +3923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si +3924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +3926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +3934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +3938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +3944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +3945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable associated Interrupts */ +3947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +3948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +3950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +3959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA TX */ +3961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +3962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + ARM GAS /tmp/ccEimIdZ.s page 71 + + +3965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +3971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +3980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +3983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +3985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +3986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +3987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +3990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +3992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +3994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +3997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* REnable ADDR interrupt */ +3998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +3999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +4005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param pData Pointer to data buffer +4014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Amount of data to be sent +4015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +4019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +4021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 72 + + +4022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +4023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +4031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable associated Interrupts */ +4044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA TX */ +4058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +4067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +4069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +4078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 73 + + +4079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA RX */ +4080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +4081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +4084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +4091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare transfer parameters */ +4101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; +4103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +4106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +4111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the DMA error callback */ +4113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +4114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +4117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +4118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +4120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +4121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +4125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +4129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +4132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +4135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 74 + + +4136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +4138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +4140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +4141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset XferSize */ +4143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = 0; +4144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C state */ +4148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update I2C error code */ +4152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +4155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +4158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +4161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +4168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +4173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +4177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +4178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +4184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Enable the Address listen mode with Interrupt. +4189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + ARM GAS /tmp/ccEimIdZ.s page 75 + + +4193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +4194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +4196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the Address Match interrupt */ +4201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +4208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Disable the Address listen mode with Interrupt. +4213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C +4215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +4218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmp; +4221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address listen mode only if a transfer is not ongoing */ +4223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +4224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; +4226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); +4227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +4230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable the Address Match interrupt */ +4232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_BUSY; +4239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Abort a master I2C IT or DMA process communication with Interrupt. +4244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +4247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +4248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + ARM GAS /tmp/ccEimIdZ.s page 76 + + +4250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +4251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) +4253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +4258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +4259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +4262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +4266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +4267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Do nothing */ +4271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set State at HAL_I2C_STATE_ABORT */ +4274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_ABORT; +4275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ +4277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe +4278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); +4279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +4281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** process unlock */ +4286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wrong usage of abort function */ +4293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* This function should be used only in case of abort monitored by master device */ +4294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +4295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} +4300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +4303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ +4304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + ARM GAS /tmp/ccEimIdZ.s page 77 + + +4307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles I2C event interrupt request. +4308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +4313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ +4315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C events treatment -------------------------------------*/ +4319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferISR != NULL) +4320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR(hi2c, itflags, itsources); +4322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles I2C error interrupt request. +4327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +4332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmperror; +4336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C Bus error interrupt occurred ------------------------------------*/ +4338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_E +4339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; +4341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear BERR flag */ +4343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); +4344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ +4347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ER +4348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; +4350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear OVR flag */ +4352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); +4353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ +4356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_E +4357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; +4359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ARLO flag */ +4361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); +4362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 78 + + +4364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +4365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +4366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the Error Callback in case of Error detected */ +4368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_ +4369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, tmperror); +4371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Master Tx Transfer completed callback. +4376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +4381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_MasterTxCpltCallback could be implemented in the user file +4387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Master Rx Transfer completed callback. +4392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +4397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_MasterRxCpltCallback could be implemented in the user file +4403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @brief Slave Tx Transfer completed callback. +4407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +4412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file +4418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 79 + + +4421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Slave Rx Transfer completed callback. +4423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +4428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file +4434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Slave Address Match callback. +4439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE +4442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param AddrMatchCode Address Match Code +4443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM +4446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(TransferDirection); +4450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(AddrMatchCode); +4451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_AddrCallback() could be implemented in the user file +4454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Listen Complete callback. +4459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +4464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_ListenCpltCallback() could be implemented in the user file +4470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Memory Tx Transfer completed callback. +4475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None + ARM GAS /tmp/ccEimIdZ.s page 80 + + +4478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +4480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_MemTxCpltCallback could be implemented in the user file +4486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Memory Rx Transfer completed callback. +4491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +4496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_MemRxCpltCallback could be implemented in the user file +4502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C error callback. +4507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +4512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_ErrorCallback could be implemented in the user file +4518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C abort callback. +4523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +4526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +4528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(hi2c); +4531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** the HAL_I2C_AbortCpltCallback could be implemented in the user file +4534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ + ARM GAS /tmp/ccEimIdZ.s page 81 + + +4535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} +4539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions +4542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Peripheral State, Mode and Error functions +4543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * +4544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @verbatim +4545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =============================================================================== +4546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ##### Peripheral State, Mode and Error functions ##### +4547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** =============================================================================== +4548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** [..] +4549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** This subsection permit to get in run-time the status of the peripheral +4550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** and the data flow. +4551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** @endverbatim +4553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ +4554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Return the I2C handle state. +4558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL state +4561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +4563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return I2C handle state */ +4565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return hi2c->State; +4566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Returns the I2C Master, Slave, Memory or no mode. +4570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for I2C module +4572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL mode +4573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +4575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return hi2c->Mode; +4577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Return the I2C error code. +4581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval I2C Error Code +4584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +4586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return hi2c->ErrorCode; +4588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} + ARM GAS /tmp/ccEimIdZ.s page 82 + + +4592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @} +4596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions +4599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @{ +4600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. +4604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint +4611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t devaddress; +4613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +4616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ +4619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +4621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set corresponding Error Code */ +4624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +4629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, +4632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +4634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +4635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +4637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +4640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +4641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +4643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +4644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, +4646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write data to TXDR */ +4648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + ARM GAS /tmp/ccEimIdZ.s page 83 + + +4649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +4651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +4652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +4654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +4655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I +4657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +4659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +4661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +4663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +4665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START +4666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +4671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_S +4673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST +4677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +4683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +4691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2 +4697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +4703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +4704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Generate Stop */ + ARM GAS /tmp/ccEimIdZ.s page 84 + + +4706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +4707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +4718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +4725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_ +4728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Master complete process */ +4730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); +4731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +4734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. +4741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint3 +4748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +4750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process locked */ +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if STOPF is set */ +4756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_ +4757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave complete process */ +4759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, tmpITFlags); +4760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ + ARM GAS /tmp/ccEimIdZ.s page 85 + + +4763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check that I2C transfer finished */ +4765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +4766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean XferCount == 0*/ +4767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* So clear Flag NACKF only */ +4768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Sam +4771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +4773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +4774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME) +4776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +4778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +4781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +4784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +4790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +4796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +4797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +4800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +4803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +4806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, +4810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +4812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +4814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +4817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +4818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccEimIdZ.s page 86 + + +4820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +4821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferCount == 0U) && \ +4824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +4825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, +4831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, tmpITFlags); +4833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, +4835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write data to TXDR only if XferCount not reach "0" */ +4837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* A TXIS flag can be set, during STOP treatment */ +4838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if all Datas have already been sent */ +4839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ +4840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +4841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write data to TXDR */ +4843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +4844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +4846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +4847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +4849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +4850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +4854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +4856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +4864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +4867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +4870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +4873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. +4874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. + ARM GAS /tmp/ccEimIdZ.s page 87 + + +4877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +4879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +4880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uin +4881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t devaddress; +4883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; +4884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Locked */ +4886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NAC +4889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +4891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set corresponding Error Code */ +4894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +4898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +4902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_ +4905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable TC interrupt */ +4907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); +4908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +4910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Recover Slave address */ +4912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +4913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +4915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +4916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +4918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +4919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +4924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +4926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +4930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the new XferSize in Nbytes register */ + ARM GAS /tmp/ccEimIdZ.s page 88 + + +4934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +4935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update XferCount value */ +4937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +4938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +4939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable DMA Request */ +4940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +4943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +4947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +4952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +4960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_I +4966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +4972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +4973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Generate Stop */ +4975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +4976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +4987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 89 + + +4991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2 +4992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Master complete process */ +4994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +4995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +4996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +4997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +4998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +4999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +5005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. +5009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +5014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint +5016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +5018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t treatdmanack = 0U; +5019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; +5020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process locked */ +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if STOPF is set */ +5025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ +5026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); +5029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NAC +5032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean XferCount == 0 */ +5036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || +5038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) +5039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Split check of hdmarx, for MISRA compliance */ +5041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) +5044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) +5046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** treatdmanack = 1U; + ARM GAS /tmp/ccEimIdZ.s page 90 + + +5048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Split check of hdmatx, for MISRA compliance */ +5053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) +5056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) +5058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** treatdmanack = 1U; +5060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (treatdmanack == 1U) +5065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* S +5067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); +5070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM +5072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +5074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +5077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +5086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +5093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ +5099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpstate = hi2c->State; +5100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +5102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 91 + + +5105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN +5108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Do nothing */ +5114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Only Clear NACK Flag, no DMA treatment is pending */ +5124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C +5128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, ITFlags); +5130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +5134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +5140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for write reques +5144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +5149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +5151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +5152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +5153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint1 +5155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI +5157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccEimIdZ.s page 92 + + +5162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Memory Address */ +5168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +5180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +5187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) +5188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +5190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +5193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for read request +5197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddress Internal memory address +5202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +5204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +5205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +5206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16 +5208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR +5210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +5215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + ARM GAS /tmp/ccEimIdZ.s page 93 + + +5219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send Memory Address */ +5221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +5233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until TC flag is set */ +5240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) +5241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +5243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +5246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Address complete process callback. +5250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint8_t transferdirection; +5257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t slaveaddrcode; +5258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t ownadd1code; +5259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t ownadd2code; +5260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +5262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(ITFlags); +5263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* In case of Listen state, need to inform upper layer of address match code event */ +5265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +5266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** transferdirection = I2C_GET_DIR(hi2c); +5268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); +5269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); +5270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); +5271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If 10bits addressing mode is selected */ +5273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +5274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + ARM GAS /tmp/ccEimIdZ.s page 94 + + +5276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** slaveaddrcode = ownadd1code; +5278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrEventCount++; +5279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) +5280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset Address Event counter */ +5282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrEventCount = 0U; +5283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag */ +5285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Slave Addr callback */ +5291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** slaveaddrcode = ownadd2code; +5301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Slave Addr callback */ +5309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* else 7 bits addressing mode is selected */ +5317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Slave Addr callback */ +5326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 95 + + +5333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Else clear address flag only */ +5334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear ADDR flag */ +5337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Master sequential complete process. +5346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +5350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset I2C handle mode */ +5352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No Generate Stop, to permit restart mode */ +5355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ +5356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +5360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +5361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts */ +5363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +5373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +5381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts */ +5383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/ccEimIdZ.s page 96 + + +5390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Slave sequential complete process. +5399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +5403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); +5405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset I2C handle mode */ +5407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +5411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +5413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +5416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +5418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Do nothing */ +5423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +5426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ +5428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts */ +5432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +5442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +5446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 97 + + +5447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ +5448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts */ +5452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +5462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +5467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Master complete process. +5472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmperror; +5479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __IO uint32_t tmpreg; +5481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +5483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +5484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +5490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Do nothing */ +5499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +5502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +5503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 98 + + +5504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset handle parameters */ +5505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +5506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) +5509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +5511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set acknowledge error code */ +5514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Fetch Last receive data if any */ +5518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) +5519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +5521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpreg = (uint8_t)hi2c->Instance->RXDR; +5522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(tmpreg); +5523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +5526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +5529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +5530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) +5533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ +5538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +5544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemTxCpltCallback(hi2c); +5553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MemTxCpltCallback(hi2c); +5555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 99 + + +5561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +5569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +5579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MemRxCpltCallback(hi2c); +5588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MemRxCpltCallback(hi2c); +5590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +5610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Slave complete process. +5615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None + ARM GAS /tmp/ccEimIdZ.s page 100 + + +5618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); +5622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +5624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +5626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +5627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +5632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +5635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +5637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Do nothing */ +5642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +5645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +5646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +5648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +5649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +5651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +5655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +5657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); +5662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +5665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +5667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); +5672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else + ARM GAS /tmp/ccEimIdZ.s page 101 + + +5675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Do nothing */ +5677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store Last receive data if any */ +5680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) +5681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +5683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +5684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +5686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +5689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +5690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +5692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +5694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +5695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* All data are not transferred, so set error code accordingly */ +5699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +5707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) +5709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +5715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +5718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ +5723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 102 + + +5732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +5735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +5737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +5753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +5768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Listen complete process. +5774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset handle parameters */ +5781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +5786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store Last receive data if any */ +5788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + ARM GAS /tmp/ccEimIdZ.s page 103 + + +5789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Read data from RXDR */ +5791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Increment Buffer pointer */ +5794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr++; +5795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +5797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; +5799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; +5800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable all Interrupts*/ +5807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +5808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACK Flag */ +5810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +5818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +5820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C interrupts error process. +5825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param ErrorCode Error code to handle. +5827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +5830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +5832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmppreviousstate; +5833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset handle parameters */ +5835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = 0U; +5838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set new error code */ +5840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= ErrorCode; +5841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Interrupts */ +5843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_LISTEN) || +5844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || +5845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + ARM GAS /tmp/ccEimIdZ.s page 104 + + +5846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable all interrupts, except interrupts related to LISTEN state */ +5848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); +5849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* keep HAL_I2C_STATE_LISTEN if set */ +5851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +5853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable all interrupts */ +5857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +5858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If state is an abort treatment on goind, don't change state */ +5860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* This change will be do later */ +5861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State != HAL_I2C_STATE_ABORT) +5862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set HAL_I2C_STATE_READY */ +5864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; +5867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA TX transfer if any */ +5870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmppreviousstate = hi2c->PreviousState; +5871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstat +5872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +5874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) +5879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +5881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +5882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +5883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA TX */ +5888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +5889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +5891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +5892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +5897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA RX transfer if any */ +5900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviou +5901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + ARM GAS /tmp/ccEimIdZ.s page 105 + + +5903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) +5908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +5910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +5911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +5912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Abort DMA RX */ +5917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +5918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ +5920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +5921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +5926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +5931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Error callback treatment. +5936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +5940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) +5942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AbortCpltCallback(hi2c); +5952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); +5954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +5957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 106 + + +5960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +5961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCallback(hi2c); +5966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #else +5967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +5968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief I2C Tx data register flush process. +5974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +5975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +5978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 28 .loc 1 5978 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +5979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If a pending TXIS flag is set */ +5980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Write a dummy data in TXDR to clear it */ +5981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 33 .loc 1 5981 3 view .LVU1 + 34 .loc 1 5981 7 is_stmt 0 view .LVU2 + 35 0000 0368 ldr r3, [r0] + 36 0002 9A69 ldr r2, [r3, #24] + 37 .loc 1 5981 6 view .LVU3 + 38 0004 12F0020F tst r2, #2 + 39 0008 01D0 beq .L2 +5982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->TXDR = 0x00U; + 40 .loc 1 5983 5 is_stmt 1 view .LVU4 + 41 .loc 1 5983 26 is_stmt 0 view .LVU5 + 42 000a 0022 movs r2, #0 + 43 000c 9A62 str r2, [r3, #40] + 44 .L2: +5984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register if not empty */ +5987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 45 .loc 1 5987 3 is_stmt 1 view .LVU6 + 46 .loc 1 5987 7 is_stmt 0 view .LVU7 + 47 000e 0368 ldr r3, [r0] + 48 0010 9A69 ldr r2, [r3, #24] + 49 .loc 1 5987 6 view .LVU8 + 50 0012 12F0010F tst r2, #1 + 51 0016 03D1 bne .L1 +5988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +5989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 52 .loc 1 5989 5 is_stmt 1 view .LVU9 + 53 0018 9A69 ldr r2, [r3, #24] + 54 001a 42F00102 orr r2, r2, #1 + ARM GAS /tmp/ccEimIdZ.s page 107 + + + 55 001e 9A61 str r2, [r3, #24] + 56 .L1: +5990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +5991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 57 .loc 1 5991 1 is_stmt 0 view .LVU10 + 58 0020 7047 bx lr + 59 .cfi_endproc + 60 .LFE204: + 62 .section .text.I2C_TransferConfig,"ax",%progbits + 63 .align 1 + 64 .syntax unified + 65 .thumb + 66 .thumb_func + 67 .fpu fpv5-d16 + 69 I2C_TransferConfig: + 70 .LVL1: + 71 .LFB216: +5992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +5993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +5994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DMA I2C master transmit process complete callback. +5995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hdma DMA handle +5996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +5997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +5998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +5999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +6001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +6003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable STOP interrupt */ +6009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update Buffer pointer */ +6015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +6028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, h +6029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + ARM GAS /tmp/ccEimIdZ.s page 108 + + +6032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable TC interrupts */ +6036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DMA I2C slave transmit process complete callback. +6043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hdma DMA handle +6044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +6047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +6049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +6052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +6054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +6057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DMA I2C master receive process complete callback. +6070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hdma DMA handle +6071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +6074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +6076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +6078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable STOP interrupt */ +6084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 109 + + +6089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Update Buffer pointer */ +6090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable the DMA stream or channel depends on Instance */ +6103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, h +6104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable TC interrupts */ +6111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DMA I2C slave receive process complete callback. +6118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hdma DMA handle +6119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +6122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +6124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ +6127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +6128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable DMA Request */ +6130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DMA I2C communication error callback. +6145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hdma DMA handle + ARM GAS /tmp/ccEimIdZ.s page 110 + + +6146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma) +6149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t treatdmaerror = 0U; +6151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +6152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) +6156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** treatdmaerror = 1U; +6158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) +6164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** treatdmaerror = 1U; +6166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform * +6170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) +6171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable Acknowledge */ +6173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +6174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief DMA I2C communication abort callback +6182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * (To be called at end of DMA Abort procedure). +6183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hdma DMA handle. +6184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +6187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +6189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset AbortCpltCallback */ +6191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +6194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +6198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 111 + + +6203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout. +6205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Flag Specifies the I2C flag to check. +6208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Status The new Flag status (SET or RESET). +6209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +6210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +6211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +6212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta +6214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) +6216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check for the Timeout */ +6218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +6233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. +6237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +6240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +6241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +6242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) +6246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if a NACK is detected */ +6248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check for the Timeout */ +6254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/ccEimIdZ.s page 112 + + +6260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +6270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. +6274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +6277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +6278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +6279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +6283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if a NACK is detected */ +6285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check for the Timeout */ +6291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +6304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. +6308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration +6311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +6312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +6313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + ARM GAS /tmp/ccEimIdZ.s page 113 + + +6317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if a NACK is detected */ +6319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if a STOPF is detected */ +6325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) +6326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check if an RXNE is pending */ +6328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Store Last receive data if any */ +6329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) +6330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return HAL_OK */ +6332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* The Reading of data from RXDR will be done in caller function */ +6333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +6334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +6338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +6344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check for the Timeout */ +6355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +6367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief This function handles Acknowledge failed detection during an I2C Communication. +6371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Timeout Timeout duration + ARM GAS /tmp/ccEimIdZ.s page 114 + + +6374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Tickstart Tick start value +6375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval HAL status +6376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_ +6378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) +6380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Wait until STOP Flag is reset */ +6382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* AutoEnd should be initiate after AF */ +6383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +6384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check for the Timeout */ +6386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear NACKF Flag */ +6403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear STOP Flag */ +6406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Flush TX register */ +6409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Process Unlocked */ +6419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; +6422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_OK; +6424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar +6428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +6429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param DevAddress Specifies the slave address to be programmed. +6430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Size Specifies the number of bytes to be programmed. + ARM GAS /tmp/ccEimIdZ.s page 115 + + +6431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This parameter must be a value between 0 and 255. +6432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Mode New state of the I2C START condition generation. +6433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This parameter can be one of the following values: +6434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_RELOAD_MODE Enable Reload mode . +6435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. +6436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. +6437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param Request New state of the I2C START condition generation. +6438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * This parameter can be one of the following values: +6439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. +6440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). +6441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. +6442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. +6443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t +6446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 72 .loc 1 6446 1 is_stmt 1 view -0 + 73 .cfi_startproc + 74 @ args = 4, pretend = 0, frame = 0 + 75 @ frame_needed = 0, uses_anonymous_args = 0 + 76 @ link register save eliminated. + 77 .loc 1 6446 1 is_stmt 0 view .LVU12 + 78 0000 30B4 push {r4, r5} + 79 .LCFI0: + 80 .cfi_def_cfa_offset 8 + 81 .cfi_offset 4, -8 + 82 .cfi_offset 5, -4 + 83 0002 029D ldr r5, [sp, #8] +6447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ +6448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 84 .loc 1 6448 3 is_stmt 1 view .LVU13 +6449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_TRANSFER_MODE(Mode)); + 85 .loc 1 6449 3 view .LVU14 +6450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_TRANSFER_REQUEST(Request)); + 86 .loc 1 6450 3 view .LVU15 +6451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* update CR2 register */ +6453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEN + 87 .loc 1 6453 3 view .LVU16 + 88 0004 0468 ldr r4, [r0] + 89 0006 6068 ldr r0, [r4, #4] + 90 .LVL2: + 91 .loc 1 6453 3 is_stmt 0 view .LVU17 + 92 0008 4FEA555C lsr ip, r5, #21 + 93 000c 0CF4806C and ip, ip, #1024 + 94 0010 4CF07F7C orr ip, ip, #66846720 + 95 0014 4CF4583C orr ip, ip, #221184 + 96 0018 4CF47F7C orr ip, ip, #1020 + 97 001c 4CF0030C orr ip, ip, #3 + 98 0020 20EA0C00 bic r0, r0, ip + 99 0024 C1F30901 ubfx r1, r1, #0, #10 + 100 .LVL3: + 101 .loc 1 6453 3 view .LVU18 + 102 0028 41EA0241 orr r1, r1, r2, lsl #16 + 103 002c 1943 orrs r1, r1, r3 + 104 002e 2943 orrs r1, r1, r5 + 105 0030 0143 orrs r1, r1, r0 + ARM GAS /tmp/ccEimIdZ.s page 116 + + + 106 0032 6160 str r1, [r4, #4] +6454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_ +6455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 107 .loc 1 6455 1 view .LVU19 + 108 0034 30BC pop {r4, r5} + 109 .LCFI1: + 110 .cfi_restore 5 + 111 .cfi_restore 4 + 112 .cfi_def_cfa_offset 0 + 113 .LVL4: + 114 .loc 1 6455 1 view .LVU20 + 115 0036 7047 bx lr + 116 .cfi_endproc + 117 .LFE216: + 119 .section .text.I2C_Enable_IRQ,"ax",%progbits + 120 .align 1 + 121 .syntax unified + 122 .thumb + 123 .thumb_func + 124 .fpu fpv5-d16 + 126 I2C_Enable_IRQ: + 127 .LVL5: + 128 .LFB217: +6456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Manage the enabling of Interrupts. +6459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +6462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +6465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 129 .loc 1 6465 1 is_stmt 1 view -0 + 130 .cfi_startproc + 131 @ args = 0, pretend = 0, frame = 0 + 132 @ frame_needed = 0, uses_anonymous_args = 0 + 133 @ link register save eliminated. +6466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 134 .loc 1 6466 3 view .LVU22 +6467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + 135 .loc 1 6468 3 view .LVU23 + 136 .loc 1 6468 12 is_stmt 0 view .LVU24 + 137 0000 436B ldr r3, [r0, #52] + 138 .loc 1 6468 6 view .LVU25 + 139 0002 1A4A ldr r2, .L21 + 140 0004 9342 cmp r3, r2 + 141 0006 15D0 beq .L7 + 142 .loc 1 6468 45 discriminator 1 view .LVU26 + 143 0008 194A ldr r2, .L21+4 + 144 000a 9342 cmp r3, r2 + 145 000c 12D0 beq .L7 +6469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) +6470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) +6472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 117 + + +6473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +6474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) +6478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +6480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +6481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) +6484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable STOP interrupts */ +6486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); +6487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) +6490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable TC interrupts */ +6492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +6493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 146 .loc 1 6497 5 is_stmt 1 view .LVU27 + 147 .loc 1 6497 8 is_stmt 0 view .LVU28 + 148 000e 11F4004F tst r1, #32768 + 149 0012 29D1 bne .L17 +6466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 150 .loc 1 6466 12 view .LVU29 + 151 0014 0023 movs r3, #0 + 152 .L13: + 153 .LVL6: +6498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, and ADDR interrupts */ +6500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 154 .loc 1 6503 5 is_stmt 1 view .LVU30 + 155 .loc 1 6503 8 is_stmt 0 view .LVU31 + 156 0016 11F0010F tst r1, #1 + 157 001a 01D0 beq .L14 +6504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +6506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 158 .loc 1 6506 7 is_stmt 1 view .LVU32 + 159 .loc 1 6506 14 is_stmt 0 view .LVU33 + 160 001c 43F0F203 orr r3, r3, #242 + 161 .LVL7: + 162 .L14: +6507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 163 .loc 1 6509 5 is_stmt 1 view .LVU34 + 164 .loc 1 6509 8 is_stmt 0 view .LVU35 + ARM GAS /tmp/ccEimIdZ.s page 118 + + + 165 0020 11F0020F tst r1, #2 + 166 0024 01D0 beq .L15 +6510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +6512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 167 .loc 1 6512 7 is_stmt 1 view .LVU36 + 168 .loc 1 6512 14 is_stmt 0 view .LVU37 + 169 0026 43F0F403 orr r3, r3, #244 + 170 .LVL8: + 171 .L15: +6513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 172 .loc 1 6515 5 is_stmt 1 view .LVU38 + 173 .loc 1 6515 8 is_stmt 0 view .LVU39 + 174 002a 2029 cmp r1, #32 + 175 002c 0CD1 bne .L12 +6516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable STOP interrupts */ +6518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; + 176 .loc 1 6518 7 is_stmt 1 view .LVU40 + 177 .loc 1 6518 14 is_stmt 0 view .LVU41 + 178 002e 43F02003 orr r3, r3, #32 + 179 .LVL9: + 180 .loc 1 6518 14 view .LVU42 + 181 0032 09E0 b .L12 + 182 .LVL10: + 183 .L7: +6471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 184 .loc 1 6471 5 is_stmt 1 view .LVU43 +6471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 185 .loc 1 6471 8 is_stmt 0 view .LVU44 + 186 0034 11F4004F tst r1, #32768 + 187 0038 0BD1 bne .L16 +6466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 188 .loc 1 6466 12 view .LVU45 + 189 003a 0023 movs r3, #0 + 190 .L9: + 191 .LVL11: +6477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 192 .loc 1 6477 5 is_stmt 1 view .LVU46 +6477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 193 .loc 1 6477 8 is_stmt 0 view .LVU47 + 194 003c 1029 cmp r1, #16 + 195 003e 0AD0 beq .L18 + 196 .L10: +6483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 197 .loc 1 6483 5 is_stmt 1 view .LVU48 +6483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 198 .loc 1 6483 8 is_stmt 0 view .LVU49 + 199 0040 2029 cmp r1, #32 + 200 0042 0BD0 beq .L19 + 201 .L11: +6489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 202 .loc 1 6489 5 is_stmt 1 view .LVU50 +6489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 203 .loc 1 6489 8 is_stmt 0 view .LVU51 + ARM GAS /tmp/ccEimIdZ.s page 119 + + + 204 0044 4029 cmp r1, #64 + 205 0046 0CD0 beq .L20 + 206 .L12: +6519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable interrupts only at the end */ +6523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* to avoid the risk of I2C interrupt handle execution before */ +6524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* all interrupts requested done */ +6525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + 207 .loc 1 6525 3 is_stmt 1 view .LVU52 + 208 0048 0168 ldr r1, [r0] + 209 .LVL12: + 210 .loc 1 6525 3 is_stmt 0 view .LVU53 + 211 004a 0A68 ldr r2, [r1] + 212 004c 1343 orrs r3, r3, r2 + 213 .LVL13: + 214 .loc 1 6525 3 view .LVU54 + 215 004e 0B60 str r3, [r1] +6526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 216 .loc 1 6526 1 view .LVU55 + 217 0050 7047 bx lr + 218 .LVL14: + 219 .L16: +6474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 220 .loc 1 6474 14 view .LVU56 + 221 0052 B823 movs r3, #184 + 222 0054 F2E7 b .L9 + 223 .LVL15: + 224 .L18: +6480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 225 .loc 1 6480 7 is_stmt 1 view .LVU57 +6480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 226 .loc 1 6480 14 is_stmt 0 view .LVU58 + 227 0056 43F09003 orr r3, r3, #144 + 228 .LVL16: +6480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 229 .loc 1 6480 14 view .LVU59 + 230 005a F1E7 b .L10 + 231 .L19: +6486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 232 .loc 1 6486 7 is_stmt 1 view .LVU60 +6486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 233 .loc 1 6486 14 is_stmt 0 view .LVU61 + 234 005c 43F06003 orr r3, r3, #96 + 235 .LVL17: +6486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 236 .loc 1 6486 14 view .LVU62 + 237 0060 F0E7 b .L11 + 238 .L20: +6492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 239 .loc 1 6492 7 is_stmt 1 view .LVU63 +6492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 240 .loc 1 6492 14 is_stmt 0 view .LVU64 + 241 0062 43F04003 orr r3, r3, #64 + 242 .LVL18: +6492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 120 + + + 243 .loc 1 6492 14 view .LVU65 + 244 0066 EFE7 b .L12 + 245 .LVL19: + 246 .L17: +6500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 247 .loc 1 6500 14 view .LVU66 + 248 0068 B823 movs r3, #184 + 249 006a D4E7 b .L13 + 250 .L22: + 251 .align 2 + 252 .L21: + 253 006c 00000000 .word I2C_Master_ISR_DMA + 254 0070 00000000 .word I2C_Slave_ISR_DMA + 255 .cfi_endproc + 256 .LFE217: + 258 .section .text.I2C_Disable_IRQ,"ax",%progbits + 259 .align 1 + 260 .syntax unified + 261 .thumb + 262 .thumb_func + 263 .fpu fpv5-d16 + 265 I2C_Disable_IRQ: + 266 .LVL20: + 267 .LFB218: +6527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Manage the disabling of Interrupts. +6530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * the configuration information for the specified I2C. +6532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +6533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +6536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 268 .loc 1 6536 1 is_stmt 1 view -0 + 269 .cfi_startproc + 270 @ args = 0, pretend = 0, frame = 0 + 271 @ frame_needed = 0, uses_anonymous_args = 0 + 272 @ link register save eliminated. +6537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 273 .loc 1 6537 3 view .LVU68 +6538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 274 .loc 1 6539 3 view .LVU69 + 275 .loc 1 6539 6 is_stmt 0 view .LVU70 + 276 0000 11F0010F tst r1, #1 + 277 0004 09D0 beq .L30 +6540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable TC and TXI interrupts */ +6542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + 278 .loc 1 6542 5 is_stmt 1 view .LVU71 + 279 .LVL21: +6543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 280 .loc 1 6544 5 view .LVU72 + 281 .loc 1 6544 24 is_stmt 0 view .LVU73 + 282 0006 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + ARM GAS /tmp/ccEimIdZ.s page 121 + + + 283 .loc 1 6544 8 view .LVU74 + 284 000a 03F02803 and r3, r3, #40 + 285 000e 282B cmp r3, #40 + 286 0010 01D0 beq .L33 +6545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +6547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 287 .loc 1 6547 14 view .LVU75 + 288 0012 F223 movs r3, #242 + 289 0014 02E0 b .L24 + 290 .L33: +6542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 291 .loc 1 6542 12 view .LVU76 + 292 0016 4223 movs r3, #66 + 293 0018 00E0 b .L24 + 294 .LVL22: + 295 .L30: +6537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 296 .loc 1 6537 12 view .LVU77 + 297 001a 0023 movs r3, #0 + 298 .LVL23: + 299 .L24: +6548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 300 .loc 1 6551 3 is_stmt 1 view .LVU78 + 301 .loc 1 6551 6 is_stmt 0 view .LVU79 + 302 001c 11F0020F tst r1, #2 + 303 0020 09D0 beq .L25 +6552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable TC and RXI interrupts */ +6554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 304 .loc 1 6554 5 is_stmt 1 view .LVU80 + 305 .loc 1 6554 12 is_stmt 0 view .LVU81 + 306 0022 43F0440C orr ip, r3, #68 + 307 .LVL24: +6555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 308 .loc 1 6556 5 is_stmt 1 view .LVU82 + 309 .loc 1 6556 24 is_stmt 0 view .LVU83 + 310 0026 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 311 .loc 1 6556 8 view .LVU84 + 312 002a 02F02802 and r2, r2, #40 + 313 002e 282A cmp r2, #40 + 314 0030 10D0 beq .L32 +6557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +6559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 315 .loc 1 6559 7 is_stmt 1 view .LVU85 + 316 .loc 1 6559 14 is_stmt 0 view .LVU86 + 317 0032 43F0F403 orr r3, r3, #244 + 318 .LVL25: + 319 .L25: +6560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 122 + + +6563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 320 .loc 1 6563 3 is_stmt 1 view .LVU87 + 321 .loc 1 6563 6 is_stmt 0 view .LVU88 + 322 0036 11F4004F tst r1, #32768 + 323 003a 0DD1 bne .L34 + 324 .L26: +6564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable ADDR, NACK and STOP interrupts */ +6566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 325 .loc 1 6569 3 is_stmt 1 view .LVU89 + 326 .loc 1 6569 6 is_stmt 0 view .LVU90 + 327 003c 1029 cmp r1, #16 + 328 003e 0ED0 beq .L35 + 329 .L27: +6570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +6572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +6573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 330 .loc 1 6575 3 is_stmt 1 view .LVU91 + 331 .loc 1 6575 6 is_stmt 0 view .LVU92 + 332 0040 2029 cmp r1, #32 + 333 0042 0FD0 beq .L36 + 334 .L28: +6576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable STOP interrupts */ +6578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +6579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) + 335 .loc 1 6581 3 is_stmt 1 view .LVU93 + 336 .loc 1 6581 6 is_stmt 0 view .LVU94 + 337 0044 4029 cmp r1, #64 + 338 0046 10D0 beq .L37 + 339 .L29: +6582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Enable TC interrupts */ +6584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +6585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Disable interrupts only at the end */ +6588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* to avoid a breaking situation like at "t" time */ +6589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* all disable interrupts request are not done */ +6590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 340 .loc 1 6590 3 is_stmt 1 view .LVU95 + 341 0048 0168 ldr r1, [r0] + 342 .LVL26: + 343 .loc 1 6590 3 is_stmt 0 view .LVU96 + 344 004a 0A68 ldr r2, [r1] + 345 004c 22EA0303 bic r3, r2, r3 + 346 .LVL27: + 347 .loc 1 6590 3 view .LVU97 + 348 0050 0B60 str r3, [r1] + ARM GAS /tmp/ccEimIdZ.s page 123 + + +6591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 349 .loc 1 6591 1 view .LVU98 + 350 0052 7047 bx lr + 351 .LVL28: + 352 .L32: +6554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 353 .loc 1 6554 12 view .LVU99 + 354 0054 6346 mov r3, ip + 355 0056 EEE7 b .L25 + 356 .LVL29: + 357 .L34: +6566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 358 .loc 1 6566 5 is_stmt 1 view .LVU100 +6566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 359 .loc 1 6566 12 is_stmt 0 view .LVU101 + 360 0058 43F0B803 orr r3, r3, #184 + 361 .LVL30: +6566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 362 .loc 1 6566 12 view .LVU102 + 363 005c EEE7 b .L26 + 364 .L35: +6572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 365 .loc 1 6572 5 is_stmt 1 view .LVU103 +6572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 366 .loc 1 6572 12 is_stmt 0 view .LVU104 + 367 005e 43F09003 orr r3, r3, #144 + 368 .LVL31: +6572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 369 .loc 1 6572 12 view .LVU105 + 370 0062 EDE7 b .L27 + 371 .L36: +6578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 372 .loc 1 6578 5 is_stmt 1 view .LVU106 +6578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 373 .loc 1 6578 12 is_stmt 0 view .LVU107 + 374 0064 43F02003 orr r3, r3, #32 + 375 .LVL32: +6578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 376 .loc 1 6578 12 view .LVU108 + 377 0068 ECE7 b .L28 + 378 .L37: +6584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 379 .loc 1 6584 5 is_stmt 1 view .LVU109 +6584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 380 .loc 1 6584 12 is_stmt 0 view .LVU110 + 381 006a 43F04003 orr r3, r3, #64 + 382 .LVL33: +6584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 383 .loc 1 6584 12 view .LVU111 + 384 006e EBE7 b .L29 + 385 .cfi_endproc + 386 .LFE218: + 388 .section .text.I2C_ConvertOtherXferOptions,"ax",%progbits + 389 .align 1 + 390 .syntax unified + 391 .thumb + 392 .thumb_func + ARM GAS /tmp/ccEimIdZ.s page 124 + + + 393 .fpu fpv5-d16 + 395 I2C_ConvertOtherXferOptions: + 396 .LVL34: + 397 .LFB219: +6592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** +6593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** +6594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. +6595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @param hi2c I2C handle. +6596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** * @retval None +6597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** */ +6598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +6599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 398 .loc 1 6599 1 is_stmt 1 view -0 + 399 .cfi_startproc + 400 @ args = 0, pretend = 0, frame = 0 + 401 @ frame_needed = 0, uses_anonymous_args = 0 + 402 @ link register save eliminated. +6600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* if user set XferOptions to I2C_OTHER_FRAME */ +6601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +6602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_FRAME */ +6603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_OTHER_FRAME) + 403 .loc 1 6603 3 view .LVU113 + 404 .loc 1 6603 11 is_stmt 0 view .LVU114 + 405 0000 C36A ldr r3, [r0, #44] + 406 .loc 1 6603 6 view .LVU115 + 407 0002 AA2B cmp r3, #170 + 408 0004 04D0 beq .L41 +6604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_FRAME; +6606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ +6608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +6609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* then generate a stop condition at the end of transfer */ +6610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ +6611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + 409 .loc 1 6611 8 is_stmt 1 view .LVU116 + 410 .loc 1 6611 16 is_stmt 0 view .LVU117 + 411 0006 C36A ldr r3, [r0, #44] + 412 .loc 1 6611 11 view .LVU118 + 413 0008 B3F52A4F cmp r3, #43520 + 414 000c 03D0 beq .L42 + 415 .L38: +6612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; +6614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** else +6616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { +6617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Nothing to do */ +6618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } +6619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 416 .loc 1 6619 1 view .LVU119 + 417 000e 7047 bx lr + 418 .L41: +6605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 419 .loc 1 6605 5 is_stmt 1 view .LVU120 +6605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 420 .loc 1 6605 23 is_stmt 0 view .LVU121 + ARM GAS /tmp/ccEimIdZ.s page 125 + + + 421 0010 0023 movs r3, #0 + 422 0012 C362 str r3, [r0, #44] + 423 0014 7047 bx lr + 424 .L42: +6613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 425 .loc 1 6613 5 is_stmt 1 view .LVU122 +6613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 426 .loc 1 6613 23 is_stmt 0 view .LVU123 + 427 0016 4FF00073 mov r3, #33554432 + 428 001a C362 str r3, [r0, #44] +6618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 429 .loc 1 6618 3 is_stmt 1 view .LVU124 + 430 .loc 1 6619 1 is_stmt 0 view .LVU125 + 431 001c F7E7 b .L38 + 432 .cfi_endproc + 433 .LFE219: + 435 .section .text.I2C_IsAcknowledgeFailed,"ax",%progbits + 436 .align 1 + 437 .syntax unified + 438 .thumb + 439 .thumb_func + 440 .fpu fpv5-d16 + 442 I2C_IsAcknowledgeFailed: + 443 .LVL35: + 444 .LFB215: +6378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 445 .loc 1 6378 1 is_stmt 1 view -0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 0 + 448 @ frame_needed = 0, uses_anonymous_args = 0 +6378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 449 .loc 1 6378 1 is_stmt 0 view .LVU127 + 450 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 451 .LCFI2: + 452 .cfi_def_cfa_offset 24 + 453 .cfi_offset 3, -24 + 454 .cfi_offset 4, -20 + 455 .cfi_offset 5, -16 + 456 .cfi_offset 6, -12 + 457 .cfi_offset 7, -8 + 458 .cfi_offset 14, -4 + 459 0002 0546 mov r5, r0 + 460 0004 0E46 mov r6, r1 + 461 0006 1746 mov r7, r2 +6379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 462 .loc 1 6379 3 is_stmt 1 view .LVU128 +6379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 463 .loc 1 6379 7 is_stmt 0 view .LVU129 + 464 0008 0368 ldr r3, [r0] + 465 000a 9B69 ldr r3, [r3, #24] +6379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 466 .loc 1 6379 6 view .LVU130 + 467 000c 13F0100F tst r3, #16 + 468 0010 01D1 bne .L46 +6423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 469 .loc 1 6423 10 view .LVU131 + 470 0012 0020 movs r0, #0 + ARM GAS /tmp/ccEimIdZ.s page 126 + + + 471 .LVL36: + 472 .L45: +6424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 473 .loc 1 6424 1 view .LVU132 + 474 0014 F8BD pop {r3, r4, r5, r6, r7, pc} + 475 .LVL37: + 476 .L46: +6383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 477 .loc 1 6383 11 is_stmt 1 view .LVU133 +6383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 478 .loc 1 6383 12 is_stmt 0 view .LVU134 + 479 0016 2B68 ldr r3, [r5] + 480 0018 9C69 ldr r4, [r3, #24] +6383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 481 .loc 1 6383 11 view .LVU135 + 482 001a 14F0200F tst r4, #32 + 483 001e 17D1 bne .L50 +6386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 484 .loc 1 6386 7 is_stmt 1 view .LVU136 +6386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 485 .loc 1 6386 10 is_stmt 0 view .LVU137 + 486 0020 B6F1FF3F cmp r6, #-1 + 487 0024 F7D0 beq .L46 +6388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 488 .loc 1 6388 9 is_stmt 1 view .LVU138 +6388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 489 .loc 1 6388 15 is_stmt 0 view .LVU139 + 490 0026 FFF7FEFF bl HAL_GetTick + 491 .LVL38: +6388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 492 .loc 1 6388 29 view .LVU140 + 493 002a C01B subs r0, r0, r7 +6388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 494 .loc 1 6388 12 view .LVU141 + 495 002c B042 cmp r0, r6 + 496 002e 01D8 bhi .L47 +6388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 497 .loc 1 6388 53 discriminator 1 view .LVU142 + 498 0030 002E cmp r6, #0 + 499 0032 F0D1 bne .L46 + 500 .L47: +6390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 501 .loc 1 6390 11 is_stmt 1 view .LVU143 +6390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 502 .loc 1 6390 27 is_stmt 0 view .LVU144 + 503 0034 6B6C ldr r3, [r5, #68] + 504 0036 43F02003 orr r3, r3, #32 + 505 003a 6B64 str r3, [r5, #68] +6391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 506 .loc 1 6391 11 is_stmt 1 view .LVU145 +6391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 507 .loc 1 6391 23 is_stmt 0 view .LVU146 + 508 003c 2023 movs r3, #32 + 509 003e 85F84130 strb r3, [r5, #65] +6392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 510 .loc 1 6392 11 is_stmt 1 view .LVU147 +6392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 127 + + + 511 .loc 1 6392 22 is_stmt 0 view .LVU148 + 512 0042 0023 movs r3, #0 + 513 0044 85F84230 strb r3, [r5, #66] +6395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 514 .loc 1 6395 11 is_stmt 1 view .LVU149 +6395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 515 .loc 1 6395 11 view .LVU150 + 516 0048 85F84030 strb r3, [r5, #64] +6395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 517 .loc 1 6395 11 view .LVU151 +6397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 518 .loc 1 6397 11 view .LVU152 +6397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 519 .loc 1 6397 18 is_stmt 0 view .LVU153 + 520 004c 0120 movs r0, #1 + 521 004e E1E7 b .L45 + 522 .L50: +6403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 523 .loc 1 6403 5 is_stmt 1 view .LVU154 + 524 0050 1022 movs r2, #16 + 525 0052 DA61 str r2, [r3, #28] +6406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 526 .loc 1 6406 5 view .LVU155 + 527 0054 2B68 ldr r3, [r5] + 528 0056 2024 movs r4, #32 + 529 0058 DC61 str r4, [r3, #28] +6409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 530 .loc 1 6409 5 view .LVU156 + 531 005a 2846 mov r0, r5 + 532 005c FFF7FEFF bl I2C_Flush_TXDR + 533 .LVL39: +6412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 534 .loc 1 6412 5 view .LVU157 + 535 0060 2A68 ldr r2, [r5] + 536 0062 5368 ldr r3, [r2, #4] + 537 0064 23F0FF73 bic r3, r3, #33423360 + 538 0068 23F48B33 bic r3, r3, #71168 + 539 006c 23F4FF73 bic r3, r3, #510 + 540 0070 23F00103 bic r3, r3, #1 + 541 0074 5360 str r3, [r2, #4] +6414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 542 .loc 1 6414 5 view .LVU158 +6414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 543 .loc 1 6414 21 is_stmt 0 view .LVU159 + 544 0076 6B6C ldr r3, [r5, #68] + 545 0078 43F00403 orr r3, r3, #4 + 546 007c 6B64 str r3, [r5, #68] +6415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 547 .loc 1 6415 5 is_stmt 1 view .LVU160 +6415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 548 .loc 1 6415 17 is_stmt 0 view .LVU161 + 549 007e 85F84140 strb r4, [r5, #65] +6416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 550 .loc 1 6416 5 is_stmt 1 view .LVU162 +6416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 551 .loc 1 6416 16 is_stmt 0 view .LVU163 + 552 0082 0023 movs r3, #0 + ARM GAS /tmp/ccEimIdZ.s page 128 + + + 553 0084 85F84230 strb r3, [r5, #66] +6419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 554 .loc 1 6419 5 is_stmt 1 view .LVU164 +6419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 555 .loc 1 6419 5 view .LVU165 + 556 0088 85F84030 strb r3, [r5, #64] +6419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 557 .loc 1 6419 5 view .LVU166 +6421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 558 .loc 1 6421 5 view .LVU167 +6421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 559 .loc 1 6421 12 is_stmt 0 view .LVU168 + 560 008c 0120 movs r0, #1 + 561 008e C1E7 b .L45 + 562 .cfi_endproc + 563 .LFE215: + 565 .section .text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits + 566 .align 1 + 567 .syntax unified + 568 .thumb + 569 .thumb_func + 570 .fpu fpv5-d16 + 572 I2C_WaitOnTXISFlagUntilTimeout: + 573 .LVL40: + 574 .LFB212: +6244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 575 .loc 1 6244 1 is_stmt 1 view -0 + 576 .cfi_startproc + 577 @ args = 0, pretend = 0, frame = 0 + 578 @ frame_needed = 0, uses_anonymous_args = 0 +6244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 579 .loc 1 6244 1 is_stmt 0 view .LVU170 + 580 0000 70B5 push {r4, r5, r6, lr} + 581 .LCFI3: + 582 .cfi_def_cfa_offset 16 + 583 .cfi_offset 4, -16 + 584 .cfi_offset 5, -12 + 585 .cfi_offset 6, -8 + 586 .cfi_offset 14, -4 + 587 0002 0446 mov r4, r0 + 588 0004 0D46 mov r5, r1 + 589 0006 1646 mov r6, r2 +6245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 590 .loc 1 6245 3 is_stmt 1 view .LVU171 + 591 .LVL41: + 592 .L54: +6245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 593 .loc 1 6245 9 view .LVU172 +6245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 594 .loc 1 6245 10 is_stmt 0 view .LVU173 + 595 0008 2368 ldr r3, [r4] + 596 000a 9B69 ldr r3, [r3, #24] +6245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 597 .loc 1 6245 9 view .LVU174 + 598 000c 13F0020F tst r3, #2 + 599 0010 1DD1 bne .L59 +6248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 129 + + + 600 .loc 1 6248 5 is_stmt 1 view .LVU175 +6248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 601 .loc 1 6248 9 is_stmt 0 view .LVU176 + 602 0012 3246 mov r2, r6 + 603 0014 2946 mov r1, r5 + 604 0016 2046 mov r0, r4 + 605 0018 FFF7FEFF bl I2C_IsAcknowledgeFailed + 606 .LVL42: +6248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 607 .loc 1 6248 8 view .LVU177 + 608 001c C8B9 cbnz r0, .L57 +6254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 609 .loc 1 6254 5 is_stmt 1 view .LVU178 +6254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 610 .loc 1 6254 8 is_stmt 0 view .LVU179 + 611 001e B5F1FF3F cmp r5, #-1 + 612 0022 F1D0 beq .L54 +6256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 613 .loc 1 6256 7 is_stmt 1 view .LVU180 +6256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 614 .loc 1 6256 13 is_stmt 0 view .LVU181 + 615 0024 FFF7FEFF bl HAL_GetTick + 616 .LVL43: +6256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 617 .loc 1 6256 27 view .LVU182 + 618 0028 801B subs r0, r0, r6 +6256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 619 .loc 1 6256 10 view .LVU183 + 620 002a A842 cmp r0, r5 + 621 002c 01D8 bhi .L55 +6256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 622 .loc 1 6256 51 discriminator 1 view .LVU184 + 623 002e 002D cmp r5, #0 + 624 0030 EAD1 bne .L54 + 625 .L55: +6258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 626 .loc 1 6258 9 is_stmt 1 view .LVU185 +6258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 627 .loc 1 6258 25 is_stmt 0 view .LVU186 + 628 0032 636C ldr r3, [r4, #68] + 629 0034 43F02003 orr r3, r3, #32 + 630 0038 6364 str r3, [r4, #68] +6259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 631 .loc 1 6259 9 is_stmt 1 view .LVU187 +6259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 632 .loc 1 6259 21 is_stmt 0 view .LVU188 + 633 003a 2023 movs r3, #32 + 634 003c 84F84130 strb r3, [r4, #65] +6260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 635 .loc 1 6260 9 is_stmt 1 view .LVU189 +6260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 636 .loc 1 6260 20 is_stmt 0 view .LVU190 + 637 0040 0023 movs r3, #0 + 638 0042 84F84230 strb r3, [r4, #66] +6263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 639 .loc 1 6263 9 is_stmt 1 view .LVU191 +6263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 130 + + + 640 .loc 1 6263 9 view .LVU192 + 641 0046 84F84030 strb r3, [r4, #64] +6263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 642 .loc 1 6263 9 view .LVU193 +6265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 643 .loc 1 6265 9 view .LVU194 +6265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 644 .loc 1 6265 16 is_stmt 0 view .LVU195 + 645 004a 0120 movs r0, #1 + 646 004c 00E0 b .L53 + 647 .L59: +6269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 648 .loc 1 6269 10 view .LVU196 + 649 004e 0020 movs r0, #0 + 650 .L53: +6270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 651 .loc 1 6270 1 view .LVU197 + 652 0050 70BD pop {r4, r5, r6, pc} + 653 .LVL44: + 654 .L57: +6250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 655 .loc 1 6250 14 view .LVU198 + 656 0052 0120 movs r0, #1 + 657 0054 FCE7 b .L53 + 658 .cfi_endproc + 659 .LFE212: + 661 .section .text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits + 662 .align 1 + 663 .syntax unified + 664 .thumb + 665 .thumb_func + 666 .fpu fpv5-d16 + 668 I2C_WaitOnFlagUntilTimeout: + 669 .LVL45: + 670 .LFB211: +6214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 671 .loc 1 6214 1 is_stmt 1 view -0 + 672 .cfi_startproc + 673 @ args = 4, pretend = 0, frame = 0 + 674 @ frame_needed = 0, uses_anonymous_args = 0 +6214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 675 .loc 1 6214 1 is_stmt 0 view .LVU200 + 676 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 677 .LCFI4: + 678 .cfi_def_cfa_offset 24 + 679 .cfi_offset 4, -24 + 680 .cfi_offset 5, -20 + 681 .cfi_offset 6, -16 + 682 .cfi_offset 7, -12 + 683 .cfi_offset 8, -8 + 684 .cfi_offset 14, -4 + 685 0004 0646 mov r6, r0 + 686 0006 8846 mov r8, r1 + 687 0008 1746 mov r7, r2 + 688 000a 1D46 mov r5, r3 +6215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 689 .loc 1 6215 3 is_stmt 1 view .LVU201 + ARM GAS /tmp/ccEimIdZ.s page 131 + + + 690 .LVL46: + 691 .L62: +6215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 692 .loc 1 6215 9 view .LVU202 +6215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 693 .loc 1 6215 10 is_stmt 0 view .LVU203 + 694 000c 3468 ldr r4, [r6] + 695 000e A469 ldr r4, [r4, #24] + 696 0010 38EA0403 bics r3, r8, r4 + 697 0014 0CBF ite eq + 698 0016 4FF0010C moveq ip, #1 + 699 001a 4FF0000C movne ip, #0 +6215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 700 .loc 1 6215 9 view .LVU204 + 701 001e BC45 cmp ip, r7 + 702 0020 18D1 bne .L67 +6218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 703 .loc 1 6218 5 is_stmt 1 view .LVU205 +6218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 704 .loc 1 6218 8 is_stmt 0 view .LVU206 + 705 0022 B5F1FF3F cmp r5, #-1 + 706 0026 F1D0 beq .L62 +6220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 707 .loc 1 6220 7 is_stmt 1 view .LVU207 +6220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 708 .loc 1 6220 13 is_stmt 0 view .LVU208 + 709 0028 FFF7FEFF bl HAL_GetTick + 710 .LVL47: +6220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 711 .loc 1 6220 27 view .LVU209 + 712 002c 069B ldr r3, [sp, #24] + 713 002e C01A subs r0, r0, r3 +6220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 714 .loc 1 6220 10 view .LVU210 + 715 0030 A842 cmp r0, r5 + 716 0032 01D8 bhi .L63 +6220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 717 .loc 1 6220 51 discriminator 1 view .LVU211 + 718 0034 002D cmp r5, #0 + 719 0036 E9D1 bne .L62 + 720 .L63: +6222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 721 .loc 1 6222 9 is_stmt 1 view .LVU212 +6222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 722 .loc 1 6222 25 is_stmt 0 view .LVU213 + 723 0038 736C ldr r3, [r6, #68] + 724 003a 43F02003 orr r3, r3, #32 + 725 003e 7364 str r3, [r6, #68] +6223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 726 .loc 1 6223 9 is_stmt 1 view .LVU214 +6223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 727 .loc 1 6223 21 is_stmt 0 view .LVU215 + 728 0040 2023 movs r3, #32 + 729 0042 86F84130 strb r3, [r6, #65] +6224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 730 .loc 1 6224 9 is_stmt 1 view .LVU216 +6224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 132 + + + 731 .loc 1 6224 20 is_stmt 0 view .LVU217 + 732 0046 0023 movs r3, #0 + 733 0048 86F84230 strb r3, [r6, #66] +6227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 734 .loc 1 6227 9 is_stmt 1 view .LVU218 +6227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 735 .loc 1 6227 9 view .LVU219 + 736 004c 86F84030 strb r3, [r6, #64] +6227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 737 .loc 1 6227 9 view .LVU220 +6228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 738 .loc 1 6228 9 view .LVU221 +6228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 739 .loc 1 6228 16 is_stmt 0 view .LVU222 + 740 0050 0120 movs r0, #1 + 741 0052 00E0 b .L64 + 742 .L67: +6232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 743 .loc 1 6232 10 view .LVU223 + 744 0054 0020 movs r0, #0 + 745 .L64: +6233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 746 .loc 1 6233 1 view .LVU224 + 747 0056 BDE8F081 pop {r4, r5, r6, r7, r8, pc} +6233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 748 .loc 1 6233 1 view .LVU225 + 749 .cfi_endproc + 750 .LFE211: + 752 .section .text.I2C_RequestMemoryWrite,"ax",%progbits + 753 .align 1 + 754 .syntax unified + 755 .thumb + 756 .thumb_func + 757 .fpu fpv5-d16 + 759 I2C_RequestMemoryWrite: + 760 .LVL48: + 761 .LFB194: +5155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 762 .loc 1 5155 1 is_stmt 1 view -0 + 763 .cfi_startproc + 764 @ args = 8, pretend = 0, frame = 0 + 765 @ frame_needed = 0, uses_anonymous_args = 0 +5155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 766 .loc 1 5155 1 is_stmt 0 view .LVU227 + 767 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 768 .LCFI5: + 769 .cfi_def_cfa_offset 24 + 770 .cfi_offset 4, -24 + 771 .cfi_offset 5, -20 + 772 .cfi_offset 6, -16 + 773 .cfi_offset 7, -12 + 774 .cfi_offset 8, -8 + 775 .cfi_offset 14, -4 + 776 0004 82B0 sub sp, sp, #8 + 777 .LCFI6: + 778 .cfi_def_cfa_offset 32 + 779 0006 0446 mov r4, r0 + ARM GAS /tmp/ccEimIdZ.s page 133 + + + 780 0008 9046 mov r8, r2 + 781 000a 1D46 mov r5, r3 + 782 000c 089E ldr r6, [sp, #32] + 783 000e 099F ldr r7, [sp, #36] +5156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 784 .loc 1 5156 3 is_stmt 1 view .LVU228 + 785 0010 194B ldr r3, .L77 + 786 .LVL49: +5156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 787 .loc 1 5156 3 is_stmt 0 view .LVU229 + 788 0012 0093 str r3, [sp] + 789 0014 4FF08073 mov r3, #16777216 + 790 0018 EAB2 uxtb r2, r5 + 791 .LVL50: +5156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 792 .loc 1 5156 3 view .LVU230 + 793 001a FFF7FEFF bl I2C_TransferConfig + 794 .LVL51: +5159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 795 .loc 1 5159 3 is_stmt 1 view .LVU231 +5159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 796 .loc 1 5159 7 is_stmt 0 view .LVU232 + 797 001e 3A46 mov r2, r7 + 798 0020 3146 mov r1, r6 + 799 0022 2046 mov r0, r4 + 800 0024 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 801 .LVL52: +5159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 802 .loc 1 5159 6 view .LVU233 + 803 0028 F8B9 cbnz r0, .L72 +5165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 804 .loc 1 5165 3 is_stmt 1 view .LVU234 +5165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 805 .loc 1 5165 6 is_stmt 0 view .LVU235 + 806 002a 012D cmp r5, #1 + 807 002c 0ED1 bne .L70 +5168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 808 .loc 1 5168 5 is_stmt 1 view .LVU236 +5168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 809 .loc 1 5168 9 is_stmt 0 view .LVU237 + 810 002e 2368 ldr r3, [r4] +5168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 811 .loc 1 5168 28 view .LVU238 + 812 0030 5FFA88F2 uxtb r2, r8 +5168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 813 .loc 1 5168 26 view .LVU239 + 814 0034 9A62 str r2, [r3, #40] + 815 .L71: +5187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 816 .loc 1 5187 3 is_stmt 1 view .LVU240 +5187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 817 .loc 1 5187 7 is_stmt 0 view .LVU241 + 818 0036 0097 str r7, [sp] + 819 0038 3346 mov r3, r6 + 820 003a 0022 movs r2, #0 + 821 003c 8021 movs r1, #128 + 822 003e 2046 mov r0, r4 + ARM GAS /tmp/ccEimIdZ.s page 134 + + + 823 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 824 .LVL53: +5187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 825 .loc 1 5187 6 view .LVU242 + 826 0044 A8B9 cbnz r0, .L76 + 827 .L69: +5193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 828 .loc 1 5193 1 view .LVU243 + 829 0046 02B0 add sp, sp, #8 + 830 .LCFI7: + 831 .cfi_remember_state + 832 .cfi_def_cfa_offset 24 + 833 @ sp needed + 834 0048 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 835 .LVL54: + 836 .L70: + 837 .LCFI8: + 838 .cfi_restore_state +5174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 839 .loc 1 5174 5 is_stmt 1 view .LVU244 +5174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 840 .loc 1 5174 9 is_stmt 0 view .LVU245 + 841 004c 2368 ldr r3, [r4] +5174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 842 .loc 1 5174 28 view .LVU246 + 843 004e 4FEA1822 lsr r2, r8, #8 +5174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 844 .loc 1 5174 26 view .LVU247 + 845 0052 9A62 str r2, [r3, #40] +5177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 846 .loc 1 5177 5 is_stmt 1 view .LVU248 +5177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 847 .loc 1 5177 9 is_stmt 0 view .LVU249 + 848 0054 3A46 mov r2, r7 + 849 0056 3146 mov r1, r6 + 850 0058 2046 mov r0, r4 + 851 005a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 852 .LVL55: +5177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 853 .loc 1 5177 8 view .LVU250 + 854 005e 30B9 cbnz r0, .L73 +5183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 855 .loc 1 5183 5 is_stmt 1 view .LVU251 +5183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 856 .loc 1 5183 9 is_stmt 0 view .LVU252 + 857 0060 2368 ldr r3, [r4] +5183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 858 .loc 1 5183 28 view .LVU253 + 859 0062 5FFA88F2 uxtb r2, r8 +5183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 860 .loc 1 5183 26 view .LVU254 + 861 0066 9A62 str r2, [r3, #40] + 862 0068 E5E7 b .L71 + 863 .L72: +5161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 864 .loc 1 5161 12 view .LVU255 + 865 006a 0120 movs r0, #1 + ARM GAS /tmp/ccEimIdZ.s page 135 + + + 866 006c EBE7 b .L69 + 867 .L73: +5179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 868 .loc 1 5179 14 view .LVU256 + 869 006e 0120 movs r0, #1 + 870 0070 E9E7 b .L69 + 871 .L76: +5189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 872 .loc 1 5189 12 view .LVU257 + 873 0072 0120 movs r0, #1 + 874 0074 E7E7 b .L69 + 875 .L78: + 876 0076 00BF .align 2 + 877 .L77: + 878 0078 00200080 .word -2147475456 + 879 .cfi_endproc + 880 .LFE194: + 882 .section .text.I2C_RequestMemoryRead,"ax",%progbits + 883 .align 1 + 884 .syntax unified + 885 .thumb + 886 .thumb_func + 887 .fpu fpv5-d16 + 889 I2C_RequestMemoryRead: + 890 .LVL56: + 891 .LFB195: +5208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 892 .loc 1 5208 1 is_stmt 1 view -0 + 893 .cfi_startproc + 894 @ args = 8, pretend = 0, frame = 0 + 895 @ frame_needed = 0, uses_anonymous_args = 0 +5208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 896 .loc 1 5208 1 is_stmt 0 view .LVU259 + 897 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 898 .LCFI9: + 899 .cfi_def_cfa_offset 24 + 900 .cfi_offset 4, -24 + 901 .cfi_offset 5, -20 + 902 .cfi_offset 6, -16 + 903 .cfi_offset 7, -12 + 904 .cfi_offset 8, -8 + 905 .cfi_offset 14, -4 + 906 0004 82B0 sub sp, sp, #8 + 907 .LCFI10: + 908 .cfi_def_cfa_offset 32 + 909 0006 0446 mov r4, r0 + 910 0008 9046 mov r8, r2 + 911 000a 1D46 mov r5, r3 + 912 000c 089E ldr r6, [sp, #32] + 913 000e 099F ldr r7, [sp, #36] +5209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 914 .loc 1 5209 3 is_stmt 1 view .LVU260 + 915 0010 184B ldr r3, .L88 + 916 .LVL57: +5209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 917 .loc 1 5209 3 is_stmt 0 view .LVU261 + 918 0012 0093 str r3, [sp] + ARM GAS /tmp/ccEimIdZ.s page 136 + + + 919 0014 0023 movs r3, #0 + 920 0016 EAB2 uxtb r2, r5 + 921 .LVL58: +5209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 922 .loc 1 5209 3 view .LVU262 + 923 0018 FFF7FEFF bl I2C_TransferConfig + 924 .LVL59: +5212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 925 .loc 1 5212 3 is_stmt 1 view .LVU263 +5212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 926 .loc 1 5212 7 is_stmt 0 view .LVU264 + 927 001c 3A46 mov r2, r7 + 928 001e 3146 mov r1, r6 + 929 0020 2046 mov r0, r4 + 930 0022 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 931 .LVL60: +5212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 932 .loc 1 5212 6 view .LVU265 + 933 0026 F8B9 cbnz r0, .L83 +5218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 934 .loc 1 5218 3 is_stmt 1 view .LVU266 +5218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 935 .loc 1 5218 6 is_stmt 0 view .LVU267 + 936 0028 012D cmp r5, #1 + 937 002a 0ED1 bne .L81 +5221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 938 .loc 1 5221 5 is_stmt 1 view .LVU268 +5221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 939 .loc 1 5221 9 is_stmt 0 view .LVU269 + 940 002c 2368 ldr r3, [r4] +5221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 941 .loc 1 5221 28 view .LVU270 + 942 002e 5FFA88F2 uxtb r2, r8 +5221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 943 .loc 1 5221 26 view .LVU271 + 944 0032 9A62 str r2, [r3, #40] + 945 .L82: +5240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 946 .loc 1 5240 3 is_stmt 1 view .LVU272 +5240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 947 .loc 1 5240 7 is_stmt 0 view .LVU273 + 948 0034 0097 str r7, [sp] + 949 0036 3346 mov r3, r6 + 950 0038 0022 movs r2, #0 + 951 003a 4021 movs r1, #64 + 952 003c 2046 mov r0, r4 + 953 003e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 954 .LVL61: +5240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 955 .loc 1 5240 6 view .LVU274 + 956 0042 A8B9 cbnz r0, .L87 + 957 .L80: +5246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 958 .loc 1 5246 1 view .LVU275 + 959 0044 02B0 add sp, sp, #8 + 960 .LCFI11: + 961 .cfi_remember_state + ARM GAS /tmp/ccEimIdZ.s page 137 + + + 962 .cfi_def_cfa_offset 24 + 963 @ sp needed + 964 0046 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 965 .LVL62: + 966 .L81: + 967 .LCFI12: + 968 .cfi_restore_state +5227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 969 .loc 1 5227 5 is_stmt 1 view .LVU276 +5227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 970 .loc 1 5227 9 is_stmt 0 view .LVU277 + 971 004a 2368 ldr r3, [r4] +5227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 972 .loc 1 5227 28 view .LVU278 + 973 004c 4FEA1822 lsr r2, r8, #8 +5227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 974 .loc 1 5227 26 view .LVU279 + 975 0050 9A62 str r2, [r3, #40] +5230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 976 .loc 1 5230 5 is_stmt 1 view .LVU280 +5230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 977 .loc 1 5230 9 is_stmt 0 view .LVU281 + 978 0052 3A46 mov r2, r7 + 979 0054 3146 mov r1, r6 + 980 0056 2046 mov r0, r4 + 981 0058 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 982 .LVL63: +5230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 983 .loc 1 5230 8 view .LVU282 + 984 005c 30B9 cbnz r0, .L84 +5236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 985 .loc 1 5236 5 is_stmt 1 view .LVU283 +5236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 986 .loc 1 5236 9 is_stmt 0 view .LVU284 + 987 005e 2368 ldr r3, [r4] +5236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 988 .loc 1 5236 28 view .LVU285 + 989 0060 5FFA88F2 uxtb r2, r8 +5236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 990 .loc 1 5236 26 view .LVU286 + 991 0064 9A62 str r2, [r3, #40] + 992 0066 E5E7 b .L82 + 993 .L83: +5214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 994 .loc 1 5214 12 view .LVU287 + 995 0068 0120 movs r0, #1 + 996 006a EBE7 b .L80 + 997 .L84: +5232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 998 .loc 1 5232 14 view .LVU288 + 999 006c 0120 movs r0, #1 + 1000 006e E9E7 b .L80 + 1001 .L87: +5242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1002 .loc 1 5242 12 view .LVU289 + 1003 0070 0120 movs r0, #1 + 1004 0072 E7E7 b .L80 + ARM GAS /tmp/ccEimIdZ.s page 138 + + + 1005 .L89: + 1006 .align 2 + 1007 .L88: + 1008 0074 00200080 .word -2147475456 + 1009 .cfi_endproc + 1010 .LFE195: + 1012 .section .text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits + 1013 .align 1 + 1014 .syntax unified + 1015 .thumb + 1016 .thumb_func + 1017 .fpu fpv5-d16 + 1019 I2C_WaitOnSTOPFlagUntilTimeout: + 1020 .LVL64: + 1021 .LFB213: +6281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1022 .loc 1 6281 1 is_stmt 1 view -0 + 1023 .cfi_startproc + 1024 @ args = 0, pretend = 0, frame = 0 + 1025 @ frame_needed = 0, uses_anonymous_args = 0 +6281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1026 .loc 1 6281 1 is_stmt 0 view .LVU291 + 1027 0000 70B5 push {r4, r5, r6, lr} + 1028 .LCFI13: + 1029 .cfi_def_cfa_offset 16 + 1030 .cfi_offset 4, -16 + 1031 .cfi_offset 5, -12 + 1032 .cfi_offset 6, -8 + 1033 .cfi_offset 14, -4 + 1034 0002 0546 mov r5, r0 + 1035 0004 0C46 mov r4, r1 + 1036 0006 1646 mov r6, r2 +6282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1037 .loc 1 6282 3 is_stmt 1 view .LVU292 + 1038 .LVL65: + 1039 .L91: +6282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1040 .loc 1 6282 9 view .LVU293 +6282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1041 .loc 1 6282 10 is_stmt 0 view .LVU294 + 1042 0008 2B68 ldr r3, [r5] + 1043 000a 9B69 ldr r3, [r3, #24] +6282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1044 .loc 1 6282 9 view .LVU295 + 1045 000c 13F0200F tst r3, #32 + 1046 0010 1AD1 bne .L97 +6285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1047 .loc 1 6285 5 is_stmt 1 view .LVU296 +6285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1048 .loc 1 6285 9 is_stmt 0 view .LVU297 + 1049 0012 3246 mov r2, r6 + 1050 0014 2146 mov r1, r4 + 1051 0016 2846 mov r0, r5 + 1052 0018 FFF7FEFF bl I2C_IsAcknowledgeFailed + 1053 .LVL66: +6285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1054 .loc 1 6285 8 view .LVU298 + ARM GAS /tmp/ccEimIdZ.s page 139 + + + 1055 001c B0B9 cbnz r0, .L95 +6291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1056 .loc 1 6291 5 is_stmt 1 view .LVU299 +6291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1057 .loc 1 6291 11 is_stmt 0 view .LVU300 + 1058 001e FFF7FEFF bl HAL_GetTick + 1059 .LVL67: +6291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1060 .loc 1 6291 25 view .LVU301 + 1061 0022 801B subs r0, r0, r6 +6291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1062 .loc 1 6291 8 view .LVU302 + 1063 0024 A042 cmp r0, r4 + 1064 0026 01D8 bhi .L93 +6291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1065 .loc 1 6291 49 discriminator 1 view .LVU303 + 1066 0028 002C cmp r4, #0 + 1067 002a EDD1 bne .L91 + 1068 .L93: +6293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1069 .loc 1 6293 7 is_stmt 1 view .LVU304 +6293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1070 .loc 1 6293 23 is_stmt 0 view .LVU305 + 1071 002c 6B6C ldr r3, [r5, #68] + 1072 002e 43F02003 orr r3, r3, #32 + 1073 0032 6B64 str r3, [r5, #68] +6294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1074 .loc 1 6294 7 is_stmt 1 view .LVU306 +6294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1075 .loc 1 6294 19 is_stmt 0 view .LVU307 + 1076 0034 2023 movs r3, #32 + 1077 0036 85F84130 strb r3, [r5, #65] +6295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1078 .loc 1 6295 7 is_stmt 1 view .LVU308 +6295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1079 .loc 1 6295 18 is_stmt 0 view .LVU309 + 1080 003a 0023 movs r3, #0 + 1081 003c 85F84230 strb r3, [r5, #66] +6298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1082 .loc 1 6298 7 is_stmt 1 view .LVU310 +6298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1083 .loc 1 6298 7 view .LVU311 + 1084 0040 85F84030 strb r3, [r5, #64] +6298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1085 .loc 1 6298 7 view .LVU312 +6300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1086 .loc 1 6300 7 view .LVU313 +6300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1087 .loc 1 6300 14 is_stmt 0 view .LVU314 + 1088 0044 0120 movs r0, #1 + 1089 .L92: +6304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1090 .loc 1 6304 1 view .LVU315 + 1091 0046 70BD pop {r4, r5, r6, pc} + 1092 .LVL68: + 1093 .L97: +6303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 140 + + + 1094 .loc 1 6303 10 view .LVU316 + 1095 0048 0020 movs r0, #0 + 1096 004a FCE7 b .L92 + 1097 .L95: +6287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1098 .loc 1 6287 14 view .LVU317 + 1099 004c 0120 movs r0, #1 + 1100 004e FAE7 b .L92 + 1101 .cfi_endproc + 1102 .LFE213: + 1104 .section .text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits + 1105 .align 1 + 1106 .syntax unified + 1107 .thumb + 1108 .thumb_func + 1109 .fpu fpv5-d16 + 1111 I2C_WaitOnRXNEFlagUntilTimeout: + 1112 .LVL69: + 1113 .LFB214: +6315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 1114 .loc 1 6315 1 is_stmt 1 view -0 + 1115 .cfi_startproc + 1116 @ args = 0, pretend = 0, frame = 0 + 1117 @ frame_needed = 0, uses_anonymous_args = 0 +6315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 1118 .loc 1 6315 1 is_stmt 0 view .LVU319 + 1119 0000 70B5 push {r4, r5, r6, lr} + 1120 .LCFI14: + 1121 .cfi_def_cfa_offset 16 + 1122 .cfi_offset 4, -16 + 1123 .cfi_offset 5, -12 + 1124 .cfi_offset 6, -8 + 1125 .cfi_offset 14, -4 + 1126 0002 0446 mov r4, r0 + 1127 0004 0D46 mov r5, r1 + 1128 0006 1646 mov r6, r2 +6316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1129 .loc 1 6316 3 is_stmt 1 view .LVU320 + 1130 .LVL70: + 1131 .L99: +6316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1132 .loc 1 6316 9 view .LVU321 +6316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1133 .loc 1 6316 10 is_stmt 0 view .LVU322 + 1134 0008 2368 ldr r3, [r4] + 1135 000a 9B69 ldr r3, [r3, #24] +6316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1136 .loc 1 6316 9 view .LVU323 + 1137 000c 13F0040F tst r3, #4 + 1138 0010 3ED1 bne .L107 +6319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1139 .loc 1 6319 5 is_stmt 1 view .LVU324 +6319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1140 .loc 1 6319 9 is_stmt 0 view .LVU325 + 1141 0012 3246 mov r2, r6 + 1142 0014 2946 mov r1, r5 + 1143 0016 2046 mov r0, r4 + ARM GAS /tmp/ccEimIdZ.s page 141 + + + 1144 0018 FFF7FEFF bl I2C_IsAcknowledgeFailed + 1145 .LVL71: +6319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1146 .loc 1 6319 8 view .LVU326 + 1147 001c 0146 mov r1, r0 + 1148 001e 0028 cmp r0, #0 + 1149 0020 38D1 bne .L105 +6325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1150 .loc 1 6325 5 is_stmt 1 view .LVU327 +6325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1151 .loc 1 6325 9 is_stmt 0 view .LVU328 + 1152 0022 2368 ldr r3, [r4] + 1153 0024 9A69 ldr r2, [r3, #24] +6325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1154 .loc 1 6325 8 view .LVU329 + 1155 0026 12F0200F tst r2, #32 + 1156 002a 13D1 bne .L108 +6355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1157 .loc 1 6355 5 is_stmt 1 view .LVU330 +6355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1158 .loc 1 6355 11 is_stmt 0 view .LVU331 + 1159 002c FFF7FEFF bl HAL_GetTick + 1160 .LVL72: +6355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1161 .loc 1 6355 25 view .LVU332 + 1162 0030 801B subs r0, r0, r6 +6355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1163 .loc 1 6355 8 view .LVU333 + 1164 0032 A842 cmp r0, r5 + 1165 0034 01D8 bhi .L103 +6355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1166 .loc 1 6355 49 discriminator 1 view .LVU334 + 1167 0036 002D cmp r5, #0 + 1168 0038 E6D1 bne .L99 + 1169 .L103: +6357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1170 .loc 1 6357 7 is_stmt 1 view .LVU335 +6357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1171 .loc 1 6357 23 is_stmt 0 view .LVU336 + 1172 003a 636C ldr r3, [r4, #68] + 1173 003c 43F02003 orr r3, r3, #32 + 1174 0040 6364 str r3, [r4, #68] +6358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1175 .loc 1 6358 7 is_stmt 1 view .LVU337 +6358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1176 .loc 1 6358 19 is_stmt 0 view .LVU338 + 1177 0042 2023 movs r3, #32 + 1178 0044 84F84130 strb r3, [r4, #65] +6361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1179 .loc 1 6361 7 is_stmt 1 view .LVU339 +6361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1180 .loc 1 6361 7 view .LVU340 + 1181 0048 0023 movs r3, #0 + 1182 004a 84F84030 strb r3, [r4, #64] +6361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1183 .loc 1 6361 7 view .LVU341 +6363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 142 + + + 1184 .loc 1 6363 7 view .LVU342 +6363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1185 .loc 1 6363 14 is_stmt 0 view .LVU343 + 1186 004e 0121 movs r1, #1 + 1187 .L100: +6367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1188 .loc 1 6367 1 view .LVU344 + 1189 0050 0846 mov r0, r1 + 1190 0052 70BD pop {r4, r5, r6, pc} + 1191 .LVL73: + 1192 .L108: +6329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1193 .loc 1 6329 7 is_stmt 1 view .LVU345 +6329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1194 .loc 1 6329 12 is_stmt 0 view .LVU346 + 1195 0054 9A69 ldr r2, [r3, #24] +6329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1196 .loc 1 6329 10 view .LVU347 + 1197 0056 12F0040F tst r2, #4 + 1198 005a 02D0 beq .L102 +6329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1199 .loc 1 6329 68 discriminator 1 view .LVU348 + 1200 005c 228D ldrh r2, [r4, #40] +6329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1201 .loc 1 6329 60 discriminator 1 view .LVU349 + 1202 005e 002A cmp r2, #0 + 1203 0060 F6D1 bne .L100 + 1204 .L102: +6338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1205 .loc 1 6338 9 is_stmt 1 view .LVU350 + 1206 0062 2022 movs r2, #32 + 1207 0064 DA61 str r2, [r3, #28] +6341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1208 .loc 1 6341 9 view .LVU351 + 1209 0066 2168 ldr r1, [r4] + 1210 0068 4B68 ldr r3, [r1, #4] + 1211 006a 23F0FF73 bic r3, r3, #33423360 + 1212 006e 23F48B33 bic r3, r3, #71168 + 1213 0072 23F4FF73 bic r3, r3, #510 + 1214 0076 23F00103 bic r3, r3, #1 + 1215 007a 4B60 str r3, [r1, #4] +6343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1216 .loc 1 6343 9 view .LVU352 +6343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1217 .loc 1 6343 25 is_stmt 0 view .LVU353 + 1218 007c 0023 movs r3, #0 + 1219 007e 6364 str r3, [r4, #68] +6344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1220 .loc 1 6344 9 is_stmt 1 view .LVU354 +6344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1221 .loc 1 6344 21 is_stmt 0 view .LVU355 + 1222 0080 84F84120 strb r2, [r4, #65] +6345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1223 .loc 1 6345 9 is_stmt 1 view .LVU356 +6345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1224 .loc 1 6345 20 is_stmt 0 view .LVU357 + 1225 0084 84F84230 strb r3, [r4, #66] + ARM GAS /tmp/ccEimIdZ.s page 143 + + +6348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1226 .loc 1 6348 9 is_stmt 1 view .LVU358 +6348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1227 .loc 1 6348 9 view .LVU359 + 1228 0088 84F84030 strb r3, [r4, #64] +6348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1229 .loc 1 6348 9 view .LVU360 +6350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1230 .loc 1 6350 9 view .LVU361 +6350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1231 .loc 1 6350 16 is_stmt 0 view .LVU362 + 1232 008c 0121 movs r1, #1 + 1233 008e DFE7 b .L100 + 1234 .L107: +6366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1235 .loc 1 6366 10 view .LVU363 + 1236 0090 0021 movs r1, #0 + 1237 0092 DDE7 b .L100 + 1238 .L105: +6321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1239 .loc 1 6321 14 view .LVU364 + 1240 0094 0121 movs r1, #1 + 1241 0096 DBE7 b .L100 + 1242 .cfi_endproc + 1243 .LFE214: + 1245 .section .text.HAL_I2C_MspInit,"ax",%progbits + 1246 .align 1 + 1247 .weak HAL_I2C_MspInit + 1248 .syntax unified + 1249 .thumb + 1250 .thumb_func + 1251 .fpu fpv5-d16 + 1253 HAL_I2C_MspInit: + 1254 .LVL74: + 1255 .LFB143: + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1256 .loc 1 628 1 is_stmt 1 view -0 + 1257 .cfi_startproc + 1258 @ args = 0, pretend = 0, frame = 0 + 1259 @ frame_needed = 0, uses_anonymous_args = 0 + 1260 @ link register save eliminated. + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1261 .loc 1 630 3 view .LVU366 + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1262 .loc 1 635 1 is_stmt 0 view .LVU367 + 1263 0000 7047 bx lr + 1264 .cfi_endproc + 1265 .LFE143: + 1267 .section .text.HAL_I2C_Init,"ax",%progbits + 1268 .align 1 + 1269 .global HAL_I2C_Init + 1270 .syntax unified + 1271 .thumb + 1272 .thumb_func + 1273 .fpu fpv5-d16 + 1275 HAL_I2C_Init: + 1276 .LVL75: + ARM GAS /tmp/ccEimIdZ.s page 144 + + + 1277 .LFB141: + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1278 .loc 1 473 1 is_stmt 1 view -0 + 1279 .cfi_startproc + 1280 @ args = 0, pretend = 0, frame = 0 + 1281 @ frame_needed = 0, uses_anonymous_args = 0 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1282 .loc 1 475 3 view .LVU369 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1283 .loc 1 475 6 is_stmt 0 view .LVU370 + 1284 0000 0028 cmp r0, #0 + 1285 0002 57D0 beq .L116 + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1286 .loc 1 473 1 view .LVU371 + 1287 0004 10B5 push {r4, lr} + 1288 .LCFI15: + 1289 .cfi_def_cfa_offset 8 + 1290 .cfi_offset 4, -8 + 1291 .cfi_offset 14, -4 + 1292 0006 0446 mov r4, r0 + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 1293 .loc 1 481 3 is_stmt 1 view .LVU372 + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 1294 .loc 1 482 3 view .LVU373 + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 1295 .loc 1 483 3 view .LVU374 + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 1296 .loc 1 484 3 view .LVU375 + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 1297 .loc 1 485 3 view .LVU376 + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 1298 .loc 1 486 3 view .LVU377 + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 1299 .loc 1 487 3 view .LVU378 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1300 .loc 1 488 3 view .LVU379 + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1301 .loc 1 490 3 view .LVU380 + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1302 .loc 1 490 11 is_stmt 0 view .LVU381 + 1303 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1304 .loc 1 490 6 view .LVU382 + 1305 000c 002B cmp r3, #0 + 1306 000e 41D0 beq .L121 + 1307 .LVL76: + 1308 .L112: + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1309 .loc 1 521 3 is_stmt 1 view .LVU383 + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1310 .loc 1 521 15 is_stmt 0 view .LVU384 + 1311 0010 2423 movs r3, #36 + 1312 0012 84F84130 strb r3, [r4, #65] + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1313 .loc 1 524 3 is_stmt 1 view .LVU385 + 1314 0016 2268 ldr r2, [r4] + 1315 0018 1368 ldr r3, [r2] + ARM GAS /tmp/ccEimIdZ.s page 145 + + + 1316 001a 23F00103 bic r3, r3, #1 + 1317 001e 1360 str r3, [r2] + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1318 .loc 1 528 3 view .LVU386 + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1319 .loc 1 528 39 is_stmt 0 view .LVU387 + 1320 0020 6368 ldr r3, [r4, #4] + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1321 .loc 1 528 7 view .LVU388 + 1322 0022 2268 ldr r2, [r4] + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1323 .loc 1 528 47 view .LVU389 + 1324 0024 23F07063 bic r3, r3, #251658240 + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1325 .loc 1 528 27 view .LVU390 + 1326 0028 1361 str r3, [r2, #16] + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1327 .loc 1 532 3 is_stmt 1 view .LVU391 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1328 .loc 1 532 7 is_stmt 0 view .LVU392 + 1329 002a 2268 ldr r2, [r4] + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1330 .loc 1 532 24 view .LVU393 + 1331 002c 9368 ldr r3, [r2, #8] + 1332 002e 23F40043 bic r3, r3, #32768 + 1333 0032 9360 str r3, [r2, #8] + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1334 .loc 1 535 3 is_stmt 1 view .LVU394 + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1335 .loc 1 535 17 is_stmt 0 view .LVU395 + 1336 0034 E368 ldr r3, [r4, #12] + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1337 .loc 1 535 6 view .LVU396 + 1338 0036 012B cmp r3, #1 + 1339 0038 31D0 beq .L122 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1340 .loc 1 541 5 is_stmt 1 view .LVU397 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1341 .loc 1 541 75 is_stmt 0 view .LVU398 + 1342 003a A368 ldr r3, [r4, #8] + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1343 .loc 1 541 9 view .LVU399 + 1344 003c 2268 ldr r2, [r4] + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1345 .loc 1 541 63 view .LVU400 + 1346 003e 43F40443 orr r3, r3, #33792 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1347 .loc 1 541 26 view .LVU401 + 1348 0042 9360 str r3, [r2, #8] + 1349 .L114: + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1350 .loc 1 546 3 is_stmt 1 view .LVU402 + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1351 .loc 1 546 17 is_stmt 0 view .LVU403 + 1352 0044 E368 ldr r3, [r4, #12] + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1353 .loc 1 546 6 view .LVU404 + ARM GAS /tmp/ccEimIdZ.s page 146 + + + 1354 0046 022B cmp r3, #2 + 1355 0048 2FD0 beq .L123 + 1356 .L115: + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1357 .loc 1 551 3 is_stmt 1 view .LVU405 + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1358 .loc 1 551 7 is_stmt 0 view .LVU406 + 1359 004a 2268 ldr r2, [r4] + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1360 .loc 1 551 23 view .LVU407 + 1361 004c 5168 ldr r1, [r2, #4] + 1362 004e 1A4B ldr r3, .L124 + 1363 0050 0B43 orrs r3, r3, r1 + 1364 0052 5360 str r3, [r2, #4] + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1365 .loc 1 555 3 is_stmt 1 view .LVU408 + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1366 .loc 1 555 7 is_stmt 0 view .LVU409 + 1367 0054 2268 ldr r2, [r4] + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1368 .loc 1 555 24 view .LVU410 + 1369 0056 D368 ldr r3, [r2, #12] + 1370 0058 23F40043 bic r3, r3, #32768 + 1371 005c D360 str r3, [r2, #12] + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1372 .loc 1 558 3 is_stmt 1 view .LVU411 + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1373 .loc 1 558 37 is_stmt 0 view .LVU412 + 1374 005e 2369 ldr r3, [r4, #16] + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1375 .loc 1 558 66 view .LVU413 + 1376 0060 6269 ldr r2, [r4, #20] + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1377 .loc 1 558 54 view .LVU414 + 1378 0062 1343 orrs r3, r3, r2 + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1379 .loc 1 558 92 view .LVU415 + 1380 0064 A169 ldr r1, [r4, #24] + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1381 .loc 1 558 7 view .LVU416 + 1382 0066 2268 ldr r2, [r4] + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1383 .loc 1 558 79 view .LVU417 + 1384 0068 43EA0123 orr r3, r3, r1, lsl #8 + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1385 .loc 1 558 24 view .LVU418 + 1386 006c D360 str r3, [r2, #12] + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1387 .loc 1 562 3 is_stmt 1 view .LVU419 + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1388 .loc 1 562 36 is_stmt 0 view .LVU420 + 1389 006e E369 ldr r3, [r4, #28] + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1390 .loc 1 562 65 view .LVU421 + 1391 0070 216A ldr r1, [r4, #32] + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1392 .loc 1 562 7 view .LVU422 + ARM GAS /tmp/ccEimIdZ.s page 147 + + + 1393 0072 2268 ldr r2, [r4] + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1394 .loc 1 562 53 view .LVU423 + 1395 0074 0B43 orrs r3, r3, r1 + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1396 .loc 1 562 23 view .LVU424 + 1397 0076 1360 str r3, [r2] + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1398 .loc 1 565 3 is_stmt 1 view .LVU425 + 1399 0078 2268 ldr r2, [r4] + 1400 007a 1368 ldr r3, [r2] + 1401 007c 43F00103 orr r3, r3, #1 + 1402 0080 1360 str r3, [r2] + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1403 .loc 1 567 3 view .LVU426 + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1404 .loc 1 567 19 is_stmt 0 view .LVU427 + 1405 0082 0020 movs r0, #0 + 1406 0084 6064 str r0, [r4, #68] + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1407 .loc 1 568 3 is_stmt 1 view .LVU428 + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1408 .loc 1 568 15 is_stmt 0 view .LVU429 + 1409 0086 2023 movs r3, #32 + 1410 0088 84F84130 strb r3, [r4, #65] + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1411 .loc 1 569 3 is_stmt 1 view .LVU430 + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1412 .loc 1 569 23 is_stmt 0 view .LVU431 + 1413 008c 2063 str r0, [r4, #48] + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1414 .loc 1 570 3 is_stmt 1 view .LVU432 + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1415 .loc 1 570 14 is_stmt 0 view .LVU433 + 1416 008e 84F84200 strb r0, [r4, #66] + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1417 .loc 1 572 3 is_stmt 1 view .LVU434 + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1418 .loc 1 573 1 is_stmt 0 view .LVU435 + 1419 0092 10BD pop {r4, pc} + 1420 .LVL77: + 1421 .L121: + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1422 .loc 1 493 5 is_stmt 1 view .LVU436 + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1423 .loc 1 493 16 is_stmt 0 view .LVU437 + 1424 0094 80F84030 strb r3, [r0, #64] + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1425 .loc 1 517 5 is_stmt 1 view .LVU438 + 1426 0098 FFF7FEFF bl HAL_I2C_MspInit + 1427 .LVL78: + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1428 .loc 1 517 5 is_stmt 0 view .LVU439 + 1429 009c B8E7 b .L112 + 1430 .L122: + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1431 .loc 1 537 5 is_stmt 1 view .LVU440 + ARM GAS /tmp/ccEimIdZ.s page 148 + + + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1432 .loc 1 537 56 is_stmt 0 view .LVU441 + 1433 009e A368 ldr r3, [r4, #8] + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1434 .loc 1 537 9 view .LVU442 + 1435 00a0 2268 ldr r2, [r4] + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1436 .loc 1 537 44 view .LVU443 + 1437 00a2 43F40043 orr r3, r3, #32768 + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1438 .loc 1 537 26 view .LVU444 + 1439 00a6 9360 str r3, [r2, #8] + 1440 00a8 CCE7 b .L114 + 1441 .L123: + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1442 .loc 1 548 5 is_stmt 1 view .LVU445 + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1443 .loc 1 548 9 is_stmt 0 view .LVU446 + 1444 00aa 2368 ldr r3, [r4] + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1445 .loc 1 548 25 view .LVU447 + 1446 00ac 4FF40062 mov r2, #2048 + 1447 00b0 5A60 str r2, [r3, #4] + 1448 00b2 CAE7 b .L115 + 1449 .LVL79: + 1450 .L116: + 1451 .LCFI16: + 1452 .cfi_def_cfa_offset 0 + 1453 .cfi_restore 4 + 1454 .cfi_restore 14 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1455 .loc 1 477 12 view .LVU448 + 1456 00b4 0120 movs r0, #1 + 1457 .LVL80: + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1458 .loc 1 573 1 view .LVU449 + 1459 00b6 7047 bx lr + 1460 .L125: + 1461 .align 2 + 1462 .L124: + 1463 00b8 00800002 .word 33587200 + 1464 .cfi_endproc + 1465 .LFE141: + 1467 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 1468 .align 1 + 1469 .weak HAL_I2C_MspDeInit + 1470 .syntax unified + 1471 .thumb + 1472 .thumb_func + 1473 .fpu fpv5-d16 + 1475 HAL_I2C_MspDeInit: + 1476 .LVL81: + 1477 .LFB144: + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1478 .loc 1 644 1 is_stmt 1 view -0 + 1479 .cfi_startproc + 1480 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccEimIdZ.s page 149 + + + 1481 @ frame_needed = 0, uses_anonymous_args = 0 + 1482 @ link register save eliminated. + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1483 .loc 1 646 3 view .LVU451 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1484 .loc 1 651 1 is_stmt 0 view .LVU452 + 1485 0000 7047 bx lr + 1486 .cfi_endproc + 1487 .LFE144: + 1489 .section .text.HAL_I2C_DeInit,"ax",%progbits + 1490 .align 1 + 1491 .global HAL_I2C_DeInit + 1492 .syntax unified + 1493 .thumb + 1494 .thumb_func + 1495 .fpu fpv5-d16 + 1497 HAL_I2C_DeInit: + 1498 .LVL82: + 1499 .LFB142: + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1500 .loc 1 582 1 is_stmt 1 view -0 + 1501 .cfi_startproc + 1502 @ args = 0, pretend = 0, frame = 0 + 1503 @ frame_needed = 0, uses_anonymous_args = 0 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1504 .loc 1 584 3 view .LVU454 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1505 .loc 1 584 6 is_stmt 0 view .LVU455 + 1506 0000 A8B1 cbz r0, .L129 + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1507 .loc 1 582 1 view .LVU456 + 1508 0002 10B5 push {r4, lr} + 1509 .LCFI17: + 1510 .cfi_def_cfa_offset 8 + 1511 .cfi_offset 4, -8 + 1512 .cfi_offset 14, -4 + 1513 0004 0446 mov r4, r0 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1514 .loc 1 590 3 is_stmt 1 view .LVU457 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1515 .loc 1 592 3 view .LVU458 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1516 .loc 1 592 15 is_stmt 0 view .LVU459 + 1517 0006 2423 movs r3, #36 + 1518 0008 80F84130 strb r3, [r0, #65] + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1519 .loc 1 595 3 is_stmt 1 view .LVU460 + 1520 000c 0268 ldr r2, [r0] + 1521 000e 1368 ldr r3, [r2] + 1522 0010 23F00103 bic r3, r3, #1 + 1523 0014 1360 str r3, [r2] + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1524 .loc 1 607 3 view .LVU461 + 1525 0016 FFF7FEFF bl HAL_I2C_MspDeInit + 1526 .LVL83: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1527 .loc 1 610 3 view .LVU462 + ARM GAS /tmp/ccEimIdZ.s page 150 + + + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1528 .loc 1 610 19 is_stmt 0 view .LVU463 + 1529 001a 0020 movs r0, #0 + 1530 001c 6064 str r0, [r4, #68] + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1531 .loc 1 611 3 is_stmt 1 view .LVU464 + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1532 .loc 1 611 15 is_stmt 0 view .LVU465 + 1533 001e 84F84100 strb r0, [r4, #65] + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1534 .loc 1 612 3 is_stmt 1 view .LVU466 + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1535 .loc 1 612 23 is_stmt 0 view .LVU467 + 1536 0022 2063 str r0, [r4, #48] + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1537 .loc 1 613 3 is_stmt 1 view .LVU468 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1538 .loc 1 613 14 is_stmt 0 view .LVU469 + 1539 0024 84F84200 strb r0, [r4, #66] + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1540 .loc 1 616 3 is_stmt 1 view .LVU470 + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1541 .loc 1 616 3 view .LVU471 + 1542 0028 84F84000 strb r0, [r4, #64] + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1543 .loc 1 616 3 view .LVU472 + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1544 .loc 1 618 3 view .LVU473 + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1545 .loc 1 619 1 is_stmt 0 view .LVU474 + 1546 002c 10BD pop {r4, pc} + 1547 .LVL84: + 1548 .L129: + 1549 .LCFI18: + 1550 .cfi_def_cfa_offset 0 + 1551 .cfi_restore 4 + 1552 .cfi_restore 14 + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1553 .loc 1 586 12 view .LVU475 + 1554 002e 0120 movs r0, #1 + 1555 .LVL85: + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1556 .loc 1 619 1 view .LVU476 + 1557 0030 7047 bx lr + 1558 .cfi_endproc + 1559 .LFE142: + 1561 .section .text.HAL_I2C_Master_Transmit,"ax",%progbits + 1562 .align 1 + 1563 .global HAL_I2C_Master_Transmit + 1564 .syntax unified + 1565 .thumb + 1566 .thumb_func + 1567 .fpu fpv5-d16 + 1569 HAL_I2C_Master_Transmit: + 1570 .LVL86: + 1571 .LFB145: +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + ARM GAS /tmp/ccEimIdZ.s page 151 + + + 1572 .loc 1 1064 1 is_stmt 1 view -0 + 1573 .cfi_startproc + 1574 @ args = 4, pretend = 0, frame = 0 + 1575 @ frame_needed = 0, uses_anonymous_args = 0 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 1576 .loc 1 1064 1 is_stmt 0 view .LVU478 + 1577 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 1578 .LCFI19: + 1579 .cfi_def_cfa_offset 32 + 1580 .cfi_offset 4, -32 + 1581 .cfi_offset 5, -28 + 1582 .cfi_offset 6, -24 + 1583 .cfi_offset 7, -20 + 1584 .cfi_offset 8, -16 + 1585 .cfi_offset 9, -12 + 1586 .cfi_offset 10, -8 + 1587 .cfi_offset 14, -4 + 1588 0004 82B0 sub sp, sp, #8 + 1589 .LCFI20: + 1590 .cfi_def_cfa_offset 40 + 1591 0006 0F46 mov r7, r1 + 1592 0008 0A9E ldr r6, [sp, #40] +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1593 .loc 1 1065 3 is_stmt 1 view .LVU479 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1594 .loc 1 1067 3 view .LVU480 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1595 .loc 1 1067 11 is_stmt 0 view .LVU481 + 1596 000a 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 1597 .LVL87: +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1598 .loc 1 1067 11 view .LVU482 + 1599 000e C9B2 uxtb r1, r1 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1600 .loc 1 1067 6 view .LVU483 + 1601 0010 2029 cmp r1, #32 + 1602 0012 40F0A380 bne .L142 + 1603 0016 0446 mov r4, r0 + 1604 0018 9046 mov r8, r2 + 1605 001a 9946 mov r9, r3 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1606 .loc 1 1070 5 is_stmt 1 view .LVU484 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1607 .loc 1 1070 5 view .LVU485 + 1608 001c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 1609 .LVL88: +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1610 .loc 1 1070 5 is_stmt 0 view .LVU486 + 1611 0020 012B cmp r3, #1 + 1612 0022 00F09F80 beq .L143 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1613 .loc 1 1070 5 is_stmt 1 discriminator 2 view .LVU487 + 1614 0026 4FF0010A mov r10, #1 + 1615 002a 80F840A0 strb r10, [r0, #64] +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1616 .loc 1 1070 5 discriminator 2 view .LVU488 +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 152 + + + 1617 .loc 1 1073 5 discriminator 2 view .LVU489 +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1618 .loc 1 1073 17 is_stmt 0 discriminator 2 view .LVU490 + 1619 002e FFF7FEFF bl HAL_GetTick + 1620 .LVL89: +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1621 .loc 1 1073 17 discriminator 2 view .LVU491 + 1622 0032 0546 mov r5, r0 + 1623 .LVL90: +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1624 .loc 1 1075 5 is_stmt 1 discriminator 2 view .LVU492 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1625 .loc 1 1075 9 is_stmt 0 discriminator 2 view .LVU493 + 1626 0034 0090 str r0, [sp] + 1627 0036 1923 movs r3, #25 + 1628 0038 5246 mov r2, r10 + 1629 003a 4FF40041 mov r1, #32768 + 1630 003e 2046 mov r0, r4 + 1631 .LVL91: +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1632 .loc 1 1075 9 discriminator 2 view .LVU494 + 1633 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1634 .LVL92: +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1635 .loc 1 1075 8 discriminator 2 view .LVU495 + 1636 0044 0028 cmp r0, #0 + 1637 0046 40F08F80 bne .L144 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1638 .loc 1 1080 5 is_stmt 1 view .LVU496 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1639 .loc 1 1080 21 is_stmt 0 view .LVU497 + 1640 004a 2123 movs r3, #33 + 1641 004c 84F84130 strb r3, [r4, #65] +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1642 .loc 1 1081 5 is_stmt 1 view .LVU498 +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1643 .loc 1 1081 21 is_stmt 0 view .LVU499 + 1644 0050 1023 movs r3, #16 + 1645 0052 84F84230 strb r3, [r4, #66] +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1646 .loc 1 1082 5 is_stmt 1 view .LVU500 +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1647 .loc 1 1082 21 is_stmt 0 view .LVU501 + 1648 0056 0023 movs r3, #0 + 1649 0058 6364 str r3, [r4, #68] +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 1650 .loc 1 1085 5 is_stmt 1 view .LVU502 +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 1651 .loc 1 1085 21 is_stmt 0 view .LVU503 + 1652 005a C4F82480 str r8, [r4, #36] +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1653 .loc 1 1086 5 is_stmt 1 view .LVU504 +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1654 .loc 1 1086 21 is_stmt 0 view .LVU505 + 1655 005e A4F82A90 strh r9, [r4, #42] @ movhi +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1656 .loc 1 1087 5 is_stmt 1 view .LVU506 + ARM GAS /tmp/ccEimIdZ.s page 153 + + +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1657 .loc 1 1087 21 is_stmt 0 view .LVU507 + 1658 0062 6363 str r3, [r4, #52] +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1659 .loc 1 1091 5 is_stmt 1 view .LVU508 +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1660 .loc 1 1091 13 is_stmt 0 view .LVU509 + 1661 0064 638D ldrh r3, [r4, #42] + 1662 0066 9BB2 uxth r3, r3 +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1663 .loc 1 1091 8 view .LVU510 + 1664 0068 FF2B cmp r3, #255 + 1665 006a 0AD9 bls .L136 +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S + 1666 .loc 1 1093 7 is_stmt 1 view .LVU511 +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S + 1667 .loc 1 1093 22 is_stmt 0 view .LVU512 + 1668 006c FF22 movs r2, #255 + 1669 006e 2285 strh r2, [r4, #40] @ movhi +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1670 .loc 1 1094 7 is_stmt 1 view .LVU513 + 1671 0070 414B ldr r3, .L150 + 1672 0072 0093 str r3, [sp] + 1673 0074 4FF08073 mov r3, #16777216 + 1674 0078 3946 mov r1, r7 + 1675 007a 2046 mov r0, r4 + 1676 007c FFF7FEFF bl I2C_TransferConfig + 1677 .LVL93: + 1678 0080 18E0 b .L138 + 1679 .L136: +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 1680 .loc 1 1098 7 view .LVU514 +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 1681 .loc 1 1098 28 is_stmt 0 view .LVU515 + 1682 0082 628D ldrh r2, [r4, #42] + 1683 0084 92B2 uxth r2, r2 +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 1684 .loc 1 1098 22 view .LVU516 + 1685 0086 2285 strh r2, [r4, #40] @ movhi +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1686 .loc 1 1099 7 is_stmt 1 view .LVU517 + 1687 0088 3B4B ldr r3, .L150 + 1688 008a 0093 str r3, [sp] + 1689 008c 4FF00073 mov r3, #33554432 + 1690 0090 D2B2 uxtb r2, r2 + 1691 0092 3946 mov r1, r7 + 1692 0094 2046 mov r0, r4 + 1693 0096 FFF7FEFF bl I2C_TransferConfig + 1694 .LVL94: + 1695 009a 0BE0 b .L138 + 1696 .L140: +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 1697 .loc 1 1133 11 view .LVU518 +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 1698 .loc 1 1133 32 is_stmt 0 view .LVU519 + 1699 009c 628D ldrh r2, [r4, #42] + 1700 009e 92B2 uxth r2, r2 + ARM GAS /tmp/ccEimIdZ.s page 154 + + +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 1701 .loc 1 1133 26 view .LVU520 + 1702 00a0 2285 strh r2, [r4, #40] @ movhi +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1703 .loc 1 1134 11 is_stmt 1 view .LVU521 + 1704 00a2 0023 movs r3, #0 + 1705 00a4 0093 str r3, [sp] + 1706 00a6 4FF00073 mov r3, #33554432 + 1707 00aa D2B2 uxtb r2, r2 + 1708 00ac 3946 mov r1, r7 + 1709 00ae 2046 mov r0, r4 + 1710 00b0 FFF7FEFF bl I2C_TransferConfig + 1711 .LVL95: + 1712 .L138: +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1713 .loc 1 1102 11 view .LVU522 +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1714 .loc 1 1102 16 is_stmt 0 view .LVU523 + 1715 00b4 638D ldrh r3, [r4, #42] + 1716 00b6 9BB2 uxth r3, r3 +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1717 .loc 1 1102 11 view .LVU524 + 1718 00b8 002B cmp r3, #0 + 1719 00ba 33D0 beq .L149 +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1720 .loc 1 1105 7 is_stmt 1 view .LVU525 +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1721 .loc 1 1105 11 is_stmt 0 view .LVU526 + 1722 00bc 2A46 mov r2, r5 + 1723 00be 3146 mov r1, r6 + 1724 00c0 2046 mov r0, r4 + 1725 00c2 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1726 .LVL96: +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1727 .loc 1 1105 10 view .LVU527 + 1728 00c6 0028 cmp r0, #0 + 1729 00c8 50D1 bne .L145 +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1730 .loc 1 1110 7 is_stmt 1 view .LVU528 +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1731 .loc 1 1110 35 is_stmt 0 view .LVU529 + 1732 00ca 626A ldr r2, [r4, #36] +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1733 .loc 1 1110 11 view .LVU530 + 1734 00cc 2368 ldr r3, [r4] +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1735 .loc 1 1110 30 view .LVU531 + 1736 00ce 1278 ldrb r2, [r2] @ zero_extendqisi2 +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1737 .loc 1 1110 28 view .LVU532 + 1738 00d0 9A62 str r2, [r3, #40] +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1739 .loc 1 1113 7 is_stmt 1 view .LVU533 +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1740 .loc 1 1113 11 is_stmt 0 view .LVU534 + 1741 00d2 636A ldr r3, [r4, #36] +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 155 + + + 1742 .loc 1 1113 21 view .LVU535 + 1743 00d4 0133 adds r3, r3, #1 + 1744 00d6 6362 str r3, [r4, #36] +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 1745 .loc 1 1115 7 is_stmt 1 view .LVU536 +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 1746 .loc 1 1115 11 is_stmt 0 view .LVU537 + 1747 00d8 638D ldrh r3, [r4, #42] + 1748 00da 9BB2 uxth r3, r3 +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 1749 .loc 1 1115 22 view .LVU538 + 1750 00dc 013B subs r3, r3, #1 + 1751 00de 9BB2 uxth r3, r3 + 1752 00e0 6385 strh r3, [r4, #42] @ movhi +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1753 .loc 1 1116 7 is_stmt 1 view .LVU539 +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1754 .loc 1 1116 11 is_stmt 0 view .LVU540 + 1755 00e2 238D ldrh r3, [r4, #40] +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1756 .loc 1 1116 21 view .LVU541 + 1757 00e4 013B subs r3, r3, #1 + 1758 00e6 9BB2 uxth r3, r3 + 1759 00e8 2385 strh r3, [r4, #40] @ movhi +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1760 .loc 1 1118 7 is_stmt 1 view .LVU542 +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1761 .loc 1 1118 16 is_stmt 0 view .LVU543 + 1762 00ea 628D ldrh r2, [r4, #42] + 1763 00ec 92B2 uxth r2, r2 +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1764 .loc 1 1118 10 view .LVU544 + 1765 00ee 002A cmp r2, #0 + 1766 00f0 E0D0 beq .L138 +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1767 .loc 1 1118 35 discriminator 1 view .LVU545 + 1768 00f2 002B cmp r3, #0 + 1769 00f4 DED1 bne .L138 +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1770 .loc 1 1121 9 is_stmt 1 view .LVU546 +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1771 .loc 1 1121 13 is_stmt 0 view .LVU547 + 1772 00f6 0095 str r5, [sp] + 1773 00f8 3346 mov r3, r6 + 1774 00fa 0022 movs r2, #0 + 1775 00fc 8021 movs r1, #128 + 1776 00fe 2046 mov r0, r4 + 1777 0100 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1778 .LVL97: +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1779 .loc 1 1121 12 view .LVU548 + 1780 0104 A0BB cbnz r0, .L146 +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1781 .loc 1 1126 9 is_stmt 1 view .LVU549 +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1782 .loc 1 1126 17 is_stmt 0 view .LVU550 + 1783 0106 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccEimIdZ.s page 156 + + + 1784 0108 9BB2 uxth r3, r3 +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1785 .loc 1 1126 12 view .LVU551 + 1786 010a FF2B cmp r3, #255 + 1787 010c C6D9 bls .L140 +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA + 1788 .loc 1 1128 11 is_stmt 1 view .LVU552 +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA + 1789 .loc 1 1128 26 is_stmt 0 view .LVU553 + 1790 010e FF22 movs r2, #255 + 1791 0110 2285 strh r2, [r4, #40] @ movhi +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1792 .loc 1 1129 11 is_stmt 1 view .LVU554 + 1793 0112 0023 movs r3, #0 + 1794 0114 0093 str r3, [sp] + 1795 0116 4FF08073 mov r3, #16777216 + 1796 011a 3946 mov r1, r7 + 1797 011c 2046 mov r0, r4 + 1798 011e FFF7FEFF bl I2C_TransferConfig + 1799 .LVL98: + 1800 0122 C7E7 b .L138 + 1801 .L149: +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1802 .loc 1 1141 5 view .LVU555 +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1803 .loc 1 1141 9 is_stmt 0 view .LVU556 + 1804 0124 2A46 mov r2, r5 + 1805 0126 3146 mov r1, r6 + 1806 0128 2046 mov r0, r4 + 1807 012a FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 1808 .LVL99: +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1809 .loc 1 1141 8 view .LVU557 + 1810 012e 08BB cbnz r0, .L147 +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1811 .loc 1 1147 5 is_stmt 1 view .LVU558 + 1812 0130 2368 ldr r3, [r4] + 1813 0132 2022 movs r2, #32 + 1814 0134 DA61 str r2, [r3, #28] +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1815 .loc 1 1150 5 view .LVU559 + 1816 0136 2168 ldr r1, [r4] + 1817 0138 4B68 ldr r3, [r1, #4] + 1818 013a 23F0FF73 bic r3, r3, #33423360 + 1819 013e 23F48B33 bic r3, r3, #71168 + 1820 0142 23F4FF73 bic r3, r3, #510 + 1821 0146 23F00103 bic r3, r3, #1 + 1822 014a 4B60 str r3, [r1, #4] +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1823 .loc 1 1152 5 view .LVU560 +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1824 .loc 1 1152 17 is_stmt 0 view .LVU561 + 1825 014c 84F84120 strb r2, [r4, #65] +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1826 .loc 1 1153 5 is_stmt 1 view .LVU562 +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1827 .loc 1 1153 17 is_stmt 0 view .LVU563 + ARM GAS /tmp/ccEimIdZ.s page 157 + + + 1828 0150 0023 movs r3, #0 + 1829 0152 84F84230 strb r3, [r4, #66] +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1830 .loc 1 1156 5 is_stmt 1 view .LVU564 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1831 .loc 1 1156 5 view .LVU565 + 1832 0156 84F84030 strb r3, [r4, #64] +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1833 .loc 1 1156 5 view .LVU566 +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1834 .loc 1 1158 5 view .LVU567 +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1835 .loc 1 1158 12 is_stmt 0 view .LVU568 + 1836 015a 00E0 b .L135 + 1837 .LVL100: + 1838 .L142: +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1839 .loc 1 1162 12 view .LVU569 + 1840 015c 0220 movs r0, #2 + 1841 .LVL101: + 1842 .L135: +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1843 .loc 1 1164 1 view .LVU570 + 1844 015e 02B0 add sp, sp, #8 + 1845 .LCFI21: + 1846 .cfi_remember_state + 1847 .cfi_def_cfa_offset 32 + 1848 @ sp needed + 1849 0160 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 1850 .LVL102: + 1851 .L143: + 1852 .LCFI22: + 1853 .cfi_restore_state +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1854 .loc 1 1070 5 view .LVU571 + 1855 0164 0220 movs r0, #2 + 1856 .LVL103: +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1857 .loc 1 1070 5 view .LVU572 + 1858 0166 FAE7 b .L135 + 1859 .LVL104: + 1860 .L144: +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1861 .loc 1 1077 14 view .LVU573 + 1862 0168 0120 movs r0, #1 + 1863 016a F8E7 b .L135 + 1864 .L145: +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1865 .loc 1 1107 16 view .LVU574 + 1866 016c 0120 movs r0, #1 + 1867 016e F6E7 b .L135 + 1868 .L146: +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1869 .loc 1 1123 18 view .LVU575 + 1870 0170 0120 movs r0, #1 + 1871 0172 F4E7 b .L135 + 1872 .L147: + ARM GAS /tmp/ccEimIdZ.s page 158 + + +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1873 .loc 1 1143 14 view .LVU576 + 1874 0174 0120 movs r0, #1 + 1875 0176 F2E7 b .L135 + 1876 .L151: + 1877 .align 2 + 1878 .L150: + 1879 0178 00200080 .word -2147475456 + 1880 .cfi_endproc + 1881 .LFE145: + 1883 .section .text.HAL_I2C_Master_Receive,"ax",%progbits + 1884 .align 1 + 1885 .global HAL_I2C_Master_Receive + 1886 .syntax unified + 1887 .thumb + 1888 .thumb_func + 1889 .fpu fpv5-d16 + 1891 HAL_I2C_Master_Receive: + 1892 .LVL105: + 1893 .LFB146: +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 1894 .loc 1 1178 1 is_stmt 1 view -0 + 1895 .cfi_startproc + 1896 @ args = 4, pretend = 0, frame = 0 + 1897 @ frame_needed = 0, uses_anonymous_args = 0 +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 1898 .loc 1 1178 1 is_stmt 0 view .LVU578 + 1899 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 1900 .LCFI23: + 1901 .cfi_def_cfa_offset 32 + 1902 .cfi_offset 4, -32 + 1903 .cfi_offset 5, -28 + 1904 .cfi_offset 6, -24 + 1905 .cfi_offset 7, -20 + 1906 .cfi_offset 8, -16 + 1907 .cfi_offset 9, -12 + 1908 .cfi_offset 10, -8 + 1909 .cfi_offset 14, -4 + 1910 0004 82B0 sub sp, sp, #8 + 1911 .LCFI24: + 1912 .cfi_def_cfa_offset 40 + 1913 0006 0F46 mov r7, r1 + 1914 0008 0A9E ldr r6, [sp, #40] +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1915 .loc 1 1179 3 is_stmt 1 view .LVU579 +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1916 .loc 1 1181 3 view .LVU580 +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1917 .loc 1 1181 11 is_stmt 0 view .LVU581 + 1918 000a 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 1919 .LVL106: +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1920 .loc 1 1181 11 view .LVU582 + 1921 000e C9B2 uxtb r1, r1 +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1922 .loc 1 1181 6 view .LVU583 + 1923 0010 2029 cmp r1, #32 + ARM GAS /tmp/ccEimIdZ.s page 159 + + + 1924 0012 40F0A280 bne .L160 + 1925 0016 0446 mov r4, r0 + 1926 0018 9046 mov r8, r2 + 1927 001a 9946 mov r9, r3 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1928 .loc 1 1184 5 is_stmt 1 view .LVU584 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1929 .loc 1 1184 5 view .LVU585 + 1930 001c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 1931 .LVL107: +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1932 .loc 1 1184 5 is_stmt 0 view .LVU586 + 1933 0020 012B cmp r3, #1 + 1934 0022 00F09E80 beq .L161 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1935 .loc 1 1184 5 is_stmt 1 discriminator 2 view .LVU587 + 1936 0026 4FF0010A mov r10, #1 + 1937 002a 80F840A0 strb r10, [r0, #64] +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1938 .loc 1 1184 5 discriminator 2 view .LVU588 +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1939 .loc 1 1187 5 discriminator 2 view .LVU589 +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1940 .loc 1 1187 17 is_stmt 0 discriminator 2 view .LVU590 + 1941 002e FFF7FEFF bl HAL_GetTick + 1942 .LVL108: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1943 .loc 1 1187 17 discriminator 2 view .LVU591 + 1944 0032 0546 mov r5, r0 + 1945 .LVL109: +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1946 .loc 1 1189 5 is_stmt 1 discriminator 2 view .LVU592 +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1947 .loc 1 1189 9 is_stmt 0 discriminator 2 view .LVU593 + 1948 0034 0090 str r0, [sp] + 1949 0036 1923 movs r3, #25 + 1950 0038 5246 mov r2, r10 + 1951 003a 4FF40041 mov r1, #32768 + 1952 003e 2046 mov r0, r4 + 1953 .LVL110: +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1954 .loc 1 1189 9 discriminator 2 view .LVU594 + 1955 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1956 .LVL111: +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1957 .loc 1 1189 8 discriminator 2 view .LVU595 + 1958 0044 0028 cmp r0, #0 + 1959 0046 40F08E80 bne .L162 +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1960 .loc 1 1194 5 is_stmt 1 view .LVU596 +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1961 .loc 1 1194 21 is_stmt 0 view .LVU597 + 1962 004a 2223 movs r3, #34 + 1963 004c 84F84130 strb r3, [r4, #65] +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1964 .loc 1 1195 5 is_stmt 1 view .LVU598 +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/ccEimIdZ.s page 160 + + + 1965 .loc 1 1195 21 is_stmt 0 view .LVU599 + 1966 0050 1023 movs r3, #16 + 1967 0052 84F84230 strb r3, [r4, #66] +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1968 .loc 1 1196 5 is_stmt 1 view .LVU600 +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1969 .loc 1 1196 21 is_stmt 0 view .LVU601 + 1970 0056 0023 movs r3, #0 + 1971 0058 6364 str r3, [r4, #68] +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 1972 .loc 1 1199 5 is_stmt 1 view .LVU602 +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 1973 .loc 1 1199 21 is_stmt 0 view .LVU603 + 1974 005a C4F82480 str r8, [r4, #36] +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1975 .loc 1 1200 5 is_stmt 1 view .LVU604 +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1976 .loc 1 1200 21 is_stmt 0 view .LVU605 + 1977 005e A4F82A90 strh r9, [r4, #42] @ movhi +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1978 .loc 1 1201 5 is_stmt 1 view .LVU606 +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 1979 .loc 1 1201 21 is_stmt 0 view .LVU607 + 1980 0062 6363 str r3, [r4, #52] +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1981 .loc 1 1205 5 is_stmt 1 view .LVU608 +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1982 .loc 1 1205 13 is_stmt 0 view .LVU609 + 1983 0064 638D ldrh r3, [r4, #42] + 1984 0066 9BB2 uxth r3, r3 +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 1985 .loc 1 1205 8 view .LVU610 + 1986 0068 FF2B cmp r3, #255 + 1987 006a 0AD9 bls .L154 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S + 1988 .loc 1 1207 7 is_stmt 1 view .LVU611 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S + 1989 .loc 1 1207 22 is_stmt 0 view .LVU612 + 1990 006c FF22 movs r2, #255 + 1991 006e 2285 strh r2, [r4, #40] @ movhi +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 1992 .loc 1 1208 7 is_stmt 1 view .LVU613 + 1993 0070 414B ldr r3, .L168 + 1994 0072 0093 str r3, [sp] + 1995 0074 4FF08073 mov r3, #16777216 + 1996 0078 3946 mov r1, r7 + 1997 007a 2046 mov r0, r4 + 1998 007c FFF7FEFF bl I2C_TransferConfig + 1999 .LVL112: + 2000 0080 18E0 b .L156 + 2001 .L154: +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 2002 .loc 1 1212 7 view .LVU614 +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 2003 .loc 1 1212 28 is_stmt 0 view .LVU615 + 2004 0082 628D ldrh r2, [r4, #42] + 2005 0084 92B2 uxth r2, r2 + ARM GAS /tmp/ccEimIdZ.s page 161 + + +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 2006 .loc 1 1212 22 view .LVU616 + 2007 0086 2285 strh r2, [r4, #40] @ movhi +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2008 .loc 1 1213 7 is_stmt 1 view .LVU617 + 2009 0088 3B4B ldr r3, .L168 + 2010 008a 0093 str r3, [sp] + 2011 008c 4FF00073 mov r3, #33554432 + 2012 0090 D2B2 uxtb r2, r2 + 2013 0092 3946 mov r1, r7 + 2014 0094 2046 mov r0, r4 + 2015 0096 FFF7FEFF bl I2C_TransferConfig + 2016 .LVL113: + 2017 009a 0BE0 b .L156 + 2018 .L158: +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 2019 .loc 1 1248 11 view .LVU618 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 2020 .loc 1 1248 32 is_stmt 0 view .LVU619 + 2021 009c 628D ldrh r2, [r4, #42] + 2022 009e 92B2 uxth r2, r2 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 2023 .loc 1 1248 26 view .LVU620 + 2024 00a0 2285 strh r2, [r4, #40] @ movhi +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2025 .loc 1 1249 11 is_stmt 1 view .LVU621 + 2026 00a2 0023 movs r3, #0 + 2027 00a4 0093 str r3, [sp] + 2028 00a6 4FF00073 mov r3, #33554432 + 2029 00aa D2B2 uxtb r2, r2 + 2030 00ac 3946 mov r1, r7 + 2031 00ae 2046 mov r0, r4 + 2032 00b0 FFF7FEFF bl I2C_TransferConfig + 2033 .LVL114: + 2034 .L156: +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2035 .loc 1 1216 11 view .LVU622 +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2036 .loc 1 1216 16 is_stmt 0 view .LVU623 + 2037 00b4 638D ldrh r3, [r4, #42] + 2038 00b6 9BB2 uxth r3, r3 +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2039 .loc 1 1216 11 view .LVU624 + 2040 00b8 002B cmp r3, #0 + 2041 00ba 32D0 beq .L167 +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2042 .loc 1 1219 7 is_stmt 1 view .LVU625 +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2043 .loc 1 1219 11 is_stmt 0 view .LVU626 + 2044 00bc 2A46 mov r2, r5 + 2045 00be 3146 mov r1, r6 + 2046 00c0 2046 mov r0, r4 + 2047 00c2 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2048 .LVL115: +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2049 .loc 1 1219 10 view .LVU627 + 2050 00c6 0028 cmp r0, #0 + ARM GAS /tmp/ccEimIdZ.s page 162 + + + 2051 00c8 4FD1 bne .L163 +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2052 .loc 1 1225 7 is_stmt 1 view .LVU628 +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2053 .loc 1 1225 38 is_stmt 0 view .LVU629 + 2054 00ca 2368 ldr r3, [r4] +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2055 .loc 1 1225 48 view .LVU630 + 2056 00cc 5A6A ldr r2, [r3, #36] +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2057 .loc 1 1225 12 view .LVU631 + 2058 00ce 636A ldr r3, [r4, #36] +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2059 .loc 1 1225 23 view .LVU632 + 2060 00d0 1A70 strb r2, [r3] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2061 .loc 1 1228 7 is_stmt 1 view .LVU633 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2062 .loc 1 1228 11 is_stmt 0 view .LVU634 + 2063 00d2 636A ldr r3, [r4, #36] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2064 .loc 1 1228 21 view .LVU635 + 2065 00d4 0133 adds r3, r3, #1 + 2066 00d6 6362 str r3, [r4, #36] +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 2067 .loc 1 1230 7 is_stmt 1 view .LVU636 +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 2068 .loc 1 1230 11 is_stmt 0 view .LVU637 + 2069 00d8 228D ldrh r2, [r4, #40] +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 2070 .loc 1 1230 21 view .LVU638 + 2071 00da 013A subs r2, r2, #1 + 2072 00dc 92B2 uxth r2, r2 + 2073 00de 2285 strh r2, [r4, #40] @ movhi +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2074 .loc 1 1231 7 is_stmt 1 view .LVU639 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2075 .loc 1 1231 11 is_stmt 0 view .LVU640 + 2076 00e0 638D ldrh r3, [r4, #42] + 2077 00e2 9BB2 uxth r3, r3 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2078 .loc 1 1231 22 view .LVU641 + 2079 00e4 013B subs r3, r3, #1 + 2080 00e6 9BB2 uxth r3, r3 + 2081 00e8 6385 strh r3, [r4, #42] @ movhi +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2082 .loc 1 1233 7 is_stmt 1 view .LVU642 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2083 .loc 1 1233 16 is_stmt 0 view .LVU643 + 2084 00ea 638D ldrh r3, [r4, #42] + 2085 00ec 9BB2 uxth r3, r3 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2086 .loc 1 1233 10 view .LVU644 + 2087 00ee 002B cmp r3, #0 + 2088 00f0 E0D0 beq .L156 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2089 .loc 1 1233 35 discriminator 1 view .LVU645 + ARM GAS /tmp/ccEimIdZ.s page 163 + + + 2090 00f2 002A cmp r2, #0 + 2091 00f4 DED1 bne .L156 +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2092 .loc 1 1236 9 is_stmt 1 view .LVU646 +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2093 .loc 1 1236 13 is_stmt 0 view .LVU647 + 2094 00f6 0095 str r5, [sp] + 2095 00f8 3346 mov r3, r6 + 2096 00fa 8021 movs r1, #128 + 2097 00fc 2046 mov r0, r4 + 2098 00fe FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2099 .LVL116: +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2100 .loc 1 1236 12 view .LVU648 + 2101 0102 A0BB cbnz r0, .L164 +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2102 .loc 1 1241 9 is_stmt 1 view .LVU649 +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2103 .loc 1 1241 17 is_stmt 0 view .LVU650 + 2104 0104 638D ldrh r3, [r4, #42] + 2105 0106 9BB2 uxth r3, r3 +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2106 .loc 1 1241 12 view .LVU651 + 2107 0108 FF2B cmp r3, #255 + 2108 010a C7D9 bls .L158 +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA + 2109 .loc 1 1243 11 is_stmt 1 view .LVU652 +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA + 2110 .loc 1 1243 26 is_stmt 0 view .LVU653 + 2111 010c FF22 movs r2, #255 + 2112 010e 2285 strh r2, [r4, #40] @ movhi +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2113 .loc 1 1244 11 is_stmt 1 view .LVU654 + 2114 0110 0023 movs r3, #0 + 2115 0112 0093 str r3, [sp] + 2116 0114 4FF08073 mov r3, #16777216 + 2117 0118 3946 mov r1, r7 + 2118 011a 2046 mov r0, r4 + 2119 011c FFF7FEFF bl I2C_TransferConfig + 2120 .LVL117: + 2121 0120 C8E7 b .L156 + 2122 .L167: +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2123 .loc 1 1256 5 view .LVU655 +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2124 .loc 1 1256 9 is_stmt 0 view .LVU656 + 2125 0122 2A46 mov r2, r5 + 2126 0124 3146 mov r1, r6 + 2127 0126 2046 mov r0, r4 + 2128 0128 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2129 .LVL118: +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2130 .loc 1 1256 8 view .LVU657 + 2131 012c 08BB cbnz r0, .L165 +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2132 .loc 1 1262 5 is_stmt 1 view .LVU658 + 2133 012e 2368 ldr r3, [r4] + ARM GAS /tmp/ccEimIdZ.s page 164 + + + 2134 0130 2022 movs r2, #32 + 2135 0132 DA61 str r2, [r3, #28] +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2136 .loc 1 1265 5 view .LVU659 + 2137 0134 2168 ldr r1, [r4] + 2138 0136 4B68 ldr r3, [r1, #4] + 2139 0138 23F0FF73 bic r3, r3, #33423360 + 2140 013c 23F48B33 bic r3, r3, #71168 + 2141 0140 23F4FF73 bic r3, r3, #510 + 2142 0144 23F00103 bic r3, r3, #1 + 2143 0148 4B60 str r3, [r1, #4] +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2144 .loc 1 1267 5 view .LVU660 +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2145 .loc 1 1267 17 is_stmt 0 view .LVU661 + 2146 014a 84F84120 strb r2, [r4, #65] +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2147 .loc 1 1268 5 is_stmt 1 view .LVU662 +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2148 .loc 1 1268 17 is_stmt 0 view .LVU663 + 2149 014e 0023 movs r3, #0 + 2150 0150 84F84230 strb r3, [r4, #66] +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2151 .loc 1 1271 5 is_stmt 1 view .LVU664 +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2152 .loc 1 1271 5 view .LVU665 + 2153 0154 84F84030 strb r3, [r4, #64] +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2154 .loc 1 1271 5 view .LVU666 +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2155 .loc 1 1273 5 view .LVU667 +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2156 .loc 1 1273 12 is_stmt 0 view .LVU668 + 2157 0158 00E0 b .L153 + 2158 .LVL119: + 2159 .L160: +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2160 .loc 1 1277 12 view .LVU669 + 2161 015a 0220 movs r0, #2 + 2162 .LVL120: + 2163 .L153: +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2164 .loc 1 1279 1 view .LVU670 + 2165 015c 02B0 add sp, sp, #8 + 2166 .LCFI25: + 2167 .cfi_remember_state + 2168 .cfi_def_cfa_offset 32 + 2169 @ sp needed + 2170 015e BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 2171 .LVL121: + 2172 .L161: + 2173 .LCFI26: + 2174 .cfi_restore_state +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2175 .loc 1 1184 5 view .LVU671 + 2176 0162 0220 movs r0, #2 + 2177 .LVL122: + ARM GAS /tmp/ccEimIdZ.s page 165 + + +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2178 .loc 1 1184 5 view .LVU672 + 2179 0164 FAE7 b .L153 + 2180 .LVL123: + 2181 .L162: +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2182 .loc 1 1191 14 view .LVU673 + 2183 0166 0120 movs r0, #1 + 2184 0168 F8E7 b .L153 + 2185 .L163: +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2186 .loc 1 1221 16 view .LVU674 + 2187 016a 0120 movs r0, #1 + 2188 016c F6E7 b .L153 + 2189 .L164: +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2190 .loc 1 1238 18 view .LVU675 + 2191 016e 0120 movs r0, #1 + 2192 0170 F4E7 b .L153 + 2193 .L165: +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2194 .loc 1 1258 14 view .LVU676 + 2195 0172 0120 movs r0, #1 + 2196 0174 F2E7 b .L153 + 2197 .L169: + 2198 0176 00BF .align 2 + 2199 .L168: + 2200 0178 00240080 .word -2147474432 + 2201 .cfi_endproc + 2202 .LFE146: + 2204 .section .text.HAL_I2C_Slave_Transmit,"ax",%progbits + 2205 .align 1 + 2206 .global HAL_I2C_Slave_Transmit + 2207 .syntax unified + 2208 .thumb + 2209 .thumb_func + 2210 .fpu fpv5-d16 + 2212 HAL_I2C_Slave_Transmit: + 2213 .LVL124: + 2214 .LFB147: +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 2215 .loc 1 1291 1 is_stmt 1 view -0 + 2216 .cfi_startproc + 2217 @ args = 0, pretend = 0, frame = 0 + 2218 @ frame_needed = 0, uses_anonymous_args = 0 +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 2219 .loc 1 1291 1 is_stmt 0 view .LVU678 + 2220 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2221 .LCFI27: + 2222 .cfi_def_cfa_offset 24 + 2223 .cfi_offset 4, -24 + 2224 .cfi_offset 5, -20 + 2225 .cfi_offset 6, -16 + 2226 .cfi_offset 7, -12 + 2227 .cfi_offset 8, -8 + 2228 .cfi_offset 14, -4 + 2229 0004 82B0 sub sp, sp, #8 + ARM GAS /tmp/ccEimIdZ.s page 166 + + + 2230 .LCFI28: + 2231 .cfi_def_cfa_offset 32 + 2232 0006 1D46 mov r5, r3 +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2233 .loc 1 1292 3 is_stmt 1 view .LVU679 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2234 .loc 1 1294 3 view .LVU680 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2235 .loc 1 1294 11 is_stmt 0 view .LVU681 + 2236 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 2237 .LVL125: +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2238 .loc 1 1294 11 view .LVU682 + 2239 000c DBB2 uxtb r3, r3 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2240 .loc 1 1294 6 view .LVU683 + 2241 000e 202B cmp r3, #32 + 2242 0010 40F0B680 bne .L181 + 2243 0014 0446 mov r4, r0 + 2244 0016 0F46 mov r7, r1 + 2245 0018 9046 mov r8, r2 +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2246 .loc 1 1296 5 is_stmt 1 view .LVU684 +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2247 .loc 1 1296 8 is_stmt 0 view .LVU685 + 2248 001a 002A cmp r2, #0 + 2249 001c 18BF it ne + 2250 001e 0029 cmpne r1, #0 + 2251 0020 50D0 beq .L185 +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2252 .loc 1 1302 5 is_stmt 1 view .LVU686 +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2253 .loc 1 1302 5 view .LVU687 + 2254 0022 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 2255 0026 012B cmp r3, #1 + 2256 0028 00F0AE80 beq .L182 +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2257 .loc 1 1302 5 discriminator 2 view .LVU688 + 2258 002c 0123 movs r3, #1 + 2259 002e 80F84030 strb r3, [r0, #64] +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2260 .loc 1 1302 5 discriminator 2 view .LVU689 +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2261 .loc 1 1305 5 discriminator 2 view .LVU690 +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2262 .loc 1 1305 17 is_stmt 0 discriminator 2 view .LVU691 + 2263 0032 FFF7FEFF bl HAL_GetTick + 2264 .LVL126: +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2265 .loc 1 1305 17 discriminator 2 view .LVU692 + 2266 0036 0646 mov r6, r0 + 2267 .LVL127: +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2268 .loc 1 1307 5 is_stmt 1 discriminator 2 view .LVU693 +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2269 .loc 1 1307 21 is_stmt 0 discriminator 2 view .LVU694 + 2270 0038 2123 movs r3, #33 + ARM GAS /tmp/ccEimIdZ.s page 167 + + + 2271 003a 84F84130 strb r3, [r4, #65] +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2272 .loc 1 1308 5 is_stmt 1 discriminator 2 view .LVU695 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2273 .loc 1 1308 21 is_stmt 0 discriminator 2 view .LVU696 + 2274 003e 2023 movs r3, #32 + 2275 0040 84F84230 strb r3, [r4, #66] +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2276 .loc 1 1309 5 is_stmt 1 discriminator 2 view .LVU697 +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2277 .loc 1 1309 21 is_stmt 0 discriminator 2 view .LVU698 + 2278 0044 0022 movs r2, #0 + 2279 0046 6264 str r2, [r4, #68] +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2280 .loc 1 1312 5 is_stmt 1 discriminator 2 view .LVU699 +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2281 .loc 1 1312 21 is_stmt 0 discriminator 2 view .LVU700 + 2282 0048 6762 str r7, [r4, #36] +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2283 .loc 1 1313 5 is_stmt 1 discriminator 2 view .LVU701 +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2284 .loc 1 1313 21 is_stmt 0 discriminator 2 view .LVU702 + 2285 004a A4F82A80 strh r8, [r4, #42] @ movhi +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2286 .loc 1 1314 5 is_stmt 1 discriminator 2 view .LVU703 +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2287 .loc 1 1314 21 is_stmt 0 discriminator 2 view .LVU704 + 2288 004e 6263 str r2, [r4, #52] +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2289 .loc 1 1317 5 is_stmt 1 discriminator 2 view .LVU705 +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2290 .loc 1 1317 9 is_stmt 0 discriminator 2 view .LVU706 + 2291 0050 2168 ldr r1, [r4] +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2292 .loc 1 1317 25 discriminator 2 view .LVU707 + 2293 0052 4B68 ldr r3, [r1, #4] + 2294 0054 23F40043 bic r3, r3, #32768 + 2295 0058 4B60 str r3, [r1, #4] +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2296 .loc 1 1320 5 is_stmt 1 discriminator 2 view .LVU708 +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2297 .loc 1 1320 9 is_stmt 0 discriminator 2 view .LVU709 + 2298 005a 0090 str r0, [sp] + 2299 005c 2B46 mov r3, r5 + 2300 005e 0821 movs r1, #8 + 2301 0060 2046 mov r0, r4 + 2302 .LVL128: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2303 .loc 1 1320 9 discriminator 2 view .LVU710 + 2304 0062 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2305 .LVL129: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2306 .loc 1 1320 8 discriminator 2 view .LVU711 + 2307 0066 0028 cmp r0, #0 + 2308 0068 31D1 bne .L186 +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2309 .loc 1 1328 5 is_stmt 1 view .LVU712 + ARM GAS /tmp/ccEimIdZ.s page 168 + + + 2310 006a 2368 ldr r3, [r4] + 2311 006c 0822 movs r2, #8 + 2312 006e DA61 str r2, [r3, #28] +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2313 .loc 1 1331 5 view .LVU713 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2314 .loc 1 1331 19 is_stmt 0 view .LVU714 + 2315 0070 E368 ldr r3, [r4, #12] +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2316 .loc 1 1331 8 view .LVU715 + 2317 0072 022B cmp r3, #2 + 2318 0074 32D0 beq .L187 + 2319 .L174: +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2320 .loc 1 1346 5 is_stmt 1 view .LVU716 +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2321 .loc 1 1346 9 is_stmt 0 view .LVU717 + 2322 0076 0096 str r6, [sp] + 2323 0078 2B46 mov r3, r5 + 2324 007a 0022 movs r2, #0 + 2325 007c 4FF48031 mov r1, #65536 + 2326 0080 2046 mov r0, r4 + 2327 0082 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2328 .LVL130: +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2329 .loc 1 1346 8 view .LVU718 + 2330 0086 0028 cmp r0, #0 + 2331 0088 3BD1 bne .L188 + 2332 .L176: +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2333 .loc 1 1353 11 is_stmt 1 view .LVU719 +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2334 .loc 1 1353 16 is_stmt 0 view .LVU720 + 2335 008a 638D ldrh r3, [r4, #42] + 2336 008c 9BB2 uxth r3, r3 +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2337 .loc 1 1353 11 view .LVU721 + 2338 008e 002B cmp r3, #0 + 2339 0090 45D0 beq .L189 +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2340 .loc 1 1356 7 is_stmt 1 view .LVU722 +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2341 .loc 1 1356 11 is_stmt 0 view .LVU723 + 2342 0092 3246 mov r2, r6 + 2343 0094 2946 mov r1, r5 + 2344 0096 2046 mov r0, r4 + 2345 0098 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 2346 .LVL131: +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2347 .loc 1 1356 10 view .LVU724 + 2348 009c 0028 cmp r0, #0 + 2349 009e 37D1 bne .L190 +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2350 .loc 1 1364 7 is_stmt 1 view .LVU725 +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2351 .loc 1 1364 35 is_stmt 0 view .LVU726 + 2352 00a0 626A ldr r2, [r4, #36] + ARM GAS /tmp/ccEimIdZ.s page 169 + + +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2353 .loc 1 1364 11 view .LVU727 + 2354 00a2 2368 ldr r3, [r4] +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2355 .loc 1 1364 30 view .LVU728 + 2356 00a4 1278 ldrb r2, [r2] @ zero_extendqisi2 +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2357 .loc 1 1364 28 view .LVU729 + 2358 00a6 9A62 str r2, [r3, #40] +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2359 .loc 1 1367 7 is_stmt 1 view .LVU730 +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2360 .loc 1 1367 11 is_stmt 0 view .LVU731 + 2361 00a8 636A ldr r3, [r4, #36] +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2362 .loc 1 1367 21 view .LVU732 + 2363 00aa 0133 adds r3, r3, #1 + 2364 00ac 6362 str r3, [r4, #36] +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2365 .loc 1 1369 7 is_stmt 1 view .LVU733 +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2366 .loc 1 1369 11 is_stmt 0 view .LVU734 + 2367 00ae B4F82AC0 ldrh ip, [r4, #42] + 2368 00b2 1FFA8CFC uxth ip, ip +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2369 .loc 1 1369 22 view .LVU735 + 2370 00b6 0CF1FF3C add ip, ip, #-1 + 2371 00ba 1FFA8CFC uxth ip, ip + 2372 00be A4F82AC0 strh ip, [r4, #42] @ movhi + 2373 00c2 E2E7 b .L176 + 2374 .LVL132: + 2375 .L185: +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2376 .loc 1 1298 7 is_stmt 1 view .LVU736 +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2377 .loc 1 1298 23 is_stmt 0 view .LVU737 + 2378 00c4 4FF40073 mov r3, #512 + 2379 00c8 4364 str r3, [r0, #68] +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2380 .loc 1 1299 7 is_stmt 1 view .LVU738 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2381 .loc 1 1299 15 is_stmt 0 view .LVU739 + 2382 00ca 0120 movs r0, #1 + 2383 .LVL133: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2384 .loc 1 1299 15 view .LVU740 + 2385 00cc 59E0 b .L171 + 2386 .LVL134: + 2387 .L186: +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2388 .loc 1 1323 7 is_stmt 1 view .LVU741 +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2389 .loc 1 1323 11 is_stmt 0 view .LVU742 + 2390 00ce 2268 ldr r2, [r4] +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2391 .loc 1 1323 27 view .LVU743 + 2392 00d0 5368 ldr r3, [r2, #4] + ARM GAS /tmp/ccEimIdZ.s page 170 + + + 2393 00d2 43F40043 orr r3, r3, #32768 + 2394 00d6 5360 str r3, [r2, #4] +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2395 .loc 1 1324 7 is_stmt 1 view .LVU744 +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2396 .loc 1 1324 14 is_stmt 0 view .LVU745 + 2397 00d8 0120 movs r0, #1 + 2398 00da 52E0 b .L171 + 2399 .L187: +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2400 .loc 1 1334 7 is_stmt 1 view .LVU746 +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2401 .loc 1 1334 11 is_stmt 0 view .LVU747 + 2402 00dc 0096 str r6, [sp] + 2403 00de 2B46 mov r3, r5 + 2404 00e0 0022 movs r2, #0 + 2405 00e2 0821 movs r1, #8 + 2406 00e4 2046 mov r0, r4 + 2407 00e6 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2408 .LVL135: +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2409 .loc 1 1334 10 view .LVU748 + 2410 00ea 18B9 cbnz r0, .L191 +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2411 .loc 1 1342 7 is_stmt 1 view .LVU749 + 2412 00ec 2368 ldr r3, [r4] + 2413 00ee 0822 movs r2, #8 + 2414 00f0 DA61 str r2, [r3, #28] + 2415 00f2 C0E7 b .L174 + 2416 .L191: +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2417 .loc 1 1337 9 view .LVU750 +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2418 .loc 1 1337 13 is_stmt 0 view .LVU751 + 2419 00f4 2268 ldr r2, [r4] +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2420 .loc 1 1337 29 view .LVU752 + 2421 00f6 5368 ldr r3, [r2, #4] + 2422 00f8 43F40043 orr r3, r3, #32768 + 2423 00fc 5360 str r3, [r2, #4] +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2424 .loc 1 1338 9 is_stmt 1 view .LVU753 +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2425 .loc 1 1338 16 is_stmt 0 view .LVU754 + 2426 00fe 0120 movs r0, #1 + 2427 0100 3FE0 b .L171 + 2428 .L188: +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2429 .loc 1 1349 7 is_stmt 1 view .LVU755 +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2430 .loc 1 1349 11 is_stmt 0 view .LVU756 + 2431 0102 2268 ldr r2, [r4] +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2432 .loc 1 1349 27 view .LVU757 + 2433 0104 5368 ldr r3, [r2, #4] + 2434 0106 43F40043 orr r3, r3, #32768 + 2435 010a 5360 str r3, [r2, #4] + ARM GAS /tmp/ccEimIdZ.s page 171 + + +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2436 .loc 1 1350 7 is_stmt 1 view .LVU758 +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2437 .loc 1 1350 14 is_stmt 0 view .LVU759 + 2438 010c 0120 movs r0, #1 + 2439 010e 38E0 b .L171 + 2440 .L190: +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2441 .loc 1 1359 9 is_stmt 1 view .LVU760 +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2442 .loc 1 1359 13 is_stmt 0 view .LVU761 + 2443 0110 2268 ldr r2, [r4] +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2444 .loc 1 1359 29 view .LVU762 + 2445 0112 5368 ldr r3, [r2, #4] + 2446 0114 43F40043 orr r3, r3, #32768 + 2447 0118 5360 str r3, [r2, #4] +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2448 .loc 1 1360 9 is_stmt 1 view .LVU763 +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2449 .loc 1 1360 16 is_stmt 0 view .LVU764 + 2450 011a 0120 movs r0, #1 + 2451 011c 31E0 b .L171 + 2452 .L189: +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2453 .loc 1 1373 5 is_stmt 1 view .LVU765 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2454 .loc 1 1373 9 is_stmt 0 view .LVU766 + 2455 011e 3246 mov r2, r6 + 2456 0120 2946 mov r1, r5 + 2457 0122 2046 mov r0, r4 + 2458 0124 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2459 .LVL136: +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2460 .loc 1 1373 8 view .LVU767 + 2461 0128 48B1 cbz r0, .L179 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2462 .loc 1 1376 7 is_stmt 1 view .LVU768 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2463 .loc 1 1376 11 is_stmt 0 view .LVU769 + 2464 012a 2268 ldr r2, [r4] +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2465 .loc 1 1376 27 view .LVU770 + 2466 012c 5368 ldr r3, [r2, #4] + 2467 012e 43F40043 orr r3, r3, #32768 + 2468 0132 5360 str r3, [r2, #4] +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2469 .loc 1 1378 7 is_stmt 1 view .LVU771 +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2470 .loc 1 1378 15 is_stmt 0 view .LVU772 + 2471 0134 636C ldr r3, [r4, #68] +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2472 .loc 1 1378 10 view .LVU773 + 2473 0136 042B cmp r3, #4 + 2474 0138 28D1 bne .L183 +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2475 .loc 1 1382 9 is_stmt 1 view .LVU774 + ARM GAS /tmp/ccEimIdZ.s page 172 + + +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2476 .loc 1 1382 25 is_stmt 0 view .LVU775 + 2477 013a 0023 movs r3, #0 + 2478 013c 6364 str r3, [r4, #68] + 2479 .L179: +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2480 .loc 1 1391 5 is_stmt 1 view .LVU776 + 2481 013e 2368 ldr r3, [r4] + 2482 0140 2022 movs r2, #32 + 2483 0142 DA61 str r2, [r3, #28] +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2484 .loc 1 1394 5 view .LVU777 +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2485 .loc 1 1394 9 is_stmt 0 view .LVU778 + 2486 0144 0096 str r6, [sp] + 2487 0146 2B46 mov r3, r5 + 2488 0148 0122 movs r2, #1 + 2489 014a 4FF40041 mov r1, #32768 + 2490 014e 2046 mov r0, r4 + 2491 0150 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2492 .LVL137: +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2493 .loc 1 1394 8 view .LVU779 + 2494 0154 30B1 cbz r0, .L180 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2495 .loc 1 1397 7 is_stmt 1 view .LVU780 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2496 .loc 1 1397 11 is_stmt 0 view .LVU781 + 2497 0156 2268 ldr r2, [r4] +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2498 .loc 1 1397 27 view .LVU782 + 2499 0158 5368 ldr r3, [r2, #4] + 2500 015a 43F40043 orr r3, r3, #32768 + 2501 015e 5360 str r3, [r2, #4] +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2502 .loc 1 1398 7 is_stmt 1 view .LVU783 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2503 .loc 1 1398 14 is_stmt 0 view .LVU784 + 2504 0160 0120 movs r0, #1 + 2505 0162 0EE0 b .L171 + 2506 .L180: +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2507 .loc 1 1402 5 is_stmt 1 view .LVU785 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2508 .loc 1 1402 9 is_stmt 0 view .LVU786 + 2509 0164 2268 ldr r2, [r4] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2510 .loc 1 1402 25 view .LVU787 + 2511 0166 5368 ldr r3, [r2, #4] + 2512 0168 43F40043 orr r3, r3, #32768 + 2513 016c 5360 str r3, [r2, #4] +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2514 .loc 1 1404 5 is_stmt 1 view .LVU788 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2515 .loc 1 1404 17 is_stmt 0 view .LVU789 + 2516 016e 2023 movs r3, #32 + 2517 0170 84F84130 strb r3, [r4, #65] + ARM GAS /tmp/ccEimIdZ.s page 173 + + +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2518 .loc 1 1405 5 is_stmt 1 view .LVU790 +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2519 .loc 1 1405 17 is_stmt 0 view .LVU791 + 2520 0174 0023 movs r3, #0 + 2521 0176 84F84230 strb r3, [r4, #66] +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2522 .loc 1 1408 5 is_stmt 1 view .LVU792 +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2523 .loc 1 1408 5 view .LVU793 + 2524 017a 84F84030 strb r3, [r4, #64] +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2525 .loc 1 1408 5 view .LVU794 +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2526 .loc 1 1410 5 view .LVU795 +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2527 .loc 1 1410 12 is_stmt 0 view .LVU796 + 2528 017e 00E0 b .L171 + 2529 .LVL138: + 2530 .L181: +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2531 .loc 1 1414 12 view .LVU797 + 2532 0180 0220 movs r0, #2 + 2533 .LVL139: + 2534 .L171: +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2535 .loc 1 1416 1 view .LVU798 + 2536 0182 02B0 add sp, sp, #8 + 2537 .LCFI29: + 2538 .cfi_remember_state + 2539 .cfi_def_cfa_offset 24 + 2540 @ sp needed + 2541 0184 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2542 .LVL140: + 2543 .L182: + 2544 .LCFI30: + 2545 .cfi_restore_state +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2546 .loc 1 1302 5 view .LVU799 + 2547 0188 0220 movs r0, #2 + 2548 .LVL141: +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2549 .loc 1 1302 5 view .LVU800 + 2550 018a FAE7 b .L171 + 2551 .LVL142: + 2552 .L183: +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2553 .loc 1 1386 16 view .LVU801 + 2554 018c 0120 movs r0, #1 + 2555 018e F8E7 b .L171 + 2556 .cfi_endproc + 2557 .LFE147: + 2559 .section .text.HAL_I2C_Slave_Receive,"ax",%progbits + 2560 .align 1 + 2561 .global HAL_I2C_Slave_Receive + 2562 .syntax unified + 2563 .thumb + ARM GAS /tmp/ccEimIdZ.s page 174 + + + 2564 .thumb_func + 2565 .fpu fpv5-d16 + 2567 HAL_I2C_Slave_Receive: + 2568 .LVL143: + 2569 .LFB148: +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 2570 .loc 1 1428 1 is_stmt 1 view -0 + 2571 .cfi_startproc + 2572 @ args = 0, pretend = 0, frame = 0 + 2573 @ frame_needed = 0, uses_anonymous_args = 0 +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 2574 .loc 1 1428 1 is_stmt 0 view .LVU803 + 2575 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2576 .LCFI31: + 2577 .cfi_def_cfa_offset 24 + 2578 .cfi_offset 4, -24 + 2579 .cfi_offset 5, -20 + 2580 .cfi_offset 6, -16 + 2581 .cfi_offset 7, -12 + 2582 .cfi_offset 8, -8 + 2583 .cfi_offset 14, -4 + 2584 0004 82B0 sub sp, sp, #8 + 2585 .LCFI32: + 2586 .cfi_def_cfa_offset 32 + 2587 0006 1D46 mov r5, r3 +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2588 .loc 1 1429 3 is_stmt 1 view .LVU804 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2589 .loc 1 1431 3 view .LVU805 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2590 .loc 1 1431 11 is_stmt 0 view .LVU806 + 2591 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 2592 .LVL144: +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2593 .loc 1 1431 11 view .LVU807 + 2594 000c DBB2 uxtb r3, r3 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2595 .loc 1 1431 6 view .LVU808 + 2596 000e 202B cmp r3, #32 + 2597 0010 40F0AA80 bne .L202 + 2598 0014 0446 mov r4, r0 + 2599 0016 0F46 mov r7, r1 + 2600 0018 9046 mov r8, r2 +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2601 .loc 1 1433 5 is_stmt 1 view .LVU809 +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2602 .loc 1 1433 8 is_stmt 0 view .LVU810 + 2603 001a 002A cmp r2, #0 + 2604 001c 18BF it ne + 2605 001e 0029 cmpne r1, #0 + 2606 0020 29D0 beq .L205 +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2607 .loc 1 1439 5 is_stmt 1 view .LVU811 +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2608 .loc 1 1439 5 view .LVU812 + 2609 0022 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 2610 0026 012B cmp r3, #1 + ARM GAS /tmp/ccEimIdZ.s page 175 + + + 2611 0028 00F0A280 beq .L203 +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2612 .loc 1 1439 5 discriminator 2 view .LVU813 + 2613 002c 0123 movs r3, #1 + 2614 002e 80F84030 strb r3, [r0, #64] +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2615 .loc 1 1439 5 discriminator 2 view .LVU814 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2616 .loc 1 1442 5 discriminator 2 view .LVU815 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2617 .loc 1 1442 17 is_stmt 0 discriminator 2 view .LVU816 + 2618 0032 FFF7FEFF bl HAL_GetTick + 2619 .LVL145: +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2620 .loc 1 1442 17 discriminator 2 view .LVU817 + 2621 0036 0646 mov r6, r0 + 2622 .LVL146: +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2623 .loc 1 1444 5 is_stmt 1 discriminator 2 view .LVU818 +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2624 .loc 1 1444 21 is_stmt 0 discriminator 2 view .LVU819 + 2625 0038 2223 movs r3, #34 + 2626 003a 84F84130 strb r3, [r4, #65] +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2627 .loc 1 1445 5 is_stmt 1 discriminator 2 view .LVU820 +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2628 .loc 1 1445 21 is_stmt 0 discriminator 2 view .LVU821 + 2629 003e 2023 movs r3, #32 + 2630 0040 84F84230 strb r3, [r4, #66] +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2631 .loc 1 1446 5 is_stmt 1 discriminator 2 view .LVU822 +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2632 .loc 1 1446 21 is_stmt 0 discriminator 2 view .LVU823 + 2633 0044 0022 movs r2, #0 + 2634 0046 6264 str r2, [r4, #68] +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2635 .loc 1 1449 5 is_stmt 1 discriminator 2 view .LVU824 +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2636 .loc 1 1449 21 is_stmt 0 discriminator 2 view .LVU825 + 2637 0048 6762 str r7, [r4, #36] +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2638 .loc 1 1450 5 is_stmt 1 discriminator 2 view .LVU826 +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2639 .loc 1 1450 21 is_stmt 0 discriminator 2 view .LVU827 + 2640 004a A4F82A80 strh r8, [r4, #42] @ movhi +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2641 .loc 1 1451 5 is_stmt 1 discriminator 2 view .LVU828 +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2642 .loc 1 1451 21 is_stmt 0 discriminator 2 view .LVU829 + 2643 004e 6263 str r2, [r4, #52] +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2644 .loc 1 1454 5 is_stmt 1 discriminator 2 view .LVU830 +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2645 .loc 1 1454 9 is_stmt 0 discriminator 2 view .LVU831 + 2646 0050 2168 ldr r1, [r4] +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2647 .loc 1 1454 25 discriminator 2 view .LVU832 + ARM GAS /tmp/ccEimIdZ.s page 176 + + + 2648 0052 4B68 ldr r3, [r1, #4] + 2649 0054 23F40043 bic r3, r3, #32768 + 2650 0058 4B60 str r3, [r1, #4] +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2651 .loc 1 1457 5 is_stmt 1 discriminator 2 view .LVU833 +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2652 .loc 1 1457 9 is_stmt 0 discriminator 2 view .LVU834 + 2653 005a 0090 str r0, [sp] + 2654 005c 2B46 mov r3, r5 + 2655 005e 0821 movs r1, #8 + 2656 0060 2046 mov r0, r4 + 2657 .LVL147: +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2658 .loc 1 1457 9 discriminator 2 view .LVU835 + 2659 0062 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2660 .LVL148: +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2661 .loc 1 1457 8 discriminator 2 view .LVU836 + 2662 0066 58B1 cbz r0, .L195 +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2663 .loc 1 1460 7 is_stmt 1 view .LVU837 +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2664 .loc 1 1460 11 is_stmt 0 view .LVU838 + 2665 0068 2268 ldr r2, [r4] +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2666 .loc 1 1460 27 view .LVU839 + 2667 006a 5368 ldr r3, [r2, #4] + 2668 006c 43F40043 orr r3, r3, #32768 + 2669 0070 5360 str r3, [r2, #4] +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2670 .loc 1 1461 7 is_stmt 1 view .LVU840 +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2671 .loc 1 1461 14 is_stmt 0 view .LVU841 + 2672 0072 0120 movs r0, #1 + 2673 0074 79E0 b .L193 + 2674 .LVL149: + 2675 .L205: +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2676 .loc 1 1435 7 is_stmt 1 view .LVU842 +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2677 .loc 1 1435 23 is_stmt 0 view .LVU843 + 2678 0076 4FF40073 mov r3, #512 + 2679 007a 4364 str r3, [r0, #68] +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2680 .loc 1 1436 7 is_stmt 1 view .LVU844 +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2681 .loc 1 1436 15 is_stmt 0 view .LVU845 + 2682 007c 0120 movs r0, #1 + 2683 .LVL150: +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2684 .loc 1 1436 15 view .LVU846 + 2685 007e 74E0 b .L193 + 2686 .LVL151: + 2687 .L195: +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2688 .loc 1 1465 5 is_stmt 1 view .LVU847 + 2689 0080 2368 ldr r3, [r4] + ARM GAS /tmp/ccEimIdZ.s page 177 + + + 2690 0082 0822 movs r2, #8 + 2691 0084 DA61 str r2, [r3, #28] +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2692 .loc 1 1468 5 view .LVU848 +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2693 .loc 1 1468 9 is_stmt 0 view .LVU849 + 2694 0086 0096 str r6, [sp] + 2695 0088 2B46 mov r3, r5 + 2696 008a 0122 movs r2, #1 + 2697 008c 4FF48031 mov r1, #65536 + 2698 0090 2046 mov r0, r4 + 2699 0092 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2700 .LVL152: +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2701 .loc 1 1468 8 view .LVU850 + 2702 0096 D8B9 cbnz r0, .L206 + 2703 .L196: +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2704 .loc 1 1475 11 is_stmt 1 view .LVU851 +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2705 .loc 1 1475 16 is_stmt 0 view .LVU852 + 2706 0098 638D ldrh r3, [r4, #42] + 2707 009a 9BB2 uxth r3, r3 +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2708 .loc 1 1475 11 view .LVU853 + 2709 009c 002B cmp r3, #0 + 2710 009e 35D0 beq .L207 +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2711 .loc 1 1478 7 is_stmt 1 view .LVU854 +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2712 .loc 1 1478 11 is_stmt 0 view .LVU855 + 2713 00a0 3246 mov r2, r6 + 2714 00a2 2946 mov r1, r5 + 2715 00a4 2046 mov r0, r4 + 2716 00a6 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2717 .LVL153: +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2718 .loc 1 1478 10 view .LVU856 + 2719 00aa C0B9 cbnz r0, .L208 +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2720 .loc 1 1499 7 is_stmt 1 view .LVU857 +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2721 .loc 1 1499 38 is_stmt 0 view .LVU858 + 2722 00ac 2368 ldr r3, [r4] +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2723 .loc 1 1499 48 view .LVU859 + 2724 00ae 5A6A ldr r2, [r3, #36] +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2725 .loc 1 1499 12 view .LVU860 + 2726 00b0 636A ldr r3, [r4, #36] +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2727 .loc 1 1499 23 view .LVU861 + 2728 00b2 1A70 strb r2, [r3] +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2729 .loc 1 1502 7 is_stmt 1 view .LVU862 +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2730 .loc 1 1502 11 is_stmt 0 view .LVU863 + ARM GAS /tmp/ccEimIdZ.s page 178 + + + 2731 00b4 636A ldr r3, [r4, #36] +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2732 .loc 1 1502 21 view .LVU864 + 2733 00b6 0133 adds r3, r3, #1 + 2734 00b8 6362 str r3, [r4, #36] +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2735 .loc 1 1504 7 is_stmt 1 view .LVU865 +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2736 .loc 1 1504 11 is_stmt 0 view .LVU866 + 2737 00ba B4F82AC0 ldrh ip, [r4, #42] + 2738 00be 1FFA8CFC uxth ip, ip +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2739 .loc 1 1504 22 view .LVU867 + 2740 00c2 0CF1FF3C add ip, ip, #-1 + 2741 00c6 1FFA8CFC uxth ip, ip + 2742 00ca A4F82AC0 strh ip, [r4, #42] @ movhi + 2743 00ce E3E7 b .L196 + 2744 .L206: +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2745 .loc 1 1471 7 is_stmt 1 view .LVU868 +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2746 .loc 1 1471 11 is_stmt 0 view .LVU869 + 2747 00d0 2268 ldr r2, [r4] +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2748 .loc 1 1471 27 view .LVU870 + 2749 00d2 5368 ldr r3, [r2, #4] + 2750 00d4 43F40043 orr r3, r3, #32768 + 2751 00d8 5360 str r3, [r2, #4] +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2752 .loc 1 1472 7 is_stmt 1 view .LVU871 +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2753 .loc 1 1472 14 is_stmt 0 view .LVU872 + 2754 00da 0120 movs r0, #1 + 2755 00dc 45E0 b .L193 + 2756 .L208: +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2757 .loc 1 1481 9 is_stmt 1 view .LVU873 +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2758 .loc 1 1481 13 is_stmt 0 view .LVU874 + 2759 00de 2268 ldr r2, [r4] +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2760 .loc 1 1481 29 view .LVU875 + 2761 00e0 5368 ldr r3, [r2, #4] + 2762 00e2 43F40043 orr r3, r3, #32768 + 2763 00e6 5360 str r3, [r2, #4] +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2764 .loc 1 1484 9 is_stmt 1 view .LVU876 +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2765 .loc 1 1484 13 is_stmt 0 view .LVU877 + 2766 00e8 2368 ldr r3, [r4] + 2767 00ea 9A69 ldr r2, [r3, #24] +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2768 .loc 1 1484 12 view .LVU878 + 2769 00ec 12F0040F tst r2, #4 + 2770 00f0 0AD0 beq .L198 +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2771 .loc 1 1487 11 is_stmt 1 view .LVU879 + ARM GAS /tmp/ccEimIdZ.s page 179 + + +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2772 .loc 1 1487 52 is_stmt 0 view .LVU880 + 2773 00f2 5A6A ldr r2, [r3, #36] +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2774 .loc 1 1487 16 view .LVU881 + 2775 00f4 636A ldr r3, [r4, #36] +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2776 .loc 1 1487 27 view .LVU882 + 2777 00f6 1A70 strb r2, [r3] +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2778 .loc 1 1490 11 is_stmt 1 view .LVU883 +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2779 .loc 1 1490 15 is_stmt 0 view .LVU884 + 2780 00f8 636A ldr r3, [r4, #36] +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2781 .loc 1 1490 25 view .LVU885 + 2782 00fa 0133 adds r3, r3, #1 + 2783 00fc 6362 str r3, [r4, #36] +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2784 .loc 1 1492 11 is_stmt 1 view .LVU886 +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2785 .loc 1 1492 15 is_stmt 0 view .LVU887 + 2786 00fe 638D ldrh r3, [r4, #42] + 2787 0100 9BB2 uxth r3, r3 +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2788 .loc 1 1492 26 view .LVU888 + 2789 0102 013B subs r3, r3, #1 + 2790 0104 9BB2 uxth r3, r3 + 2791 0106 6385 strh r3, [r4, #42] @ movhi + 2792 .L198: +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2793 .loc 1 1495 9 is_stmt 1 view .LVU889 +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2794 .loc 1 1495 16 is_stmt 0 view .LVU890 + 2795 0108 0120 movs r0, #1 + 2796 010a 2EE0 b .L193 + 2797 .L207: +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2798 .loc 1 1508 5 is_stmt 1 view .LVU891 +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2799 .loc 1 1508 9 is_stmt 0 view .LVU892 + 2800 010c 3246 mov r2, r6 + 2801 010e 2946 mov r1, r5 + 2802 0110 2046 mov r0, r4 + 2803 0112 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2804 .LVL154: +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2805 .loc 1 1508 8 view .LVU893 + 2806 0116 30B1 cbz r0, .L200 +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2807 .loc 1 1511 7 is_stmt 1 view .LVU894 +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2808 .loc 1 1511 11 is_stmt 0 view .LVU895 + 2809 0118 2268 ldr r2, [r4] +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2810 .loc 1 1511 27 view .LVU896 + 2811 011a 5368 ldr r3, [r2, #4] + ARM GAS /tmp/ccEimIdZ.s page 180 + + + 2812 011c 43F40043 orr r3, r3, #32768 + 2813 0120 5360 str r3, [r2, #4] +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2814 .loc 1 1512 7 is_stmt 1 view .LVU897 +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2815 .loc 1 1512 14 is_stmt 0 view .LVU898 + 2816 0122 0120 movs r0, #1 + 2817 0124 21E0 b .L193 + 2818 .L200: +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2819 .loc 1 1516 5 is_stmt 1 view .LVU899 + 2820 0126 2368 ldr r3, [r4] + 2821 0128 2022 movs r2, #32 + 2822 012a DA61 str r2, [r3, #28] +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2823 .loc 1 1519 5 view .LVU900 +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2824 .loc 1 1519 9 is_stmt 0 view .LVU901 + 2825 012c 0096 str r6, [sp] + 2826 012e 2B46 mov r3, r5 + 2827 0130 0122 movs r2, #1 + 2828 0132 4FF40041 mov r1, #32768 + 2829 0136 2046 mov r0, r4 + 2830 0138 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2831 .LVL155: +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2832 .loc 1 1519 8 view .LVU902 + 2833 013c 30B1 cbz r0, .L201 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2834 .loc 1 1522 7 is_stmt 1 view .LVU903 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2835 .loc 1 1522 11 is_stmt 0 view .LVU904 + 2836 013e 2268 ldr r2, [r4] +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 2837 .loc 1 1522 27 view .LVU905 + 2838 0140 5368 ldr r3, [r2, #4] + 2839 0142 43F40043 orr r3, r3, #32768 + 2840 0146 5360 str r3, [r2, #4] +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2841 .loc 1 1523 7 is_stmt 1 view .LVU906 +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2842 .loc 1 1523 14 is_stmt 0 view .LVU907 + 2843 0148 0120 movs r0, #1 + 2844 014a 0EE0 b .L193 + 2845 .L201: +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2846 .loc 1 1527 5 is_stmt 1 view .LVU908 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2847 .loc 1 1527 9 is_stmt 0 view .LVU909 + 2848 014c 2268 ldr r2, [r4] +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2849 .loc 1 1527 25 view .LVU910 + 2850 014e 5368 ldr r3, [r2, #4] + 2851 0150 43F40043 orr r3, r3, #32768 + 2852 0154 5360 str r3, [r2, #4] +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2853 .loc 1 1529 5 is_stmt 1 view .LVU911 + ARM GAS /tmp/ccEimIdZ.s page 181 + + +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2854 .loc 1 1529 17 is_stmt 0 view .LVU912 + 2855 0156 2023 movs r3, #32 + 2856 0158 84F84130 strb r3, [r4, #65] +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2857 .loc 1 1530 5 is_stmt 1 view .LVU913 +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2858 .loc 1 1530 17 is_stmt 0 view .LVU914 + 2859 015c 0023 movs r3, #0 + 2860 015e 84F84230 strb r3, [r4, #66] +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2861 .loc 1 1533 5 is_stmt 1 view .LVU915 +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2862 .loc 1 1533 5 view .LVU916 + 2863 0162 84F84030 strb r3, [r4, #64] +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2864 .loc 1 1533 5 view .LVU917 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2865 .loc 1 1535 5 view .LVU918 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2866 .loc 1 1535 12 is_stmt 0 view .LVU919 + 2867 0166 00E0 b .L193 + 2868 .LVL156: + 2869 .L202: +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2870 .loc 1 1539 12 view .LVU920 + 2871 0168 0220 movs r0, #2 + 2872 .LVL157: + 2873 .L193: +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2874 .loc 1 1541 1 view .LVU921 + 2875 016a 02B0 add sp, sp, #8 + 2876 .LCFI33: + 2877 .cfi_remember_state + 2878 .cfi_def_cfa_offset 24 + 2879 @ sp needed + 2880 016c BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2881 .LVL158: + 2882 .L203: + 2883 .LCFI34: + 2884 .cfi_restore_state +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2885 .loc 1 1439 5 view .LVU922 + 2886 0170 0220 movs r0, #2 + 2887 .LVL159: +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2888 .loc 1 1439 5 view .LVU923 + 2889 0172 FAE7 b .L193 + 2890 .cfi_endproc + 2891 .LFE148: + 2893 .section .text.HAL_I2C_Master_Transmit_IT,"ax",%progbits + 2894 .align 1 + 2895 .global HAL_I2C_Master_Transmit_IT + 2896 .syntax unified + 2897 .thumb + 2898 .thumb_func + 2899 .fpu fpv5-d16 + ARM GAS /tmp/ccEimIdZ.s page 182 + + + 2901 HAL_I2C_Master_Transmit_IT: + 2902 .LVL160: + 2903 .LFB149: +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 2904 .loc 1 1554 1 is_stmt 1 view -0 + 2905 .cfi_startproc + 2906 @ args = 0, pretend = 0, frame = 0 + 2907 @ frame_needed = 0, uses_anonymous_args = 0 +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 2908 .loc 1 1554 1 is_stmt 0 view .LVU925 + 2909 0000 30B5 push {r4, r5, lr} + 2910 .LCFI35: + 2911 .cfi_def_cfa_offset 12 + 2912 .cfi_offset 4, -12 + 2913 .cfi_offset 5, -8 + 2914 .cfi_offset 14, -4 + 2915 0002 83B0 sub sp, sp, #12 + 2916 .LCFI36: + 2917 .cfi_def_cfa_offset 24 + 2918 0004 0446 mov r4, r0 +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2919 .loc 1 1555 3 is_stmt 1 view .LVU926 +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2920 .loc 1 1557 3 view .LVU927 +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2921 .loc 1 1557 11 is_stmt 0 view .LVU928 + 2922 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 2923 .LVL161: +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2924 .loc 1 1557 11 view .LVU929 + 2925 000a C0B2 uxtb r0, r0 +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2926 .loc 1 1557 6 view .LVU930 + 2927 000c 2028 cmp r0, #32 + 2928 000e 37D1 bne .L213 +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2929 .loc 1 1559 5 is_stmt 1 view .LVU931 +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2930 .loc 1 1559 9 is_stmt 0 view .LVU932 + 2931 0010 2068 ldr r0, [r4] + 2932 0012 8069 ldr r0, [r0, #24] +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2933 .loc 1 1559 8 view .LVU933 + 2934 0014 10F4004F tst r0, #32768 + 2935 0018 34D1 bne .L214 +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2936 .loc 1 1565 5 is_stmt 1 view .LVU934 +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2937 .loc 1 1565 5 view .LVU935 + 2938 001a 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 2939 001e 0128 cmp r0, #1 + 2940 0020 32D0 beq .L215 +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2941 .loc 1 1565 5 discriminator 2 view .LVU936 + 2942 0022 0120 movs r0, #1 + 2943 0024 84F84000 strb r0, [r4, #64] +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 183 + + + 2944 .loc 1 1565 5 discriminator 2 view .LVU937 +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2945 .loc 1 1567 5 discriminator 2 view .LVU938 +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2946 .loc 1 1567 23 is_stmt 0 discriminator 2 view .LVU939 + 2947 0028 2120 movs r0, #33 + 2948 002a 84F84100 strb r0, [r4, #65] +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2949 .loc 1 1568 5 is_stmt 1 discriminator 2 view .LVU940 +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2950 .loc 1 1568 23 is_stmt 0 discriminator 2 view .LVU941 + 2951 002e 1020 movs r0, #16 + 2952 0030 84F84200 strb r0, [r4, #66] +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2953 .loc 1 1569 5 is_stmt 1 discriminator 2 view .LVU942 +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2954 .loc 1 1569 23 is_stmt 0 discriminator 2 view .LVU943 + 2955 0034 0020 movs r0, #0 + 2956 0036 6064 str r0, [r4, #68] +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2957 .loc 1 1572 5 is_stmt 1 discriminator 2 view .LVU944 +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2958 .loc 1 1572 23 is_stmt 0 discriminator 2 view .LVU945 + 2959 0038 6262 str r2, [r4, #36] +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2960 .loc 1 1573 5 is_stmt 1 discriminator 2 view .LVU946 +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2961 .loc 1 1573 23 is_stmt 0 discriminator 2 view .LVU947 + 2962 003a 6385 strh r3, [r4, #42] @ movhi +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2963 .loc 1 1574 5 is_stmt 1 discriminator 2 view .LVU948 +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2964 .loc 1 1574 23 is_stmt 0 discriminator 2 view .LVU949 + 2965 003c 134B ldr r3, .L217 + 2966 .LVL162: +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2967 .loc 1 1574 23 discriminator 2 view .LVU950 + 2968 003e E362 str r3, [r4, #44] + 2969 .LVL163: +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2970 .loc 1 1575 5 is_stmt 1 discriminator 2 view .LVU951 +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2971 .loc 1 1575 23 is_stmt 0 discriminator 2 view .LVU952 + 2972 0040 134B ldr r3, .L217+4 + 2973 0042 6363 str r3, [r4, #52] +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2974 .loc 1 1577 5 is_stmt 1 discriminator 2 view .LVU953 +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2975 .loc 1 1577 13 is_stmt 0 discriminator 2 view .LVU954 + 2976 0044 638D ldrh r3, [r4, #42] + 2977 0046 9BB2 uxth r3, r3 +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 2978 .loc 1 1577 8 discriminator 2 view .LVU955 + 2979 0048 FF2B cmp r3, #255 + 2980 004a 14D9 bls .L211 +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2981 .loc 1 1579 7 is_stmt 1 view .LVU956 + ARM GAS /tmp/ccEimIdZ.s page 184 + + +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2982 .loc 1 1579 22 is_stmt 0 view .LVU957 + 2983 004c FF23 movs r3, #255 + 2984 004e 2385 strh r3, [r4, #40] @ movhi +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2985 .loc 1 1580 7 is_stmt 1 view .LVU958 + 2986 .LVL164: +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 2987 .loc 1 1580 16 is_stmt 0 view .LVU959 + 2988 0050 4FF08073 mov r3, #16777216 + 2989 .LVL165: + 2990 .L212: +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2991 .loc 1 1590 5 is_stmt 1 view .LVU960 + 2992 0054 0F4A ldr r2, .L217+8 + 2993 .LVL166: +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2994 .loc 1 1590 5 is_stmt 0 view .LVU961 + 2995 0056 0092 str r2, [sp] + 2996 .LVL167: +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 2997 .loc 1 1590 5 view .LVU962 + 2998 0058 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 2999 005c 2046 mov r0, r4 + 3000 005e FFF7FEFF bl I2C_TransferConfig + 3001 .LVL168: +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3002 .loc 1 1593 5 is_stmt 1 view .LVU963 +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3003 .loc 1 1593 5 view .LVU964 + 3004 0062 0025 movs r5, #0 + 3005 0064 84F84050 strb r5, [r4, #64] +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3006 .loc 1 1593 5 view .LVU965 +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3007 .loc 1 1602 5 view .LVU966 + 3008 0068 0121 movs r1, #1 + 3009 006a 2046 mov r0, r4 + 3010 006c FFF7FEFF bl I2C_Enable_IRQ + 3011 .LVL169: +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3012 .loc 1 1604 5 view .LVU967 +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3013 .loc 1 1604 12 is_stmt 0 view .LVU968 + 3014 0070 2846 mov r0, r5 + 3015 .L210: +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3016 .loc 1 1610 1 view .LVU969 + 3017 0072 03B0 add sp, sp, #12 + 3018 .LCFI37: + 3019 .cfi_remember_state + 3020 .cfi_def_cfa_offset 12 + 3021 @ sp needed + 3022 0074 30BD pop {r4, r5, pc} + 3023 .LVL170: + 3024 .L211: + 3025 .LCFI38: + ARM GAS /tmp/ccEimIdZ.s page 185 + + + 3026 .cfi_restore_state +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3027 .loc 1 1584 7 is_stmt 1 view .LVU970 +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3028 .loc 1 1584 28 is_stmt 0 view .LVU971 + 3029 0076 638D ldrh r3, [r4, #42] +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3030 .loc 1 1584 22 view .LVU972 + 3031 0078 2385 strh r3, [r4, #40] @ movhi +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3032 .loc 1 1585 7 is_stmt 1 view .LVU973 + 3033 .LVL171: +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3034 .loc 1 1585 16 is_stmt 0 view .LVU974 + 3035 007a 4FF00073 mov r3, #33554432 + 3036 007e E9E7 b .L212 + 3037 .LVL172: + 3038 .L213: +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3039 .loc 1 1608 12 view .LVU975 + 3040 0080 0220 movs r0, #2 + 3041 0082 F6E7 b .L210 + 3042 .L214: +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3043 .loc 1 1561 14 view .LVU976 + 3044 0084 0220 movs r0, #2 + 3045 0086 F4E7 b .L210 + 3046 .L215: +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3047 .loc 1 1565 5 view .LVU977 + 3048 0088 0220 movs r0, #2 + 3049 008a F2E7 b .L210 + 3050 .L218: + 3051 .align 2 + 3052 .L217: + 3053 008c 0000FFFF .word -65536 + 3054 0090 00000000 .word I2C_Master_ISR_IT + 3055 0094 00200080 .word -2147475456 + 3056 .cfi_endproc + 3057 .LFE149: + 3059 .section .text.HAL_I2C_Master_Receive_IT,"ax",%progbits + 3060 .align 1 + 3061 .global HAL_I2C_Master_Receive_IT + 3062 .syntax unified + 3063 .thumb + 3064 .thumb_func + 3065 .fpu fpv5-d16 + 3067 HAL_I2C_Master_Receive_IT: + 3068 .LVL173: + 3069 .LFB150: +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 3070 .loc 1 1623 1 is_stmt 1 view -0 + 3071 .cfi_startproc + 3072 @ args = 0, pretend = 0, frame = 0 + 3073 @ frame_needed = 0, uses_anonymous_args = 0 +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 3074 .loc 1 1623 1 is_stmt 0 view .LVU979 + ARM GAS /tmp/ccEimIdZ.s page 186 + + + 3075 0000 30B5 push {r4, r5, lr} + 3076 .LCFI39: + 3077 .cfi_def_cfa_offset 12 + 3078 .cfi_offset 4, -12 + 3079 .cfi_offset 5, -8 + 3080 .cfi_offset 14, -4 + 3081 0002 83B0 sub sp, sp, #12 + 3082 .LCFI40: + 3083 .cfi_def_cfa_offset 24 + 3084 0004 0446 mov r4, r0 +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3085 .loc 1 1624 3 is_stmt 1 view .LVU980 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3086 .loc 1 1626 3 view .LVU981 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3087 .loc 1 1626 11 is_stmt 0 view .LVU982 + 3088 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3089 .LVL174: +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3090 .loc 1 1626 11 view .LVU983 + 3091 000a C0B2 uxtb r0, r0 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3092 .loc 1 1626 6 view .LVU984 + 3093 000c 2028 cmp r0, #32 + 3094 000e 37D1 bne .L223 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3095 .loc 1 1628 5 is_stmt 1 view .LVU985 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3096 .loc 1 1628 9 is_stmt 0 view .LVU986 + 3097 0010 2068 ldr r0, [r4] + 3098 0012 8069 ldr r0, [r0, #24] +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3099 .loc 1 1628 8 view .LVU987 + 3100 0014 10F4004F tst r0, #32768 + 3101 0018 34D1 bne .L224 +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3102 .loc 1 1634 5 is_stmt 1 view .LVU988 +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3103 .loc 1 1634 5 view .LVU989 + 3104 001a 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 3105 001e 0128 cmp r0, #1 + 3106 0020 32D0 beq .L225 +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3107 .loc 1 1634 5 discriminator 2 view .LVU990 + 3108 0022 0120 movs r0, #1 + 3109 0024 84F84000 strb r0, [r4, #64] +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3110 .loc 1 1634 5 discriminator 2 view .LVU991 +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3111 .loc 1 1636 5 discriminator 2 view .LVU992 +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3112 .loc 1 1636 23 is_stmt 0 discriminator 2 view .LVU993 + 3113 0028 2220 movs r0, #34 + 3114 002a 84F84100 strb r0, [r4, #65] +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3115 .loc 1 1637 5 is_stmt 1 discriminator 2 view .LVU994 +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/ccEimIdZ.s page 187 + + + 3116 .loc 1 1637 23 is_stmt 0 discriminator 2 view .LVU995 + 3117 002e 1020 movs r0, #16 + 3118 0030 84F84200 strb r0, [r4, #66] +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3119 .loc 1 1638 5 is_stmt 1 discriminator 2 view .LVU996 +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3120 .loc 1 1638 23 is_stmt 0 discriminator 2 view .LVU997 + 3121 0034 0020 movs r0, #0 + 3122 0036 6064 str r0, [r4, #68] +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3123 .loc 1 1641 5 is_stmt 1 discriminator 2 view .LVU998 +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3124 .loc 1 1641 23 is_stmt 0 discriminator 2 view .LVU999 + 3125 0038 6262 str r2, [r4, #36] +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3126 .loc 1 1642 5 is_stmt 1 discriminator 2 view .LVU1000 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3127 .loc 1 1642 23 is_stmt 0 discriminator 2 view .LVU1001 + 3128 003a 6385 strh r3, [r4, #42] @ movhi +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3129 .loc 1 1643 5 is_stmt 1 discriminator 2 view .LVU1002 +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3130 .loc 1 1643 23 is_stmt 0 discriminator 2 view .LVU1003 + 3131 003c 134B ldr r3, .L227 + 3132 .LVL175: +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3133 .loc 1 1643 23 discriminator 2 view .LVU1004 + 3134 003e E362 str r3, [r4, #44] + 3135 .LVL176: +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3136 .loc 1 1644 5 is_stmt 1 discriminator 2 view .LVU1005 +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3137 .loc 1 1644 23 is_stmt 0 discriminator 2 view .LVU1006 + 3138 0040 134B ldr r3, .L227+4 + 3139 0042 6363 str r3, [r4, #52] +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3140 .loc 1 1646 5 is_stmt 1 discriminator 2 view .LVU1007 +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3141 .loc 1 1646 13 is_stmt 0 discriminator 2 view .LVU1008 + 3142 0044 638D ldrh r3, [r4, #42] + 3143 0046 9BB2 uxth r3, r3 +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3144 .loc 1 1646 8 discriminator 2 view .LVU1009 + 3145 0048 FF2B cmp r3, #255 + 3146 004a 14D9 bls .L221 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3147 .loc 1 1648 7 is_stmt 1 view .LVU1010 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3148 .loc 1 1648 22 is_stmt 0 view .LVU1011 + 3149 004c FF23 movs r3, #255 + 3150 004e 2385 strh r3, [r4, #40] @ movhi +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3151 .loc 1 1649 7 is_stmt 1 view .LVU1012 + 3152 .LVL177: +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3153 .loc 1 1649 16 is_stmt 0 view .LVU1013 + 3154 0050 4FF08073 mov r3, #16777216 + ARM GAS /tmp/ccEimIdZ.s page 188 + + + 3155 .LVL178: + 3156 .L222: +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3157 .loc 1 1659 5 is_stmt 1 view .LVU1014 + 3158 0054 0F4A ldr r2, .L227+8 + 3159 .LVL179: +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3160 .loc 1 1659 5 is_stmt 0 view .LVU1015 + 3161 0056 0092 str r2, [sp] + 3162 .LVL180: +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3163 .loc 1 1659 5 view .LVU1016 + 3164 0058 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3165 005c 2046 mov r0, r4 + 3166 005e FFF7FEFF bl I2C_TransferConfig + 3167 .LVL181: +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3168 .loc 1 1662 5 is_stmt 1 view .LVU1017 +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3169 .loc 1 1662 5 view .LVU1018 + 3170 0062 0025 movs r5, #0 + 3171 0064 84F84050 strb r5, [r4, #64] +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3172 .loc 1 1662 5 view .LVU1019 +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3173 .loc 1 1671 5 view .LVU1020 + 3174 0068 0221 movs r1, #2 + 3175 006a 2046 mov r0, r4 + 3176 006c FFF7FEFF bl I2C_Enable_IRQ + 3177 .LVL182: +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3178 .loc 1 1673 5 view .LVU1021 +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3179 .loc 1 1673 12 is_stmt 0 view .LVU1022 + 3180 0070 2846 mov r0, r5 + 3181 .L220: +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3182 .loc 1 1679 1 view .LVU1023 + 3183 0072 03B0 add sp, sp, #12 + 3184 .LCFI41: + 3185 .cfi_remember_state + 3186 .cfi_def_cfa_offset 12 + 3187 @ sp needed + 3188 0074 30BD pop {r4, r5, pc} + 3189 .LVL183: + 3190 .L221: + 3191 .LCFI42: + 3192 .cfi_restore_state +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3193 .loc 1 1653 7 is_stmt 1 view .LVU1024 +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3194 .loc 1 1653 28 is_stmt 0 view .LVU1025 + 3195 0076 638D ldrh r3, [r4, #42] +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3196 .loc 1 1653 22 view .LVU1026 + 3197 0078 2385 strh r3, [r4, #40] @ movhi +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 189 + + + 3198 .loc 1 1654 7 is_stmt 1 view .LVU1027 + 3199 .LVL184: +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3200 .loc 1 1654 16 is_stmt 0 view .LVU1028 + 3201 007a 4FF00073 mov r3, #33554432 + 3202 007e E9E7 b .L222 + 3203 .LVL185: + 3204 .L223: +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3205 .loc 1 1677 12 view .LVU1029 + 3206 0080 0220 movs r0, #2 + 3207 0082 F6E7 b .L220 + 3208 .L224: +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3209 .loc 1 1630 14 view .LVU1030 + 3210 0084 0220 movs r0, #2 + 3211 0086 F4E7 b .L220 + 3212 .L225: +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3213 .loc 1 1634 5 view .LVU1031 + 3214 0088 0220 movs r0, #2 + 3215 008a F2E7 b .L220 + 3216 .L228: + 3217 .align 2 + 3218 .L227: + 3219 008c 0000FFFF .word -65536 + 3220 0090 00000000 .word I2C_Master_ISR_IT + 3221 0094 00240080 .word -2147474432 + 3222 .cfi_endproc + 3223 .LFE150: + 3225 .section .text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits + 3226 .align 1 + 3227 .global HAL_I2C_Slave_Transmit_IT + 3228 .syntax unified + 3229 .thumb + 3230 .thumb_func + 3231 .fpu fpv5-d16 + 3233 HAL_I2C_Slave_Transmit_IT: + 3234 .LVL186: + 3235 .LFB151: +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3236 .loc 1 1690 1 is_stmt 1 view -0 + 3237 .cfi_startproc + 3238 @ args = 0, pretend = 0, frame = 0 + 3239 @ frame_needed = 0, uses_anonymous_args = 0 +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3240 .loc 1 1690 1 is_stmt 0 view .LVU1033 + 3241 0000 38B5 push {r3, r4, r5, lr} + 3242 .LCFI43: + 3243 .cfi_def_cfa_offset 16 + 3244 .cfi_offset 3, -16 + 3245 .cfi_offset 4, -12 + 3246 .cfi_offset 5, -8 + 3247 .cfi_offset 14, -4 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3248 .loc 1 1691 3 is_stmt 1 view .LVU1034 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 190 + + + 3249 .loc 1 1691 11 is_stmt 0 view .LVU1035 + 3250 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3251 0006 DBB2 uxtb r3, r3 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3252 .loc 1 1691 6 view .LVU1036 + 3253 0008 202B cmp r3, #32 + 3254 000a 23D1 bne .L231 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3255 .loc 1 1694 5 is_stmt 1 view .LVU1037 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3256 .loc 1 1694 5 view .LVU1038 + 3257 000c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 3258 0010 012B cmp r3, #1 + 3259 0012 21D0 beq .L232 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3260 .loc 1 1694 5 discriminator 2 view .LVU1039 + 3261 0014 0123 movs r3, #1 + 3262 0016 80F84030 strb r3, [r0, #64] +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3263 .loc 1 1694 5 discriminator 2 view .LVU1040 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3264 .loc 1 1696 5 discriminator 2 view .LVU1041 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3265 .loc 1 1696 23 is_stmt 0 discriminator 2 view .LVU1042 + 3266 001a 2123 movs r3, #33 + 3267 001c 80F84130 strb r3, [r0, #65] +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3268 .loc 1 1697 5 is_stmt 1 discriminator 2 view .LVU1043 +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3269 .loc 1 1697 23 is_stmt 0 discriminator 2 view .LVU1044 + 3270 0020 2023 movs r3, #32 + 3271 0022 80F84230 strb r3, [r0, #66] +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3272 .loc 1 1698 5 is_stmt 1 discriminator 2 view .LVU1045 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3273 .loc 1 1698 23 is_stmt 0 discriminator 2 view .LVU1046 + 3274 0026 0024 movs r4, #0 + 3275 0028 4464 str r4, [r0, #68] +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3276 .loc 1 1701 5 is_stmt 1 discriminator 2 view .LVU1047 +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3277 .loc 1 1701 9 is_stmt 0 discriminator 2 view .LVU1048 + 3278 002a 0568 ldr r5, [r0] +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3279 .loc 1 1701 25 discriminator 2 view .LVU1049 + 3280 002c 6B68 ldr r3, [r5, #4] + 3281 002e 23F40043 bic r3, r3, #32768 + 3282 0032 6B60 str r3, [r5, #4] +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3283 .loc 1 1704 5 is_stmt 1 discriminator 2 view .LVU1050 +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3284 .loc 1 1704 23 is_stmt 0 discriminator 2 view .LVU1051 + 3285 0034 4162 str r1, [r0, #36] +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3286 .loc 1 1705 5 is_stmt 1 discriminator 2 view .LVU1052 +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3287 .loc 1 1705 23 is_stmt 0 discriminator 2 view .LVU1053 + ARM GAS /tmp/ccEimIdZ.s page 191 + + + 3288 0036 4285 strh r2, [r0, #42] @ movhi +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3289 .loc 1 1706 5 is_stmt 1 discriminator 2 view .LVU1054 +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3290 .loc 1 1706 29 is_stmt 0 discriminator 2 view .LVU1055 + 3291 0038 438D ldrh r3, [r0, #42] +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3292 .loc 1 1706 23 discriminator 2 view .LVU1056 + 3293 003a 0385 strh r3, [r0, #40] @ movhi +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3294 .loc 1 1707 5 is_stmt 1 discriminator 2 view .LVU1057 +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3295 .loc 1 1707 23 is_stmt 0 discriminator 2 view .LVU1058 + 3296 003c 074B ldr r3, .L234 + 3297 003e C362 str r3, [r0, #44] +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3298 .loc 1 1708 5 is_stmt 1 discriminator 2 view .LVU1059 +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3299 .loc 1 1708 23 is_stmt 0 discriminator 2 view .LVU1060 + 3300 0040 074B ldr r3, .L234+4 + 3301 0042 4363 str r3, [r0, #52] +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3302 .loc 1 1711 5 is_stmt 1 discriminator 2 view .LVU1061 +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3303 .loc 1 1711 5 discriminator 2 view .LVU1062 + 3304 0044 80F84040 strb r4, [r0, #64] +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3305 .loc 1 1711 5 discriminator 2 view .LVU1063 +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3306 .loc 1 1720 5 discriminator 2 view .LVU1064 + 3307 0048 48F20101 movw r1, #32769 + 3308 .LVL187: +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3309 .loc 1 1720 5 is_stmt 0 discriminator 2 view .LVU1065 + 3310 004c FFF7FEFF bl I2C_Enable_IRQ + 3311 .LVL188: +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3312 .loc 1 1722 5 is_stmt 1 discriminator 2 view .LVU1066 +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3313 .loc 1 1722 12 is_stmt 0 discriminator 2 view .LVU1067 + 3314 0050 2046 mov r0, r4 + 3315 .L230: +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3316 .loc 1 1728 1 view .LVU1068 + 3317 0052 38BD pop {r3, r4, r5, pc} + 3318 .LVL189: + 3319 .L231: +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3320 .loc 1 1726 12 view .LVU1069 + 3321 0054 0220 movs r0, #2 + 3322 .LVL190: +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3323 .loc 1 1726 12 view .LVU1070 + 3324 0056 FCE7 b .L230 + 3325 .LVL191: + 3326 .L232: +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 192 + + + 3327 .loc 1 1694 5 view .LVU1071 + 3328 0058 0220 movs r0, #2 + 3329 .LVL192: +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3330 .loc 1 1694 5 view .LVU1072 + 3331 005a FAE7 b .L230 + 3332 .L235: + 3333 .align 2 + 3334 .L234: + 3335 005c 0000FFFF .word -65536 + 3336 0060 00000000 .word I2C_Slave_ISR_IT + 3337 .cfi_endproc + 3338 .LFE151: + 3340 .section .text.HAL_I2C_Slave_Receive_IT,"ax",%progbits + 3341 .align 1 + 3342 .global HAL_I2C_Slave_Receive_IT + 3343 .syntax unified + 3344 .thumb + 3345 .thumb_func + 3346 .fpu fpv5-d16 + 3348 HAL_I2C_Slave_Receive_IT: + 3349 .LVL193: + 3350 .LFB152: +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3351 .loc 1 1739 1 is_stmt 1 view -0 + 3352 .cfi_startproc + 3353 @ args = 0, pretend = 0, frame = 0 + 3354 @ frame_needed = 0, uses_anonymous_args = 0 +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3355 .loc 1 1739 1 is_stmt 0 view .LVU1074 + 3356 0000 38B5 push {r3, r4, r5, lr} + 3357 .LCFI44: + 3358 .cfi_def_cfa_offset 16 + 3359 .cfi_offset 3, -16 + 3360 .cfi_offset 4, -12 + 3361 .cfi_offset 5, -8 + 3362 .cfi_offset 14, -4 +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3363 .loc 1 1740 3 is_stmt 1 view .LVU1075 +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3364 .loc 1 1740 11 is_stmt 0 view .LVU1076 + 3365 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3366 0006 DBB2 uxtb r3, r3 +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3367 .loc 1 1740 6 view .LVU1077 + 3368 0008 202B cmp r3, #32 + 3369 000a 23D1 bne .L238 +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3370 .loc 1 1743 5 is_stmt 1 view .LVU1078 +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3371 .loc 1 1743 5 view .LVU1079 + 3372 000c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 3373 0010 012B cmp r3, #1 + 3374 0012 21D0 beq .L239 +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3375 .loc 1 1743 5 discriminator 2 view .LVU1080 + 3376 0014 0123 movs r3, #1 + ARM GAS /tmp/ccEimIdZ.s page 193 + + + 3377 0016 80F84030 strb r3, [r0, #64] +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3378 .loc 1 1743 5 discriminator 2 view .LVU1081 +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3379 .loc 1 1745 5 discriminator 2 view .LVU1082 +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3380 .loc 1 1745 23 is_stmt 0 discriminator 2 view .LVU1083 + 3381 001a 2223 movs r3, #34 + 3382 001c 80F84130 strb r3, [r0, #65] +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3383 .loc 1 1746 5 is_stmt 1 discriminator 2 view .LVU1084 +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3384 .loc 1 1746 23 is_stmt 0 discriminator 2 view .LVU1085 + 3385 0020 2023 movs r3, #32 + 3386 0022 80F84230 strb r3, [r0, #66] +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3387 .loc 1 1747 5 is_stmt 1 discriminator 2 view .LVU1086 +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3388 .loc 1 1747 23 is_stmt 0 discriminator 2 view .LVU1087 + 3389 0026 0024 movs r4, #0 + 3390 0028 4464 str r4, [r0, #68] +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3391 .loc 1 1750 5 is_stmt 1 discriminator 2 view .LVU1088 +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3392 .loc 1 1750 9 is_stmt 0 discriminator 2 view .LVU1089 + 3393 002a 0568 ldr r5, [r0] +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3394 .loc 1 1750 25 discriminator 2 view .LVU1090 + 3395 002c 6B68 ldr r3, [r5, #4] + 3396 002e 23F40043 bic r3, r3, #32768 + 3397 0032 6B60 str r3, [r5, #4] +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3398 .loc 1 1753 5 is_stmt 1 discriminator 2 view .LVU1091 +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3399 .loc 1 1753 23 is_stmt 0 discriminator 2 view .LVU1092 + 3400 0034 4162 str r1, [r0, #36] +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3401 .loc 1 1754 5 is_stmt 1 discriminator 2 view .LVU1093 +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3402 .loc 1 1754 23 is_stmt 0 discriminator 2 view .LVU1094 + 3403 0036 4285 strh r2, [r0, #42] @ movhi +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3404 .loc 1 1755 5 is_stmt 1 discriminator 2 view .LVU1095 +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3405 .loc 1 1755 29 is_stmt 0 discriminator 2 view .LVU1096 + 3406 0038 438D ldrh r3, [r0, #42] +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3407 .loc 1 1755 23 discriminator 2 view .LVU1097 + 3408 003a 0385 strh r3, [r0, #40] @ movhi +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3409 .loc 1 1756 5 is_stmt 1 discriminator 2 view .LVU1098 +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3410 .loc 1 1756 23 is_stmt 0 discriminator 2 view .LVU1099 + 3411 003c 074B ldr r3, .L241 + 3412 003e C362 str r3, [r0, #44] +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3413 .loc 1 1757 5 is_stmt 1 discriminator 2 view .LVU1100 + ARM GAS /tmp/ccEimIdZ.s page 194 + + +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3414 .loc 1 1757 23 is_stmt 0 discriminator 2 view .LVU1101 + 3415 0040 074B ldr r3, .L241+4 + 3416 0042 4363 str r3, [r0, #52] +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3417 .loc 1 1760 5 is_stmt 1 discriminator 2 view .LVU1102 +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3418 .loc 1 1760 5 discriminator 2 view .LVU1103 + 3419 0044 80F84040 strb r4, [r0, #64] +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3420 .loc 1 1760 5 discriminator 2 view .LVU1104 +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3421 .loc 1 1769 5 discriminator 2 view .LVU1105 + 3422 0048 48F20201 movw r1, #32770 + 3423 .LVL194: +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3424 .loc 1 1769 5 is_stmt 0 discriminator 2 view .LVU1106 + 3425 004c FFF7FEFF bl I2C_Enable_IRQ + 3426 .LVL195: +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3427 .loc 1 1771 5 is_stmt 1 discriminator 2 view .LVU1107 +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3428 .loc 1 1771 12 is_stmt 0 discriminator 2 view .LVU1108 + 3429 0050 2046 mov r0, r4 + 3430 .L237: +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3431 .loc 1 1777 1 view .LVU1109 + 3432 0052 38BD pop {r3, r4, r5, pc} + 3433 .LVL196: + 3434 .L238: +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3435 .loc 1 1775 12 view .LVU1110 + 3436 0054 0220 movs r0, #2 + 3437 .LVL197: +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3438 .loc 1 1775 12 view .LVU1111 + 3439 0056 FCE7 b .L237 + 3440 .LVL198: + 3441 .L239: +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3442 .loc 1 1743 5 view .LVU1112 + 3443 0058 0220 movs r0, #2 + 3444 .LVL199: +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3445 .loc 1 1743 5 view .LVU1113 + 3446 005a FAE7 b .L237 + 3447 .L242: + 3448 .align 2 + 3449 .L241: + 3450 005c 0000FFFF .word -65536 + 3451 0060 00000000 .word I2C_Slave_ISR_IT + 3452 .cfi_endproc + 3453 .LFE152: + 3455 .section .text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits + 3456 .align 1 + 3457 .global HAL_I2C_Master_Transmit_DMA + 3458 .syntax unified + ARM GAS /tmp/ccEimIdZ.s page 195 + + + 3459 .thumb + 3460 .thumb_func + 3461 .fpu fpv5-d16 + 3463 HAL_I2C_Master_Transmit_DMA: + 3464 .LVL200: + 3465 .LFB153: +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 3466 .loc 1 1790 1 is_stmt 1 view -0 + 3467 .cfi_startproc + 3468 @ args = 0, pretend = 0, frame = 0 + 3469 @ frame_needed = 0, uses_anonymous_args = 0 +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 3470 .loc 1 1790 1 is_stmt 0 view .LVU1115 + 3471 0000 70B5 push {r4, r5, r6, lr} + 3472 .LCFI45: + 3473 .cfi_def_cfa_offset 16 + 3474 .cfi_offset 4, -16 + 3475 .cfi_offset 5, -12 + 3476 .cfi_offset 6, -8 + 3477 .cfi_offset 14, -4 + 3478 0002 82B0 sub sp, sp, #8 + 3479 .LCFI46: + 3480 .cfi_def_cfa_offset 24 + 3481 0004 0446 mov r4, r0 +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 3482 .loc 1 1791 3 is_stmt 1 view .LVU1116 +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3483 .loc 1 1792 3 view .LVU1117 +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3484 .loc 1 1794 3 view .LVU1118 +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3485 .loc 1 1794 11 is_stmt 0 view .LVU1119 + 3486 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3487 .LVL201: +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3488 .loc 1 1794 11 view .LVU1120 + 3489 000a C0B2 uxtb r0, r0 +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3490 .loc 1 1794 6 view .LVU1121 + 3491 000c 2028 cmp r0, #32 + 3492 000e 40F08D80 bne .L252 + 3493 0012 0D46 mov r5, r1 + 3494 0014 1146 mov r1, r2 + 3495 .LVL202: +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3496 .loc 1 1796 5 is_stmt 1 view .LVU1122 +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3497 .loc 1 1796 9 is_stmt 0 view .LVU1123 + 3498 0016 2268 ldr r2, [r4] + 3499 .LVL203: +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3500 .loc 1 1796 9 view .LVU1124 + 3501 0018 9269 ldr r2, [r2, #24] +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3502 .loc 1 1796 8 view .LVU1125 + 3503 001a 12F4004F tst r2, #32768 + 3504 001e 40F08880 bne .L253 + ARM GAS /tmp/ccEimIdZ.s page 196 + + +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3505 .loc 1 1802 5 is_stmt 1 view .LVU1126 +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3506 .loc 1 1802 5 view .LVU1127 + 3507 0022 94F84020 ldrb r2, [r4, #64] @ zero_extendqisi2 + 3508 0026 012A cmp r2, #1 + 3509 0028 00F08580 beq .L254 +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3510 .loc 1 1802 5 discriminator 2 view .LVU1128 + 3511 002c 0122 movs r2, #1 + 3512 002e 84F84020 strb r2, [r4, #64] +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3513 .loc 1 1802 5 discriminator 2 view .LVU1129 +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3514 .loc 1 1804 5 discriminator 2 view .LVU1130 +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3515 .loc 1 1804 23 is_stmt 0 discriminator 2 view .LVU1131 + 3516 0032 2122 movs r2, #33 + 3517 0034 84F84120 strb r2, [r4, #65] +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3518 .loc 1 1805 5 is_stmt 1 discriminator 2 view .LVU1132 +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3519 .loc 1 1805 23 is_stmt 0 discriminator 2 view .LVU1133 + 3520 0038 1022 movs r2, #16 + 3521 003a 84F84220 strb r2, [r4, #66] +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3522 .loc 1 1806 5 is_stmt 1 discriminator 2 view .LVU1134 +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3523 .loc 1 1806 23 is_stmt 0 discriminator 2 view .LVU1135 + 3524 003e 0022 movs r2, #0 + 3525 0040 6264 str r2, [r4, #68] +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3526 .loc 1 1809 5 is_stmt 1 discriminator 2 view .LVU1136 +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3527 .loc 1 1809 23 is_stmt 0 discriminator 2 view .LVU1137 + 3528 0042 6162 str r1, [r4, #36] +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3529 .loc 1 1810 5 is_stmt 1 discriminator 2 view .LVU1138 +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3530 .loc 1 1810 23 is_stmt 0 discriminator 2 view .LVU1139 + 3531 0044 6385 strh r3, [r4, #42] @ movhi +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3532 .loc 1 1811 5 is_stmt 1 discriminator 2 view .LVU1140 +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3533 .loc 1 1811 23 is_stmt 0 discriminator 2 view .LVU1141 + 3534 0046 3D4B ldr r3, .L258 + 3535 .LVL204: +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3536 .loc 1 1811 23 discriminator 2 view .LVU1142 + 3537 0048 E362 str r3, [r4, #44] + 3538 .LVL205: +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3539 .loc 1 1812 5 is_stmt 1 discriminator 2 view .LVU1143 +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3540 .loc 1 1812 23 is_stmt 0 discriminator 2 view .LVU1144 + 3541 004a 3D4B ldr r3, .L258+4 + 3542 004c 6363 str r3, [r4, #52] + ARM GAS /tmp/ccEimIdZ.s page 197 + + +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3543 .loc 1 1814 5 is_stmt 1 discriminator 2 view .LVU1145 +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3544 .loc 1 1814 13 is_stmt 0 discriminator 2 view .LVU1146 + 3545 004e 638D ldrh r3, [r4, #42] + 3546 0050 9BB2 uxth r3, r3 +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3547 .loc 1 1814 8 discriminator 2 view .LVU1147 + 3548 0052 FF2B cmp r3, #255 + 3549 0054 27D9 bls .L245 +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3550 .loc 1 1816 7 is_stmt 1 view .LVU1148 +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3551 .loc 1 1816 22 is_stmt 0 view .LVU1149 + 3552 0056 FF23 movs r3, #255 + 3553 0058 2385 strh r3, [r4, #40] @ movhi +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3554 .loc 1 1817 7 is_stmt 1 view .LVU1150 + 3555 .LVL206: +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3556 .loc 1 1817 16 is_stmt 0 view .LVU1151 + 3557 005a 4FF08076 mov r6, #16777216 + 3558 .LVL207: + 3559 .L246: +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3560 .loc 1 1825 5 is_stmt 1 view .LVU1152 +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3561 .loc 1 1825 13 is_stmt 0 view .LVU1153 + 3562 005e 228D ldrh r2, [r4, #40] +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3563 .loc 1 1825 8 view .LVU1154 + 3564 0060 002A cmp r2, #0 + 3565 0062 4FD0 beq .L247 +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3566 .loc 1 1827 7 is_stmt 1 view .LVU1155 +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3567 .loc 1 1827 15 is_stmt 0 view .LVU1156 + 3568 0064 A36B ldr r3, [r4, #56] +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3569 .loc 1 1827 10 view .LVU1157 + 3570 0066 1BB3 cbz r3, .L248 +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3571 .loc 1 1830 9 is_stmt 1 view .LVU1158 +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3572 .loc 1 1830 40 is_stmt 0 view .LVU1159 + 3573 0068 364A ldr r2, .L258+8 + 3574 006a DA63 str r2, [r3, #60] +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3575 .loc 1 1833 9 is_stmt 1 view .LVU1160 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3576 .loc 1 1833 13 is_stmt 0 view .LVU1161 + 3577 006c A36B ldr r3, [r4, #56] +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3578 .loc 1 1833 41 view .LVU1162 + 3579 006e 364A ldr r2, .L258+12 + 3580 0070 DA64 str r2, [r3, #76] +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + ARM GAS /tmp/ccEimIdZ.s page 198 + + + 3581 .loc 1 1836 9 is_stmt 1 view .LVU1163 +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3582 .loc 1 1836 13 is_stmt 0 view .LVU1164 + 3583 0072 A26B ldr r2, [r4, #56] +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3584 .loc 1 1836 44 view .LVU1165 + 3585 0074 0023 movs r3, #0 + 3586 0076 1364 str r3, [r2, #64] +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3587 .loc 1 1837 9 is_stmt 1 view .LVU1166 +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3588 .loc 1 1837 13 is_stmt 0 view .LVU1167 + 3589 0078 A26B ldr r2, [r4, #56] +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3590 .loc 1 1837 41 view .LVU1168 + 3591 007a 1365 str r3, [r2, #80] +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3592 .loc 1 1840 9 is_stmt 1 view .LVU1169 +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3593 .loc 1 1840 88 is_stmt 0 view .LVU1170 + 3594 007c 2268 ldr r2, [r4] +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3595 .loc 1 1840 25 view .LVU1171 + 3596 007e 238D ldrh r3, [r4, #40] + 3597 0080 2832 adds r2, r2, #40 + 3598 0082 A06B ldr r0, [r4, #56] + 3599 0084 FFF7FEFF bl HAL_DMA_Start_IT + 3600 .LVL208: +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3601 .loc 1 1857 7 is_stmt 1 view .LVU1172 +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3602 .loc 1 1857 10 is_stmt 0 view .LVU1173 + 3603 0088 00B3 cbz r0, .L257 +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3604 .loc 1 1881 9 is_stmt 1 view .LVU1174 +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3605 .loc 1 1881 25 is_stmt 0 view .LVU1175 + 3606 008a 2023 movs r3, #32 + 3607 008c 84F84130 strb r3, [r4, #65] +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3608 .loc 1 1882 9 is_stmt 1 view .LVU1176 +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3609 .loc 1 1882 25 is_stmt 0 view .LVU1177 + 3610 0090 0022 movs r2, #0 + 3611 0092 84F84220 strb r2, [r4, #66] +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3612 .loc 1 1885 9 is_stmt 1 view .LVU1178 +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3613 .loc 1 1885 25 is_stmt 0 view .LVU1179 + 3614 0096 636C ldr r3, [r4, #68] + 3615 0098 43F01003 orr r3, r3, #16 + 3616 009c 6364 str r3, [r4, #68] +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3617 .loc 1 1888 9 is_stmt 1 view .LVU1180 +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3618 .loc 1 1888 9 view .LVU1181 + 3619 009e 84F84020 strb r2, [r4, #64] + ARM GAS /tmp/ccEimIdZ.s page 199 + + +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3620 .loc 1 1888 9 view .LVU1182 +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3621 .loc 1 1890 9 view .LVU1183 +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3622 .loc 1 1890 16 is_stmt 0 view .LVU1184 + 3623 00a2 0120 movs r0, #1 + 3624 .LVL209: +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3625 .loc 1 1890 16 view .LVU1185 + 3626 00a4 43E0 b .L244 + 3627 .LVL210: + 3628 .L245: +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3629 .loc 1 1821 7 is_stmt 1 view .LVU1186 +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3630 .loc 1 1821 28 is_stmt 0 view .LVU1187 + 3631 00a6 638D ldrh r3, [r4, #42] +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3632 .loc 1 1821 22 view .LVU1188 + 3633 00a8 2385 strh r3, [r4, #40] @ movhi +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3634 .loc 1 1822 7 is_stmt 1 view .LVU1189 + 3635 .LVL211: +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3636 .loc 1 1822 16 is_stmt 0 view .LVU1190 + 3637 00aa 4FF00076 mov r6, #33554432 + 3638 00ae D6E7 b .L246 + 3639 .LVL212: + 3640 .L248: +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3641 .loc 1 1845 9 is_stmt 1 view .LVU1191 +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3642 .loc 1 1845 25 is_stmt 0 view .LVU1192 + 3643 00b0 2023 movs r3, #32 + 3644 00b2 84F84130 strb r3, [r4, #65] +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3645 .loc 1 1846 9 is_stmt 1 view .LVU1193 +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3646 .loc 1 1846 25 is_stmt 0 view .LVU1194 + 3647 00b6 0022 movs r2, #0 + 3648 00b8 84F84220 strb r2, [r4, #66] +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3649 .loc 1 1849 9 is_stmt 1 view .LVU1195 +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3650 .loc 1 1849 25 is_stmt 0 view .LVU1196 + 3651 00bc 636C ldr r3, [r4, #68] + 3652 00be 43F08003 orr r3, r3, #128 + 3653 00c2 6364 str r3, [r4, #68] +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3654 .loc 1 1852 9 is_stmt 1 view .LVU1197 +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3655 .loc 1 1852 9 view .LVU1198 + 3656 00c4 84F84020 strb r2, [r4, #64] +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3657 .loc 1 1852 9 view .LVU1199 +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 200 + + + 3658 .loc 1 1854 9 view .LVU1200 +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3659 .loc 1 1854 16 is_stmt 0 view .LVU1201 + 3660 00c8 0120 movs r0, #1 + 3661 00ca 30E0 b .L244 + 3662 .LVL213: + 3663 .L257: +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3664 .loc 1 1861 9 is_stmt 1 view .LVU1202 + 3665 00cc 1F4B ldr r3, .L258+16 + 3666 00ce 0093 str r3, [sp] + 3667 00d0 3346 mov r3, r6 + 3668 00d2 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3669 00d6 2946 mov r1, r5 + 3670 00d8 2046 mov r0, r4 + 3671 .LVL214: +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3672 .loc 1 1861 9 is_stmt 0 view .LVU1203 + 3673 00da FFF7FEFF bl I2C_TransferConfig + 3674 .LVL215: +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3675 .loc 1 1864 9 is_stmt 1 view .LVU1204 +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3676 .loc 1 1864 25 is_stmt 0 view .LVU1205 + 3677 00de 638D ldrh r3, [r4, #42] + 3678 00e0 9BB2 uxth r3, r3 +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3679 .loc 1 1864 32 view .LVU1206 + 3680 00e2 228D ldrh r2, [r4, #40] +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3681 .loc 1 1864 25 view .LVU1207 + 3682 00e4 9B1A subs r3, r3, r2 + 3683 00e6 9BB2 uxth r3, r3 + 3684 00e8 6385 strh r3, [r4, #42] @ movhi +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3685 .loc 1 1867 9 is_stmt 1 view .LVU1208 +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3686 .loc 1 1867 9 view .LVU1209 + 3687 00ea 0023 movs r3, #0 + 3688 00ec 84F84030 strb r3, [r4, #64] +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3689 .loc 1 1867 9 view .LVU1210 +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3690 .loc 1 1873 9 view .LVU1211 + 3691 00f0 1021 movs r1, #16 + 3692 00f2 2046 mov r0, r4 + 3693 00f4 FFF7FEFF bl I2C_Enable_IRQ + 3694 .LVL216: +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3695 .loc 1 1876 9 view .LVU1212 +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3696 .loc 1 1876 13 is_stmt 0 view .LVU1213 + 3697 00f8 2268 ldr r2, [r4] +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3698 .loc 1 1876 29 view .LVU1214 + 3699 00fa 1368 ldr r3, [r2] + 3700 00fc 43F48043 orr r3, r3, #16384 + ARM GAS /tmp/ccEimIdZ.s page 201 + + + 3701 0100 1360 str r3, [r2] + 3702 0102 11E0 b .L251 + 3703 .LVL217: + 3704 .L247: +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3705 .loc 1 1896 7 is_stmt 1 view .LVU1215 +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3706 .loc 1 1896 21 is_stmt 0 view .LVU1216 + 3707 0104 124B ldr r3, .L258+20 + 3708 0106 6363 str r3, [r4, #52] +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3709 .loc 1 1900 7 is_stmt 1 view .LVU1217 + 3710 0108 104B ldr r3, .L258+16 + 3711 010a 0093 str r3, [sp] + 3712 010c 4FF00073 mov r3, #33554432 + 3713 0110 D2B2 uxtb r2, r2 + 3714 0112 2946 mov r1, r5 + 3715 .LVL218: +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3716 .loc 1 1900 7 is_stmt 0 view .LVU1218 + 3717 0114 2046 mov r0, r4 + 3718 0116 FFF7FEFF bl I2C_TransferConfig + 3719 .LVL219: +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3720 .loc 1 1903 7 is_stmt 1 view .LVU1219 +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3721 .loc 1 1903 7 view .LVU1220 + 3722 011a 0023 movs r3, #0 + 3723 011c 84F84030 strb r3, [r4, #64] +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3724 .loc 1 1903 7 view .LVU1221 +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3725 .loc 1 1911 7 view .LVU1222 + 3726 0120 0121 movs r1, #1 + 3727 0122 2046 mov r0, r4 + 3728 0124 FFF7FEFF bl I2C_Enable_IRQ + 3729 .LVL220: + 3730 .L251: +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3731 .loc 1 1914 5 view .LVU1223 +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3732 .loc 1 1914 12 is_stmt 0 view .LVU1224 + 3733 0128 0020 movs r0, #0 + 3734 012a 00E0 b .L244 + 3735 .LVL221: + 3736 .L252: +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3737 .loc 1 1918 12 view .LVU1225 + 3738 012c 0220 movs r0, #2 + 3739 .LVL222: + 3740 .L244: +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3741 .loc 1 1920 1 view .LVU1226 + 3742 012e 02B0 add sp, sp, #8 + 3743 .LCFI47: + 3744 .cfi_remember_state + 3745 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccEimIdZ.s page 202 + + + 3746 @ sp needed + 3747 0130 70BD pop {r4, r5, r6, pc} + 3748 .LVL223: + 3749 .L253: + 3750 .LCFI48: + 3751 .cfi_restore_state +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3752 .loc 1 1798 14 view .LVU1227 + 3753 0132 0220 movs r0, #2 + 3754 0134 FBE7 b .L244 + 3755 .L254: +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3756 .loc 1 1802 5 view .LVU1228 + 3757 0136 0220 movs r0, #2 + 3758 0138 F9E7 b .L244 + 3759 .L259: + 3760 013a 00BF .align 2 + 3761 .L258: + 3762 013c 0000FFFF .word -65536 + 3763 0140 00000000 .word I2C_Master_ISR_DMA + 3764 0144 00000000 .word I2C_DMAMasterTransmitCplt + 3765 0148 00000000 .word I2C_DMAError + 3766 014c 00200080 .word -2147475456 + 3767 0150 00000000 .word I2C_Master_ISR_IT + 3768 .cfi_endproc + 3769 .LFE153: + 3771 .section .text.HAL_I2C_Master_Receive_DMA,"ax",%progbits + 3772 .align 1 + 3773 .global HAL_I2C_Master_Receive_DMA + 3774 .syntax unified + 3775 .thumb + 3776 .thumb_func + 3777 .fpu fpv5-d16 + 3779 HAL_I2C_Master_Receive_DMA: + 3780 .LVL224: + 3781 .LFB154: +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 3782 .loc 1 1933 1 is_stmt 1 view -0 + 3783 .cfi_startproc + 3784 @ args = 0, pretend = 0, frame = 0 + 3785 @ frame_needed = 0, uses_anonymous_args = 0 +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 3786 .loc 1 1933 1 is_stmt 0 view .LVU1230 + 3787 0000 70B5 push {r4, r5, r6, lr} + 3788 .LCFI49: + 3789 .cfi_def_cfa_offset 16 + 3790 .cfi_offset 4, -16 + 3791 .cfi_offset 5, -12 + 3792 .cfi_offset 6, -8 + 3793 .cfi_offset 14, -4 + 3794 0002 82B0 sub sp, sp, #8 + 3795 .LCFI50: + 3796 .cfi_def_cfa_offset 24 + 3797 0004 0446 mov r4, r0 +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 3798 .loc 1 1934 3 is_stmt 1 view .LVU1231 +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 203 + + + 3799 .loc 1 1935 3 view .LVU1232 +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3800 .loc 1 1937 3 view .LVU1233 +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3801 .loc 1 1937 11 is_stmt 0 view .LVU1234 + 3802 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3803 .LVL225: +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3804 .loc 1 1937 11 view .LVU1235 + 3805 000a C0B2 uxtb r0, r0 +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3806 .loc 1 1937 6 view .LVU1236 + 3807 000c 2028 cmp r0, #32 + 3808 000e 40F08C80 bne .L269 + 3809 0012 0D46 mov r5, r1 +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3810 .loc 1 1939 5 is_stmt 1 view .LVU1237 +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3811 .loc 1 1939 9 is_stmt 0 view .LVU1238 + 3812 0014 2168 ldr r1, [r4] + 3813 .LVL226: +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3814 .loc 1 1939 9 view .LVU1239 + 3815 0016 8969 ldr r1, [r1, #24] +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3816 .loc 1 1939 8 view .LVU1240 + 3817 0018 11F4004F tst r1, #32768 + 3818 001c 40F08880 bne .L270 +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3819 .loc 1 1945 5 is_stmt 1 view .LVU1241 +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3820 .loc 1 1945 5 view .LVU1242 + 3821 0020 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 3822 0024 0129 cmp r1, #1 + 3823 0026 00F08580 beq .L271 +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3824 .loc 1 1945 5 discriminator 2 view .LVU1243 + 3825 002a 0121 movs r1, #1 + 3826 002c 84F84010 strb r1, [r4, #64] +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3827 .loc 1 1945 5 discriminator 2 view .LVU1244 +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3828 .loc 1 1947 5 discriminator 2 view .LVU1245 +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3829 .loc 1 1947 23 is_stmt 0 discriminator 2 view .LVU1246 + 3830 0030 2221 movs r1, #34 + 3831 0032 84F84110 strb r1, [r4, #65] +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3832 .loc 1 1948 5 is_stmt 1 discriminator 2 view .LVU1247 +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3833 .loc 1 1948 23 is_stmt 0 discriminator 2 view .LVU1248 + 3834 0036 1021 movs r1, #16 + 3835 0038 84F84210 strb r1, [r4, #66] +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3836 .loc 1 1949 5 is_stmt 1 discriminator 2 view .LVU1249 +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3837 .loc 1 1949 23 is_stmt 0 discriminator 2 view .LVU1250 + ARM GAS /tmp/ccEimIdZ.s page 204 + + + 3838 003c 0021 movs r1, #0 + 3839 003e 6164 str r1, [r4, #68] +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3840 .loc 1 1952 5 is_stmt 1 discriminator 2 view .LVU1251 +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3841 .loc 1 1952 23 is_stmt 0 discriminator 2 view .LVU1252 + 3842 0040 6262 str r2, [r4, #36] +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3843 .loc 1 1953 5 is_stmt 1 discriminator 2 view .LVU1253 +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3844 .loc 1 1953 23 is_stmt 0 discriminator 2 view .LVU1254 + 3845 0042 6385 strh r3, [r4, #42] @ movhi +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3846 .loc 1 1954 5 is_stmt 1 discriminator 2 view .LVU1255 +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3847 .loc 1 1954 23 is_stmt 0 discriminator 2 view .LVU1256 + 3848 0044 3C4B ldr r3, .L275 + 3849 .LVL227: +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3850 .loc 1 1954 23 discriminator 2 view .LVU1257 + 3851 0046 E362 str r3, [r4, #44] + 3852 .LVL228: +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3853 .loc 1 1955 5 is_stmt 1 discriminator 2 view .LVU1258 +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3854 .loc 1 1955 23 is_stmt 0 discriminator 2 view .LVU1259 + 3855 0048 3C4B ldr r3, .L275+4 + 3856 004a 6363 str r3, [r4, #52] +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3857 .loc 1 1957 5 is_stmt 1 discriminator 2 view .LVU1260 +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3858 .loc 1 1957 13 is_stmt 0 discriminator 2 view .LVU1261 + 3859 004c 638D ldrh r3, [r4, #42] + 3860 004e 9BB2 uxth r3, r3 +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3861 .loc 1 1957 8 discriminator 2 view .LVU1262 + 3862 0050 FF2B cmp r3, #255 + 3863 0052 27D9 bls .L262 +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3864 .loc 1 1959 7 is_stmt 1 view .LVU1263 +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3865 .loc 1 1959 22 is_stmt 0 view .LVU1264 + 3866 0054 FF23 movs r3, #255 + 3867 0056 2385 strh r3, [r4, #40] @ movhi +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3868 .loc 1 1960 7 is_stmt 1 view .LVU1265 + 3869 .LVL229: +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3870 .loc 1 1960 16 is_stmt 0 view .LVU1266 + 3871 0058 4FF08076 mov r6, #16777216 + 3872 .LVL230: + 3873 .L263: +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3874 .loc 1 1968 5 is_stmt 1 view .LVU1267 +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3875 .loc 1 1968 13 is_stmt 0 view .LVU1268 + 3876 005c 218D ldrh r1, [r4, #40] + ARM GAS /tmp/ccEimIdZ.s page 205 + + +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3877 .loc 1 1968 8 view .LVU1269 + 3878 005e 0029 cmp r1, #0 + 3879 0060 4FD0 beq .L264 +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3880 .loc 1 1970 7 is_stmt 1 view .LVU1270 +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3881 .loc 1 1970 15 is_stmt 0 view .LVU1271 + 3882 0062 E36B ldr r3, [r4, #60] +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3883 .loc 1 1970 10 view .LVU1272 + 3884 0064 1BB3 cbz r3, .L265 +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3885 .loc 1 1973 9 is_stmt 1 view .LVU1273 +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3886 .loc 1 1973 40 is_stmt 0 view .LVU1274 + 3887 0066 3649 ldr r1, .L275+8 + 3888 0068 D963 str r1, [r3, #60] +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3889 .loc 1 1976 9 is_stmt 1 view .LVU1275 +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3890 .loc 1 1976 13 is_stmt 0 view .LVU1276 + 3891 006a E36B ldr r3, [r4, #60] +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3892 .loc 1 1976 41 view .LVU1277 + 3893 006c 3549 ldr r1, .L275+12 + 3894 006e D964 str r1, [r3, #76] +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3895 .loc 1 1979 9 is_stmt 1 view .LVU1278 +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3896 .loc 1 1979 13 is_stmt 0 view .LVU1279 + 3897 0070 E16B ldr r1, [r4, #60] +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3898 .loc 1 1979 44 view .LVU1280 + 3899 0072 0023 movs r3, #0 + 3900 0074 0B64 str r3, [r1, #64] +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3901 .loc 1 1980 9 is_stmt 1 view .LVU1281 +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3902 .loc 1 1980 13 is_stmt 0 view .LVU1282 + 3903 0076 E16B ldr r1, [r4, #60] +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3904 .loc 1 1980 41 view .LVU1283 + 3905 0078 0B65 str r3, [r1, #80] +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3906 .loc 1 1983 9 is_stmt 1 view .LVU1284 +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3907 .loc 1 1983 71 is_stmt 0 view .LVU1285 + 3908 007a 2168 ldr r1, [r4] +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3909 .loc 1 1983 25 view .LVU1286 + 3910 007c 238D ldrh r3, [r4, #40] + 3911 007e 2431 adds r1, r1, #36 + 3912 0080 E06B ldr r0, [r4, #60] + 3913 0082 FFF7FEFF bl HAL_DMA_Start_IT + 3914 .LVL231: +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 206 + + + 3915 .loc 1 2000 7 is_stmt 1 view .LVU1287 +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 3916 .loc 1 2000 10 is_stmt 0 view .LVU1288 + 3917 0086 00B3 cbz r0, .L274 +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3918 .loc 1 2024 9 is_stmt 1 view .LVU1289 +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3919 .loc 1 2024 25 is_stmt 0 view .LVU1290 + 3920 0088 2023 movs r3, #32 + 3921 008a 84F84130 strb r3, [r4, #65] +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3922 .loc 1 2025 9 is_stmt 1 view .LVU1291 +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3923 .loc 1 2025 25 is_stmt 0 view .LVU1292 + 3924 008e 0022 movs r2, #0 + 3925 0090 84F84220 strb r2, [r4, #66] +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3926 .loc 1 2028 9 is_stmt 1 view .LVU1293 +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3927 .loc 1 2028 25 is_stmt 0 view .LVU1294 + 3928 0094 636C ldr r3, [r4, #68] + 3929 0096 43F01003 orr r3, r3, #16 + 3930 009a 6364 str r3, [r4, #68] +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3931 .loc 1 2031 9 is_stmt 1 view .LVU1295 +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3932 .loc 1 2031 9 view .LVU1296 + 3933 009c 84F84020 strb r2, [r4, #64] +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3934 .loc 1 2031 9 view .LVU1297 +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3935 .loc 1 2033 9 view .LVU1298 +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3936 .loc 1 2033 16 is_stmt 0 view .LVU1299 + 3937 00a0 0120 movs r0, #1 + 3938 .LVL232: +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3939 .loc 1 2033 16 view .LVU1300 + 3940 00a2 43E0 b .L261 + 3941 .LVL233: + 3942 .L262: +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3943 .loc 1 1964 7 is_stmt 1 view .LVU1301 +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3944 .loc 1 1964 28 is_stmt 0 view .LVU1302 + 3945 00a4 638D ldrh r3, [r4, #42] +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3946 .loc 1 1964 22 view .LVU1303 + 3947 00a6 2385 strh r3, [r4, #40] @ movhi +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3948 .loc 1 1965 7 is_stmt 1 view .LVU1304 + 3949 .LVL234: +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3950 .loc 1 1965 16 is_stmt 0 view .LVU1305 + 3951 00a8 4FF00076 mov r6, #33554432 + 3952 00ac D6E7 b .L263 + 3953 .LVL235: + ARM GAS /tmp/ccEimIdZ.s page 207 + + + 3954 .L265: +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3955 .loc 1 1988 9 is_stmt 1 view .LVU1306 +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3956 .loc 1 1988 25 is_stmt 0 view .LVU1307 + 3957 00ae 2023 movs r3, #32 + 3958 00b0 84F84130 strb r3, [r4, #65] +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3959 .loc 1 1989 9 is_stmt 1 view .LVU1308 +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3960 .loc 1 1989 25 is_stmt 0 view .LVU1309 + 3961 00b4 0022 movs r2, #0 + 3962 .LVL236: +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3963 .loc 1 1989 25 view .LVU1310 + 3964 00b6 84F84220 strb r2, [r4, #66] +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3965 .loc 1 1992 9 is_stmt 1 view .LVU1311 +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3966 .loc 1 1992 25 is_stmt 0 view .LVU1312 + 3967 00ba 636C ldr r3, [r4, #68] + 3968 00bc 43F08003 orr r3, r3, #128 + 3969 00c0 6364 str r3, [r4, #68] +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3970 .loc 1 1995 9 is_stmt 1 view .LVU1313 +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3971 .loc 1 1995 9 view .LVU1314 + 3972 00c2 84F84020 strb r2, [r4, #64] +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3973 .loc 1 1995 9 view .LVU1315 +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3974 .loc 1 1997 9 view .LVU1316 +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 3975 .loc 1 1997 16 is_stmt 0 view .LVU1317 + 3976 00c6 0120 movs r0, #1 + 3977 00c8 30E0 b .L261 + 3978 .LVL237: + 3979 .L274: +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3980 .loc 1 2004 9 is_stmt 1 view .LVU1318 + 3981 00ca 1F4B ldr r3, .L275+16 + 3982 00cc 0093 str r3, [sp] + 3983 00ce 3346 mov r3, r6 + 3984 00d0 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3985 00d4 2946 mov r1, r5 + 3986 00d6 2046 mov r0, r4 + 3987 .LVL238: +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3988 .loc 1 2004 9 is_stmt 0 view .LVU1319 + 3989 00d8 FFF7FEFF bl I2C_TransferConfig + 3990 .LVL239: +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3991 .loc 1 2007 9 is_stmt 1 view .LVU1320 +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3992 .loc 1 2007 25 is_stmt 0 view .LVU1321 + 3993 00dc 638D ldrh r3, [r4, #42] + 3994 00de 9BB2 uxth r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 208 + + +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3995 .loc 1 2007 32 view .LVU1322 + 3996 00e0 228D ldrh r2, [r4, #40] +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 3997 .loc 1 2007 25 view .LVU1323 + 3998 00e2 9B1A subs r3, r3, r2 + 3999 00e4 9BB2 uxth r3, r3 + 4000 00e6 6385 strh r3, [r4, #42] @ movhi +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4001 .loc 1 2010 9 is_stmt 1 view .LVU1324 +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4002 .loc 1 2010 9 view .LVU1325 + 4003 00e8 0023 movs r3, #0 + 4004 00ea 84F84030 strb r3, [r4, #64] +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4005 .loc 1 2010 9 view .LVU1326 +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4006 .loc 1 2016 9 view .LVU1327 + 4007 00ee 1021 movs r1, #16 + 4008 00f0 2046 mov r0, r4 + 4009 00f2 FFF7FEFF bl I2C_Enable_IRQ + 4010 .LVL240: +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4011 .loc 1 2019 9 view .LVU1328 +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4012 .loc 1 2019 13 is_stmt 0 view .LVU1329 + 4013 00f6 2268 ldr r2, [r4] +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4014 .loc 1 2019 29 view .LVU1330 + 4015 00f8 1368 ldr r3, [r2] + 4016 00fa 43F40043 orr r3, r3, #32768 + 4017 00fe 1360 str r3, [r2] + 4018 0100 11E0 b .L268 + 4019 .LVL241: + 4020 .L264: +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4021 .loc 1 2039 7 is_stmt 1 view .LVU1331 +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4022 .loc 1 2039 21 is_stmt 0 view .LVU1332 + 4023 0102 124B ldr r3, .L275+20 + 4024 0104 6363 str r3, [r4, #52] +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4025 .loc 1 2043 7 is_stmt 1 view .LVU1333 + 4026 0106 104B ldr r3, .L275+16 + 4027 0108 0093 str r3, [sp] + 4028 010a 4FF00073 mov r3, #33554432 + 4029 010e CAB2 uxtb r2, r1 + 4030 .LVL242: +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4031 .loc 1 2043 7 is_stmt 0 view .LVU1334 + 4032 0110 2946 mov r1, r5 + 4033 0112 2046 mov r0, r4 + 4034 0114 FFF7FEFF bl I2C_TransferConfig + 4035 .LVL243: +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4036 .loc 1 2046 7 is_stmt 1 view .LVU1335 +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 209 + + + 4037 .loc 1 2046 7 view .LVU1336 + 4038 0118 0023 movs r3, #0 + 4039 011a 84F84030 strb r3, [r4, #64] +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4040 .loc 1 2046 7 view .LVU1337 +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4041 .loc 1 2054 7 view .LVU1338 + 4042 011e 0121 movs r1, #1 + 4043 0120 2046 mov r0, r4 + 4044 0122 FFF7FEFF bl I2C_Enable_IRQ + 4045 .LVL244: + 4046 .L268: +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4047 .loc 1 2057 5 view .LVU1339 +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4048 .loc 1 2057 12 is_stmt 0 view .LVU1340 + 4049 0126 0020 movs r0, #0 + 4050 0128 00E0 b .L261 + 4051 .LVL245: + 4052 .L269: +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4053 .loc 1 2061 12 view .LVU1341 + 4054 012a 0220 movs r0, #2 + 4055 .LVL246: + 4056 .L261: +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4057 .loc 1 2063 1 view .LVU1342 + 4058 012c 02B0 add sp, sp, #8 + 4059 .LCFI51: + 4060 .cfi_remember_state + 4061 .cfi_def_cfa_offset 16 + 4062 @ sp needed + 4063 012e 70BD pop {r4, r5, r6, pc} + 4064 .LVL247: + 4065 .L270: + 4066 .LCFI52: + 4067 .cfi_restore_state +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4068 .loc 1 1941 14 view .LVU1343 + 4069 0130 0220 movs r0, #2 + 4070 0132 FBE7 b .L261 + 4071 .L271: +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4072 .loc 1 1945 5 view .LVU1344 + 4073 0134 0220 movs r0, #2 + 4074 0136 F9E7 b .L261 + 4075 .L276: + 4076 .align 2 + 4077 .L275: + 4078 0138 0000FFFF .word -65536 + 4079 013c 00000000 .word I2C_Master_ISR_DMA + 4080 0140 00000000 .word I2C_DMAMasterReceiveCplt + 4081 0144 00000000 .word I2C_DMAError + 4082 0148 00240080 .word -2147474432 + 4083 014c 00000000 .word I2C_Master_ISR_IT + 4084 .cfi_endproc + 4085 .LFE154: + ARM GAS /tmp/ccEimIdZ.s page 210 + + + 4087 .section .text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits + 4088 .align 1 + 4089 .global HAL_I2C_Slave_Transmit_DMA + 4090 .syntax unified + 4091 .thumb + 4092 .thumb_func + 4093 .fpu fpv5-d16 + 4095 HAL_I2C_Slave_Transmit_DMA: + 4096 .LVL248: + 4097 .LFB155: +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4098 .loc 1 2074 1 is_stmt 1 view -0 + 4099 .cfi_startproc + 4100 @ args = 0, pretend = 0, frame = 0 + 4101 @ frame_needed = 0, uses_anonymous_args = 0 +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4102 .loc 1 2074 1 is_stmt 0 view .LVU1346 + 4103 0000 38B5 push {r3, r4, r5, lr} + 4104 .LCFI53: + 4105 .cfi_def_cfa_offset 16 + 4106 .cfi_offset 3, -16 + 4107 .cfi_offset 4, -12 + 4108 .cfi_offset 5, -8 + 4109 .cfi_offset 14, -4 +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4110 .loc 1 2075 3 is_stmt 1 view .LVU1347 +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4111 .loc 1 2077 3 view .LVU1348 +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4112 .loc 1 2077 11 is_stmt 0 view .LVU1349 + 4113 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 4114 0006 DBB2 uxtb r3, r3 +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4115 .loc 1 2077 6 view .LVU1350 + 4116 0008 202B cmp r3, #32 + 4117 000a 63D1 bne .L283 + 4118 000c 0446 mov r4, r0 +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4119 .loc 1 2079 5 is_stmt 1 view .LVU1351 +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4120 .loc 1 2079 8 is_stmt 0 view .LVU1352 + 4121 000e 002A cmp r2, #0 + 4122 0010 18BF it ne + 4123 0012 0029 cmpne r1, #0 + 4124 0014 38D0 beq .L287 +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4125 .loc 1 2085 5 is_stmt 1 view .LVU1353 +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4126 .loc 1 2085 5 view .LVU1354 + 4127 0016 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4128 001a 012B cmp r3, #1 + 4129 001c 5DD0 beq .L284 +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4130 .loc 1 2085 5 discriminator 2 view .LVU1355 + 4131 001e 0123 movs r3, #1 + 4132 0020 80F84030 strb r3, [r0, #64] +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 211 + + + 4133 .loc 1 2085 5 discriminator 2 view .LVU1356 +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4134 .loc 1 2087 5 discriminator 2 view .LVU1357 +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4135 .loc 1 2087 23 is_stmt 0 discriminator 2 view .LVU1358 + 4136 0024 2123 movs r3, #33 + 4137 0026 80F84130 strb r3, [r0, #65] +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4138 .loc 1 2088 5 is_stmt 1 discriminator 2 view .LVU1359 +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4139 .loc 1 2088 23 is_stmt 0 discriminator 2 view .LVU1360 + 4140 002a 2023 movs r3, #32 + 4141 002c 80F84230 strb r3, [r0, #66] +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4142 .loc 1 2089 5 is_stmt 1 discriminator 2 view .LVU1361 +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4143 .loc 1 2089 23 is_stmt 0 discriminator 2 view .LVU1362 + 4144 0030 0023 movs r3, #0 + 4145 0032 4364 str r3, [r0, #68] +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4146 .loc 1 2092 5 is_stmt 1 discriminator 2 view .LVU1363 +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4147 .loc 1 2092 23 is_stmt 0 discriminator 2 view .LVU1364 + 4148 0034 4162 str r1, [r0, #36] +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4149 .loc 1 2093 5 is_stmt 1 discriminator 2 view .LVU1365 +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4150 .loc 1 2093 23 is_stmt 0 discriminator 2 view .LVU1366 + 4151 0036 4285 strh r2, [r0, #42] @ movhi +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4152 .loc 1 2094 5 is_stmt 1 discriminator 2 view .LVU1367 +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4153 .loc 1 2094 29 is_stmt 0 discriminator 2 view .LVU1368 + 4154 0038 438D ldrh r3, [r0, #42] +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4155 .loc 1 2094 23 discriminator 2 view .LVU1369 + 4156 003a 0385 strh r3, [r0, #40] @ movhi +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4157 .loc 1 2095 5 is_stmt 1 discriminator 2 view .LVU1370 +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4158 .loc 1 2095 23 is_stmt 0 discriminator 2 view .LVU1371 + 4159 003c 284B ldr r3, .L289 + 4160 003e C362 str r3, [r0, #44] +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4161 .loc 1 2096 5 is_stmt 1 discriminator 2 view .LVU1372 +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4162 .loc 1 2096 23 is_stmt 0 discriminator 2 view .LVU1373 + 4163 0040 284B ldr r3, .L289+4 + 4164 0042 4363 str r3, [r0, #52] +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4165 .loc 1 2098 5 is_stmt 1 discriminator 2 view .LVU1374 +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4166 .loc 1 2098 13 is_stmt 0 discriminator 2 view .LVU1375 + 4167 0044 836B ldr r3, [r0, #56] +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4168 .loc 1 2098 8 discriminator 2 view .LVU1376 + 4169 0046 23B3 cbz r3, .L280 + ARM GAS /tmp/ccEimIdZ.s page 212 + + +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4170 .loc 1 2101 7 is_stmt 1 view .LVU1377 +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4171 .loc 1 2101 38 is_stmt 0 view .LVU1378 + 4172 0048 274A ldr r2, .L289+8 + 4173 .LVL249: +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4174 .loc 1 2101 38 view .LVU1379 + 4175 004a DA63 str r2, [r3, #60] +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4176 .loc 1 2104 7 is_stmt 1 view .LVU1380 +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4177 .loc 1 2104 11 is_stmt 0 view .LVU1381 + 4178 004c 836B ldr r3, [r0, #56] +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4179 .loc 1 2104 39 view .LVU1382 + 4180 004e 274A ldr r2, .L289+12 + 4181 0050 DA64 str r2, [r3, #76] +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4182 .loc 1 2107 7 is_stmt 1 view .LVU1383 +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4183 .loc 1 2107 11 is_stmt 0 view .LVU1384 + 4184 0052 826B ldr r2, [r0, #56] +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4185 .loc 1 2107 42 view .LVU1385 + 4186 0054 0023 movs r3, #0 + 4187 0056 1364 str r3, [r2, #64] +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4188 .loc 1 2108 7 is_stmt 1 view .LVU1386 +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4189 .loc 1 2108 11 is_stmt 0 view .LVU1387 + 4190 0058 826B ldr r2, [r0, #56] +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4191 .loc 1 2108 39 view .LVU1388 + 4192 005a 1365 str r3, [r2, #80] +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4193 .loc 1 2111 7 is_stmt 1 view .LVU1389 +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4194 .loc 1 2111 86 is_stmt 0 view .LVU1390 + 4195 005c 0268 ldr r2, [r0] +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4196 .loc 1 2111 23 view .LVU1391 + 4197 005e 038D ldrh r3, [r0, #40] + 4198 0060 2832 adds r2, r2, #40 + 4199 0062 806B ldr r0, [r0, #56] + 4200 .LVL250: +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4201 .loc 1 2111 23 view .LVU1392 + 4202 0064 FFF7FEFF bl HAL_DMA_Start_IT + 4203 .LVL251: +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4204 .loc 1 2128 5 is_stmt 1 view .LVU1393 +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4205 .loc 1 2128 8 is_stmt 0 view .LVU1394 + 4206 0068 0546 mov r5, r0 + 4207 006a 00B3 cbz r0, .L288 +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccEimIdZ.s page 213 + + + 4208 .loc 1 2148 7 is_stmt 1 view .LVU1395 +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4209 .loc 1 2148 23 is_stmt 0 view .LVU1396 + 4210 006c 2823 movs r3, #40 + 4211 006e 84F84130 strb r3, [r4, #65] +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4212 .loc 1 2149 7 is_stmt 1 view .LVU1397 +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4213 .loc 1 2149 23 is_stmt 0 view .LVU1398 + 4214 0072 0022 movs r2, #0 + 4215 0074 84F84220 strb r2, [r4, #66] +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4216 .loc 1 2152 7 is_stmt 1 view .LVU1399 +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4217 .loc 1 2152 23 is_stmt 0 view .LVU1400 + 4218 0078 636C ldr r3, [r4, #68] + 4219 007a 43F01003 orr r3, r3, #16 + 4220 007e 6364 str r3, [r4, #68] +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4221 .loc 1 2155 7 is_stmt 1 view .LVU1401 +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4222 .loc 1 2155 7 view .LVU1402 + 4223 0080 84F84020 strb r2, [r4, #64] +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4224 .loc 1 2155 7 view .LVU1403 +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4225 .loc 1 2157 7 view .LVU1404 +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4226 .loc 1 2157 14 is_stmt 0 view .LVU1405 + 4227 0084 0125 movs r5, #1 + 4228 0086 26E0 b .L278 + 4229 .LVL252: + 4230 .L287: +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4231 .loc 1 2081 7 is_stmt 1 view .LVU1406 +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4232 .loc 1 2081 23 is_stmt 0 view .LVU1407 + 4233 0088 4FF40073 mov r3, #512 + 4234 008c 4364 str r3, [r0, #68] +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4235 .loc 1 2082 7 is_stmt 1 view .LVU1408 +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4236 .loc 1 2082 15 is_stmt 0 view .LVU1409 + 4237 008e 0125 movs r5, #1 + 4238 0090 21E0 b .L278 + 4239 .L280: +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4240 .loc 1 2116 7 is_stmt 1 view .LVU1410 +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4241 .loc 1 2116 23 is_stmt 0 view .LVU1411 + 4242 0092 2823 movs r3, #40 + 4243 0094 80F84130 strb r3, [r0, #65] +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4244 .loc 1 2117 7 is_stmt 1 view .LVU1412 +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4245 .loc 1 2117 23 is_stmt 0 view .LVU1413 + 4246 0098 0022 movs r2, #0 + ARM GAS /tmp/ccEimIdZ.s page 214 + + + 4247 .LVL253: +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4248 .loc 1 2117 23 view .LVU1414 + 4249 009a 80F84220 strb r2, [r0, #66] +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4250 .loc 1 2120 7 is_stmt 1 view .LVU1415 +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4251 .loc 1 2120 23 is_stmt 0 view .LVU1416 + 4252 009e 436C ldr r3, [r0, #68] + 4253 00a0 43F08003 orr r3, r3, #128 + 4254 00a4 4364 str r3, [r0, #68] +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4255 .loc 1 2123 7 is_stmt 1 view .LVU1417 +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4256 .loc 1 2123 7 view .LVU1418 + 4257 00a6 80F84020 strb r2, [r0, #64] +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4258 .loc 1 2123 7 view .LVU1419 +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4259 .loc 1 2125 7 view .LVU1420 +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4260 .loc 1 2125 14 is_stmt 0 view .LVU1421 + 4261 00aa 0125 movs r5, #1 + 4262 00ac 13E0 b .L278 + 4263 .LVL254: + 4264 .L288: +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4265 .loc 1 2131 7 is_stmt 1 view .LVU1422 +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4266 .loc 1 2131 11 is_stmt 0 view .LVU1423 + 4267 00ae 2268 ldr r2, [r4] +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4268 .loc 1 2131 27 view .LVU1424 + 4269 00b0 5368 ldr r3, [r2, #4] + 4270 00b2 23F40043 bic r3, r3, #32768 + 4271 00b6 5360 str r3, [r2, #4] +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4272 .loc 1 2134 7 is_stmt 1 view .LVU1425 +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4273 .loc 1 2134 7 view .LVU1426 + 4274 00b8 0023 movs r3, #0 + 4275 00ba 84F84030 strb r3, [r4, #64] +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4276 .loc 1 2134 7 view .LVU1427 +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4277 .loc 1 2140 7 view .LVU1428 + 4278 00be 4FF40041 mov r1, #32768 + 4279 00c2 2046 mov r0, r4 + 4280 .LVL255: +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4281 .loc 1 2140 7 is_stmt 0 view .LVU1429 + 4282 00c4 FFF7FEFF bl I2C_Enable_IRQ + 4283 .LVL256: +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4284 .loc 1 2143 7 is_stmt 1 view .LVU1430 +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4285 .loc 1 2143 11 is_stmt 0 view .LVU1431 + ARM GAS /tmp/ccEimIdZ.s page 215 + + + 4286 00c8 2268 ldr r2, [r4] +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4287 .loc 1 2143 27 view .LVU1432 + 4288 00ca 1368 ldr r3, [r2] + 4289 00cc 43F48043 orr r3, r3, #16384 + 4290 00d0 1360 str r3, [r2] +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4291 .loc 1 2160 5 is_stmt 1 view .LVU1433 +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4292 .loc 1 2160 12 is_stmt 0 view .LVU1434 + 4293 00d2 00E0 b .L278 + 4294 .LVL257: + 4295 .L283: +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4296 .loc 1 2164 12 view .LVU1435 + 4297 00d4 0225 movs r5, #2 + 4298 .LVL258: + 4299 .L278: +2166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4300 .loc 1 2166 1 view .LVU1436 + 4301 00d6 2846 mov r0, r5 + 4302 00d8 38BD pop {r3, r4, r5, pc} + 4303 .LVL259: + 4304 .L284: +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4305 .loc 1 2085 5 view .LVU1437 + 4306 00da 0225 movs r5, #2 + 4307 00dc FBE7 b .L278 + 4308 .L290: + 4309 00de 00BF .align 2 + 4310 .L289: + 4311 00e0 0000FFFF .word -65536 + 4312 00e4 00000000 .word I2C_Slave_ISR_DMA + 4313 00e8 00000000 .word I2C_DMASlaveTransmitCplt + 4314 00ec 00000000 .word I2C_DMAError + 4315 .cfi_endproc + 4316 .LFE155: + 4318 .section .text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits + 4319 .align 1 + 4320 .global HAL_I2C_Slave_Receive_DMA + 4321 .syntax unified + 4322 .thumb + 4323 .thumb_func + 4324 .fpu fpv5-d16 + 4326 HAL_I2C_Slave_Receive_DMA: + 4327 .LVL260: + 4328 .LFB156: +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4329 .loc 1 2177 1 is_stmt 1 view -0 + 4330 .cfi_startproc + 4331 @ args = 0, pretend = 0, frame = 0 + 4332 @ frame_needed = 0, uses_anonymous_args = 0 +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4333 .loc 1 2177 1 is_stmt 0 view .LVU1439 + 4334 0000 38B5 push {r3, r4, r5, lr} + 4335 .LCFI54: + 4336 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccEimIdZ.s page 216 + + + 4337 .cfi_offset 3, -16 + 4338 .cfi_offset 4, -12 + 4339 .cfi_offset 5, -8 + 4340 .cfi_offset 14, -4 +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4341 .loc 1 2178 3 is_stmt 1 view .LVU1440 +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4342 .loc 1 2180 3 view .LVU1441 +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4343 .loc 1 2180 11 is_stmt 0 view .LVU1442 + 4344 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 4345 0006 DBB2 uxtb r3, r3 +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4346 .loc 1 2180 6 view .LVU1443 + 4347 0008 202B cmp r3, #32 + 4348 000a 65D1 bne .L297 + 4349 000c 0446 mov r4, r0 +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4350 .loc 1 2182 5 is_stmt 1 view .LVU1444 +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4351 .loc 1 2182 8 is_stmt 0 view .LVU1445 + 4352 000e 002A cmp r2, #0 + 4353 0010 18BF it ne + 4354 0012 0029 cmpne r1, #0 + 4355 0014 3AD0 beq .L301 +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4356 .loc 1 2188 5 is_stmt 1 view .LVU1446 +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4357 .loc 1 2188 5 view .LVU1447 + 4358 0016 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4359 001a 012B cmp r3, #1 + 4360 001c 5FD0 beq .L298 +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4361 .loc 1 2188 5 discriminator 2 view .LVU1448 + 4362 001e 0123 movs r3, #1 + 4363 0020 80F84030 strb r3, [r0, #64] +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4364 .loc 1 2188 5 discriminator 2 view .LVU1449 +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4365 .loc 1 2190 5 discriminator 2 view .LVU1450 +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4366 .loc 1 2190 23 is_stmt 0 discriminator 2 view .LVU1451 + 4367 0024 2223 movs r3, #34 + 4368 0026 80F84130 strb r3, [r0, #65] +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4369 .loc 1 2191 5 is_stmt 1 discriminator 2 view .LVU1452 +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4370 .loc 1 2191 23 is_stmt 0 discriminator 2 view .LVU1453 + 4371 002a 2023 movs r3, #32 + 4372 002c 80F84230 strb r3, [r0, #66] +2192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4373 .loc 1 2192 5 is_stmt 1 discriminator 2 view .LVU1454 +2192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4374 .loc 1 2192 23 is_stmt 0 discriminator 2 view .LVU1455 + 4375 0030 0023 movs r3, #0 + 4376 0032 4364 str r3, [r0, #68] +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + ARM GAS /tmp/ccEimIdZ.s page 217 + + + 4377 .loc 1 2195 5 is_stmt 1 discriminator 2 view .LVU1456 +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4378 .loc 1 2195 23 is_stmt 0 discriminator 2 view .LVU1457 + 4379 0034 4162 str r1, [r0, #36] +2196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4380 .loc 1 2196 5 is_stmt 1 discriminator 2 view .LVU1458 +2196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4381 .loc 1 2196 23 is_stmt 0 discriminator 2 view .LVU1459 + 4382 0036 4285 strh r2, [r0, #42] @ movhi +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4383 .loc 1 2197 5 is_stmt 1 discriminator 2 view .LVU1460 +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4384 .loc 1 2197 29 is_stmt 0 discriminator 2 view .LVU1461 + 4385 0038 438D ldrh r3, [r0, #42] +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4386 .loc 1 2197 23 discriminator 2 view .LVU1462 + 4387 003a 0385 strh r3, [r0, #40] @ movhi +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4388 .loc 1 2198 5 is_stmt 1 discriminator 2 view .LVU1463 +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4389 .loc 1 2198 23 is_stmt 0 discriminator 2 view .LVU1464 + 4390 003c 294B ldr r3, .L303 + 4391 003e C362 str r3, [r0, #44] +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4392 .loc 1 2199 5 is_stmt 1 discriminator 2 view .LVU1465 +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4393 .loc 1 2199 23 is_stmt 0 discriminator 2 view .LVU1466 + 4394 0040 294B ldr r3, .L303+4 + 4395 0042 4363 str r3, [r0, #52] +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4396 .loc 1 2201 5 is_stmt 1 discriminator 2 view .LVU1467 +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4397 .loc 1 2201 13 is_stmt 0 discriminator 2 view .LVU1468 + 4398 0044 C36B ldr r3, [r0, #60] +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4399 .loc 1 2201 8 discriminator 2 view .LVU1469 + 4400 0046 33B3 cbz r3, .L294 +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4401 .loc 1 2204 7 is_stmt 1 view .LVU1470 +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4402 .loc 1 2204 38 is_stmt 0 view .LVU1471 + 4403 0048 284A ldr r2, .L303+8 + 4404 .LVL261: +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4405 .loc 1 2204 38 view .LVU1472 + 4406 004a DA63 str r2, [r3, #60] +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4407 .loc 1 2207 7 is_stmt 1 view .LVU1473 +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4408 .loc 1 2207 11 is_stmt 0 view .LVU1474 + 4409 004c C36B ldr r3, [r0, #60] +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4410 .loc 1 2207 39 view .LVU1475 + 4411 004e 284A ldr r2, .L303+12 + 4412 0050 DA64 str r2, [r3, #76] +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4413 .loc 1 2210 7 is_stmt 1 view .LVU1476 + ARM GAS /tmp/ccEimIdZ.s page 218 + + +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4414 .loc 1 2210 11 is_stmt 0 view .LVU1477 + 4415 0052 C26B ldr r2, [r0, #60] +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4416 .loc 1 2210 42 view .LVU1478 + 4417 0054 0023 movs r3, #0 + 4418 0056 1364 str r3, [r2, #64] +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4419 .loc 1 2211 7 is_stmt 1 view .LVU1479 +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4420 .loc 1 2211 11 is_stmt 0 view .LVU1480 + 4421 0058 C26B ldr r2, [r0, #60] +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4422 .loc 1 2211 39 view .LVU1481 + 4423 005a 1365 str r3, [r2, #80] +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4424 .loc 1 2214 7 is_stmt 1 view .LVU1482 +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4425 .loc 1 2214 69 is_stmt 0 view .LVU1483 + 4426 005c 0068 ldr r0, [r0] + 4427 .LVL262: +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4428 .loc 1 2214 23 view .LVU1484 + 4429 005e 238D ldrh r3, [r4, #40] + 4430 0060 0A46 mov r2, r1 + 4431 0062 00F12401 add r1, r0, #36 + 4432 .LVL263: +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4433 .loc 1 2214 23 view .LVU1485 + 4434 0066 E06B ldr r0, [r4, #60] + 4435 0068 FFF7FEFF bl HAL_DMA_Start_IT + 4436 .LVL264: +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4437 .loc 1 2231 5 is_stmt 1 view .LVU1486 +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4438 .loc 1 2231 8 is_stmt 0 view .LVU1487 + 4439 006c 0546 mov r5, r0 + 4440 006e 00B3 cbz r0, .L302 +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4441 .loc 1 2251 7 is_stmt 1 view .LVU1488 +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4442 .loc 1 2251 23 is_stmt 0 view .LVU1489 + 4443 0070 2823 movs r3, #40 + 4444 0072 84F84130 strb r3, [r4, #65] +2252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4445 .loc 1 2252 7 is_stmt 1 view .LVU1490 +2252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4446 .loc 1 2252 23 is_stmt 0 view .LVU1491 + 4447 0076 0022 movs r2, #0 + 4448 0078 84F84220 strb r2, [r4, #66] +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4449 .loc 1 2255 7 is_stmt 1 view .LVU1492 +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4450 .loc 1 2255 23 is_stmt 0 view .LVU1493 + 4451 007c 636C ldr r3, [r4, #68] + 4452 007e 43F01003 orr r3, r3, #16 + 4453 0082 6364 str r3, [r4, #68] + ARM GAS /tmp/ccEimIdZ.s page 219 + + +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4454 .loc 1 2258 7 is_stmt 1 view .LVU1494 +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4455 .loc 1 2258 7 view .LVU1495 + 4456 0084 84F84020 strb r2, [r4, #64] +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4457 .loc 1 2258 7 view .LVU1496 +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4458 .loc 1 2260 7 view .LVU1497 +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4459 .loc 1 2260 14 is_stmt 0 view .LVU1498 + 4460 0088 0125 movs r5, #1 + 4461 008a 26E0 b .L292 + 4462 .LVL265: + 4463 .L301: +2184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4464 .loc 1 2184 7 is_stmt 1 view .LVU1499 +2184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4465 .loc 1 2184 23 is_stmt 0 view .LVU1500 + 4466 008c 4FF40073 mov r3, #512 + 4467 0090 4364 str r3, [r0, #68] +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4468 .loc 1 2185 7 is_stmt 1 view .LVU1501 +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4469 .loc 1 2185 15 is_stmt 0 view .LVU1502 + 4470 0092 0125 movs r5, #1 + 4471 0094 21E0 b .L292 + 4472 .L294: +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4473 .loc 1 2219 7 is_stmt 1 view .LVU1503 +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4474 .loc 1 2219 23 is_stmt 0 view .LVU1504 + 4475 0096 2823 movs r3, #40 + 4476 0098 80F84130 strb r3, [r0, #65] +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4477 .loc 1 2220 7 is_stmt 1 view .LVU1505 +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4478 .loc 1 2220 23 is_stmt 0 view .LVU1506 + 4479 009c 0022 movs r2, #0 + 4480 .LVL266: +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4481 .loc 1 2220 23 view .LVU1507 + 4482 009e 80F84220 strb r2, [r0, #66] +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4483 .loc 1 2223 7 is_stmt 1 view .LVU1508 +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4484 .loc 1 2223 23 is_stmt 0 view .LVU1509 + 4485 00a2 436C ldr r3, [r0, #68] + 4486 00a4 43F08003 orr r3, r3, #128 + 4487 00a8 4364 str r3, [r0, #68] +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4488 .loc 1 2226 7 is_stmt 1 view .LVU1510 +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4489 .loc 1 2226 7 view .LVU1511 + 4490 00aa 80F84020 strb r2, [r0, #64] +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4491 .loc 1 2226 7 view .LVU1512 + ARM GAS /tmp/ccEimIdZ.s page 220 + + +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4492 .loc 1 2228 7 view .LVU1513 +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4493 .loc 1 2228 14 is_stmt 0 view .LVU1514 + 4494 00ae 0125 movs r5, #1 + 4495 00b0 13E0 b .L292 + 4496 .LVL267: + 4497 .L302: +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4498 .loc 1 2234 7 is_stmt 1 view .LVU1515 +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4499 .loc 1 2234 11 is_stmt 0 view .LVU1516 + 4500 00b2 2268 ldr r2, [r4] +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4501 .loc 1 2234 27 view .LVU1517 + 4502 00b4 5368 ldr r3, [r2, #4] + 4503 00b6 23F40043 bic r3, r3, #32768 + 4504 00ba 5360 str r3, [r2, #4] +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4505 .loc 1 2237 7 is_stmt 1 view .LVU1518 +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4506 .loc 1 2237 7 view .LVU1519 + 4507 00bc 0023 movs r3, #0 + 4508 00be 84F84030 strb r3, [r4, #64] +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4509 .loc 1 2237 7 view .LVU1520 +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4510 .loc 1 2243 7 view .LVU1521 + 4511 00c2 4FF40041 mov r1, #32768 + 4512 00c6 2046 mov r0, r4 + 4513 .LVL268: +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4514 .loc 1 2243 7 is_stmt 0 view .LVU1522 + 4515 00c8 FFF7FEFF bl I2C_Enable_IRQ + 4516 .LVL269: +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4517 .loc 1 2246 7 is_stmt 1 view .LVU1523 +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4518 .loc 1 2246 11 is_stmt 0 view .LVU1524 + 4519 00cc 2268 ldr r2, [r4] +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4520 .loc 1 2246 27 view .LVU1525 + 4521 00ce 1368 ldr r3, [r2] + 4522 00d0 43F40043 orr r3, r3, #32768 + 4523 00d4 1360 str r3, [r2] +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4524 .loc 1 2263 5 is_stmt 1 view .LVU1526 +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4525 .loc 1 2263 12 is_stmt 0 view .LVU1527 + 4526 00d6 00E0 b .L292 + 4527 .LVL270: + 4528 .L297: +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4529 .loc 1 2267 12 view .LVU1528 + 4530 00d8 0225 movs r5, #2 + 4531 .LVL271: + 4532 .L292: + ARM GAS /tmp/ccEimIdZ.s page 221 + + +2269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 4533 .loc 1 2269 1 view .LVU1529 + 4534 00da 2846 mov r0, r5 + 4535 00dc 38BD pop {r3, r4, r5, pc} + 4536 .LVL272: + 4537 .L298: +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4538 .loc 1 2188 5 view .LVU1530 + 4539 00de 0225 movs r5, #2 + 4540 00e0 FBE7 b .L292 + 4541 .L304: + 4542 00e2 00BF .align 2 + 4543 .L303: + 4544 00e4 0000FFFF .word -65536 + 4545 00e8 00000000 .word I2C_Slave_ISR_DMA + 4546 00ec 00000000 .word I2C_DMASlaveReceiveCplt + 4547 00f0 00000000 .word I2C_DMAError + 4548 .cfi_endproc + 4549 .LFE156: + 4551 .section .text.HAL_I2C_Mem_Write,"ax",%progbits + 4552 .align 1 + 4553 .global HAL_I2C_Mem_Write + 4554 .syntax unified + 4555 .thumb + 4556 .thumb_func + 4557 .fpu fpv5-d16 + 4559 HAL_I2C_Mem_Write: + 4560 .LVL273: + 4561 .LFB157: +2284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 4562 .loc 1 2284 1 is_stmt 1 view -0 + 4563 .cfi_startproc + 4564 @ args = 12, pretend = 0, frame = 0 + 4565 @ frame_needed = 0, uses_anonymous_args = 0 +2284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 4566 .loc 1 2284 1 is_stmt 0 view .LVU1532 + 4567 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 4568 .LCFI55: + 4569 .cfi_def_cfa_offset 36 + 4570 .cfi_offset 4, -36 + 4571 .cfi_offset 5, -32 + 4572 .cfi_offset 6, -28 + 4573 .cfi_offset 7, -24 + 4574 .cfi_offset 8, -20 + 4575 .cfi_offset 9, -16 + 4576 .cfi_offset 10, -12 + 4577 .cfi_offset 11, -8 + 4578 .cfi_offset 14, -4 + 4579 0004 83B0 sub sp, sp, #12 + 4580 .LCFI56: + 4581 .cfi_def_cfa_offset 48 + 4582 0006 0D46 mov r5, r1 + 4583 0008 BDF834A0 ldrh r10, [sp, #52] + 4584 000c 0E9F ldr r7, [sp, #56] +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4585 .loc 1 2285 3 is_stmt 1 view .LVU1533 +2288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 222 + + + 4586 .loc 1 2288 3 view .LVU1534 +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4587 .loc 1 2290 3 view .LVU1535 +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4588 .loc 1 2290 11 is_stmt 0 view .LVU1536 + 4589 000e 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 4590 .LVL274: +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4591 .loc 1 2290 11 view .LVU1537 + 4592 0012 C9B2 uxtb r1, r1 +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4593 .loc 1 2290 6 view .LVU1538 + 4594 0014 2029 cmp r1, #32 + 4595 0016 40F0BC80 bne .L314 + 4596 001a 0446 mov r4, r0 + 4597 001c 9046 mov r8, r2 + 4598 001e 9946 mov r9, r3 +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4599 .loc 1 2292 5 is_stmt 1 view .LVU1539 +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4600 .loc 1 2292 8 is_stmt 0 view .LVU1540 + 4601 0020 0C9B ldr r3, [sp, #48] + 4602 .LVL275: +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4603 .loc 1 2292 8 view .LVU1541 + 4604 0022 BAF1000F cmp r10, #0 + 4605 0026 18BF it ne + 4606 0028 002B cmpne r3, #0 + 4607 002a 16D0 beq .L321 +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4608 .loc 1 2299 5 is_stmt 1 view .LVU1542 +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4609 .loc 1 2299 5 view .LVU1543 + 4610 002c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4611 0030 012B cmp r3, #1 + 4612 0032 00F0B280 beq .L315 +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4613 .loc 1 2299 5 discriminator 2 view .LVU1544 + 4614 0036 4FF0010B mov fp, #1 + 4615 003a 80F840B0 strb fp, [r0, #64] +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4616 .loc 1 2299 5 discriminator 2 view .LVU1545 +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4617 .loc 1 2302 5 discriminator 2 view .LVU1546 +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4618 .loc 1 2302 17 is_stmt 0 discriminator 2 view .LVU1547 + 4619 003e FFF7FEFF bl HAL_GetTick + 4620 .LVL276: +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4621 .loc 1 2302 17 discriminator 2 view .LVU1548 + 4622 0042 0646 mov r6, r0 + 4623 .LVL277: +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4624 .loc 1 2304 5 is_stmt 1 discriminator 2 view .LVU1549 +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4625 .loc 1 2304 9 is_stmt 0 discriminator 2 view .LVU1550 + 4626 0044 0090 str r0, [sp] + ARM GAS /tmp/ccEimIdZ.s page 223 + + + 4627 0046 1923 movs r3, #25 + 4628 0048 5A46 mov r2, fp + 4629 004a 4FF40041 mov r1, #32768 + 4630 004e 2046 mov r0, r4 + 4631 .LVL278: +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4632 .loc 1 2304 9 discriminator 2 view .LVU1551 + 4633 0050 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4634 .LVL279: +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4635 .loc 1 2304 8 discriminator 2 view .LVU1552 + 4636 0054 30B1 cbz r0, .L322 +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4637 .loc 1 2306 14 view .LVU1553 + 4638 0056 0120 movs r0, #1 + 4639 0058 9CE0 b .L306 + 4640 .LVL280: + 4641 .L321: +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4642 .loc 1 2294 7 is_stmt 1 view .LVU1554 +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4643 .loc 1 2294 23 is_stmt 0 view .LVU1555 + 4644 005a 4FF40073 mov r3, #512 + 4645 005e 4364 str r3, [r0, #68] +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4646 .loc 1 2295 7 is_stmt 1 view .LVU1556 +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4647 .loc 1 2295 15 is_stmt 0 view .LVU1557 + 4648 0060 0120 movs r0, #1 + 4649 .LVL281: +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4650 .loc 1 2295 15 view .LVU1558 + 4651 0062 97E0 b .L306 + 4652 .LVL282: + 4653 .L322: +2309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4654 .loc 1 2309 5 is_stmt 1 view .LVU1559 +2309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4655 .loc 1 2309 21 is_stmt 0 view .LVU1560 + 4656 0064 2123 movs r3, #33 + 4657 0066 84F84130 strb r3, [r4, #65] +2310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4658 .loc 1 2310 5 is_stmt 1 view .LVU1561 +2310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4659 .loc 1 2310 21 is_stmt 0 view .LVU1562 + 4660 006a 4023 movs r3, #64 + 4661 006c 84F84230 strb r3, [r4, #66] +2311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4662 .loc 1 2311 5 is_stmt 1 view .LVU1563 +2311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4663 .loc 1 2311 21 is_stmt 0 view .LVU1564 + 4664 0070 0023 movs r3, #0 + 4665 0072 6364 str r3, [r4, #68] +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4666 .loc 1 2314 5 is_stmt 1 view .LVU1565 +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4667 .loc 1 2314 21 is_stmt 0 view .LVU1566 + ARM GAS /tmp/ccEimIdZ.s page 224 + + + 4668 0074 0C9A ldr r2, [sp, #48] + 4669 0076 6262 str r2, [r4, #36] +2315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4670 .loc 1 2315 5 is_stmt 1 view .LVU1567 +2315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4671 .loc 1 2315 21 is_stmt 0 view .LVU1568 + 4672 0078 A4F82AA0 strh r10, [r4, #42] @ movhi +2316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4673 .loc 1 2316 5 is_stmt 1 view .LVU1569 +2316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4674 .loc 1 2316 21 is_stmt 0 view .LVU1570 + 4675 007c 6363 str r3, [r4, #52] +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4676 .loc 1 2319 5 is_stmt 1 view .LVU1571 +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4677 .loc 1 2319 9 is_stmt 0 view .LVU1572 + 4678 007e 0196 str r6, [sp, #4] + 4679 0080 0097 str r7, [sp] + 4680 0082 4B46 mov r3, r9 + 4681 0084 4246 mov r2, r8 + 4682 0086 2946 mov r1, r5 + 4683 0088 2046 mov r0, r4 + 4684 008a FFF7FEFF bl I2C_RequestMemoryWrite + 4685 .LVL283: +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4686 .loc 1 2319 8 view .LVU1573 + 4687 008e 70B9 cbnz r0, .L323 +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4688 .loc 1 2327 5 is_stmt 1 view .LVU1574 +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4689 .loc 1 2327 13 is_stmt 0 view .LVU1575 + 4690 0090 638D ldrh r3, [r4, #42] + 4691 0092 9BB2 uxth r3, r3 +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4692 .loc 1 2327 8 view .LVU1576 + 4693 0094 FF2B cmp r3, #255 + 4694 0096 0FD9 bls .L309 +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 4695 .loc 1 2329 7 is_stmt 1 view .LVU1577 +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 4696 .loc 1 2329 22 is_stmt 0 view .LVU1578 + 4697 0098 FF22 movs r2, #255 + 4698 009a 2285 strh r2, [r4, #40] @ movhi +2330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4699 .loc 1 2330 7 is_stmt 1 view .LVU1579 + 4700 009c 0023 movs r3, #0 + 4701 009e 0093 str r3, [sp] + 4702 00a0 4FF08073 mov r3, #16777216 + 4703 00a4 2946 mov r1, r5 + 4704 00a6 2046 mov r0, r4 + 4705 00a8 FFF7FEFF bl I2C_TransferConfig + 4706 .LVL284: + 4707 00ac 21E0 b .L313 + 4708 .L323: +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4709 .loc 1 2322 7 view .LVU1580 +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccEimIdZ.s page 225 + + + 4710 .loc 1 2322 7 view .LVU1581 + 4711 00ae 0023 movs r3, #0 + 4712 00b0 84F84030 strb r3, [r4, #64] +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 4713 .loc 1 2322 7 view .LVU1582 +2323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4714 .loc 1 2323 7 view .LVU1583 +2323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4715 .loc 1 2323 14 is_stmt 0 view .LVU1584 + 4716 00b4 5846 mov r0, fp + 4717 00b6 6DE0 b .L306 + 4718 .L309: +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 4719 .loc 1 2334 7 is_stmt 1 view .LVU1585 +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 4720 .loc 1 2334 28 is_stmt 0 view .LVU1586 + 4721 00b8 628D ldrh r2, [r4, #42] + 4722 00ba 92B2 uxth r2, r2 +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 4723 .loc 1 2334 22 view .LVU1587 + 4724 00bc 2285 strh r2, [r4, #40] @ movhi +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4725 .loc 1 2335 7 is_stmt 1 view .LVU1588 + 4726 00be 0023 movs r3, #0 + 4727 00c0 0093 str r3, [sp] + 4728 00c2 4FF00073 mov r3, #33554432 + 4729 00c6 D2B2 uxtb r2, r2 + 4730 00c8 2946 mov r1, r5 + 4731 00ca 2046 mov r0, r4 + 4732 00cc FFF7FEFF bl I2C_TransferConfig + 4733 .LVL285: + 4734 00d0 0FE0 b .L313 + 4735 .L312: +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 4736 .loc 1 2370 11 view .LVU1589 +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 4737 .loc 1 2370 32 is_stmt 0 view .LVU1590 + 4738 00d2 628D ldrh r2, [r4, #42] + 4739 00d4 92B2 uxth r2, r2 +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 4740 .loc 1 2370 26 view .LVU1591 + 4741 00d6 2285 strh r2, [r4, #40] @ movhi +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4742 .loc 1 2371 11 is_stmt 1 view .LVU1592 + 4743 00d8 0023 movs r3, #0 + 4744 00da 0093 str r3, [sp] + 4745 00dc 4FF00073 mov r3, #33554432 + 4746 00e0 D2B2 uxtb r2, r2 + 4747 00e2 2946 mov r1, r5 + 4748 00e4 2046 mov r0, r4 + 4749 00e6 FFF7FEFF bl I2C_TransferConfig + 4750 .LVL286: + 4751 .L311: +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4752 .loc 1 2376 11 view .LVU1593 +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4753 .loc 1 2376 16 is_stmt 0 view .LVU1594 + ARM GAS /tmp/ccEimIdZ.s page 226 + + + 4754 00ea 638D ldrh r3, [r4, #42] + 4755 00ec 9BB2 uxth r3, r3 +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4756 .loc 1 2376 5 view .LVU1595 + 4757 00ee 002B cmp r3, #0 + 4758 00f0 33D0 beq .L324 + 4759 .L313: +2338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4760 .loc 1 2338 5 is_stmt 1 view .LVU1596 +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4761 .loc 1 2341 7 view .LVU1597 +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4762 .loc 1 2341 11 is_stmt 0 view .LVU1598 + 4763 00f2 3246 mov r2, r6 + 4764 00f4 3946 mov r1, r7 + 4765 00f6 2046 mov r0, r4 + 4766 00f8 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 4767 .LVL287: +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4768 .loc 1 2341 10 view .LVU1599 + 4769 00fc 0028 cmp r0, #0 + 4770 00fe 4ED1 bne .L317 +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4771 .loc 1 2347 7 is_stmt 1 view .LVU1600 +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4772 .loc 1 2347 35 is_stmt 0 view .LVU1601 + 4773 0100 626A ldr r2, [r4, #36] +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4774 .loc 1 2347 11 view .LVU1602 + 4775 0102 2368 ldr r3, [r4] +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4776 .loc 1 2347 30 view .LVU1603 + 4777 0104 1278 ldrb r2, [r2] @ zero_extendqisi2 +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4778 .loc 1 2347 28 view .LVU1604 + 4779 0106 9A62 str r2, [r3, #40] +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4780 .loc 1 2350 7 is_stmt 1 view .LVU1605 +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4781 .loc 1 2350 11 is_stmt 0 view .LVU1606 + 4782 0108 636A ldr r3, [r4, #36] +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4783 .loc 1 2350 21 view .LVU1607 + 4784 010a 0133 adds r3, r3, #1 + 4785 010c 6362 str r3, [r4, #36] +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 4786 .loc 1 2352 7 is_stmt 1 view .LVU1608 +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 4787 .loc 1 2352 11 is_stmt 0 view .LVU1609 + 4788 010e 638D ldrh r3, [r4, #42] + 4789 0110 9BB2 uxth r3, r3 +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 4790 .loc 1 2352 22 view .LVU1610 + 4791 0112 013B subs r3, r3, #1 + 4792 0114 9BB2 uxth r3, r3 + 4793 0116 6385 strh r3, [r4, #42] @ movhi +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 227 + + + 4794 .loc 1 2353 7 is_stmt 1 view .LVU1611 +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4795 .loc 1 2353 11 is_stmt 0 view .LVU1612 + 4796 0118 238D ldrh r3, [r4, #40] +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4797 .loc 1 2353 21 view .LVU1613 + 4798 011a 013B subs r3, r3, #1 + 4799 011c 9BB2 uxth r3, r3 + 4800 011e 2385 strh r3, [r4, #40] @ movhi +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4801 .loc 1 2355 7 is_stmt 1 view .LVU1614 +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4802 .loc 1 2355 16 is_stmt 0 view .LVU1615 + 4803 0120 628D ldrh r2, [r4, #42] + 4804 0122 92B2 uxth r2, r2 +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4805 .loc 1 2355 10 view .LVU1616 + 4806 0124 002A cmp r2, #0 + 4807 0126 E0D0 beq .L311 +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4808 .loc 1 2355 35 discriminator 1 view .LVU1617 + 4809 0128 002B cmp r3, #0 + 4810 012a DED1 bne .L311 +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4811 .loc 1 2358 9 is_stmt 1 view .LVU1618 +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4812 .loc 1 2358 13 is_stmt 0 view .LVU1619 + 4813 012c 0096 str r6, [sp] + 4814 012e 3B46 mov r3, r7 + 4815 0130 0022 movs r2, #0 + 4816 0132 8021 movs r1, #128 + 4817 0134 2046 mov r0, r4 + 4818 0136 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4819 .LVL288: +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4820 .loc 1 2358 12 view .LVU1620 + 4821 013a 90BB cbnz r0, .L318 +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4822 .loc 1 2363 9 is_stmt 1 view .LVU1621 +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4823 .loc 1 2363 17 is_stmt 0 view .LVU1622 + 4824 013c 638D ldrh r3, [r4, #42] + 4825 013e 9BB2 uxth r3, r3 +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4826 .loc 1 2363 12 view .LVU1623 + 4827 0140 FF2B cmp r3, #255 + 4828 0142 C6D9 bls .L312 +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA + 4829 .loc 1 2365 11 is_stmt 1 view .LVU1624 +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STA + 4830 .loc 1 2365 26 is_stmt 0 view .LVU1625 + 4831 0144 FF22 movs r2, #255 + 4832 0146 2285 strh r2, [r4, #40] @ movhi +2366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4833 .loc 1 2366 11 is_stmt 1 view .LVU1626 + 4834 0148 0023 movs r3, #0 + 4835 014a 0093 str r3, [sp] + ARM GAS /tmp/ccEimIdZ.s page 228 + + + 4836 014c 4FF08073 mov r3, #16777216 + 4837 0150 2946 mov r1, r5 + 4838 0152 2046 mov r0, r4 + 4839 0154 FFF7FEFF bl I2C_TransferConfig + 4840 .LVL289: + 4841 0158 C7E7 b .L311 + 4842 .L324: +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4843 .loc 1 2380 5 view .LVU1627 +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4844 .loc 1 2380 9 is_stmt 0 view .LVU1628 + 4845 015a 3246 mov r2, r6 + 4846 015c 3946 mov r1, r7 + 4847 015e 2046 mov r0, r4 + 4848 0160 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 4849 .LVL290: +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4850 .loc 1 2380 8 view .LVU1629 + 4851 0164 F8B9 cbnz r0, .L319 +2386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4852 .loc 1 2386 5 is_stmt 1 view .LVU1630 + 4853 0166 2368 ldr r3, [r4] + 4854 0168 2022 movs r2, #32 + 4855 016a DA61 str r2, [r3, #28] +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4856 .loc 1 2389 5 view .LVU1631 + 4857 016c 2168 ldr r1, [r4] + 4858 016e 4B68 ldr r3, [r1, #4] + 4859 0170 23F0FF73 bic r3, r3, #33423360 + 4860 0174 23F48B33 bic r3, r3, #71168 + 4861 0178 23F4FF73 bic r3, r3, #510 + 4862 017c 23F00103 bic r3, r3, #1 + 4863 0180 4B60 str r3, [r1, #4] +2391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4864 .loc 1 2391 5 view .LVU1632 +2391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4865 .loc 1 2391 17 is_stmt 0 view .LVU1633 + 4866 0182 84F84120 strb r2, [r4, #65] +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4867 .loc 1 2392 5 is_stmt 1 view .LVU1634 +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4868 .loc 1 2392 17 is_stmt 0 view .LVU1635 + 4869 0186 0023 movs r3, #0 + 4870 0188 84F84230 strb r3, [r4, #66] +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4871 .loc 1 2395 5 is_stmt 1 view .LVU1636 +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4872 .loc 1 2395 5 view .LVU1637 + 4873 018c 84F84030 strb r3, [r4, #64] +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4874 .loc 1 2395 5 view .LVU1638 +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4875 .loc 1 2397 5 view .LVU1639 +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4876 .loc 1 2397 12 is_stmt 0 view .LVU1640 + 4877 0190 00E0 b .L306 + 4878 .LVL291: + ARM GAS /tmp/ccEimIdZ.s page 229 + + + 4879 .L314: +2401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4880 .loc 1 2401 12 view .LVU1641 + 4881 0192 0220 movs r0, #2 + 4882 .LVL292: + 4883 .L306: +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4884 .loc 1 2403 1 view .LVU1642 + 4885 0194 03B0 add sp, sp, #12 + 4886 .LCFI57: + 4887 .cfi_remember_state + 4888 .cfi_def_cfa_offset 36 + 4889 @ sp needed + 4890 0196 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 4891 .LVL293: + 4892 .L315: + 4893 .LCFI58: + 4894 .cfi_restore_state +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4895 .loc 1 2299 5 view .LVU1643 + 4896 019a 0220 movs r0, #2 + 4897 .LVL294: +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4898 .loc 1 2299 5 view .LVU1644 + 4899 019c FAE7 b .L306 + 4900 .LVL295: + 4901 .L317: +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4902 .loc 1 2343 16 view .LVU1645 + 4903 019e 0120 movs r0, #1 + 4904 01a0 F8E7 b .L306 + 4905 .L318: +2360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4906 .loc 1 2360 18 view .LVU1646 + 4907 01a2 0120 movs r0, #1 + 4908 01a4 F6E7 b .L306 + 4909 .L319: +2382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 4910 .loc 1 2382 14 view .LVU1647 + 4911 01a6 0120 movs r0, #1 + 4912 01a8 F4E7 b .L306 + 4913 .cfi_endproc + 4914 .LFE157: + 4916 .section .text.HAL_I2C_Mem_Read,"ax",%progbits + 4917 .align 1 + 4918 .global HAL_I2C_Mem_Read + 4919 .syntax unified + 4920 .thumb + 4921 .thumb_func + 4922 .fpu fpv5-d16 + 4924 HAL_I2C_Mem_Read: + 4925 .LVL296: + 4926 .LFB158: +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 4927 .loc 1 2419 1 is_stmt 1 view -0 + 4928 .cfi_startproc + 4929 @ args = 12, pretend = 0, frame = 0 + ARM GAS /tmp/ccEimIdZ.s page 230 + + + 4930 @ frame_needed = 0, uses_anonymous_args = 0 +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 4931 .loc 1 2419 1 is_stmt 0 view .LVU1649 + 4932 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 4933 .LCFI59: + 4934 .cfi_def_cfa_offset 36 + 4935 .cfi_offset 4, -36 + 4936 .cfi_offset 5, -32 + 4937 .cfi_offset 6, -28 + 4938 .cfi_offset 7, -24 + 4939 .cfi_offset 8, -20 + 4940 .cfi_offset 9, -16 + 4941 .cfi_offset 10, -12 + 4942 .cfi_offset 11, -8 + 4943 .cfi_offset 14, -4 + 4944 0004 83B0 sub sp, sp, #12 + 4945 .LCFI60: + 4946 .cfi_def_cfa_offset 48 + 4947 0006 0D46 mov r5, r1 + 4948 0008 BDF834A0 ldrh r10, [sp, #52] + 4949 000c 0E9F ldr r7, [sp, #56] +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4950 .loc 1 2420 3 is_stmt 1 view .LVU1650 +2423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4951 .loc 1 2423 3 view .LVU1651 +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4952 .loc 1 2425 3 view .LVU1652 +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4953 .loc 1 2425 11 is_stmt 0 view .LVU1653 + 4954 000e 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 4955 .LVL297: +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4956 .loc 1 2425 11 view .LVU1654 + 4957 0012 C9B2 uxtb r1, r1 +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4958 .loc 1 2425 6 view .LVU1655 + 4959 0014 2029 cmp r1, #32 + 4960 0016 40F0BD80 bne .L334 + 4961 001a 0446 mov r4, r0 + 4962 001c 9046 mov r8, r2 + 4963 001e 9946 mov r9, r3 +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4964 .loc 1 2427 5 is_stmt 1 view .LVU1656 +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4965 .loc 1 2427 8 is_stmt 0 view .LVU1657 + 4966 0020 0C9B ldr r3, [sp, #48] + 4967 .LVL298: +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4968 .loc 1 2427 8 view .LVU1658 + 4969 0022 BAF1000F cmp r10, #0 + 4970 0026 18BF it ne + 4971 0028 002B cmpne r3, #0 + 4972 002a 16D0 beq .L341 +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4973 .loc 1 2434 5 is_stmt 1 view .LVU1659 +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4974 .loc 1 2434 5 view .LVU1660 + ARM GAS /tmp/ccEimIdZ.s page 231 + + + 4975 002c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4976 0030 012B cmp r3, #1 + 4977 0032 00F0B380 beq .L335 +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4978 .loc 1 2434 5 discriminator 2 view .LVU1661 + 4979 0036 4FF0010B mov fp, #1 + 4980 003a 80F840B0 strb fp, [r0, #64] +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4981 .loc 1 2434 5 discriminator 2 view .LVU1662 +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4982 .loc 1 2437 5 discriminator 2 view .LVU1663 +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4983 .loc 1 2437 17 is_stmt 0 discriminator 2 view .LVU1664 + 4984 003e FFF7FEFF bl HAL_GetTick + 4985 .LVL299: +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 4986 .loc 1 2437 17 discriminator 2 view .LVU1665 + 4987 0042 0646 mov r6, r0 + 4988 .LVL300: +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4989 .loc 1 2439 5 is_stmt 1 discriminator 2 view .LVU1666 +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4990 .loc 1 2439 9 is_stmt 0 discriminator 2 view .LVU1667 + 4991 0044 0090 str r0, [sp] + 4992 0046 1923 movs r3, #25 + 4993 0048 5A46 mov r2, fp + 4994 004a 4FF40041 mov r1, #32768 + 4995 004e 2046 mov r0, r4 + 4996 .LVL301: +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 4997 .loc 1 2439 9 discriminator 2 view .LVU1668 + 4998 0050 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4999 .LVL302: +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5000 .loc 1 2439 8 discriminator 2 view .LVU1669 + 5001 0054 30B1 cbz r0, .L342 +2441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5002 .loc 1 2441 14 view .LVU1670 + 5003 0056 0120 movs r0, #1 + 5004 0058 9DE0 b .L326 + 5005 .LVL303: + 5006 .L341: +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5007 .loc 1 2429 7 is_stmt 1 view .LVU1671 +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5008 .loc 1 2429 23 is_stmt 0 view .LVU1672 + 5009 005a 4FF40073 mov r3, #512 + 5010 005e 4364 str r3, [r0, #68] +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5011 .loc 1 2430 7 is_stmt 1 view .LVU1673 +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5012 .loc 1 2430 15 is_stmt 0 view .LVU1674 + 5013 0060 0120 movs r0, #1 + 5014 .LVL304: +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5015 .loc 1 2430 15 view .LVU1675 + 5016 0062 98E0 b .L326 + ARM GAS /tmp/ccEimIdZ.s page 232 + + + 5017 .LVL305: + 5018 .L342: +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5019 .loc 1 2444 5 is_stmt 1 view .LVU1676 +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5020 .loc 1 2444 21 is_stmt 0 view .LVU1677 + 5021 0064 2223 movs r3, #34 + 5022 0066 84F84130 strb r3, [r4, #65] +2445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5023 .loc 1 2445 5 is_stmt 1 view .LVU1678 +2445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5024 .loc 1 2445 21 is_stmt 0 view .LVU1679 + 5025 006a 4023 movs r3, #64 + 5026 006c 84F84230 strb r3, [r4, #66] +2446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5027 .loc 1 2446 5 is_stmt 1 view .LVU1680 +2446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5028 .loc 1 2446 21 is_stmt 0 view .LVU1681 + 5029 0070 0023 movs r3, #0 + 5030 0072 6364 str r3, [r4, #68] +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5031 .loc 1 2449 5 is_stmt 1 view .LVU1682 +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5032 .loc 1 2449 21 is_stmt 0 view .LVU1683 + 5033 0074 0C9A ldr r2, [sp, #48] + 5034 0076 6262 str r2, [r4, #36] +2450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5035 .loc 1 2450 5 is_stmt 1 view .LVU1684 +2450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5036 .loc 1 2450 21 is_stmt 0 view .LVU1685 + 5037 0078 A4F82AA0 strh r10, [r4, #42] @ movhi +2451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5038 .loc 1 2451 5 is_stmt 1 view .LVU1686 +2451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5039 .loc 1 2451 21 is_stmt 0 view .LVU1687 + 5040 007c 6363 str r3, [r4, #52] +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5041 .loc 1 2454 5 is_stmt 1 view .LVU1688 +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5042 .loc 1 2454 9 is_stmt 0 view .LVU1689 + 5043 007e 0196 str r6, [sp, #4] + 5044 0080 0097 str r7, [sp] + 5045 0082 4B46 mov r3, r9 + 5046 0084 4246 mov r2, r8 + 5047 0086 2946 mov r1, r5 + 5048 0088 2046 mov r0, r4 + 5049 008a FFF7FEFF bl I2C_RequestMemoryRead + 5050 .LVL306: +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5051 .loc 1 2454 8 view .LVU1690 + 5052 008e 70B9 cbnz r0, .L343 +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5053 .loc 1 2463 5 is_stmt 1 view .LVU1691 +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5054 .loc 1 2463 13 is_stmt 0 view .LVU1692 + 5055 0090 638D ldrh r3, [r4, #42] + 5056 0092 9BB2 uxth r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 233 + + +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5057 .loc 1 2463 8 view .LVU1693 + 5058 0094 FF2B cmp r3, #255 + 5059 0096 0FD9 bls .L329 +2465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S + 5060 .loc 1 2465 7 is_stmt 1 view .LVU1694 +2465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_S + 5061 .loc 1 2465 22 is_stmt 0 view .LVU1695 + 5062 0098 FF22 movs r2, #255 + 5063 009a 2285 strh r2, [r4, #40] @ movhi +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5064 .loc 1 2466 7 is_stmt 1 view .LVU1696 + 5065 009c 434B ldr r3, .L345 + 5066 009e 0093 str r3, [sp] + 5067 00a0 4FF08073 mov r3, #16777216 + 5068 00a4 2946 mov r1, r5 + 5069 00a6 2046 mov r0, r4 + 5070 00a8 FFF7FEFF bl I2C_TransferConfig + 5071 .LVL307: + 5072 00ac 21E0 b .L333 + 5073 .L343: +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5074 .loc 1 2457 7 view .LVU1697 +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5075 .loc 1 2457 7 view .LVU1698 + 5076 00ae 0023 movs r3, #0 + 5077 00b0 84F84030 strb r3, [r4, #64] +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5078 .loc 1 2457 7 view .LVU1699 +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5079 .loc 1 2458 7 view .LVU1700 +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5080 .loc 1 2458 14 is_stmt 0 view .LVU1701 + 5081 00b4 5846 mov r0, fp + 5082 00b6 6EE0 b .L326 + 5083 .L329: +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 5084 .loc 1 2470 7 is_stmt 1 view .LVU1702 +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 5085 .loc 1 2470 28 is_stmt 0 view .LVU1703 + 5086 00b8 628D ldrh r2, [r4, #42] + 5087 00ba 92B2 uxth r2, r2 +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_ + 5088 .loc 1 2470 22 view .LVU1704 + 5089 00bc 2285 strh r2, [r4, #40] @ movhi +2471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5090 .loc 1 2471 7 is_stmt 1 view .LVU1705 + 5091 00be 3B4B ldr r3, .L345 + 5092 00c0 0093 str r3, [sp] + 5093 00c2 4FF00073 mov r3, #33554432 + 5094 00c6 D2B2 uxtb r2, r2 + 5095 00c8 2946 mov r1, r5 + 5096 00ca 2046 mov r0, r4 + 5097 00cc FFF7FEFF bl I2C_TransferConfig + 5098 .LVL308: + 5099 00d0 0FE0 b .L333 + 5100 .L332: + ARM GAS /tmp/ccEimIdZ.s page 234 + + +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 5101 .loc 1 2506 11 view .LVU1706 +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 5102 .loc 1 2506 32 is_stmt 0 view .LVU1707 + 5103 00d2 628D ldrh r2, [r4, #42] + 5104 00d4 92B2 uxth r2, r2 +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_ST + 5105 .loc 1 2506 26 view .LVU1708 + 5106 00d6 2285 strh r2, [r4, #40] @ movhi +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5107 .loc 1 2507 11 is_stmt 1 view .LVU1709 + 5108 00d8 0023 movs r3, #0 + 5109 00da 0093 str r3, [sp] + 5110 00dc 4FF00073 mov r3, #33554432 + 5111 00e0 D2B2 uxtb r2, r2 + 5112 00e2 2946 mov r1, r5 + 5113 00e4 2046 mov r0, r4 + 5114 00e6 FFF7FEFF bl I2C_TransferConfig + 5115 .LVL309: + 5116 .L331: +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5117 .loc 1 2511 11 view .LVU1710 +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5118 .loc 1 2511 16 is_stmt 0 view .LVU1711 + 5119 00ea 638D ldrh r3, [r4, #42] + 5120 00ec 9BB2 uxth r3, r3 +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5121 .loc 1 2511 5 view .LVU1712 + 5122 00ee 002B cmp r3, #0 + 5123 00f0 34D0 beq .L344 + 5124 .L333: +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5125 .loc 1 2474 5 is_stmt 1 view .LVU1713 +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5126 .loc 1 2477 7 view .LVU1714 +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5127 .loc 1 2477 11 is_stmt 0 view .LVU1715 + 5128 00f2 0096 str r6, [sp] + 5129 00f4 3B46 mov r3, r7 + 5130 00f6 0022 movs r2, #0 + 5131 00f8 0421 movs r1, #4 + 5132 00fa 2046 mov r0, r4 + 5133 00fc FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5134 .LVL310: +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5135 .loc 1 2477 10 view .LVU1716 + 5136 0100 0028 cmp r0, #0 + 5137 0102 4DD1 bne .L337 +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5138 .loc 1 2483 7 is_stmt 1 view .LVU1717 +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5139 .loc 1 2483 38 is_stmt 0 view .LVU1718 + 5140 0104 2368 ldr r3, [r4] +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5141 .loc 1 2483 48 view .LVU1719 + 5142 0106 5A6A ldr r2, [r3, #36] +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 235 + + + 5143 .loc 1 2483 12 view .LVU1720 + 5144 0108 636A ldr r3, [r4, #36] +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5145 .loc 1 2483 23 view .LVU1721 + 5146 010a 1A70 strb r2, [r3] +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5147 .loc 1 2486 7 is_stmt 1 view .LVU1722 +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5148 .loc 1 2486 11 is_stmt 0 view .LVU1723 + 5149 010c 636A ldr r3, [r4, #36] +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5150 .loc 1 2486 21 view .LVU1724 + 5151 010e 0133 adds r3, r3, #1 + 5152 0110 6362 str r3, [r4, #36] +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 5153 .loc 1 2488 7 is_stmt 1 view .LVU1725 +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 5154 .loc 1 2488 11 is_stmt 0 view .LVU1726 + 5155 0112 228D ldrh r2, [r4, #40] +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 5156 .loc 1 2488 21 view .LVU1727 + 5157 0114 013A subs r2, r2, #1 + 5158 0116 92B2 uxth r2, r2 + 5159 0118 2285 strh r2, [r4, #40] @ movhi +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5160 .loc 1 2489 7 is_stmt 1 view .LVU1728 +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5161 .loc 1 2489 11 is_stmt 0 view .LVU1729 + 5162 011a 638D ldrh r3, [r4, #42] + 5163 011c 9BB2 uxth r3, r3 +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5164 .loc 1 2489 22 view .LVU1730 + 5165 011e 013B subs r3, r3, #1 + 5166 0120 9BB2 uxth r3, r3 + 5167 0122 6385 strh r3, [r4, #42] @ movhi +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5168 .loc 1 2491 7 is_stmt 1 view .LVU1731 +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5169 .loc 1 2491 16 is_stmt 0 view .LVU1732 + 5170 0124 638D ldrh r3, [r4, #42] + 5171 0126 9BB2 uxth r3, r3 +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5172 .loc 1 2491 10 view .LVU1733 + 5173 0128 002B cmp r3, #0 + 5174 012a DED0 beq .L331 +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5175 .loc 1 2491 35 discriminator 1 view .LVU1734 + 5176 012c 002A cmp r2, #0 + 5177 012e DCD1 bne .L331 +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5178 .loc 1 2494 9 is_stmt 1 view .LVU1735 +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5179 .loc 1 2494 13 is_stmt 0 view .LVU1736 + 5180 0130 0096 str r6, [sp] + 5181 0132 3B46 mov r3, r7 + 5182 0134 8021 movs r1, #128 + 5183 0136 2046 mov r0, r4 + ARM GAS /tmp/ccEimIdZ.s page 236 + + + 5184 0138 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5185 .LVL311: +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5186 .loc 1 2494 12 view .LVU1737 + 5187 013c 90BB cbnz r0, .L338 +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5188 .loc 1 2499 9 is_stmt 1 view .LVU1738 +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5189 .loc 1 2499 17 is_stmt 0 view .LVU1739 + 5190 013e 638D ldrh r3, [r4, #42] + 5191 0140 9BB2 uxth r3, r3 +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5192 .loc 1 2499 12 view .LVU1740 + 5193 0142 FF2B cmp r3, #255 + 5194 0144 C5D9 bls .L332 +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_ST + 5195 .loc 1 2501 11 is_stmt 1 view .LVU1741 +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_ST + 5196 .loc 1 2501 26 is_stmt 0 view .LVU1742 + 5197 0146 FF22 movs r2, #255 + 5198 0148 2285 strh r2, [r4, #40] @ movhi +2502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5199 .loc 1 2502 11 is_stmt 1 view .LVU1743 + 5200 014a 0023 movs r3, #0 + 5201 014c 0093 str r3, [sp] + 5202 014e 4FF08073 mov r3, #16777216 + 5203 0152 2946 mov r1, r5 + 5204 0154 2046 mov r0, r4 + 5205 0156 FFF7FEFF bl I2C_TransferConfig + 5206 .LVL312: + 5207 015a C6E7 b .L331 + 5208 .L344: +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5209 .loc 1 2515 5 view .LVU1744 +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5210 .loc 1 2515 9 is_stmt 0 view .LVU1745 + 5211 015c 3246 mov r2, r6 + 5212 015e 3946 mov r1, r7 + 5213 0160 2046 mov r0, r4 + 5214 0162 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5215 .LVL313: +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5216 .loc 1 2515 8 view .LVU1746 + 5217 0166 F8B9 cbnz r0, .L339 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5218 .loc 1 2521 5 is_stmt 1 view .LVU1747 + 5219 0168 2368 ldr r3, [r4] + 5220 016a 2022 movs r2, #32 + 5221 016c DA61 str r2, [r3, #28] +2524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5222 .loc 1 2524 5 view .LVU1748 + 5223 016e 2168 ldr r1, [r4] + 5224 0170 4B68 ldr r3, [r1, #4] + 5225 0172 23F0FF73 bic r3, r3, #33423360 + 5226 0176 23F48B33 bic r3, r3, #71168 + 5227 017a 23F4FF73 bic r3, r3, #510 + 5228 017e 23F00103 bic r3, r3, #1 + ARM GAS /tmp/ccEimIdZ.s page 237 + + + 5229 0182 4B60 str r3, [r1, #4] +2526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5230 .loc 1 2526 5 view .LVU1749 +2526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5231 .loc 1 2526 17 is_stmt 0 view .LVU1750 + 5232 0184 84F84120 strb r2, [r4, #65] +2527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5233 .loc 1 2527 5 is_stmt 1 view .LVU1751 +2527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5234 .loc 1 2527 17 is_stmt 0 view .LVU1752 + 5235 0188 0023 movs r3, #0 + 5236 018a 84F84230 strb r3, [r4, #66] +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5237 .loc 1 2530 5 is_stmt 1 view .LVU1753 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5238 .loc 1 2530 5 view .LVU1754 + 5239 018e 84F84030 strb r3, [r4, #64] +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5240 .loc 1 2530 5 view .LVU1755 +2532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5241 .loc 1 2532 5 view .LVU1756 +2532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5242 .loc 1 2532 12 is_stmt 0 view .LVU1757 + 5243 0192 00E0 b .L326 + 5244 .LVL314: + 5245 .L334: +2536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5246 .loc 1 2536 12 view .LVU1758 + 5247 0194 0220 movs r0, #2 + 5248 .LVL315: + 5249 .L326: +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 5250 .loc 1 2538 1 view .LVU1759 + 5251 0196 03B0 add sp, sp, #12 + 5252 .LCFI61: + 5253 .cfi_remember_state + 5254 .cfi_def_cfa_offset 36 + 5255 @ sp needed + 5256 0198 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 5257 .LVL316: + 5258 .L335: + 5259 .LCFI62: + 5260 .cfi_restore_state +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5261 .loc 1 2434 5 view .LVU1760 + 5262 019c 0220 movs r0, #2 + 5263 .LVL317: +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5264 .loc 1 2434 5 view .LVU1761 + 5265 019e FAE7 b .L326 + 5266 .LVL318: + 5267 .L337: +2479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5268 .loc 1 2479 16 view .LVU1762 + 5269 01a0 0120 movs r0, #1 + 5270 01a2 F8E7 b .L326 + 5271 .L338: + ARM GAS /tmp/ccEimIdZ.s page 238 + + +2496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5272 .loc 1 2496 18 view .LVU1763 + 5273 01a4 0120 movs r0, #1 + 5274 01a6 F6E7 b .L326 + 5275 .L339: +2517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5276 .loc 1 2517 14 view .LVU1764 + 5277 01a8 0120 movs r0, #1 + 5278 01aa F4E7 b .L326 + 5279 .L346: + 5280 .align 2 + 5281 .L345: + 5282 01ac 00240080 .word -2147474432 + 5283 .cfi_endproc + 5284 .LFE158: + 5286 .section .text.HAL_I2C_Mem_Write_IT,"ax",%progbits + 5287 .align 1 + 5288 .global HAL_I2C_Mem_Write_IT + 5289 .syntax unified + 5290 .thumb + 5291 .thumb_func + 5292 .fpu fpv5-d16 + 5294 HAL_I2C_Mem_Write_IT: + 5295 .LVL319: + 5296 .LFB159: +2552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 5297 .loc 1 2552 1 is_stmt 1 view -0 + 5298 .cfi_startproc + 5299 @ args = 8, pretend = 0, frame = 0 + 5300 @ frame_needed = 0, uses_anonymous_args = 0 +2552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 5301 .loc 1 2552 1 is_stmt 0 view .LVU1766 + 5302 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 5303 .LCFI63: + 5304 .cfi_def_cfa_offset 24 + 5305 .cfi_offset 4, -24 + 5306 .cfi_offset 5, -20 + 5307 .cfi_offset 6, -16 + 5308 .cfi_offset 7, -12 + 5309 .cfi_offset 8, -8 + 5310 .cfi_offset 14, -4 + 5311 0004 82B0 sub sp, sp, #8 + 5312 .LCFI64: + 5313 .cfi_def_cfa_offset 32 + 5314 0006 0446 mov r4, r0 + 5315 0008 BDF82480 ldrh r8, [sp, #36] +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 5316 .loc 1 2553 3 is_stmt 1 view .LVU1767 +2554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5317 .loc 1 2554 3 view .LVU1768 +2557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5318 .loc 1 2557 3 view .LVU1769 +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5319 .loc 1 2559 3 view .LVU1770 +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5320 .loc 1 2559 11 is_stmt 0 view .LVU1771 + 5321 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + ARM GAS /tmp/ccEimIdZ.s page 239 + + + 5322 .LVL320: +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5323 .loc 1 2559 11 view .LVU1772 + 5324 0010 C0B2 uxtb r0, r0 +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5325 .loc 1 2559 6 view .LVU1773 + 5326 0012 2028 cmp r0, #32 + 5327 0014 58D1 bne .L353 + 5328 0016 0D46 mov r5, r1 + 5329 0018 1746 mov r7, r2 + 5330 001a 1E46 mov r6, r3 +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5331 .loc 1 2561 5 is_stmt 1 view .LVU1774 +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5332 .loc 1 2561 8 is_stmt 0 view .LVU1775 + 5333 001c 089B ldr r3, [sp, #32] + 5334 .LVL321: +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5335 .loc 1 2561 8 view .LVU1776 + 5336 001e B8F1000F cmp r8, #0 + 5337 0022 18BF it ne + 5338 0024 002B cmpne r3, #0 + 5339 0026 35D0 beq .L357 +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5340 .loc 1 2567 5 is_stmt 1 view .LVU1777 +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5341 .loc 1 2567 9 is_stmt 0 view .LVU1778 + 5342 0028 2368 ldr r3, [r4] + 5343 002a 9B69 ldr r3, [r3, #24] +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5344 .loc 1 2567 8 view .LVU1779 + 5345 002c 13F4004F tst r3, #32768 + 5346 0030 4FD1 bne .L354 +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5347 .loc 1 2573 5 is_stmt 1 view .LVU1780 +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5348 .loc 1 2573 5 view .LVU1781 + 5349 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 5350 0036 012B cmp r3, #1 + 5351 0038 4DD0 beq .L355 +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5352 .loc 1 2573 5 discriminator 2 view .LVU1782 + 5353 003a 0123 movs r3, #1 + 5354 003c 84F84030 strb r3, [r4, #64] +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5355 .loc 1 2573 5 discriminator 2 view .LVU1783 +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5356 .loc 1 2576 5 discriminator 2 view .LVU1784 +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5357 .loc 1 2576 17 is_stmt 0 discriminator 2 view .LVU1785 + 5358 0040 FFF7FEFF bl HAL_GetTick + 5359 .LVL322: +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5360 .loc 1 2578 5 is_stmt 1 discriminator 2 view .LVU1786 +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5361 .loc 1 2578 23 is_stmt 0 discriminator 2 view .LVU1787 + 5362 0044 2123 movs r3, #33 + ARM GAS /tmp/ccEimIdZ.s page 240 + + + 5363 0046 84F84130 strb r3, [r4, #65] +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5364 .loc 1 2579 5 is_stmt 1 discriminator 2 view .LVU1788 +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5365 .loc 1 2579 23 is_stmt 0 discriminator 2 view .LVU1789 + 5366 004a 4023 movs r3, #64 + 5367 004c 84F84230 strb r3, [r4, #66] +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5368 .loc 1 2580 5 is_stmt 1 discriminator 2 view .LVU1790 +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5369 .loc 1 2580 23 is_stmt 0 discriminator 2 view .LVU1791 + 5370 0050 0023 movs r3, #0 + 5371 0052 6364 str r3, [r4, #68] +2583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5372 .loc 1 2583 5 is_stmt 1 discriminator 2 view .LVU1792 +2583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5373 .loc 1 2583 23 is_stmt 0 discriminator 2 view .LVU1793 + 5374 0054 089B ldr r3, [sp, #32] + 5375 0056 6362 str r3, [r4, #36] +2584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5376 .loc 1 2584 5 is_stmt 1 discriminator 2 view .LVU1794 +2584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5377 .loc 1 2584 23 is_stmt 0 discriminator 2 view .LVU1795 + 5378 0058 A4F82A80 strh r8, [r4, #42] @ movhi +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5379 .loc 1 2585 5 is_stmt 1 discriminator 2 view .LVU1796 +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5380 .loc 1 2585 23 is_stmt 0 discriminator 2 view .LVU1797 + 5381 005c 1F4B ldr r3, .L358 + 5382 005e E362 str r3, [r4, #44] +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5383 .loc 1 2586 5 is_stmt 1 discriminator 2 view .LVU1798 +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5384 .loc 1 2586 23 is_stmt 0 discriminator 2 view .LVU1799 + 5385 0060 1F4B ldr r3, .L358+4 + 5386 0062 6363 str r3, [r4, #52] +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5387 .loc 1 2588 5 is_stmt 1 discriminator 2 view .LVU1800 +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5388 .loc 1 2588 13 is_stmt 0 discriminator 2 view .LVU1801 + 5389 0064 638D ldrh r3, [r4, #42] + 5390 0066 9BB2 uxth r3, r3 +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5391 .loc 1 2588 8 discriminator 2 view .LVU1802 + 5392 0068 FF2B cmp r3, #255 + 5393 006a 18D9 bls .L350 +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5394 .loc 1 2590 7 is_stmt 1 view .LVU1803 +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5395 .loc 1 2590 22 is_stmt 0 view .LVU1804 + 5396 006c FF23 movs r3, #255 + 5397 006e 2385 strh r3, [r4, #40] @ movhi +2591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5398 .loc 1 2591 7 is_stmt 1 view .LVU1805 + 5399 .LVL323: +2591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5400 .loc 1 2591 16 is_stmt 0 view .LVU1806 + ARM GAS /tmp/ccEimIdZ.s page 241 + + + 5401 0070 4FF08078 mov r8, #16777216 + 5402 .LVL324: + 5403 .L351: +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5404 .loc 1 2600 5 is_stmt 1 view .LVU1807 +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5405 .loc 1 2600 9 is_stmt 0 view .LVU1808 + 5406 0074 0190 str r0, [sp, #4] + 5407 0076 1923 movs r3, #25 + 5408 0078 0093 str r3, [sp] + 5409 007a 3346 mov r3, r6 + 5410 007c 3A46 mov r2, r7 + 5411 007e 2946 mov r1, r5 + 5412 0080 2046 mov r0, r4 + 5413 .LVL325: +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5414 .loc 1 2600 9 view .LVU1809 + 5415 0082 FFF7FEFF bl I2C_RequestMemoryWrite + 5416 .LVL326: +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5417 .loc 1 2600 8 view .LVU1810 + 5418 0086 0646 mov r6, r0 + 5419 0088 70B1 cbz r0, .L352 +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5420 .loc 1 2603 7 is_stmt 1 view .LVU1811 +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5421 .loc 1 2603 7 view .LVU1812 + 5422 008a 0023 movs r3, #0 + 5423 008c 84F84030 strb r3, [r4, #64] +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5424 .loc 1 2603 7 view .LVU1813 +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5425 .loc 1 2604 7 view .LVU1814 +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5426 .loc 1 2604 14 is_stmt 0 view .LVU1815 + 5427 0090 0126 movs r6, #1 + 5428 0092 1AE0 b .L348 + 5429 .LVL327: + 5430 .L357: +2563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5431 .loc 1 2563 7 is_stmt 1 view .LVU1816 +2563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5432 .loc 1 2563 23 is_stmt 0 view .LVU1817 + 5433 0094 4FF40073 mov r3, #512 + 5434 0098 6364 str r3, [r4, #68] +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5435 .loc 1 2564 7 is_stmt 1 view .LVU1818 +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5436 .loc 1 2564 15 is_stmt 0 view .LVU1819 + 5437 009a 0126 movs r6, #1 + 5438 009c 15E0 b .L348 + 5439 .LVL328: + 5440 .L350: +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5441 .loc 1 2595 7 is_stmt 1 view .LVU1820 +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5442 .loc 1 2595 28 is_stmt 0 view .LVU1821 + ARM GAS /tmp/ccEimIdZ.s page 242 + + + 5443 009e 638D ldrh r3, [r4, #42] +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5444 .loc 1 2595 22 view .LVU1822 + 5445 00a0 2385 strh r3, [r4, #40] @ movhi +2596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5446 .loc 1 2596 7 is_stmt 1 view .LVU1823 + 5447 .LVL329: +2596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5448 .loc 1 2596 16 is_stmt 0 view .LVU1824 + 5449 00a2 4FF00078 mov r8, #33554432 + 5450 00a6 E5E7 b .L351 + 5451 .LVL330: + 5452 .L352: +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5453 .loc 1 2608 5 is_stmt 1 view .LVU1825 + 5454 00a8 0027 movs r7, #0 + 5455 00aa 0097 str r7, [sp] + 5456 00ac 4346 mov r3, r8 + 5457 00ae 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 5458 00b2 2946 mov r1, r5 + 5459 00b4 2046 mov r0, r4 + 5460 00b6 FFF7FEFF bl I2C_TransferConfig + 5461 .LVL331: +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5462 .loc 1 2611 5 view .LVU1826 +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5463 .loc 1 2611 5 view .LVU1827 + 5464 00ba 84F84070 strb r7, [r4, #64] +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5465 .loc 1 2611 5 view .LVU1828 +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5466 .loc 1 2620 5 view .LVU1829 + 5467 00be 0121 movs r1, #1 + 5468 00c0 2046 mov r0, r4 + 5469 00c2 FFF7FEFF bl I2C_Enable_IRQ + 5470 .LVL332: +2622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5471 .loc 1 2622 5 view .LVU1830 +2622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5472 .loc 1 2622 12 is_stmt 0 view .LVU1831 + 5473 00c6 00E0 b .L348 + 5474 .LVL333: + 5475 .L353: +2626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5476 .loc 1 2626 12 view .LVU1832 + 5477 00c8 0226 movs r6, #2 + 5478 .LVL334: + 5479 .L348: +2628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5480 .loc 1 2628 1 view .LVU1833 + 5481 00ca 3046 mov r0, r6 + 5482 00cc 02B0 add sp, sp, #8 + 5483 .LCFI65: + 5484 .cfi_remember_state + 5485 .cfi_def_cfa_offset 24 + 5486 @ sp needed + 5487 00ce BDE8F081 pop {r4, r5, r6, r7, r8, pc} + ARM GAS /tmp/ccEimIdZ.s page 243 + + + 5488 .LVL335: + 5489 .L354: + 5490 .LCFI66: + 5491 .cfi_restore_state +2569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5492 .loc 1 2569 14 view .LVU1834 + 5493 00d2 0226 movs r6, #2 + 5494 00d4 F9E7 b .L348 + 5495 .L355: +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5496 .loc 1 2573 5 view .LVU1835 + 5497 00d6 0226 movs r6, #2 + 5498 00d8 F7E7 b .L348 + 5499 .L359: + 5500 00da 00BF .align 2 + 5501 .L358: + 5502 00dc 0000FFFF .word -65536 + 5503 00e0 00000000 .word I2C_Master_ISR_IT + 5504 .cfi_endproc + 5505 .LFE159: + 5507 .section .text.HAL_I2C_Mem_Read_IT,"ax",%progbits + 5508 .align 1 + 5509 .global HAL_I2C_Mem_Read_IT + 5510 .syntax unified + 5511 .thumb + 5512 .thumb_func + 5513 .fpu fpv5-d16 + 5515 HAL_I2C_Mem_Read_IT: + 5516 .LVL336: + 5517 .LFB160: +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 5518 .loc 1 2643 1 is_stmt 1 view -0 + 5519 .cfi_startproc + 5520 @ args = 8, pretend = 0, frame = 0 + 5521 @ frame_needed = 0, uses_anonymous_args = 0 +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 5522 .loc 1 2643 1 is_stmt 0 view .LVU1837 + 5523 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 5524 .LCFI67: + 5525 .cfi_def_cfa_offset 24 + 5526 .cfi_offset 4, -24 + 5527 .cfi_offset 5, -20 + 5528 .cfi_offset 6, -16 + 5529 .cfi_offset 7, -12 + 5530 .cfi_offset 8, -8 + 5531 .cfi_offset 14, -4 + 5532 0004 82B0 sub sp, sp, #8 + 5533 .LCFI68: + 5534 .cfi_def_cfa_offset 32 + 5535 0006 0446 mov r4, r0 + 5536 0008 BDF82480 ldrh r8, [sp, #36] +2644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 5537 .loc 1 2644 3 is_stmt 1 view .LVU1838 +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5538 .loc 1 2645 3 view .LVU1839 +2648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5539 .loc 1 2648 3 view .LVU1840 + ARM GAS /tmp/ccEimIdZ.s page 244 + + +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5540 .loc 1 2650 3 view .LVU1841 +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5541 .loc 1 2650 11 is_stmt 0 view .LVU1842 + 5542 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5543 .LVL337: +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5544 .loc 1 2650 11 view .LVU1843 + 5545 0010 C0B2 uxtb r0, r0 +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5546 .loc 1 2650 6 view .LVU1844 + 5547 0012 2028 cmp r0, #32 + 5548 0014 59D1 bne .L366 + 5549 0016 0D46 mov r5, r1 + 5550 0018 1746 mov r7, r2 + 5551 001a 1E46 mov r6, r3 +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5552 .loc 1 2652 5 is_stmt 1 view .LVU1845 +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5553 .loc 1 2652 8 is_stmt 0 view .LVU1846 + 5554 001c 089B ldr r3, [sp, #32] + 5555 .LVL338: +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5556 .loc 1 2652 8 view .LVU1847 + 5557 001e B8F1000F cmp r8, #0 + 5558 0022 18BF it ne + 5559 0024 002B cmpne r3, #0 + 5560 0026 35D0 beq .L370 +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5561 .loc 1 2658 5 is_stmt 1 view .LVU1848 +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5562 .loc 1 2658 9 is_stmt 0 view .LVU1849 + 5563 0028 2368 ldr r3, [r4] + 5564 002a 9B69 ldr r3, [r3, #24] +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5565 .loc 1 2658 8 view .LVU1850 + 5566 002c 13F4004F tst r3, #32768 + 5567 0030 50D1 bne .L367 +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5568 .loc 1 2664 5 is_stmt 1 view .LVU1851 +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5569 .loc 1 2664 5 view .LVU1852 + 5570 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 5571 0036 012B cmp r3, #1 + 5572 0038 4ED0 beq .L368 +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5573 .loc 1 2664 5 discriminator 2 view .LVU1853 + 5574 003a 0123 movs r3, #1 + 5575 003c 84F84030 strb r3, [r4, #64] +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5576 .loc 1 2664 5 discriminator 2 view .LVU1854 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5577 .loc 1 2667 5 discriminator 2 view .LVU1855 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5578 .loc 1 2667 17 is_stmt 0 discriminator 2 view .LVU1856 + 5579 0040 FFF7FEFF bl HAL_GetTick + 5580 .LVL339: + ARM GAS /tmp/ccEimIdZ.s page 245 + + +2669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5581 .loc 1 2669 5 is_stmt 1 discriminator 2 view .LVU1857 +2669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5582 .loc 1 2669 23 is_stmt 0 discriminator 2 view .LVU1858 + 5583 0044 2223 movs r3, #34 + 5584 0046 84F84130 strb r3, [r4, #65] +2670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5585 .loc 1 2670 5 is_stmt 1 discriminator 2 view .LVU1859 +2670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5586 .loc 1 2670 23 is_stmt 0 discriminator 2 view .LVU1860 + 5587 004a 4023 movs r3, #64 + 5588 004c 84F84230 strb r3, [r4, #66] +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5589 .loc 1 2671 5 is_stmt 1 discriminator 2 view .LVU1861 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5590 .loc 1 2671 23 is_stmt 0 discriminator 2 view .LVU1862 + 5591 0050 0023 movs r3, #0 + 5592 0052 6364 str r3, [r4, #68] +2674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5593 .loc 1 2674 5 is_stmt 1 discriminator 2 view .LVU1863 +2674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5594 .loc 1 2674 23 is_stmt 0 discriminator 2 view .LVU1864 + 5595 0054 089B ldr r3, [sp, #32] + 5596 0056 6362 str r3, [r4, #36] +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5597 .loc 1 2675 5 is_stmt 1 discriminator 2 view .LVU1865 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5598 .loc 1 2675 23 is_stmt 0 discriminator 2 view .LVU1866 + 5599 0058 A4F82A80 strh r8, [r4, #42] @ movhi +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5600 .loc 1 2676 5 is_stmt 1 discriminator 2 view .LVU1867 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5601 .loc 1 2676 23 is_stmt 0 discriminator 2 view .LVU1868 + 5602 005c 1F4B ldr r3, .L371 + 5603 005e E362 str r3, [r4, #44] +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5604 .loc 1 2677 5 is_stmt 1 discriminator 2 view .LVU1869 +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5605 .loc 1 2677 23 is_stmt 0 discriminator 2 view .LVU1870 + 5606 0060 1F4B ldr r3, .L371+4 + 5607 0062 6363 str r3, [r4, #52] +2679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5608 .loc 1 2679 5 is_stmt 1 discriminator 2 view .LVU1871 +2679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5609 .loc 1 2679 13 is_stmt 0 discriminator 2 view .LVU1872 + 5610 0064 638D ldrh r3, [r4, #42] + 5611 0066 9BB2 uxth r3, r3 +2679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5612 .loc 1 2679 8 discriminator 2 view .LVU1873 + 5613 0068 FF2B cmp r3, #255 + 5614 006a 18D9 bls .L363 +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5615 .loc 1 2681 7 is_stmt 1 view .LVU1874 +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5616 .loc 1 2681 22 is_stmt 0 view .LVU1875 + 5617 006c FF23 movs r3, #255 + 5618 006e 2385 strh r3, [r4, #40] @ movhi + ARM GAS /tmp/ccEimIdZ.s page 246 + + +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5619 .loc 1 2682 7 is_stmt 1 view .LVU1876 + 5620 .LVL340: +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5621 .loc 1 2682 16 is_stmt 0 view .LVU1877 + 5622 0070 4FF08078 mov r8, #16777216 + 5623 .LVL341: + 5624 .L364: +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5625 .loc 1 2691 5 is_stmt 1 view .LVU1878 +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5626 .loc 1 2691 9 is_stmt 0 view .LVU1879 + 5627 0074 0190 str r0, [sp, #4] + 5628 0076 1923 movs r3, #25 + 5629 0078 0093 str r3, [sp] + 5630 007a 3346 mov r3, r6 + 5631 007c 3A46 mov r2, r7 + 5632 007e 2946 mov r1, r5 + 5633 0080 2046 mov r0, r4 + 5634 .LVL342: +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5635 .loc 1 2691 9 view .LVU1880 + 5636 0082 FFF7FEFF bl I2C_RequestMemoryRead + 5637 .LVL343: +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5638 .loc 1 2691 8 view .LVU1881 + 5639 0086 0646 mov r6, r0 + 5640 0088 70B1 cbz r0, .L365 +2694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5641 .loc 1 2694 7 is_stmt 1 view .LVU1882 +2694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5642 .loc 1 2694 7 view .LVU1883 + 5643 008a 0023 movs r3, #0 + 5644 008c 84F84030 strb r3, [r4, #64] +2694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5645 .loc 1 2694 7 view .LVU1884 +2695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5646 .loc 1 2695 7 view .LVU1885 +2695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5647 .loc 1 2695 14 is_stmt 0 view .LVU1886 + 5648 0090 0126 movs r6, #1 + 5649 0092 1BE0 b .L361 + 5650 .LVL344: + 5651 .L370: +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5652 .loc 1 2654 7 is_stmt 1 view .LVU1887 +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5653 .loc 1 2654 23 is_stmt 0 view .LVU1888 + 5654 0094 4FF40073 mov r3, #512 + 5655 0098 6364 str r3, [r4, #68] +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5656 .loc 1 2655 7 is_stmt 1 view .LVU1889 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5657 .loc 1 2655 15 is_stmt 0 view .LVU1890 + 5658 009a 0126 movs r6, #1 + 5659 009c 16E0 b .L361 + 5660 .LVL345: + ARM GAS /tmp/ccEimIdZ.s page 247 + + + 5661 .L363: +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5662 .loc 1 2686 7 is_stmt 1 view .LVU1891 +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5663 .loc 1 2686 28 is_stmt 0 view .LVU1892 + 5664 009e 638D ldrh r3, [r4, #42] +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5665 .loc 1 2686 22 view .LVU1893 + 5666 00a0 2385 strh r3, [r4, #40] @ movhi +2687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5667 .loc 1 2687 7 is_stmt 1 view .LVU1894 + 5668 .LVL346: +2687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5669 .loc 1 2687 16 is_stmt 0 view .LVU1895 + 5670 00a2 4FF00078 mov r8, #33554432 + 5671 00a6 E5E7 b .L364 + 5672 .LVL347: + 5673 .L365: +2699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5674 .loc 1 2699 5 is_stmt 1 view .LVU1896 + 5675 00a8 0E4B ldr r3, .L371+8 + 5676 00aa 0093 str r3, [sp] + 5677 00ac 4346 mov r3, r8 + 5678 00ae 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 5679 00b2 2946 mov r1, r5 + 5680 00b4 2046 mov r0, r4 + 5681 00b6 FFF7FEFF bl I2C_TransferConfig + 5682 .LVL348: +2702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5683 .loc 1 2702 5 view .LVU1897 +2702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5684 .loc 1 2702 5 view .LVU1898 + 5685 00ba 0023 movs r3, #0 + 5686 00bc 84F84030 strb r3, [r4, #64] +2702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5687 .loc 1 2702 5 view .LVU1899 +2711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5688 .loc 1 2711 5 view .LVU1900 + 5689 00c0 0221 movs r1, #2 + 5690 00c2 2046 mov r0, r4 + 5691 00c4 FFF7FEFF bl I2C_Enable_IRQ + 5692 .LVL349: +2713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5693 .loc 1 2713 5 view .LVU1901 +2713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5694 .loc 1 2713 12 is_stmt 0 view .LVU1902 + 5695 00c8 00E0 b .L361 + 5696 .LVL350: + 5697 .L366: +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5698 .loc 1 2717 12 view .LVU1903 + 5699 00ca 0226 movs r6, #2 + 5700 .LVL351: + 5701 .L361: +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /** + 5702 .loc 1 2719 1 view .LVU1904 + 5703 00cc 3046 mov r0, r6 + ARM GAS /tmp/ccEimIdZ.s page 248 + + + 5704 00ce 02B0 add sp, sp, #8 + 5705 .LCFI69: + 5706 .cfi_remember_state + 5707 .cfi_def_cfa_offset 24 + 5708 @ sp needed + 5709 00d0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 5710 .LVL352: + 5711 .L367: + 5712 .LCFI70: + 5713 .cfi_restore_state +2660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5714 .loc 1 2660 14 view .LVU1905 + 5715 00d4 0226 movs r6, #2 + 5716 00d6 F9E7 b .L361 + 5717 .L368: +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5718 .loc 1 2664 5 view .LVU1906 + 5719 00d8 0226 movs r6, #2 + 5720 00da F7E7 b .L361 + 5721 .L372: + 5722 .align 2 + 5723 .L371: + 5724 00dc 0000FFFF .word -65536 + 5725 00e0 00000000 .word I2C_Master_ISR_IT + 5726 00e4 00240080 .word -2147474432 + 5727 .cfi_endproc + 5728 .LFE160: + 5730 .section .text.HAL_I2C_Mem_Write_DMA,"ax",%progbits + 5731 .align 1 + 5732 .global HAL_I2C_Mem_Write_DMA + 5733 .syntax unified + 5734 .thumb + 5735 .thumb_func + 5736 .fpu fpv5-d16 + 5738 HAL_I2C_Mem_Write_DMA: + 5739 .LVL353: + 5740 .LFB161: +2733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 5741 .loc 1 2733 1 is_stmt 1 view -0 + 5742 .cfi_startproc + 5743 @ args = 8, pretend = 0, frame = 0 + 5744 @ frame_needed = 0, uses_anonymous_args = 0 +2733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 5745 .loc 1 2733 1 is_stmt 0 view .LVU1908 + 5746 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 5747 .LCFI71: + 5748 .cfi_def_cfa_offset 28 + 5749 .cfi_offset 4, -28 + 5750 .cfi_offset 5, -24 + 5751 .cfi_offset 6, -20 + 5752 .cfi_offset 7, -16 + 5753 .cfi_offset 8, -12 + 5754 .cfi_offset 9, -8 + 5755 .cfi_offset 14, -4 + 5756 0004 83B0 sub sp, sp, #12 + 5757 .LCFI72: + 5758 .cfi_def_cfa_offset 40 + ARM GAS /tmp/ccEimIdZ.s page 249 + + + 5759 0006 0446 mov r4, r0 + 5760 0008 0A9D ldr r5, [sp, #40] + 5761 000a BDF82C90 ldrh r9, [sp, #44] +2734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 5762 .loc 1 2734 3 is_stmt 1 view .LVU1909 +2735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 5763 .loc 1 2735 3 view .LVU1910 +2736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5764 .loc 1 2736 3 view .LVU1911 +2739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5765 .loc 1 2739 3 view .LVU1912 +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5766 .loc 1 2741 3 view .LVU1913 +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5767 .loc 1 2741 11 is_stmt 0 view .LVU1914 + 5768 000e 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5769 .LVL354: +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5770 .loc 1 2741 11 view .LVU1915 + 5771 0012 C0B2 uxtb r0, r0 +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5772 .loc 1 2741 6 view .LVU1916 + 5773 0014 2028 cmp r0, #32 + 5774 0016 40F09780 bne .L382 + 5775 001a 0E46 mov r6, r1 + 5776 001c 9046 mov r8, r2 + 5777 001e 1F46 mov r7, r3 +2743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5778 .loc 1 2743 5 is_stmt 1 view .LVU1917 +2743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5779 .loc 1 2743 8 is_stmt 0 view .LVU1918 + 5780 0020 B9F1000F cmp r9, #0 + 5781 0024 18BF it ne + 5782 0026 002D cmpne r5, #0 + 5783 0028 56D0 beq .L387 +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5784 .loc 1 2749 5 is_stmt 1 view .LVU1919 +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5785 .loc 1 2749 9 is_stmt 0 view .LVU1920 + 5786 002a 2368 ldr r3, [r4] + 5787 .LVL355: +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5788 .loc 1 2749 9 view .LVU1921 + 5789 002c 9B69 ldr r3, [r3, #24] +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5790 .loc 1 2749 8 view .LVU1922 + 5791 002e 13F4004F tst r3, #32768 + 5792 0032 40F08E80 bne .L383 +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5793 .loc 1 2755 5 is_stmt 1 view .LVU1923 +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5794 .loc 1 2755 5 view .LVU1924 + 5795 0036 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 5796 003a 012B cmp r3, #1 + 5797 003c 00F08B80 beq .L384 +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5798 .loc 1 2755 5 discriminator 2 view .LVU1925 + ARM GAS /tmp/ccEimIdZ.s page 250 + + + 5799 0040 0123 movs r3, #1 + 5800 0042 84F84030 strb r3, [r4, #64] +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5801 .loc 1 2755 5 discriminator 2 view .LVU1926 +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5802 .loc 1 2758 5 discriminator 2 view .LVU1927 +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5803 .loc 1 2758 17 is_stmt 0 discriminator 2 view .LVU1928 + 5804 0046 FFF7FEFF bl HAL_GetTick + 5805 .LVL356: +2760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5806 .loc 1 2760 5 is_stmt 1 discriminator 2 view .LVU1929 +2760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5807 .loc 1 2760 23 is_stmt 0 discriminator 2 view .LVU1930 + 5808 004a 2123 movs r3, #33 + 5809 004c 84F84130 strb r3, [r4, #65] +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5810 .loc 1 2761 5 is_stmt 1 discriminator 2 view .LVU1931 +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5811 .loc 1 2761 23 is_stmt 0 discriminator 2 view .LVU1932 + 5812 0050 4023 movs r3, #64 + 5813 0052 84F84230 strb r3, [r4, #66] +2762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5814 .loc 1 2762 5 is_stmt 1 discriminator 2 view .LVU1933 +2762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5815 .loc 1 2762 23 is_stmt 0 discriminator 2 view .LVU1934 + 5816 0056 0023 movs r3, #0 + 5817 0058 6364 str r3, [r4, #68] +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5818 .loc 1 2765 5 is_stmt 1 discriminator 2 view .LVU1935 +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5819 .loc 1 2765 23 is_stmt 0 discriminator 2 view .LVU1936 + 5820 005a 6562 str r5, [r4, #36] +2766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5821 .loc 1 2766 5 is_stmt 1 discriminator 2 view .LVU1937 +2766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5822 .loc 1 2766 23 is_stmt 0 discriminator 2 view .LVU1938 + 5823 005c A4F82A90 strh r9, [r4, #42] @ movhi +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 5824 .loc 1 2767 5 is_stmt 1 discriminator 2 view .LVU1939 +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 5825 .loc 1 2767 23 is_stmt 0 discriminator 2 view .LVU1940 + 5826 0060 A3F58033 sub r3, r3, #65536 + 5827 0064 E362 str r3, [r4, #44] +2768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5828 .loc 1 2768 5 is_stmt 1 discriminator 2 view .LVU1941 +2768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5829 .loc 1 2768 23 is_stmt 0 discriminator 2 view .LVU1942 + 5830 0066 3D4B ldr r3, .L390 + 5831 0068 6363 str r3, [r4, #52] +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5832 .loc 1 2770 5 is_stmt 1 discriminator 2 view .LVU1943 +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5833 .loc 1 2770 13 is_stmt 0 discriminator 2 view .LVU1944 + 5834 006a 638D ldrh r3, [r4, #42] + 5835 006c 9BB2 uxth r3, r3 +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 251 + + + 5836 .loc 1 2770 8 discriminator 2 view .LVU1945 + 5837 006e FF2B cmp r3, #255 + 5838 0070 37D9 bls .L376 +2772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5839 .loc 1 2772 7 is_stmt 1 view .LVU1946 +2772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5840 .loc 1 2772 22 is_stmt 0 view .LVU1947 + 5841 0072 FF23 movs r3, #255 + 5842 0074 2385 strh r3, [r4, #40] @ movhi +2773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5843 .loc 1 2773 7 is_stmt 1 view .LVU1948 + 5844 .LVL357: +2773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5845 .loc 1 2773 16 is_stmt 0 view .LVU1949 + 5846 0076 4FF08079 mov r9, #16777216 + 5847 .LVL358: + 5848 .L377: +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5849 .loc 1 2782 5 is_stmt 1 view .LVU1950 +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5850 .loc 1 2782 9 is_stmt 0 view .LVU1951 + 5851 007a 0190 str r0, [sp, #4] + 5852 007c 1923 movs r3, #25 + 5853 007e 0093 str r3, [sp] + 5854 0080 3B46 mov r3, r7 + 5855 0082 4246 mov r2, r8 + 5856 0084 3146 mov r1, r6 + 5857 0086 2046 mov r0, r4 + 5858 .LVL359: +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5859 .loc 1 2782 9 view .LVU1952 + 5860 0088 FFF7FEFF bl I2C_RequestMemoryWrite + 5861 .LVL360: +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5862 .loc 1 2782 8 view .LVU1953 + 5863 008c 0028 cmp r0, #0 + 5864 008e 2DD1 bne .L388 +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5865 .loc 1 2790 5 is_stmt 1 view .LVU1954 +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5866 .loc 1 2790 13 is_stmt 0 view .LVU1955 + 5867 0090 A36B ldr r3, [r4, #56] +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5868 .loc 1 2790 8 view .LVU1956 + 5869 0092 002B cmp r3, #0 + 5870 0094 2FD0 beq .L379 +2793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5871 .loc 1 2793 7 is_stmt 1 view .LVU1957 +2793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5872 .loc 1 2793 38 is_stmt 0 view .LVU1958 + 5873 0096 324A ldr r2, .L390+4 + 5874 0098 DA63 str r2, [r3, #60] +2796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5875 .loc 1 2796 7 is_stmt 1 view .LVU1959 +2796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5876 .loc 1 2796 11 is_stmt 0 view .LVU1960 + 5877 009a A36B ldr r3, [r4, #56] + ARM GAS /tmp/ccEimIdZ.s page 252 + + +2796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5878 .loc 1 2796 39 view .LVU1961 + 5879 009c 314A ldr r2, .L390+8 + 5880 009e DA64 str r2, [r3, #76] +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 5881 .loc 1 2799 7 is_stmt 1 view .LVU1962 +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 5882 .loc 1 2799 11 is_stmt 0 view .LVU1963 + 5883 00a0 A26B ldr r2, [r4, #56] +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 5884 .loc 1 2799 42 view .LVU1964 + 5885 00a2 0023 movs r3, #0 + 5886 00a4 1364 str r3, [r2, #64] +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5887 .loc 1 2800 7 is_stmt 1 view .LVU1965 +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5888 .loc 1 2800 11 is_stmt 0 view .LVU1966 + 5889 00a6 A26B ldr r2, [r4, #56] +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5890 .loc 1 2800 39 view .LVU1967 + 5891 00a8 1365 str r3, [r2, #80] +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5892 .loc 1 2803 7 is_stmt 1 view .LVU1968 +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5893 .loc 1 2803 86 is_stmt 0 view .LVU1969 + 5894 00aa 2268 ldr r2, [r4] +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5895 .loc 1 2803 23 view .LVU1970 + 5896 00ac 238D ldrh r3, [r4, #40] + 5897 00ae 2832 adds r2, r2, #40 + 5898 00b0 2946 mov r1, r5 + 5899 00b2 A06B ldr r0, [r4, #56] + 5900 00b4 FFF7FEFF bl HAL_DMA_Start_IT + 5901 .LVL361: +2820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5902 .loc 1 2820 5 is_stmt 1 view .LVU1971 +2820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 5903 .loc 1 2820 8 is_stmt 0 view .LVU1972 + 5904 00b8 0546 mov r5, r0 + 5905 00ba 50B3 cbz r0, .L389 +2844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5906 .loc 1 2844 7 is_stmt 1 view .LVU1973 +2844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5907 .loc 1 2844 23 is_stmt 0 view .LVU1974 + 5908 00bc 2023 movs r3, #32 + 5909 00be 84F84130 strb r3, [r4, #65] +2845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5910 .loc 1 2845 7 is_stmt 1 view .LVU1975 +2845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5911 .loc 1 2845 23 is_stmt 0 view .LVU1976 + 5912 00c2 0022 movs r2, #0 + 5913 00c4 84F84220 strb r2, [r4, #66] +2848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5914 .loc 1 2848 7 is_stmt 1 view .LVU1977 +2848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5915 .loc 1 2848 23 is_stmt 0 view .LVU1978 + 5916 00c8 636C ldr r3, [r4, #68] + ARM GAS /tmp/ccEimIdZ.s page 253 + + + 5917 00ca 43F01003 orr r3, r3, #16 + 5918 00ce 6364 str r3, [r4, #68] +2851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5919 .loc 1 2851 7 is_stmt 1 view .LVU1979 +2851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5920 .loc 1 2851 7 view .LVU1980 + 5921 00d0 84F84020 strb r2, [r4, #64] +2851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5922 .loc 1 2851 7 view .LVU1981 +2853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5923 .loc 1 2853 7 view .LVU1982 +2853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5924 .loc 1 2853 14 is_stmt 0 view .LVU1983 + 5925 00d4 0125 movs r5, #1 + 5926 00d6 38E0 b .L374 + 5927 .LVL362: + 5928 .L387: +2745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5929 .loc 1 2745 7 is_stmt 1 view .LVU1984 +2745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5930 .loc 1 2745 23 is_stmt 0 view .LVU1985 + 5931 00d8 4FF40073 mov r3, #512 + 5932 .LVL363: +2745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5933 .loc 1 2745 23 view .LVU1986 + 5934 00dc 6364 str r3, [r4, #68] +2746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5935 .loc 1 2746 7 is_stmt 1 view .LVU1987 +2746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5936 .loc 1 2746 15 is_stmt 0 view .LVU1988 + 5937 00de 0125 movs r5, #1 + 5938 00e0 33E0 b .L374 + 5939 .LVL364: + 5940 .L376: +2777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5941 .loc 1 2777 7 is_stmt 1 view .LVU1989 +2777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5942 .loc 1 2777 28 is_stmt 0 view .LVU1990 + 5943 00e2 638D ldrh r3, [r4, #42] +2777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5944 .loc 1 2777 22 view .LVU1991 + 5945 00e4 2385 strh r3, [r4, #40] @ movhi +2778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5946 .loc 1 2778 7 is_stmt 1 view .LVU1992 + 5947 .LVL365: +2778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5948 .loc 1 2778 16 is_stmt 0 view .LVU1993 + 5949 00e6 4FF00079 mov r9, #33554432 + 5950 00ea C6E7 b .L377 + 5951 .LVL366: + 5952 .L388: +2785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5953 .loc 1 2785 7 is_stmt 1 view .LVU1994 +2785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5954 .loc 1 2785 7 view .LVU1995 + 5955 00ec 0023 movs r3, #0 + 5956 00ee 84F84030 strb r3, [r4, #64] + ARM GAS /tmp/ccEimIdZ.s page 254 + + +2785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 5957 .loc 1 2785 7 view .LVU1996 +2786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5958 .loc 1 2786 7 view .LVU1997 +2786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5959 .loc 1 2786 14 is_stmt 0 view .LVU1998 + 5960 00f2 0125 movs r5, #1 + 5961 00f4 29E0 b .L374 + 5962 .L379: +2808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5963 .loc 1 2808 7 is_stmt 1 view .LVU1999 +2808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5964 .loc 1 2808 23 is_stmt 0 view .LVU2000 + 5965 00f6 2023 movs r3, #32 + 5966 00f8 84F84130 strb r3, [r4, #65] +2809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5967 .loc 1 2809 7 is_stmt 1 view .LVU2001 +2809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5968 .loc 1 2809 23 is_stmt 0 view .LVU2002 + 5969 00fc 0022 movs r2, #0 + 5970 00fe 84F84220 strb r2, [r4, #66] +2812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5971 .loc 1 2812 7 is_stmt 1 view .LVU2003 +2812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5972 .loc 1 2812 23 is_stmt 0 view .LVU2004 + 5973 0102 636C ldr r3, [r4, #68] + 5974 0104 43F08003 orr r3, r3, #128 + 5975 0108 6364 str r3, [r4, #68] +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5976 .loc 1 2815 7 is_stmt 1 view .LVU2005 +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5977 .loc 1 2815 7 view .LVU2006 + 5978 010a 84F84020 strb r2, [r4, #64] +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5979 .loc 1 2815 7 view .LVU2007 +2817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5980 .loc 1 2817 7 view .LVU2008 +2817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 5981 .loc 1 2817 14 is_stmt 0 view .LVU2009 + 5982 010e 0125 movs r5, #1 + 5983 0110 1BE0 b .L374 + 5984 .LVL367: + 5985 .L389: +2824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5986 .loc 1 2824 7 is_stmt 1 view .LVU2010 + 5987 0112 0027 movs r7, #0 + 5988 0114 0097 str r7, [sp] + 5989 0116 4B46 mov r3, r9 + 5990 0118 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 5991 011c 3146 mov r1, r6 + 5992 011e 2046 mov r0, r4 + 5993 .LVL368: +2824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5994 .loc 1 2824 7 is_stmt 0 view .LVU2011 + 5995 0120 FFF7FEFF bl I2C_TransferConfig + 5996 .LVL369: +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 255 + + + 5997 .loc 1 2827 7 is_stmt 1 view .LVU2012 +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 5998 .loc 1 2827 23 is_stmt 0 view .LVU2013 + 5999 0124 638D ldrh r3, [r4, #42] + 6000 0126 9BB2 uxth r3, r3 +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6001 .loc 1 2827 30 view .LVU2014 + 6002 0128 228D ldrh r2, [r4, #40] +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6003 .loc 1 2827 23 view .LVU2015 + 6004 012a 9B1A subs r3, r3, r2 + 6005 012c 9BB2 uxth r3, r3 + 6006 012e 6385 strh r3, [r4, #42] @ movhi +2830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6007 .loc 1 2830 7 is_stmt 1 view .LVU2016 +2830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6008 .loc 1 2830 7 view .LVU2017 + 6009 0130 84F84070 strb r7, [r4, #64] +2830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6010 .loc 1 2830 7 view .LVU2018 +2836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6011 .loc 1 2836 7 view .LVU2019 + 6012 0134 1021 movs r1, #16 + 6013 0136 2046 mov r0, r4 + 6014 0138 FFF7FEFF bl I2C_Enable_IRQ + 6015 .LVL370: +2839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6016 .loc 1 2839 7 view .LVU2020 +2839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6017 .loc 1 2839 11 is_stmt 0 view .LVU2021 + 6018 013c 2268 ldr r2, [r4] +2839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6019 .loc 1 2839 27 view .LVU2022 + 6020 013e 1368 ldr r3, [r2] + 6021 0140 43F48043 orr r3, r3, #16384 + 6022 0144 1360 str r3, [r2] +2856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6023 .loc 1 2856 5 is_stmt 1 view .LVU2023 +2856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6024 .loc 1 2856 12 is_stmt 0 view .LVU2024 + 6025 0146 00E0 b .L374 + 6026 .LVL371: + 6027 .L382: +2860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6028 .loc 1 2860 12 view .LVU2025 + 6029 0148 0225 movs r5, #2 + 6030 .LVL372: + 6031 .L374: +2862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6032 .loc 1 2862 1 view .LVU2026 + 6033 014a 2846 mov r0, r5 + 6034 014c 03B0 add sp, sp, #12 + 6035 .LCFI73: + 6036 .cfi_remember_state + 6037 .cfi_def_cfa_offset 28 + 6038 @ sp needed + 6039 014e BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + ARM GAS /tmp/ccEimIdZ.s page 256 + + + 6040 .LVL373: + 6041 .L383: + 6042 .LCFI74: + 6043 .cfi_restore_state +2751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6044 .loc 1 2751 14 view .LVU2027 + 6045 0152 0225 movs r5, #2 + 6046 0154 F9E7 b .L374 + 6047 .L384: +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6048 .loc 1 2755 5 view .LVU2028 + 6049 0156 0225 movs r5, #2 + 6050 0158 F7E7 b .L374 + 6051 .L391: + 6052 015a 00BF .align 2 + 6053 .L390: + 6054 015c 00000000 .word I2C_Master_ISR_DMA + 6055 0160 00000000 .word I2C_DMAMasterTransmitCplt + 6056 0164 00000000 .word I2C_DMAError + 6057 .cfi_endproc + 6058 .LFE161: + 6060 .section .text.HAL_I2C_Mem_Read_DMA,"ax",%progbits + 6061 .align 1 + 6062 .global HAL_I2C_Mem_Read_DMA + 6063 .syntax unified + 6064 .thumb + 6065 .thumb_func + 6066 .fpu fpv5-d16 + 6068 HAL_I2C_Mem_Read_DMA: + 6069 .LVL374: + 6070 .LFB162: +2877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 6071 .loc 1 2877 1 is_stmt 1 view -0 + 6072 .cfi_startproc + 6073 @ args = 8, pretend = 0, frame = 0 + 6074 @ frame_needed = 0, uses_anonymous_args = 0 +2877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 6075 .loc 1 2877 1 is_stmt 0 view .LVU2030 + 6076 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 6077 .LCFI75: + 6078 .cfi_def_cfa_offset 28 + 6079 .cfi_offset 4, -28 + 6080 .cfi_offset 5, -24 + 6081 .cfi_offset 6, -20 + 6082 .cfi_offset 7, -16 + 6083 .cfi_offset 8, -12 + 6084 .cfi_offset 9, -8 + 6085 .cfi_offset 14, -4 + 6086 0004 83B0 sub sp, sp, #12 + 6087 .LCFI76: + 6088 .cfi_def_cfa_offset 40 + 6089 0006 0446 mov r4, r0 + 6090 0008 0A9D ldr r5, [sp, #40] + 6091 000a BDF82C90 ldrh r9, [sp, #44] +2878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 6092 .loc 1 2878 3 is_stmt 1 view .LVU2031 +2879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + ARM GAS /tmp/ccEimIdZ.s page 257 + + + 6093 .loc 1 2879 3 view .LVU2032 +2880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6094 .loc 1 2880 3 view .LVU2033 +2883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6095 .loc 1 2883 3 view .LVU2034 +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6096 .loc 1 2885 3 view .LVU2035 +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6097 .loc 1 2885 11 is_stmt 0 view .LVU2036 + 6098 000e 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6099 .LVL375: +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6100 .loc 1 2885 11 view .LVU2037 + 6101 0012 C0B2 uxtb r0, r0 +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6102 .loc 1 2885 6 view .LVU2038 + 6103 0014 2028 cmp r0, #32 + 6104 0016 40F09880 bne .L401 + 6105 001a 0E46 mov r6, r1 + 6106 001c 9046 mov r8, r2 + 6107 001e 1F46 mov r7, r3 +2887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6108 .loc 1 2887 5 is_stmt 1 view .LVU2039 +2887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6109 .loc 1 2887 8 is_stmt 0 view .LVU2040 + 6110 0020 B9F1000F cmp r9, #0 + 6111 0024 18BF it ne + 6112 0026 002D cmpne r5, #0 + 6113 0028 56D0 beq .L406 +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6114 .loc 1 2893 5 is_stmt 1 view .LVU2041 +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6115 .loc 1 2893 9 is_stmt 0 view .LVU2042 + 6116 002a 2368 ldr r3, [r4] + 6117 .LVL376: +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6118 .loc 1 2893 9 view .LVU2043 + 6119 002c 9B69 ldr r3, [r3, #24] +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6120 .loc 1 2893 8 view .LVU2044 + 6121 002e 13F4004F tst r3, #32768 + 6122 0032 40F08F80 bne .L402 +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6123 .loc 1 2899 5 is_stmt 1 view .LVU2045 +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6124 .loc 1 2899 5 view .LVU2046 + 6125 0036 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 6126 003a 012B cmp r3, #1 + 6127 003c 00F08C80 beq .L403 +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6128 .loc 1 2899 5 discriminator 2 view .LVU2047 + 6129 0040 0123 movs r3, #1 + 6130 0042 84F84030 strb r3, [r4, #64] +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6131 .loc 1 2899 5 discriminator 2 view .LVU2048 +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6132 .loc 1 2902 5 discriminator 2 view .LVU2049 + ARM GAS /tmp/ccEimIdZ.s page 258 + + +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6133 .loc 1 2902 17 is_stmt 0 discriminator 2 view .LVU2050 + 6134 0046 FFF7FEFF bl HAL_GetTick + 6135 .LVL377: +2904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6136 .loc 1 2904 5 is_stmt 1 discriminator 2 view .LVU2051 +2904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6137 .loc 1 2904 23 is_stmt 0 discriminator 2 view .LVU2052 + 6138 004a 2223 movs r3, #34 + 6139 004c 84F84130 strb r3, [r4, #65] +2905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6140 .loc 1 2905 5 is_stmt 1 discriminator 2 view .LVU2053 +2905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6141 .loc 1 2905 23 is_stmt 0 discriminator 2 view .LVU2054 + 6142 0050 4023 movs r3, #64 + 6143 0052 84F84230 strb r3, [r4, #66] +2906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6144 .loc 1 2906 5 is_stmt 1 discriminator 2 view .LVU2055 +2906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6145 .loc 1 2906 23 is_stmt 0 discriminator 2 view .LVU2056 + 6146 0056 0023 movs r3, #0 + 6147 0058 6364 str r3, [r4, #68] +2909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6148 .loc 1 2909 5 is_stmt 1 discriminator 2 view .LVU2057 +2909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6149 .loc 1 2909 23 is_stmt 0 discriminator 2 view .LVU2058 + 6150 005a 6562 str r5, [r4, #36] +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6151 .loc 1 2910 5 is_stmt 1 discriminator 2 view .LVU2059 +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6152 .loc 1 2910 23 is_stmt 0 discriminator 2 view .LVU2060 + 6153 005c A4F82A90 strh r9, [r4, #42] @ movhi +2911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6154 .loc 1 2911 5 is_stmt 1 discriminator 2 view .LVU2061 +2911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6155 .loc 1 2911 23 is_stmt 0 discriminator 2 view .LVU2062 + 6156 0060 A3F58033 sub r3, r3, #65536 + 6157 0064 E362 str r3, [r4, #44] +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6158 .loc 1 2912 5 is_stmt 1 discriminator 2 view .LVU2063 +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6159 .loc 1 2912 23 is_stmt 0 discriminator 2 view .LVU2064 + 6160 0066 3D4B ldr r3, .L409 + 6161 0068 6363 str r3, [r4, #52] +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6162 .loc 1 2914 5 is_stmt 1 discriminator 2 view .LVU2065 +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6163 .loc 1 2914 13 is_stmt 0 discriminator 2 view .LVU2066 + 6164 006a 638D ldrh r3, [r4, #42] + 6165 006c 9BB2 uxth r3, r3 +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6166 .loc 1 2914 8 discriminator 2 view .LVU2067 + 6167 006e FF2B cmp r3, #255 + 6168 0070 37D9 bls .L395 +2916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6169 .loc 1 2916 7 is_stmt 1 view .LVU2068 +2916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + ARM GAS /tmp/ccEimIdZ.s page 259 + + + 6170 .loc 1 2916 22 is_stmt 0 view .LVU2069 + 6171 0072 FF23 movs r3, #255 + 6172 0074 2385 strh r3, [r4, #40] @ movhi +2917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6173 .loc 1 2917 7 is_stmt 1 view .LVU2070 + 6174 .LVL378: +2917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6175 .loc 1 2917 16 is_stmt 0 view .LVU2071 + 6176 0076 4FF08079 mov r9, #16777216 + 6177 .LVL379: + 6178 .L396: +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6179 .loc 1 2926 5 is_stmt 1 view .LVU2072 +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6180 .loc 1 2926 9 is_stmt 0 view .LVU2073 + 6181 007a 0190 str r0, [sp, #4] + 6182 007c 1923 movs r3, #25 + 6183 007e 0093 str r3, [sp] + 6184 0080 3B46 mov r3, r7 + 6185 0082 4246 mov r2, r8 + 6186 0084 3146 mov r1, r6 + 6187 0086 2046 mov r0, r4 + 6188 .LVL380: +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6189 .loc 1 2926 9 view .LVU2074 + 6190 0088 FFF7FEFF bl I2C_RequestMemoryRead + 6191 .LVL381: +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6192 .loc 1 2926 8 view .LVU2075 + 6193 008c 0028 cmp r0, #0 + 6194 008e 2DD1 bne .L407 +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6195 .loc 1 2933 5 is_stmt 1 view .LVU2076 +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6196 .loc 1 2933 13 is_stmt 0 view .LVU2077 + 6197 0090 E36B ldr r3, [r4, #60] +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6198 .loc 1 2933 8 view .LVU2078 + 6199 0092 002B cmp r3, #0 + 6200 0094 2FD0 beq .L398 +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6201 .loc 1 2936 7 is_stmt 1 view .LVU2079 +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6202 .loc 1 2936 38 is_stmt 0 view .LVU2080 + 6203 0096 324A ldr r2, .L409+4 + 6204 0098 DA63 str r2, [r3, #60] +2939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6205 .loc 1 2939 7 is_stmt 1 view .LVU2081 +2939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6206 .loc 1 2939 11 is_stmt 0 view .LVU2082 + 6207 009a E36B ldr r3, [r4, #60] +2939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6208 .loc 1 2939 39 view .LVU2083 + 6209 009c 314A ldr r2, .L409+8 + 6210 009e DA64 str r2, [r3, #76] +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6211 .loc 1 2942 7 is_stmt 1 view .LVU2084 + ARM GAS /tmp/ccEimIdZ.s page 260 + + +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6212 .loc 1 2942 11 is_stmt 0 view .LVU2085 + 6213 00a0 E26B ldr r2, [r4, #60] +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6214 .loc 1 2942 42 view .LVU2086 + 6215 00a2 0023 movs r3, #0 + 6216 00a4 1364 str r3, [r2, #64] +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6217 .loc 1 2943 7 is_stmt 1 view .LVU2087 +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6218 .loc 1 2943 11 is_stmt 0 view .LVU2088 + 6219 00a6 E26B ldr r2, [r4, #60] +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6220 .loc 1 2943 39 view .LVU2089 + 6221 00a8 1365 str r3, [r2, #80] +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6222 .loc 1 2946 7 is_stmt 1 view .LVU2090 +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6223 .loc 1 2946 69 is_stmt 0 view .LVU2091 + 6224 00aa 2168 ldr r1, [r4] +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6225 .loc 1 2946 23 view .LVU2092 + 6226 00ac 238D ldrh r3, [r4, #40] + 6227 00ae 2A46 mov r2, r5 + 6228 00b0 2431 adds r1, r1, #36 + 6229 00b2 E06B ldr r0, [r4, #60] + 6230 00b4 FFF7FEFF bl HAL_DMA_Start_IT + 6231 .LVL382: +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6232 .loc 1 2963 5 is_stmt 1 view .LVU2093 +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6233 .loc 1 2963 8 is_stmt 0 view .LVU2094 + 6234 00b8 0546 mov r5, r0 + 6235 00ba 50B3 cbz r0, .L408 +2986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6236 .loc 1 2986 7 is_stmt 1 view .LVU2095 +2986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6237 .loc 1 2986 23 is_stmt 0 view .LVU2096 + 6238 00bc 2023 movs r3, #32 + 6239 00be 84F84130 strb r3, [r4, #65] +2987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6240 .loc 1 2987 7 is_stmt 1 view .LVU2097 +2987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6241 .loc 1 2987 23 is_stmt 0 view .LVU2098 + 6242 00c2 0022 movs r2, #0 + 6243 00c4 84F84220 strb r2, [r4, #66] +2990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6244 .loc 1 2990 7 is_stmt 1 view .LVU2099 +2990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6245 .loc 1 2990 23 is_stmt 0 view .LVU2100 + 6246 00c8 636C ldr r3, [r4, #68] + 6247 00ca 43F01003 orr r3, r3, #16 + 6248 00ce 6364 str r3, [r4, #68] +2993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6249 .loc 1 2993 7 is_stmt 1 view .LVU2101 +2993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6250 .loc 1 2993 7 view .LVU2102 + ARM GAS /tmp/ccEimIdZ.s page 261 + + + 6251 00d0 84F84020 strb r2, [r4, #64] +2993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6252 .loc 1 2993 7 view .LVU2103 +2995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6253 .loc 1 2995 7 view .LVU2104 +2995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6254 .loc 1 2995 14 is_stmt 0 view .LVU2105 + 6255 00d4 0125 movs r5, #1 + 6256 00d6 39E0 b .L393 + 6257 .LVL383: + 6258 .L406: +2889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 6259 .loc 1 2889 7 is_stmt 1 view .LVU2106 +2889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 6260 .loc 1 2889 23 is_stmt 0 view .LVU2107 + 6261 00d8 4FF40073 mov r3, #512 + 6262 .LVL384: +2889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 6263 .loc 1 2889 23 view .LVU2108 + 6264 00dc 6364 str r3, [r4, #68] +2890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6265 .loc 1 2890 7 is_stmt 1 view .LVU2109 +2890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6266 .loc 1 2890 15 is_stmt 0 view .LVU2110 + 6267 00de 0125 movs r5, #1 + 6268 00e0 34E0 b .L393 + 6269 .LVL385: + 6270 .L395: +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6271 .loc 1 2921 7 is_stmt 1 view .LVU2111 +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6272 .loc 1 2921 28 is_stmt 0 view .LVU2112 + 6273 00e2 638D ldrh r3, [r4, #42] +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6274 .loc 1 2921 22 view .LVU2113 + 6275 00e4 2385 strh r3, [r4, #40] @ movhi +2922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6276 .loc 1 2922 7 is_stmt 1 view .LVU2114 + 6277 .LVL386: +2922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6278 .loc 1 2922 16 is_stmt 0 view .LVU2115 + 6279 00e6 4FF00079 mov r9, #33554432 + 6280 00ea C6E7 b .L396 + 6281 .LVL387: + 6282 .L407: +2929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 6283 .loc 1 2929 7 is_stmt 1 view .LVU2116 +2929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 6284 .loc 1 2929 7 view .LVU2117 + 6285 00ec 0023 movs r3, #0 + 6286 00ee 84F84030 strb r3, [r4, #64] +2929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 6287 .loc 1 2929 7 view .LVU2118 +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6288 .loc 1 2930 7 view .LVU2119 +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6289 .loc 1 2930 14 is_stmt 0 view .LVU2120 + ARM GAS /tmp/ccEimIdZ.s page 262 + + + 6290 00f2 0125 movs r5, #1 + 6291 00f4 2AE0 b .L393 + 6292 .L398: +2951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6293 .loc 1 2951 7 is_stmt 1 view .LVU2121 +2951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6294 .loc 1 2951 23 is_stmt 0 view .LVU2122 + 6295 00f6 2023 movs r3, #32 + 6296 00f8 84F84130 strb r3, [r4, #65] +2952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6297 .loc 1 2952 7 is_stmt 1 view .LVU2123 +2952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6298 .loc 1 2952 23 is_stmt 0 view .LVU2124 + 6299 00fc 0022 movs r2, #0 + 6300 00fe 84F84220 strb r2, [r4, #66] +2955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6301 .loc 1 2955 7 is_stmt 1 view .LVU2125 +2955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6302 .loc 1 2955 23 is_stmt 0 view .LVU2126 + 6303 0102 636C ldr r3, [r4, #68] + 6304 0104 43F08003 orr r3, r3, #128 + 6305 0108 6364 str r3, [r4, #68] +2958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6306 .loc 1 2958 7 is_stmt 1 view .LVU2127 +2958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6307 .loc 1 2958 7 view .LVU2128 + 6308 010a 84F84020 strb r2, [r4, #64] +2958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6309 .loc 1 2958 7 view .LVU2129 +2960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6310 .loc 1 2960 7 view .LVU2130 +2960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6311 .loc 1 2960 14 is_stmt 0 view .LVU2131 + 6312 010e 0125 movs r5, #1 + 6313 0110 1CE0 b .L393 + 6314 .LVL388: + 6315 .L408: +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6316 .loc 1 2966 7 is_stmt 1 view .LVU2132 + 6317 0112 154B ldr r3, .L409+12 + 6318 0114 0093 str r3, [sp] + 6319 0116 4B46 mov r3, r9 + 6320 0118 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 6321 011c 3146 mov r1, r6 + 6322 011e 2046 mov r0, r4 + 6323 .LVL389: +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6324 .loc 1 2966 7 is_stmt 0 view .LVU2133 + 6325 0120 FFF7FEFF bl I2C_TransferConfig + 6326 .LVL390: +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6327 .loc 1 2969 7 is_stmt 1 view .LVU2134 +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6328 .loc 1 2969 23 is_stmt 0 view .LVU2135 + 6329 0124 638D ldrh r3, [r4, #42] + 6330 0126 9BB2 uxth r3, r3 +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 263 + + + 6331 .loc 1 2969 30 view .LVU2136 + 6332 0128 228D ldrh r2, [r4, #40] +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6333 .loc 1 2969 23 view .LVU2137 + 6334 012a 9B1A subs r3, r3, r2 + 6335 012c 9BB2 uxth r3, r3 + 6336 012e 6385 strh r3, [r4, #42] @ movhi +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6337 .loc 1 2972 7 is_stmt 1 view .LVU2138 +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6338 .loc 1 2972 7 view .LVU2139 + 6339 0130 0023 movs r3, #0 + 6340 0132 84F84030 strb r3, [r4, #64] +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6341 .loc 1 2972 7 view .LVU2140 +2978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6342 .loc 1 2978 7 view .LVU2141 + 6343 0136 1021 movs r1, #16 + 6344 0138 2046 mov r0, r4 + 6345 013a FFF7FEFF bl I2C_Enable_IRQ + 6346 .LVL391: +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6347 .loc 1 2981 7 view .LVU2142 +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6348 .loc 1 2981 11 is_stmt 0 view .LVU2143 + 6349 013e 2268 ldr r2, [r4] +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6350 .loc 1 2981 27 view .LVU2144 + 6351 0140 1368 ldr r3, [r2] + 6352 0142 43F40043 orr r3, r3, #32768 + 6353 0146 1360 str r3, [r2] +2998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6354 .loc 1 2998 5 is_stmt 1 view .LVU2145 +2998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6355 .loc 1 2998 12 is_stmt 0 view .LVU2146 + 6356 0148 00E0 b .L393 + 6357 .LVL392: + 6358 .L401: +3002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6359 .loc 1 3002 12 view .LVU2147 + 6360 014a 0225 movs r5, #2 + 6361 .LVL393: + 6362 .L393: +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6363 .loc 1 3004 1 view .LVU2148 + 6364 014c 2846 mov r0, r5 + 6365 014e 03B0 add sp, sp, #12 + 6366 .LCFI77: + 6367 .cfi_remember_state + 6368 .cfi_def_cfa_offset 28 + 6369 @ sp needed + 6370 0150 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 6371 .LVL394: + 6372 .L402: + 6373 .LCFI78: + 6374 .cfi_restore_state +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 264 + + + 6375 .loc 1 2895 14 view .LVU2149 + 6376 0154 0225 movs r5, #2 + 6377 0156 F9E7 b .L393 + 6378 .L403: +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6379 .loc 1 2899 5 view .LVU2150 + 6380 0158 0225 movs r5, #2 + 6381 015a F7E7 b .L393 + 6382 .L410: + 6383 .align 2 + 6384 .L409: + 6385 015c 00000000 .word I2C_Master_ISR_DMA + 6386 0160 00000000 .word I2C_DMAMasterReceiveCplt + 6387 0164 00000000 .word I2C_DMAError + 6388 0168 00240080 .word -2147474432 + 6389 .cfi_endproc + 6390 .LFE162: + 6392 .section .text.HAL_I2C_IsDeviceReady,"ax",%progbits + 6393 .align 1 + 6394 .global HAL_I2C_IsDeviceReady + 6395 .syntax unified + 6396 .thumb + 6397 .thumb_func + 6398 .fpu fpv5-d16 + 6400 HAL_I2C_IsDeviceReady: + 6401 .LVL395: + 6402 .LFB163: +3018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 6403 .loc 1 3018 1 is_stmt 1 view -0 + 6404 .cfi_startproc + 6405 @ args = 0, pretend = 0, frame = 8 + 6406 @ frame_needed = 0, uses_anonymous_args = 0 +3018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tickstart; + 6407 .loc 1 3018 1 is_stmt 0 view .LVU2152 + 6408 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 6409 .LCFI79: + 6410 .cfi_def_cfa_offset 28 + 6411 .cfi_offset 4, -28 + 6412 .cfi_offset 5, -24 + 6413 .cfi_offset 6, -20 + 6414 .cfi_offset 7, -16 + 6415 .cfi_offset 8, -12 + 6416 .cfi_offset 9, -8 + 6417 .cfi_offset 14, -4 + 6418 0004 85B0 sub sp, sp, #20 + 6419 .LCFI80: + 6420 .cfi_def_cfa_offset 48 + 6421 0006 1D46 mov r5, r3 +3019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6422 .loc 1 3019 3 is_stmt 1 view .LVU2153 +3021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6423 .loc 1 3021 3 view .LVU2154 +3021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6424 .loc 1 3021 17 is_stmt 0 view .LVU2155 + 6425 0008 0023 movs r3, #0 + 6426 .LVL396: +3021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 265 + + + 6427 .loc 1 3021 17 view .LVU2156 + 6428 000a 0393 str r3, [sp, #12] +3023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** FlagStatus tmp2; + 6429 .loc 1 3023 3 is_stmt 1 view .LVU2157 +3024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6430 .loc 1 3024 3 view .LVU2158 +3026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6431 .loc 1 3026 3 view .LVU2159 +3026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6432 .loc 1 3026 11 is_stmt 0 view .LVU2160 + 6433 000c 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 6434 0010 DBB2 uxtb r3, r3 +3026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6435 .loc 1 3026 6 view .LVU2161 + 6436 0012 202B cmp r3, #32 + 6437 0014 40F09C80 bne .L422 + 6438 0018 0646 mov r6, r0 + 6439 001a 8946 mov r9, r1 + 6440 001c 9046 mov r8, r2 +3028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6441 .loc 1 3028 5 is_stmt 1 view .LVU2162 +3028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6442 .loc 1 3028 9 is_stmt 0 view .LVU2163 + 6443 001e 0368 ldr r3, [r0] + 6444 0020 9B69 ldr r3, [r3, #24] +3028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6445 .loc 1 3028 8 view .LVU2164 + 6446 0022 13F4004F tst r3, #32768 + 6447 0026 40F09580 bne .L423 +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6448 .loc 1 3034 5 is_stmt 1 view .LVU2165 +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6449 .loc 1 3034 5 view .LVU2166 + 6450 002a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 6451 002e 012B cmp r3, #1 + 6452 0030 00F09280 beq .L424 +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6453 .loc 1 3034 5 discriminator 2 view .LVU2167 + 6454 0034 0123 movs r3, #1 + 6455 0036 80F84030 strb r3, [r0, #64] +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6456 .loc 1 3034 5 discriminator 2 view .LVU2168 +3036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6457 .loc 1 3036 5 discriminator 2 view .LVU2169 +3036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6458 .loc 1 3036 17 is_stmt 0 discriminator 2 view .LVU2170 + 6459 003a 2423 movs r3, #36 + 6460 003c 80F84130 strb r3, [r0, #65] +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6461 .loc 1 3037 5 is_stmt 1 discriminator 2 view .LVU2171 +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6462 .loc 1 3037 21 is_stmt 0 discriminator 2 view .LVU2172 + 6463 0040 0023 movs r3, #0 + 6464 0042 4364 str r3, [r0, #68] + 6465 .LVL397: + 6466 .L421: +3039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 266 + + + 6467 .loc 1 3039 5 is_stmt 1 view .LVU2173 +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6468 .loc 1 3042 7 view .LVU2174 +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6469 .loc 1 3042 29 is_stmt 0 view .LVU2175 + 6470 0044 F368 ldr r3, [r6, #12] + 6471 0046 012B cmp r3, #1 + 6472 0048 10D0 beq .L429 +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6473 .loc 1 3042 29 discriminator 2 view .LVU2176 + 6474 004a C9F30903 ubfx r3, r9, #0, #10 + 6475 004e 43F42053 orr r3, r3, #10240 + 6476 .L414: +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6477 .loc 1 3042 11 discriminator 4 view .LVU2177 + 6478 0052 3268 ldr r2, [r6] +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6479 .loc 1 3042 27 discriminator 4 view .LVU2178 + 6480 0054 5360 str r3, [r2, #4] +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6481 .loc 1 3046 7 is_stmt 1 discriminator 4 view .LVU2179 +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6482 .loc 1 3046 19 is_stmt 0 discriminator 4 view .LVU2180 + 6483 0056 FFF7FEFF bl HAL_GetTick + 6484 .LVL398: + 6485 005a 0746 mov r7, r0 + 6486 .LVL399: +3048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6487 .loc 1 3048 7 is_stmt 1 discriminator 4 view .LVU2181 +3048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6488 .loc 1 3048 14 is_stmt 0 discriminator 4 view .LVU2182 + 6489 005c 3268 ldr r2, [r6] + 6490 005e 9369 ldr r3, [r2, #24] + 6491 0060 C3F34013 ubfx r3, r3, #5, #1 + 6492 .LVL400: +3049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6493 .loc 1 3049 7 is_stmt 1 discriminator 4 view .LVU2183 +3049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6494 .loc 1 3049 14 is_stmt 0 discriminator 4 view .LVU2184 + 6495 0064 9469 ldr r4, [r2, #24] + 6496 0066 C4F3001C ubfx ip, r4, #4, #1 + 6497 .LVL401: +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6498 .loc 1 3051 7 is_stmt 1 discriminator 4 view .LVU2185 +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6499 .loc 1 3051 13 is_stmt 0 discriminator 4 view .LVU2186 + 6500 006a 0BE0 b .L415 + 6501 .LVL402: + 6502 .L429: +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6503 .loc 1 3042 29 discriminator 1 view .LVU2187 + 6504 006c C9F30902 ubfx r2, r9, #0, #10 + 6505 0070 3D4B ldr r3, .L433 + 6506 0072 1343 orrs r3, r3, r2 + 6507 0074 EDE7 b .L414 + 6508 .LVL403: + 6509 .L416: + ARM GAS /tmp/ccEimIdZ.s page 267 + + +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6510 .loc 1 3070 9 is_stmt 1 view .LVU2188 +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6511 .loc 1 3070 16 is_stmt 0 view .LVU2189 + 6512 0076 3268 ldr r2, [r6] + 6513 0078 9369 ldr r3, [r2, #24] + 6514 007a C3F34013 ubfx r3, r3, #5, #1 + 6515 .LVL404: +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6516 .loc 1 3071 9 is_stmt 1 view .LVU2190 +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6517 .loc 1 3071 16 is_stmt 0 view .LVU2191 + 6518 007e 9469 ldr r4, [r2, #24] + 6519 0080 C4F3001C ubfx ip, r4, #4, #1 + 6520 .LVL405: + 6521 .L415: +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6522 .loc 1 3051 13 is_stmt 1 view .LVU2192 + 6523 0084 53EA0C03 orrs r3, r3, ip + 6524 .LVL406: +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6525 .loc 1 3051 13 is_stmt 0 view .LVU2193 + 6526 0088 17D1 bne .L430 +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6527 .loc 1 3053 9 is_stmt 1 view .LVU2194 +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6528 .loc 1 3053 12 is_stmt 0 view .LVU2195 + 6529 008a B5F1FF3F cmp r5, #-1 + 6530 008e F2D0 beq .L416 +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6531 .loc 1 3055 11 is_stmt 1 view .LVU2196 +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6532 .loc 1 3055 17 is_stmt 0 view .LVU2197 + 6533 0090 FFF7FEFF bl HAL_GetTick + 6534 .LVL407: +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6535 .loc 1 3055 31 view .LVU2198 + 6536 0094 C01B subs r0, r0, r7 +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6537 .loc 1 3055 14 view .LVU2199 + 6538 0096 A842 cmp r0, r5 + 6539 0098 01D8 bhi .L417 +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6540 .loc 1 3055 55 discriminator 1 view .LVU2200 + 6541 009a 002D cmp r5, #0 + 6542 009c EBD1 bne .L416 + 6543 .L417: +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6544 .loc 1 3058 13 is_stmt 1 view .LVU2201 +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6545 .loc 1 3058 25 is_stmt 0 view .LVU2202 + 6546 009e 2023 movs r3, #32 + 6547 00a0 86F84130 strb r3, [r6, #65] +3061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6548 .loc 1 3061 13 is_stmt 1 view .LVU2203 +3061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6549 .loc 1 3061 29 is_stmt 0 view .LVU2204 + ARM GAS /tmp/ccEimIdZ.s page 268 + + + 6550 00a4 736C ldr r3, [r6, #68] + 6551 00a6 43F02003 orr r3, r3, #32 + 6552 00aa 7364 str r3, [r6, #68] +3064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6553 .loc 1 3064 13 is_stmt 1 view .LVU2205 +3064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6554 .loc 1 3064 13 view .LVU2206 + 6555 00ac 0023 movs r3, #0 + 6556 00ae 86F84030 strb r3, [r6, #64] +3064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6557 .loc 1 3064 13 view .LVU2207 +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6558 .loc 1 3066 13 view .LVU2208 +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6559 .loc 1 3066 20 is_stmt 0 view .LVU2209 + 6560 00b2 0120 movs r0, #1 + 6561 .LVL408: + 6562 .L412: +3145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6563 .loc 1 3145 1 view .LVU2210 + 6564 00b4 05B0 add sp, sp, #20 + 6565 .LCFI81: + 6566 .cfi_remember_state + 6567 .cfi_def_cfa_offset 28 + 6568 @ sp needed + 6569 00b6 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 6570 .LVL409: + 6571 .L430: + 6572 .LCFI82: + 6573 .cfi_restore_state +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6574 .loc 1 3075 7 is_stmt 1 view .LVU2211 +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6575 .loc 1 3075 11 is_stmt 0 view .LVU2212 + 6576 00ba 3368 ldr r3, [r6] + 6577 00bc 9B69 ldr r3, [r3, #24] +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6578 .loc 1 3075 10 view .LVU2213 + 6579 00be 13F0100F tst r3, #16 + 6580 00c2 23D0 beq .L431 +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6581 .loc 1 3097 9 is_stmt 1 view .LVU2214 +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6582 .loc 1 3097 13 is_stmt 0 view .LVU2215 + 6583 00c4 0097 str r7, [sp] + 6584 00c6 2B46 mov r3, r5 + 6585 00c8 0022 movs r2, #0 + 6586 00ca 2021 movs r1, #32 + 6587 00cc 3046 mov r0, r6 + 6588 00ce FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6589 .LVL410: +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6590 .loc 1 3097 12 view .LVU2216 + 6591 00d2 0028 cmp r0, #0 + 6592 00d4 44D1 bne .L426 +3103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6593 .loc 1 3103 9 is_stmt 1 view .LVU2217 + ARM GAS /tmp/ccEimIdZ.s page 269 + + + 6594 00d6 3368 ldr r3, [r6] + 6595 00d8 1022 movs r2, #16 + 6596 00da DA61 str r2, [r3, #28] +3106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6597 .loc 1 3106 9 view .LVU2218 + 6598 00dc 3368 ldr r3, [r6] + 6599 00de 2022 movs r2, #32 + 6600 00e0 DA61 str r2, [r3, #28] +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6601 .loc 1 3110 7 view .LVU2219 +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6602 .loc 1 3110 22 is_stmt 0 view .LVU2220 + 6603 00e2 039B ldr r3, [sp, #12] +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6604 .loc 1 3110 10 view .LVU2221 + 6605 00e4 4345 cmp r3, r8 + 6606 00e6 22D0 beq .L432 + 6607 .L420: +3126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6608 .loc 1 3126 7 is_stmt 1 view .LVU2222 +3126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6609 .loc 1 3126 17 is_stmt 0 view .LVU2223 + 6610 00e8 039B ldr r3, [sp, #12] + 6611 00ea 0133 adds r3, r3, #1 + 6612 00ec 0393 str r3, [sp, #12] +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6613 .loc 1 3128 11 is_stmt 1 view .LVU2224 +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6614 .loc 1 3128 23 is_stmt 0 view .LVU2225 + 6615 00ee 039B ldr r3, [sp, #12] +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6616 .loc 1 3128 5 view .LVU2226 + 6617 00f0 4345 cmp r3, r8 + 6618 00f2 A7D3 bcc .L421 +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6619 .loc 1 3131 5 is_stmt 1 view .LVU2227 +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6620 .loc 1 3131 17 is_stmt 0 view .LVU2228 + 6621 00f4 2023 movs r3, #32 + 6622 00f6 86F84130 strb r3, [r6, #65] +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6623 .loc 1 3134 5 is_stmt 1 view .LVU2229 +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6624 .loc 1 3134 21 is_stmt 0 view .LVU2230 + 6625 00fa 736C ldr r3, [r6, #68] + 6626 00fc 43F02003 orr r3, r3, #32 + 6627 0100 7364 str r3, [r6, #68] +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6628 .loc 1 3137 5 is_stmt 1 view .LVU2231 +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6629 .loc 1 3137 5 view .LVU2232 + 6630 0102 0023 movs r3, #0 + 6631 0104 86F84030 strb r3, [r6, #64] +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6632 .loc 1 3137 5 view .LVU2233 +3139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6633 .loc 1 3139 5 view .LVU2234 + ARM GAS /tmp/ccEimIdZ.s page 270 + + +3139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6634 .loc 1 3139 12 is_stmt 0 view .LVU2235 + 6635 0108 0120 movs r0, #1 + 6636 010a D3E7 b .L412 + 6637 .LVL411: + 6638 .L431: +3078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6639 .loc 1 3078 9 is_stmt 1 view .LVU2236 +3078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6640 .loc 1 3078 13 is_stmt 0 view .LVU2237 + 6641 010c 0097 str r7, [sp] + 6642 010e 2B46 mov r3, r5 + 6643 0110 0022 movs r2, #0 + 6644 0112 2021 movs r1, #32 + 6645 0114 3046 mov r0, r6 + 6646 0116 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6647 .LVL412: +3078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6648 .loc 1 3078 12 view .LVU2238 + 6649 011a F8B9 cbnz r0, .L425 +3084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6650 .loc 1 3084 9 is_stmt 1 view .LVU2239 + 6651 011c 3268 ldr r2, [r6] + 6652 011e 2023 movs r3, #32 + 6653 0120 D361 str r3, [r2, #28] +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6654 .loc 1 3087 9 view .LVU2240 +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6655 .loc 1 3087 21 is_stmt 0 view .LVU2241 + 6656 0122 86F84130 strb r3, [r6, #65] +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6657 .loc 1 3090 9 is_stmt 1 view .LVU2242 +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6658 .loc 1 3090 9 view .LVU2243 + 6659 0126 0023 movs r3, #0 + 6660 0128 86F84030 strb r3, [r6, #64] +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6661 .loc 1 3090 9 view .LVU2244 +3092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6662 .loc 1 3092 9 view .LVU2245 +3092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6663 .loc 1 3092 16 is_stmt 0 view .LVU2246 + 6664 012c C2E7 b .L412 + 6665 .L432: +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6666 .loc 1 3113 9 is_stmt 1 view .LVU2247 +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6667 .loc 1 3113 13 is_stmt 0 view .LVU2248 + 6668 012e 3268 ldr r2, [r6] +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6669 .loc 1 3113 29 view .LVU2249 + 6670 0130 5368 ldr r3, [r2, #4] + 6671 0132 43F48043 orr r3, r3, #16384 + 6672 0136 5360 str r3, [r2, #4] +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6673 .loc 1 3116 9 is_stmt 1 view .LVU2250 +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 271 + + + 6674 .loc 1 3116 13 is_stmt 0 view .LVU2251 + 6675 0138 0097 str r7, [sp] + 6676 013a 2B46 mov r3, r5 + 6677 013c 0022 movs r2, #0 + 6678 013e 2021 movs r1, #32 + 6679 0140 3046 mov r0, r6 + 6680 0142 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6681 .LVL413: +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6682 .loc 1 3116 12 view .LVU2252 + 6683 0146 68B9 cbnz r0, .L427 +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6684 .loc 1 3122 9 is_stmt 1 view .LVU2253 + 6685 0148 3368 ldr r3, [r6] + 6686 014a 2022 movs r2, #32 + 6687 014c DA61 str r2, [r3, #28] + 6688 014e CBE7 b .L420 + 6689 .LVL414: + 6690 .L422: +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6691 .loc 1 3143 12 is_stmt 0 view .LVU2254 + 6692 0150 0220 movs r0, #2 + 6693 .LVL415: +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6694 .loc 1 3143 12 view .LVU2255 + 6695 0152 AFE7 b .L412 + 6696 .LVL416: + 6697 .L423: +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6698 .loc 1 3030 14 view .LVU2256 + 6699 0154 0220 movs r0, #2 + 6700 .LVL417: +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6701 .loc 1 3030 14 view .LVU2257 + 6702 0156 ADE7 b .L412 + 6703 .LVL418: + 6704 .L424: +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6705 .loc 1 3034 5 view .LVU2258 + 6706 0158 0220 movs r0, #2 + 6707 .LVL419: +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6708 .loc 1 3034 5 view .LVU2259 + 6709 015a ABE7 b .L412 + 6710 .LVL420: + 6711 .L425: +3080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6712 .loc 1 3080 18 view .LVU2260 + 6713 015c 0120 movs r0, #1 + 6714 015e A9E7 b .L412 + 6715 .L426: +3099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6716 .loc 1 3099 18 view .LVU2261 + 6717 0160 0120 movs r0, #1 + 6718 0162 A7E7 b .L412 + 6719 .L427: +3118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 272 + + + 6720 .loc 1 3118 18 view .LVU2262 + 6721 0164 0120 movs r0, #1 + 6722 0166 A5E7 b .L412 + 6723 .L434: + 6724 .align 2 + 6725 .L433: + 6726 0168 00200002 .word 33562624 + 6727 .cfi_endproc + 6728 .LFE163: + 6730 .section .text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits + 6731 .align 1 + 6732 .global HAL_I2C_Master_Seq_Transmit_IT + 6733 .syntax unified + 6734 .thumb + 6735 .thumb_func + 6736 .fpu fpv5-d16 + 6738 HAL_I2C_Master_Seq_Transmit_IT: + 6739 .LVL421: + 6740 .LFB164: +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 6741 .loc 1 3160 1 is_stmt 1 view -0 + 6742 .cfi_startproc + 6743 @ args = 4, pretend = 0, frame = 0 + 6744 @ frame_needed = 0, uses_anonymous_args = 0 +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 6745 .loc 1 3160 1 is_stmt 0 view .LVU2264 + 6746 0000 70B5 push {r4, r5, r6, lr} + 6747 .LCFI83: + 6748 .cfi_def_cfa_offset 16 + 6749 .cfi_offset 4, -16 + 6750 .cfi_offset 5, -12 + 6751 .cfi_offset 6, -8 + 6752 .cfi_offset 14, -4 + 6753 0002 82B0 sub sp, sp, #8 + 6754 .LCFI84: + 6755 .cfi_def_cfa_offset 24 + 6756 0004 0446 mov r4, r0 + 6757 0006 0D46 mov r5, r1 + 6758 0008 0699 ldr r1, [sp, #24] + 6759 .LVL422: +3161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 6760 .loc 1 3161 3 is_stmt 1 view .LVU2265 +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6761 .loc 1 3162 3 view .LVU2266 +3165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6762 .loc 1 3165 3 view .LVU2267 +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6763 .loc 1 3167 3 view .LVU2268 +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6764 .loc 1 3167 11 is_stmt 0 view .LVU2269 + 6765 000a 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6766 .LVL423: +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6767 .loc 1 3167 11 view .LVU2270 + 6768 000e C0B2 uxtb r0, r0 +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6769 .loc 1 3167 6 view .LVU2271 + ARM GAS /tmp/ccEimIdZ.s page 273 + + + 6770 0010 2028 cmp r0, #32 + 6771 0012 46D1 bne .L441 +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6772 .loc 1 3170 5 is_stmt 1 view .LVU2272 +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6773 .loc 1 3170 5 view .LVU2273 + 6774 0014 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 6775 0018 0128 cmp r0, #1 + 6776 001a 44D0 beq .L442 +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6777 .loc 1 3170 5 discriminator 2 view .LVU2274 + 6778 001c 0120 movs r0, #1 + 6779 001e 84F84000 strb r0, [r4, #64] +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6780 .loc 1 3170 5 discriminator 2 view .LVU2275 +3172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6781 .loc 1 3172 5 discriminator 2 view .LVU2276 +3172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6782 .loc 1 3172 21 is_stmt 0 discriminator 2 view .LVU2277 + 6783 0022 2120 movs r0, #33 + 6784 0024 84F84100 strb r0, [r4, #65] +3173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6785 .loc 1 3173 5 is_stmt 1 discriminator 2 view .LVU2278 +3173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6786 .loc 1 3173 21 is_stmt 0 discriminator 2 view .LVU2279 + 6787 0028 1020 movs r0, #16 + 6788 002a 84F84200 strb r0, [r4, #66] +3174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6789 .loc 1 3174 5 is_stmt 1 discriminator 2 view .LVU2280 +3174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6790 .loc 1 3174 21 is_stmt 0 discriminator 2 view .LVU2281 + 6791 002e 0020 movs r0, #0 + 6792 0030 6064 str r0, [r4, #68] +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6793 .loc 1 3177 5 is_stmt 1 discriminator 2 view .LVU2282 +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6794 .loc 1 3177 23 is_stmt 0 discriminator 2 view .LVU2283 + 6795 0032 6262 str r2, [r4, #36] +3178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6796 .loc 1 3178 5 is_stmt 1 discriminator 2 view .LVU2284 +3178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6797 .loc 1 3178 23 is_stmt 0 discriminator 2 view .LVU2285 + 6798 0034 6385 strh r3, [r4, #42] @ movhi +3179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6799 .loc 1 3179 5 is_stmt 1 discriminator 2 view .LVU2286 +3179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6800 .loc 1 3179 23 is_stmt 0 discriminator 2 view .LVU2287 + 6801 0036 E162 str r1, [r4, #44] +3180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6802 .loc 1 3180 5 is_stmt 1 discriminator 2 view .LVU2288 +3180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6803 .loc 1 3180 23 is_stmt 0 discriminator 2 view .LVU2289 + 6804 0038 1C4B ldr r3, .L446 + 6805 .LVL424: +3180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6806 .loc 1 3180 23 discriminator 2 view .LVU2290 + 6807 003a 6363 str r3, [r4, #52] + ARM GAS /tmp/ccEimIdZ.s page 274 + + +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6808 .loc 1 3183 5 is_stmt 1 discriminator 2 view .LVU2291 +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6809 .loc 1 3183 13 is_stmt 0 discriminator 2 view .LVU2292 + 6810 003c 638D ldrh r3, [r4, #42] + 6811 003e 9BB2 uxth r3, r3 +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6812 .loc 1 3183 8 discriminator 2 view .LVU2293 + 6813 0040 FF2B cmp r3, #255 + 6814 0042 26D9 bls .L437 +3185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6815 .loc 1 3185 7 is_stmt 1 view .LVU2294 +3185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6816 .loc 1 3185 22 is_stmt 0 view .LVU2295 + 6817 0044 FF23 movs r3, #255 + 6818 0046 2385 strh r3, [r4, #40] @ movhi +3186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6819 .loc 1 3186 7 is_stmt 1 view .LVU2296 + 6820 .LVL425: +3186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6821 .loc 1 3186 16 is_stmt 0 view .LVU2297 + 6822 0048 4FF08076 mov r6, #16777216 + 6823 .LVL426: + 6824 .L438: +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6825 .loc 1 3196 5 is_stmt 1 view .LVU2298 +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6826 .loc 1 3196 14 is_stmt 0 view .LVU2299 + 6827 004c 236B ldr r3, [r4, #48] +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6828 .loc 1 3196 8 view .LVU2300 + 6829 004e 112B cmp r3, #17 + 6830 0050 04D1 bne .L439 +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6831 .loc 1 3196 59 discriminator 1 view .LVU2301 + 6832 0052 B1F52A4F cmp r1, #43520 + 6833 0056 18BF it ne + 6834 0058 AA29 cmpne r1, #170 + 6835 005a 1ED1 bne .L443 + 6836 .L439: +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6837 .loc 1 3203 7 is_stmt 1 view .LVU2302 + 6838 005c 2046 mov r0, r4 + 6839 005e FFF7FEFF bl I2C_ConvertOtherXferOptions + 6840 .LVL427: +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6841 .loc 1 3206 7 view .LVU2303 +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6842 .loc 1 3206 15 is_stmt 0 view .LVU2304 + 6843 0062 638D ldrh r3, [r4, #42] + 6844 0064 9BB2 uxth r3, r3 +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6845 .loc 1 3206 10 view .LVU2305 + 6846 0066 FF2B cmp r3, #255 + 6847 0068 19D8 bhi .L444 +3208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6848 .loc 1 3208 9 is_stmt 1 view .LVU2306 + ARM GAS /tmp/ccEimIdZ.s page 275 + + +3208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6849 .loc 1 3208 18 is_stmt 0 view .LVU2307 + 6850 006a E66A ldr r6, [r4, #44] + 6851 .LVL428: +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6852 .loc 1 3162 12 view .LVU2308 + 6853 006c 104B ldr r3, .L446+4 + 6854 .L440: + 6855 .LVL429: +3213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6856 .loc 1 3213 5 is_stmt 1 view .LVU2309 + 6857 006e 0093 str r3, [sp] + 6858 0070 3346 mov r3, r6 + 6859 .LVL430: +3213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6860 .loc 1 3213 5 is_stmt 0 view .LVU2310 + 6861 0072 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 6862 0076 2946 mov r1, r5 + 6863 0078 2046 mov r0, r4 + 6864 007a FFF7FEFF bl I2C_TransferConfig + 6865 .LVL431: +3216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6866 .loc 1 3216 5 is_stmt 1 view .LVU2311 +3216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6867 .loc 1 3216 5 view .LVU2312 + 6868 007e 0025 movs r5, #0 + 6869 0080 84F84050 strb r5, [r4, #64] +3216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6870 .loc 1 3216 5 view .LVU2313 +3221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6871 .loc 1 3221 5 view .LVU2314 + 6872 0084 0121 movs r1, #1 + 6873 0086 2046 mov r0, r4 + 6874 0088 FFF7FEFF bl I2C_Enable_IRQ + 6875 .LVL432: +3223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6876 .loc 1 3223 5 view .LVU2315 +3223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6877 .loc 1 3223 12 is_stmt 0 view .LVU2316 + 6878 008c 2846 mov r0, r5 + 6879 .LVL433: + 6880 .L436: +3229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6881 .loc 1 3229 1 view .LVU2317 + 6882 008e 02B0 add sp, sp, #8 + 6883 .LCFI85: + 6884 .cfi_remember_state + 6885 .cfi_def_cfa_offset 16 + 6886 @ sp needed + 6887 0090 70BD pop {r4, r5, r6, pc} + 6888 .LVL434: + 6889 .L437: + 6890 .LCFI86: + 6891 .cfi_restore_state +3190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6892 .loc 1 3190 7 is_stmt 1 view .LVU2318 +3190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + ARM GAS /tmp/ccEimIdZ.s page 276 + + + 6893 .loc 1 3190 28 is_stmt 0 view .LVU2319 + 6894 0092 638D ldrh r3, [r4, #42] +3190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6895 .loc 1 3190 22 view .LVU2320 + 6896 0094 2385 strh r3, [r4, #40] @ movhi +3191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6897 .loc 1 3191 7 is_stmt 1 view .LVU2321 +3191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6898 .loc 1 3191 16 is_stmt 0 view .LVU2322 + 6899 0096 E66A ldr r6, [r4, #44] + 6900 .LVL435: +3191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6901 .loc 1 3191 16 view .LVU2323 + 6902 0098 D8E7 b .L438 + 6903 .L443: +3198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6904 .loc 1 3198 19 view .LVU2324 + 6905 009a 0023 movs r3, #0 + 6906 009c E7E7 b .L440 + 6907 .LVL436: + 6908 .L444: +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6909 .loc 1 3162 12 view .LVU2325 + 6910 009e 044B ldr r3, .L446+4 + 6911 00a0 E5E7 b .L440 + 6912 .LVL437: + 6913 .L441: +3227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 6914 .loc 1 3227 12 view .LVU2326 + 6915 00a2 0220 movs r0, #2 + 6916 00a4 F3E7 b .L436 + 6917 .L442: +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6918 .loc 1 3170 5 view .LVU2327 + 6919 00a6 0220 movs r0, #2 + 6920 00a8 F1E7 b .L436 + 6921 .L447: + 6922 00aa 00BF .align 2 + 6923 .L446: + 6924 00ac 00000000 .word I2C_Master_ISR_IT + 6925 00b0 00200080 .word -2147475456 + 6926 .cfi_endproc + 6927 .LFE164: + 6929 .section .text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits + 6930 .align 1 + 6931 .global HAL_I2C_Master_Seq_Transmit_DMA + 6932 .syntax unified + 6933 .thumb + 6934 .thumb_func + 6935 .fpu fpv5-d16 + 6937 HAL_I2C_Master_Seq_Transmit_DMA: + 6938 .LVL438: + 6939 .LFB165: +3244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 6940 .loc 1 3244 1 is_stmt 1 view -0 + 6941 .cfi_startproc + 6942 @ args = 4, pretend = 0, frame = 0 + ARM GAS /tmp/ccEimIdZ.s page 277 + + + 6943 @ frame_needed = 0, uses_anonymous_args = 0 +3244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 6944 .loc 1 3244 1 is_stmt 0 view .LVU2329 + 6945 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 6946 .LCFI87: + 6947 .cfi_def_cfa_offset 24 + 6948 .cfi_offset 4, -24 + 6949 .cfi_offset 5, -20 + 6950 .cfi_offset 6, -16 + 6951 .cfi_offset 7, -12 + 6952 .cfi_offset 8, -8 + 6953 .cfi_offset 14, -4 + 6954 0004 82B0 sub sp, sp, #8 + 6955 .LCFI88: + 6956 .cfi_def_cfa_offset 32 + 6957 0006 0446 mov r4, r0 + 6958 0008 1546 mov r5, r2 + 6959 000a 089A ldr r2, [sp, #32] + 6960 .LVL439: +3245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 6961 .loc 1 3245 3 is_stmt 1 view .LVU2330 +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6962 .loc 1 3246 3 view .LVU2331 +3247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6963 .loc 1 3247 3 view .LVU2332 +3250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6964 .loc 1 3250 3 view .LVU2333 +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6965 .loc 1 3252 3 view .LVU2334 +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6966 .loc 1 3252 11 is_stmt 0 view .LVU2335 + 6967 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6968 .LVL440: +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6969 .loc 1 3252 11 view .LVU2336 + 6970 0010 C0B2 uxtb r0, r0 +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 6971 .loc 1 3252 6 view .LVU2337 + 6972 0012 2028 cmp r0, #32 + 6973 0014 40F09D80 bne .L459 + 6974 0018 0E46 mov r6, r1 +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6975 .loc 1 3255 5 is_stmt 1 view .LVU2338 +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6976 .loc 1 3255 5 view .LVU2339 + 6977 001a 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 6978 .LVL441: +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6979 .loc 1 3255 5 is_stmt 0 view .LVU2340 + 6980 001e 0129 cmp r1, #1 + 6981 0020 00F09B80 beq .L460 +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6982 .loc 1 3255 5 is_stmt 1 discriminator 2 view .LVU2341 + 6983 0024 0121 movs r1, #1 + 6984 0026 84F84010 strb r1, [r4, #64] +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6985 .loc 1 3255 5 discriminator 2 view .LVU2342 + ARM GAS /tmp/ccEimIdZ.s page 278 + + +3257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6986 .loc 1 3257 5 discriminator 2 view .LVU2343 +3257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6987 .loc 1 3257 21 is_stmt 0 discriminator 2 view .LVU2344 + 6988 002a 2121 movs r1, #33 + 6989 002c 84F84110 strb r1, [r4, #65] +3258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6990 .loc 1 3258 5 is_stmt 1 discriminator 2 view .LVU2345 +3258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6991 .loc 1 3258 21 is_stmt 0 discriminator 2 view .LVU2346 + 6992 0030 1021 movs r1, #16 + 6993 0032 84F84210 strb r1, [r4, #66] +3259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6994 .loc 1 3259 5 is_stmt 1 discriminator 2 view .LVU2347 +3259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 6995 .loc 1 3259 21 is_stmt 0 discriminator 2 view .LVU2348 + 6996 0036 0021 movs r1, #0 + 6997 0038 6164 str r1, [r4, #68] +3262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6998 .loc 1 3262 5 is_stmt 1 discriminator 2 view .LVU2349 +3262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6999 .loc 1 3262 23 is_stmt 0 discriminator 2 view .LVU2350 + 7000 003a 6562 str r5, [r4, #36] +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7001 .loc 1 3263 5 is_stmt 1 discriminator 2 view .LVU2351 +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7002 .loc 1 3263 23 is_stmt 0 discriminator 2 view .LVU2352 + 7003 003c 6385 strh r3, [r4, #42] @ movhi +3264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7004 .loc 1 3264 5 is_stmt 1 discriminator 2 view .LVU2353 +3264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7005 .loc 1 3264 23 is_stmt 0 discriminator 2 view .LVU2354 + 7006 003e E262 str r2, [r4, #44] +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7007 .loc 1 3265 5 is_stmt 1 discriminator 2 view .LVU2355 +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7008 .loc 1 3265 23 is_stmt 0 discriminator 2 view .LVU2356 + 7009 0040 474B ldr r3, .L466 + 7010 .LVL442: +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7011 .loc 1 3265 23 discriminator 2 view .LVU2357 + 7012 0042 6363 str r3, [r4, #52] +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7013 .loc 1 3268 5 is_stmt 1 discriminator 2 view .LVU2358 +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7014 .loc 1 3268 13 is_stmt 0 discriminator 2 view .LVU2359 + 7015 0044 638D ldrh r3, [r4, #42] + 7016 0046 9BB2 uxth r3, r3 +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7017 .loc 1 3268 8 discriminator 2 view .LVU2360 + 7018 0048 FF2B cmp r3, #255 + 7019 004a 3AD9 bls .L450 +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7020 .loc 1 3270 7 is_stmt 1 view .LVU2361 +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7021 .loc 1 3270 22 is_stmt 0 view .LVU2362 + 7022 004c FF23 movs r3, #255 + ARM GAS /tmp/ccEimIdZ.s page 279 + + + 7023 004e 2385 strh r3, [r4, #40] @ movhi +3271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7024 .loc 1 3271 7 is_stmt 1 view .LVU2363 + 7025 .LVL443: +3271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7026 .loc 1 3271 16 is_stmt 0 view .LVU2364 + 7027 0050 4FF08077 mov r7, #16777216 + 7028 .LVL444: + 7029 .L451: +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7030 .loc 1 3281 5 is_stmt 1 view .LVU2365 +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7031 .loc 1 3281 14 is_stmt 0 view .LVU2366 + 7032 0054 236B ldr r3, [r4, #48] +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7033 .loc 1 3281 8 view .LVU2367 + 7034 0056 112B cmp r3, #17 + 7035 0058 04D1 bne .L452 +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7036 .loc 1 3281 59 discriminator 1 view .LVU2368 + 7037 005a B2F52A4F cmp r2, #43520 + 7038 005e 18BF it ne + 7039 0060 AA2A cmpne r2, #170 + 7040 0062 32D1 bne .L461 + 7041 .L452: +3288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7042 .loc 1 3288 7 is_stmt 1 view .LVU2369 + 7043 0064 2046 mov r0, r4 + 7044 0066 FFF7FEFF bl I2C_ConvertOtherXferOptions + 7045 .LVL445: +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7046 .loc 1 3291 7 view .LVU2370 +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7047 .loc 1 3291 15 is_stmt 0 view .LVU2371 + 7048 006a 638D ldrh r3, [r4, #42] + 7049 006c 9BB2 uxth r3, r3 +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7050 .loc 1 3291 10 view .LVU2372 + 7051 006e FF2B cmp r3, #255 + 7052 0070 2ED8 bhi .L462 +3293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7053 .loc 1 3293 9 is_stmt 1 view .LVU2373 +3293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7054 .loc 1 3293 18 is_stmt 0 view .LVU2374 + 7055 0072 E76A ldr r7, [r4, #44] + 7056 .LVL446: +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7057 .loc 1 3246 12 view .LVU2375 + 7058 0074 DFF8F880 ldr r8, .L466+16 + 7059 .L453: + 7060 .LVL447: +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7061 .loc 1 3297 5 is_stmt 1 view .LVU2376 +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7062 .loc 1 3297 13 is_stmt 0 view .LVU2377 + 7063 0078 228D ldrh r2, [r4, #40] +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 280 + + + 7064 .loc 1 3297 8 view .LVU2378 + 7065 007a 002A cmp r2, #0 + 7066 007c 55D0 beq .L454 +3299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7067 .loc 1 3299 7 is_stmt 1 view .LVU2379 +3299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7068 .loc 1 3299 15 is_stmt 0 view .LVU2380 + 7069 007e A36B ldr r3, [r4, #56] +3299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7070 .loc 1 3299 10 view .LVU2381 + 7071 0080 4BB3 cbz r3, .L455 +3302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7072 .loc 1 3302 9 is_stmt 1 view .LVU2382 +3302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7073 .loc 1 3302 40 is_stmt 0 view .LVU2383 + 7074 0082 384A ldr r2, .L466+4 + 7075 0084 DA63 str r2, [r3, #60] +3305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7076 .loc 1 3305 9 is_stmt 1 view .LVU2384 +3305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7077 .loc 1 3305 13 is_stmt 0 view .LVU2385 + 7078 0086 A36B ldr r3, [r4, #56] +3305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7079 .loc 1 3305 41 view .LVU2386 + 7080 0088 374A ldr r2, .L466+8 + 7081 008a DA64 str r2, [r3, #76] +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7082 .loc 1 3308 9 is_stmt 1 view .LVU2387 +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7083 .loc 1 3308 13 is_stmt 0 view .LVU2388 + 7084 008c A26B ldr r2, [r4, #56] +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7085 .loc 1 3308 44 view .LVU2389 + 7086 008e 0023 movs r3, #0 + 7087 0090 1364 str r3, [r2, #64] +3309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7088 .loc 1 3309 9 is_stmt 1 view .LVU2390 +3309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7089 .loc 1 3309 13 is_stmt 0 view .LVU2391 + 7090 0092 A26B ldr r2, [r4, #56] +3309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7091 .loc 1 3309 41 view .LVU2392 + 7092 0094 1365 str r3, [r2, #80] +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7093 .loc 1 3312 9 is_stmt 1 view .LVU2393 +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7094 .loc 1 3312 88 is_stmt 0 view .LVU2394 + 7095 0096 2268 ldr r2, [r4] +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7096 .loc 1 3312 25 view .LVU2395 + 7097 0098 238D ldrh r3, [r4, #40] + 7098 009a 2832 adds r2, r2, #40 + 7099 009c 2946 mov r1, r5 + 7100 009e A06B ldr r0, [r4, #56] + 7101 00a0 FFF7FEFF bl HAL_DMA_Start_IT + 7102 .LVL448: +3329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 281 + + + 7103 .loc 1 3329 7 is_stmt 1 view .LVU2396 +3329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7104 .loc 1 3329 10 is_stmt 0 view .LVU2397 + 7105 00a4 28B3 cbz r0, .L465 +3352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7106 .loc 1 3352 9 is_stmt 1 view .LVU2398 +3352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7107 .loc 1 3352 25 is_stmt 0 view .LVU2399 + 7108 00a6 2023 movs r3, #32 + 7109 00a8 84F84130 strb r3, [r4, #65] +3353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7110 .loc 1 3353 9 is_stmt 1 view .LVU2400 +3353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7111 .loc 1 3353 25 is_stmt 0 view .LVU2401 + 7112 00ac 0022 movs r2, #0 + 7113 00ae 84F84220 strb r2, [r4, #66] +3356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7114 .loc 1 3356 9 is_stmt 1 view .LVU2402 +3356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7115 .loc 1 3356 25 is_stmt 0 view .LVU2403 + 7116 00b2 636C ldr r3, [r4, #68] + 7117 00b4 43F01003 orr r3, r3, #16 + 7118 00b8 6364 str r3, [r4, #68] +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7119 .loc 1 3359 9 is_stmt 1 view .LVU2404 +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7120 .loc 1 3359 9 view .LVU2405 + 7121 00ba 84F84020 strb r2, [r4, #64] +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7122 .loc 1 3359 9 view .LVU2406 +3361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7123 .loc 1 3361 9 view .LVU2407 +3361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7124 .loc 1 3361 16 is_stmt 0 view .LVU2408 + 7125 00be 0120 movs r0, #1 + 7126 .LVL449: +3361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7127 .loc 1 3361 16 view .LVU2409 + 7128 00c0 48E0 b .L449 + 7129 .LVL450: + 7130 .L450: +3275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7131 .loc 1 3275 7 is_stmt 1 view .LVU2410 +3275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7132 .loc 1 3275 28 is_stmt 0 view .LVU2411 + 7133 00c2 638D ldrh r3, [r4, #42] +3275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7134 .loc 1 3275 22 view .LVU2412 + 7135 00c4 2385 strh r3, [r4, #40] @ movhi +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7136 .loc 1 3276 7 is_stmt 1 view .LVU2413 +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7137 .loc 1 3276 16 is_stmt 0 view .LVU2414 + 7138 00c6 E76A ldr r7, [r4, #44] + 7139 .LVL451: +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7140 .loc 1 3276 16 view .LVU2415 + ARM GAS /tmp/ccEimIdZ.s page 282 + + + 7141 00c8 C4E7 b .L451 + 7142 .L461: +3283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7143 .loc 1 3283 19 view .LVU2416 + 7144 00ca 4FF00008 mov r8, #0 + 7145 00ce D3E7 b .L453 + 7146 .L462: +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7147 .loc 1 3246 12 view .LVU2417 + 7148 00d0 DFF89C80 ldr r8, .L466+16 + 7149 00d4 D0E7 b .L453 + 7150 .LVL452: + 7151 .L455: +3317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7152 .loc 1 3317 9 is_stmt 1 view .LVU2418 +3317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7153 .loc 1 3317 25 is_stmt 0 view .LVU2419 + 7154 00d6 2023 movs r3, #32 + 7155 00d8 84F84130 strb r3, [r4, #65] +3318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7156 .loc 1 3318 9 is_stmt 1 view .LVU2420 +3318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7157 .loc 1 3318 25 is_stmt 0 view .LVU2421 + 7158 00dc 0022 movs r2, #0 + 7159 00de 84F84220 strb r2, [r4, #66] +3321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7160 .loc 1 3321 9 is_stmt 1 view .LVU2422 +3321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7161 .loc 1 3321 25 is_stmt 0 view .LVU2423 + 7162 00e2 636C ldr r3, [r4, #68] + 7163 00e4 43F08003 orr r3, r3, #128 + 7164 00e8 6364 str r3, [r4, #68] +3324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7165 .loc 1 3324 9 is_stmt 1 view .LVU2424 +3324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7166 .loc 1 3324 9 view .LVU2425 + 7167 00ea 84F84020 strb r2, [r4, #64] +3324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7168 .loc 1 3324 9 view .LVU2426 +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7169 .loc 1 3326 9 view .LVU2427 +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7170 .loc 1 3326 16 is_stmt 0 view .LVU2428 + 7171 00ee 0120 movs r0, #1 + 7172 00f0 30E0 b .L449 + 7173 .LVL453: + 7174 .L465: +3332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7175 .loc 1 3332 9 is_stmt 1 view .LVU2429 + 7176 00f2 CDF80080 str r8, [sp] + 7177 00f6 3B46 mov r3, r7 + 7178 00f8 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7179 00fc 3146 mov r1, r6 + 7180 00fe 2046 mov r0, r4 + 7181 .LVL454: +3332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7182 .loc 1 3332 9 is_stmt 0 view .LVU2430 + ARM GAS /tmp/ccEimIdZ.s page 283 + + + 7183 0100 FFF7FEFF bl I2C_TransferConfig + 7184 .LVL455: +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7185 .loc 1 3335 9 is_stmt 1 view .LVU2431 +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7186 .loc 1 3335 25 is_stmt 0 view .LVU2432 + 7187 0104 638D ldrh r3, [r4, #42] + 7188 0106 9BB2 uxth r3, r3 +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7189 .loc 1 3335 32 view .LVU2433 + 7190 0108 228D ldrh r2, [r4, #40] +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7191 .loc 1 3335 25 view .LVU2434 + 7192 010a 9B1A subs r3, r3, r2 + 7193 010c 9BB2 uxth r3, r3 + 7194 010e 6385 strh r3, [r4, #42] @ movhi +3338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7195 .loc 1 3338 9 is_stmt 1 view .LVU2435 +3338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7196 .loc 1 3338 9 view .LVU2436 + 7197 0110 0023 movs r3, #0 + 7198 0112 84F84030 strb r3, [r4, #64] +3338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7199 .loc 1 3338 9 view .LVU2437 +3344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7200 .loc 1 3344 9 view .LVU2438 + 7201 0116 1021 movs r1, #16 + 7202 0118 2046 mov r0, r4 + 7203 011a FFF7FEFF bl I2C_Enable_IRQ + 7204 .LVL456: +3347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7205 .loc 1 3347 9 view .LVU2439 +3347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7206 .loc 1 3347 13 is_stmt 0 view .LVU2440 + 7207 011e 2268 ldr r2, [r4] +3347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7208 .loc 1 3347 29 view .LVU2441 + 7209 0120 1368 ldr r3, [r2] + 7210 0122 43F48043 orr r3, r3, #16384 + 7211 0126 1360 str r3, [r2] + 7212 0128 11E0 b .L458 + 7213 .L454: +3367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7214 .loc 1 3367 7 is_stmt 1 view .LVU2442 +3367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7215 .loc 1 3367 21 is_stmt 0 view .LVU2443 + 7216 012a 104B ldr r3, .L466+12 + 7217 012c 6363 str r3, [r4, #52] +3371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7218 .loc 1 3371 7 is_stmt 1 view .LVU2444 + 7219 012e 104B ldr r3, .L466+16 + 7220 0130 0093 str r3, [sp] + 7221 0132 4FF00073 mov r3, #33554432 + 7222 0136 D2B2 uxtb r2, r2 + 7223 0138 3146 mov r1, r6 + 7224 013a 2046 mov r0, r4 + 7225 013c FFF7FEFF bl I2C_TransferConfig + ARM GAS /tmp/ccEimIdZ.s page 284 + + + 7226 .LVL457: +3374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7227 .loc 1 3374 7 view .LVU2445 +3374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7228 .loc 1 3374 7 view .LVU2446 + 7229 0140 0023 movs r3, #0 + 7230 0142 84F84030 strb r3, [r4, #64] +3374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7231 .loc 1 3374 7 view .LVU2447 +3382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7232 .loc 1 3382 7 view .LVU2448 + 7233 0146 0121 movs r1, #1 + 7234 0148 2046 mov r0, r4 + 7235 014a FFF7FEFF bl I2C_Enable_IRQ + 7236 .LVL458: + 7237 .L458: +3385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7238 .loc 1 3385 5 view .LVU2449 +3385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7239 .loc 1 3385 12 is_stmt 0 view .LVU2450 + 7240 014e 0020 movs r0, #0 + 7241 0150 00E0 b .L449 + 7242 .LVL459: + 7243 .L459: +3389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7244 .loc 1 3389 12 view .LVU2451 + 7245 0152 0220 movs r0, #2 + 7246 .LVL460: + 7247 .L449: +3391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7248 .loc 1 3391 1 view .LVU2452 + 7249 0154 02B0 add sp, sp, #8 + 7250 .LCFI89: + 7251 .cfi_remember_state + 7252 .cfi_def_cfa_offset 24 + 7253 @ sp needed + 7254 0156 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 7255 .LVL461: + 7256 .L460: + 7257 .LCFI90: + 7258 .cfi_restore_state +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7259 .loc 1 3255 5 view .LVU2453 + 7260 015a 0220 movs r0, #2 + 7261 015c FAE7 b .L449 + 7262 .L467: + 7263 015e 00BF .align 2 + 7264 .L466: + 7265 0160 00000000 .word I2C_Master_ISR_DMA + 7266 0164 00000000 .word I2C_DMAMasterTransmitCplt + 7267 0168 00000000 .word I2C_DMAError + 7268 016c 00000000 .word I2C_Master_ISR_IT + 7269 0170 00200080 .word -2147475456 + 7270 .cfi_endproc + 7271 .LFE165: + 7273 .section .text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits + 7274 .align 1 + ARM GAS /tmp/ccEimIdZ.s page 285 + + + 7275 .global HAL_I2C_Master_Seq_Receive_IT + 7276 .syntax unified + 7277 .thumb + 7278 .thumb_func + 7279 .fpu fpv5-d16 + 7281 HAL_I2C_Master_Seq_Receive_IT: + 7282 .LVL462: + 7283 .LFB166: +3406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 7284 .loc 1 3406 1 is_stmt 1 view -0 + 7285 .cfi_startproc + 7286 @ args = 4, pretend = 0, frame = 0 + 7287 @ frame_needed = 0, uses_anonymous_args = 0 +3406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 7288 .loc 1 3406 1 is_stmt 0 view .LVU2455 + 7289 0000 70B5 push {r4, r5, r6, lr} + 7290 .LCFI91: + 7291 .cfi_def_cfa_offset 16 + 7292 .cfi_offset 4, -16 + 7293 .cfi_offset 5, -12 + 7294 .cfi_offset 6, -8 + 7295 .cfi_offset 14, -4 + 7296 0002 82B0 sub sp, sp, #8 + 7297 .LCFI92: + 7298 .cfi_def_cfa_offset 24 + 7299 0004 0446 mov r4, r0 + 7300 0006 0D46 mov r5, r1 + 7301 0008 0699 ldr r1, [sp, #24] + 7302 .LVL463: +3407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 7303 .loc 1 3407 3 is_stmt 1 view .LVU2456 +3408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7304 .loc 1 3408 3 view .LVU2457 +3411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7305 .loc 1 3411 3 view .LVU2458 +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7306 .loc 1 3413 3 view .LVU2459 +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7307 .loc 1 3413 11 is_stmt 0 view .LVU2460 + 7308 000a 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7309 .LVL464: +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7310 .loc 1 3413 11 view .LVU2461 + 7311 000e C0B2 uxtb r0, r0 +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7312 .loc 1 3413 6 view .LVU2462 + 7313 0010 2028 cmp r0, #32 + 7314 0012 46D1 bne .L474 +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7315 .loc 1 3416 5 is_stmt 1 view .LVU2463 +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7316 .loc 1 3416 5 view .LVU2464 + 7317 0014 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 7318 0018 0128 cmp r0, #1 + 7319 001a 44D0 beq .L475 +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7320 .loc 1 3416 5 discriminator 2 view .LVU2465 + ARM GAS /tmp/ccEimIdZ.s page 286 + + + 7321 001c 0120 movs r0, #1 + 7322 001e 84F84000 strb r0, [r4, #64] +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7323 .loc 1 3416 5 discriminator 2 view .LVU2466 +3418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7324 .loc 1 3418 5 discriminator 2 view .LVU2467 +3418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7325 .loc 1 3418 21 is_stmt 0 discriminator 2 view .LVU2468 + 7326 0022 2220 movs r0, #34 + 7327 0024 84F84100 strb r0, [r4, #65] +3419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7328 .loc 1 3419 5 is_stmt 1 discriminator 2 view .LVU2469 +3419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7329 .loc 1 3419 21 is_stmt 0 discriminator 2 view .LVU2470 + 7330 0028 1020 movs r0, #16 + 7331 002a 84F84200 strb r0, [r4, #66] +3420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7332 .loc 1 3420 5 is_stmt 1 discriminator 2 view .LVU2471 +3420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7333 .loc 1 3420 21 is_stmt 0 discriminator 2 view .LVU2472 + 7334 002e 0020 movs r0, #0 + 7335 0030 6064 str r0, [r4, #68] +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7336 .loc 1 3423 5 is_stmt 1 discriminator 2 view .LVU2473 +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7337 .loc 1 3423 23 is_stmt 0 discriminator 2 view .LVU2474 + 7338 0032 6262 str r2, [r4, #36] +3424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7339 .loc 1 3424 5 is_stmt 1 discriminator 2 view .LVU2475 +3424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7340 .loc 1 3424 23 is_stmt 0 discriminator 2 view .LVU2476 + 7341 0034 6385 strh r3, [r4, #42] @ movhi +3425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7342 .loc 1 3425 5 is_stmt 1 discriminator 2 view .LVU2477 +3425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7343 .loc 1 3425 23 is_stmt 0 discriminator 2 view .LVU2478 + 7344 0036 E162 str r1, [r4, #44] +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7345 .loc 1 3426 5 is_stmt 1 discriminator 2 view .LVU2479 +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7346 .loc 1 3426 23 is_stmt 0 discriminator 2 view .LVU2480 + 7347 0038 1C4B ldr r3, .L479 + 7348 .LVL465: +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7349 .loc 1 3426 23 discriminator 2 view .LVU2481 + 7350 003a 6363 str r3, [r4, #52] +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7351 .loc 1 3429 5 is_stmt 1 discriminator 2 view .LVU2482 +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7352 .loc 1 3429 13 is_stmt 0 discriminator 2 view .LVU2483 + 7353 003c 638D ldrh r3, [r4, #42] + 7354 003e 9BB2 uxth r3, r3 +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7355 .loc 1 3429 8 discriminator 2 view .LVU2484 + 7356 0040 FF2B cmp r3, #255 + 7357 0042 26D9 bls .L470 +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + ARM GAS /tmp/ccEimIdZ.s page 287 + + + 7358 .loc 1 3431 7 is_stmt 1 view .LVU2485 +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7359 .loc 1 3431 22 is_stmt 0 view .LVU2486 + 7360 0044 FF23 movs r3, #255 + 7361 0046 2385 strh r3, [r4, #40] @ movhi +3432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7362 .loc 1 3432 7 is_stmt 1 view .LVU2487 + 7363 .LVL466: +3432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7364 .loc 1 3432 16 is_stmt 0 view .LVU2488 + 7365 0048 4FF08076 mov r6, #16777216 + 7366 .LVL467: + 7367 .L471: +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7368 .loc 1 3442 5 is_stmt 1 view .LVU2489 +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7369 .loc 1 3442 14 is_stmt 0 view .LVU2490 + 7370 004c 236B ldr r3, [r4, #48] +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7371 .loc 1 3442 8 view .LVU2491 + 7372 004e 122B cmp r3, #18 + 7373 0050 04D1 bne .L472 +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7374 .loc 1 3442 59 discriminator 1 view .LVU2492 + 7375 0052 B1F52A4F cmp r1, #43520 + 7376 0056 18BF it ne + 7377 0058 AA29 cmpne r1, #170 + 7378 005a 1ED1 bne .L476 + 7379 .L472: +3449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7380 .loc 1 3449 7 is_stmt 1 view .LVU2493 + 7381 005c 2046 mov r0, r4 + 7382 005e FFF7FEFF bl I2C_ConvertOtherXferOptions + 7383 .LVL468: +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7384 .loc 1 3452 7 view .LVU2494 +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7385 .loc 1 3452 15 is_stmt 0 view .LVU2495 + 7386 0062 638D ldrh r3, [r4, #42] + 7387 0064 9BB2 uxth r3, r3 +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7388 .loc 1 3452 10 view .LVU2496 + 7389 0066 FF2B cmp r3, #255 + 7390 0068 19D8 bhi .L477 +3454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7391 .loc 1 3454 9 is_stmt 1 view .LVU2497 +3454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7392 .loc 1 3454 18 is_stmt 0 view .LVU2498 + 7393 006a E66A ldr r6, [r4, #44] + 7394 .LVL469: +3408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7395 .loc 1 3408 12 view .LVU2499 + 7396 006c 104B ldr r3, .L479+4 + 7397 .L473: + 7398 .LVL470: +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7399 .loc 1 3459 5 is_stmt 1 view .LVU2500 + ARM GAS /tmp/ccEimIdZ.s page 288 + + + 7400 006e 0093 str r3, [sp] + 7401 0070 3346 mov r3, r6 + 7402 .LVL471: +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7403 .loc 1 3459 5 is_stmt 0 view .LVU2501 + 7404 0072 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7405 0076 2946 mov r1, r5 + 7406 0078 2046 mov r0, r4 + 7407 007a FFF7FEFF bl I2C_TransferConfig + 7408 .LVL472: +3462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7409 .loc 1 3462 5 is_stmt 1 view .LVU2502 +3462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7410 .loc 1 3462 5 view .LVU2503 + 7411 007e 0025 movs r5, #0 + 7412 0080 84F84050 strb r5, [r4, #64] +3462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7413 .loc 1 3462 5 view .LVU2504 +3467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7414 .loc 1 3467 5 view .LVU2505 + 7415 0084 0221 movs r1, #2 + 7416 0086 2046 mov r0, r4 + 7417 0088 FFF7FEFF bl I2C_Enable_IRQ + 7418 .LVL473: +3469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7419 .loc 1 3469 5 view .LVU2506 +3469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7420 .loc 1 3469 12 is_stmt 0 view .LVU2507 + 7421 008c 2846 mov r0, r5 + 7422 .LVL474: + 7423 .L469: +3475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7424 .loc 1 3475 1 view .LVU2508 + 7425 008e 02B0 add sp, sp, #8 + 7426 .LCFI93: + 7427 .cfi_remember_state + 7428 .cfi_def_cfa_offset 16 + 7429 @ sp needed + 7430 0090 70BD pop {r4, r5, r6, pc} + 7431 .LVL475: + 7432 .L470: + 7433 .LCFI94: + 7434 .cfi_restore_state +3436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7435 .loc 1 3436 7 is_stmt 1 view .LVU2509 +3436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7436 .loc 1 3436 28 is_stmt 0 view .LVU2510 + 7437 0092 638D ldrh r3, [r4, #42] +3436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7438 .loc 1 3436 22 view .LVU2511 + 7439 0094 2385 strh r3, [r4, #40] @ movhi +3437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7440 .loc 1 3437 7 is_stmt 1 view .LVU2512 +3437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7441 .loc 1 3437 16 is_stmt 0 view .LVU2513 + 7442 0096 E66A ldr r6, [r4, #44] + 7443 .LVL476: + ARM GAS /tmp/ccEimIdZ.s page 289 + + +3437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7444 .loc 1 3437 16 view .LVU2514 + 7445 0098 D8E7 b .L471 + 7446 .L476: +3444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7447 .loc 1 3444 19 view .LVU2515 + 7448 009a 0023 movs r3, #0 + 7449 009c E7E7 b .L473 + 7450 .LVL477: + 7451 .L477: +3408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7452 .loc 1 3408 12 view .LVU2516 + 7453 009e 044B ldr r3, .L479+4 + 7454 00a0 E5E7 b .L473 + 7455 .LVL478: + 7456 .L474: +3473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7457 .loc 1 3473 12 view .LVU2517 + 7458 00a2 0220 movs r0, #2 + 7459 00a4 F3E7 b .L469 + 7460 .L475: +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7461 .loc 1 3416 5 view .LVU2518 + 7462 00a6 0220 movs r0, #2 + 7463 00a8 F1E7 b .L469 + 7464 .L480: + 7465 00aa 00BF .align 2 + 7466 .L479: + 7467 00ac 00000000 .word I2C_Master_ISR_IT + 7468 00b0 00240080 .word -2147474432 + 7469 .cfi_endproc + 7470 .LFE166: + 7472 .section .text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits + 7473 .align 1 + 7474 .global HAL_I2C_Master_Seq_Receive_DMA + 7475 .syntax unified + 7476 .thumb + 7477 .thumb_func + 7478 .fpu fpv5-d16 + 7480 HAL_I2C_Master_Seq_Receive_DMA: + 7481 .LVL479: + 7482 .LFB167: +3490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 7483 .loc 1 3490 1 is_stmt 1 view -0 + 7484 .cfi_startproc + 7485 @ args = 4, pretend = 0, frame = 0 + 7486 @ frame_needed = 0, uses_anonymous_args = 0 +3490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 7487 .loc 1 3490 1 is_stmt 0 view .LVU2520 + 7488 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 7489 .LCFI95: + 7490 .cfi_def_cfa_offset 24 + 7491 .cfi_offset 4, -24 + 7492 .cfi_offset 5, -20 + 7493 .cfi_offset 6, -16 + 7494 .cfi_offset 7, -12 + 7495 .cfi_offset 8, -8 + ARM GAS /tmp/ccEimIdZ.s page 290 + + + 7496 .cfi_offset 14, -4 + 7497 0004 82B0 sub sp, sp, #8 + 7498 .LCFI96: + 7499 .cfi_def_cfa_offset 32 + 7500 0006 0446 mov r4, r0 + 7501 0008 1546 mov r5, r2 + 7502 000a 089A ldr r2, [sp, #32] + 7503 .LVL480: +3491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 7504 .loc 1 3491 3 is_stmt 1 view .LVU2521 +3492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7505 .loc 1 3492 3 view .LVU2522 +3493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7506 .loc 1 3493 3 view .LVU2523 +3496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7507 .loc 1 3496 3 view .LVU2524 +3498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7508 .loc 1 3498 3 view .LVU2525 +3498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7509 .loc 1 3498 11 is_stmt 0 view .LVU2526 + 7510 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7511 .LVL481: +3498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7512 .loc 1 3498 11 view .LVU2527 + 7513 0010 C0B2 uxtb r0, r0 +3498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7514 .loc 1 3498 6 view .LVU2528 + 7515 0012 2028 cmp r0, #32 + 7516 0014 40F09D80 bne .L492 + 7517 0018 0E46 mov r6, r1 +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7518 .loc 1 3501 5 is_stmt 1 view .LVU2529 +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7519 .loc 1 3501 5 view .LVU2530 + 7520 001a 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 7521 .LVL482: +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7522 .loc 1 3501 5 is_stmt 0 view .LVU2531 + 7523 001e 0129 cmp r1, #1 + 7524 0020 00F09B80 beq .L493 +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7525 .loc 1 3501 5 is_stmt 1 discriminator 2 view .LVU2532 + 7526 0024 0121 movs r1, #1 + 7527 0026 84F84010 strb r1, [r4, #64] +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7528 .loc 1 3501 5 discriminator 2 view .LVU2533 +3503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7529 .loc 1 3503 5 discriminator 2 view .LVU2534 +3503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7530 .loc 1 3503 21 is_stmt 0 discriminator 2 view .LVU2535 + 7531 002a 2221 movs r1, #34 + 7532 002c 84F84110 strb r1, [r4, #65] +3504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7533 .loc 1 3504 5 is_stmt 1 discriminator 2 view .LVU2536 +3504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7534 .loc 1 3504 21 is_stmt 0 discriminator 2 view .LVU2537 + 7535 0030 1021 movs r1, #16 + ARM GAS /tmp/ccEimIdZ.s page 291 + + + 7536 0032 84F84210 strb r1, [r4, #66] +3505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7537 .loc 1 3505 5 is_stmt 1 discriminator 2 view .LVU2538 +3505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7538 .loc 1 3505 21 is_stmt 0 discriminator 2 view .LVU2539 + 7539 0036 0021 movs r1, #0 + 7540 0038 6164 str r1, [r4, #68] +3508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7541 .loc 1 3508 5 is_stmt 1 discriminator 2 view .LVU2540 +3508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7542 .loc 1 3508 23 is_stmt 0 discriminator 2 view .LVU2541 + 7543 003a 6562 str r5, [r4, #36] +3509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7544 .loc 1 3509 5 is_stmt 1 discriminator 2 view .LVU2542 +3509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7545 .loc 1 3509 23 is_stmt 0 discriminator 2 view .LVU2543 + 7546 003c 6385 strh r3, [r4, #42] @ movhi +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7547 .loc 1 3510 5 is_stmt 1 discriminator 2 view .LVU2544 +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7548 .loc 1 3510 23 is_stmt 0 discriminator 2 view .LVU2545 + 7549 003e E262 str r2, [r4, #44] +3511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7550 .loc 1 3511 5 is_stmt 1 discriminator 2 view .LVU2546 +3511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7551 .loc 1 3511 23 is_stmt 0 discriminator 2 view .LVU2547 + 7552 0040 474B ldr r3, .L499 + 7553 .LVL483: +3511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7554 .loc 1 3511 23 discriminator 2 view .LVU2548 + 7555 0042 6363 str r3, [r4, #52] +3514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7556 .loc 1 3514 5 is_stmt 1 discriminator 2 view .LVU2549 +3514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7557 .loc 1 3514 13 is_stmt 0 discriminator 2 view .LVU2550 + 7558 0044 638D ldrh r3, [r4, #42] + 7559 0046 9BB2 uxth r3, r3 +3514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7560 .loc 1 3514 8 discriminator 2 view .LVU2551 + 7561 0048 FF2B cmp r3, #255 + 7562 004a 3AD9 bls .L483 +3516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7563 .loc 1 3516 7 is_stmt 1 view .LVU2552 +3516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7564 .loc 1 3516 22 is_stmt 0 view .LVU2553 + 7565 004c FF23 movs r3, #255 + 7566 004e 2385 strh r3, [r4, #40] @ movhi +3517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7567 .loc 1 3517 7 is_stmt 1 view .LVU2554 + 7568 .LVL484: +3517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7569 .loc 1 3517 16 is_stmt 0 view .LVU2555 + 7570 0050 4FF08077 mov r7, #16777216 + 7571 .LVL485: + 7572 .L484: +3527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7573 .loc 1 3527 5 is_stmt 1 view .LVU2556 + ARM GAS /tmp/ccEimIdZ.s page 292 + + +3527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7574 .loc 1 3527 14 is_stmt 0 view .LVU2557 + 7575 0054 236B ldr r3, [r4, #48] +3527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7576 .loc 1 3527 8 view .LVU2558 + 7577 0056 122B cmp r3, #18 + 7578 0058 04D1 bne .L485 +3527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7579 .loc 1 3527 59 discriminator 1 view .LVU2559 + 7580 005a B2F52A4F cmp r2, #43520 + 7581 005e 18BF it ne + 7582 0060 AA2A cmpne r2, #170 + 7583 0062 32D1 bne .L494 + 7584 .L485: +3534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7585 .loc 1 3534 7 is_stmt 1 view .LVU2560 + 7586 0064 2046 mov r0, r4 + 7587 0066 FFF7FEFF bl I2C_ConvertOtherXferOptions + 7588 .LVL486: +3537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7589 .loc 1 3537 7 view .LVU2561 +3537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7590 .loc 1 3537 15 is_stmt 0 view .LVU2562 + 7591 006a 638D ldrh r3, [r4, #42] + 7592 006c 9BB2 uxth r3, r3 +3537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7593 .loc 1 3537 10 view .LVU2563 + 7594 006e FF2B cmp r3, #255 + 7595 0070 2ED8 bhi .L495 +3539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7596 .loc 1 3539 9 is_stmt 1 view .LVU2564 +3539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7597 .loc 1 3539 18 is_stmt 0 view .LVU2565 + 7598 0072 E76A ldr r7, [r4, #44] + 7599 .LVL487: +3492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7600 .loc 1 3492 12 view .LVU2566 + 7601 0074 DFF8F880 ldr r8, .L499+16 + 7602 .L486: + 7603 .LVL488: +3543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7604 .loc 1 3543 5 is_stmt 1 view .LVU2567 +3543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7605 .loc 1 3543 13 is_stmt 0 view .LVU2568 + 7606 0078 228D ldrh r2, [r4, #40] +3543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7607 .loc 1 3543 8 view .LVU2569 + 7608 007a 002A cmp r2, #0 + 7609 007c 55D0 beq .L487 +3545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7610 .loc 1 3545 7 is_stmt 1 view .LVU2570 +3545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7611 .loc 1 3545 15 is_stmt 0 view .LVU2571 + 7612 007e E36B ldr r3, [r4, #60] +3545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7613 .loc 1 3545 10 view .LVU2572 + 7614 0080 4BB3 cbz r3, .L488 + ARM GAS /tmp/ccEimIdZ.s page 293 + + +3548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7615 .loc 1 3548 9 is_stmt 1 view .LVU2573 +3548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7616 .loc 1 3548 40 is_stmt 0 view .LVU2574 + 7617 0082 384A ldr r2, .L499+4 + 7618 0084 DA63 str r2, [r3, #60] +3551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7619 .loc 1 3551 9 is_stmt 1 view .LVU2575 +3551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7620 .loc 1 3551 13 is_stmt 0 view .LVU2576 + 7621 0086 E36B ldr r3, [r4, #60] +3551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7622 .loc 1 3551 41 view .LVU2577 + 7623 0088 374A ldr r2, .L499+8 + 7624 008a DA64 str r2, [r3, #76] +3554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 7625 .loc 1 3554 9 is_stmt 1 view .LVU2578 +3554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 7626 .loc 1 3554 13 is_stmt 0 view .LVU2579 + 7627 008c E26B ldr r2, [r4, #60] +3554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 7628 .loc 1 3554 44 view .LVU2580 + 7629 008e 0023 movs r3, #0 + 7630 0090 1364 str r3, [r2, #64] +3555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7631 .loc 1 3555 9 is_stmt 1 view .LVU2581 +3555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7632 .loc 1 3555 13 is_stmt 0 view .LVU2582 + 7633 0092 E26B ldr r2, [r4, #60] +3555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7634 .loc 1 3555 41 view .LVU2583 + 7635 0094 1365 str r3, [r2, #80] +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7636 .loc 1 3558 9 is_stmt 1 view .LVU2584 +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7637 .loc 1 3558 71 is_stmt 0 view .LVU2585 + 7638 0096 2168 ldr r1, [r4] +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7639 .loc 1 3558 25 view .LVU2586 + 7640 0098 238D ldrh r3, [r4, #40] + 7641 009a 2A46 mov r2, r5 + 7642 009c 2431 adds r1, r1, #36 + 7643 009e E06B ldr r0, [r4, #60] + 7644 00a0 FFF7FEFF bl HAL_DMA_Start_IT + 7645 .LVL489: +3575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7646 .loc 1 3575 7 is_stmt 1 view .LVU2587 +3575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7647 .loc 1 3575 10 is_stmt 0 view .LVU2588 + 7648 00a4 28B3 cbz r0, .L498 +3598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7649 .loc 1 3598 9 is_stmt 1 view .LVU2589 +3598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7650 .loc 1 3598 25 is_stmt 0 view .LVU2590 + 7651 00a6 2023 movs r3, #32 + 7652 00a8 84F84130 strb r3, [r4, #65] +3599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 294 + + + 7653 .loc 1 3599 9 is_stmt 1 view .LVU2591 +3599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7654 .loc 1 3599 25 is_stmt 0 view .LVU2592 + 7655 00ac 0022 movs r2, #0 + 7656 00ae 84F84220 strb r2, [r4, #66] +3602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7657 .loc 1 3602 9 is_stmt 1 view .LVU2593 +3602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7658 .loc 1 3602 25 is_stmt 0 view .LVU2594 + 7659 00b2 636C ldr r3, [r4, #68] + 7660 00b4 43F01003 orr r3, r3, #16 + 7661 00b8 6364 str r3, [r4, #68] +3605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7662 .loc 1 3605 9 is_stmt 1 view .LVU2595 +3605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7663 .loc 1 3605 9 view .LVU2596 + 7664 00ba 84F84020 strb r2, [r4, #64] +3605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7665 .loc 1 3605 9 view .LVU2597 +3607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7666 .loc 1 3607 9 view .LVU2598 +3607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7667 .loc 1 3607 16 is_stmt 0 view .LVU2599 + 7668 00be 0120 movs r0, #1 + 7669 .LVL490: +3607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7670 .loc 1 3607 16 view .LVU2600 + 7671 00c0 48E0 b .L482 + 7672 .LVL491: + 7673 .L483: +3521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7674 .loc 1 3521 7 is_stmt 1 view .LVU2601 +3521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7675 .loc 1 3521 28 is_stmt 0 view .LVU2602 + 7676 00c2 638D ldrh r3, [r4, #42] +3521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7677 .loc 1 3521 22 view .LVU2603 + 7678 00c4 2385 strh r3, [r4, #40] @ movhi +3522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7679 .loc 1 3522 7 is_stmt 1 view .LVU2604 +3522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7680 .loc 1 3522 16 is_stmt 0 view .LVU2605 + 7681 00c6 E76A ldr r7, [r4, #44] + 7682 .LVL492: +3522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7683 .loc 1 3522 16 view .LVU2606 + 7684 00c8 C4E7 b .L484 + 7685 .L494: +3529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7686 .loc 1 3529 19 view .LVU2607 + 7687 00ca 4FF00008 mov r8, #0 + 7688 00ce D3E7 b .L486 + 7689 .L495: +3492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7690 .loc 1 3492 12 view .LVU2608 + 7691 00d0 DFF89C80 ldr r8, .L499+16 + 7692 00d4 D0E7 b .L486 + ARM GAS /tmp/ccEimIdZ.s page 295 + + + 7693 .LVL493: + 7694 .L488: +3563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7695 .loc 1 3563 9 is_stmt 1 view .LVU2609 +3563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7696 .loc 1 3563 25 is_stmt 0 view .LVU2610 + 7697 00d6 2023 movs r3, #32 + 7698 00d8 84F84130 strb r3, [r4, #65] +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7699 .loc 1 3564 9 is_stmt 1 view .LVU2611 +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7700 .loc 1 3564 25 is_stmt 0 view .LVU2612 + 7701 00dc 0022 movs r2, #0 + 7702 00de 84F84220 strb r2, [r4, #66] +3567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7703 .loc 1 3567 9 is_stmt 1 view .LVU2613 +3567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7704 .loc 1 3567 25 is_stmt 0 view .LVU2614 + 7705 00e2 636C ldr r3, [r4, #68] + 7706 00e4 43F08003 orr r3, r3, #128 + 7707 00e8 6364 str r3, [r4, #68] +3570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7708 .loc 1 3570 9 is_stmt 1 view .LVU2615 +3570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7709 .loc 1 3570 9 view .LVU2616 + 7710 00ea 84F84020 strb r2, [r4, #64] +3570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7711 .loc 1 3570 9 view .LVU2617 +3572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7712 .loc 1 3572 9 view .LVU2618 +3572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7713 .loc 1 3572 16 is_stmt 0 view .LVU2619 + 7714 00ee 0120 movs r0, #1 + 7715 00f0 30E0 b .L482 + 7716 .LVL494: + 7717 .L498: +3578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7718 .loc 1 3578 9 is_stmt 1 view .LVU2620 + 7719 00f2 CDF80080 str r8, [sp] + 7720 00f6 3B46 mov r3, r7 + 7721 00f8 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7722 00fc 3146 mov r1, r6 + 7723 00fe 2046 mov r0, r4 + 7724 .LVL495: +3578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7725 .loc 1 3578 9 is_stmt 0 view .LVU2621 + 7726 0100 FFF7FEFF bl I2C_TransferConfig + 7727 .LVL496: +3581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7728 .loc 1 3581 9 is_stmt 1 view .LVU2622 +3581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7729 .loc 1 3581 25 is_stmt 0 view .LVU2623 + 7730 0104 638D ldrh r3, [r4, #42] + 7731 0106 9BB2 uxth r3, r3 +3581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7732 .loc 1 3581 32 view .LVU2624 + 7733 0108 228D ldrh r2, [r4, #40] + ARM GAS /tmp/ccEimIdZ.s page 296 + + +3581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7734 .loc 1 3581 25 view .LVU2625 + 7735 010a 9B1A subs r3, r3, r2 + 7736 010c 9BB2 uxth r3, r3 + 7737 010e 6385 strh r3, [r4, #42] @ movhi +3584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7738 .loc 1 3584 9 is_stmt 1 view .LVU2626 +3584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7739 .loc 1 3584 9 view .LVU2627 + 7740 0110 0023 movs r3, #0 + 7741 0112 84F84030 strb r3, [r4, #64] +3584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7742 .loc 1 3584 9 view .LVU2628 +3590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7743 .loc 1 3590 9 view .LVU2629 + 7744 0116 1021 movs r1, #16 + 7745 0118 2046 mov r0, r4 + 7746 011a FFF7FEFF bl I2C_Enable_IRQ + 7747 .LVL497: +3593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7748 .loc 1 3593 9 view .LVU2630 +3593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7749 .loc 1 3593 13 is_stmt 0 view .LVU2631 + 7750 011e 2268 ldr r2, [r4] +3593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7751 .loc 1 3593 29 view .LVU2632 + 7752 0120 1368 ldr r3, [r2] + 7753 0122 43F40043 orr r3, r3, #32768 + 7754 0126 1360 str r3, [r2] + 7755 0128 11E0 b .L491 + 7756 .L487: +3613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7757 .loc 1 3613 7 is_stmt 1 view .LVU2633 +3613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7758 .loc 1 3613 21 is_stmt 0 view .LVU2634 + 7759 012a 104B ldr r3, .L499+12 + 7760 012c 6363 str r3, [r4, #52] +3617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7761 .loc 1 3617 7 is_stmt 1 view .LVU2635 + 7762 012e 104B ldr r3, .L499+16 + 7763 0130 0093 str r3, [sp] + 7764 0132 4FF00073 mov r3, #33554432 + 7765 0136 D2B2 uxtb r2, r2 + 7766 0138 3146 mov r1, r6 + 7767 013a 2046 mov r0, r4 + 7768 013c FFF7FEFF bl I2C_TransferConfig + 7769 .LVL498: +3620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7770 .loc 1 3620 7 view .LVU2636 +3620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7771 .loc 1 3620 7 view .LVU2637 + 7772 0140 0023 movs r3, #0 + 7773 0142 84F84030 strb r3, [r4, #64] +3620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7774 .loc 1 3620 7 view .LVU2638 +3628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7775 .loc 1 3628 7 view .LVU2639 + ARM GAS /tmp/ccEimIdZ.s page 297 + + + 7776 0146 0121 movs r1, #1 + 7777 0148 2046 mov r0, r4 + 7778 014a FFF7FEFF bl I2C_Enable_IRQ + 7779 .LVL499: + 7780 .L491: +3631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7781 .loc 1 3631 5 view .LVU2640 +3631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7782 .loc 1 3631 12 is_stmt 0 view .LVU2641 + 7783 014e 0020 movs r0, #0 + 7784 0150 00E0 b .L482 + 7785 .LVL500: + 7786 .L492: +3635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7787 .loc 1 3635 12 view .LVU2642 + 7788 0152 0220 movs r0, #2 + 7789 .LVL501: + 7790 .L482: +3637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7791 .loc 1 3637 1 view .LVU2643 + 7792 0154 02B0 add sp, sp, #8 + 7793 .LCFI97: + 7794 .cfi_remember_state + 7795 .cfi_def_cfa_offset 24 + 7796 @ sp needed + 7797 0156 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 7798 .LVL502: + 7799 .L493: + 7800 .LCFI98: + 7801 .cfi_restore_state +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7802 .loc 1 3501 5 view .LVU2644 + 7803 015a 0220 movs r0, #2 + 7804 015c FAE7 b .L482 + 7805 .L500: + 7806 015e 00BF .align 2 + 7807 .L499: + 7808 0160 00000000 .word I2C_Master_ISR_DMA + 7809 0164 00000000 .word I2C_DMAMasterReceiveCplt + 7810 0168 00000000 .word I2C_DMAError + 7811 016c 00000000 .word I2C_Master_ISR_IT + 7812 0170 00240080 .word -2147474432 + 7813 .cfi_endproc + 7814 .LFE167: + 7816 .section .text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits + 7817 .align 1 + 7818 .global HAL_I2C_Slave_Seq_Transmit_IT + 7819 .syntax unified + 7820 .thumb + 7821 .thumb_func + 7822 .fpu fpv5-d16 + 7824 HAL_I2C_Slave_Seq_Transmit_IT: + 7825 .LVL503: + 7826 .LFB168: +3650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ + 7827 .loc 1 3650 1 is_stmt 1 view -0 + 7828 .cfi_startproc + ARM GAS /tmp/ccEimIdZ.s page 298 + + + 7829 @ args = 0, pretend = 0, frame = 0 + 7830 @ frame_needed = 0, uses_anonymous_args = 0 +3650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ + 7831 .loc 1 3650 1 is_stmt 0 view .LVU2646 + 7832 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 7833 .LCFI99: + 7834 .cfi_def_cfa_offset 24 + 7835 .cfi_offset 3, -24 + 7836 .cfi_offset 4, -20 + 7837 .cfi_offset 5, -16 + 7838 .cfi_offset 6, -12 + 7839 .cfi_offset 7, -8 + 7840 .cfi_offset 14, -4 + 7841 0002 0446 mov r4, r0 +3652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7842 .loc 1 3652 3 is_stmt 1 view .LVU2647 +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7843 .loc 1 3654 3 view .LVU2648 +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7844 .loc 1 3654 22 is_stmt 0 view .LVU2649 + 7845 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7846 .LVL504: +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7847 .loc 1 3654 6 view .LVU2650 + 7848 0008 00F02800 and r0, r0, #40 + 7849 000c 2828 cmp r0, #40 + 7850 000e 5CD1 bne .L506 + 7851 0010 0F46 mov r7, r1 + 7852 0012 1646 mov r6, r2 + 7853 0014 1D46 mov r5, r3 +3656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7854 .loc 1 3656 5 is_stmt 1 view .LVU2651 +3656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7855 .loc 1 3656 8 is_stmt 0 view .LVU2652 + 7856 0016 002A cmp r2, #0 + 7857 0018 18BF it ne + 7858 001a 0029 cmpne r1, #0 + 7859 001c 04D1 bne .L503 +3658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 7860 .loc 1 3658 7 is_stmt 1 view .LVU2653 +3658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 7861 .loc 1 3658 23 is_stmt 0 view .LVU2654 + 7862 001e 4FF40073 mov r3, #512 + 7863 .LVL505: +3658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 7864 .loc 1 3658 23 view .LVU2655 + 7865 0022 6364 str r3, [r4, #68] +3659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7866 .loc 1 3659 7 is_stmt 1 view .LVU2656 +3659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7867 .loc 1 3659 15 is_stmt 0 view .LVU2657 + 7868 0024 0120 movs r0, #1 + 7869 0026 51E0 b .L502 + 7870 .LVL506: + 7871 .L503: +3663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7872 .loc 1 3663 5 is_stmt 1 view .LVU2658 + ARM GAS /tmp/ccEimIdZ.s page 299 + + + 7873 0028 48F20101 movw r1, #32769 + 7874 .LVL507: +3663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7875 .loc 1 3663 5 is_stmt 0 view .LVU2659 + 7876 002c 2046 mov r0, r4 + 7877 002e FFF7FEFF bl I2C_Disable_IRQ + 7878 .LVL508: +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7879 .loc 1 3666 5 is_stmt 1 view .LVU2660 +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7880 .loc 1 3666 5 view .LVU2661 + 7881 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 7882 0036 012B cmp r3, #1 + 7883 0038 49D0 beq .L507 +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7884 .loc 1 3666 5 discriminator 2 view .LVU2662 + 7885 003a 0123 movs r3, #1 + 7886 003c 84F84030 strb r3, [r4, #64] +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7887 .loc 1 3666 5 discriminator 2 view .LVU2663 +3670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7888 .loc 1 3670 5 discriminator 2 view .LVU2664 +3670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7889 .loc 1 3670 13 is_stmt 0 discriminator 2 view .LVU2665 + 7890 0040 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 7891 0044 DBB2 uxtb r3, r3 +3670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7892 .loc 1 3670 8 discriminator 2 view .LVU2666 + 7893 0046 2A2B cmp r3, #42 + 7894 0048 24D0 beq .L509 + 7895 .L504: +3696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7896 .loc 1 3696 5 is_stmt 1 view .LVU2667 +3696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7897 .loc 1 3696 21 is_stmt 0 view .LVU2668 + 7898 004a 2923 movs r3, #41 + 7899 004c 84F84130 strb r3, [r4, #65] +3697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7900 .loc 1 3697 5 is_stmt 1 view .LVU2669 +3697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7901 .loc 1 3697 21 is_stmt 0 view .LVU2670 + 7902 0050 2023 movs r3, #32 + 7903 0052 84F84230 strb r3, [r4, #66] +3698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7904 .loc 1 3698 5 is_stmt 1 view .LVU2671 +3698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7905 .loc 1 3698 21 is_stmt 0 view .LVU2672 + 7906 0056 0023 movs r3, #0 + 7907 0058 6364 str r3, [r4, #68] +3701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7908 .loc 1 3701 5 is_stmt 1 view .LVU2673 +3701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7909 .loc 1 3701 9 is_stmt 0 view .LVU2674 + 7910 005a 2268 ldr r2, [r4] +3701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7911 .loc 1 3701 25 view .LVU2675 + 7912 005c 5368 ldr r3, [r2, #4] + ARM GAS /tmp/ccEimIdZ.s page 300 + + + 7913 005e 23F40043 bic r3, r3, #32768 + 7914 0062 5360 str r3, [r2, #4] +3704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7915 .loc 1 3704 5 is_stmt 1 view .LVU2676 +3704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7916 .loc 1 3704 23 is_stmt 0 view .LVU2677 + 7917 0064 6762 str r7, [r4, #36] +3705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7918 .loc 1 3705 5 is_stmt 1 view .LVU2678 +3705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7919 .loc 1 3705 23 is_stmt 0 view .LVU2679 + 7920 0066 6685 strh r6, [r4, #42] @ movhi +3706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7921 .loc 1 3706 5 is_stmt 1 view .LVU2680 +3706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7922 .loc 1 3706 29 is_stmt 0 view .LVU2681 + 7923 0068 638D ldrh r3, [r4, #42] +3706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7924 .loc 1 3706 23 view .LVU2682 + 7925 006a 2385 strh r3, [r4, #40] @ movhi +3707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7926 .loc 1 3707 5 is_stmt 1 view .LVU2683 +3707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7927 .loc 1 3707 23 is_stmt 0 view .LVU2684 + 7928 006c E562 str r5, [r4, #44] +3708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7929 .loc 1 3708 5 is_stmt 1 view .LVU2685 +3708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7930 .loc 1 3708 23 is_stmt 0 view .LVU2686 + 7931 006e 194B ldr r3, .L510 + 7932 0070 6363 str r3, [r4, #52] +3710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7933 .loc 1 3710 5 is_stmt 1 view .LVU2687 +3710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7934 .loc 1 3710 9 is_stmt 0 view .LVU2688 + 7935 0072 2368 ldr r3, [r4] + 7936 0074 9A69 ldr r2, [r3, #24] +3710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7937 .loc 1 3710 8 view .LVU2689 + 7938 0076 12F4803F tst r2, #65536 + 7939 007a 01D0 beq .L505 +3714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7940 .loc 1 3714 7 is_stmt 1 view .LVU2690 + 7941 007c 0822 movs r2, #8 + 7942 007e DA61 str r2, [r3, #28] + 7943 .L505: +3718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7944 .loc 1 3718 5 view .LVU2691 +3718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7945 .loc 1 3718 5 view .LVU2692 + 7946 0080 0025 movs r5, #0 + 7947 .LVL509: +3718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7948 .loc 1 3718 5 is_stmt 0 view .LVU2693 + 7949 0082 84F84050 strb r5, [r4, #64] +3718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7950 .loc 1 3718 5 is_stmt 1 view .LVU2694 + ARM GAS /tmp/ccEimIdZ.s page 301 + + +3724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7951 .loc 1 3724 5 view .LVU2695 + 7952 0086 48F20101 movw r1, #32769 + 7953 008a 2046 mov r0, r4 + 7954 008c FFF7FEFF bl I2C_Enable_IRQ + 7955 .LVL510: +3726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7956 .loc 1 3726 5 view .LVU2696 +3726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7957 .loc 1 3726 12 is_stmt 0 view .LVU2697 + 7958 0090 2846 mov r0, r5 + 7959 0092 1BE0 b .L502 + 7960 .LVL511: + 7961 .L509: +3673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7962 .loc 1 3673 7 is_stmt 1 view .LVU2698 + 7963 0094 0221 movs r1, #2 + 7964 0096 2046 mov r0, r4 + 7965 0098 FFF7FEFF bl I2C_Disable_IRQ + 7966 .LVL512: +3676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7967 .loc 1 3676 7 view .LVU2699 +3676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7968 .loc 1 3676 16 is_stmt 0 view .LVU2700 + 7969 009c 2368 ldr r3, [r4] +3676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7970 .loc 1 3676 26 view .LVU2701 + 7971 009e 1A68 ldr r2, [r3] +3676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7972 .loc 1 3676 10 view .LVU2702 + 7973 00a0 12F4004F tst r2, #32768 + 7974 00a4 D1D0 beq .L504 +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7975 .loc 1 3678 9 is_stmt 1 view .LVU2703 +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7976 .loc 1 3678 29 is_stmt 0 view .LVU2704 + 7977 00a6 1A68 ldr r2, [r3] + 7978 00a8 22F40042 bic r2, r2, #32768 + 7979 00ac 1A60 str r2, [r3] +3680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7980 .loc 1 3680 9 is_stmt 1 view .LVU2705 +3680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7981 .loc 1 3680 17 is_stmt 0 view .LVU2706 + 7982 00ae E36B ldr r3, [r4, #60] +3680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7983 .loc 1 3680 12 view .LVU2707 + 7984 00b0 002B cmp r3, #0 + 7985 00b2 CAD0 beq .L504 +3684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7986 .loc 1 3684 11 is_stmt 1 view .LVU2708 +3684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 7987 .loc 1 3684 43 is_stmt 0 view .LVU2709 + 7988 00b4 084A ldr r2, .L510+4 + 7989 00b6 1A65 str r2, [r3, #80] +3687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7990 .loc 1 3687 11 is_stmt 1 view .LVU2710 +3687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 302 + + + 7991 .loc 1 3687 15 is_stmt 0 view .LVU2711 + 7992 00b8 E06B ldr r0, [r4, #60] + 7993 00ba FFF7FEFF bl HAL_DMA_Abort_IT + 7994 .LVL513: +3687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 7995 .loc 1 3687 14 view .LVU2712 + 7996 00be 0028 cmp r0, #0 + 7997 00c0 C3D0 beq .L504 +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7998 .loc 1 3690 13 is_stmt 1 view .LVU2713 +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 7999 .loc 1 3690 17 is_stmt 0 view .LVU2714 + 8000 00c2 E06B ldr r0, [r4, #60] +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8001 .loc 1 3690 25 view .LVU2715 + 8002 00c4 036D ldr r3, [r0, #80] +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8003 .loc 1 3690 13 view .LVU2716 + 8004 00c6 9847 blx r3 + 8005 .LVL514: + 8006 00c8 BFE7 b .L504 + 8007 .LVL515: + 8008 .L506: +3730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8009 .loc 1 3730 12 view .LVU2717 + 8010 00ca 0120 movs r0, #1 + 8011 .LVL516: + 8012 .L502: +3732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8013 .loc 1 3732 1 view .LVU2718 + 8014 00cc F8BD pop {r3, r4, r5, r6, r7, pc} + 8015 .LVL517: + 8016 .L507: +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8017 .loc 1 3666 5 view .LVU2719 + 8018 00ce 0220 movs r0, #2 + 8019 00d0 FCE7 b .L502 + 8020 .L511: + 8021 00d2 00BF .align 2 + 8022 .L510: + 8023 00d4 00000000 .word I2C_Slave_ISR_IT + 8024 00d8 00000000 .word I2C_DMAAbort + 8025 .cfi_endproc + 8026 .LFE168: + 8028 .section .text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits + 8029 .align 1 + 8030 .global HAL_I2C_Slave_Seq_Transmit_DMA + 8031 .syntax unified + 8032 .thumb + 8033 .thumb_func + 8034 .fpu fpv5-d16 + 8036 HAL_I2C_Slave_Seq_Transmit_DMA: + 8037 .LVL518: + 8038 .LFB169: +3745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8039 .loc 1 3745 1 is_stmt 1 view -0 + 8040 .cfi_startproc + ARM GAS /tmp/ccEimIdZ.s page 303 + + + 8041 @ args = 0, pretend = 0, frame = 0 + 8042 @ frame_needed = 0, uses_anonymous_args = 0 +3745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8043 .loc 1 3745 1 is_stmt 0 view .LVU2721 + 8044 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8045 .LCFI100: + 8046 .cfi_def_cfa_offset 24 + 8047 .cfi_offset 3, -24 + 8048 .cfi_offset 4, -20 + 8049 .cfi_offset 5, -16 + 8050 .cfi_offset 6, -12 + 8051 .cfi_offset 7, -8 + 8052 .cfi_offset 14, -4 + 8053 0002 0446 mov r4, r0 +3746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8054 .loc 1 3746 3 is_stmt 1 view .LVU2722 +3749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8055 .loc 1 3749 3 view .LVU2723 +3751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8056 .loc 1 3751 3 view .LVU2724 +3751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8057 .loc 1 3751 22 is_stmt 0 view .LVU2725 + 8058 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8059 .LVL519: +3751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8060 .loc 1 3751 6 view .LVU2726 + 8061 0008 00F02800 and r0, r0, #40 + 8062 000c 2828 cmp r0, #40 + 8063 000e 40F0BB80 bne .L522 + 8064 0012 0F46 mov r7, r1 + 8065 0014 1646 mov r6, r2 + 8066 0016 1D46 mov r5, r3 +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8067 .loc 1 3753 5 is_stmt 1 view .LVU2727 +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8068 .loc 1 3753 8 is_stmt 0 view .LVU2728 + 8069 0018 002A cmp r2, #0 + 8070 001a 18BF it ne + 8071 001c 0029 cmpne r1, #0 + 8072 001e 4FD0 beq .L526 +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8073 .loc 1 3760 5 is_stmt 1 view .LVU2729 +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8074 .loc 1 3760 5 view .LVU2730 + 8075 0020 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8076 .LVL520: +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8077 .loc 1 3760 5 is_stmt 0 view .LVU2731 + 8078 0024 012B cmp r3, #1 + 8079 0026 00F0B280 beq .L523 +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8080 .loc 1 3760 5 is_stmt 1 discriminator 2 view .LVU2732 + 8081 002a 0123 movs r3, #1 + 8082 002c 84F84030 strb r3, [r4, #64] +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8083 .loc 1 3760 5 discriminator 2 view .LVU2733 +3763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 304 + + + 8084 .loc 1 3763 5 discriminator 2 view .LVU2734 + 8085 0030 48F20101 movw r1, #32769 + 8086 .LVL521: +3763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8087 .loc 1 3763 5 is_stmt 0 discriminator 2 view .LVU2735 + 8088 0034 2046 mov r0, r4 + 8089 0036 FFF7FEFF bl I2C_Disable_IRQ + 8090 .LVL522: +3767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8091 .loc 1 3767 5 is_stmt 1 discriminator 2 view .LVU2736 +3767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8092 .loc 1 3767 13 is_stmt 0 discriminator 2 view .LVU2737 + 8093 003a 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8094 003e DBB2 uxtb r3, r3 +3767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8095 .loc 1 3767 8 discriminator 2 view .LVU2738 + 8096 0040 2A2B cmp r3, #42 + 8097 0042 42D0 beq .L527 +3792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8098 .loc 1 3792 10 is_stmt 1 view .LVU2739 +3792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8099 .loc 1 3792 18 is_stmt 0 view .LVU2740 + 8100 0044 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8101 0048 DBB2 uxtb r3, r3 +3792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8102 .loc 1 3792 13 view .LVU2741 + 8103 004a 292B cmp r3, #41 + 8104 004c 59D0 beq .L528 + 8105 .L516: +3817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8106 .loc 1 3817 5 is_stmt 1 view .LVU2742 +3819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8107 .loc 1 3819 5 view .LVU2743 +3819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8108 .loc 1 3819 21 is_stmt 0 view .LVU2744 + 8109 004e 2923 movs r3, #41 + 8110 0050 84F84130 strb r3, [r4, #65] +3820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8111 .loc 1 3820 5 is_stmt 1 view .LVU2745 +3820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8112 .loc 1 3820 21 is_stmt 0 view .LVU2746 + 8113 0054 2023 movs r3, #32 + 8114 0056 84F84230 strb r3, [r4, #66] +3821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8115 .loc 1 3821 5 is_stmt 1 view .LVU2747 +3821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8116 .loc 1 3821 21 is_stmt 0 view .LVU2748 + 8117 005a 0023 movs r3, #0 + 8118 005c 6364 str r3, [r4, #68] +3824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8119 .loc 1 3824 5 is_stmt 1 view .LVU2749 +3824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8120 .loc 1 3824 9 is_stmt 0 view .LVU2750 + 8121 005e 2268 ldr r2, [r4] +3824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8122 .loc 1 3824 25 view .LVU2751 + 8123 0060 5368 ldr r3, [r2, #4] + ARM GAS /tmp/ccEimIdZ.s page 305 + + + 8124 0062 23F40043 bic r3, r3, #32768 + 8125 0066 5360 str r3, [r2, #4] +3827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8126 .loc 1 3827 5 is_stmt 1 view .LVU2752 +3827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8127 .loc 1 3827 23 is_stmt 0 view .LVU2753 + 8128 0068 6762 str r7, [r4, #36] +3828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8129 .loc 1 3828 5 is_stmt 1 view .LVU2754 +3828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8130 .loc 1 3828 23 is_stmt 0 view .LVU2755 + 8131 006a 6685 strh r6, [r4, #42] @ movhi +3829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8132 .loc 1 3829 5 is_stmt 1 view .LVU2756 +3829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8133 .loc 1 3829 29 is_stmt 0 view .LVU2757 + 8134 006c 638D ldrh r3, [r4, #42] +3829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8135 .loc 1 3829 23 view .LVU2758 + 8136 006e 2385 strh r3, [r4, #40] @ movhi +3830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8137 .loc 1 3830 5 is_stmt 1 view .LVU2759 +3830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8138 .loc 1 3830 23 is_stmt 0 view .LVU2760 + 8139 0070 E562 str r5, [r4, #44] +3831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8140 .loc 1 3831 5 is_stmt 1 view .LVU2761 +3831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8141 .loc 1 3831 23 is_stmt 0 view .LVU2762 + 8142 0072 484B ldr r3, .L529 + 8143 0074 6363 str r3, [r4, #52] +3833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8144 .loc 1 3833 5 is_stmt 1 view .LVU2763 +3833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8145 .loc 1 3833 13 is_stmt 0 view .LVU2764 + 8146 0076 A36B ldr r3, [r4, #56] +3833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8147 .loc 1 3833 8 view .LVU2765 + 8148 0078 002B cmp r3, #0 + 8149 007a 59D0 beq .L517 +3836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8150 .loc 1 3836 7 is_stmt 1 view .LVU2766 +3836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8151 .loc 1 3836 38 is_stmt 0 view .LVU2767 + 8152 007c 464A ldr r2, .L529+4 + 8153 007e DA63 str r2, [r3, #60] +3839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8154 .loc 1 3839 7 is_stmt 1 view .LVU2768 +3839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8155 .loc 1 3839 11 is_stmt 0 view .LVU2769 + 8156 0080 A36B ldr r3, [r4, #56] +3839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8157 .loc 1 3839 39 view .LVU2770 + 8158 0082 464A ldr r2, .L529+8 + 8159 0084 DA64 str r2, [r3, #76] +3842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8160 .loc 1 3842 7 is_stmt 1 view .LVU2771 + ARM GAS /tmp/ccEimIdZ.s page 306 + + +3842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8161 .loc 1 3842 11 is_stmt 0 view .LVU2772 + 8162 0086 A26B ldr r2, [r4, #56] +3842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8163 .loc 1 3842 42 view .LVU2773 + 8164 0088 0023 movs r3, #0 + 8165 008a 1364 str r3, [r2, #64] +3843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8166 .loc 1 3843 7 is_stmt 1 view .LVU2774 +3843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8167 .loc 1 3843 11 is_stmt 0 view .LVU2775 + 8168 008c A26B ldr r2, [r4, #56] +3843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8169 .loc 1 3843 39 view .LVU2776 + 8170 008e 1365 str r3, [r2, #80] +3846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8171 .loc 1 3846 7 is_stmt 1 view .LVU2777 +3846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8172 .loc 1 3846 86 is_stmt 0 view .LVU2778 + 8173 0090 2268 ldr r2, [r4] +3846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8174 .loc 1 3846 23 view .LVU2779 + 8175 0092 238D ldrh r3, [r4, #40] + 8176 0094 2832 adds r2, r2, #40 + 8177 0096 3946 mov r1, r7 + 8178 0098 A06B ldr r0, [r4, #56] + 8179 009a FFF7FEFF bl HAL_DMA_Start_IT + 8180 .LVL523: +3863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8181 .loc 1 3863 5 is_stmt 1 view .LVU2780 +3863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8182 .loc 1 3863 8 is_stmt 0 view .LVU2781 + 8183 009e 0546 mov r5, r0 + 8184 .LVL524: +3863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8185 .loc 1 3863 8 view .LVU2782 + 8186 00a0 0028 cmp r0, #0 + 8187 00a2 53D0 beq .L518 +3874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8188 .loc 1 3874 7 is_stmt 1 view .LVU2783 +3874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8189 .loc 1 3874 23 is_stmt 0 view .LVU2784 + 8190 00a4 2823 movs r3, #40 + 8191 00a6 84F84130 strb r3, [r4, #65] +3875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8192 .loc 1 3875 7 is_stmt 1 view .LVU2785 +3875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8193 .loc 1 3875 23 is_stmt 0 view .LVU2786 + 8194 00aa 0022 movs r2, #0 + 8195 00ac 84F84220 strb r2, [r4, #66] +3878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8196 .loc 1 3878 7 is_stmt 1 view .LVU2787 +3878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8197 .loc 1 3878 23 is_stmt 0 view .LVU2788 + 8198 00b0 636C ldr r3, [r4, #68] + 8199 00b2 43F01003 orr r3, r3, #16 + 8200 00b6 6364 str r3, [r4, #68] + ARM GAS /tmp/ccEimIdZ.s page 307 + + +3881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8201 .loc 1 3881 7 is_stmt 1 view .LVU2789 +3881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8202 .loc 1 3881 7 view .LVU2790 + 8203 00b8 84F84020 strb r2, [r4, #64] +3881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8204 .loc 1 3881 7 view .LVU2791 +3883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8205 .loc 1 3883 7 view .LVU2792 +3883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8206 .loc 1 3883 14 is_stmt 0 view .LVU2793 + 8207 00bc 0125 movs r5, #1 + 8208 00be 64E0 b .L513 + 8209 .LVL525: + 8210 .L526: +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8211 .loc 1 3755 7 is_stmt 1 view .LVU2794 +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8212 .loc 1 3755 23 is_stmt 0 view .LVU2795 + 8213 00c0 4FF40073 mov r3, #512 + 8214 .LVL526: +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8215 .loc 1 3755 23 view .LVU2796 + 8216 00c4 6364 str r3, [r4, #68] +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8217 .loc 1 3756 7 is_stmt 1 view .LVU2797 +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8218 .loc 1 3756 15 is_stmt 0 view .LVU2798 + 8219 00c6 0125 movs r5, #1 + 8220 .LVL527: +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8221 .loc 1 3756 15 view .LVU2799 + 8222 00c8 5FE0 b .L513 + 8223 .LVL528: + 8224 .L527: +3770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8225 .loc 1 3770 7 is_stmt 1 view .LVU2800 + 8226 00ca 0221 movs r1, #2 + 8227 00cc 2046 mov r0, r4 + 8228 00ce FFF7FEFF bl I2C_Disable_IRQ + 8229 .LVL529: +3772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8230 .loc 1 3772 7 view .LVU2801 +3772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8231 .loc 1 3772 16 is_stmt 0 view .LVU2802 + 8232 00d2 2368 ldr r3, [r4] +3772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8233 .loc 1 3772 26 view .LVU2803 + 8234 00d4 1A68 ldr r2, [r3] +3772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8235 .loc 1 3772 10 view .LVU2804 + 8236 00d6 12F4004F tst r2, #32768 + 8237 00da B8D0 beq .L516 +3775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8238 .loc 1 3775 9 is_stmt 1 view .LVU2805 +3775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8239 .loc 1 3775 17 is_stmt 0 view .LVU2806 + ARM GAS /tmp/ccEimIdZ.s page 308 + + + 8240 00dc E26B ldr r2, [r4, #60] +3775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8241 .loc 1 3775 12 view .LVU2807 + 8242 00de 002A cmp r2, #0 + 8243 00e0 B5D0 beq .L516 +3777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8244 .loc 1 3777 11 is_stmt 1 view .LVU2808 +3777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8245 .loc 1 3777 31 is_stmt 0 view .LVU2809 + 8246 00e2 1A68 ldr r2, [r3] + 8247 00e4 22F40042 bic r2, r2, #32768 + 8248 00e8 1A60 str r2, [r3] +3781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8249 .loc 1 3781 11 is_stmt 1 view .LVU2810 +3781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8250 .loc 1 3781 15 is_stmt 0 view .LVU2811 + 8251 00ea E36B ldr r3, [r4, #60] +3781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8252 .loc 1 3781 43 view .LVU2812 + 8253 00ec 2C4A ldr r2, .L529+12 + 8254 00ee 1A65 str r2, [r3, #80] +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8255 .loc 1 3784 11 is_stmt 1 view .LVU2813 +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8256 .loc 1 3784 15 is_stmt 0 view .LVU2814 + 8257 00f0 E06B ldr r0, [r4, #60] + 8258 00f2 FFF7FEFF bl HAL_DMA_Abort_IT + 8259 .LVL530: +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8260 .loc 1 3784 14 view .LVU2815 + 8261 00f6 0028 cmp r0, #0 + 8262 00f8 A9D0 beq .L516 +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8263 .loc 1 3787 13 is_stmt 1 view .LVU2816 +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8264 .loc 1 3787 17 is_stmt 0 view .LVU2817 + 8265 00fa E06B ldr r0, [r4, #60] +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8266 .loc 1 3787 25 view .LVU2818 + 8267 00fc 036D ldr r3, [r0, #80] +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8268 .loc 1 3787 13 view .LVU2819 + 8269 00fe 9847 blx r3 + 8270 .LVL531: + 8271 0100 A5E7 b .L516 + 8272 .L528: +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8273 .loc 1 3794 7 is_stmt 1 view .LVU2820 +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8274 .loc 1 3794 16 is_stmt 0 view .LVU2821 + 8275 0102 2368 ldr r3, [r4] +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8276 .loc 1 3794 26 view .LVU2822 + 8277 0104 1A68 ldr r2, [r3] +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8278 .loc 1 3794 10 view .LVU2823 + 8279 0106 12F4804F tst r2, #16384 + ARM GAS /tmp/ccEimIdZ.s page 309 + + + 8280 010a A0D0 beq .L516 +3796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8281 .loc 1 3796 9 is_stmt 1 view .LVU2824 +3796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8282 .loc 1 3796 29 is_stmt 0 view .LVU2825 + 8283 010c 1A68 ldr r2, [r3] + 8284 010e 22F48042 bic r2, r2, #16384 + 8285 0112 1A60 str r2, [r3] +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8286 .loc 1 3799 9 is_stmt 1 view .LVU2826 +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8287 .loc 1 3799 17 is_stmt 0 view .LVU2827 + 8288 0114 A36B ldr r3, [r4, #56] +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8289 .loc 1 3799 12 view .LVU2828 + 8290 0116 002B cmp r3, #0 + 8291 0118 99D0 beq .L516 +3803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8292 .loc 1 3803 11 is_stmt 1 view .LVU2829 +3803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8293 .loc 1 3803 43 is_stmt 0 view .LVU2830 + 8294 011a 214A ldr r2, .L529+12 + 8295 011c 1A65 str r2, [r3, #80] +3806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8296 .loc 1 3806 11 is_stmt 1 view .LVU2831 +3806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8297 .loc 1 3806 15 is_stmt 0 view .LVU2832 + 8298 011e A06B ldr r0, [r4, #56] + 8299 0120 FFF7FEFF bl HAL_DMA_Abort_IT + 8300 .LVL532: +3806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8301 .loc 1 3806 14 view .LVU2833 + 8302 0124 0028 cmp r0, #0 + 8303 0126 92D0 beq .L516 +3809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8304 .loc 1 3809 13 is_stmt 1 view .LVU2834 +3809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8305 .loc 1 3809 17 is_stmt 0 view .LVU2835 + 8306 0128 A06B ldr r0, [r4, #56] +3809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8307 .loc 1 3809 25 view .LVU2836 + 8308 012a 036D ldr r3, [r0, #80] +3809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8309 .loc 1 3809 13 view .LVU2837 + 8310 012c 9847 blx r3 + 8311 .LVL533: + 8312 012e 8EE7 b .L516 + 8313 .L517: +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8314 .loc 1 3851 7 is_stmt 1 view .LVU2838 +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8315 .loc 1 3851 23 is_stmt 0 view .LVU2839 + 8316 0130 2823 movs r3, #40 + 8317 0132 84F84130 strb r3, [r4, #65] +3852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8318 .loc 1 3852 7 is_stmt 1 view .LVU2840 +3852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 310 + + + 8319 .loc 1 3852 23 is_stmt 0 view .LVU2841 + 8320 0136 0022 movs r2, #0 + 8321 0138 84F84220 strb r2, [r4, #66] +3855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8322 .loc 1 3855 7 is_stmt 1 view .LVU2842 +3855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8323 .loc 1 3855 23 is_stmt 0 view .LVU2843 + 8324 013c 636C ldr r3, [r4, #68] + 8325 013e 43F08003 orr r3, r3, #128 + 8326 0142 6364 str r3, [r4, #68] +3858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8327 .loc 1 3858 7 is_stmt 1 view .LVU2844 +3858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8328 .loc 1 3858 7 view .LVU2845 + 8329 0144 84F84020 strb r2, [r4, #64] +3858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8330 .loc 1 3858 7 view .LVU2846 +3860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8331 .loc 1 3860 7 view .LVU2847 +3860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8332 .loc 1 3860 14 is_stmt 0 view .LVU2848 + 8333 0148 0125 movs r5, #1 + 8334 .LVL534: +3860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8335 .loc 1 3860 14 view .LVU2849 + 8336 014a 1EE0 b .L513 + 8337 .LVL535: + 8338 .L518: +3866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8339 .loc 1 3866 7 is_stmt 1 view .LVU2850 +3866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8340 .loc 1 3866 23 is_stmt 0 view .LVU2851 + 8341 014c 638D ldrh r3, [r4, #42] + 8342 014e 9BB2 uxth r3, r3 +3866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8343 .loc 1 3866 30 view .LVU2852 + 8344 0150 228D ldrh r2, [r4, #40] +3866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8345 .loc 1 3866 23 view .LVU2853 + 8346 0152 9B1A subs r3, r3, r2 + 8347 0154 9BB2 uxth r3, r3 + 8348 0156 6385 strh r3, [r4, #42] @ movhi +3869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8349 .loc 1 3869 7 is_stmt 1 view .LVU2854 +3869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8350 .loc 1 3869 22 is_stmt 0 view .LVU2855 + 8351 0158 0023 movs r3, #0 + 8352 015a 2385 strh r3, [r4, #40] @ movhi +3886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8353 .loc 1 3886 5 is_stmt 1 view .LVU2856 +3886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8354 .loc 1 3886 9 is_stmt 0 view .LVU2857 + 8355 015c 2368 ldr r3, [r4] + 8356 015e 9A69 ldr r2, [r3, #24] +3886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8357 .loc 1 3886 8 view .LVU2858 + 8358 0160 12F4803F tst r2, #65536 + ARM GAS /tmp/ccEimIdZ.s page 311 + + + 8359 0164 0DD1 bne .L520 + 8360 .L521: +3894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8361 .loc 1 3894 5 is_stmt 1 view .LVU2859 +3894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8362 .loc 1 3894 5 view .LVU2860 + 8363 0166 0023 movs r3, #0 + 8364 0168 84F84030 strb r3, [r4, #64] +3894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8365 .loc 1 3894 5 view .LVU2861 +3900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8366 .loc 1 3900 5 view .LVU2862 + 8367 016c 4FF40041 mov r1, #32768 + 8368 0170 2046 mov r0, r4 + 8369 .LVL536: +3900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8370 .loc 1 3900 5 is_stmt 0 view .LVU2863 + 8371 0172 FFF7FEFF bl I2C_Enable_IRQ + 8372 .LVL537: +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8373 .loc 1 3903 5 is_stmt 1 view .LVU2864 +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8374 .loc 1 3903 9 is_stmt 0 view .LVU2865 + 8375 0176 2268 ldr r2, [r4] +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8376 .loc 1 3903 25 view .LVU2866 + 8377 0178 1368 ldr r3, [r2] + 8378 017a 43F48043 orr r3, r3, #16384 + 8379 017e 1360 str r3, [r2] +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8380 .loc 1 3905 5 is_stmt 1 view .LVU2867 +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8381 .loc 1 3905 12 is_stmt 0 view .LVU2868 + 8382 0180 03E0 b .L513 + 8383 .LVL538: + 8384 .L520: +3890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8385 .loc 1 3890 7 is_stmt 1 view .LVU2869 + 8386 0182 0822 movs r2, #8 + 8387 0184 DA61 str r2, [r3, #28] + 8388 0186 EEE7 b .L521 + 8389 .LVL539: + 8390 .L522: +3909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8391 .loc 1 3909 12 is_stmt 0 view .LVU2870 + 8392 0188 0125 movs r5, #1 + 8393 .LVL540: + 8394 .L513: +3911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8395 .loc 1 3911 1 view .LVU2871 + 8396 018a 2846 mov r0, r5 + 8397 018c F8BD pop {r3, r4, r5, r6, r7, pc} + 8398 .LVL541: + 8399 .L523: +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8400 .loc 1 3760 5 view .LVU2872 + 8401 018e 0225 movs r5, #2 + ARM GAS /tmp/ccEimIdZ.s page 312 + + + 8402 .LVL542: +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8403 .loc 1 3760 5 view .LVU2873 + 8404 0190 FBE7 b .L513 + 8405 .L530: + 8406 0192 00BF .align 2 + 8407 .L529: + 8408 0194 00000000 .word I2C_Slave_ISR_DMA + 8409 0198 00000000 .word I2C_DMASlaveTransmitCplt + 8410 019c 00000000 .word I2C_DMAError + 8411 01a0 00000000 .word I2C_DMAAbort + 8412 .cfi_endproc + 8413 .LFE169: + 8415 .section .text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits + 8416 .align 1 + 8417 .global HAL_I2C_Slave_Seq_Receive_IT + 8418 .syntax unified + 8419 .thumb + 8420 .thumb_func + 8421 .fpu fpv5-d16 + 8423 HAL_I2C_Slave_Seq_Receive_IT: + 8424 .LVL543: + 8425 .LFB170: +3924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ + 8426 .loc 1 3924 1 is_stmt 1 view -0 + 8427 .cfi_startproc + 8428 @ args = 0, pretend = 0, frame = 0 + 8429 @ frame_needed = 0, uses_anonymous_args = 0 +3924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Check the parameters */ + 8430 .loc 1 3924 1 is_stmt 0 view .LVU2875 + 8431 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8432 .LCFI101: + 8433 .cfi_def_cfa_offset 24 + 8434 .cfi_offset 3, -24 + 8435 .cfi_offset 4, -20 + 8436 .cfi_offset 5, -16 + 8437 .cfi_offset 6, -12 + 8438 .cfi_offset 7, -8 + 8439 .cfi_offset 14, -4 + 8440 0002 0446 mov r4, r0 +3926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8441 .loc 1 3926 3 is_stmt 1 view .LVU2876 +3928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8442 .loc 1 3928 3 view .LVU2877 +3928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8443 .loc 1 3928 22 is_stmt 0 view .LVU2878 + 8444 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8445 .LVL544: +3928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8446 .loc 1 3928 6 view .LVU2879 + 8447 0008 00F02800 and r0, r0, #40 + 8448 000c 2828 cmp r0, #40 + 8449 000e 5CD1 bne .L536 + 8450 0010 0F46 mov r7, r1 + 8451 0012 1646 mov r6, r2 + 8452 0014 1D46 mov r5, r3 +3930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 313 + + + 8453 .loc 1 3930 5 is_stmt 1 view .LVU2880 +3930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8454 .loc 1 3930 8 is_stmt 0 view .LVU2881 + 8455 0016 002A cmp r2, #0 + 8456 0018 18BF it ne + 8457 001a 0029 cmpne r1, #0 + 8458 001c 04D1 bne .L533 +3932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8459 .loc 1 3932 7 is_stmt 1 view .LVU2882 +3932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8460 .loc 1 3932 23 is_stmt 0 view .LVU2883 + 8461 001e 4FF40073 mov r3, #512 + 8462 .LVL545: +3932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8463 .loc 1 3932 23 view .LVU2884 + 8464 0022 6364 str r3, [r4, #68] +3933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8465 .loc 1 3933 7 is_stmt 1 view .LVU2885 +3933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8466 .loc 1 3933 15 is_stmt 0 view .LVU2886 + 8467 0024 0120 movs r0, #1 + 8468 0026 51E0 b .L532 + 8469 .LVL546: + 8470 .L533: +3937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8471 .loc 1 3937 5 is_stmt 1 view .LVU2887 + 8472 0028 48F20201 movw r1, #32770 + 8473 .LVL547: +3937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8474 .loc 1 3937 5 is_stmt 0 view .LVU2888 + 8475 002c 2046 mov r0, r4 + 8476 002e FFF7FEFF bl I2C_Disable_IRQ + 8477 .LVL548: +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8478 .loc 1 3940 5 is_stmt 1 view .LVU2889 +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8479 .loc 1 3940 5 view .LVU2890 + 8480 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8481 0036 012B cmp r3, #1 + 8482 0038 49D0 beq .L537 +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8483 .loc 1 3940 5 discriminator 2 view .LVU2891 + 8484 003a 0123 movs r3, #1 + 8485 003c 84F84030 strb r3, [r4, #64] +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8486 .loc 1 3940 5 discriminator 2 view .LVU2892 +3944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8487 .loc 1 3944 5 discriminator 2 view .LVU2893 +3944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8488 .loc 1 3944 13 is_stmt 0 discriminator 2 view .LVU2894 + 8489 0040 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8490 0044 DBB2 uxtb r3, r3 +3944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8491 .loc 1 3944 8 discriminator 2 view .LVU2895 + 8492 0046 292B cmp r3, #41 + 8493 0048 24D0 beq .L539 + 8494 .L534: + ARM GAS /tmp/ccEimIdZ.s page 314 + + +3970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8495 .loc 1 3970 5 is_stmt 1 view .LVU2896 +3970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8496 .loc 1 3970 21 is_stmt 0 view .LVU2897 + 8497 004a 2A23 movs r3, #42 + 8498 004c 84F84130 strb r3, [r4, #65] +3971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8499 .loc 1 3971 5 is_stmt 1 view .LVU2898 +3971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8500 .loc 1 3971 21 is_stmt 0 view .LVU2899 + 8501 0050 2023 movs r3, #32 + 8502 0052 84F84230 strb r3, [r4, #66] +3972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8503 .loc 1 3972 5 is_stmt 1 view .LVU2900 +3972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8504 .loc 1 3972 21 is_stmt 0 view .LVU2901 + 8505 0056 0023 movs r3, #0 + 8506 0058 6364 str r3, [r4, #68] +3975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8507 .loc 1 3975 5 is_stmt 1 view .LVU2902 +3975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8508 .loc 1 3975 9 is_stmt 0 view .LVU2903 + 8509 005a 2268 ldr r2, [r4] +3975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8510 .loc 1 3975 25 view .LVU2904 + 8511 005c 5368 ldr r3, [r2, #4] + 8512 005e 23F40043 bic r3, r3, #32768 + 8513 0062 5360 str r3, [r2, #4] +3978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8514 .loc 1 3978 5 is_stmt 1 view .LVU2905 +3978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8515 .loc 1 3978 23 is_stmt 0 view .LVU2906 + 8516 0064 6762 str r7, [r4, #36] +3979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8517 .loc 1 3979 5 is_stmt 1 view .LVU2907 +3979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8518 .loc 1 3979 23 is_stmt 0 view .LVU2908 + 8519 0066 6685 strh r6, [r4, #42] @ movhi +3980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8520 .loc 1 3980 5 is_stmt 1 view .LVU2909 +3980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8521 .loc 1 3980 29 is_stmt 0 view .LVU2910 + 8522 0068 638D ldrh r3, [r4, #42] +3980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8523 .loc 1 3980 23 view .LVU2911 + 8524 006a 2385 strh r3, [r4, #40] @ movhi +3981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8525 .loc 1 3981 5 is_stmt 1 view .LVU2912 +3981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8526 .loc 1 3981 23 is_stmt 0 view .LVU2913 + 8527 006c E562 str r5, [r4, #44] +3982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8528 .loc 1 3982 5 is_stmt 1 view .LVU2914 +3982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8529 .loc 1 3982 23 is_stmt 0 view .LVU2915 + 8530 006e 194B ldr r3, .L540 + 8531 0070 6363 str r3, [r4, #52] + ARM GAS /tmp/ccEimIdZ.s page 315 + + +3984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8532 .loc 1 3984 5 is_stmt 1 view .LVU2916 +3984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8533 .loc 1 3984 9 is_stmt 0 view .LVU2917 + 8534 0072 2368 ldr r3, [r4] + 8535 0074 9A69 ldr r2, [r3, #24] +3984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8536 .loc 1 3984 8 view .LVU2918 + 8537 0076 12F4803F tst r2, #65536 + 8538 007a 01D1 bne .L535 +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8539 .loc 1 3988 7 is_stmt 1 view .LVU2919 + 8540 007c 0822 movs r2, #8 + 8541 007e DA61 str r2, [r3, #28] + 8542 .L535: +3992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8543 .loc 1 3992 5 view .LVU2920 +3992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8544 .loc 1 3992 5 view .LVU2921 + 8545 0080 0025 movs r5, #0 + 8546 .LVL549: +3992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8547 .loc 1 3992 5 is_stmt 0 view .LVU2922 + 8548 0082 84F84050 strb r5, [r4, #64] +3992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8549 .loc 1 3992 5 is_stmt 1 view .LVU2923 +3998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8550 .loc 1 3998 5 view .LVU2924 + 8551 0086 48F20201 movw r1, #32770 + 8552 008a 2046 mov r0, r4 + 8553 008c FFF7FEFF bl I2C_Enable_IRQ + 8554 .LVL550: +4000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8555 .loc 1 4000 5 view .LVU2925 +4000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8556 .loc 1 4000 12 is_stmt 0 view .LVU2926 + 8557 0090 2846 mov r0, r5 + 8558 0092 1BE0 b .L532 + 8559 .LVL551: + 8560 .L539: +3947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8561 .loc 1 3947 7 is_stmt 1 view .LVU2927 + 8562 0094 0121 movs r1, #1 + 8563 0096 2046 mov r0, r4 + 8564 0098 FFF7FEFF bl I2C_Disable_IRQ + 8565 .LVL552: +3949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8566 .loc 1 3949 7 view .LVU2928 +3949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8567 .loc 1 3949 16 is_stmt 0 view .LVU2929 + 8568 009c 2368 ldr r3, [r4] +3949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8569 .loc 1 3949 26 view .LVU2930 + 8570 009e 1A68 ldr r2, [r3] +3949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8571 .loc 1 3949 10 view .LVU2931 + 8572 00a0 12F4804F tst r2, #16384 + ARM GAS /tmp/ccEimIdZ.s page 316 + + + 8573 00a4 D1D0 beq .L534 +3951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8574 .loc 1 3951 9 is_stmt 1 view .LVU2932 +3951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8575 .loc 1 3951 29 is_stmt 0 view .LVU2933 + 8576 00a6 1A68 ldr r2, [r3] + 8577 00a8 22F48042 bic r2, r2, #16384 + 8578 00ac 1A60 str r2, [r3] +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8579 .loc 1 3954 9 is_stmt 1 view .LVU2934 +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8580 .loc 1 3954 17 is_stmt 0 view .LVU2935 + 8581 00ae A36B ldr r3, [r4, #56] +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8582 .loc 1 3954 12 view .LVU2936 + 8583 00b0 002B cmp r3, #0 + 8584 00b2 CAD0 beq .L534 +3958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8585 .loc 1 3958 11 is_stmt 1 view .LVU2937 +3958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8586 .loc 1 3958 43 is_stmt 0 view .LVU2938 + 8587 00b4 084A ldr r2, .L540+4 + 8588 00b6 1A65 str r2, [r3, #80] +3961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8589 .loc 1 3961 11 is_stmt 1 view .LVU2939 +3961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8590 .loc 1 3961 15 is_stmt 0 view .LVU2940 + 8591 00b8 A06B ldr r0, [r4, #56] + 8592 00ba FFF7FEFF bl HAL_DMA_Abort_IT + 8593 .LVL553: +3961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8594 .loc 1 3961 14 view .LVU2941 + 8595 00be 0028 cmp r0, #0 + 8596 00c0 C3D0 beq .L534 +3964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8597 .loc 1 3964 13 is_stmt 1 view .LVU2942 +3964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8598 .loc 1 3964 17 is_stmt 0 view .LVU2943 + 8599 00c2 A06B ldr r0, [r4, #56] +3964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8600 .loc 1 3964 25 view .LVU2944 + 8601 00c4 036D ldr r3, [r0, #80] +3964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8602 .loc 1 3964 13 view .LVU2945 + 8603 00c6 9847 blx r3 + 8604 .LVL554: + 8605 00c8 BFE7 b .L534 + 8606 .LVL555: + 8607 .L536: +4004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8608 .loc 1 4004 12 view .LVU2946 + 8609 00ca 0120 movs r0, #1 + 8610 .LVL556: + 8611 .L532: +4006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8612 .loc 1 4006 1 view .LVU2947 + 8613 00cc F8BD pop {r3, r4, r5, r6, r7, pc} + ARM GAS /tmp/ccEimIdZ.s page 317 + + + 8614 .LVL557: + 8615 .L537: +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8616 .loc 1 3940 5 view .LVU2948 + 8617 00ce 0220 movs r0, #2 + 8618 00d0 FCE7 b .L532 + 8619 .L541: + 8620 00d2 00BF .align 2 + 8621 .L540: + 8622 00d4 00000000 .word I2C_Slave_ISR_IT + 8623 00d8 00000000 .word I2C_DMAAbort + 8624 .cfi_endproc + 8625 .LFE170: + 8627 .section .text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits + 8628 .align 1 + 8629 .global HAL_I2C_Slave_Seq_Receive_DMA + 8630 .syntax unified + 8631 .thumb + 8632 .thumb_func + 8633 .fpu fpv5-d16 + 8635 HAL_I2C_Slave_Seq_Receive_DMA: + 8636 .LVL558: + 8637 .LFB171: +4019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8638 .loc 1 4019 1 is_stmt 1 view -0 + 8639 .cfi_startproc + 8640 @ args = 0, pretend = 0, frame = 0 + 8641 @ frame_needed = 0, uses_anonymous_args = 0 +4019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8642 .loc 1 4019 1 is_stmt 0 view .LVU2950 + 8643 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8644 .LCFI102: + 8645 .cfi_def_cfa_offset 24 + 8646 .cfi_offset 3, -24 + 8647 .cfi_offset 4, -20 + 8648 .cfi_offset 5, -16 + 8649 .cfi_offset 6, -12 + 8650 .cfi_offset 7, -8 + 8651 .cfi_offset 14, -4 + 8652 0002 0446 mov r4, r0 +4020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8653 .loc 1 4020 3 is_stmt 1 view .LVU2951 +4023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8654 .loc 1 4023 3 view .LVU2952 +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8655 .loc 1 4025 3 view .LVU2953 +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8656 .loc 1 4025 22 is_stmt 0 view .LVU2954 + 8657 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8658 .LVL559: +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8659 .loc 1 4025 6 view .LVU2955 + 8660 0008 00F02800 and r0, r0, #40 + 8661 000c 2828 cmp r0, #40 + 8662 000e 40F0BB80 bne .L552 + 8663 0012 0F46 mov r7, r1 + 8664 0014 1646 mov r6, r2 + ARM GAS /tmp/ccEimIdZ.s page 318 + + + 8665 0016 1D46 mov r5, r3 +4027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8666 .loc 1 4027 5 is_stmt 1 view .LVU2956 +4027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8667 .loc 1 4027 8 is_stmt 0 view .LVU2957 + 8668 0018 002A cmp r2, #0 + 8669 001a 18BF it ne + 8670 001c 0029 cmpne r1, #0 + 8671 001e 04D1 bne .L544 +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8672 .loc 1 4029 7 is_stmt 1 view .LVU2958 +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8673 .loc 1 4029 23 is_stmt 0 view .LVU2959 + 8674 0020 4FF40073 mov r3, #512 + 8675 .LVL560: +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return HAL_ERROR; + 8676 .loc 1 4029 23 view .LVU2960 + 8677 0024 6364 str r3, [r4, #68] +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8678 .loc 1 4030 7 is_stmt 1 view .LVU2961 +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8679 .loc 1 4030 15 is_stmt 0 view .LVU2962 + 8680 0026 0125 movs r5, #1 + 8681 .LVL561: +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8682 .loc 1 4030 15 view .LVU2963 + 8683 0028 AFE0 b .L543 + 8684 .LVL562: + 8685 .L544: +4034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8686 .loc 1 4034 5 is_stmt 1 view .LVU2964 + 8687 002a 48F20201 movw r1, #32770 + 8688 .LVL563: +4034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8689 .loc 1 4034 5 is_stmt 0 view .LVU2965 + 8690 002e 2046 mov r0, r4 + 8691 0030 FFF7FEFF bl I2C_Disable_IRQ + 8692 .LVL564: +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8693 .loc 1 4037 5 is_stmt 1 view .LVU2966 +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8694 .loc 1 4037 5 view .LVU2967 + 8695 0034 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8696 0038 012B cmp r3, #1 + 8697 003a 00F0A880 beq .L553 +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8698 .loc 1 4037 5 discriminator 2 view .LVU2968 + 8699 003e 0123 movs r3, #1 + 8700 0040 84F84030 strb r3, [r4, #64] +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8701 .loc 1 4037 5 discriminator 2 view .LVU2969 +4041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8702 .loc 1 4041 5 discriminator 2 view .LVU2970 +4041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8703 .loc 1 4041 13 is_stmt 0 discriminator 2 view .LVU2971 + 8704 0044 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8705 0048 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 319 + + +4041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8706 .loc 1 4041 8 discriminator 2 view .LVU2972 + 8707 004a 292B cmp r3, #41 + 8708 004c 3DD0 beq .L556 +4066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8709 .loc 1 4066 10 is_stmt 1 view .LVU2973 +4066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8710 .loc 1 4066 18 is_stmt 0 view .LVU2974 + 8711 004e 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8712 0052 DBB2 uxtb r3, r3 +4066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8713 .loc 1 4066 13 view .LVU2975 + 8714 0054 2A2B cmp r3, #42 + 8715 0056 54D0 beq .L557 + 8716 .L546: +4091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8717 .loc 1 4091 5 is_stmt 1 view .LVU2976 +4093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8718 .loc 1 4093 5 view .LVU2977 +4093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8719 .loc 1 4093 21 is_stmt 0 view .LVU2978 + 8720 0058 2A23 movs r3, #42 + 8721 005a 84F84130 strb r3, [r4, #65] +4094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8722 .loc 1 4094 5 is_stmt 1 view .LVU2979 +4094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8723 .loc 1 4094 21 is_stmt 0 view .LVU2980 + 8724 005e 2023 movs r3, #32 + 8725 0060 84F84230 strb r3, [r4, #66] +4095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8726 .loc 1 4095 5 is_stmt 1 view .LVU2981 +4095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8727 .loc 1 4095 21 is_stmt 0 view .LVU2982 + 8728 0064 0023 movs r3, #0 + 8729 0066 6364 str r3, [r4, #68] +4098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8730 .loc 1 4098 5 is_stmt 1 view .LVU2983 +4098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8731 .loc 1 4098 9 is_stmt 0 view .LVU2984 + 8732 0068 2268 ldr r2, [r4] +4098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8733 .loc 1 4098 25 view .LVU2985 + 8734 006a 5368 ldr r3, [r2, #4] + 8735 006c 23F40043 bic r3, r3, #32768 + 8736 0070 5360 str r3, [r2, #4] +4101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8737 .loc 1 4101 5 is_stmt 1 view .LVU2986 +4101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8738 .loc 1 4101 23 is_stmt 0 view .LVU2987 + 8739 0072 6762 str r7, [r4, #36] +4102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8740 .loc 1 4102 5 is_stmt 1 view .LVU2988 +4102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8741 .loc 1 4102 23 is_stmt 0 view .LVU2989 + 8742 0074 6685 strh r6, [r4, #42] @ movhi +4103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8743 .loc 1 4103 5 is_stmt 1 view .LVU2990 + ARM GAS /tmp/ccEimIdZ.s page 320 + + +4103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8744 .loc 1 4103 29 is_stmt 0 view .LVU2991 + 8745 0076 638D ldrh r3, [r4, #42] +4103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8746 .loc 1 4103 23 view .LVU2992 + 8747 0078 2385 strh r3, [r4, #40] @ movhi +4104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8748 .loc 1 4104 5 is_stmt 1 view .LVU2993 +4104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8749 .loc 1 4104 23 is_stmt 0 view .LVU2994 + 8750 007a E562 str r5, [r4, #44] +4105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8751 .loc 1 4105 5 is_stmt 1 view .LVU2995 +4105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8752 .loc 1 4105 23 is_stmt 0 view .LVU2996 + 8753 007c 454B ldr r3, .L558 + 8754 007e 6363 str r3, [r4, #52] +4107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8755 .loc 1 4107 5 is_stmt 1 view .LVU2997 +4107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8756 .loc 1 4107 13 is_stmt 0 view .LVU2998 + 8757 0080 E36B ldr r3, [r4, #60] +4107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8758 .loc 1 4107 8 view .LVU2999 + 8759 0082 002B cmp r3, #0 + 8760 0084 54D0 beq .L547 +4110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8761 .loc 1 4110 7 is_stmt 1 view .LVU3000 +4110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8762 .loc 1 4110 38 is_stmt 0 view .LVU3001 + 8763 0086 444A ldr r2, .L558+4 + 8764 0088 DA63 str r2, [r3, #60] +4113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8765 .loc 1 4113 7 is_stmt 1 view .LVU3002 +4113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8766 .loc 1 4113 11 is_stmt 0 view .LVU3003 + 8767 008a E36B ldr r3, [r4, #60] +4113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8768 .loc 1 4113 39 view .LVU3004 + 8769 008c 434A ldr r2, .L558+8 + 8770 008e DA64 str r2, [r3, #76] +4116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8771 .loc 1 4116 7 is_stmt 1 view .LVU3005 +4116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8772 .loc 1 4116 11 is_stmt 0 view .LVU3006 + 8773 0090 E26B ldr r2, [r4, #60] +4116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8774 .loc 1 4116 42 view .LVU3007 + 8775 0092 0023 movs r3, #0 + 8776 0094 1364 str r3, [r2, #64] +4117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8777 .loc 1 4117 7 is_stmt 1 view .LVU3008 +4117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8778 .loc 1 4117 11 is_stmt 0 view .LVU3009 + 8779 0096 E26B ldr r2, [r4, #60] +4117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8780 .loc 1 4117 39 view .LVU3010 + ARM GAS /tmp/ccEimIdZ.s page 321 + + + 8781 0098 1365 str r3, [r2, #80] +4120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8782 .loc 1 4120 7 is_stmt 1 view .LVU3011 +4120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8783 .loc 1 4120 69 is_stmt 0 view .LVU3012 + 8784 009a 2168 ldr r1, [r4] +4120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8785 .loc 1 4120 23 view .LVU3013 + 8786 009c 238D ldrh r3, [r4, #40] + 8787 009e 3A46 mov r2, r7 + 8788 00a0 2431 adds r1, r1, #36 + 8789 00a2 E06B ldr r0, [r4, #60] + 8790 00a4 FFF7FEFF bl HAL_DMA_Start_IT + 8791 .LVL565: +4137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8792 .loc 1 4137 5 is_stmt 1 view .LVU3014 +4137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8793 .loc 1 4137 8 is_stmt 0 view .LVU3015 + 8794 00a8 0546 mov r5, r0 + 8795 .LVL566: +4137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8796 .loc 1 4137 8 view .LVU3016 + 8797 00aa 0028 cmp r0, #0 + 8798 00ac 4ED0 beq .L548 +4148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8799 .loc 1 4148 7 is_stmt 1 view .LVU3017 +4148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8800 .loc 1 4148 23 is_stmt 0 view .LVU3018 + 8801 00ae 2823 movs r3, #40 + 8802 00b0 84F84130 strb r3, [r4, #65] +4149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8803 .loc 1 4149 7 is_stmt 1 view .LVU3019 +4149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8804 .loc 1 4149 23 is_stmt 0 view .LVU3020 + 8805 00b4 0022 movs r2, #0 + 8806 00b6 84F84220 strb r2, [r4, #66] +4152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8807 .loc 1 4152 7 is_stmt 1 view .LVU3021 +4152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8808 .loc 1 4152 23 is_stmt 0 view .LVU3022 + 8809 00ba 636C ldr r3, [r4, #68] + 8810 00bc 43F01003 orr r3, r3, #16 + 8811 00c0 6364 str r3, [r4, #68] +4155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8812 .loc 1 4155 7 is_stmt 1 view .LVU3023 +4155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8813 .loc 1 4155 7 view .LVU3024 + 8814 00c2 84F84020 strb r2, [r4, #64] +4155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8815 .loc 1 4155 7 view .LVU3025 +4157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8816 .loc 1 4157 7 view .LVU3026 +4157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8817 .loc 1 4157 14 is_stmt 0 view .LVU3027 + 8818 00c6 0125 movs r5, #1 + 8819 00c8 5FE0 b .L543 + 8820 .LVL567: + ARM GAS /tmp/ccEimIdZ.s page 322 + + + 8821 .L556: +4044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8822 .loc 1 4044 7 is_stmt 1 view .LVU3028 + 8823 00ca 0121 movs r1, #1 + 8824 00cc 2046 mov r0, r4 + 8825 00ce FFF7FEFF bl I2C_Disable_IRQ + 8826 .LVL568: +4046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8827 .loc 1 4046 7 view .LVU3029 +4046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8828 .loc 1 4046 16 is_stmt 0 view .LVU3030 + 8829 00d2 2368 ldr r3, [r4] +4046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8830 .loc 1 4046 26 view .LVU3031 + 8831 00d4 1A68 ldr r2, [r3] +4046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8832 .loc 1 4046 10 view .LVU3032 + 8833 00d6 12F4804F tst r2, #16384 + 8834 00da BDD0 beq .L546 +4049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8835 .loc 1 4049 9 is_stmt 1 view .LVU3033 +4049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8836 .loc 1 4049 17 is_stmt 0 view .LVU3034 + 8837 00dc A26B ldr r2, [r4, #56] +4049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8838 .loc 1 4049 12 view .LVU3035 + 8839 00de 002A cmp r2, #0 + 8840 00e0 BAD0 beq .L546 +4051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8841 .loc 1 4051 11 is_stmt 1 view .LVU3036 +4051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8842 .loc 1 4051 31 is_stmt 0 view .LVU3037 + 8843 00e2 1A68 ldr r2, [r3] + 8844 00e4 22F48042 bic r2, r2, #16384 + 8845 00e8 1A60 str r2, [r3] +4055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8846 .loc 1 4055 11 is_stmt 1 view .LVU3038 +4055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8847 .loc 1 4055 15 is_stmt 0 view .LVU3039 + 8848 00ea A36B ldr r3, [r4, #56] +4055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8849 .loc 1 4055 43 view .LVU3040 + 8850 00ec 2C4A ldr r2, .L558+12 + 8851 00ee 1A65 str r2, [r3, #80] +4058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8852 .loc 1 4058 11 is_stmt 1 view .LVU3041 +4058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8853 .loc 1 4058 15 is_stmt 0 view .LVU3042 + 8854 00f0 A06B ldr r0, [r4, #56] + 8855 00f2 FFF7FEFF bl HAL_DMA_Abort_IT + 8856 .LVL569: +4058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8857 .loc 1 4058 14 view .LVU3043 + 8858 00f6 0028 cmp r0, #0 + 8859 00f8 AED0 beq .L546 +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8860 .loc 1 4061 13 is_stmt 1 view .LVU3044 + ARM GAS /tmp/ccEimIdZ.s page 323 + + +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8861 .loc 1 4061 17 is_stmt 0 view .LVU3045 + 8862 00fa A06B ldr r0, [r4, #56] +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8863 .loc 1 4061 25 view .LVU3046 + 8864 00fc 036D ldr r3, [r0, #80] +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8865 .loc 1 4061 13 view .LVU3047 + 8866 00fe 9847 blx r3 + 8867 .LVL570: + 8868 0100 AAE7 b .L546 + 8869 .L557: +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8870 .loc 1 4068 7 is_stmt 1 view .LVU3048 +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8871 .loc 1 4068 16 is_stmt 0 view .LVU3049 + 8872 0102 2368 ldr r3, [r4] +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8873 .loc 1 4068 26 view .LVU3050 + 8874 0104 1A68 ldr r2, [r3] +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8875 .loc 1 4068 10 view .LVU3051 + 8876 0106 12F4004F tst r2, #32768 + 8877 010a A5D0 beq .L546 +4070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8878 .loc 1 4070 9 is_stmt 1 view .LVU3052 +4070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8879 .loc 1 4070 29 is_stmt 0 view .LVU3053 + 8880 010c 1A68 ldr r2, [r3] + 8881 010e 22F40042 bic r2, r2, #32768 + 8882 0112 1A60 str r2, [r3] +4073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8883 .loc 1 4073 9 is_stmt 1 view .LVU3054 +4073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8884 .loc 1 4073 17 is_stmt 0 view .LVU3055 + 8885 0114 E36B ldr r3, [r4, #60] +4073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8886 .loc 1 4073 12 view .LVU3056 + 8887 0116 002B cmp r3, #0 + 8888 0118 9ED0 beq .L546 +4077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8889 .loc 1 4077 11 is_stmt 1 view .LVU3057 +4077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8890 .loc 1 4077 43 is_stmt 0 view .LVU3058 + 8891 011a 214A ldr r2, .L558+12 + 8892 011c 1A65 str r2, [r3, #80] +4080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8893 .loc 1 4080 11 is_stmt 1 view .LVU3059 +4080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8894 .loc 1 4080 15 is_stmt 0 view .LVU3060 + 8895 011e E06B ldr r0, [r4, #60] + 8896 0120 FFF7FEFF bl HAL_DMA_Abort_IT + 8897 .LVL571: +4080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8898 .loc 1 4080 14 view .LVU3061 + 8899 0124 0028 cmp r0, #0 + 8900 0126 97D0 beq .L546 + ARM GAS /tmp/ccEimIdZ.s page 324 + + +4083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8901 .loc 1 4083 13 is_stmt 1 view .LVU3062 +4083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8902 .loc 1 4083 17 is_stmt 0 view .LVU3063 + 8903 0128 E06B ldr r0, [r4, #60] +4083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8904 .loc 1 4083 25 view .LVU3064 + 8905 012a 036D ldr r3, [r0, #80] +4083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8906 .loc 1 4083 13 view .LVU3065 + 8907 012c 9847 blx r3 + 8908 .LVL572: + 8909 012e 93E7 b .L546 + 8910 .L547: +4125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8911 .loc 1 4125 7 is_stmt 1 view .LVU3066 +4125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8912 .loc 1 4125 23 is_stmt 0 view .LVU3067 + 8913 0130 2823 movs r3, #40 + 8914 0132 84F84130 strb r3, [r4, #65] +4126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8915 .loc 1 4126 7 is_stmt 1 view .LVU3068 +4126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8916 .loc 1 4126 23 is_stmt 0 view .LVU3069 + 8917 0136 0022 movs r2, #0 + 8918 0138 84F84220 strb r2, [r4, #66] +4129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8919 .loc 1 4129 7 is_stmt 1 view .LVU3070 +4129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8920 .loc 1 4129 23 is_stmt 0 view .LVU3071 + 8921 013c 636C ldr r3, [r4, #68] + 8922 013e 43F08003 orr r3, r3, #128 + 8923 0142 6364 str r3, [r4, #68] +4132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8924 .loc 1 4132 7 is_stmt 1 view .LVU3072 +4132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8925 .loc 1 4132 7 view .LVU3073 + 8926 0144 84F84020 strb r2, [r4, #64] +4132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8927 .loc 1 4132 7 view .LVU3074 +4134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8928 .loc 1 4134 7 view .LVU3075 +4134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8929 .loc 1 4134 14 is_stmt 0 view .LVU3076 + 8930 0148 0125 movs r5, #1 + 8931 .LVL573: +4134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8932 .loc 1 4134 14 view .LVU3077 + 8933 014a 1EE0 b .L543 + 8934 .LVL574: + 8935 .L548: +4140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8936 .loc 1 4140 7 is_stmt 1 view .LVU3078 +4140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8937 .loc 1 4140 23 is_stmt 0 view .LVU3079 + 8938 014c 638D ldrh r3, [r4, #42] + 8939 014e 9BB2 uxth r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 325 + + +4140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8940 .loc 1 4140 30 view .LVU3080 + 8941 0150 228D ldrh r2, [r4, #40] +4140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8942 .loc 1 4140 23 view .LVU3081 + 8943 0152 9B1A subs r3, r3, r2 + 8944 0154 9BB2 uxth r3, r3 + 8945 0156 6385 strh r3, [r4, #42] @ movhi +4143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8946 .loc 1 4143 7 is_stmt 1 view .LVU3082 +4143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8947 .loc 1 4143 22 is_stmt 0 view .LVU3083 + 8948 0158 0023 movs r3, #0 + 8949 015a 2385 strh r3, [r4, #40] @ movhi +4160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8950 .loc 1 4160 5 is_stmt 1 view .LVU3084 +4160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8951 .loc 1 4160 9 is_stmt 0 view .LVU3085 + 8952 015c 2368 ldr r3, [r4] + 8953 015e 9A69 ldr r2, [r3, #24] +4160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 8954 .loc 1 4160 8 view .LVU3086 + 8955 0160 12F4803F tst r2, #65536 + 8956 0164 0DD0 beq .L550 + 8957 .L551: +4168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8958 .loc 1 4168 5 is_stmt 1 view .LVU3087 +4168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8959 .loc 1 4168 5 view .LVU3088 + 8960 0166 0023 movs r3, #0 + 8961 0168 84F84030 strb r3, [r4, #64] +4168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8962 .loc 1 4168 5 view .LVU3089 +4174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8963 .loc 1 4174 5 view .LVU3090 + 8964 016c 48F20201 movw r1, #32770 + 8965 0170 2046 mov r0, r4 + 8966 .LVL575: +4174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8967 .loc 1 4174 5 is_stmt 0 view .LVU3091 + 8968 0172 FFF7FEFF bl I2C_Enable_IRQ + 8969 .LVL576: +4177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8970 .loc 1 4177 5 is_stmt 1 view .LVU3092 +4177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8971 .loc 1 4177 9 is_stmt 0 view .LVU3093 + 8972 0176 2268 ldr r2, [r4] +4177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8973 .loc 1 4177 25 view .LVU3094 + 8974 0178 1368 ldr r3, [r2] + 8975 017a 43F40043 orr r3, r3, #32768 + 8976 017e 1360 str r3, [r2] +4179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8977 .loc 1 4179 5 is_stmt 1 view .LVU3095 +4179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8978 .loc 1 4179 12 is_stmt 0 view .LVU3096 + 8979 0180 03E0 b .L543 + ARM GAS /tmp/ccEimIdZ.s page 326 + + + 8980 .LVL577: + 8981 .L550: +4164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8982 .loc 1 4164 7 is_stmt 1 view .LVU3097 + 8983 0182 0822 movs r2, #8 + 8984 0184 DA61 str r2, [r3, #28] + 8985 0186 EEE7 b .L551 + 8986 .LVL578: + 8987 .L552: +4183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 8988 .loc 1 4183 12 is_stmt 0 view .LVU3098 + 8989 0188 0125 movs r5, #1 + 8990 .LVL579: + 8991 .L543: +4185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8992 .loc 1 4185 1 view .LVU3099 + 8993 018a 2846 mov r0, r5 + 8994 018c F8BD pop {r3, r4, r5, r6, r7, pc} + 8995 .LVL580: + 8996 .L553: +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 8997 .loc 1 4037 5 view .LVU3100 + 8998 018e 0225 movs r5, #2 + 8999 .LVL581: +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9000 .loc 1 4037 5 view .LVU3101 + 9001 0190 FBE7 b .L543 + 9002 .L559: + 9003 0192 00BF .align 2 + 9004 .L558: + 9005 0194 00000000 .word I2C_Slave_ISR_DMA + 9006 0198 00000000 .word I2C_DMASlaveReceiveCplt + 9007 019c 00000000 .word I2C_DMAError + 9008 01a0 00000000 .word I2C_DMAAbort + 9009 .cfi_endproc + 9010 .LFE171: + 9012 .section .text.HAL_I2C_EnableListen_IT,"ax",%progbits + 9013 .align 1 + 9014 .global HAL_I2C_EnableListen_IT + 9015 .syntax unified + 9016 .thumb + 9017 .thumb_func + 9018 .fpu fpv5-d16 + 9020 HAL_I2C_EnableListen_IT: + 9021 .LVL582: + 9022 .LFB172: +4194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 9023 .loc 1 4194 1 is_stmt 1 view -0 + 9024 .cfi_startproc + 9025 @ args = 0, pretend = 0, frame = 0 + 9026 @ frame_needed = 0, uses_anonymous_args = 0 +4194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 9027 .loc 1 4194 1 is_stmt 0 view .LVU3103 + 9028 0000 08B5 push {r3, lr} + 9029 .LCFI103: + 9030 .cfi_def_cfa_offset 8 + 9031 .cfi_offset 3, -8 + ARM GAS /tmp/ccEimIdZ.s page 327 + + + 9032 .cfi_offset 14, -4 +4195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9033 .loc 1 4195 3 is_stmt 1 view .LVU3104 +4195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9034 .loc 1 4195 11 is_stmt 0 view .LVU3105 + 9035 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9036 0006 DBB2 uxtb r3, r3 +4195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9037 .loc 1 4195 6 view .LVU3106 + 9038 0008 202B cmp r3, #32 + 9039 000a 01D0 beq .L564 +4207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9040 .loc 1 4207 12 view .LVU3107 + 9041 000c 0220 movs r0, #2 + 9042 .LVL583: + 9043 .L561: +4209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9044 .loc 1 4209 1 view .LVU3108 + 9045 000e 08BD pop {r3, pc} + 9046 .LVL584: + 9047 .L564: +4197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9048 .loc 1 4197 5 is_stmt 1 view .LVU3109 +4197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9049 .loc 1 4197 17 is_stmt 0 view .LVU3110 + 9050 0010 2823 movs r3, #40 + 9051 0012 80F84130 strb r3, [r0, #65] +4198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9052 .loc 1 4198 5 is_stmt 1 view .LVU3111 +4198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9053 .loc 1 4198 19 is_stmt 0 view .LVU3112 + 9054 0016 044B ldr r3, .L565 + 9055 0018 4363 str r3, [r0, #52] +4201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9056 .loc 1 4201 5 is_stmt 1 view .LVU3113 + 9057 001a 4FF40041 mov r1, #32768 + 9058 001e FFF7FEFF bl I2C_Enable_IRQ + 9059 .LVL585: +4203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9060 .loc 1 4203 5 view .LVU3114 +4203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9061 .loc 1 4203 12 is_stmt 0 view .LVU3115 + 9062 0022 0020 movs r0, #0 + 9063 0024 F3E7 b .L561 + 9064 .L566: + 9065 0026 00BF .align 2 + 9066 .L565: + 9067 0028 00000000 .word I2C_Slave_ISR_IT + 9068 .cfi_endproc + 9069 .LFE172: + 9071 .section .text.HAL_I2C_DisableListen_IT,"ax",%progbits + 9072 .align 1 + 9073 .global HAL_I2C_DisableListen_IT + 9074 .syntax unified + 9075 .thumb + 9076 .thumb_func + 9077 .fpu fpv5-d16 + ARM GAS /tmp/ccEimIdZ.s page 328 + + + 9079 HAL_I2C_DisableListen_IT: + 9080 .LVL586: + 9081 .LFB173: +4218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9082 .loc 1 4218 1 is_stmt 1 view -0 + 9083 .cfi_startproc + 9084 @ args = 0, pretend = 0, frame = 0 + 9085 @ frame_needed = 0, uses_anonymous_args = 0 +4220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9086 .loc 1 4220 3 view .LVU3117 +4223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9087 .loc 1 4223 3 view .LVU3118 +4223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9088 .loc 1 4223 11 is_stmt 0 view .LVU3119 + 9089 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9090 0004 DBB2 uxtb r3, r3 +4223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9091 .loc 1 4223 6 view .LVU3120 + 9092 0006 282B cmp r3, #40 + 9093 0008 01D0 beq .L574 +4238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9094 .loc 1 4238 12 view .LVU3121 + 9095 000a 0220 movs r0, #2 + 9096 .LVL587: +4240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9097 .loc 1 4240 1 view .LVU3122 + 9098 000c 7047 bx lr + 9099 .LVL588: + 9100 .L574: +4218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9101 .loc 1 4218 1 view .LVU3123 + 9102 000e 10B5 push {r4, lr} + 9103 .LCFI104: + 9104 .cfi_def_cfa_offset 8 + 9105 .cfi_offset 4, -8 + 9106 .cfi_offset 14, -4 +4225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9107 .loc 1 4225 5 is_stmt 1 view .LVU3124 +4225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9108 .loc 1 4225 26 is_stmt 0 view .LVU3125 + 9109 0010 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 9110 .LVL589: +4226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9111 .loc 1 4226 5 is_stmt 1 view .LVU3126 +4226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9112 .loc 1 4226 48 is_stmt 0 view .LVU3127 + 9113 0014 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 +4226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9114 .loc 1 4226 31 view .LVU3128 + 9115 0018 02F00302 and r2, r2, #3 + 9116 .LVL590: +4226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9117 .loc 1 4226 31 view .LVU3129 + 9118 001c 1343 orrs r3, r3, r2 +4226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9119 .loc 1 4226 25 view .LVU3130 + 9120 001e 0363 str r3, [r0, #48] + ARM GAS /tmp/ccEimIdZ.s page 329 + + +4227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9121 .loc 1 4227 5 is_stmt 1 view .LVU3131 +4227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9122 .loc 1 4227 17 is_stmt 0 view .LVU3132 + 9123 0020 2023 movs r3, #32 + 9124 0022 80F84130 strb r3, [r0, #65] +4228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9125 .loc 1 4228 5 is_stmt 1 view .LVU3133 +4228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9126 .loc 1 4228 16 is_stmt 0 view .LVU3134 + 9127 0026 0024 movs r4, #0 + 9128 0028 80F84240 strb r4, [r0, #66] +4229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9129 .loc 1 4229 5 is_stmt 1 view .LVU3135 +4229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9130 .loc 1 4229 19 is_stmt 0 view .LVU3136 + 9131 002c 4463 str r4, [r0, #52] +4232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9132 .loc 1 4232 5 is_stmt 1 view .LVU3137 + 9133 002e 4FF40041 mov r1, #32768 + 9134 0032 FFF7FEFF bl I2C_Disable_IRQ + 9135 .LVL591: +4234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9136 .loc 1 4234 5 view .LVU3138 +4234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9137 .loc 1 4234 12 is_stmt 0 view .LVU3139 + 9138 0036 2046 mov r0, r4 +4240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9139 .loc 1 4240 1 view .LVU3140 + 9140 0038 10BD pop {r4, pc} + 9141 .cfi_endproc + 9142 .LFE173: + 9144 .section .text.HAL_I2C_Master_Abort_IT,"ax",%progbits + 9145 .align 1 + 9146 .global HAL_I2C_Master_Abort_IT + 9147 .syntax unified + 9148 .thumb + 9149 .thumb_func + 9150 .fpu fpv5-d16 + 9152 HAL_I2C_Master_Abort_IT: + 9153 .LVL592: + 9154 .LFB174: +4251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 9155 .loc 1 4251 1 is_stmt 1 view -0 + 9156 .cfi_startproc + 9157 @ args = 0, pretend = 0, frame = 0 + 9158 @ frame_needed = 0, uses_anonymous_args = 0 +4252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9159 .loc 1 4252 3 view .LVU3142 +4252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9160 .loc 1 4252 11 is_stmt 0 view .LVU3143 + 9161 0000 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 9162 0004 DBB2 uxtb r3, r3 +4252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9163 .loc 1 4252 6 view .LVU3144 + 9164 0006 102B cmp r3, #16 + 9165 0008 36D1 bne .L579 + ARM GAS /tmp/ccEimIdZ.s page 330 + + +4251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 9166 .loc 1 4251 1 view .LVU3145 + 9167 000a 30B5 push {r4, r5, lr} + 9168 .LCFI105: + 9169 .cfi_def_cfa_offset 12 + 9170 .cfi_offset 4, -12 + 9171 .cfi_offset 5, -8 + 9172 .cfi_offset 14, -4 + 9173 000c 83B0 sub sp, sp, #12 + 9174 .LCFI106: + 9175 .cfi_def_cfa_offset 24 + 9176 000e 0446 mov r4, r0 + 9177 0010 0D46 mov r5, r1 +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9178 .loc 1 4255 5 is_stmt 1 view .LVU3146 +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9179 .loc 1 4255 5 view .LVU3147 + 9180 0012 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 9181 0016 012B cmp r3, #1 + 9182 0018 30D0 beq .L580 +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9183 .loc 1 4255 5 discriminator 2 view .LVU3148 + 9184 001a 0123 movs r3, #1 + 9185 001c 80F84030 strb r3, [r0, #64] +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9186 .loc 1 4255 5 discriminator 2 view .LVU3149 +4258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9187 .loc 1 4258 5 discriminator 2 view .LVU3150 +4258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9188 .loc 1 4258 13 is_stmt 0 discriminator 2 view .LVU3151 + 9189 0020 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9190 0024 DBB2 uxtb r3, r3 +4258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9191 .loc 1 4258 8 discriminator 2 view .LVU3152 + 9192 0026 212B cmp r3, #33 + 9193 0028 1AD0 beq .L585 +4263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9194 .loc 1 4263 10 is_stmt 1 view .LVU3153 +4263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9195 .loc 1 4263 18 is_stmt 0 view .LVU3154 + 9196 002a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9197 002e DBB2 uxtb r3, r3 +4263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9198 .loc 1 4263 13 view .LVU3155 + 9199 0030 222B cmp r3, #34 + 9200 0032 1BD0 beq .L586 + 9201 .LVL593: + 9202 .L578: +4271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9203 .loc 1 4271 5 is_stmt 1 view .LVU3156 +4274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9204 .loc 1 4274 5 view .LVU3157 +4274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9205 .loc 1 4274 17 is_stmt 0 view .LVU3158 + 9206 0034 6023 movs r3, #96 + 9207 0036 84F84130 strb r3, [r4, #65] +4278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 331 + + + 9208 .loc 1 4278 5 is_stmt 1 view .LVU3159 + 9209 003a 114B ldr r3, .L587 + 9210 003c 0093 str r3, [sp] + 9211 003e 4FF00073 mov r3, #33554432 + 9212 0042 0122 movs r2, #1 + 9213 0044 2946 mov r1, r5 + 9214 0046 2046 mov r0, r4 + 9215 0048 FFF7FEFF bl I2C_TransferConfig + 9216 .LVL594: +4281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9217 .loc 1 4281 5 view .LVU3160 +4281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9218 .loc 1 4281 5 view .LVU3161 + 9219 004c 0025 movs r5, #0 + 9220 004e 84F84050 strb r5, [r4, #64] +4281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9221 .loc 1 4281 5 view .LVU3162 +4286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9222 .loc 1 4286 5 view .LVU3163 + 9223 0052 2021 movs r1, #32 + 9224 0054 2046 mov r0, r4 + 9225 0056 FFF7FEFF bl I2C_Enable_IRQ + 9226 .LVL595: +4288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9227 .loc 1 4288 5 view .LVU3164 +4288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9228 .loc 1 4288 12 is_stmt 0 view .LVU3165 + 9229 005a 2846 mov r0, r5 + 9230 .L576: +4296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9231 .loc 1 4296 1 view .LVU3166 + 9232 005c 03B0 add sp, sp, #12 + 9233 .LCFI107: + 9234 .cfi_remember_state + 9235 .cfi_def_cfa_offset 12 + 9236 @ sp needed + 9237 005e 30BD pop {r4, r5, pc} + 9238 .LVL596: + 9239 .L585: + 9240 .LCFI108: + 9241 .cfi_restore_state +4260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9242 .loc 1 4260 7 is_stmt 1 view .LVU3167 + 9243 0060 0121 movs r1, #1 + 9244 .LVL597: +4260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9245 .loc 1 4260 7 is_stmt 0 view .LVU3168 + 9246 0062 FFF7FEFF bl I2C_Disable_IRQ + 9247 .LVL598: +4261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9248 .loc 1 4261 7 is_stmt 1 view .LVU3169 +4261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9249 .loc 1 4261 27 is_stmt 0 view .LVU3170 + 9250 0066 1123 movs r3, #17 + 9251 0068 2363 str r3, [r4, #48] + 9252 006a E3E7 b .L578 + 9253 .LVL599: + ARM GAS /tmp/ccEimIdZ.s page 332 + + + 9254 .L586: +4265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9255 .loc 1 4265 7 is_stmt 1 view .LVU3171 + 9256 006c 0221 movs r1, #2 + 9257 .LVL600: +4265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9258 .loc 1 4265 7 is_stmt 0 view .LVU3172 + 9259 006e FFF7FEFF bl I2C_Disable_IRQ + 9260 .LVL601: +4266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9261 .loc 1 4266 7 is_stmt 1 view .LVU3173 +4266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9262 .loc 1 4266 27 is_stmt 0 view .LVU3174 + 9263 0072 1223 movs r3, #18 + 9264 0074 2363 str r3, [r4, #48] + 9265 0076 DDE7 b .L578 + 9266 .LVL602: + 9267 .L579: + 9268 .LCFI109: + 9269 .cfi_def_cfa_offset 0 + 9270 .cfi_restore 4 + 9271 .cfi_restore 5 + 9272 .cfi_restore 14 +4294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9273 .loc 1 4294 12 view .LVU3175 + 9274 0078 0120 movs r0, #1 + 9275 .LVL603: +4296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9276 .loc 1 4296 1 view .LVU3176 + 9277 007a 7047 bx lr + 9278 .LVL604: + 9279 .L580: + 9280 .LCFI110: + 9281 .cfi_def_cfa_offset 24 + 9282 .cfi_offset 4, -12 + 9283 .cfi_offset 5, -8 + 9284 .cfi_offset 14, -4 +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9285 .loc 1 4255 5 view .LVU3177 + 9286 007c 0220 movs r0, #2 + 9287 .LVL605: +4255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9288 .loc 1 4255 5 view .LVU3178 + 9289 007e EDE7 b .L576 + 9290 .L588: + 9291 .align 2 + 9292 .L587: + 9293 0080 00400080 .word -2147467264 + 9294 .cfi_endproc + 9295 .LFE174: + 9297 .section .text.HAL_I2C_EV_IRQHandler,"ax",%progbits + 9298 .align 1 + 9299 .global HAL_I2C_EV_IRQHandler + 9300 .syntax unified + 9301 .thumb + 9302 .thumb_func + 9303 .fpu fpv5-d16 + ARM GAS /tmp/ccEimIdZ.s page 333 + + + 9305 HAL_I2C_EV_IRQHandler: + 9306 .LVL606: + 9307 .LFB175: +4313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 9308 .loc 1 4313 1 is_stmt 1 view -0 + 9309 .cfi_startproc + 9310 @ args = 0, pretend = 0, frame = 0 + 9311 @ frame_needed = 0, uses_anonymous_args = 0 +4313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 9312 .loc 1 4313 1 is_stmt 0 view .LVU3180 + 9313 0000 08B5 push {r3, lr} + 9314 .LCFI111: + 9315 .cfi_def_cfa_offset 8 + 9316 .cfi_offset 3, -8 + 9317 .cfi_offset 14, -4 +4315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 9318 .loc 1 4315 3 is_stmt 1 view .LVU3181 +4315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 9319 .loc 1 4315 24 is_stmt 0 view .LVU3182 + 9320 0002 0368 ldr r3, [r0] +4315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 9321 .loc 1 4315 12 view .LVU3183 + 9322 0004 9969 ldr r1, [r3, #24] + 9323 .LVL607: +4316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9324 .loc 1 4316 3 is_stmt 1 view .LVU3184 +4316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9325 .loc 1 4316 12 is_stmt 0 view .LVU3185 + 9326 0006 1A68 ldr r2, [r3] + 9327 .LVL608: +4319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9328 .loc 1 4319 3 is_stmt 1 view .LVU3186 +4319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9329 .loc 1 4319 11 is_stmt 0 view .LVU3187 + 9330 0008 436B ldr r3, [r0, #52] +4319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9331 .loc 1 4319 6 view .LVU3188 + 9332 000a 03B1 cbz r3, .L589 +4321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9333 .loc 1 4321 5 is_stmt 1 view .LVU3189 + 9334 000c 9847 blx r3 + 9335 .LVL609: + 9336 .L589: +4323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9337 .loc 1 4323 1 is_stmt 0 view .LVU3190 + 9338 000e 08BD pop {r3, pc} + 9339 .cfi_endproc + 9340 .LFE175: + 9342 .section .text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits + 9343 .align 1 + 9344 .weak HAL_I2C_MasterTxCpltCallback + 9345 .syntax unified + 9346 .thumb + 9347 .thumb_func + 9348 .fpu fpv5-d16 + 9350 HAL_I2C_MasterTxCpltCallback: + 9351 .LVL610: + ARM GAS /tmp/ccEimIdZ.s page 334 + + + 9352 .LFB177: +4381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9353 .loc 1 4381 1 is_stmt 1 view -0 + 9354 .cfi_startproc + 9355 @ args = 0, pretend = 0, frame = 0 + 9356 @ frame_needed = 0, uses_anonymous_args = 0 + 9357 @ link register save eliminated. +4383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9358 .loc 1 4383 3 view .LVU3192 +4388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9359 .loc 1 4388 1 is_stmt 0 view .LVU3193 + 9360 0000 7047 bx lr + 9361 .cfi_endproc + 9362 .LFE177: + 9364 .section .text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits + 9365 .align 1 + 9366 .weak HAL_I2C_MasterRxCpltCallback + 9367 .syntax unified + 9368 .thumb + 9369 .thumb_func + 9370 .fpu fpv5-d16 + 9372 HAL_I2C_MasterRxCpltCallback: + 9373 .LVL611: + 9374 .LFB178: +4397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9375 .loc 1 4397 1 is_stmt 1 view -0 + 9376 .cfi_startproc + 9377 @ args = 0, pretend = 0, frame = 0 + 9378 @ frame_needed = 0, uses_anonymous_args = 0 + 9379 @ link register save eliminated. +4399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9380 .loc 1 4399 3 view .LVU3195 +4404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9381 .loc 1 4404 1 is_stmt 0 view .LVU3196 + 9382 0000 7047 bx lr + 9383 .cfi_endproc + 9384 .LFE178: + 9386 .section .text.I2C_ITMasterSeqCplt,"ax",%progbits + 9387 .align 1 + 9388 .syntax unified + 9389 .thumb + 9390 .thumb_func + 9391 .fpu fpv5-d16 + 9393 I2C_ITMasterSeqCplt: + 9394 .LVL612: + 9395 .LFB197: +5350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset I2C handle mode */ + 9396 .loc 1 5350 1 is_stmt 1 view -0 + 9397 .cfi_startproc + 9398 @ args = 0, pretend = 0, frame = 0 + 9399 @ frame_needed = 0, uses_anonymous_args = 0 +5350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset I2C handle mode */ + 9400 .loc 1 5350 1 is_stmt 0 view .LVU3198 + 9401 0000 38B5 push {r3, r4, r5, lr} + 9402 .LCFI112: + 9403 .cfi_def_cfa_offset 16 + 9404 .cfi_offset 3, -16 + ARM GAS /tmp/ccEimIdZ.s page 335 + + + 9405 .cfi_offset 4, -12 + 9406 .cfi_offset 5, -8 + 9407 .cfi_offset 14, -4 + 9408 0002 0446 mov r4, r0 +5352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9409 .loc 1 5352 3 is_stmt 1 view .LVU3199 +5352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9410 .loc 1 5352 14 is_stmt 0 view .LVU3200 + 9411 0004 0023 movs r3, #0 + 9412 0006 80F84230 strb r3, [r0, #66] +5356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9413 .loc 1 5356 3 is_stmt 1 view .LVU3201 +5356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9414 .loc 1 5356 11 is_stmt 0 view .LVU3202 + 9415 000a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9416 000e DBB2 uxtb r3, r3 +5356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9417 .loc 1 5356 6 view .LVU3203 + 9418 0010 212B cmp r3, #33 + 9419 0012 0FD0 beq .L598 +5378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9420 .loc 1 5378 5 is_stmt 1 view .LVU3204 +5378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9421 .loc 1 5378 25 is_stmt 0 view .LVU3205 + 9422 0014 2023 movs r3, #32 + 9423 0016 80F84130 strb r3, [r0, #65] +5379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9424 .loc 1 5379 5 is_stmt 1 view .LVU3206 +5379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9425 .loc 1 5379 25 is_stmt 0 view .LVU3207 + 9426 001a 1223 movs r3, #18 + 9427 001c 0363 str r3, [r0, #48] +5380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9428 .loc 1 5380 5 is_stmt 1 view .LVU3208 +5380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9429 .loc 1 5380 25 is_stmt 0 view .LVU3209 + 9430 001e 0025 movs r5, #0 + 9431 0020 4563 str r5, [r0, #52] +5383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9432 .loc 1 5383 5 is_stmt 1 view .LVU3210 + 9433 0022 0221 movs r1, #2 + 9434 0024 FFF7FEFF bl I2C_Disable_IRQ + 9435 .LVL613: +5386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9436 .loc 1 5386 5 view .LVU3211 +5386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9437 .loc 1 5386 5 view .LVU3212 + 9438 0028 84F84050 strb r5, [r4, #64] +5386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9439 .loc 1 5386 5 view .LVU3213 +5392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9440 .loc 1 5392 5 view .LVU3214 + 9441 002c 2046 mov r0, r4 + 9442 002e FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 9443 .LVL614: + 9444 .L594: +5395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 336 + + + 9445 .loc 1 5395 1 is_stmt 0 view .LVU3215 + 9446 0032 38BD pop {r3, r4, r5, pc} + 9447 .LVL615: + 9448 .L598: +5358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9449 .loc 1 5358 5 is_stmt 1 view .LVU3216 +5358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9450 .loc 1 5358 25 is_stmt 0 view .LVU3217 + 9451 0034 2023 movs r3, #32 + 9452 0036 80F84130 strb r3, [r0, #65] +5359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9453 .loc 1 5359 5 is_stmt 1 view .LVU3218 +5359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9454 .loc 1 5359 25 is_stmt 0 view .LVU3219 + 9455 003a 1123 movs r3, #17 + 9456 003c 0363 str r3, [r0, #48] +5360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9457 .loc 1 5360 5 is_stmt 1 view .LVU3220 +5360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9458 .loc 1 5360 25 is_stmt 0 view .LVU3221 + 9459 003e 0025 movs r5, #0 + 9460 0040 4563 str r5, [r0, #52] +5363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9461 .loc 1 5363 5 is_stmt 1 view .LVU3222 + 9462 0042 0121 movs r1, #1 + 9463 0044 FFF7FEFF bl I2C_Disable_IRQ + 9464 .LVL616: +5366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9465 .loc 1 5366 5 view .LVU3223 +5366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9466 .loc 1 5366 5 view .LVU3224 + 9467 0048 84F84050 strb r5, [r4, #64] +5366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9468 .loc 1 5366 5 view .LVU3225 +5372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9469 .loc 1 5372 5 view .LVU3226 + 9470 004c 2046 mov r0, r4 + 9471 004e FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 9472 .LVL617: + 9473 0052 EEE7 b .L594 + 9474 .cfi_endproc + 9475 .LFE197: + 9477 .section .text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits + 9478 .align 1 + 9479 .weak HAL_I2C_SlaveTxCpltCallback + 9480 .syntax unified + 9481 .thumb + 9482 .thumb_func + 9483 .fpu fpv5-d16 + 9485 HAL_I2C_SlaveTxCpltCallback: + 9486 .LVL618: + 9487 .LFB179: +4412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9488 .loc 1 4412 1 view -0 + 9489 .cfi_startproc + 9490 @ args = 0, pretend = 0, frame = 0 + 9491 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccEimIdZ.s page 337 + + + 9492 @ link register save eliminated. +4414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9493 .loc 1 4414 3 view .LVU3228 +4419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9494 .loc 1 4419 1 is_stmt 0 view .LVU3229 + 9495 0000 7047 bx lr + 9496 .cfi_endproc + 9497 .LFE179: + 9499 .section .text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits + 9500 .align 1 + 9501 .weak HAL_I2C_SlaveRxCpltCallback + 9502 .syntax unified + 9503 .thumb + 9504 .thumb_func + 9505 .fpu fpv5-d16 + 9507 HAL_I2C_SlaveRxCpltCallback: + 9508 .LVL619: + 9509 .LFB180: +4428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9510 .loc 1 4428 1 is_stmt 1 view -0 + 9511 .cfi_startproc + 9512 @ args = 0, pretend = 0, frame = 0 + 9513 @ frame_needed = 0, uses_anonymous_args = 0 + 9514 @ link register save eliminated. +4430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9515 .loc 1 4430 3 view .LVU3231 +4435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9516 .loc 1 4435 1 is_stmt 0 view .LVU3232 + 9517 0000 7047 bx lr + 9518 .cfi_endproc + 9519 .LFE180: + 9521 .section .text.I2C_ITSlaveSeqCplt,"ax",%progbits + 9522 .align 1 + 9523 .syntax unified + 9524 .thumb + 9525 .thumb_func + 9526 .fpu fpv5-d16 + 9528 I2C_ITSlaveSeqCplt: + 9529 .LVL620: + 9530 .LFB198: +5403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 9531 .loc 1 5403 1 is_stmt 1 view -0 + 9532 .cfi_startproc + 9533 @ args = 0, pretend = 0, frame = 0 + 9534 @ frame_needed = 0, uses_anonymous_args = 0 +5403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 9535 .loc 1 5403 1 is_stmt 0 view .LVU3234 + 9536 0000 10B5 push {r4, lr} + 9537 .LCFI113: + 9538 .cfi_def_cfa_offset 8 + 9539 .cfi_offset 4, -8 + 9540 .cfi_offset 14, -4 + 9541 0002 0446 mov r4, r0 +5404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9542 .loc 1 5404 3 is_stmt 1 view .LVU3235 +5404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9543 .loc 1 5404 26 is_stmt 0 view .LVU3236 + ARM GAS /tmp/ccEimIdZ.s page 338 + + + 9544 0004 0368 ldr r3, [r0] +5404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9545 .loc 1 5404 12 view .LVU3237 + 9546 0006 1A68 ldr r2, [r3] + 9547 .LVL621: +5407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9548 .loc 1 5407 3 is_stmt 1 view .LVU3238 +5407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9549 .loc 1 5407 14 is_stmt 0 view .LVU3239 + 9550 0008 0021 movs r1, #0 + 9551 000a 80F84210 strb r1, [r0, #66] +5410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9552 .loc 1 5410 3 is_stmt 1 view .LVU3240 +5410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9553 .loc 1 5410 6 is_stmt 0 view .LVU3241 + 9554 000e 12F4804F tst r2, #16384 + 9555 0012 0ED0 beq .L602 +5413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9556 .loc 1 5413 5 is_stmt 1 view .LVU3242 +5413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9557 .loc 1 5413 25 is_stmt 0 view .LVU3243 + 9558 0014 1A68 ldr r2, [r3] + 9559 .LVL622: +5413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9560 .loc 1 5413 25 view .LVU3244 + 9561 0016 22F48042 bic r2, r2, #16384 + 9562 001a 1A60 str r2, [r3] + 9563 .L603: +5423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9564 .loc 1 5423 3 is_stmt 1 view .LVU3245 +5425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9565 .loc 1 5425 3 view .LVU3246 +5425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9566 .loc 1 5425 11 is_stmt 0 view .LVU3247 + 9567 001c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9568 0020 DBB2 uxtb r3, r3 +5425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9569 .loc 1 5425 6 view .LVU3248 + 9570 0022 292B cmp r3, #41 + 9571 0024 0DD0 beq .L607 +5445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9572 .loc 1 5445 8 is_stmt 1 view .LVU3249 +5445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9573 .loc 1 5445 16 is_stmt 0 view .LVU3250 + 9574 0026 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9575 002a DBB2 uxtb r3, r3 +5445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9576 .loc 1 5445 11 view .LVU3251 + 9577 002c 2A2B cmp r3, #42 + 9578 002e 18D0 beq .L608 + 9579 .LVL623: + 9580 .L601: +5468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9581 .loc 1 5468 1 view .LVU3252 + 9582 0030 10BD pop {r4, pc} + 9583 .LVL624: + 9584 .L602: + ARM GAS /tmp/ccEimIdZ.s page 339 + + +5415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9585 .loc 1 5415 8 is_stmt 1 view .LVU3253 +5415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9586 .loc 1 5415 11 is_stmt 0 view .LVU3254 + 9587 0032 12F4004F tst r2, #32768 + 9588 0036 F1D0 beq .L603 +5418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9589 .loc 1 5418 5 is_stmt 1 view .LVU3255 +5418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9590 .loc 1 5418 25 is_stmt 0 view .LVU3256 + 9591 0038 1A68 ldr r2, [r3] + 9592 .LVL625: +5418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9593 .loc 1 5418 25 view .LVU3257 + 9594 003a 22F40042 bic r2, r2, #32768 + 9595 003e 1A60 str r2, [r3] + 9596 0040 ECE7 b .L603 + 9597 .L607: +5428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 9598 .loc 1 5428 5 is_stmt 1 view .LVU3258 +5428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 9599 .loc 1 5428 25 is_stmt 0 view .LVU3259 + 9600 0042 2823 movs r3, #40 + 9601 0044 84F84130 strb r3, [r4, #65] +5429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9602 .loc 1 5429 5 is_stmt 1 view .LVU3260 +5429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9603 .loc 1 5429 25 is_stmt 0 view .LVU3261 + 9604 0048 2123 movs r3, #33 + 9605 004a 2363 str r3, [r4, #48] +5432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9606 .loc 1 5432 5 is_stmt 1 view .LVU3262 + 9607 004c 0121 movs r1, #1 + 9608 004e 2046 mov r0, r4 + 9609 .LVL626: +5432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9610 .loc 1 5432 5 is_stmt 0 view .LVU3263 + 9611 0050 FFF7FEFF bl I2C_Disable_IRQ + 9612 .LVL627: +5435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9613 .loc 1 5435 5 is_stmt 1 view .LVU3264 +5435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9614 .loc 1 5435 5 view .LVU3265 + 9615 0054 0023 movs r3, #0 + 9616 0056 84F84030 strb r3, [r4, #64] +5435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9617 .loc 1 5435 5 view .LVU3266 +5441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9618 .loc 1 5441 5 view .LVU3267 + 9619 005a 2046 mov r0, r4 + 9620 005c FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 9621 .LVL628: + 9622 0060 E6E7 b .L601 + 9623 .LVL629: + 9624 .L608: +5448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 9625 .loc 1 5448 5 view .LVU3268 + ARM GAS /tmp/ccEimIdZ.s page 340 + + +5448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 9626 .loc 1 5448 25 is_stmt 0 view .LVU3269 + 9627 0062 2823 movs r3, #40 + 9628 0064 84F84130 strb r3, [r4, #65] +5449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9629 .loc 1 5449 5 is_stmt 1 view .LVU3270 +5449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9630 .loc 1 5449 25 is_stmt 0 view .LVU3271 + 9631 0068 2223 movs r3, #34 + 9632 006a 2363 str r3, [r4, #48] +5452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9633 .loc 1 5452 5 is_stmt 1 view .LVU3272 + 9634 006c 0221 movs r1, #2 + 9635 006e 2046 mov r0, r4 + 9636 .LVL630: +5452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9637 .loc 1 5452 5 is_stmt 0 view .LVU3273 + 9638 0070 FFF7FEFF bl I2C_Disable_IRQ + 9639 .LVL631: +5455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9640 .loc 1 5455 5 is_stmt 1 view .LVU3274 +5455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9641 .loc 1 5455 5 view .LVU3275 + 9642 0074 0023 movs r3, #0 + 9643 0076 84F84030 strb r3, [r4, #64] +5455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9644 .loc 1 5455 5 view .LVU3276 +5461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9645 .loc 1 5461 5 view .LVU3277 + 9646 007a 2046 mov r0, r4 + 9647 007c FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 9648 .LVL632: +5467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9649 .loc 1 5467 3 view .LVU3278 +5468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9650 .loc 1 5468 1 is_stmt 0 view .LVU3279 + 9651 0080 D6E7 b .L601 + 9652 .cfi_endproc + 9653 .LFE198: + 9655 .section .text.I2C_DMASlaveTransmitCplt,"ax",%progbits + 9656 .align 1 + 9657 .syntax unified + 9658 .thumb + 9659 .thumb_func + 9660 .fpu fpv5-d16 + 9662 I2C_DMASlaveTransmitCplt: + 9663 .LVL633: + 9664 .LFB206: +6047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 9665 .loc 1 6047 1 is_stmt 1 view -0 + 9666 .cfi_startproc + 9667 @ args = 0, pretend = 0, frame = 0 + 9668 @ frame_needed = 0, uses_anonymous_args = 0 +6047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 9669 .loc 1 6047 1 is_stmt 0 view .LVU3281 + 9670 0000 08B5 push {r3, lr} + 9671 .LCFI114: + ARM GAS /tmp/ccEimIdZ.s page 341 + + + 9672 .cfi_def_cfa_offset 8 + 9673 .cfi_offset 3, -8 + 9674 .cfi_offset 14, -4 +6048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9675 .loc 1 6048 3 is_stmt 1 view .LVU3282 +6048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9676 .loc 1 6048 22 is_stmt 0 view .LVU3283 + 9677 0002 806B ldr r0, [r0, #56] + 9678 .LVL634: +6049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9679 .loc 1 6049 3 is_stmt 1 view .LVU3284 +6049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9680 .loc 1 6049 12 is_stmt 0 view .LVU3285 + 9681 0004 C36A ldr r3, [r0, #44] + 9682 .LVL635: +6051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9683 .loc 1 6051 3 is_stmt 1 view .LVU3286 +6051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9684 .loc 1 6051 6 is_stmt 0 view .LVU3287 + 9685 0006 002B cmp r3, #0 + 9686 0008 18BF it ne + 9687 000a B3F1807F cmpne r3, #16777216 + 9688 000e 00D0 beq .L612 + 9689 .LVL636: + 9690 .L609: +6066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9691 .loc 1 6066 1 view .LVU3288 + 9692 0010 08BD pop {r3, pc} + 9693 .LVL637: + 9694 .L612: +6054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9695 .loc 1 6054 5 is_stmt 1 view .LVU3289 +6054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9696 .loc 1 6054 9 is_stmt 0 view .LVU3290 + 9697 0012 0268 ldr r2, [r0] +6054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9698 .loc 1 6054 25 view .LVU3291 + 9699 0014 1368 ldr r3, [r2] + 9700 .LVL638: +6054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9701 .loc 1 6054 25 view .LVU3292 + 9702 0016 23F48043 bic r3, r3, #16384 + 9703 001a 1360 str r3, [r2] +6058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9704 .loc 1 6058 5 is_stmt 1 view .LVU3293 + 9705 001c FFF7FEFF bl I2C_ITSlaveSeqCplt + 9706 .LVL639: +6065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9707 .loc 1 6065 3 view .LVU3294 +6066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9708 .loc 1 6066 1 is_stmt 0 view .LVU3295 + 9709 0020 F6E7 b .L609 + 9710 .cfi_endproc + 9711 .LFE206: + 9713 .section .text.I2C_DMASlaveReceiveCplt,"ax",%progbits + 9714 .align 1 + 9715 .syntax unified + ARM GAS /tmp/ccEimIdZ.s page 342 + + + 9716 .thumb + 9717 .thumb_func + 9718 .fpu fpv5-d16 + 9720 I2C_DMASlaveReceiveCplt: + 9721 .LVL640: + 9722 .LFB208: +6122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 9723 .loc 1 6122 1 is_stmt 1 view -0 + 9724 .cfi_startproc + 9725 @ args = 0, pretend = 0, frame = 0 + 9726 @ frame_needed = 0, uses_anonymous_args = 0 +6122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 9727 .loc 1 6122 1 is_stmt 0 view .LVU3297 + 9728 0000 10B5 push {r4, lr} + 9729 .LCFI115: + 9730 .cfi_def_cfa_offset 8 + 9731 .cfi_offset 4, -8 + 9732 .cfi_offset 14, -4 +6123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9733 .loc 1 6123 3 is_stmt 1 view .LVU3298 +6123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9734 .loc 1 6123 22 is_stmt 0 view .LVU3299 + 9735 0002 806B ldr r0, [r0, #56] + 9736 .LVL641: +6124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9737 .loc 1 6124 3 is_stmt 1 view .LVU3300 +6124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9738 .loc 1 6124 12 is_stmt 0 view .LVU3301 + 9739 0004 C46A ldr r4, [r0, #44] + 9740 .LVL642: +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9741 .loc 1 6126 3 is_stmt 1 view .LVU3302 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9742 .loc 1 6126 8 is_stmt 0 view .LVU3303 + 9743 0006 C36B ldr r3, [r0, #60] + 9744 0008 1B68 ldr r3, [r3] +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9745 .loc 1 6126 44 view .LVU3304 + 9746 000a 2349 ldr r1, .L620 + 9747 000c 234A ldr r2, .L620+4 + 9748 000e 9342 cmp r3, r2 + 9749 0010 18BF it ne + 9750 0012 8B42 cmpne r3, r1 + 9751 0014 2FD0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9752 .loc 1 6126 8 discriminator 2 view .LVU3305 + 9753 0016 1832 adds r2, r2, #24 + 9754 0018 9342 cmp r3, r2 + 9755 001a 2CD0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9756 .loc 1 6126 8 discriminator 4 view .LVU3306 + 9757 001c 1832 adds r2, r2, #24 + 9758 001e 9342 cmp r3, r2 + 9759 0020 29D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9760 .loc 1 6126 8 discriminator 6 view .LVU3307 + 9761 0022 1832 adds r2, r2, #24 + ARM GAS /tmp/ccEimIdZ.s page 343 + + + 9762 0024 9342 cmp r3, r2 + 9763 0026 26D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9764 .loc 1 6126 8 discriminator 8 view .LVU3308 + 9765 0028 1832 adds r2, r2, #24 + 9766 002a 9342 cmp r3, r2 + 9767 002c 23D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9768 .loc 1 6126 8 discriminator 10 view .LVU3309 + 9769 002e 1832 adds r2, r2, #24 + 9770 0030 9342 cmp r3, r2 + 9771 0032 20D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9772 .loc 1 6126 8 discriminator 12 view .LVU3310 + 9773 0034 1832 adds r2, r2, #24 + 9774 0036 9342 cmp r3, r2 + 9775 0038 1DD0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9776 .loc 1 6126 8 discriminator 14 view .LVU3311 + 9777 003a 02F55672 add r2, r2, #856 + 9778 003e 9342 cmp r3, r2 + 9779 0040 19D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9780 .loc 1 6126 8 discriminator 16 view .LVU3312 + 9781 0042 1832 adds r2, r2, #24 + 9782 0044 9342 cmp r3, r2 + 9783 0046 16D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9784 .loc 1 6126 8 discriminator 18 view .LVU3313 + 9785 0048 1832 adds r2, r2, #24 + 9786 004a 9342 cmp r3, r2 + 9787 004c 13D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9788 .loc 1 6126 8 discriminator 20 view .LVU3314 + 9789 004e 1832 adds r2, r2, #24 + 9790 0050 9342 cmp r3, r2 + 9791 0052 10D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9792 .loc 1 6126 8 discriminator 22 view .LVU3315 + 9793 0054 1832 adds r2, r2, #24 + 9794 0056 9342 cmp r3, r2 + 9795 0058 0DD0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9796 .loc 1 6126 8 discriminator 24 view .LVU3316 + 9797 005a 1832 adds r2, r2, #24 + 9798 005c 9342 cmp r3, r2 + 9799 005e 0AD0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9800 .loc 1 6126 8 discriminator 26 view .LVU3317 + 9801 0060 1832 adds r2, r2, #24 + 9802 0062 9342 cmp r3, r2 + 9803 0064 07D0 beq .L614 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9804 .loc 1 6126 8 discriminator 28 view .LVU3318 + 9805 0066 1832 adds r2, r2, #24 + 9806 0068 9342 cmp r3, r2 + 9807 006a 04D0 beq .L614 + ARM GAS /tmp/ccEimIdZ.s page 344 + + +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9808 .loc 1 6126 8 discriminator 30 view .LVU3319 + 9809 006c 5B68 ldr r3, [r3, #4] +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9810 .loc 1 6126 44 discriminator 30 view .LVU3320 + 9811 006e B3FA83F3 clz r3, r3 + 9812 0072 5B09 lsrs r3, r3, #5 + 9813 0074 03E0 b .L616 + 9814 .L614: +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9815 .loc 1 6126 8 discriminator 29 view .LVU3321 + 9816 0076 5B68 ldr r3, [r3, #4] +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9817 .loc 1 6126 44 discriminator 29 view .LVU3322 + 9818 0078 B3FA83F3 clz r3, r3 + 9819 007c 5B09 lsrs r3, r3, #5 + 9820 .L616: +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9821 .loc 1 6126 6 discriminator 32 view .LVU3323 + 9822 007e 13B1 cbz r3, .L613 +6126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9823 .loc 1 6126 51 discriminator 33 view .LVU3324 + 9824 0080 14F5803F cmn r4, #65536 + 9825 0084 00D1 bne .L619 + 9826 .LVL643: + 9827 .L613: +6141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9828 .loc 1 6141 1 view .LVU3325 + 9829 0086 10BD pop {r4, pc} + 9830 .LVL644: + 9831 .L619: +6130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9832 .loc 1 6130 5 is_stmt 1 view .LVU3326 +6130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9833 .loc 1 6130 9 is_stmt 0 view .LVU3327 + 9834 0088 0268 ldr r2, [r0] +6130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9835 .loc 1 6130 25 view .LVU3328 + 9836 008a 1368 ldr r3, [r2] + 9837 008c 23F40043 bic r3, r3, #32768 + 9838 0090 1360 str r3, [r2] +6133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9839 .loc 1 6133 5 is_stmt 1 view .LVU3329 + 9840 0092 FFF7FEFF bl I2C_ITSlaveSeqCplt + 9841 .LVL645: +6140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9842 .loc 1 6140 3 view .LVU3330 +6141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9843 .loc 1 6141 1 is_stmt 0 view .LVU3331 + 9844 0096 F6E7 b .L613 + 9845 .L621: + 9846 .align 2 + 9847 .L620: + 9848 0098 10000240 .word 1073872912 + 9849 009c 28000240 .word 1073872936 + 9850 .cfi_endproc + 9851 .LFE208: + ARM GAS /tmp/ccEimIdZ.s page 345 + + + 9853 .section .text.HAL_I2C_AddrCallback,"ax",%progbits + 9854 .align 1 + 9855 .weak HAL_I2C_AddrCallback + 9856 .syntax unified + 9857 .thumb + 9858 .thumb_func + 9859 .fpu fpv5-d16 + 9861 HAL_I2C_AddrCallback: + 9862 .LVL646: + 9863 .LFB181: +4446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9864 .loc 1 4446 1 is_stmt 1 view -0 + 9865 .cfi_startproc + 9866 @ args = 0, pretend = 0, frame = 0 + 9867 @ frame_needed = 0, uses_anonymous_args = 0 + 9868 @ link register save eliminated. +4448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(TransferDirection); + 9869 .loc 1 4448 3 view .LVU3333 +4449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(AddrMatchCode); + 9870 .loc 1 4449 3 view .LVU3334 +4450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9871 .loc 1 4450 3 view .LVU3335 +4455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9872 .loc 1 4455 1 is_stmt 0 view .LVU3336 + 9873 0000 7047 bx lr + 9874 .cfi_endproc + 9875 .LFE181: + 9877 .section .text.I2C_ITAddrCplt,"ax",%progbits + 9878 .align 1 + 9879 .syntax unified + 9880 .thumb + 9881 .thumb_func + 9882 .fpu fpv5-d16 + 9884 I2C_ITAddrCplt: + 9885 .LVL647: + 9886 .LFB196: +5255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint8_t transferdirection; + 9887 .loc 1 5255 1 is_stmt 1 view -0 + 9888 .cfi_startproc + 9889 @ args = 0, pretend = 0, frame = 0 + 9890 @ frame_needed = 0, uses_anonymous_args = 0 +5255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint8_t transferdirection; + 9891 .loc 1 5255 1 is_stmt 0 view .LVU3338 + 9892 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 9893 .LCFI116: + 9894 .cfi_def_cfa_offset 24 + 9895 .cfi_offset 3, -24 + 9896 .cfi_offset 4, -20 + 9897 .cfi_offset 5, -16 + 9898 .cfi_offset 6, -12 + 9899 .cfi_offset 7, -8 + 9900 .cfi_offset 14, -4 + 9901 0002 0446 mov r4, r0 +5256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t slaveaddrcode; + 9902 .loc 1 5256 3 is_stmt 1 view .LVU3339 +5257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t ownadd1code; + 9903 .loc 1 5257 3 view .LVU3340 + ARM GAS /tmp/ccEimIdZ.s page 346 + + +5258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t ownadd2code; + 9904 .loc 1 5258 3 view .LVU3341 +5259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9905 .loc 1 5259 3 view .LVU3342 +5262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9906 .loc 1 5262 3 view .LVU3343 +5265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9907 .loc 1 5265 3 view .LVU3344 +5265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9908 .loc 1 5265 22 is_stmt 0 view .LVU3345 + 9909 0004 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 +5265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9910 .loc 1 5265 6 view .LVU3346 + 9911 0008 03F02803 and r3, r3, #40 + 9912 000c 282B cmp r3, #40 + 9913 000e 06D0 beq .L629 +5337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9914 .loc 1 5337 5 is_stmt 1 view .LVU3347 + 9915 0010 0368 ldr r3, [r0] + 9916 0012 0822 movs r2, #8 + 9917 0014 DA61 str r2, [r3, #28] +5340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9918 .loc 1 5340 5 view .LVU3348 +5340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9919 .loc 1 5340 5 view .LVU3349 + 9920 0016 0023 movs r3, #0 + 9921 0018 80F84030 strb r3, [r0, #64] +5340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 9922 .loc 1 5340 5 view .LVU3350 + 9923 .LVL648: + 9924 .L623: +5342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9925 .loc 1 5342 1 is_stmt 0 view .LVU3351 + 9926 001c F8BD pop {r3, r4, r5, r6, r7, pc} + 9927 .LVL649: + 9928 .L629: +5267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9929 .loc 1 5267 5 is_stmt 1 view .LVU3352 +5267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9930 .loc 1 5267 25 is_stmt 0 view .LVU3353 + 9931 001e 0368 ldr r3, [r0] + 9932 0020 9E69 ldr r6, [r3, #24] +5267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9933 .loc 1 5267 23 view .LVU3354 + 9934 0022 C6F30046 ubfx r6, r6, #16, #1 + 9935 .LVL650: +5268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9936 .loc 1 5268 5 is_stmt 1 view .LVU3355 +5268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9937 .loc 1 5268 25 is_stmt 0 view .LVU3356 + 9938 0026 9A69 ldr r2, [r3, #24] + 9939 0028 120C lsrs r2, r2, #16 +5268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9940 .loc 1 5268 23 view .LVU3357 + 9941 002a 02F0FE05 and r5, r2, #254 + 9942 .LVL651: +5269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + ARM GAS /tmp/ccEimIdZ.s page 347 + + + 9943 .loc 1 5269 5 is_stmt 1 view .LVU3358 +5269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 9944 .loc 1 5269 25 is_stmt 0 view .LVU3359 + 9945 002e 9A68 ldr r2, [r3, #8] +5269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 9946 .loc 1 5269 23 view .LVU3360 + 9947 0030 C2F30902 ubfx r2, r2, #0, #10 + 9948 .LVL652: +5270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9949 .loc 1 5270 5 is_stmt 1 view .LVU3361 +5270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9950 .loc 1 5270 25 is_stmt 0 view .LVU3362 + 9951 0034 DF68 ldr r7, [r3, #12] +5270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9952 .loc 1 5270 23 view .LVU3363 + 9953 0036 07F0FE07 and r7, r7, #254 + 9954 .LVL653: +5273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9955 .loc 1 5273 5 is_stmt 1 view .LVU3364 +5273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9956 .loc 1 5273 19 is_stmt 0 view .LVU3365 + 9957 003a C168 ldr r1, [r0, #12] + 9958 .LVL654: +5273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9959 .loc 1 5273 8 view .LVU3366 + 9960 003c 0229 cmp r1, #2 + 9961 003e 22D1 bne .L625 +5275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9962 .loc 1 5275 7 is_stmt 1 view .LVU3367 +5275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9963 .loc 1 5275 43 is_stmt 0 view .LVU3368 + 9964 0040 85EAD215 eor r5, r5, r2, lsr #7 + 9965 .LVL655: +5275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9966 .loc 1 5275 10 view .LVU3369 + 9967 0044 15F0060F tst r5, #6 + 9968 0048 10D1 bne .L626 +5277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->AddrEventCount++; + 9969 .loc 1 5277 9 is_stmt 1 view .LVU3370 + 9970 .LVL656: +5278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9971 .loc 1 5278 9 view .LVU3371 +5278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9972 .loc 1 5278 13 is_stmt 0 view .LVU3372 + 9973 004a 816C ldr r1, [r0, #72] +5278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9974 .loc 1 5278 29 view .LVU3373 + 9975 004c 0131 adds r1, r1, #1 + 9976 004e 8164 str r1, [r0, #72] +5279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9977 .loc 1 5279 9 is_stmt 1 view .LVU3374 +5279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9978 .loc 1 5279 17 is_stmt 0 view .LVU3375 + 9979 0050 816C ldr r1, [r0, #72] +5279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 9980 .loc 1 5279 12 view .LVU3376 + 9981 0052 0229 cmp r1, #2 + ARM GAS /tmp/ccEimIdZ.s page 348 + + + 9982 0054 E2D1 bne .L623 +5282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9983 .loc 1 5282 11 is_stmt 1 view .LVU3377 +5282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9984 .loc 1 5282 32 is_stmt 0 view .LVU3378 + 9985 0056 0021 movs r1, #0 + 9986 0058 8164 str r1, [r0, #72] +5285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9987 .loc 1 5285 11 is_stmt 1 view .LVU3379 + 9988 005a 0820 movs r0, #8 + 9989 .LVL657: +5285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9990 .loc 1 5285 11 is_stmt 0 view .LVU3380 + 9991 005c D861 str r0, [r3, #28] +5288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9992 .loc 1 5288 11 is_stmt 1 view .LVU3381 +5288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9993 .loc 1 5288 11 view .LVU3382 + 9994 005e 84F84010 strb r1, [r4, #64] +5288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 9995 .loc 1 5288 11 view .LVU3383 +5294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9996 .loc 1 5294 11 view .LVU3384 + 9997 0062 3146 mov r1, r6 + 9998 0064 2046 mov r0, r4 + 9999 0066 FFF7FEFF bl HAL_I2C_AddrCallback + 10000 .LVL658: +5294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10001 .loc 1 5294 11 is_stmt 0 view .LVU3385 + 10002 006a D7E7 b .L623 + 10003 .LVL659: + 10004 .L626: +5300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10005 .loc 1 5300 9 is_stmt 1 view .LVU3386 +5303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10006 .loc 1 5303 9 view .LVU3387 + 10007 006c 4FF40041 mov r1, #32768 + 10008 0070 FFF7FEFF bl I2C_Disable_IRQ + 10009 .LVL660: +5306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10010 .loc 1 5306 9 view .LVU3388 +5306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10011 .loc 1 5306 9 view .LVU3389 + 10012 0074 0023 movs r3, #0 + 10013 0076 84F84030 strb r3, [r4, #64] +5306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10014 .loc 1 5306 9 view .LVU3390 +5312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10015 .loc 1 5312 9 view .LVU3391 + 10016 007a 3A46 mov r2, r7 + 10017 007c 3146 mov r1, r6 + 10018 007e 2046 mov r0, r4 + 10019 0080 FFF7FEFF bl HAL_I2C_AddrCallback + 10020 .LVL661: + 10021 0084 CAE7 b .L623 + 10022 .LVL662: + 10023 .L625: + ARM GAS /tmp/ccEimIdZ.s page 349 + + +5320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10024 .loc 1 5320 7 view .LVU3392 + 10025 0086 4FF40041 mov r1, #32768 + 10026 008a FFF7FEFF bl I2C_Disable_IRQ + 10027 .LVL663: +5323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10028 .loc 1 5323 7 view .LVU3393 +5323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10029 .loc 1 5323 7 view .LVU3394 + 10030 008e 0023 movs r3, #0 + 10031 0090 84F84030 strb r3, [r4, #64] +5323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10032 .loc 1 5323 7 view .LVU3395 +5329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10033 .loc 1 5329 7 view .LVU3396 + 10034 0094 2A46 mov r2, r5 + 10035 0096 3146 mov r1, r6 + 10036 0098 2046 mov r0, r4 + 10037 009a FFF7FEFF bl HAL_I2C_AddrCallback + 10038 .LVL664: + 10039 009e BDE7 b .L623 + 10040 .cfi_endproc + 10041 .LFE196: + 10043 .section .text.HAL_I2C_ListenCpltCallback,"ax",%progbits + 10044 .align 1 + 10045 .weak HAL_I2C_ListenCpltCallback + 10046 .syntax unified + 10047 .thumb + 10048 .thumb_func + 10049 .fpu fpv5-d16 + 10051 HAL_I2C_ListenCpltCallback: + 10052 .LVL665: + 10053 .LFB182: +4464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10054 .loc 1 4464 1 view -0 + 10055 .cfi_startproc + 10056 @ args = 0, pretend = 0, frame = 0 + 10057 @ frame_needed = 0, uses_anonymous_args = 0 + 10058 @ link register save eliminated. +4466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10059 .loc 1 4466 3 view .LVU3398 +4471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10060 .loc 1 4471 1 is_stmt 0 view .LVU3399 + 10061 0000 7047 bx lr + 10062 .cfi_endproc + 10063 .LFE182: + 10065 .section .text.I2C_ITListenCplt,"ax",%progbits + 10066 .align 1 + 10067 .syntax unified + 10068 .thumb + 10069 .thumb_func + 10070 .fpu fpv5-d16 + 10072 I2C_ITListenCplt: + 10073 .LVL666: + 10074 .LFB201: +5779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset handle parameters */ + 10075 .loc 1 5779 1 is_stmt 1 view -0 + ARM GAS /tmp/ccEimIdZ.s page 350 + + + 10076 .cfi_startproc + 10077 @ args = 0, pretend = 0, frame = 0 + 10078 @ frame_needed = 0, uses_anonymous_args = 0 +5779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Reset handle parameters */ + 10079 .loc 1 5779 1 is_stmt 0 view .LVU3401 + 10080 0000 10B5 push {r4, lr} + 10081 .LCFI117: + 10082 .cfi_def_cfa_offset 8 + 10083 .cfi_offset 4, -8 + 10084 .cfi_offset 14, -4 + 10085 0002 0446 mov r4, r0 +5781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10086 .loc 1 5781 3 is_stmt 1 view .LVU3402 +5781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10087 .loc 1 5781 21 is_stmt 0 view .LVU3403 + 10088 0004 174B ldr r3, .L634 + 10089 0006 C362 str r3, [r0, #44] +5782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10090 .loc 1 5782 3 is_stmt 1 view .LVU3404 +5782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10091 .loc 1 5782 23 is_stmt 0 view .LVU3405 + 10092 0008 0023 movs r3, #0 + 10093 000a 0363 str r3, [r0, #48] +5783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10094 .loc 1 5783 3 is_stmt 1 view .LVU3406 +5783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10095 .loc 1 5783 15 is_stmt 0 view .LVU3407 + 10096 000c 2022 movs r2, #32 + 10097 000e 80F84120 strb r2, [r0, #65] +5784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10098 .loc 1 5784 3 is_stmt 1 view .LVU3408 +5784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10099 .loc 1 5784 14 is_stmt 0 view .LVU3409 + 10100 0012 80F84230 strb r3, [r0, #66] +5785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10101 .loc 1 5785 3 is_stmt 1 view .LVU3410 +5785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10102 .loc 1 5785 17 is_stmt 0 view .LVU3411 + 10103 0016 4363 str r3, [r0, #52] +5788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10104 .loc 1 5788 3 is_stmt 1 view .LVU3412 +5788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10105 .loc 1 5788 6 is_stmt 0 view .LVU3413 + 10106 0018 11F0040F tst r1, #4 + 10107 001c 13D0 beq .L632 +5791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10108 .loc 1 5791 5 is_stmt 1 view .LVU3414 +5791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10109 .loc 1 5791 36 is_stmt 0 view .LVU3415 + 10110 001e 0368 ldr r3, [r0] +5791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10111 .loc 1 5791 46 view .LVU3416 + 10112 0020 5A6A ldr r2, [r3, #36] +5791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10113 .loc 1 5791 10 view .LVU3417 + 10114 0022 436A ldr r3, [r0, #36] +5791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 351 + + + 10115 .loc 1 5791 21 view .LVU3418 + 10116 0024 1A70 strb r2, [r3] +5794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10117 .loc 1 5794 5 is_stmt 1 view .LVU3419 +5794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10118 .loc 1 5794 9 is_stmt 0 view .LVU3420 + 10119 0026 436A ldr r3, [r0, #36] +5794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10120 .loc 1 5794 19 view .LVU3421 + 10121 0028 0133 adds r3, r3, #1 + 10122 002a 4362 str r3, [r0, #36] +5796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10123 .loc 1 5796 5 is_stmt 1 view .LVU3422 +5796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10124 .loc 1 5796 14 is_stmt 0 view .LVU3423 + 10125 002c 038D ldrh r3, [r0, #40] +5796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10126 .loc 1 5796 8 view .LVU3424 + 10127 002e 53B1 cbz r3, .L632 +5798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 10128 .loc 1 5798 7 is_stmt 1 view .LVU3425 +5798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 10129 .loc 1 5798 21 is_stmt 0 view .LVU3426 + 10130 0030 013B subs r3, r3, #1 + 10131 0032 0385 strh r3, [r0, #40] @ movhi +5799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10132 .loc 1 5799 7 is_stmt 1 view .LVU3427 +5799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10133 .loc 1 5799 11 is_stmt 0 view .LVU3428 + 10134 0034 438D ldrh r3, [r0, #42] + 10135 0036 9BB2 uxth r3, r3 +5799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10136 .loc 1 5799 22 view .LVU3429 + 10137 0038 013B subs r3, r3, #1 + 10138 003a 9BB2 uxth r3, r3 + 10139 003c 4385 strh r3, [r0, #42] @ movhi +5802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10140 .loc 1 5802 7 is_stmt 1 view .LVU3430 +5802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10141 .loc 1 5802 23 is_stmt 0 view .LVU3431 + 10142 003e 436C ldr r3, [r0, #68] + 10143 0040 43F00403 orr r3, r3, #4 + 10144 0044 4364 str r3, [r0, #68] + 10145 .L632: +5807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10146 .loc 1 5807 3 is_stmt 1 view .LVU3432 + 10147 0046 48F20301 movw r1, #32771 + 10148 .LVL667: +5807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10149 .loc 1 5807 3 is_stmt 0 view .LVU3433 + 10150 004a 2046 mov r0, r4 + 10151 .LVL668: +5807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10152 .loc 1 5807 3 view .LVU3434 + 10153 004c FFF7FEFF bl I2C_Disable_IRQ + 10154 .LVL669: +5810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 352 + + + 10155 .loc 1 5810 3 is_stmt 1 view .LVU3435 + 10156 0050 2368 ldr r3, [r4] + 10157 0052 1022 movs r2, #16 + 10158 0054 DA61 str r2, [r3, #28] +5813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10159 .loc 1 5813 3 view .LVU3436 +5813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10160 .loc 1 5813 3 view .LVU3437 + 10161 0056 0023 movs r3, #0 + 10162 0058 84F84030 strb r3, [r4, #64] +5813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10163 .loc 1 5813 3 view .LVU3438 +5819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10164 .loc 1 5819 3 view .LVU3439 + 10165 005c 2046 mov r0, r4 + 10166 005e FFF7FEFF bl HAL_I2C_ListenCpltCallback + 10167 .LVL670: +5821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10168 .loc 1 5821 1 is_stmt 0 view .LVU3440 + 10169 0062 10BD pop {r4, pc} + 10170 .LVL671: + 10171 .L635: +5821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10172 .loc 1 5821 1 view .LVU3441 + 10173 .align 2 + 10174 .L634: + 10175 0064 0000FFFF .word -65536 + 10176 .cfi_endproc + 10177 .LFE201: + 10179 .section .text.HAL_I2C_MemTxCpltCallback,"ax",%progbits + 10180 .align 1 + 10181 .weak HAL_I2C_MemTxCpltCallback + 10182 .syntax unified + 10183 .thumb + 10184 .thumb_func + 10185 .fpu fpv5-d16 + 10187 HAL_I2C_MemTxCpltCallback: + 10188 .LVL672: + 10189 .LFB183: +4480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10190 .loc 1 4480 1 is_stmt 1 view -0 + 10191 .cfi_startproc + 10192 @ args = 0, pretend = 0, frame = 0 + 10193 @ frame_needed = 0, uses_anonymous_args = 0 + 10194 @ link register save eliminated. +4482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10195 .loc 1 4482 3 view .LVU3443 +4487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10196 .loc 1 4487 1 is_stmt 0 view .LVU3444 + 10197 0000 7047 bx lr + 10198 .cfi_endproc + 10199 .LFE183: + 10201 .section .text.HAL_I2C_MemRxCpltCallback,"ax",%progbits + 10202 .align 1 + 10203 .weak HAL_I2C_MemRxCpltCallback + 10204 .syntax unified + 10205 .thumb + ARM GAS /tmp/ccEimIdZ.s page 353 + + + 10206 .thumb_func + 10207 .fpu fpv5-d16 + 10209 HAL_I2C_MemRxCpltCallback: + 10210 .LVL673: + 10211 .LFB184: +4496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10212 .loc 1 4496 1 is_stmt 1 view -0 + 10213 .cfi_startproc + 10214 @ args = 0, pretend = 0, frame = 0 + 10215 @ frame_needed = 0, uses_anonymous_args = 0 + 10216 @ link register save eliminated. +4498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10217 .loc 1 4498 3 view .LVU3446 +4503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10218 .loc 1 4503 1 is_stmt 0 view .LVU3447 + 10219 0000 7047 bx lr + 10220 .cfi_endproc + 10221 .LFE184: + 10223 .section .text.HAL_I2C_ErrorCallback,"ax",%progbits + 10224 .align 1 + 10225 .weak HAL_I2C_ErrorCallback + 10226 .syntax unified + 10227 .thumb + 10228 .thumb_func + 10229 .fpu fpv5-d16 + 10231 HAL_I2C_ErrorCallback: + 10232 .LVL674: + 10233 .LFB185: +4512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10234 .loc 1 4512 1 is_stmt 1 view -0 + 10235 .cfi_startproc + 10236 @ args = 0, pretend = 0, frame = 0 + 10237 @ frame_needed = 0, uses_anonymous_args = 0 + 10238 @ link register save eliminated. +4514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10239 .loc 1 4514 3 view .LVU3449 +4519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10240 .loc 1 4519 1 is_stmt 0 view .LVU3450 + 10241 0000 7047 bx lr + 10242 .cfi_endproc + 10243 .LFE185: + 10245 .section .text.HAL_I2C_AbortCpltCallback,"ax",%progbits + 10246 .align 1 + 10247 .weak HAL_I2C_AbortCpltCallback + 10248 .syntax unified + 10249 .thumb + 10250 .thumb_func + 10251 .fpu fpv5-d16 + 10253 HAL_I2C_AbortCpltCallback: + 10254 .LVL675: + 10255 .LFB186: +4528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10256 .loc 1 4528 1 is_stmt 1 view -0 + 10257 .cfi_startproc + 10258 @ args = 0, pretend = 0, frame = 0 + 10259 @ frame_needed = 0, uses_anonymous_args = 0 + 10260 @ link register save eliminated. + ARM GAS /tmp/ccEimIdZ.s page 354 + + +4530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10261 .loc 1 4530 3 view .LVU3452 +4535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10262 .loc 1 4535 1 is_stmt 0 view .LVU3453 + 10263 0000 7047 bx lr + 10264 .cfi_endproc + 10265 .LFE186: + 10267 .section .text.I2C_TreatErrorCallback,"ax",%progbits + 10268 .align 1 + 10269 .syntax unified + 10270 .thumb + 10271 .thumb_func + 10272 .fpu fpv5-d16 + 10274 I2C_TreatErrorCallback: + 10275 .LVL676: + 10276 .LFB203: +5940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 10277 .loc 1 5940 1 is_stmt 1 view -0 + 10278 .cfi_startproc + 10279 @ args = 0, pretend = 0, frame = 0 + 10280 @ frame_needed = 0, uses_anonymous_args = 0 +5940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 10281 .loc 1 5940 1 is_stmt 0 view .LVU3455 + 10282 0000 08B5 push {r3, lr} + 10283 .LCFI118: + 10284 .cfi_def_cfa_offset 8 + 10285 .cfi_offset 3, -8 + 10286 .cfi_offset 14, -4 +5941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10287 .loc 1 5941 3 is_stmt 1 view .LVU3456 +5941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10288 .loc 1 5941 11 is_stmt 0 view .LVU3457 + 10289 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10290 0006 DBB2 uxtb r3, r3 +5941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10291 .loc 1 5941 6 view .LVU3458 + 10292 0008 602B cmp r3, #96 + 10293 000a 06D0 beq .L644 +5958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10294 .loc 1 5958 5 is_stmt 1 view .LVU3459 +5958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10295 .loc 1 5958 25 is_stmt 0 view .LVU3460 + 10296 000c 0023 movs r3, #0 + 10297 000e 0363 str r3, [r0, #48] +5961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10298 .loc 1 5961 5 is_stmt 1 view .LVU3461 +5961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10299 .loc 1 5961 5 view .LVU3462 + 10300 0010 80F84030 strb r3, [r0, #64] +5961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10301 .loc 1 5961 5 view .LVU3463 +5967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10302 .loc 1 5967 5 view .LVU3464 + 10303 0014 FFF7FEFF bl HAL_I2C_ErrorCallback + 10304 .LVL677: + 10305 .L640: +5970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 355 + + + 10306 .loc 1 5970 1 is_stmt 0 view .LVU3465 + 10307 0018 08BD pop {r3, pc} + 10308 .LVL678: + 10309 .L644: +5943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10310 .loc 1 5943 5 is_stmt 1 view .LVU3466 +5943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10311 .loc 1 5943 17 is_stmt 0 view .LVU3467 + 10312 001a 2023 movs r3, #32 + 10313 001c 80F84130 strb r3, [r0, #65] +5944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10314 .loc 1 5944 5 is_stmt 1 view .LVU3468 +5944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10315 .loc 1 5944 25 is_stmt 0 view .LVU3469 + 10316 0020 0023 movs r3, #0 + 10317 0022 0363 str r3, [r0, #48] +5947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10318 .loc 1 5947 5 is_stmt 1 view .LVU3470 +5947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10319 .loc 1 5947 5 view .LVU3471 + 10320 0024 80F84030 strb r3, [r0, #64] +5947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10321 .loc 1 5947 5 view .LVU3472 +5953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10322 .loc 1 5953 5 view .LVU3473 + 10323 0028 FFF7FEFF bl HAL_I2C_AbortCpltCallback + 10324 .LVL679: +5953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10325 .loc 1 5953 5 is_stmt 0 view .LVU3474 + 10326 002c F4E7 b .L640 + 10327 .cfi_endproc + 10328 .LFE203: + 10330 .section .text.I2C_ITError,"ax",%progbits + 10331 .align 1 + 10332 .syntax unified + 10333 .thumb + 10334 .thumb_func + 10335 .fpu fpv5-d16 + 10337 I2C_ITError: + 10338 .LVL680: + 10339 .LFB202: +5830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10340 .loc 1 5830 1 is_stmt 1 view -0 + 10341 .cfi_startproc + 10342 @ args = 0, pretend = 0, frame = 0 + 10343 @ frame_needed = 0, uses_anonymous_args = 0 +5830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10344 .loc 1 5830 1 is_stmt 0 view .LVU3476 + 10345 0000 10B5 push {r4, lr} + 10346 .LCFI119: + 10347 .cfi_def_cfa_offset 8 + 10348 .cfi_offset 4, -8 + 10349 .cfi_offset 14, -4 + 10350 0002 0446 mov r4, r0 +5831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmppreviousstate; + 10351 .loc 1 5831 3 is_stmt 1 view .LVU3477 +5831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmppreviousstate; + ARM GAS /tmp/ccEimIdZ.s page 356 + + + 10352 .loc 1 5831 24 is_stmt 0 view .LVU3478 + 10353 0004 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10354 .LVL681: +5832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10355 .loc 1 5832 3 is_stmt 1 view .LVU3479 +5835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 10356 .loc 1 5835 3 view .LVU3480 +5835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 10357 .loc 1 5835 23 is_stmt 0 view .LVU3481 + 10358 0008 0020 movs r0, #0 + 10359 .LVL682: +5835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 10360 .loc 1 5835 23 view .LVU3482 + 10361 000a 84F84200 strb r0, [r4, #66] +5836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = 0U; + 10362 .loc 1 5836 3 is_stmt 1 view .LVU3483 +5836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount = 0U; + 10363 .loc 1 5836 23 is_stmt 0 view .LVU3484 + 10364 000e 3B4A ldr r2, .L657 + 10365 0010 E262 str r2, [r4, #44] +5837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10366 .loc 1 5837 3 is_stmt 1 view .LVU3485 +5837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10367 .loc 1 5837 23 is_stmt 0 view .LVU3486 + 10368 0012 6085 strh r0, [r4, #42] @ movhi +5840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10369 .loc 1 5840 3 is_stmt 1 view .LVU3487 +5840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10370 .loc 1 5840 19 is_stmt 0 view .LVU3488 + 10371 0014 626C ldr r2, [r4, #68] + 10372 0016 0A43 orrs r2, r2, r1 + 10373 0018 6264 str r2, [r4, #68] +5843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 10374 .loc 1 5843 3 is_stmt 1 view .LVU3489 +5844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 10375 .loc 1 5844 50 is_stmt 0 view .LVU3490 + 10376 001a 283B subs r3, r3, #40 + 10377 .LVL683: +5844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 10378 .loc 1 5844 50 view .LVU3491 + 10379 001c DBB2 uxtb r3, r3 +5843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 10380 .loc 1 5843 6 view .LVU3492 + 10381 001e 022B cmp r3, #2 + 10382 0020 2DD8 bhi .L646 +5848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10383 .loc 1 5848 5 is_stmt 1 view .LVU3493 + 10384 0022 0321 movs r1, #3 + 10385 .LVL684: +5848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10386 .loc 1 5848 5 is_stmt 0 view .LVU3494 + 10387 0024 2046 mov r0, r4 + 10388 0026 FFF7FEFF bl I2C_Disable_IRQ + 10389 .LVL685: +5851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 10390 .loc 1 5851 5 is_stmt 1 view .LVU3495 +5851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + ARM GAS /tmp/ccEimIdZ.s page 357 + + + 10391 .loc 1 5851 25 is_stmt 0 view .LVU3496 + 10392 002a 2823 movs r3, #40 + 10393 002c 84F84130 strb r3, [r4, #65] +5852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10394 .loc 1 5852 5 is_stmt 1 view .LVU3497 +5852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10395 .loc 1 5852 25 is_stmt 0 view .LVU3498 + 10396 0030 334B ldr r3, .L657+4 + 10397 0032 6363 str r3, [r4, #52] + 10398 .L647: +5870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstat + 10399 .loc 1 5870 3 is_stmt 1 view .LVU3499 +5870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstat + 10400 .loc 1 5870 20 is_stmt 0 view .LVU3500 + 10401 0034 236B ldr r3, [r4, #48] + 10402 .LVL686: +5871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10403 .loc 1 5871 3 is_stmt 1 view .LVU3501 +5871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10404 .loc 1 5871 12 is_stmt 0 view .LVU3502 + 10405 0036 A26B ldr r2, [r4, #56] +5871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10406 .loc 1 5871 6 view .LVU3503 + 10407 0038 002A cmp r2, #0 + 10408 003a 34D0 beq .L649 +5871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10409 .loc 1 5871 30 discriminator 1 view .LVU3504 + 10410 003c 212B cmp r3, #33 + 10411 003e 18BF it ne + 10412 0040 112B cmpne r3, #17 + 10413 0042 30D1 bne .L649 +5873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10414 .loc 1 5873 5 is_stmt 1 view .LVU3505 +5873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10415 .loc 1 5873 14 is_stmt 0 view .LVU3506 + 10416 0044 2368 ldr r3, [r4] + 10417 .LVL687: +5873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10418 .loc 1 5873 24 view .LVU3507 + 10419 0046 1A68 ldr r2, [r3] +5873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10420 .loc 1 5873 8 view .LVU3508 + 10421 0048 12F4804F tst r2, #16384 + 10422 004c 03D0 beq .L650 +5875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10423 .loc 1 5875 7 is_stmt 1 view .LVU3509 +5875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10424 .loc 1 5875 27 is_stmt 0 view .LVU3510 + 10425 004e 1A68 ldr r2, [r3] + 10426 0050 22F48042 bic r2, r2, #16384 + 10427 0054 1A60 str r2, [r3] + 10428 .L650: +5878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10429 .loc 1 5878 5 is_stmt 1 view .LVU3511 +5878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10430 .loc 1 5878 9 is_stmt 0 view .LVU3512 + 10431 0056 A06B ldr r0, [r4, #56] + ARM GAS /tmp/ccEimIdZ.s page 358 + + + 10432 0058 FFF7FEFF bl HAL_DMA_GetState + 10433 .LVL688: +5878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10434 .loc 1 5878 8 view .LVU3513 + 10435 005c 0128 cmp r0, #1 + 10436 005e 1ED0 beq .L651 +5882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10437 .loc 1 5882 7 is_stmt 1 view .LVU3514 +5882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10438 .loc 1 5882 11 is_stmt 0 view .LVU3515 + 10439 0060 A36B ldr r3, [r4, #56] +5882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10440 .loc 1 5882 39 view .LVU3516 + 10441 0062 284A ldr r2, .L657+8 + 10442 0064 1A65 str r2, [r3, #80] +5885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10443 .loc 1 5885 7 is_stmt 1 view .LVU3517 +5885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10444 .loc 1 5885 7 view .LVU3518 + 10445 0066 0023 movs r3, #0 + 10446 0068 84F84030 strb r3, [r4, #64] +5885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10447 .loc 1 5885 7 view .LVU3519 +5888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10448 .loc 1 5888 7 view .LVU3520 +5888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10449 .loc 1 5888 11 is_stmt 0 view .LVU3521 + 10450 006c A06B ldr r0, [r4, #56] + 10451 006e FFF7FEFF bl HAL_DMA_Abort_IT + 10452 .LVL689: +5888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10453 .loc 1 5888 10 view .LVU3522 + 10454 0072 0028 cmp r0, #0 + 10455 0074 40D0 beq .L645 +5891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10456 .loc 1 5891 9 is_stmt 1 view .LVU3523 +5891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10457 .loc 1 5891 13 is_stmt 0 view .LVU3524 + 10458 0076 A06B ldr r0, [r4, #56] +5891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10459 .loc 1 5891 21 view .LVU3525 + 10460 0078 036D ldr r3, [r0, #80] +5891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10461 .loc 1 5891 9 view .LVU3526 + 10462 007a 9847 blx r3 + 10463 .LVL690: + 10464 007c 3CE0 b .L645 + 10465 .LVL691: + 10466 .L646: +5857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10467 .loc 1 5857 5 is_stmt 1 view .LVU3527 + 10468 007e 48F20301 movw r1, #32771 + 10469 .LVL692: +5857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10470 .loc 1 5857 5 is_stmt 0 view .LVU3528 + 10471 0082 2046 mov r0, r4 + 10472 0084 FFF7FEFF bl I2C_Disable_IRQ + ARM GAS /tmp/ccEimIdZ.s page 359 + + + 10473 .LVL693: +5861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10474 .loc 1 5861 5 is_stmt 1 view .LVU3529 +5861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10475 .loc 1 5861 13 is_stmt 0 view .LVU3530 + 10476 0088 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10477 008c DBB2 uxtb r3, r3 +5861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10478 .loc 1 5861 8 view .LVU3531 + 10479 008e 602B cmp r3, #96 + 10480 0090 02D0 beq .L648 +5864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10481 .loc 1 5864 7 is_stmt 1 view .LVU3532 +5864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10482 .loc 1 5864 27 is_stmt 0 view .LVU3533 + 10483 0092 2023 movs r3, #32 + 10484 0094 84F84130 strb r3, [r4, #65] + 10485 .L648: +5866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10486 .loc 1 5866 5 is_stmt 1 view .LVU3534 +5866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10487 .loc 1 5866 25 is_stmt 0 view .LVU3535 + 10488 0098 0023 movs r3, #0 + 10489 009a 6363 str r3, [r4, #52] + 10490 009c CAE7 b .L647 + 10491 .L651: +5896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10492 .loc 1 5896 7 is_stmt 1 view .LVU3536 + 10493 009e 2046 mov r0, r4 + 10494 00a0 FFF7FEFF bl I2C_TreatErrorCallback + 10495 .LVL694: + 10496 00a4 28E0 b .L645 + 10497 .LVL695: + 10498 .L649: +5900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10499 .loc 1 5900 8 view .LVU3537 +5900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10500 .loc 1 5900 17 is_stmt 0 view .LVU3538 + 10501 00a6 E26B ldr r2, [r4, #60] +5900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10502 .loc 1 5900 11 view .LVU3539 + 10503 00a8 1AB3 cbz r2, .L653 +5900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10504 .loc 1 5900 35 discriminator 1 view .LVU3540 + 10505 00aa 222B cmp r3, #34 + 10506 00ac 18BF it ne + 10507 00ae 122B cmpne r3, #18 + 10508 00b0 1FD1 bne .L653 +5902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10509 .loc 1 5902 5 is_stmt 1 view .LVU3541 +5902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10510 .loc 1 5902 14 is_stmt 0 view .LVU3542 + 10511 00b2 2368 ldr r3, [r4] + 10512 .LVL696: +5902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10513 .loc 1 5902 24 view .LVU3543 + 10514 00b4 1A68 ldr r2, [r3] + ARM GAS /tmp/ccEimIdZ.s page 360 + + +5902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10515 .loc 1 5902 8 view .LVU3544 + 10516 00b6 12F4004F tst r2, #32768 + 10517 00ba 03D0 beq .L654 +5904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10518 .loc 1 5904 7 is_stmt 1 view .LVU3545 +5904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10519 .loc 1 5904 27 is_stmt 0 view .LVU3546 + 10520 00bc 1A68 ldr r2, [r3] + 10521 00be 22F40042 bic r2, r2, #32768 + 10522 00c2 1A60 str r2, [r3] + 10523 .L654: +5907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10524 .loc 1 5907 5 is_stmt 1 view .LVU3547 +5907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10525 .loc 1 5907 9 is_stmt 0 view .LVU3548 + 10526 00c4 E06B ldr r0, [r4, #60] + 10527 00c6 FFF7FEFF bl HAL_DMA_GetState + 10528 .LVL697: +5907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10529 .loc 1 5907 8 view .LVU3549 + 10530 00ca 0128 cmp r0, #1 + 10531 00cc 0DD0 beq .L655 +5911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10532 .loc 1 5911 7 is_stmt 1 view .LVU3550 +5911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10533 .loc 1 5911 11 is_stmt 0 view .LVU3551 + 10534 00ce E36B ldr r3, [r4, #60] +5911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10535 .loc 1 5911 39 view .LVU3552 + 10536 00d0 0C4A ldr r2, .L657+8 + 10537 00d2 1A65 str r2, [r3, #80] +5914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10538 .loc 1 5914 7 is_stmt 1 view .LVU3553 +5914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10539 .loc 1 5914 7 view .LVU3554 + 10540 00d4 0023 movs r3, #0 + 10541 00d6 84F84030 strb r3, [r4, #64] +5914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10542 .loc 1 5914 7 view .LVU3555 +5917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10543 .loc 1 5917 7 view .LVU3556 +5917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10544 .loc 1 5917 11 is_stmt 0 view .LVU3557 + 10545 00da E06B ldr r0, [r4, #60] + 10546 00dc FFF7FEFF bl HAL_DMA_Abort_IT + 10547 .LVL698: +5917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10548 .loc 1 5917 10 view .LVU3558 + 10549 00e0 50B1 cbz r0, .L645 +5920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10550 .loc 1 5920 9 is_stmt 1 view .LVU3559 +5920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10551 .loc 1 5920 13 is_stmt 0 view .LVU3560 + 10552 00e2 E06B ldr r0, [r4, #60] +5920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10553 .loc 1 5920 21 view .LVU3561 + ARM GAS /tmp/ccEimIdZ.s page 361 + + + 10554 00e4 036D ldr r3, [r0, #80] +5920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10555 .loc 1 5920 9 view .LVU3562 + 10556 00e6 9847 blx r3 + 10557 .LVL699: + 10558 00e8 06E0 b .L645 + 10559 .L655: +5925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10560 .loc 1 5925 7 is_stmt 1 view .LVU3563 + 10561 00ea 2046 mov r0, r4 + 10562 00ec FFF7FEFF bl I2C_TreatErrorCallback + 10563 .LVL700: + 10564 00f0 02E0 b .L645 + 10565 .LVL701: + 10566 .L653: +5930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10567 .loc 1 5930 5 view .LVU3564 + 10568 00f2 2046 mov r0, r4 + 10569 00f4 FFF7FEFF bl I2C_TreatErrorCallback + 10570 .LVL702: + 10571 .L645: +5932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10572 .loc 1 5932 1 is_stmt 0 view .LVU3565 + 10573 00f8 10BD pop {r4, pc} + 10574 .LVL703: + 10575 .L658: +5932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10576 .loc 1 5932 1 view .LVU3566 + 10577 00fa 00BF .align 2 + 10578 .L657: + 10579 00fc 0000FFFF .word -65536 + 10580 0100 00000000 .word I2C_Slave_ISR_IT + 10581 0104 00000000 .word I2C_DMAAbort + 10582 .cfi_endproc + 10583 .LFE202: + 10585 .section .text.I2C_ITSlaveCplt,"ax",%progbits + 10586 .align 1 + 10587 .syntax unified + 10588 .thumb + 10589 .thumb_func + 10590 .fpu fpv5-d16 + 10592 I2C_ITSlaveCplt: + 10593 .LVL704: + 10594 .LFB200: +5620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10595 .loc 1 5620 1 is_stmt 1 view -0 + 10596 .cfi_startproc + 10597 @ args = 0, pretend = 0, frame = 0 + 10598 @ frame_needed = 0, uses_anonymous_args = 0 +5620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10599 .loc 1 5620 1 is_stmt 0 view .LVU3568 + 10600 0000 70B5 push {r4, r5, r6, lr} + 10601 .LCFI120: + 10602 .cfi_def_cfa_offset 16 + 10603 .cfi_offset 4, -16 + 10604 .cfi_offset 5, -12 + 10605 .cfi_offset 6, -8 + ARM GAS /tmp/ccEimIdZ.s page 362 + + + 10606 .cfi_offset 14, -4 + 10607 0002 0446 mov r4, r0 + 10608 0004 0D46 mov r5, r1 +5621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10609 .loc 1 5621 3 is_stmt 1 view .LVU3569 +5621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10610 .loc 1 5621 26 is_stmt 0 view .LVU3570 + 10611 0006 0268 ldr r2, [r0] +5621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10612 .loc 1 5621 12 view .LVU3571 + 10613 0008 1668 ldr r6, [r2] + 10614 .LVL705: +5622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10615 .loc 1 5622 3 is_stmt 1 view .LVU3572 +5623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10616 .loc 1 5623 3 view .LVU3573 +5623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10617 .loc 1 5623 24 is_stmt 0 view .LVU3574 + 10618 000a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10619 000e DBB2 uxtb r3, r3 + 10620 .LVL706: +5626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10621 .loc 1 5626 3 is_stmt 1 view .LVU3575 + 10622 0010 2021 movs r1, #32 + 10623 .LVL707: +5626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10624 .loc 1 5626 3 is_stmt 0 view .LVU3576 + 10625 0012 D161 str r1, [r2, #28] +5629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10626 .loc 1 5629 3 is_stmt 1 view .LVU3577 +5629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10627 .loc 1 5629 6 is_stmt 0 view .LVU3578 + 10628 0014 292B cmp r3, #41 + 10629 0016 18BF it ne + 10630 0018 212B cmpne r3, #33 + 10631 001a 57D0 beq .L677 +5634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10632 .loc 1 5634 8 is_stmt 1 view .LVU3579 +5634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10633 .loc 1 5634 11 is_stmt 0 view .LVU3580 + 10634 001c 2A2B cmp r3, #42 + 10635 001e 18BF it ne + 10636 0020 222B cmpne r3, #34 + 10637 0022 5AD0 beq .L678 + 10638 .LVL708: + 10639 .L661: +5642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10640 .loc 1 5642 3 is_stmt 1 view .LVU3581 +5645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10641 .loc 1 5645 3 view .LVU3582 +5645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10642 .loc 1 5645 7 is_stmt 0 view .LVU3583 + 10643 0024 2268 ldr r2, [r4] +5645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10644 .loc 1 5645 23 view .LVU3584 + 10645 0026 5368 ldr r3, [r2, #4] + 10646 0028 43F40043 orr r3, r3, #32768 + ARM GAS /tmp/ccEimIdZ.s page 363 + + + 10647 002c 5360 str r3, [r2, #4] +5648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10648 .loc 1 5648 3 is_stmt 1 view .LVU3585 + 10649 002e 2268 ldr r2, [r4] + 10650 0030 5368 ldr r3, [r2, #4] + 10651 0032 23F0FF73 bic r3, r3, #33423360 + 10652 0036 23F48B33 bic r3, r3, #71168 + 10653 003a 23F4FF73 bic r3, r3, #510 + 10654 003e 23F00103 bic r3, r3, #1 + 10655 0042 5360 str r3, [r2, #4] +5651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10656 .loc 1 5651 3 view .LVU3586 + 10657 0044 2046 mov r0, r4 + 10658 0046 FFF7FEFF bl I2C_Flush_TXDR + 10659 .LVL709: +5654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10660 .loc 1 5654 3 view .LVU3587 +5654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10661 .loc 1 5654 6 is_stmt 0 view .LVU3588 + 10662 004a 16F4804F tst r6, #16384 + 10663 004e 00F08580 beq .L662 +5657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10664 .loc 1 5657 5 is_stmt 1 view .LVU3589 +5657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10665 .loc 1 5657 9 is_stmt 0 view .LVU3590 + 10666 0052 2268 ldr r2, [r4] +5657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10667 .loc 1 5657 25 view .LVU3591 + 10668 0054 1368 ldr r3, [r2] + 10669 0056 23F48043 bic r3, r3, #16384 + 10670 005a 1360 str r3, [r2] +5659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10671 .loc 1 5659 5 is_stmt 1 view .LVU3592 +5659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10672 .loc 1 5659 13 is_stmt 0 view .LVU3593 + 10673 005c A36B ldr r3, [r4, #56] +5659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10674 .loc 1 5659 8 view .LVU3594 + 10675 005e 002B cmp r3, #0 + 10676 0060 45D0 beq .L663 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10677 .loc 1 5661 7 is_stmt 1 view .LVU3595 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10678 .loc 1 5661 35 is_stmt 0 view .LVU3596 + 10679 0062 1B68 ldr r3, [r3] +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10680 .loc 1 5661 25 view .LVU3597 + 10681 0064 7449 ldr r1, .L682 + 10682 0066 754A ldr r2, .L682+4 + 10683 0068 9342 cmp r3, r2 + 10684 006a 18BF it ne + 10685 006c 8B42 cmpne r3, r1 + 10686 006e 3BD0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10687 .loc 1 5661 35 discriminator 2 view .LVU3598 + 10688 0070 1832 adds r2, r2, #24 + 10689 0072 9342 cmp r3, r2 + ARM GAS /tmp/ccEimIdZ.s page 364 + + + 10690 0074 38D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10691 .loc 1 5661 35 discriminator 4 view .LVU3599 + 10692 0076 1832 adds r2, r2, #24 + 10693 0078 9342 cmp r3, r2 + 10694 007a 35D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10695 .loc 1 5661 35 discriminator 6 view .LVU3600 + 10696 007c 1832 adds r2, r2, #24 + 10697 007e 9342 cmp r3, r2 + 10698 0080 32D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10699 .loc 1 5661 35 discriminator 8 view .LVU3601 + 10700 0082 1832 adds r2, r2, #24 + 10701 0084 9342 cmp r3, r2 + 10702 0086 2FD0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10703 .loc 1 5661 35 discriminator 10 view .LVU3602 + 10704 0088 1832 adds r2, r2, #24 + 10705 008a 9342 cmp r3, r2 + 10706 008c 2CD0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10707 .loc 1 5661 35 discriminator 12 view .LVU3603 + 10708 008e 1832 adds r2, r2, #24 + 10709 0090 9342 cmp r3, r2 + 10710 0092 29D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10711 .loc 1 5661 35 discriminator 14 view .LVU3604 + 10712 0094 02F55672 add r2, r2, #856 + 10713 0098 9342 cmp r3, r2 + 10714 009a 25D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10715 .loc 1 5661 35 discriminator 16 view .LVU3605 + 10716 009c 1832 adds r2, r2, #24 + 10717 009e 9342 cmp r3, r2 + 10718 00a0 22D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10719 .loc 1 5661 35 discriminator 18 view .LVU3606 + 10720 00a2 1832 adds r2, r2, #24 + 10721 00a4 9342 cmp r3, r2 + 10722 00a6 1FD0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10723 .loc 1 5661 35 discriminator 20 view .LVU3607 + 10724 00a8 1832 adds r2, r2, #24 + 10725 00aa 9342 cmp r3, r2 + 10726 00ac 1CD0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10727 .loc 1 5661 35 discriminator 22 view .LVU3608 + 10728 00ae 1832 adds r2, r2, #24 + 10729 00b0 9342 cmp r3, r2 + 10730 00b2 19D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10731 .loc 1 5661 35 discriminator 24 view .LVU3609 + 10732 00b4 1832 adds r2, r2, #24 + 10733 00b6 9342 cmp r3, r2 + 10734 00b8 16D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 365 + + + 10735 .loc 1 5661 35 discriminator 26 view .LVU3610 + 10736 00ba 1832 adds r2, r2, #24 + 10737 00bc 9342 cmp r3, r2 + 10738 00be 13D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10739 .loc 1 5661 35 discriminator 28 view .LVU3611 + 10740 00c0 1832 adds r2, r2, #24 + 10741 00c2 9342 cmp r3, r2 + 10742 00c4 10D0 beq .L664 +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10743 .loc 1 5661 35 discriminator 30 view .LVU3612 + 10744 00c6 5B68 ldr r3, [r3, #4] +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10745 .loc 1 5661 25 discriminator 30 view .LVU3613 + 10746 00c8 9BB2 uxth r3, r3 + 10747 00ca 0FE0 b .L666 + 10748 .LVL710: + 10749 .L677: +5631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10750 .loc 1 5631 5 is_stmt 1 view .LVU3614 + 10751 00cc 48F20101 movw r1, #32769 + 10752 00d0 FFF7FEFF bl I2C_Disable_IRQ + 10753 .LVL711: +5632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10754 .loc 1 5632 5 view .LVU3615 +5632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10755 .loc 1 5632 25 is_stmt 0 view .LVU3616 + 10756 00d4 2123 movs r3, #33 + 10757 00d6 2363 str r3, [r4, #48] + 10758 00d8 A4E7 b .L661 + 10759 .LVL712: + 10760 .L678: +5636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10761 .loc 1 5636 5 is_stmt 1 view .LVU3617 + 10762 00da 48F20201 movw r1, #32770 + 10763 00de FFF7FEFF bl I2C_Disable_IRQ + 10764 .LVL713: +5637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10765 .loc 1 5637 5 view .LVU3618 +5637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10766 .loc 1 5637 25 is_stmt 0 view .LVU3619 + 10767 00e2 2223 movs r3, #34 + 10768 00e4 2363 str r3, [r4, #48] + 10769 00e6 9DE7 b .L661 + 10770 .L664: +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10771 .loc 1 5661 35 discriminator 29 view .LVU3620 + 10772 00e8 5B68 ldr r3, [r3, #4] +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10773 .loc 1 5661 25 discriminator 29 view .LVU3621 + 10774 00ea 9BB2 uxth r3, r3 + 10775 .L666: +5661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10776 .loc 1 5661 23 discriminator 32 view .LVU3622 + 10777 00ec 6385 strh r3, [r4, #42] @ movhi + 10778 .L663: +5677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 366 + + + 10779 .loc 1 5677 3 is_stmt 1 view .LVU3623 +5680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10780 .loc 1 5680 3 view .LVU3624 +5680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10781 .loc 1 5680 6 is_stmt 0 view .LVU3625 + 10782 00ee 15F0040F tst r5, #4 + 10783 00f2 11D0 beq .L670 +5683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10784 .loc 1 5683 5 is_stmt 1 view .LVU3626 +5683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10785 .loc 1 5683 16 is_stmt 0 view .LVU3627 + 10786 00f4 25F00405 bic r5, r5, #4 + 10787 .LVL714: +5686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10788 .loc 1 5686 5 is_stmt 1 view .LVU3628 +5686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10789 .loc 1 5686 36 is_stmt 0 view .LVU3629 + 10790 00f8 2368 ldr r3, [r4] +5686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10791 .loc 1 5686 46 view .LVU3630 + 10792 00fa 5A6A ldr r2, [r3, #36] +5686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10793 .loc 1 5686 10 view .LVU3631 + 10794 00fc 636A ldr r3, [r4, #36] +5686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10795 .loc 1 5686 21 view .LVU3632 + 10796 00fe 1A70 strb r2, [r3] +5689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10797 .loc 1 5689 5 is_stmt 1 view .LVU3633 +5689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10798 .loc 1 5689 9 is_stmt 0 view .LVU3634 + 10799 0100 636A ldr r3, [r4, #36] +5689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10800 .loc 1 5689 19 view .LVU3635 + 10801 0102 0133 adds r3, r3, #1 + 10802 0104 6362 str r3, [r4, #36] +5691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10803 .loc 1 5691 5 is_stmt 1 view .LVU3636 +5691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10804 .loc 1 5691 14 is_stmt 0 view .LVU3637 + 10805 0106 238D ldrh r3, [r4, #40] +5691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10806 .loc 1 5691 8 view .LVU3638 + 10807 0108 33B1 cbz r3, .L670 +5693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 10808 .loc 1 5693 7 is_stmt 1 view .LVU3639 +5693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 10809 .loc 1 5693 21 is_stmt 0 view .LVU3640 + 10810 010a 013B subs r3, r3, #1 + 10811 010c 2385 strh r3, [r4, #40] @ movhi +5694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10812 .loc 1 5694 7 is_stmt 1 view .LVU3641 +5694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10813 .loc 1 5694 11 is_stmt 0 view .LVU3642 + 10814 010e 638D ldrh r3, [r4, #42] + 10815 0110 9BB2 uxth r3, r3 +5694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 367 + + + 10816 .loc 1 5694 22 view .LVU3643 + 10817 0112 013B subs r3, r3, #1 + 10818 0114 9BB2 uxth r3, r3 + 10819 0116 6385 strh r3, [r4, #42] @ movhi + 10820 .L670: +5699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10821 .loc 1 5699 3 is_stmt 1 view .LVU3644 +5699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10822 .loc 1 5699 11 is_stmt 0 view .LVU3645 + 10823 0118 638D ldrh r3, [r4, #42] + 10824 011a 9BB2 uxth r3, r3 +5699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10825 .loc 1 5699 6 view .LVU3646 + 10826 011c 1BB1 cbz r3, .L671 +5702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10827 .loc 1 5702 5 is_stmt 1 view .LVU3647 +5702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10828 .loc 1 5702 21 is_stmt 0 view .LVU3648 + 10829 011e 636C ldr r3, [r4, #68] + 10830 0120 43F00403 orr r3, r3, #4 + 10831 0124 6364 str r3, [r4, #68] + 10832 .L671: +5705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10833 .loc 1 5705 3 is_stmt 1 view .LVU3649 +5705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10834 .loc 1 5705 14 is_stmt 0 view .LVU3650 + 10835 0126 0023 movs r3, #0 + 10836 0128 84F84230 strb r3, [r4, #66] +5706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10837 .loc 1 5706 3 is_stmt 1 view .LVU3651 +5706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10838 .loc 1 5706 17 is_stmt 0 view .LVU3652 + 10839 012c 6363 str r3, [r4, #52] +5708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10840 .loc 1 5708 3 is_stmt 1 view .LVU3653 +5708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10841 .loc 1 5708 11 is_stmt 0 view .LVU3654 + 10842 012e 636C ldr r3, [r4, #68] +5708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10843 .loc 1 5708 6 view .LVU3655 + 10844 0130 002B cmp r3, #0 + 10845 0132 57D1 bne .L679 +5720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10846 .loc 1 5720 8 is_stmt 1 view .LVU3656 +5720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10847 .loc 1 5720 16 is_stmt 0 view .LVU3657 + 10848 0134 E36A ldr r3, [r4, #44] +5720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10849 .loc 1 5720 11 view .LVU3658 + 10850 0136 13F5803F cmn r3, #65536 + 10851 013a 61D1 bne .L680 +5740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10852 .loc 1 5740 8 is_stmt 1 view .LVU3659 +5740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10853 .loc 1 5740 16 is_stmt 0 view .LVU3660 + 10854 013c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10855 0140 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 368 + + +5740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10856 .loc 1 5740 11 view .LVU3661 + 10857 0142 222B cmp r3, #34 + 10858 0144 6CD0 beq .L681 +5757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10859 .loc 1 5757 5 is_stmt 1 view .LVU3662 +5757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10860 .loc 1 5757 17 is_stmt 0 view .LVU3663 + 10861 0146 2023 movs r3, #32 + 10862 0148 84F84130 strb r3, [r4, #65] +5758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10863 .loc 1 5758 5 is_stmt 1 view .LVU3664 +5758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10864 .loc 1 5758 25 is_stmt 0 view .LVU3665 + 10865 014c 0023 movs r3, #0 + 10866 014e 2363 str r3, [r4, #48] +5761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10867 .loc 1 5761 5 is_stmt 1 view .LVU3666 +5761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10868 .loc 1 5761 5 view .LVU3667 + 10869 0150 84F84030 strb r3, [r4, #64] +5761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10870 .loc 1 5761 5 view .LVU3668 +5767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10871 .loc 1 5767 5 view .LVU3669 + 10872 0154 2046 mov r0, r4 + 10873 0156 FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 10874 .LVL715: +5770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10875 .loc 1 5770 1 is_stmt 0 view .LVU3670 + 10876 015a 60E0 b .L659 + 10877 .LVL716: + 10878 .L662: +5664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10879 .loc 1 5664 8 is_stmt 1 view .LVU3671 +5664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10880 .loc 1 5664 11 is_stmt 0 view .LVU3672 + 10881 015c 16F4004F tst r6, #32768 + 10882 0160 C5D0 beq .L663 +5667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10883 .loc 1 5667 5 is_stmt 1 view .LVU3673 +5667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10884 .loc 1 5667 9 is_stmt 0 view .LVU3674 + 10885 0162 2268 ldr r2, [r4] +5667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10886 .loc 1 5667 25 view .LVU3675 + 10887 0164 1368 ldr r3, [r2] + 10888 0166 23F40043 bic r3, r3, #32768 + 10889 016a 1360 str r3, [r2] +5669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10890 .loc 1 5669 5 is_stmt 1 view .LVU3676 +5669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10891 .loc 1 5669 13 is_stmt 0 view .LVU3677 + 10892 016c E36B ldr r3, [r4, #60] +5669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10893 .loc 1 5669 8 view .LVU3678 + 10894 016e 002B cmp r3, #0 + ARM GAS /tmp/ccEimIdZ.s page 369 + + + 10895 0170 BDD0 beq .L663 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10896 .loc 1 5671 7 is_stmt 1 view .LVU3679 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10897 .loc 1 5671 35 is_stmt 0 view .LVU3680 + 10898 0172 1B68 ldr r3, [r3] +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10899 .loc 1 5671 25 view .LVU3681 + 10900 0174 3049 ldr r1, .L682 + 10901 0176 314A ldr r2, .L682+4 + 10902 0178 9342 cmp r3, r2 + 10903 017a 18BF it ne + 10904 017c 8B42 cmpne r3, r1 + 10905 017e 2DD0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10906 .loc 1 5671 35 discriminator 2 view .LVU3682 + 10907 0180 1832 adds r2, r2, #24 + 10908 0182 9342 cmp r3, r2 + 10909 0184 2AD0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10910 .loc 1 5671 35 discriminator 4 view .LVU3683 + 10911 0186 1832 adds r2, r2, #24 + 10912 0188 9342 cmp r3, r2 + 10913 018a 27D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10914 .loc 1 5671 35 discriminator 6 view .LVU3684 + 10915 018c 1832 adds r2, r2, #24 + 10916 018e 9342 cmp r3, r2 + 10917 0190 24D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10918 .loc 1 5671 35 discriminator 8 view .LVU3685 + 10919 0192 1832 adds r2, r2, #24 + 10920 0194 9342 cmp r3, r2 + 10921 0196 21D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10922 .loc 1 5671 35 discriminator 10 view .LVU3686 + 10923 0198 1832 adds r2, r2, #24 + 10924 019a 9342 cmp r3, r2 + 10925 019c 1ED0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10926 .loc 1 5671 35 discriminator 12 view .LVU3687 + 10927 019e 1832 adds r2, r2, #24 + 10928 01a0 9342 cmp r3, r2 + 10929 01a2 1BD0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10930 .loc 1 5671 35 discriminator 14 view .LVU3688 + 10931 01a4 02F55672 add r2, r2, #856 + 10932 01a8 9342 cmp r3, r2 + 10933 01aa 17D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10934 .loc 1 5671 35 discriminator 16 view .LVU3689 + 10935 01ac 1832 adds r2, r2, #24 + 10936 01ae 9342 cmp r3, r2 + 10937 01b0 14D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10938 .loc 1 5671 35 discriminator 18 view .LVU3690 + 10939 01b2 1832 adds r2, r2, #24 + ARM GAS /tmp/ccEimIdZ.s page 370 + + + 10940 01b4 9342 cmp r3, r2 + 10941 01b6 11D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10942 .loc 1 5671 35 discriminator 20 view .LVU3691 + 10943 01b8 1832 adds r2, r2, #24 + 10944 01ba 9342 cmp r3, r2 + 10945 01bc 0ED0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10946 .loc 1 5671 35 discriminator 22 view .LVU3692 + 10947 01be 1832 adds r2, r2, #24 + 10948 01c0 9342 cmp r3, r2 + 10949 01c2 0BD0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10950 .loc 1 5671 35 discriminator 24 view .LVU3693 + 10951 01c4 1832 adds r2, r2, #24 + 10952 01c6 9342 cmp r3, r2 + 10953 01c8 08D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10954 .loc 1 5671 35 discriminator 26 view .LVU3694 + 10955 01ca 1832 adds r2, r2, #24 + 10956 01cc 9342 cmp r3, r2 + 10957 01ce 05D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10958 .loc 1 5671 35 discriminator 28 view .LVU3695 + 10959 01d0 1832 adds r2, r2, #24 + 10960 01d2 9342 cmp r3, r2 + 10961 01d4 02D0 beq .L667 +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10962 .loc 1 5671 35 discriminator 30 view .LVU3696 + 10963 01d6 5B68 ldr r3, [r3, #4] +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10964 .loc 1 5671 25 discriminator 30 view .LVU3697 + 10965 01d8 9BB2 uxth r3, r3 + 10966 01da 01E0 b .L669 + 10967 .L667: +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10968 .loc 1 5671 35 discriminator 29 view .LVU3698 + 10969 01dc 5B68 ldr r3, [r3, #4] +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10970 .loc 1 5671 25 discriminator 29 view .LVU3699 + 10971 01de 9BB2 uxth r3, r3 + 10972 .L669: +5671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10973 .loc 1 5671 23 discriminator 32 view .LVU3700 + 10974 01e0 6385 strh r3, [r4, #42] @ movhi + 10975 01e2 84E7 b .L663 + 10976 .LVL717: + 10977 .L679: +5711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10978 .loc 1 5711 5 is_stmt 1 view .LVU3701 + 10979 01e4 616C ldr r1, [r4, #68] + 10980 01e6 2046 mov r0, r4 + 10981 01e8 FFF7FEFF bl I2C_ITError + 10982 .LVL718: +5714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10983 .loc 1 5714 5 view .LVU3702 +5714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 371 + + + 10984 .loc 1 5714 13 is_stmt 0 view .LVU3703 + 10985 01ec 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10986 01f0 DBB2 uxtb r3, r3 +5714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 10987 .loc 1 5714 8 view .LVU3704 + 10988 01f2 282B cmp r3, #40 + 10989 01f4 13D1 bne .L659 +5717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 10990 .loc 1 5717 7 is_stmt 1 view .LVU3705 + 10991 01f6 2946 mov r1, r5 + 10992 01f8 2046 mov r0, r4 + 10993 01fa FFF7FEFF bl I2C_ITListenCplt + 10994 .LVL719: + 10995 01fe 0EE0 b .L659 + 10996 .L680: +5723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 10997 .loc 1 5723 5 view .LVU3706 + 10998 0200 2046 mov r0, r4 + 10999 0202 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11000 .LVL720: +5725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11001 .loc 1 5725 5 view .LVU3707 +5725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11002 .loc 1 5725 23 is_stmt 0 view .LVU3708 + 11003 0206 0E4B ldr r3, .L682+8 + 11004 0208 E362 str r3, [r4, #44] +5726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11005 .loc 1 5726 5 is_stmt 1 view .LVU3709 +5726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11006 .loc 1 5726 17 is_stmt 0 view .LVU3710 + 11007 020a 2023 movs r3, #32 + 11008 020c 84F84130 strb r3, [r4, #65] +5727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11009 .loc 1 5727 5 is_stmt 1 view .LVU3711 +5727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11010 .loc 1 5727 25 is_stmt 0 view .LVU3712 + 11011 0210 0023 movs r3, #0 + 11012 0212 2363 str r3, [r4, #48] +5730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11013 .loc 1 5730 5 is_stmt 1 view .LVU3713 +5730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11014 .loc 1 5730 5 view .LVU3714 + 11015 0214 84F84030 strb r3, [r4, #64] +5730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11016 .loc 1 5730 5 view .LVU3715 +5736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11017 .loc 1 5736 5 view .LVU3716 + 11018 0218 2046 mov r0, r4 + 11019 021a FFF7FEFF bl HAL_I2C_ListenCpltCallback + 11020 .LVL721: + 11021 .L659: +5770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11022 .loc 1 5770 1 is_stmt 0 view .LVU3717 + 11023 021e 70BD pop {r4, r5, r6, pc} + 11024 .LVL722: + 11025 .L681: +5742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + ARM GAS /tmp/ccEimIdZ.s page 372 + + + 11026 .loc 1 5742 5 is_stmt 1 view .LVU3718 +5742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11027 .loc 1 5742 17 is_stmt 0 view .LVU3719 + 11028 0220 2023 movs r3, #32 + 11029 0222 84F84130 strb r3, [r4, #65] +5743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11030 .loc 1 5743 5 is_stmt 1 view .LVU3720 +5743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11031 .loc 1 5743 25 is_stmt 0 view .LVU3721 + 11032 0226 0023 movs r3, #0 + 11033 0228 2363 str r3, [r4, #48] +5746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11034 .loc 1 5746 5 is_stmt 1 view .LVU3722 +5746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11035 .loc 1 5746 5 view .LVU3723 + 11036 022a 84F84030 strb r3, [r4, #64] +5746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11037 .loc 1 5746 5 view .LVU3724 +5752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11038 .loc 1 5752 5 view .LVU3725 + 11039 022e 2046 mov r0, r4 + 11040 0230 FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 11041 .LVL723: + 11042 0234 F3E7 b .L659 + 11043 .L683: + 11044 0236 00BF .align 2 + 11045 .L682: + 11046 0238 10000240 .word 1073872912 + 11047 023c 28000240 .word 1073872936 + 11048 0240 0000FFFF .word -65536 + 11049 .cfi_endproc + 11050 .LFE200: + 11052 .section .text.I2C_Slave_ISR_IT,"ax",%progbits + 11053 .align 1 + 11054 .syntax unified + 11055 .thumb + 11056 .thumb_func + 11057 .fpu fpv5-d16 + 11059 I2C_Slave_ISR_IT: + 11060 .LVL724: + 11061 .LFB191: +4748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11062 .loc 1 4748 1 view -0 + 11063 .cfi_startproc + 11064 @ args = 0, pretend = 0, frame = 0 + 11065 @ frame_needed = 0, uses_anonymous_args = 0 +4748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11066 .loc 1 4748 1 is_stmt 0 view .LVU3727 + 11067 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 11068 .LCFI121: + 11069 .cfi_def_cfa_offset 24 + 11070 .cfi_offset 3, -24 + 11071 .cfi_offset 4, -20 + 11072 .cfi_offset 5, -16 + 11073 .cfi_offset 6, -12 + 11074 .cfi_offset 7, -8 + 11075 .cfi_offset 14, -4 + ARM GAS /tmp/ccEimIdZ.s page 373 + + +4749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11076 .loc 1 4749 3 is_stmt 1 view .LVU3728 +4749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11077 .loc 1 4749 12 is_stmt 0 view .LVU3729 + 11078 0002 C76A ldr r7, [r0, #44] + 11079 .LVL725: +4750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11080 .loc 1 4750 3 is_stmt 1 view .LVU3730 +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11081 .loc 1 4753 3 view .LVU3731 +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11082 .loc 1 4753 3 view .LVU3732 + 11083 0004 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 11084 0008 012B cmp r3, #1 + 11085 000a 00F09F80 beq .L696 + 11086 000e 0446 mov r4, r0 + 11087 0010 0D46 mov r5, r1 + 11088 0012 1646 mov r6, r2 +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11089 .loc 1 4753 3 discriminator 2 view .LVU3733 + 11090 0014 0123 movs r3, #1 + 11091 0016 80F84030 strb r3, [r0, #64] +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11092 .loc 1 4753 3 discriminator 2 view .LVU3734 +4756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11093 .loc 1 4756 3 discriminator 2 view .LVU3735 +4756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11094 .loc 1 4756 6 is_stmt 0 discriminator 2 view .LVU3736 + 11095 001a 11F0200F tst r1, #32 + 11096 001e 02D0 beq .L686 +4756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11097 .loc 1 4756 61 discriminator 1 view .LVU3737 + 11098 0020 12F0200F tst r2, #32 + 11099 0024 19D1 bne .L698 + 11100 .LVL726: + 11101 .L686: +4762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11102 .loc 1 4762 3 is_stmt 1 view .LVU3738 +4762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11103 .loc 1 4762 6 is_stmt 0 view .LVU3739 + 11104 0026 15F0100F tst r5, #16 + 11105 002a 3FD0 beq .L687 +4762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11106 .loc 1 4762 58 discriminator 1 view .LVU3740 + 11107 002c 16F0100F tst r6, #16 + 11108 0030 3CD0 beq .L687 +4768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11109 .loc 1 4768 5 is_stmt 1 view .LVU3741 +4768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11110 .loc 1 4768 13 is_stmt 0 view .LVU3742 + 11111 0032 638D ldrh r3, [r4, #42] + 11112 0034 9BB2 uxth r3, r3 +4768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11113 .loc 1 4768 8 view .LVU3743 + 11114 0036 43BB cbnz r3, .L688 +4770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11115 .loc 1 4770 7 is_stmt 1 view .LVU3744 + ARM GAS /tmp/ccEimIdZ.s page 374 + + +4770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11116 .loc 1 4770 16 is_stmt 0 view .LVU3745 + 11117 0038 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11118 003c DBB2 uxtb r3, r3 +4770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11119 .loc 1 4770 10 view .LVU3746 + 11120 003e 282B cmp r3, #40 + 11121 0040 0ED0 beq .L699 + 11122 .L689: +4775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11123 .loc 1 4775 12 is_stmt 1 view .LVU3747 +4775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11124 .loc 1 4775 21 is_stmt 0 view .LVU3748 + 11125 0042 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11126 0046 DBB2 uxtb r3, r3 +4775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11127 .loc 1 4775 15 view .LVU3749 + 11128 0048 292B cmp r3, #41 + 11129 004a 11D0 beq .L700 + 11130 .L691: +4790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11131 .loc 1 4790 9 is_stmt 1 view .LVU3750 + 11132 004c 2368 ldr r3, [r4] + 11133 004e 1022 movs r2, #16 + 11134 0050 DA61 str r2, [r3, #28] + 11135 .L690: +4864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11136 .loc 1 4864 3 view .LVU3751 +4867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11137 .loc 1 4867 3 view .LVU3752 +4867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11138 .loc 1 4867 3 view .LVU3753 + 11139 0052 0020 movs r0, #0 + 11140 0054 84F84000 strb r0, [r4, #64] +4867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11141 .loc 1 4867 3 view .LVU3754 +4869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11142 .loc 1 4869 3 view .LVU3755 + 11143 .LVL727: + 11144 .L685: +4870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11145 .loc 1 4870 1 is_stmt 0 view .LVU3756 + 11146 0058 F8BD pop {r3, r4, r5, r6, r7, pc} + 11147 .LVL728: + 11148 .L698: +4759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11149 .loc 1 4759 5 is_stmt 1 view .LVU3757 + 11150 005a FFF7FEFF bl I2C_ITSlaveCplt + 11151 .LVL729: +4759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11152 .loc 1 4759 5 is_stmt 0 view .LVU3758 + 11153 005e E2E7 b .L686 + 11154 .L699: +4770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11155 .loc 1 4770 49 discriminator 1 view .LVU3759 + 11156 0060 B7F1007F cmp r7, #33554432 + 11157 0064 EDD1 bne .L689 + ARM GAS /tmp/ccEimIdZ.s page 375 + + +4773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11158 .loc 1 4773 9 is_stmt 1 view .LVU3760 + 11159 0066 2946 mov r1, r5 + 11160 0068 2046 mov r0, r4 + 11161 006a FFF7FEFF bl I2C_ITListenCplt + 11162 .LVL730: + 11163 006e F0E7 b .L690 + 11164 .L700: +4775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11165 .loc 1 4775 62 is_stmt 0 discriminator 1 view .LVU3761 + 11166 0070 17F5803F cmn r7, #65536 + 11167 0074 EAD0 beq .L691 +4778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11168 .loc 1 4778 9 is_stmt 1 view .LVU3762 + 11169 0076 2368 ldr r3, [r4] + 11170 0078 1022 movs r2, #16 + 11171 007a DA61 str r2, [r3, #28] +4781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11172 .loc 1 4781 9 view .LVU3763 + 11173 007c 2046 mov r0, r4 + 11174 007e FFF7FEFF bl I2C_Flush_TXDR + 11175 .LVL731: +4785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11176 .loc 1 4785 9 view .LVU3764 + 11177 0082 2046 mov r0, r4 + 11178 0084 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11179 .LVL732: + 11180 0088 E3E7 b .L690 + 11181 .L688: +4797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11182 .loc 1 4797 7 view .LVU3765 + 11183 008a 2368 ldr r3, [r4] + 11184 008c 1022 movs r2, #16 + 11185 008e DA61 str r2, [r3, #28] +4800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11186 .loc 1 4800 7 view .LVU3766 +4800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11187 .loc 1 4800 23 is_stmt 0 view .LVU3767 + 11188 0090 636C ldr r3, [r4, #68] + 11189 0092 43F00403 orr r3, r3, #4 + 11190 0096 6364 str r3, [r4, #68] +4802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11191 .loc 1 4802 7 is_stmt 1 view .LVU3768 +4802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11192 .loc 1 4802 10 is_stmt 0 view .LVU3769 + 11193 0098 B7F1807F cmp r7, #16777216 + 11194 009c 18BF it ne + 11195 009e 002F cmpne r7, #0 + 11196 00a0 D7D1 bne .L690 +4805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11197 .loc 1 4805 9 is_stmt 1 view .LVU3770 + 11198 00a2 616C ldr r1, [r4, #68] + 11199 00a4 2046 mov r0, r4 + 11200 00a6 FFF7FEFF bl I2C_ITError + 11201 .LVL733: + 11202 00aa D2E7 b .L690 + 11203 .L687: + ARM GAS /tmp/ccEimIdZ.s page 376 + + +4809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11204 .loc 1 4809 8 view .LVU3771 +4809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11205 .loc 1 4809 11 is_stmt 0 view .LVU3772 + 11206 00ac 15F0040F tst r5, #4 + 11207 00b0 1FD0 beq .L692 +4809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11208 .loc 1 4809 65 discriminator 1 view .LVU3773 + 11209 00b2 16F0040F tst r6, #4 + 11210 00b6 1CD0 beq .L692 +4811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11211 .loc 1 4811 5 is_stmt 1 view .LVU3774 +4811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11212 .loc 1 4811 13 is_stmt 0 view .LVU3775 + 11213 00b8 638D ldrh r3, [r4, #42] + 11214 00ba 9BB2 uxth r3, r3 +4811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11215 .loc 1 4811 8 view .LVU3776 + 11216 00bc 73B1 cbz r3, .L693 +4814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11217 .loc 1 4814 7 is_stmt 1 view .LVU3777 +4814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11218 .loc 1 4814 38 is_stmt 0 view .LVU3778 + 11219 00be 2368 ldr r3, [r4] +4814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11220 .loc 1 4814 48 view .LVU3779 + 11221 00c0 5A6A ldr r2, [r3, #36] +4814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11222 .loc 1 4814 12 view .LVU3780 + 11223 00c2 636A ldr r3, [r4, #36] +4814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11224 .loc 1 4814 23 view .LVU3781 + 11225 00c4 1A70 strb r2, [r3] +4817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11226 .loc 1 4817 7 is_stmt 1 view .LVU3782 +4817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11227 .loc 1 4817 11 is_stmt 0 view .LVU3783 + 11228 00c6 636A ldr r3, [r4, #36] +4817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11229 .loc 1 4817 21 view .LVU3784 + 11230 00c8 0133 adds r3, r3, #1 + 11231 00ca 6362 str r3, [r4, #36] +4819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11232 .loc 1 4819 7 is_stmt 1 view .LVU3785 +4819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11233 .loc 1 4819 11 is_stmt 0 view .LVU3786 + 11234 00cc 238D ldrh r3, [r4, #40] +4819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11235 .loc 1 4819 21 view .LVU3787 + 11236 00ce 013B subs r3, r3, #1 + 11237 00d0 2385 strh r3, [r4, #40] @ movhi +4820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11238 .loc 1 4820 7 is_stmt 1 view .LVU3788 +4820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11239 .loc 1 4820 11 is_stmt 0 view .LVU3789 + 11240 00d2 638D ldrh r3, [r4, #42] + 11241 00d4 9BB2 uxth r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 377 + + +4820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11242 .loc 1 4820 22 view .LVU3790 + 11243 00d6 013B subs r3, r3, #1 + 11244 00d8 9BB2 uxth r3, r3 + 11245 00da 6385 strh r3, [r4, #42] @ movhi + 11246 .L693: +4823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11247 .loc 1 4823 5 is_stmt 1 view .LVU3791 +4823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11248 .loc 1 4823 14 is_stmt 0 view .LVU3792 + 11249 00dc 638D ldrh r3, [r4, #42] + 11250 00de 9BB2 uxth r3, r3 +4823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11251 .loc 1 4823 8 view .LVU3793 + 11252 00e0 002B cmp r3, #0 + 11253 00e2 B6D1 bne .L690 +4823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11254 .loc 1 4823 33 discriminator 1 view .LVU3794 + 11255 00e4 17F5803F cmn r7, #65536 + 11256 00e8 B3D0 beq .L690 +4827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11257 .loc 1 4827 7 is_stmt 1 view .LVU3795 + 11258 00ea 2046 mov r0, r4 + 11259 00ec FFF7FEFF bl I2C_ITSlaveSeqCplt + 11260 .LVL734: + 11261 00f0 AFE7 b .L690 + 11262 .L692: +4830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11263 .loc 1 4830 8 view .LVU3796 +4830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11264 .loc 1 4830 11 is_stmt 0 view .LVU3797 + 11265 00f2 15F0080F tst r5, #8 + 11266 00f6 02D0 beq .L694 +4830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11267 .loc 1 4830 65 discriminator 1 view .LVU3798 + 11268 00f8 16F0080F tst r6, #8 + 11269 00fc 18D1 bne .L701 + 11270 .L694: +4834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11271 .loc 1 4834 8 is_stmt 1 view .LVU3799 +4834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11272 .loc 1 4834 11 is_stmt 0 view .LVU3800 + 11273 00fe 15F0020F tst r5, #2 + 11274 0102 A6D0 beq .L690 +4834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11275 .loc 1 4834 65 discriminator 1 view .LVU3801 + 11276 0104 16F0020F tst r6, #2 + 11277 0108 A3D0 beq .L690 +4840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11278 .loc 1 4840 5 is_stmt 1 view .LVU3802 +4840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11279 .loc 1 4840 13 is_stmt 0 view .LVU3803 + 11280 010a 638D ldrh r3, [r4, #42] + 11281 010c 9BB2 uxth r3, r3 +4840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11282 .loc 1 4840 8 view .LVU3804 + 11283 010e A3B1 cbz r3, .L695 + ARM GAS /tmp/ccEimIdZ.s page 378 + + +4843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11284 .loc 1 4843 7 is_stmt 1 view .LVU3805 +4843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11285 .loc 1 4843 35 is_stmt 0 view .LVU3806 + 11286 0110 626A ldr r2, [r4, #36] +4843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11287 .loc 1 4843 11 view .LVU3807 + 11288 0112 2368 ldr r3, [r4] +4843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11289 .loc 1 4843 30 view .LVU3808 + 11290 0114 1278 ldrb r2, [r2] @ zero_extendqisi2 +4843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11291 .loc 1 4843 28 view .LVU3809 + 11292 0116 9A62 str r2, [r3, #40] +4846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11293 .loc 1 4846 7 is_stmt 1 view .LVU3810 +4846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11294 .loc 1 4846 11 is_stmt 0 view .LVU3811 + 11295 0118 636A ldr r3, [r4, #36] +4846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11296 .loc 1 4846 21 view .LVU3812 + 11297 011a 0133 adds r3, r3, #1 + 11298 011c 6362 str r3, [r4, #36] +4848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 11299 .loc 1 4848 7 is_stmt 1 view .LVU3813 +4848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 11300 .loc 1 4848 11 is_stmt 0 view .LVU3814 + 11301 011e 638D ldrh r3, [r4, #42] + 11302 0120 9BB2 uxth r3, r3 +4848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferSize--; + 11303 .loc 1 4848 22 view .LVU3815 + 11304 0122 013B subs r3, r3, #1 + 11305 0124 9BB2 uxth r3, r3 + 11306 0126 6385 strh r3, [r4, #42] @ movhi +4849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11307 .loc 1 4849 7 is_stmt 1 view .LVU3816 +4849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11308 .loc 1 4849 11 is_stmt 0 view .LVU3817 + 11309 0128 238D ldrh r3, [r4, #40] +4849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11310 .loc 1 4849 21 view .LVU3818 + 11311 012a 013B subs r3, r3, #1 + 11312 012c 2385 strh r3, [r4, #40] @ movhi + 11313 012e 90E7 b .L690 + 11314 .L701: +4832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11315 .loc 1 4832 5 is_stmt 1 view .LVU3819 + 11316 0130 2946 mov r1, r5 + 11317 0132 2046 mov r0, r4 + 11318 0134 FFF7FEFF bl I2C_ITAddrCplt + 11319 .LVL735: + 11320 0138 8BE7 b .L690 + 11321 .L695: +4853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11322 .loc 1 4853 7 view .LVU3820 +4853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11323 .loc 1 4853 10 is_stmt 0 view .LVU3821 + ARM GAS /tmp/ccEimIdZ.s page 379 + + + 11324 013a 002F cmp r7, #0 + 11325 013c 18BF it ne + 11326 013e B7F1807F cmpne r7, #16777216 + 11327 0142 86D1 bne .L690 +4857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11328 .loc 1 4857 9 is_stmt 1 view .LVU3822 + 11329 0144 2046 mov r0, r4 + 11330 0146 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11331 .LVL736: + 11332 014a 82E7 b .L690 + 11333 .LVL737: + 11334 .L696: +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11335 .loc 1 4753 3 is_stmt 0 view .LVU3823 + 11336 014c 0220 movs r0, #2 + 11337 .LVL738: +4753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11338 .loc 1 4753 3 view .LVU3824 + 11339 014e 83E7 b .L685 + 11340 .cfi_endproc + 11341 .LFE191: + 11343 .section .text.I2C_ITMasterCplt,"ax",%progbits + 11344 .align 1 + 11345 .syntax unified + 11346 .thumb + 11347 .thumb_func + 11348 .fpu fpv5-d16 + 11350 I2C_ITMasterCplt: + 11351 .LVL739: + 11352 .LFB199: +5477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmperror; + 11353 .loc 1 5477 1 is_stmt 1 view -0 + 11354 .cfi_startproc + 11355 @ args = 0, pretend = 0, frame = 8 + 11356 @ frame_needed = 0, uses_anonymous_args = 0 +5477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmperror; + 11357 .loc 1 5477 1 is_stmt 0 view .LVU3826 + 11358 0000 30B5 push {r4, r5, lr} + 11359 .LCFI122: + 11360 .cfi_def_cfa_offset 12 + 11361 .cfi_offset 4, -12 + 11362 .cfi_offset 5, -8 + 11363 .cfi_offset 14, -4 + 11364 0002 83B0 sub sp, sp, #12 + 11365 .LCFI123: + 11366 .cfi_def_cfa_offset 24 + 11367 0004 0446 mov r4, r0 + 11368 0006 0D46 mov r5, r1 +5478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11369 .loc 1 5478 3 is_stmt 1 view .LVU3827 +5479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** __IO uint32_t tmpreg; + 11370 .loc 1 5479 3 view .LVU3828 + 11371 .LVL740: +5480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11372 .loc 1 5480 3 view .LVU3829 +5483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11373 .loc 1 5483 3 view .LVU3830 + ARM GAS /tmp/ccEimIdZ.s page 380 + + + 11374 0008 0368 ldr r3, [r0] + 11375 000a 2022 movs r2, #32 + 11376 000c DA61 str r2, [r3, #28] +5486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11377 .loc 1 5486 3 view .LVU3831 +5486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11378 .loc 1 5486 11 is_stmt 0 view .LVU3832 + 11379 000e 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11380 0012 DBB2 uxtb r3, r3 +5486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11381 .loc 1 5486 6 view .LVU3833 + 11382 0014 212B cmp r3, #33 + 11383 0016 33D0 beq .L714 +5491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11384 .loc 1 5491 8 is_stmt 1 view .LVU3834 +5491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11385 .loc 1 5491 16 is_stmt 0 view .LVU3835 + 11386 0018 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11387 001c DBB2 uxtb r3, r3 +5491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11388 .loc 1 5491 11 view .LVU3836 + 11389 001e 222B cmp r3, #34 + 11390 0020 34D0 beq .L715 + 11391 .LVL741: + 11392 .L704: +5499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11393 .loc 1 5499 3 is_stmt 1 view .LVU3837 +5502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11394 .loc 1 5502 3 view .LVU3838 + 11395 0022 2268 ldr r2, [r4] + 11396 0024 5368 ldr r3, [r2, #4] + 11397 0026 23F0FF73 bic r3, r3, #33423360 + 11398 002a 23F48B33 bic r3, r3, #71168 + 11399 002e 23F4FF73 bic r3, r3, #510 + 11400 0032 23F00103 bic r3, r3, #1 + 11401 0036 5360 str r3, [r2, #4] +5505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11402 .loc 1 5505 3 view .LVU3839 +5505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11403 .loc 1 5505 23 is_stmt 0 view .LVU3840 + 11404 0038 0023 movs r3, #0 + 11405 003a 6363 str r3, [r4, #52] +5506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11406 .loc 1 5506 3 is_stmt 1 view .LVU3841 +5506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11407 .loc 1 5506 23 is_stmt 0 view .LVU3842 + 11408 003c A3F58033 sub r3, r3, #65536 + 11409 0040 E362 str r3, [r4, #44] +5508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11410 .loc 1 5508 3 is_stmt 1 view .LVU3843 +5508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11411 .loc 1 5508 6 is_stmt 0 view .LVU3844 + 11412 0042 15F0100F tst r5, #16 + 11413 0046 06D0 beq .L705 +5511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11414 .loc 1 5511 5 is_stmt 1 view .LVU3845 + 11415 0048 2368 ldr r3, [r4] + ARM GAS /tmp/ccEimIdZ.s page 381 + + + 11416 004a 1022 movs r2, #16 + 11417 004c DA61 str r2, [r3, #28] +5514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11418 .loc 1 5514 5 view .LVU3846 +5514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11419 .loc 1 5514 21 is_stmt 0 view .LVU3847 + 11420 004e 636C ldr r3, [r4, #68] + 11421 0050 43F00403 orr r3, r3, #4 + 11422 0054 6364 str r3, [r4, #68] + 11423 .L705: +5518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11424 .loc 1 5518 3 is_stmt 1 view .LVU3848 +5518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11425 .loc 1 5518 12 is_stmt 0 view .LVU3849 + 11426 0056 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11427 005a DBB2 uxtb r3, r3 +5518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11428 .loc 1 5518 6 view .LVU3850 + 11429 005c 602B cmp r3, #96 + 11430 005e 1BD0 beq .L716 + 11431 .L706: +5526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11432 .loc 1 5526 3 is_stmt 1 view .LVU3851 + 11433 0060 2046 mov r0, r4 + 11434 0062 FFF7FEFF bl I2C_Flush_TXDR + 11435 .LVL742: +5529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11436 .loc 1 5529 3 view .LVU3852 +5529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11437 .loc 1 5529 12 is_stmt 0 view .LVU3853 + 11438 0066 626C ldr r2, [r4, #68] + 11439 .LVL743: +5532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11440 .loc 1 5532 3 is_stmt 1 view .LVU3854 +5532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11441 .loc 1 5532 12 is_stmt 0 view .LVU3855 + 11442 0068 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11443 006c DBB2 uxtb r3, r3 +5532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11444 .loc 1 5532 6 view .LVU3856 + 11445 006e 602B cmp r3, #96 + 11446 0070 00D0 beq .L707 +5532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11447 .loc 1 5532 44 discriminator 1 view .LVU3857 + 11448 0072 D2B1 cbz r2, .L708 + 11449 .L707: +5535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11450 .loc 1 5535 5 is_stmt 1 view .LVU3858 + 11451 0074 616C ldr r1, [r4, #68] + 11452 0076 2046 mov r0, r4 + 11453 0078 FFF7FEFF bl I2C_ITError + 11454 .LVL744: + 11455 .L702: +5611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11456 .loc 1 5611 1 is_stmt 0 view .LVU3859 + 11457 007c 03B0 add sp, sp, #12 + 11458 .LCFI124: + ARM GAS /tmp/ccEimIdZ.s page 382 + + + 11459 .cfi_remember_state + 11460 .cfi_def_cfa_offset 12 + 11461 @ sp needed + 11462 007e 30BD pop {r4, r5, pc} + 11463 .LVL745: + 11464 .L714: + 11465 .LCFI125: + 11466 .cfi_restore_state +5488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 11467 .loc 1 5488 5 is_stmt 1 view .LVU3860 + 11468 0080 0121 movs r1, #1 + 11469 .LVL746: +5488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 11470 .loc 1 5488 5 is_stmt 0 view .LVU3861 + 11471 0082 FFF7FEFF bl I2C_Disable_IRQ + 11472 .LVL747: +5489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11473 .loc 1 5489 5 is_stmt 1 view .LVU3862 +5489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11474 .loc 1 5489 25 is_stmt 0 view .LVU3863 + 11475 0086 1123 movs r3, #17 + 11476 0088 2363 str r3, [r4, #48] + 11477 008a CAE7 b .L704 + 11478 .LVL748: + 11479 .L715: +5493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 11480 .loc 1 5493 5 is_stmt 1 view .LVU3864 + 11481 008c 0221 movs r1, #2 + 11482 .LVL749: +5493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 11483 .loc 1 5493 5 is_stmt 0 view .LVU3865 + 11484 008e FFF7FEFF bl I2C_Disable_IRQ + 11485 .LVL750: +5494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11486 .loc 1 5494 5 is_stmt 1 view .LVU3866 +5494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11487 .loc 1 5494 25 is_stmt 0 view .LVU3867 + 11488 0092 1223 movs r3, #18 + 11489 0094 2363 str r3, [r4, #48] + 11490 0096 C4E7 b .L704 + 11491 .L716: +5518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11492 .loc 1 5518 44 discriminator 1 view .LVU3868 + 11493 0098 15F0040F tst r5, #4 + 11494 009c E0D0 beq .L706 +5521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(tmpreg); + 11495 .loc 1 5521 5 is_stmt 1 view .LVU3869 +5521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(tmpreg); + 11496 .loc 1 5521 27 is_stmt 0 view .LVU3870 + 11497 009e 2368 ldr r3, [r4] +5521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(tmpreg); + 11498 .loc 1 5521 37 view .LVU3871 + 11499 00a0 5B6A ldr r3, [r3, #36] + 11500 00a2 DBB2 uxtb r3, r3 +5521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** UNUSED(tmpreg); + 11501 .loc 1 5521 12 view .LVU3872 + 11502 00a4 0193 str r3, [sp, #4] + ARM GAS /tmp/ccEimIdZ.s page 383 + + +5522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11503 .loc 1 5522 5 is_stmt 1 view .LVU3873 + 11504 00a6 019B ldr r3, [sp, #4] + 11505 00a8 DAE7 b .L706 + 11506 .LVL751: + 11507 .L708: +5538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11508 .loc 1 5538 8 view .LVU3874 +5538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11509 .loc 1 5538 16 is_stmt 0 view .LVU3875 + 11510 00aa 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11511 00ae DBB2 uxtb r3, r3 +5538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11512 .loc 1 5538 11 view .LVU3876 + 11513 00b0 212B cmp r3, #33 + 11514 00b2 17D0 beq .L717 +5573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11515 .loc 1 5573 8 is_stmt 1 view .LVU3877 +5573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11516 .loc 1 5573 16 is_stmt 0 view .LVU3878 + 11517 00b4 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11518 00b8 DBB2 uxtb r3, r3 +5573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11519 .loc 1 5573 11 view .LVU3879 + 11520 00ba 222B cmp r3, #34 + 11521 00bc DED1 bne .L702 +5575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11522 .loc 1 5575 5 is_stmt 1 view .LVU3880 +5575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11523 .loc 1 5575 17 is_stmt 0 view .LVU3881 + 11524 00be 2023 movs r3, #32 + 11525 00c0 84F84130 strb r3, [r4, #65] +5576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11526 .loc 1 5576 5 is_stmt 1 view .LVU3882 +5576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11527 .loc 1 5576 25 is_stmt 0 view .LVU3883 + 11528 00c4 0023 movs r3, #0 + 11529 00c6 2363 str r3, [r4, #48] +5578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11530 .loc 1 5578 5 is_stmt 1 view .LVU3884 +5578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11531 .loc 1 5578 13 is_stmt 0 view .LVU3885 + 11532 00c8 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 11533 00cc DBB2 uxtb r3, r3 +5578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11534 .loc 1 5578 8 view .LVU3886 + 11535 00ce 402B cmp r3, #64 + 11536 00d0 24D0 beq .L718 +5594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11537 .loc 1 5594 7 is_stmt 1 view .LVU3887 +5594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11538 .loc 1 5594 18 is_stmt 0 view .LVU3888 + 11539 00d2 0023 movs r3, #0 + 11540 00d4 84F84230 strb r3, [r4, #66] +5597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11541 .loc 1 5597 7 is_stmt 1 view .LVU3889 +5597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 384 + + + 11542 .loc 1 5597 7 view .LVU3890 + 11543 00d8 84F84030 strb r3, [r4, #64] +5597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11544 .loc 1 5597 7 view .LVU3891 +5603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11545 .loc 1 5603 7 view .LVU3892 + 11546 00dc 2046 mov r0, r4 + 11547 00de FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 11548 .LVL752: +5610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11549 .loc 1 5610 3 view .LVU3893 +5611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11550 .loc 1 5611 1 is_stmt 0 view .LVU3894 + 11551 00e2 CBE7 b .L702 + 11552 .LVL753: + 11553 .L717: +5540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11554 .loc 1 5540 5 is_stmt 1 view .LVU3895 +5540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11555 .loc 1 5540 17 is_stmt 0 view .LVU3896 + 11556 00e4 2023 movs r3, #32 + 11557 00e6 84F84130 strb r3, [r4, #65] +5541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11558 .loc 1 5541 5 is_stmt 1 view .LVU3897 +5541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11559 .loc 1 5541 25 is_stmt 0 view .LVU3898 + 11560 00ea 0023 movs r3, #0 + 11561 00ec 2363 str r3, [r4, #48] +5543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11562 .loc 1 5543 5 is_stmt 1 view .LVU3899 +5543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11563 .loc 1 5543 13 is_stmt 0 view .LVU3900 + 11564 00ee 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 11565 00f2 DBB2 uxtb r3, r3 +5543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11566 .loc 1 5543 8 view .LVU3901 + 11567 00f4 402B cmp r3, #64 + 11568 00f6 08D0 beq .L719 +5559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11569 .loc 1 5559 7 is_stmt 1 view .LVU3902 +5559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11570 .loc 1 5559 18 is_stmt 0 view .LVU3903 + 11571 00f8 0023 movs r3, #0 + 11572 00fa 84F84230 strb r3, [r4, #66] +5562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11573 .loc 1 5562 7 is_stmt 1 view .LVU3904 +5562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11574 .loc 1 5562 7 view .LVU3905 + 11575 00fe 84F84030 strb r3, [r4, #64] +5562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11576 .loc 1 5562 7 view .LVU3906 +5568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11577 .loc 1 5568 7 view .LVU3907 + 11578 0102 2046 mov r0, r4 + 11579 0104 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 11580 .LVL754: +5568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccEimIdZ.s page 385 + + + 11581 .loc 1 5568 7 is_stmt 0 view .LVU3908 + 11582 0108 B8E7 b .L702 + 11583 .LVL755: + 11584 .L719: +5545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11585 .loc 1 5545 7 is_stmt 1 view .LVU3909 +5545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11586 .loc 1 5545 18 is_stmt 0 view .LVU3910 + 11587 010a 0023 movs r3, #0 + 11588 010c 84F84230 strb r3, [r4, #66] +5548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11589 .loc 1 5548 7 is_stmt 1 view .LVU3911 +5548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11590 .loc 1 5548 7 view .LVU3912 + 11591 0110 84F84030 strb r3, [r4, #64] +5548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11592 .loc 1 5548 7 view .LVU3913 +5554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11593 .loc 1 5554 7 view .LVU3914 + 11594 0114 2046 mov r0, r4 + 11595 0116 FFF7FEFF bl HAL_I2C_MemTxCpltCallback + 11596 .LVL756: +5554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11597 .loc 1 5554 7 is_stmt 0 view .LVU3915 + 11598 011a AFE7 b .L702 + 11599 .LVL757: + 11600 .L718: +5580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11601 .loc 1 5580 7 is_stmt 1 view .LVU3916 +5580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11602 .loc 1 5580 18 is_stmt 0 view .LVU3917 + 11603 011c 0023 movs r3, #0 + 11604 011e 84F84230 strb r3, [r4, #66] +5583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11605 .loc 1 5583 7 is_stmt 1 view .LVU3918 +5583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11606 .loc 1 5583 7 view .LVU3919 + 11607 0122 84F84030 strb r3, [r4, #64] +5583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11608 .loc 1 5583 7 view .LVU3920 +5589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11609 .loc 1 5589 7 view .LVU3921 + 11610 0126 2046 mov r0, r4 + 11611 0128 FFF7FEFF bl HAL_I2C_MemRxCpltCallback + 11612 .LVL758: +5589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11613 .loc 1 5589 7 is_stmt 0 view .LVU3922 + 11614 012c A6E7 b .L702 + 11615 .cfi_endproc + 11616 .LFE199: + 11618 .section .text.I2C_Master_ISR_IT,"ax",%progbits + 11619 .align 1 + 11620 .syntax unified + 11621 .thumb + 11622 .thumb_func + 11623 .fpu fpv5-d16 + 11625 I2C_Master_ISR_IT: + ARM GAS /tmp/ccEimIdZ.s page 386 + + + 11626 .LVL759: + 11627 .LFB190: +4611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t devaddress; + 11628 .loc 1 4611 1 is_stmt 1 view -0 + 11629 .cfi_startproc + 11630 @ args = 0, pretend = 0, frame = 0 + 11631 @ frame_needed = 0, uses_anonymous_args = 0 +4612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11632 .loc 1 4612 3 view .LVU3924 +4613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11633 .loc 1 4613 3 view .LVU3925 +4616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11634 .loc 1 4616 3 view .LVU3926 +4616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11635 .loc 1 4616 3 view .LVU3927 + 11636 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 11637 0004 012B cmp r3, #1 + 11638 0006 00F0B980 beq .L734 +4611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t devaddress; + 11639 .loc 1 4611 1 is_stmt 0 discriminator 2 view .LVU3928 + 11640 000a 70B5 push {r4, r5, r6, lr} + 11641 .LCFI126: + 11642 .cfi_def_cfa_offset 16 + 11643 .cfi_offset 4, -16 + 11644 .cfi_offset 5, -12 + 11645 .cfi_offset 6, -8 + 11646 .cfi_offset 14, -4 + 11647 000c 82B0 sub sp, sp, #8 + 11648 .LCFI127: + 11649 .cfi_def_cfa_offset 24 + 11650 000e 0446 mov r4, r0 + 11651 0010 0D46 mov r5, r1 + 11652 0012 1646 mov r6, r2 +4616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11653 .loc 1 4616 3 is_stmt 1 discriminator 2 view .LVU3929 + 11654 0014 0123 movs r3, #1 + 11655 0016 80F84030 strb r3, [r0, #64] +4616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11656 .loc 1 4616 3 discriminator 2 view .LVU3930 +4618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11657 .loc 1 4618 3 discriminator 2 view .LVU3931 +4618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11658 .loc 1 4618 6 is_stmt 0 discriminator 2 view .LVU3932 + 11659 001a 11F0100F tst r1, #16 + 11660 001e 02D0 beq .L722 +4618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11661 .loc 1 4618 58 discriminator 1 view .LVU3933 + 11662 0020 12F0100F tst r2, #16 + 11663 0024 22D1 bne .L739 + 11664 .L722: +4631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11665 .loc 1 4631 8 is_stmt 1 view .LVU3934 +4631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11666 .loc 1 4631 11 is_stmt 0 view .LVU3935 + 11667 0026 15F0040F tst r5, #4 + 11668 002a 29D0 beq .L724 +4631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 387 + + + 11669 .loc 1 4631 65 discriminator 1 view .LVU3936 + 11670 002c 16F0040F tst r6, #4 + 11671 0030 26D0 beq .L724 +4634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11672 .loc 1 4634 5 is_stmt 1 view .LVU3937 +4634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11673 .loc 1 4634 16 is_stmt 0 view .LVU3938 + 11674 0032 25F00405 bic r5, r5, #4 + 11675 .LVL760: +4637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11676 .loc 1 4637 5 is_stmt 1 view .LVU3939 +4637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11677 .loc 1 4637 36 is_stmt 0 view .LVU3940 + 11678 0036 2368 ldr r3, [r4] +4637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11679 .loc 1 4637 46 view .LVU3941 + 11680 0038 5A6A ldr r2, [r3, #36] + 11681 .LVL761: +4637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11682 .loc 1 4637 10 view .LVU3942 + 11683 003a 636A ldr r3, [r4, #36] +4637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11684 .loc 1 4637 21 view .LVU3943 + 11685 003c 1A70 strb r2, [r3] +4640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11686 .loc 1 4640 5 is_stmt 1 view .LVU3944 +4640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11687 .loc 1 4640 9 is_stmt 0 view .LVU3945 + 11688 003e 636A ldr r3, [r4, #36] +4640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11689 .loc 1 4640 19 view .LVU3946 + 11690 0040 0133 adds r3, r3, #1 + 11691 0042 6362 str r3, [r4, #36] +4642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11692 .loc 1 4642 5 is_stmt 1 view .LVU3947 +4642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11693 .loc 1 4642 9 is_stmt 0 view .LVU3948 + 11694 0044 238D ldrh r3, [r4, #40] +4642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11695 .loc 1 4642 19 view .LVU3949 + 11696 0046 013B subs r3, r3, #1 + 11697 0048 2385 strh r3, [r4, #40] @ movhi +4643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11698 .loc 1 4643 5 is_stmt 1 view .LVU3950 +4643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11699 .loc 1 4643 9 is_stmt 0 view .LVU3951 + 11700 004a 638D ldrh r3, [r4, #42] + 11701 004c 9BB2 uxth r3, r3 +4643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11702 .loc 1 4643 20 view .LVU3952 + 11703 004e 013B subs r3, r3, #1 + 11704 0050 9BB2 uxth r3, r3 + 11705 0052 6385 strh r3, [r4, #42] @ movhi + 11706 .LVL762: + 11707 .L723: +4725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11708 .loc 1 4725 3 is_stmt 1 view .LVU3953 + ARM GAS /tmp/ccEimIdZ.s page 388 + + +4727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11709 .loc 1 4727 3 view .LVU3954 +4727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11710 .loc 1 4727 6 is_stmt 0 view .LVU3955 + 11711 0054 15F0200F tst r5, #32 + 11712 0058 03D0 beq .L733 +4727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11713 .loc 1 4727 61 discriminator 1 view .LVU3956 + 11714 005a 16F0200F tst r6, #32 + 11715 005e 40F08880 bne .L740 + 11716 .L733: +4734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11717 .loc 1 4734 3 is_stmt 1 view .LVU3957 +4734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11718 .loc 1 4734 3 view .LVU3958 + 11719 0062 0020 movs r0, #0 + 11720 0064 84F84000 strb r0, [r4, #64] +4734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11721 .loc 1 4734 3 view .LVU3959 +4736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11722 .loc 1 4736 3 view .LVU3960 +4737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11723 .loc 1 4737 1 is_stmt 0 view .LVU3961 + 11724 0068 02B0 add sp, sp, #8 + 11725 .LCFI128: + 11726 .cfi_remember_state + 11727 .cfi_def_cfa_offset 16 + 11728 @ sp needed + 11729 006a 70BD pop {r4, r5, r6, pc} + 11730 .LVL763: + 11731 .L739: + 11732 .LCFI129: + 11733 .cfi_restore_state +4621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11734 .loc 1 4621 5 is_stmt 1 view .LVU3962 + 11735 006c 0368 ldr r3, [r0] + 11736 006e 1022 movs r2, #16 + 11737 .LVL764: +4621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11738 .loc 1 4621 5 is_stmt 0 view .LVU3963 + 11739 0070 DA61 str r2, [r3, #28] +4626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11740 .loc 1 4626 5 is_stmt 1 view .LVU3964 +4626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11741 .loc 1 4626 21 is_stmt 0 view .LVU3965 + 11742 0072 436C ldr r3, [r0, #68] + 11743 0074 43F00403 orr r3, r3, #4 + 11744 0078 4364 str r3, [r0, #68] +4629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11745 .loc 1 4629 5 is_stmt 1 view .LVU3966 + 11746 007a FFF7FEFF bl I2C_Flush_TXDR + 11747 .LVL765: +4629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11748 .loc 1 4629 5 is_stmt 0 view .LVU3967 + 11749 007e E9E7 b .L723 + 11750 .LVL766: + 11751 .L724: + ARM GAS /tmp/ccEimIdZ.s page 389 + + +4645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11752 .loc 1 4645 8 is_stmt 1 view .LVU3968 +4645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11753 .loc 1 4645 11 is_stmt 0 view .LVU3969 + 11754 0080 15F0020F tst r5, #2 + 11755 0084 12D0 beq .L725 +4645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11756 .loc 1 4645 65 discriminator 1 view .LVU3970 + 11757 0086 16F0020F tst r6, #2 + 11758 008a 0FD0 beq .L725 +4648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11759 .loc 1 4648 5 is_stmt 1 view .LVU3971 +4648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11760 .loc 1 4648 33 is_stmt 0 view .LVU3972 + 11761 008c 626A ldr r2, [r4, #36] + 11762 .LVL767: +4648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11763 .loc 1 4648 9 view .LVU3973 + 11764 008e 2368 ldr r3, [r4] +4648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11765 .loc 1 4648 28 view .LVU3974 + 11766 0090 1278 ldrb r2, [r2] @ zero_extendqisi2 +4648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11767 .loc 1 4648 26 view .LVU3975 + 11768 0092 9A62 str r2, [r3, #40] +4651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11769 .loc 1 4651 5 is_stmt 1 view .LVU3976 +4651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11770 .loc 1 4651 9 is_stmt 0 view .LVU3977 + 11771 0094 636A ldr r3, [r4, #36] +4651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11772 .loc 1 4651 19 view .LVU3978 + 11773 0096 0133 adds r3, r3, #1 + 11774 0098 6362 str r3, [r4, #36] +4653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11775 .loc 1 4653 5 is_stmt 1 view .LVU3979 +4653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11776 .loc 1 4653 9 is_stmt 0 view .LVU3980 + 11777 009a 238D ldrh r3, [r4, #40] +4653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** hi2c->XferCount--; + 11778 .loc 1 4653 19 view .LVU3981 + 11779 009c 013B subs r3, r3, #1 + 11780 009e 2385 strh r3, [r4, #40] @ movhi +4654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11781 .loc 1 4654 5 is_stmt 1 view .LVU3982 +4654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11782 .loc 1 4654 9 is_stmt 0 view .LVU3983 + 11783 00a0 638D ldrh r3, [r4, #42] + 11784 00a2 9BB2 uxth r3, r3 +4654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11785 .loc 1 4654 20 view .LVU3984 + 11786 00a4 013B subs r3, r3, #1 + 11787 00a6 9BB2 uxth r3, r3 + 11788 00a8 6385 strh r3, [r4, #42] @ movhi + 11789 00aa D3E7 b .L723 + 11790 .LVL768: + 11791 .L725: + ARM GAS /tmp/ccEimIdZ.s page 390 + + +4656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11792 .loc 1 4656 8 is_stmt 1 view .LVU3985 +4656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11793 .loc 1 4656 11 is_stmt 0 view .LVU3986 + 11794 00ac 15F0800F tst r5, #128 + 11795 00b0 3FD0 beq .L726 +4656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11796 .loc 1 4656 64 discriminator 1 view .LVU3987 + 11797 00b2 16F0400F tst r6, #64 + 11798 00b6 3CD0 beq .L726 +4658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11799 .loc 1 4658 5 is_stmt 1 view .LVU3988 +4658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11800 .loc 1 4658 14 is_stmt 0 view .LVU3989 + 11801 00b8 638D ldrh r3, [r4, #42] + 11802 00ba 9BB2 uxth r3, r3 +4658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11803 .loc 1 4658 8 view .LVU3990 + 11804 00bc 5BB3 cbz r3, .L727 +4658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11805 .loc 1 4658 41 discriminator 1 view .LVU3991 + 11806 00be 238D ldrh r3, [r4, #40] +4658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11807 .loc 1 4658 33 discriminator 1 view .LVU3992 + 11808 00c0 4BBB cbnz r3, .L727 +4660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11809 .loc 1 4660 7 is_stmt 1 view .LVU3993 +4660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11810 .loc 1 4660 35 is_stmt 0 view .LVU3994 + 11811 00c2 2368 ldr r3, [r4] +4660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11812 .loc 1 4660 45 view .LVU3995 + 11813 00c4 5968 ldr r1, [r3, #4] + 11814 .LVL769: +4660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11815 .loc 1 4660 18 view .LVU3996 + 11816 00c6 C1F30901 ubfx r1, r1, #0, #10 + 11817 .LVL770: +4662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11818 .loc 1 4662 7 is_stmt 1 view .LVU3997 +4662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11819 .loc 1 4662 15 is_stmt 0 view .LVU3998 + 11820 00ca 638D ldrh r3, [r4, #42] + 11821 00cc 9BB2 uxth r3, r3 +4662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11822 .loc 1 4662 10 view .LVU3999 + 11823 00ce FF2B cmp r3, #255 + 11824 00d0 0ED8 bhi .L741 +4669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11825 .loc 1 4669 9 is_stmt 1 view .LVU4000 +4669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11826 .loc 1 4669 30 is_stmt 0 view .LVU4001 + 11827 00d2 628D ldrh r2, [r4, #42] + 11828 .LVL771: +4669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11829 .loc 1 4669 30 view .LVU4002 + 11830 00d4 92B2 uxth r2, r2 + ARM GAS /tmp/ccEimIdZ.s page 391 + + +4669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11831 .loc 1 4669 24 view .LVU4003 + 11832 00d6 2285 strh r2, [r4, #40] @ movhi +4670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11833 .loc 1 4670 9 is_stmt 1 view .LVU4004 +4670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11834 .loc 1 4670 17 is_stmt 0 view .LVU4005 + 11835 00d8 E36A ldr r3, [r4, #44] +4670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11836 .loc 1 4670 12 view .LVU4006 + 11837 00da 13F5803F cmn r3, #65536 + 11838 00de 11D0 beq .L729 +4672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11839 .loc 1 4672 11 is_stmt 1 view .LVU4007 + 11840 00e0 E36A ldr r3, [r4, #44] + 11841 00e2 0020 movs r0, #0 + 11842 .LVL772: +4672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11843 .loc 1 4672 11 is_stmt 0 view .LVU4008 + 11844 00e4 0090 str r0, [sp] + 11845 00e6 D2B2 uxtb r2, r2 + 11846 00e8 2046 mov r0, r4 + 11847 00ea FFF7FEFF bl I2C_TransferConfig + 11848 .LVL773: +4672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11849 .loc 1 4672 11 view .LVU4009 + 11850 00ee B1E7 b .L723 + 11851 .LVL774: + 11852 .L741: +4664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 11853 .loc 1 4664 9 is_stmt 1 view .LVU4010 +4664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 11854 .loc 1 4664 24 is_stmt 0 view .LVU4011 + 11855 00f0 FF22 movs r2, #255 + 11856 .LVL775: +4664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 11857 .loc 1 4664 24 view .LVU4012 + 11858 00f2 2285 strh r2, [r4, #40] @ movhi +4665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11859 .loc 1 4665 9 is_stmt 1 view .LVU4013 + 11860 00f4 0023 movs r3, #0 + 11861 00f6 0093 str r3, [sp] + 11862 00f8 4FF08073 mov r3, #16777216 + 11863 00fc 2046 mov r0, r4 + 11864 .LVL776: +4665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11865 .loc 1 4665 9 is_stmt 0 view .LVU4014 + 11866 00fe FFF7FEFF bl I2C_TransferConfig + 11867 .LVL777: +4665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11868 .loc 1 4665 9 view .LVU4015 + 11869 0102 A7E7 b .L723 + 11870 .LVL778: + 11871 .L729: +4676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11872 .loc 1 4676 11 is_stmt 1 view .LVU4016 + 11873 0104 0023 movs r3, #0 + ARM GAS /tmp/ccEimIdZ.s page 392 + + + 11874 0106 0093 str r3, [sp] + 11875 0108 4FF00073 mov r3, #33554432 + 11876 010c D2B2 uxtb r2, r2 + 11877 010e 2046 mov r0, r4 + 11878 .LVL779: +4676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11879 .loc 1 4676 11 is_stmt 0 view .LVU4017 + 11880 0110 FFF7FEFF bl I2C_TransferConfig + 11881 .LVL780: +4676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11882 .loc 1 4676 11 view .LVU4018 + 11883 0114 9EE7 b .L723 + 11884 .LVL781: + 11885 .L727: +4683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11886 .loc 1 4683 7 is_stmt 1 view .LVU4019 +4683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11887 .loc 1 4683 11 is_stmt 0 view .LVU4020 + 11888 0116 2368 ldr r3, [r4] + 11889 0118 5B68 ldr r3, [r3, #4] +4683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11890 .loc 1 4683 10 view .LVU4021 + 11891 011a 13F0007F tst r3, #33554432 + 11892 011e 03D1 bne .L730 +4686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11893 .loc 1 4686 9 is_stmt 1 view .LVU4022 + 11894 0120 2046 mov r0, r4 + 11895 .LVL782: +4686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11896 .loc 1 4686 9 is_stmt 0 view .LVU4023 + 11897 0122 FFF7FEFF bl I2C_ITMasterSeqCplt + 11898 .LVL783: +4686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11899 .loc 1 4686 9 view .LVU4024 + 11900 0126 95E7 b .L723 + 11901 .LVL784: + 11902 .L730: +4692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11903 .loc 1 4692 9 is_stmt 1 view .LVU4025 + 11904 0128 4021 movs r1, #64 + 11905 .LVL785: +4692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11906 .loc 1 4692 9 is_stmt 0 view .LVU4026 + 11907 012a 2046 mov r0, r4 + 11908 .LVL786: +4692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11909 .loc 1 4692 9 view .LVU4027 + 11910 012c FFF7FEFF bl I2C_ITError + 11911 .LVL787: +4692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11912 .loc 1 4692 9 view .LVU4028 + 11913 0130 90E7 b .L723 + 11914 .LVL788: + 11915 .L726: +4696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11916 .loc 1 4696 8 is_stmt 1 view .LVU4029 +4696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 393 + + + 11917 .loc 1 4696 11 is_stmt 0 view .LVU4030 + 11918 0132 15F0400F tst r5, #64 + 11919 0136 8DD0 beq .L723 +4696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11920 .loc 1 4696 63 discriminator 1 view .LVU4031 + 11921 0138 16F0400F tst r6, #64 + 11922 013c 8AD0 beq .L723 +4698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11923 .loc 1 4698 5 is_stmt 1 view .LVU4032 +4698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11924 .loc 1 4698 13 is_stmt 0 view .LVU4033 + 11925 013e 638D ldrh r3, [r4, #42] + 11926 0140 9BB2 uxth r3, r3 +4698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11927 .loc 1 4698 8 view .LVU4034 + 11928 0142 8BB9 cbnz r3, .L731 +4700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11929 .loc 1 4700 7 is_stmt 1 view .LVU4035 +4700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11930 .loc 1 4700 11 is_stmt 0 view .LVU4036 + 11931 0144 2368 ldr r3, [r4] + 11932 0146 5A68 ldr r2, [r3, #4] + 11933 .LVL789: +4700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11934 .loc 1 4700 10 view .LVU4037 + 11935 0148 12F0007F tst r2, #33554432 + 11936 014c 82D1 bne .L723 +4703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11937 .loc 1 4703 9 is_stmt 1 view .LVU4038 +4703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11938 .loc 1 4703 17 is_stmt 0 view .LVU4039 + 11939 014e E26A ldr r2, [r4, #44] +4703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 11940 .loc 1 4703 12 view .LVU4040 + 11941 0150 12F5803F cmn r2, #65536 + 11942 0154 04D1 bne .L732 +4706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11943 .loc 1 4706 11 is_stmt 1 view .LVU4041 +4706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11944 .loc 1 4706 31 is_stmt 0 view .LVU4042 + 11945 0156 5A68 ldr r2, [r3, #4] + 11946 0158 42F48042 orr r2, r2, #16384 + 11947 015c 5A60 str r2, [r3, #4] + 11948 015e 79E7 b .L723 + 11949 .L732: +4711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11950 .loc 1 4711 11 is_stmt 1 view .LVU4043 + 11951 0160 2046 mov r0, r4 + 11952 .LVL790: +4711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11953 .loc 1 4711 11 is_stmt 0 view .LVU4044 + 11954 0162 FFF7FEFF bl I2C_ITMasterSeqCplt + 11955 .LVL791: +4711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11956 .loc 1 4711 11 view .LVU4045 + 11957 0166 75E7 b .L723 + 11958 .LVL792: + ARM GAS /tmp/ccEimIdZ.s page 394 + + + 11959 .L731: +4719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11960 .loc 1 4719 7 is_stmt 1 view .LVU4046 + 11961 0168 4021 movs r1, #64 + 11962 .LVL793: +4719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11963 .loc 1 4719 7 is_stmt 0 view .LVU4047 + 11964 016a 2046 mov r0, r4 + 11965 .LVL794: +4719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11966 .loc 1 4719 7 view .LVU4048 + 11967 016c FFF7FEFF bl I2C_ITError + 11968 .LVL795: +4719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11969 .loc 1 4719 7 view .LVU4049 + 11970 0170 70E7 b .L723 + 11971 .LVL796: + 11972 .L740: +4730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 11973 .loc 1 4730 5 is_stmt 1 view .LVU4050 + 11974 0172 2946 mov r1, r5 + 11975 0174 2046 mov r0, r4 + 11976 0176 FFF7FEFF bl I2C_ITMasterCplt + 11977 .LVL797: + 11978 017a 72E7 b .L733 + 11979 .LVL798: + 11980 .L734: + 11981 .LCFI130: + 11982 .cfi_def_cfa_offset 0 + 11983 .cfi_restore 4 + 11984 .cfi_restore 5 + 11985 .cfi_restore 6 + 11986 .cfi_restore 14 +4616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11987 .loc 1 4616 3 is_stmt 0 view .LVU4051 + 11988 017c 0220 movs r0, #2 + 11989 .LVL799: +4737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 11990 .loc 1 4737 1 view .LVU4052 + 11991 017e 7047 bx lr + 11992 .cfi_endproc + 11993 .LFE190: + 11995 .section .text.I2C_Slave_ISR_DMA,"ax",%progbits + 11996 .align 1 + 11997 .syntax unified + 11998 .thumb + 11999 .thumb_func + 12000 .fpu fpv5-d16 + 12002 I2C_Slave_ISR_DMA: + 12003 .LVL800: + 12004 .LFB193: +5016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 12005 .loc 1 5016 1 is_stmt 1 view -0 + 12006 .cfi_startproc + 12007 @ args = 0, pretend = 0, frame = 0 + 12008 @ frame_needed = 0, uses_anonymous_args = 0 +5016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + ARM GAS /tmp/ccEimIdZ.s page 395 + + + 12009 .loc 1 5016 1 is_stmt 0 view .LVU4054 + 12010 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 12011 .LCFI131: + 12012 .cfi_def_cfa_offset 24 + 12013 .cfi_offset 3, -24 + 12014 .cfi_offset 4, -20 + 12015 .cfi_offset 5, -16 + 12016 .cfi_offset 6, -12 + 12017 .cfi_offset 7, -8 + 12018 .cfi_offset 14, -4 +5017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 12019 .loc 1 5017 3 is_stmt 1 view .LVU4055 +5017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 12020 .loc 1 5017 12 is_stmt 0 view .LVU4056 + 12021 0002 C76A ldr r7, [r0, #44] + 12022 .LVL801: +5018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12023 .loc 1 5018 3 is_stmt 1 view .LVU4057 +5019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12024 .loc 1 5019 3 view .LVU4058 +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12025 .loc 1 5022 3 view .LVU4059 +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12026 .loc 1 5022 3 view .LVU4060 + 12027 0004 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 12028 0008 012B cmp r3, #1 + 12029 000a 00F00381 beq .L763 + 12030 000e 0446 mov r4, r0 + 12031 0010 0D46 mov r5, r1 + 12032 0012 1646 mov r6, r2 +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12033 .loc 1 5022 3 discriminator 2 view .LVU4061 + 12034 0014 0123 movs r3, #1 + 12035 0016 80F84030 strb r3, [r0, #64] +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12036 .loc 1 5022 3 discriminator 2 view .LVU4062 +5025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12037 .loc 1 5025 3 discriminator 2 view .LVU4063 +5025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12038 .loc 1 5025 6 is_stmt 0 discriminator 2 view .LVU4064 + 12039 001a 11F0200F tst r1, #32 + 12040 001e 02D0 beq .L744 +5025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12041 .loc 1 5025 58 discriminator 1 view .LVU4065 + 12042 0020 12F0200F tst r2, #32 + 12043 0024 4DD1 bne .L768 + 12044 .LVL802: + 12045 .L744: +5031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12046 .loc 1 5031 3 is_stmt 1 view .LVU4066 +5031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12047 .loc 1 5031 6 is_stmt 0 view .LVU4067 + 12048 0026 15F0100F tst r5, #16 + 12049 002a 00F0E480 beq .L745 +5031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12050 .loc 1 5031 55 discriminator 1 view .LVU4068 + 12051 002e 16F0100F tst r6, #16 + ARM GAS /tmp/ccEimIdZ.s page 396 + + + 12052 0032 00F0E080 beq .L745 +5037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12053 .loc 1 5037 5 is_stmt 1 view .LVU4069 +5037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12054 .loc 1 5037 10 is_stmt 0 view .LVU4070 + 12055 0036 C6F38032 ubfx r2, r6, #14, #1 +5037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12056 .loc 1 5037 8 view .LVU4071 + 12057 003a 16F4804F tst r6, #16384 + 12058 003e 03D1 bne .L746 +5037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12059 .loc 1 5037 68 discriminator 1 view .LVU4072 + 12060 0040 16F4004F tst r6, #32768 + 12061 0044 00F0D380 beq .L747 + 12062 .L746: +5041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12063 .loc 1 5041 7 is_stmt 1 view .LVU4073 +5041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12064 .loc 1 5041 15 is_stmt 0 view .LVU4074 + 12065 0048 E36B ldr r3, [r4, #60] +5041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12066 .loc 1 5041 10 view .LVU4075 + 12067 004a 002B cmp r3, #0 + 12068 004c 44D0 beq .L764 +5043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12069 .loc 1 5043 9 is_stmt 1 view .LVU4076 +5043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12070 .loc 1 5043 12 is_stmt 0 view .LVU4077 + 12071 004e 16F4004F tst r6, #32768 + 12072 0052 43D0 beq .L765 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12073 .loc 1 5045 11 is_stmt 1 view .LVU4078 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12074 .loc 1 5045 15 is_stmt 0 view .LVU4079 + 12075 0054 1B68 ldr r3, [r3] +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12076 .loc 1 5045 51 view .LVU4080 + 12077 0056 7048 ldr r0, .L772 + 12078 0058 7049 ldr r1, .L772+4 + 12079 005a 8B42 cmp r3, r1 + 12080 005c 18BF it ne + 12081 005e 8342 cmpne r3, r0 + 12082 0060 32D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12083 .loc 1 5045 15 discriminator 2 view .LVU4081 + 12084 0062 1831 adds r1, r1, #24 + 12085 0064 8B42 cmp r3, r1 + 12086 0066 2FD0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12087 .loc 1 5045 15 discriminator 4 view .LVU4082 + 12088 0068 1831 adds r1, r1, #24 + 12089 006a 8B42 cmp r3, r1 + 12090 006c 2CD0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12091 .loc 1 5045 15 discriminator 6 view .LVU4083 + 12092 006e 1831 adds r1, r1, #24 + 12093 0070 8B42 cmp r3, r1 + ARM GAS /tmp/ccEimIdZ.s page 397 + + + 12094 0072 29D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12095 .loc 1 5045 15 discriminator 8 view .LVU4084 + 12096 0074 1831 adds r1, r1, #24 + 12097 0076 8B42 cmp r3, r1 + 12098 0078 26D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12099 .loc 1 5045 15 discriminator 10 view .LVU4085 + 12100 007a 1831 adds r1, r1, #24 + 12101 007c 8B42 cmp r3, r1 + 12102 007e 23D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12103 .loc 1 5045 15 discriminator 12 view .LVU4086 + 12104 0080 1831 adds r1, r1, #24 + 12105 0082 8B42 cmp r3, r1 + 12106 0084 20D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12107 .loc 1 5045 15 discriminator 14 view .LVU4087 + 12108 0086 01F55671 add r1, r1, #856 + 12109 008a 8B42 cmp r3, r1 + 12110 008c 1CD0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12111 .loc 1 5045 15 discriminator 16 view .LVU4088 + 12112 008e 1831 adds r1, r1, #24 + 12113 0090 8B42 cmp r3, r1 + 12114 0092 19D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12115 .loc 1 5045 15 discriminator 18 view .LVU4089 + 12116 0094 1831 adds r1, r1, #24 + 12117 0096 8B42 cmp r3, r1 + 12118 0098 16D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12119 .loc 1 5045 15 discriminator 20 view .LVU4090 + 12120 009a 1831 adds r1, r1, #24 + 12121 009c 8B42 cmp r3, r1 + 12122 009e 13D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12123 .loc 1 5045 15 discriminator 22 view .LVU4091 + 12124 00a0 1831 adds r1, r1, #24 + 12125 00a2 8B42 cmp r3, r1 + 12126 00a4 10D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12127 .loc 1 5045 15 discriminator 24 view .LVU4092 + 12128 00a6 1831 adds r1, r1, #24 + 12129 00a8 8B42 cmp r3, r1 + 12130 00aa 0DD0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12131 .loc 1 5045 15 discriminator 26 view .LVU4093 + 12132 00ac 1831 adds r1, r1, #24 + 12133 00ae 8B42 cmp r3, r1 + 12134 00b0 0AD0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12135 .loc 1 5045 15 discriminator 28 view .LVU4094 + 12136 00b2 1831 adds r1, r1, #24 + 12137 00b4 8B42 cmp r3, r1 + 12138 00b6 07D0 beq .L749 +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 398 + + + 12139 .loc 1 5045 15 discriminator 30 view .LVU4095 + 12140 00b8 5B68 ldr r3, [r3, #4] +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12141 .loc 1 5045 51 discriminator 30 view .LVU4096 + 12142 00ba B3FA83F3 clz r3, r3 + 12143 00be 5B09 lsrs r3, r3, #5 + 12144 00c0 06E0 b .L751 + 12145 .LVL803: + 12146 .L768: +5028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12147 .loc 1 5028 5 is_stmt 1 view .LVU4097 + 12148 00c2 FFF7FEFF bl I2C_ITSlaveCplt + 12149 .LVL804: +5028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12150 .loc 1 5028 5 is_stmt 0 view .LVU4098 + 12151 00c6 AEE7 b .L744 + 12152 .L749: +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12153 .loc 1 5045 15 discriminator 29 view .LVU4099 + 12154 00c8 5B68 ldr r3, [r3, #4] +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12155 .loc 1 5045 51 discriminator 29 view .LVU4100 + 12156 00ca B3FA83F3 clz r3, r3 + 12157 00ce 5B09 lsrs r3, r3, #5 + 12158 .L751: +5045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12159 .loc 1 5045 14 discriminator 32 view .LVU4101 + 12160 00d0 002B cmp r3, #0 + 12161 00d2 40D1 bne .L766 +5018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12162 .loc 1 5018 12 view .LVU4102 + 12163 00d4 0021 movs r1, #0 + 12164 00d6 02E0 b .L748 + 12165 .L764: +5018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12166 .loc 1 5018 12 view .LVU4103 + 12167 00d8 0021 movs r1, #0 + 12168 00da 00E0 b .L748 + 12169 .L765: +5018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12170 .loc 1 5018 12 view .LVU4104 + 12171 00dc 0021 movs r1, #0 + 12172 .L748: + 12173 .LVL805: +5053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12174 .loc 1 5053 7 is_stmt 1 view .LVU4105 +5053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12175 .loc 1 5053 15 is_stmt 0 view .LVU4106 + 12176 00de A36B ldr r3, [r4, #56] +5053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12177 .loc 1 5053 10 view .LVU4107 + 12178 00e0 002B cmp r3, #0 + 12179 00e2 3FD0 beq .L752 +5055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12180 .loc 1 5055 9 is_stmt 1 view .LVU4108 +5055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12181 .loc 1 5055 12 is_stmt 0 view .LVU4109 + ARM GAS /tmp/ccEimIdZ.s page 399 + + + 12182 00e4 002A cmp r2, #0 + 12183 00e6 3DD0 beq .L752 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12184 .loc 1 5057 11 is_stmt 1 view .LVU4110 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12185 .loc 1 5057 15 is_stmt 0 view .LVU4111 + 12186 00e8 1B68 ldr r3, [r3] +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12187 .loc 1 5057 51 view .LVU4112 + 12188 00ea 4B48 ldr r0, .L772 + 12189 00ec 4B4A ldr r2, .L772+4 + 12190 00ee 9342 cmp r3, r2 + 12191 00f0 18BF it ne + 12192 00f2 8342 cmpne r3, r0 + 12193 00f4 31D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12194 .loc 1 5057 15 discriminator 2 view .LVU4113 + 12195 00f6 1832 adds r2, r2, #24 + 12196 00f8 9342 cmp r3, r2 + 12197 00fa 2ED0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12198 .loc 1 5057 15 discriminator 4 view .LVU4114 + 12199 00fc 1832 adds r2, r2, #24 + 12200 00fe 9342 cmp r3, r2 + 12201 0100 2BD0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12202 .loc 1 5057 15 discriminator 6 view .LVU4115 + 12203 0102 1832 adds r2, r2, #24 + 12204 0104 9342 cmp r3, r2 + 12205 0106 28D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12206 .loc 1 5057 15 discriminator 8 view .LVU4116 + 12207 0108 1832 adds r2, r2, #24 + 12208 010a 9342 cmp r3, r2 + 12209 010c 25D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12210 .loc 1 5057 15 discriminator 10 view .LVU4117 + 12211 010e 1832 adds r2, r2, #24 + 12212 0110 9342 cmp r3, r2 + 12213 0112 22D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12214 .loc 1 5057 15 discriminator 12 view .LVU4118 + 12215 0114 1832 adds r2, r2, #24 + 12216 0116 9342 cmp r3, r2 + 12217 0118 1FD0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12218 .loc 1 5057 15 discriminator 14 view .LVU4119 + 12219 011a 02F55672 add r2, r2, #856 + 12220 011e 9342 cmp r3, r2 + 12221 0120 1BD0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12222 .loc 1 5057 15 discriminator 16 view .LVU4120 + 12223 0122 1832 adds r2, r2, #24 + 12224 0124 9342 cmp r3, r2 + 12225 0126 18D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12226 .loc 1 5057 15 discriminator 18 view .LVU4121 + ARM GAS /tmp/ccEimIdZ.s page 400 + + + 12227 0128 1832 adds r2, r2, #24 + 12228 012a 9342 cmp r3, r2 + 12229 012c 15D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12230 .loc 1 5057 15 discriminator 20 view .LVU4122 + 12231 012e 1832 adds r2, r2, #24 + 12232 0130 9342 cmp r3, r2 + 12233 0132 12D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12234 .loc 1 5057 15 discriminator 22 view .LVU4123 + 12235 0134 1832 adds r2, r2, #24 + 12236 0136 9342 cmp r3, r2 + 12237 0138 0FD0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12238 .loc 1 5057 15 discriminator 24 view .LVU4124 + 12239 013a 1832 adds r2, r2, #24 + 12240 013c 9342 cmp r3, r2 + 12241 013e 0CD0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12242 .loc 1 5057 15 discriminator 26 view .LVU4125 + 12243 0140 1832 adds r2, r2, #24 + 12244 0142 9342 cmp r3, r2 + 12245 0144 09D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12246 .loc 1 5057 15 discriminator 28 view .LVU4126 + 12247 0146 1832 adds r2, r2, #24 + 12248 0148 9342 cmp r3, r2 + 12249 014a 06D0 beq .L753 +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12250 .loc 1 5057 15 discriminator 30 view .LVU4127 + 12251 014c 5B68 ldr r3, [r3, #4] +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12252 .loc 1 5057 51 discriminator 30 view .LVU4128 + 12253 014e B3FA83F3 clz r3, r3 + 12254 0152 5B09 lsrs r3, r3, #5 + 12255 0154 05E0 b .L755 + 12256 .LVL806: + 12257 .L766: +5047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12258 .loc 1 5047 26 view .LVU4129 + 12259 0156 0121 movs r1, #1 + 12260 0158 C1E7 b .L748 + 12261 .LVL807: + 12262 .L753: +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12263 .loc 1 5057 15 discriminator 29 view .LVU4130 + 12264 015a 5B68 ldr r3, [r3, #4] +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12265 .loc 1 5057 51 discriminator 29 view .LVU4131 + 12266 015c B3FA83F3 clz r3, r3 + 12267 0160 5B09 lsrs r3, r3, #5 + 12268 .L755: +5057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12269 .loc 1 5057 14 discriminator 32 view .LVU4132 + 12270 0162 D3B9 cbnz r3, .L756 + 12271 .L752: +5064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 401 + + + 12272 .loc 1 5064 7 is_stmt 1 view .LVU4133 +5064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12273 .loc 1 5064 10 is_stmt 0 view .LVU4134 + 12274 0164 C9B9 cbnz r1, .L756 +5093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12275 .loc 1 5093 9 is_stmt 1 view .LVU4135 + 12276 0166 2368 ldr r3, [r4] + 12277 0168 1022 movs r2, #16 + 12278 016a DA61 str r2, [r3, #28] +5096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12279 .loc 1 5096 9 view .LVU4136 +5096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12280 .loc 1 5096 25 is_stmt 0 view .LVU4137 + 12281 016c 636C ldr r3, [r4, #68] + 12282 016e 43F00403 orr r3, r3, #4 + 12283 0172 6364 str r3, [r4, #68] +5099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12284 .loc 1 5099 9 is_stmt 1 view .LVU4138 +5099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12285 .loc 1 5099 18 is_stmt 0 view .LVU4139 + 12286 0174 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12287 0178 DBB2 uxtb r3, r3 + 12288 .LVL808: +5101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12289 .loc 1 5101 9 is_stmt 1 view .LVU4140 +5101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12290 .loc 1 5101 12 is_stmt 0 view .LVU4141 + 12291 017a B7F1807F cmp r7, #16777216 + 12292 017e 18BF it ne + 12293 0180 002F cmpne r7, #0 + 12294 0182 3ED1 bne .L759 +5103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12295 .loc 1 5103 11 is_stmt 1 view .LVU4142 +5103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12296 .loc 1 5103 14 is_stmt 0 view .LVU4143 + 12297 0184 292B cmp r3, #41 + 12298 0186 18BF it ne + 12299 0188 212B cmpne r3, #33 + 12300 018a 29D1 bne .L761 +5105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12301 .loc 1 5105 13 is_stmt 1 view .LVU4144 +5105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12302 .loc 1 5105 33 is_stmt 0 view .LVU4145 + 12303 018c 2123 movs r3, #33 + 12304 .LVL809: +5105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12305 .loc 1 5105 33 view .LVU4146 + 12306 018e 2363 str r3, [r4, #48] + 12307 .L762: +5114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12308 .loc 1 5114 11 is_stmt 1 view .LVU4147 +5117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12309 .loc 1 5117 11 view .LVU4148 + 12310 0190 616C ldr r1, [r4, #68] + 12311 .LVL810: +5117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12312 .loc 1 5117 11 is_stmt 0 view .LVU4149 + ARM GAS /tmp/ccEimIdZ.s page 402 + + + 12313 0192 2046 mov r0, r4 + 12314 0194 FFF7FEFF bl I2C_ITError + 12315 .LVL811: + 12316 0198 33E0 b .L759 + 12317 .LVL812: + 12318 .L756: +5066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12319 .loc 1 5066 9 is_stmt 1 view .LVU4150 +5066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12320 .loc 1 5066 18 is_stmt 0 view .LVU4151 + 12321 019a 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12322 019e DBB2 uxtb r3, r3 +5066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12323 .loc 1 5066 12 view .LVU4152 + 12324 01a0 282B cmp r3, #40 + 12325 01a2 08D0 beq .L769 + 12326 .L758: +5071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12327 .loc 1 5071 14 is_stmt 1 view .LVU4153 +5071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12328 .loc 1 5071 23 is_stmt 0 view .LVU4154 + 12329 01a4 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12330 01a8 DBB2 uxtb r3, r3 +5071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12331 .loc 1 5071 17 view .LVU4155 + 12332 01aa 292B cmp r3, #41 + 12333 01ac 0BD0 beq .L770 + 12334 .L760: +5086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12335 .loc 1 5086 11 is_stmt 1 view .LVU4156 + 12336 01ae 2368 ldr r3, [r4] + 12337 01b0 1022 movs r2, #16 + 12338 01b2 DA61 str r2, [r3, #28] + 12339 01b4 25E0 b .L759 + 12340 .L769: +5066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12341 .loc 1 5066 51 is_stmt 0 discriminator 1 view .LVU4157 + 12342 01b6 B7F1007F cmp r7, #33554432 + 12343 01ba F3D1 bne .L758 +5069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12344 .loc 1 5069 11 is_stmt 1 view .LVU4158 + 12345 01bc 2946 mov r1, r5 + 12346 01be 2046 mov r0, r4 + 12347 01c0 FFF7FEFF bl I2C_ITListenCplt + 12348 .LVL813: + 12349 01c4 1DE0 b .L759 + 12350 .L770: +5071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12351 .loc 1 5071 64 is_stmt 0 discriminator 1 view .LVU4159 + 12352 01c6 17F5803F cmn r7, #65536 + 12353 01ca F0D0 beq .L760 +5074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12354 .loc 1 5074 11 is_stmt 1 view .LVU4160 + 12355 01cc 2368 ldr r3, [r4] + 12356 01ce 1022 movs r2, #16 + 12357 01d0 DA61 str r2, [r3, #28] +5077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 403 + + + 12358 .loc 1 5077 11 view .LVU4161 + 12359 01d2 2046 mov r0, r4 + 12360 01d4 FFF7FEFF bl I2C_Flush_TXDR + 12361 .LVL814: +5081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12362 .loc 1 5081 11 view .LVU4162 + 12363 01d8 2046 mov r0, r4 + 12364 01da FFF7FEFF bl I2C_ITSlaveSeqCplt + 12365 .LVL815: + 12366 01de 10E0 b .L759 + 12367 .LVL816: + 12368 .L761: +5107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12369 .loc 1 5107 16 view .LVU4163 +5107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12370 .loc 1 5107 19 is_stmt 0 view .LVU4164 + 12371 01e0 2A2B cmp r3, #42 + 12372 01e2 18BF it ne + 12373 01e4 222B cmpne r3, #34 + 12374 01e6 D3D1 bne .L762 +5109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12375 .loc 1 5109 13 is_stmt 1 view .LVU4165 +5109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12376 .loc 1 5109 33 is_stmt 0 view .LVU4166 + 12377 01e8 2223 movs r3, #34 + 12378 .LVL817: +5109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12379 .loc 1 5109 33 view .LVU4167 + 12380 01ea 2363 str r3, [r4, #48] + 12381 01ec D0E7 b .L762 + 12382 .LVL818: + 12383 .L747: +5124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12384 .loc 1 5124 7 is_stmt 1 view .LVU4168 + 12385 01ee 2368 ldr r3, [r4] + 12386 01f0 1022 movs r2, #16 + 12387 01f2 DA61 str r2, [r3, #28] + 12388 01f4 05E0 b .L759 + 12389 .L745: +5127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12390 .loc 1 5127 8 view .LVU4169 +5127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12391 .loc 1 5127 11 is_stmt 0 view .LVU4170 + 12392 01f6 15F0080F tst r5, #8 + 12393 01fa 02D0 beq .L759 +5127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12394 .loc 1 5127 62 discriminator 1 view .LVU4171 + 12395 01fc 16F0080F tst r6, #8 + 12396 0200 03D1 bne .L771 + 12397 .LVL819: + 12398 .L759: +5134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12399 .loc 1 5134 3 is_stmt 1 view .LVU4172 +5137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12400 .loc 1 5137 3 view .LVU4173 +5137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12401 .loc 1 5137 3 view .LVU4174 + ARM GAS /tmp/ccEimIdZ.s page 404 + + + 12402 0202 0020 movs r0, #0 + 12403 0204 84F84000 strb r0, [r4, #64] +5137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12404 .loc 1 5137 3 view .LVU4175 +5139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12405 .loc 1 5139 3 view .LVU4176 + 12406 .LVL820: + 12407 .L743: +5140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12408 .loc 1 5140 1 is_stmt 0 view .LVU4177 + 12409 0208 F8BD pop {r3, r4, r5, r6, r7, pc} + 12410 .LVL821: + 12411 .L771: +5129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12412 .loc 1 5129 5 is_stmt 1 view .LVU4178 + 12413 020a 2946 mov r1, r5 + 12414 020c 2046 mov r0, r4 + 12415 020e FFF7FEFF bl I2C_ITAddrCplt + 12416 .LVL822: + 12417 0212 F6E7 b .L759 + 12418 .LVL823: + 12419 .L763: +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12420 .loc 1 5022 3 is_stmt 0 view .LVU4179 + 12421 0214 0220 movs r0, #2 + 12422 .LVL824: +5022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12423 .loc 1 5022 3 view .LVU4180 + 12424 0216 F7E7 b .L743 + 12425 .L773: + 12426 .align 2 + 12427 .L772: + 12428 0218 10000240 .word 1073872912 + 12429 021c 28000240 .word 1073872936 + 12430 .cfi_endproc + 12431 .LFE193: + 12433 .section .text.I2C_Master_ISR_DMA,"ax",%progbits + 12434 .align 1 + 12435 .syntax unified + 12436 .thumb + 12437 .thumb_func + 12438 .fpu fpv5-d16 + 12440 I2C_Master_ISR_DMA: + 12441 .LVL825: + 12442 .LFB192: +4881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t devaddress; + 12443 .loc 1 4881 1 is_stmt 1 view -0 + 12444 .cfi_startproc + 12445 @ args = 0, pretend = 0, frame = 0 + 12446 @ frame_needed = 0, uses_anonymous_args = 0 +4882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t xfermode; + 12447 .loc 1 4882 3 view .LVU4182 +4883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12448 .loc 1 4883 3 view .LVU4183 +4886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12449 .loc 1 4886 3 view .LVU4184 +4886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 405 + + + 12450 .loc 1 4886 3 view .LVU4185 + 12451 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 12452 0004 012B cmp r3, #1 + 12453 0006 00F09A80 beq .L787 +4881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint16_t devaddress; + 12454 .loc 1 4881 1 is_stmt 0 discriminator 2 view .LVU4186 + 12455 000a 10B5 push {r4, lr} + 12456 .LCFI132: + 12457 .cfi_def_cfa_offset 8 + 12458 .cfi_offset 4, -8 + 12459 .cfi_offset 14, -4 + 12460 000c 82B0 sub sp, sp, #8 + 12461 .LCFI133: + 12462 .cfi_def_cfa_offset 16 + 12463 000e 0446 mov r4, r0 +4886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12464 .loc 1 4886 3 is_stmt 1 discriminator 2 view .LVU4187 + 12465 0010 0123 movs r3, #1 + 12466 0012 80F84030 strb r3, [r0, #64] +4886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12467 .loc 1 4886 3 discriminator 2 view .LVU4188 +4888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12468 .loc 1 4888 3 discriminator 2 view .LVU4189 +4888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12469 .loc 1 4888 6 is_stmt 0 discriminator 2 view .LVU4190 + 12470 0016 11F0100F tst r1, #16 + 12471 001a 02D0 beq .L776 +4888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12472 .loc 1 4888 55 discriminator 1 view .LVU4191 + 12473 001c 12F0100F tst r2, #16 + 12474 0020 32D1 bne .L793 + 12475 .L776: +4904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12476 .loc 1 4904 8 is_stmt 1 view .LVU4192 +4904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12477 .loc 1 4904 11 is_stmt 0 view .LVU4193 + 12478 0022 11F0800F tst r1, #128 + 12479 0026 60D0 beq .L778 +4904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12480 .loc 1 4904 61 discriminator 1 view .LVU4194 + 12481 0028 12F0400F tst r2, #64 + 12482 002c 5DD0 beq .L778 +4907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12483 .loc 1 4907 5 is_stmt 1 view .LVU4195 + 12484 002e 2268 ldr r2, [r4] + 12485 .LVL826: +4907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12486 .loc 1 4907 5 is_stmt 0 view .LVU4196 + 12487 0030 1368 ldr r3, [r2] + 12488 0032 23F04003 bic r3, r3, #64 + 12489 0036 1360 str r3, [r2] +4909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12490 .loc 1 4909 5 is_stmt 1 view .LVU4197 +4909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12491 .loc 1 4909 13 is_stmt 0 view .LVU4198 + 12492 0038 638D ldrh r3, [r4, #42] + 12493 003a 9BB2 uxth r3, r3 + ARM GAS /tmp/ccEimIdZ.s page 406 + + +4909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12494 .loc 1 4909 8 view .LVU4199 + 12495 003c 002B cmp r3, #0 + 12496 003e 46D0 beq .L779 +4912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12497 .loc 1 4912 7 is_stmt 1 view .LVU4200 +4912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12498 .loc 1 4912 35 is_stmt 0 view .LVU4201 + 12499 0040 2368 ldr r3, [r4] +4912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12500 .loc 1 4912 45 view .LVU4202 + 12501 0042 5968 ldr r1, [r3, #4] + 12502 .LVL827: +4912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12503 .loc 1 4912 18 view .LVU4203 + 12504 0044 C1F30901 ubfx r1, r1, #0, #10 + 12505 .LVL828: +4915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12506 .loc 1 4915 7 is_stmt 1 view .LVU4204 +4915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12507 .loc 1 4915 15 is_stmt 0 view .LVU4205 + 12508 0048 638D ldrh r3, [r4, #42] + 12509 004a 9BB2 uxth r3, r3 +4915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12510 .loc 1 4915 10 view .LVU4206 + 12511 004c FF2B cmp r3, #255 + 12512 004e 2DD9 bls .L780 +4917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 12513 .loc 1 4917 9 is_stmt 1 view .LVU4207 +4917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 12514 .loc 1 4917 24 is_stmt 0 view .LVU4208 + 12515 0050 FF23 movs r3, #255 + 12516 0052 2385 strh r3, [r4, #40] @ movhi +4918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12517 .loc 1 4918 9 is_stmt 1 view .LVU4209 + 12518 .LVL829: +4918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12519 .loc 1 4918 18 is_stmt 0 view .LVU4210 + 12520 0054 4FF08073 mov r3, #16777216 + 12521 .LVL830: + 12522 .L781: +4934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12523 .loc 1 4934 7 is_stmt 1 view .LVU4211 + 12524 0058 0022 movs r2, #0 + 12525 005a 0092 str r2, [sp] + 12526 005c 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 12527 0060 2046 mov r0, r4 + 12528 .LVL831: +4934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12529 .loc 1 4934 7 is_stmt 0 view .LVU4212 + 12530 0062 FFF7FEFF bl I2C_TransferConfig + 12531 .LVL832: +4937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12532 .loc 1 4937 7 is_stmt 1 view .LVU4213 +4937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12533 .loc 1 4937 23 is_stmt 0 view .LVU4214 + 12534 0066 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccEimIdZ.s page 407 + + + 12535 0068 9BB2 uxth r3, r3 +4937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12536 .loc 1 4937 30 view .LVU4215 + 12537 006a 228D ldrh r2, [r4, #40] +4937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12538 .loc 1 4937 23 view .LVU4216 + 12539 006c 9B1A subs r3, r3, r2 + 12540 006e 9BB2 uxth r3, r3 + 12541 0070 6385 strh r3, [r4, #42] @ movhi +4940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12542 .loc 1 4940 7 is_stmt 1 view .LVU4217 +4940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12543 .loc 1 4940 15 is_stmt 0 view .LVU4218 + 12544 0072 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12545 0076 DBB2 uxtb r3, r3 +4940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12546 .loc 1 4940 10 view .LVU4219 + 12547 0078 222B cmp r3, #34 + 12548 007a 22D0 beq .L794 +4946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12549 .loc 1 4946 9 is_stmt 1 view .LVU4220 +4946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12550 .loc 1 4946 13 is_stmt 0 view .LVU4221 + 12551 007c 2268 ldr r2, [r4] +4946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12552 .loc 1 4946 29 view .LVU4222 + 12553 007e 1368 ldr r3, [r2] + 12554 0080 43F48043 orr r3, r3, #16384 + 12555 0084 1360 str r3, [r2] + 12556 0086 0CE0 b .L777 + 12557 .LVL833: + 12558 .L793: +4891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12559 .loc 1 4891 5 is_stmt 1 view .LVU4223 + 12560 0088 0368 ldr r3, [r0] + 12561 008a 1022 movs r2, #16 + 12562 .LVL834: +4891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12563 .loc 1 4891 5 is_stmt 0 view .LVU4224 + 12564 008c DA61 str r2, [r3, #28] +4894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12565 .loc 1 4894 5 is_stmt 1 view .LVU4225 +4894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12566 .loc 1 4894 21 is_stmt 0 view .LVU4226 + 12567 008e 436C ldr r3, [r0, #68] + 12568 0090 43F00403 orr r3, r3, #4 + 12569 0094 4364 str r3, [r0, #68] +4899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12570 .loc 1 4899 5 is_stmt 1 view .LVU4227 + 12571 0096 2021 movs r1, #32 + 12572 .LVL835: +4899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12573 .loc 1 4899 5 is_stmt 0 view .LVU4228 + 12574 0098 FFF7FEFF bl I2C_Enable_IRQ + 12575 .LVL836: +4902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12576 .loc 1 4902 5 is_stmt 1 view .LVU4229 + ARM GAS /tmp/ccEimIdZ.s page 408 + + + 12577 009c 2046 mov r0, r4 + 12578 009e FFF7FEFF bl I2C_Flush_TXDR + 12579 .LVL837: + 12580 .L777: +4999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12581 .loc 1 4999 3 view .LVU4230 +5002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12582 .loc 1 5002 3 view .LVU4231 +5002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12583 .loc 1 5002 3 view .LVU4232 + 12584 00a2 0020 movs r0, #0 + 12585 00a4 84F84000 strb r0, [r4, #64] +5002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12586 .loc 1 5002 3 view .LVU4233 +5004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12587 .loc 1 5004 3 view .LVU4234 +5005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12588 .loc 1 5005 1 is_stmt 0 view .LVU4235 + 12589 00a8 02B0 add sp, sp, #8 + 12590 .LCFI134: + 12591 .cfi_remember_state + 12592 .cfi_def_cfa_offset 8 + 12593 @ sp needed + 12594 00aa 10BD pop {r4, pc} + 12595 .LVL838: + 12596 .L780: + 12597 .LCFI135: + 12598 .cfi_restore_state +4922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12599 .loc 1 4922 9 is_stmt 1 view .LVU4236 +4922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12600 .loc 1 4922 30 is_stmt 0 view .LVU4237 + 12601 00ac 638D ldrh r3, [r4, #42] +4922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12602 .loc 1 4922 24 view .LVU4238 + 12603 00ae 2385 strh r3, [r4, #40] @ movhi +4923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12604 .loc 1 4923 9 is_stmt 1 view .LVU4239 +4923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12605 .loc 1 4923 17 is_stmt 0 view .LVU4240 + 12606 00b0 E36A ldr r3, [r4, #44] +4923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12607 .loc 1 4923 12 view .LVU4241 + 12608 00b2 13F5803F cmn r3, #65536 + 12609 00b6 01D0 beq .L788 +4925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12610 .loc 1 4925 11 is_stmt 1 view .LVU4242 +4925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12611 .loc 1 4925 20 is_stmt 0 view .LVU4243 + 12612 00b8 E36A ldr r3, [r4, #44] + 12613 .LVL839: +4925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12614 .loc 1 4925 20 view .LVU4244 + 12615 00ba CDE7 b .L781 + 12616 .LVL840: + 12617 .L788: +4929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + ARM GAS /tmp/ccEimIdZ.s page 409 + + + 12618 .loc 1 4929 20 view .LVU4245 + 12619 00bc 4FF00073 mov r3, #33554432 + 12620 00c0 CAE7 b .L781 + 12621 .LVL841: + 12622 .L794: +4942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12623 .loc 1 4942 9 is_stmt 1 view .LVU4246 +4942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12624 .loc 1 4942 13 is_stmt 0 view .LVU4247 + 12625 00c2 2268 ldr r2, [r4] +4942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12626 .loc 1 4942 29 view .LVU4248 + 12627 00c4 1368 ldr r3, [r2] + 12628 00c6 43F40043 orr r3, r3, #32768 + 12629 00ca 1360 str r3, [r2] + 12630 00cc E9E7 b .L777 + 12631 .LVL842: + 12632 .L779: +4952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12633 .loc 1 4952 7 is_stmt 1 view .LVU4249 +4952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12634 .loc 1 4952 11 is_stmt 0 view .LVU4250 + 12635 00ce 2368 ldr r3, [r4] + 12636 00d0 5B68 ldr r3, [r3, #4] +4952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12637 .loc 1 4952 10 view .LVU4251 + 12638 00d2 13F0007F tst r3, #33554432 + 12639 00d6 03D1 bne .L783 +4955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12640 .loc 1 4955 9 is_stmt 1 view .LVU4252 + 12641 00d8 2046 mov r0, r4 + 12642 .LVL843: +4955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12643 .loc 1 4955 9 is_stmt 0 view .LVU4253 + 12644 00da FFF7FEFF bl I2C_ITMasterSeqCplt + 12645 .LVL844: +4955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12646 .loc 1 4955 9 view .LVU4254 + 12647 00de E0E7 b .L777 + 12648 .LVL845: + 12649 .L783: +4961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12650 .loc 1 4961 9 is_stmt 1 view .LVU4255 + 12651 00e0 4021 movs r1, #64 + 12652 .LVL846: +4961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12653 .loc 1 4961 9 is_stmt 0 view .LVU4256 + 12654 00e2 2046 mov r0, r4 + 12655 .LVL847: +4961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12656 .loc 1 4961 9 view .LVU4257 + 12657 00e4 FFF7FEFF bl I2C_ITError + 12658 .LVL848: + 12659 00e8 DBE7 b .L777 + 12660 .LVL849: + 12661 .L778: +4965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 410 + + + 12662 .loc 1 4965 8 is_stmt 1 view .LVU4258 +4965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12663 .loc 1 4965 11 is_stmt 0 view .LVU4259 + 12664 00ea 11F0400F tst r1, #64 + 12665 00ee 1CD0 beq .L784 +4965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12666 .loc 1 4965 60 discriminator 1 view .LVU4260 + 12667 00f0 12F0400F tst r2, #64 + 12668 00f4 19D0 beq .L784 +4967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12669 .loc 1 4967 5 is_stmt 1 view .LVU4261 +4967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12670 .loc 1 4967 13 is_stmt 0 view .LVU4262 + 12671 00f6 638D ldrh r3, [r4, #42] + 12672 00f8 9BB2 uxth r3, r3 +4967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12673 .loc 1 4967 8 view .LVU4263 + 12674 00fa 8BB9 cbnz r3, .L785 +4969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12675 .loc 1 4969 7 is_stmt 1 view .LVU4264 +4969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12676 .loc 1 4969 11 is_stmt 0 view .LVU4265 + 12677 00fc 2368 ldr r3, [r4] + 12678 00fe 5A68 ldr r2, [r3, #4] + 12679 .LVL850: +4969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12680 .loc 1 4969 10 view .LVU4266 + 12681 0100 12F0007F tst r2, #33554432 + 12682 0104 CDD1 bne .L777 +4972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12683 .loc 1 4972 9 is_stmt 1 view .LVU4267 +4972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12684 .loc 1 4972 17 is_stmt 0 view .LVU4268 + 12685 0106 E26A ldr r2, [r4, #44] +4972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12686 .loc 1 4972 12 view .LVU4269 + 12687 0108 12F5803F cmn r2, #65536 + 12688 010c 04D1 bne .L786 +4975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12689 .loc 1 4975 11 is_stmt 1 view .LVU4270 +4975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12690 .loc 1 4975 31 is_stmt 0 view .LVU4271 + 12691 010e 5A68 ldr r2, [r3, #4] + 12692 0110 42F48042 orr r2, r2, #16384 + 12693 0114 5A60 str r2, [r3, #4] + 12694 0116 C4E7 b .L777 + 12695 .L786: +4980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12696 .loc 1 4980 11 is_stmt 1 view .LVU4272 + 12697 0118 2046 mov r0, r4 + 12698 .LVL851: +4980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12699 .loc 1 4980 11 is_stmt 0 view .LVU4273 + 12700 011a FFF7FEFF bl I2C_ITMasterSeqCplt + 12701 .LVL852: +4980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12702 .loc 1 4980 11 view .LVU4274 + ARM GAS /tmp/ccEimIdZ.s page 411 + + + 12703 011e C0E7 b .L777 + 12704 .LVL853: + 12705 .L785: +4988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12706 .loc 1 4988 7 is_stmt 1 view .LVU4275 + 12707 0120 4021 movs r1, #64 + 12708 .LVL854: +4988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12709 .loc 1 4988 7 is_stmt 0 view .LVU4276 + 12710 0122 2046 mov r0, r4 + 12711 .LVL855: +4988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12712 .loc 1 4988 7 view .LVU4277 + 12713 0124 FFF7FEFF bl I2C_ITError + 12714 .LVL856: +4988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12715 .loc 1 4988 7 view .LVU4278 + 12716 0128 BBE7 b .L777 + 12717 .LVL857: + 12718 .L784: +4991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12719 .loc 1 4991 8 is_stmt 1 view .LVU4279 +4991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12720 .loc 1 4991 11 is_stmt 0 view .LVU4280 + 12721 012a 11F0200F tst r1, #32 + 12722 012e B8D0 beq .L777 +4991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12723 .loc 1 4991 63 discriminator 1 view .LVU4281 + 12724 0130 12F0200F tst r2, #32 + 12725 0134 B5D0 beq .L777 +4994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12726 .loc 1 4994 5 is_stmt 1 view .LVU4282 + 12727 0136 2046 mov r0, r4 + 12728 .LVL858: +4994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12729 .loc 1 4994 5 is_stmt 0 view .LVU4283 + 12730 0138 FFF7FEFF bl I2C_ITMasterCplt + 12731 .LVL859: +4994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12732 .loc 1 4994 5 view .LVU4284 + 12733 013c B1E7 b .L777 + 12734 .LVL860: + 12735 .L787: + 12736 .LCFI136: + 12737 .cfi_def_cfa_offset 0 + 12738 .cfi_restore 4 + 12739 .cfi_restore 14 +4886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12740 .loc 1 4886 3 view .LVU4285 + 12741 013e 0220 movs r0, #2 + 12742 .LVL861: +5005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12743 .loc 1 5005 1 view .LVU4286 + 12744 0140 7047 bx lr + 12745 .cfi_endproc + 12746 .LFE192: + 12748 .section .text.I2C_DMAError,"ax",%progbits + ARM GAS /tmp/ccEimIdZ.s page 412 + + + 12749 .align 1 + 12750 .syntax unified + 12751 .thumb + 12752 .thumb_func + 12753 .fpu fpv5-d16 + 12755 I2C_DMAError: + 12756 .LVL862: + 12757 .LFB209: +6149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t treatdmaerror = 0U; + 12758 .loc 1 6149 1 is_stmt 1 view -0 + 12759 .cfi_startproc + 12760 @ args = 0, pretend = 0, frame = 0 + 12761 @ frame_needed = 0, uses_anonymous_args = 0 +6149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t treatdmaerror = 0U; + 12762 .loc 1 6149 1 is_stmt 0 view .LVU4288 + 12763 0000 38B5 push {r3, r4, r5, lr} + 12764 .LCFI137: + 12765 .cfi_def_cfa_offset 16 + 12766 .cfi_offset 3, -16 + 12767 .cfi_offset 4, -12 + 12768 .cfi_offset 5, -8 + 12769 .cfi_offset 14, -4 +6150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 12770 .loc 1 6150 3 is_stmt 1 view .LVU4289 + 12771 .LVL863: +6151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12772 .loc 1 6151 3 view .LVU4290 +6151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12773 .loc 1 6151 22 is_stmt 0 view .LVU4291 + 12774 0002 846B ldr r4, [r0, #56] + 12775 .LVL864: +6153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12776 .loc 1 6153 3 is_stmt 1 view .LVU4292 +6153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12777 .loc 1 6153 11 is_stmt 0 view .LVU4293 + 12778 0004 A36B ldr r3, [r4, #56] +6153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12779 .loc 1 6153 6 view .LVU4294 + 12780 0006 002B cmp r3, #0 + 12781 0008 77D0 beq .L805 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12782 .loc 1 6155 5 is_stmt 1 view .LVU4295 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12783 .loc 1 6155 9 is_stmt 0 view .LVU4296 + 12784 000a 1B68 ldr r3, [r3] +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12785 .loc 1 6155 45 view .LVU4297 + 12786 000c 4849 ldr r1, .L810 + 12787 000e 494A ldr r2, .L810+4 + 12788 0010 9342 cmp r3, r2 + 12789 0012 18BF it ne + 12790 0014 8B42 cmpne r3, r1 + 12791 0016 2FD0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12792 .loc 1 6155 9 discriminator 2 view .LVU4298 + 12793 0018 1832 adds r2, r2, #24 + 12794 001a 9342 cmp r3, r2 + ARM GAS /tmp/ccEimIdZ.s page 413 + + + 12795 001c 2CD0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12796 .loc 1 6155 9 discriminator 4 view .LVU4299 + 12797 001e 1832 adds r2, r2, #24 + 12798 0020 9342 cmp r3, r2 + 12799 0022 29D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12800 .loc 1 6155 9 discriminator 6 view .LVU4300 + 12801 0024 1832 adds r2, r2, #24 + 12802 0026 9342 cmp r3, r2 + 12803 0028 26D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12804 .loc 1 6155 9 discriminator 8 view .LVU4301 + 12805 002a 1832 adds r2, r2, #24 + 12806 002c 9342 cmp r3, r2 + 12807 002e 23D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12808 .loc 1 6155 9 discriminator 10 view .LVU4302 + 12809 0030 1832 adds r2, r2, #24 + 12810 0032 9342 cmp r3, r2 + 12811 0034 20D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12812 .loc 1 6155 9 discriminator 12 view .LVU4303 + 12813 0036 1832 adds r2, r2, #24 + 12814 0038 9342 cmp r3, r2 + 12815 003a 1DD0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12816 .loc 1 6155 9 discriminator 14 view .LVU4304 + 12817 003c 02F55672 add r2, r2, #856 + 12818 0040 9342 cmp r3, r2 + 12819 0042 19D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12820 .loc 1 6155 9 discriminator 16 view .LVU4305 + 12821 0044 1832 adds r2, r2, #24 + 12822 0046 9342 cmp r3, r2 + 12823 0048 16D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12824 .loc 1 6155 9 discriminator 18 view .LVU4306 + 12825 004a 1832 adds r2, r2, #24 + 12826 004c 9342 cmp r3, r2 + 12827 004e 13D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12828 .loc 1 6155 9 discriminator 20 view .LVU4307 + 12829 0050 1832 adds r2, r2, #24 + 12830 0052 9342 cmp r3, r2 + 12831 0054 10D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12832 .loc 1 6155 9 discriminator 22 view .LVU4308 + 12833 0056 1832 adds r2, r2, #24 + 12834 0058 9342 cmp r3, r2 + 12835 005a 0DD0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12836 .loc 1 6155 9 discriminator 24 view .LVU4309 + 12837 005c 1832 adds r2, r2, #24 + 12838 005e 9342 cmp r3, r2 + 12839 0060 0AD0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 414 + + + 12840 .loc 1 6155 9 discriminator 26 view .LVU4310 + 12841 0062 1832 adds r2, r2, #24 + 12842 0064 9342 cmp r3, r2 + 12843 0066 07D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12844 .loc 1 6155 9 discriminator 28 view .LVU4311 + 12845 0068 1832 adds r2, r2, #24 + 12846 006a 9342 cmp r3, r2 + 12847 006c 04D0 beq .L797 +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12848 .loc 1 6155 9 discriminator 30 view .LVU4312 + 12849 006e 5B68 ldr r3, [r3, #4] +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12850 .loc 1 6155 45 discriminator 30 view .LVU4313 + 12851 0070 B3FA83F3 clz r3, r3 + 12852 0074 5B09 lsrs r3, r3, #5 + 12853 0076 03E0 b .L799 + 12854 .L797: +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12855 .loc 1 6155 9 discriminator 29 view .LVU4314 + 12856 0078 5B68 ldr r3, [r3, #4] +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12857 .loc 1 6155 45 discriminator 29 view .LVU4315 + 12858 007a B3FA83F3 clz r3, r3 + 12859 007e 5B09 lsrs r3, r3, #5 + 12860 .L799: +6155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12861 .loc 1 6155 8 discriminator 32 view .LVU4316 + 12862 0080 002B cmp r3, #0 + 12863 0082 3CD1 bne .L806 +6150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 12864 .loc 1 6150 12 view .LVU4317 + 12865 0084 0025 movs r5, #0 + 12866 .L796: + 12867 .LVL865: +6161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12868 .loc 1 6161 3 is_stmt 1 view .LVU4318 +6161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12869 .loc 1 6161 11 is_stmt 0 view .LVU4319 + 12870 0086 E36B ldr r3, [r4, #60] +6161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12871 .loc 1 6161 6 view .LVU4320 + 12872 0088 002B cmp r3, #0 + 12873 008a 40D0 beq .L800 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12874 .loc 1 6163 5 is_stmt 1 view .LVU4321 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12875 .loc 1 6163 9 is_stmt 0 view .LVU4322 + 12876 008c 1B68 ldr r3, [r3] +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12877 .loc 1 6163 45 view .LVU4323 + 12878 008e 2849 ldr r1, .L810 + 12879 0090 284A ldr r2, .L810+4 + 12880 0092 9342 cmp r3, r2 + 12881 0094 18BF it ne + 12882 0096 8B42 cmpne r3, r1 + 12883 0098 33D0 beq .L801 + ARM GAS /tmp/ccEimIdZ.s page 415 + + +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12884 .loc 1 6163 9 discriminator 2 view .LVU4324 + 12885 009a 1832 adds r2, r2, #24 + 12886 009c 9342 cmp r3, r2 + 12887 009e 30D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12888 .loc 1 6163 9 discriminator 4 view .LVU4325 + 12889 00a0 1832 adds r2, r2, #24 + 12890 00a2 9342 cmp r3, r2 + 12891 00a4 2DD0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12892 .loc 1 6163 9 discriminator 6 view .LVU4326 + 12893 00a6 1832 adds r2, r2, #24 + 12894 00a8 9342 cmp r3, r2 + 12895 00aa 2AD0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12896 .loc 1 6163 9 discriminator 8 view .LVU4327 + 12897 00ac 1832 adds r2, r2, #24 + 12898 00ae 9342 cmp r3, r2 + 12899 00b0 27D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12900 .loc 1 6163 9 discriminator 10 view .LVU4328 + 12901 00b2 1832 adds r2, r2, #24 + 12902 00b4 9342 cmp r3, r2 + 12903 00b6 24D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12904 .loc 1 6163 9 discriminator 12 view .LVU4329 + 12905 00b8 1832 adds r2, r2, #24 + 12906 00ba 9342 cmp r3, r2 + 12907 00bc 21D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12908 .loc 1 6163 9 discriminator 14 view .LVU4330 + 12909 00be 02F55672 add r2, r2, #856 + 12910 00c2 9342 cmp r3, r2 + 12911 00c4 1DD0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12912 .loc 1 6163 9 discriminator 16 view .LVU4331 + 12913 00c6 1832 adds r2, r2, #24 + 12914 00c8 9342 cmp r3, r2 + 12915 00ca 1AD0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12916 .loc 1 6163 9 discriminator 18 view .LVU4332 + 12917 00cc 1832 adds r2, r2, #24 + 12918 00ce 9342 cmp r3, r2 + 12919 00d0 17D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12920 .loc 1 6163 9 discriminator 20 view .LVU4333 + 12921 00d2 1832 adds r2, r2, #24 + 12922 00d4 9342 cmp r3, r2 + 12923 00d6 14D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12924 .loc 1 6163 9 discriminator 22 view .LVU4334 + 12925 00d8 1832 adds r2, r2, #24 + 12926 00da 9342 cmp r3, r2 + 12927 00dc 11D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12928 .loc 1 6163 9 discriminator 24 view .LVU4335 + ARM GAS /tmp/ccEimIdZ.s page 416 + + + 12929 00de 1832 adds r2, r2, #24 + 12930 00e0 9342 cmp r3, r2 + 12931 00e2 0ED0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12932 .loc 1 6163 9 discriminator 26 view .LVU4336 + 12933 00e4 1832 adds r2, r2, #24 + 12934 00e6 9342 cmp r3, r2 + 12935 00e8 0BD0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12936 .loc 1 6163 9 discriminator 28 view .LVU4337 + 12937 00ea 1832 adds r2, r2, #24 + 12938 00ec 9342 cmp r3, r2 + 12939 00ee 08D0 beq .L801 +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12940 .loc 1 6163 9 discriminator 30 view .LVU4338 + 12941 00f0 5B68 ldr r3, [r3, #4] +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12942 .loc 1 6163 45 discriminator 30 view .LVU4339 + 12943 00f2 B3FA83F3 clz r3, r3 + 12944 00f6 5B09 lsrs r3, r3, #5 + 12945 00f8 07E0 b .L803 + 12946 .LVL866: + 12947 .L805: +6150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 12948 .loc 1 6150 12 view .LVU4340 + 12949 00fa 0025 movs r5, #0 + 12950 00fc C3E7 b .L796 + 12951 .L806: +6157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12952 .loc 1 6157 21 view .LVU4341 + 12953 00fe 0125 movs r5, #1 + 12954 0100 C1E7 b .L796 + 12955 .LVL867: + 12956 .L801: +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12957 .loc 1 6163 9 discriminator 29 view .LVU4342 + 12958 0102 5B68 ldr r3, [r3, #4] +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12959 .loc 1 6163 45 discriminator 29 view .LVU4343 + 12960 0104 B3FA83F3 clz r3, r3 + 12961 0108 5B09 lsrs r3, r3, #5 + 12962 .L803: +6163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12963 .loc 1 6163 8 discriminator 32 view .LVU4344 + 12964 010a 03B1 cbz r3, .L800 +6165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12965 .loc 1 6165 21 view .LVU4345 + 12966 010c 0125 movs r5, #1 + 12967 .LVL868: + 12968 .L800: +6170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12969 .loc 1 6170 3 is_stmt 1 view .LVU4346 +6170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12970 .loc 1 6170 10 is_stmt 0 view .LVU4347 + 12971 010e FFF7FEFF bl HAL_DMA_GetError + 12972 .LVL869: +6170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 417 + + + 12973 .loc 1 6170 6 view .LVU4348 + 12974 0112 0228 cmp r0, #2 + 12975 0114 00D0 beq .L795 +6170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 12976 .loc 1 6170 55 discriminator 1 view .LVU4349 + 12977 0116 05B9 cbnz r5, .L809 + 12978 .L795: +6178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12979 .loc 1 6178 1 view .LVU4350 + 12980 0118 38BD pop {r3, r4, r5, pc} + 12981 .LVL870: + 12982 .L809: +6173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12983 .loc 1 6173 5 is_stmt 1 view .LVU4351 +6173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12984 .loc 1 6173 9 is_stmt 0 view .LVU4352 + 12985 011a 2268 ldr r2, [r4] +6173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12986 .loc 1 6173 25 view .LVU4353 + 12987 011c 5368 ldr r3, [r2, #4] + 12988 011e 43F40043 orr r3, r3, #32768 + 12989 0122 5360 str r3, [r2, #4] +6176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 12990 .loc 1 6176 5 is_stmt 1 view .LVU4354 + 12991 0124 1021 movs r1, #16 + 12992 0126 2046 mov r0, r4 + 12993 0128 FFF7FEFF bl I2C_ITError + 12994 .LVL871: +6178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 12995 .loc 1 6178 1 is_stmt 0 view .LVU4355 + 12996 012c F4E7 b .L795 + 12997 .L811: + 12998 012e 00BF .align 2 + 12999 .L810: + 13000 0130 10000240 .word 1073872912 + 13001 0134 28000240 .word 1073872936 + 13002 .cfi_endproc + 13003 .LFE209: + 13005 .section .text.I2C_DMAMasterTransmitCplt,"ax",%progbits + 13006 .align 1 + 13007 .syntax unified + 13008 .thumb + 13009 .thumb_func + 13010 .fpu fpv5-d16 + 13012 I2C_DMAMasterTransmitCplt: + 13013 .LVL872: + 13014 .LFB205: +5999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 13015 .loc 1 5999 1 is_stmt 1 view -0 + 13016 .cfi_startproc + 13017 @ args = 0, pretend = 0, frame = 0 + 13018 @ frame_needed = 0, uses_anonymous_args = 0 +5999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 13019 .loc 1 5999 1 is_stmt 0 view .LVU4357 + 13020 0000 10B5 push {r4, lr} + 13021 .LCFI138: + 13022 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccEimIdZ.s page 418 + + + 13023 .cfi_offset 4, -8 + 13024 .cfi_offset 14, -4 +6000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13025 .loc 1 6000 3 is_stmt 1 view .LVU4358 +6000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13026 .loc 1 6000 22 is_stmt 0 view .LVU4359 + 13027 0002 846B ldr r4, [r0, #56] + 13028 .LVL873: +6003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13029 .loc 1 6003 3 is_stmt 1 view .LVU4360 +6003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13030 .loc 1 6003 7 is_stmt 0 view .LVU4361 + 13031 0004 2268 ldr r2, [r4] +6003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13032 .loc 1 6003 23 view .LVU4362 + 13033 0006 1368 ldr r3, [r2] + 13034 0008 23F48043 bic r3, r3, #16384 + 13035 000c 1360 str r3, [r2] +6006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13036 .loc 1 6006 3 is_stmt 1 view .LVU4363 +6006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13037 .loc 1 6006 11 is_stmt 0 view .LVU4364 + 13038 000e 638D ldrh r3, [r4, #42] + 13039 0010 9BB2 uxth r3, r3 +6006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13040 .loc 1 6006 6 view .LVU4365 + 13041 0012 ABB1 cbz r3, .L819 +6015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13042 .loc 1 6015 5 is_stmt 1 view .LVU4366 +6015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13043 .loc 1 6015 27 is_stmt 0 view .LVU4367 + 13044 0014 238D ldrh r3, [r4, #40] +6015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13045 .loc 1 6015 20 view .LVU4368 + 13046 0016 616A ldr r1, [r4, #36] + 13047 0018 1944 add r1, r1, r3 + 13048 001a 6162 str r1, [r4, #36] +6018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13049 .loc 1 6018 5 is_stmt 1 view .LVU4369 +6018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13050 .loc 1 6018 13 is_stmt 0 view .LVU4370 + 13051 001c 638D ldrh r3, [r4, #42] + 13052 001e 9BB2 uxth r3, r3 +6018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13053 .loc 1 6018 8 view .LVU4371 + 13054 0020 FF2B cmp r3, #255 + 13055 0022 12D9 bls .L815 +6020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13056 .loc 1 6020 7 is_stmt 1 view .LVU4372 +6020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13057 .loc 1 6020 22 is_stmt 0 view .LVU4373 + 13058 0024 FF23 movs r3, #255 + 13059 0026 2385 strh r3, [r4, #40] @ movhi + 13060 .L816: +6028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13061 .loc 1 6028 5 is_stmt 1 view .LVU4374 +6028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 419 + + + 13062 .loc 1 6028 81 is_stmt 0 view .LVU4375 + 13063 0028 2268 ldr r2, [r4] +6028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13064 .loc 1 6028 9 view .LVU4376 + 13065 002a 238D ldrh r3, [r4, #40] + 13066 002c 2832 adds r2, r2, #40 + 13067 002e A06B ldr r0, [r4, #56] + 13068 .LVL874: +6028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13069 .loc 1 6028 9 view .LVU4377 + 13070 0030 FFF7FEFF bl HAL_DMA_Start_IT + 13071 .LVL875: +6028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13072 .loc 1 6028 8 view .LVU4378 + 13073 0034 60B1 cbz r0, .L817 +6031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13074 .loc 1 6031 7 is_stmt 1 view .LVU4379 + 13075 0036 1021 movs r1, #16 + 13076 0038 2046 mov r0, r4 + 13077 003a FFF7FEFF bl I2C_ITError + 13078 .LVL876: + 13079 .L812: +6039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13080 .loc 1 6039 1 is_stmt 0 view .LVU4380 + 13081 003e 10BD pop {r4, pc} + 13082 .LVL877: + 13083 .L819: +6009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13084 .loc 1 6009 5 is_stmt 1 view .LVU4381 + 13085 0040 2021 movs r1, #32 + 13086 0042 2046 mov r0, r4 + 13087 .LVL878: +6009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13088 .loc 1 6009 5 is_stmt 0 view .LVU4382 + 13089 0044 FFF7FEFF bl I2C_Enable_IRQ + 13090 .LVL879: + 13091 0048 F9E7 b .L812 + 13092 .LVL880: + 13093 .L815: +6024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13094 .loc 1 6024 7 is_stmt 1 view .LVU4383 +6024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13095 .loc 1 6024 28 is_stmt 0 view .LVU4384 + 13096 004a 638D ldrh r3, [r4, #42] +6024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13097 .loc 1 6024 22 view .LVU4385 + 13098 004c 2385 strh r3, [r4, #40] @ movhi + 13099 004e EBE7 b .L816 + 13100 .LVL881: + 13101 .L817: +6036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13102 .loc 1 6036 7 is_stmt 1 view .LVU4386 + 13103 0050 4021 movs r1, #64 + 13104 0052 2046 mov r0, r4 + 13105 0054 FFF7FEFF bl I2C_Enable_IRQ + 13106 .LVL882: +6039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + ARM GAS /tmp/ccEimIdZ.s page 420 + + + 13107 .loc 1 6039 1 is_stmt 0 view .LVU4387 + 13108 0058 F1E7 b .L812 + 13109 .cfi_endproc + 13110 .LFE205: + 13112 .section .text.I2C_DMAMasterReceiveCplt,"ax",%progbits + 13113 .align 1 + 13114 .syntax unified + 13115 .thumb + 13116 .thumb_func + 13117 .fpu fpv5-d16 + 13119 I2C_DMAMasterReceiveCplt: + 13120 .LVL883: + 13121 .LFB207: +6074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 13122 .loc 1 6074 1 is_stmt 1 view -0 + 13123 .cfi_startproc + 13124 @ args = 0, pretend = 0, frame = 0 + 13125 @ frame_needed = 0, uses_anonymous_args = 0 +6074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 13126 .loc 1 6074 1 is_stmt 0 view .LVU4389 + 13127 0000 10B5 push {r4, lr} + 13128 .LCFI139: + 13129 .cfi_def_cfa_offset 8 + 13130 .cfi_offset 4, -8 + 13131 .cfi_offset 14, -4 +6075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13132 .loc 1 6075 3 is_stmt 1 view .LVU4390 +6075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13133 .loc 1 6075 22 is_stmt 0 view .LVU4391 + 13134 0002 846B ldr r4, [r0, #56] + 13135 .LVL884: +6078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13136 .loc 1 6078 3 is_stmt 1 view .LVU4392 +6078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13137 .loc 1 6078 7 is_stmt 0 view .LVU4393 + 13138 0004 2268 ldr r2, [r4] +6078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13139 .loc 1 6078 23 view .LVU4394 + 13140 0006 1368 ldr r3, [r2] + 13141 0008 23F40043 bic r3, r3, #32768 + 13142 000c 1360 str r3, [r2] +6081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13143 .loc 1 6081 3 is_stmt 1 view .LVU4395 +6081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13144 .loc 1 6081 11 is_stmt 0 view .LVU4396 + 13145 000e 638D ldrh r3, [r4, #42] + 13146 0010 9BB2 uxth r3, r3 +6081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13147 .loc 1 6081 6 view .LVU4397 + 13148 0012 ABB1 cbz r3, .L827 +6090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13149 .loc 1 6090 5 is_stmt 1 view .LVU4398 +6090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13150 .loc 1 6090 27 is_stmt 0 view .LVU4399 + 13151 0014 238D ldrh r3, [r4, #40] +6090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13152 .loc 1 6090 20 view .LVU4400 + ARM GAS /tmp/ccEimIdZ.s page 421 + + + 13153 0016 626A ldr r2, [r4, #36] + 13154 0018 1A44 add r2, r2, r3 + 13155 001a 6262 str r2, [r4, #36] +6093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13156 .loc 1 6093 5 is_stmt 1 view .LVU4401 +6093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13157 .loc 1 6093 13 is_stmt 0 view .LVU4402 + 13158 001c 638D ldrh r3, [r4, #42] + 13159 001e 9BB2 uxth r3, r3 +6093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13160 .loc 1 6093 8 view .LVU4403 + 13161 0020 FF2B cmp r3, #255 + 13162 0022 12D9 bls .L823 +6095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13163 .loc 1 6095 7 is_stmt 1 view .LVU4404 +6095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13164 .loc 1 6095 22 is_stmt 0 view .LVU4405 + 13165 0024 FF23 movs r3, #255 + 13166 0026 2385 strh r3, [r4, #40] @ movhi + 13167 .L824: +6103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13168 .loc 1 6103 5 is_stmt 1 view .LVU4406 +6103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13169 .loc 1 6103 55 is_stmt 0 view .LVU4407 + 13170 0028 2168 ldr r1, [r4] +6103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13171 .loc 1 6103 9 view .LVU4408 + 13172 002a 238D ldrh r3, [r4, #40] + 13173 002c 2431 adds r1, r1, #36 + 13174 002e E06B ldr r0, [r4, #60] + 13175 .LVL885: +6103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13176 .loc 1 6103 9 view .LVU4409 + 13177 0030 FFF7FEFF bl HAL_DMA_Start_IT + 13178 .LVL886: +6103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13179 .loc 1 6103 8 view .LVU4410 + 13180 0034 60B1 cbz r0, .L825 +6106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13181 .loc 1 6106 7 is_stmt 1 view .LVU4411 + 13182 0036 1021 movs r1, #16 + 13183 0038 2046 mov r0, r4 + 13184 003a FFF7FEFF bl I2C_ITError + 13185 .LVL887: + 13186 .L820: +6114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13187 .loc 1 6114 1 is_stmt 0 view .LVU4412 + 13188 003e 10BD pop {r4, pc} + 13189 .LVL888: + 13190 .L827: +6084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13191 .loc 1 6084 5 is_stmt 1 view .LVU4413 + 13192 0040 2021 movs r1, #32 + 13193 0042 2046 mov r0, r4 + 13194 .LVL889: +6084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13195 .loc 1 6084 5 is_stmt 0 view .LVU4414 + ARM GAS /tmp/ccEimIdZ.s page 422 + + + 13196 0044 FFF7FEFF bl I2C_Enable_IRQ + 13197 .LVL890: + 13198 0048 F9E7 b .L820 + 13199 .LVL891: + 13200 .L823: +6099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13201 .loc 1 6099 7 is_stmt 1 view .LVU4415 +6099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13202 .loc 1 6099 28 is_stmt 0 view .LVU4416 + 13203 004a 638D ldrh r3, [r4, #42] +6099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13204 .loc 1 6099 22 view .LVU4417 + 13205 004c 2385 strh r3, [r4, #40] @ movhi + 13206 004e EBE7 b .L824 + 13207 .LVL892: + 13208 .L825: +6111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13209 .loc 1 6111 7 is_stmt 1 view .LVU4418 + 13210 0050 4021 movs r1, #64 + 13211 0052 2046 mov r0, r4 + 13212 0054 FFF7FEFF bl I2C_Enable_IRQ + 13213 .LVL893: +6114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13214 .loc 1 6114 1 is_stmt 0 view .LVU4419 + 13215 0058 F1E7 b .L820 + 13216 .cfi_endproc + 13217 .LFE207: + 13219 .section .text.HAL_I2C_ER_IRQHandler,"ax",%progbits + 13220 .align 1 + 13221 .global HAL_I2C_ER_IRQHandler + 13222 .syntax unified + 13223 .thumb + 13224 .thumb_func + 13225 .fpu fpv5-d16 + 13227 HAL_I2C_ER_IRQHandler: + 13228 .LVL894: + 13229 .LFB176: +4332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 13230 .loc 1 4332 1 is_stmt 1 view -0 + 13231 .cfi_startproc + 13232 @ args = 0, pretend = 0, frame = 0 + 13233 @ frame_needed = 0, uses_anonymous_args = 0 +4332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 13234 .loc 1 4332 1 is_stmt 0 view .LVU4421 + 13235 0000 10B5 push {r4, lr} + 13236 .LCFI140: + 13237 .cfi_def_cfa_offset 8 + 13238 .cfi_offset 4, -8 + 13239 .cfi_offset 14, -4 +4333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 13240 .loc 1 4333 3 is_stmt 1 view .LVU4422 +4333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 13241 .loc 1 4333 24 is_stmt 0 view .LVU4423 + 13242 0002 0268 ldr r2, [r0] +4333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 13243 .loc 1 4333 12 view .LVU4424 + 13244 0004 9369 ldr r3, [r2, #24] + ARM GAS /tmp/ccEimIdZ.s page 423 + + + 13245 .LVL895: +4334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmperror; + 13246 .loc 1 4334 3 is_stmt 1 view .LVU4425 +4334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** uint32_t tmperror; + 13247 .loc 1 4334 12 is_stmt 0 view .LVU4426 + 13248 0006 1168 ldr r1, [r2] + 13249 .LVL896: +4335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13250 .loc 1 4335 3 is_stmt 1 view .LVU4427 +4338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13251 .loc 1 4338 3 view .LVU4428 +4338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13252 .loc 1 4338 6 is_stmt 0 view .LVU4429 + 13253 0008 13F4807F tst r3, #256 + 13254 000c 09D0 beq .L829 +4338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13255 .loc 1 4338 57 discriminator 1 view .LVU4430 + 13256 000e 11F0800F tst r1, #128 + 13257 0012 06D0 beq .L829 +4340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13258 .loc 1 4340 5 is_stmt 1 view .LVU4431 +4340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13259 .loc 1 4340 21 is_stmt 0 view .LVU4432 + 13260 0014 446C ldr r4, [r0, #68] + 13261 0016 44F00104 orr r4, r4, #1 + 13262 001a 4464 str r4, [r0, #68] +4343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13263 .loc 1 4343 5 is_stmt 1 view .LVU4433 + 13264 001c 4FF48074 mov r4, #256 + 13265 0020 D461 str r4, [r2, #28] + 13266 .L829: +4347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13267 .loc 1 4347 3 view .LVU4434 +4347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13268 .loc 1 4347 6 is_stmt 0 view .LVU4435 + 13269 0022 13F4806F tst r3, #1024 + 13270 0026 0AD0 beq .L830 +4347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13271 .loc 1 4347 56 discriminator 1 view .LVU4436 + 13272 0028 11F0800F tst r1, #128 + 13273 002c 07D0 beq .L830 +4349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13274 .loc 1 4349 5 is_stmt 1 view .LVU4437 +4349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13275 .loc 1 4349 21 is_stmt 0 view .LVU4438 + 13276 002e 426C ldr r2, [r0, #68] + 13277 0030 42F00802 orr r2, r2, #8 + 13278 0034 4264 str r2, [r0, #68] +4352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13279 .loc 1 4352 5 is_stmt 1 view .LVU4439 + 13280 0036 0268 ldr r2, [r0] + 13281 0038 4FF48064 mov r4, #1024 + 13282 003c D461 str r4, [r2, #28] + 13283 .L830: +4356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13284 .loc 1 4356 3 view .LVU4440 +4356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + ARM GAS /tmp/ccEimIdZ.s page 424 + + + 13285 .loc 1 4356 6 is_stmt 0 view .LVU4441 + 13286 003e 13F4007F tst r3, #512 + 13287 0042 0AD0 beq .L831 +4356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13288 .loc 1 4356 57 discriminator 1 view .LVU4442 + 13289 0044 11F0800F tst r1, #128 + 13290 0048 07D0 beq .L831 +4358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13291 .loc 1 4358 5 is_stmt 1 view .LVU4443 +4358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13292 .loc 1 4358 21 is_stmt 0 view .LVU4444 + 13293 004a 436C ldr r3, [r0, #68] + 13294 .LVL897: +4358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13295 .loc 1 4358 21 view .LVU4445 + 13296 004c 43F00203 orr r3, r3, #2 + 13297 0050 4364 str r3, [r0, #68] +4361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13298 .loc 1 4361 5 is_stmt 1 view .LVU4446 + 13299 0052 0368 ldr r3, [r0] + 13300 0054 4FF40072 mov r2, #512 + 13301 0058 DA61 str r2, [r3, #28] + 13302 .L831: +4365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13303 .loc 1 4365 3 view .LVU4447 +4365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13304 .loc 1 4365 12 is_stmt 0 view .LVU4448 + 13305 005a 416C ldr r1, [r0, #68] + 13306 .LVL898: +4368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13307 .loc 1 4368 3 is_stmt 1 view .LVU4449 +4368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13308 .loc 1 4368 6 is_stmt 0 view .LVU4450 + 13309 005c 11F00B0F tst r1, #11 + 13310 0060 00D1 bne .L834 + 13311 .LVL899: + 13312 .L828: +4372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13313 .loc 1 4372 1 view .LVU4451 + 13314 0062 10BD pop {r4, pc} + 13315 .LVL900: + 13316 .L834: +4370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13317 .loc 1 4370 5 is_stmt 1 view .LVU4452 + 13318 0064 FFF7FEFF bl I2C_ITError + 13319 .LVL901: +4372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13320 .loc 1 4372 1 is_stmt 0 view .LVU4453 + 13321 0068 FBE7 b .L828 + 13322 .cfi_endproc + 13323 .LFE176: + 13325 .section .text.I2C_DMAAbort,"ax",%progbits + 13326 .align 1 + 13327 .syntax unified + 13328 .thumb + 13329 .thumb_func + 13330 .fpu fpv5-d16 + ARM GAS /tmp/ccEimIdZ.s page 425 + + + 13332 I2C_DMAAbort: + 13333 .LVL902: + 13334 .LFB210: +6187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 13335 .loc 1 6187 1 is_stmt 1 view -0 + 13336 .cfi_startproc + 13337 @ args = 0, pretend = 0, frame = 0 + 13338 @ frame_needed = 0, uses_anonymous_args = 0 +6187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 13339 .loc 1 6187 1 is_stmt 0 view .LVU4455 + 13340 0000 08B5 push {r3, lr} + 13341 .LCFI141: + 13342 .cfi_def_cfa_offset 8 + 13343 .cfi_offset 3, -8 + 13344 .cfi_offset 14, -4 +6188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13345 .loc 1 6188 3 is_stmt 1 view .LVU4456 +6188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13346 .loc 1 6188 22 is_stmt 0 view .LVU4457 + 13347 0002 806B ldr r0, [r0, #56] + 13348 .LVL903: +6191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13349 .loc 1 6191 3 is_stmt 1 view .LVU4458 +6191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13350 .loc 1 6191 11 is_stmt 0 view .LVU4459 + 13351 0004 836B ldr r3, [r0, #56] +6191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13352 .loc 1 6191 6 view .LVU4460 + 13353 0006 0BB1 cbz r3, .L836 +6193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13354 .loc 1 6193 5 is_stmt 1 view .LVU4461 +6193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13355 .loc 1 6193 37 is_stmt 0 view .LVU4462 + 13356 0008 0022 movs r2, #0 + 13357 000a 1A65 str r2, [r3, #80] + 13358 .L836: +6195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13359 .loc 1 6195 3 is_stmt 1 view .LVU4463 +6195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13360 .loc 1 6195 11 is_stmt 0 view .LVU4464 + 13361 000c C36B ldr r3, [r0, #60] +6195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** { + 13362 .loc 1 6195 6 view .LVU4465 + 13363 000e 0BB1 cbz r3, .L837 +6197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13364 .loc 1 6197 5 is_stmt 1 view .LVU4466 +6197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13365 .loc 1 6197 37 is_stmt 0 view .LVU4467 + 13366 0010 0022 movs r2, #0 + 13367 0012 1A65 str r2, [r3, #80] + 13368 .L837: +6200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13369 .loc 1 6200 3 is_stmt 1 view .LVU4468 + 13370 0014 FFF7FEFF bl I2C_TreatErrorCallback + 13371 .LVL904: +6201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13372 .loc 1 6201 1 is_stmt 0 view .LVU4469 + ARM GAS /tmp/ccEimIdZ.s page 426 + + + 13373 0018 08BD pop {r3, pc} + 13374 .cfi_endproc + 13375 .LFE210: + 13377 .section .text.HAL_I2C_GetState,"ax",%progbits + 13378 .align 1 + 13379 .global HAL_I2C_GetState + 13380 .syntax unified + 13381 .thumb + 13382 .thumb_func + 13383 .fpu fpv5-d16 + 13385 HAL_I2C_GetState: + 13386 .LVL905: + 13387 .LFB187: +4563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** /* Return I2C handle state */ + 13388 .loc 1 4563 1 is_stmt 1 view -0 + 13389 .cfi_startproc + 13390 @ args = 0, pretend = 0, frame = 0 + 13391 @ frame_needed = 0, uses_anonymous_args = 0 + 13392 @ link register save eliminated. +4565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13393 .loc 1 4565 3 view .LVU4471 +4565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13394 .loc 1 4565 14 is_stmt 0 view .LVU4472 + 13395 0000 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 13396 .LVL906: +4566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13397 .loc 1 4566 1 view .LVU4473 + 13398 0004 7047 bx lr + 13399 .cfi_endproc + 13400 .LFE187: + 13402 .section .text.HAL_I2C_GetMode,"ax",%progbits + 13403 .align 1 + 13404 .global HAL_I2C_GetMode + 13405 .syntax unified + 13406 .thumb + 13407 .thumb_func + 13408 .fpu fpv5-d16 + 13410 HAL_I2C_GetMode: + 13411 .LVL907: + 13412 .LFB188: +4575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return hi2c->Mode; + 13413 .loc 1 4575 1 is_stmt 1 view -0 + 13414 .cfi_startproc + 13415 @ args = 0, pretend = 0, frame = 0 + 13416 @ frame_needed = 0, uses_anonymous_args = 0 + 13417 @ link register save eliminated. +4576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13418 .loc 1 4576 3 view .LVU4475 +4576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13419 .loc 1 4576 14 is_stmt 0 view .LVU4476 + 13420 0000 90F84200 ldrb r0, [r0, #66] @ zero_extendqisi2 + 13421 .LVL908: +4577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13422 .loc 1 4577 1 view .LVU4477 + 13423 0004 7047 bx lr + 13424 .cfi_endproc + 13425 .LFE188: + ARM GAS /tmp/ccEimIdZ.s page 427 + + + 13427 .section .text.HAL_I2C_GetError,"ax",%progbits + 13428 .align 1 + 13429 .global HAL_I2C_GetError + 13430 .syntax unified + 13431 .thumb + 13432 .thumb_func + 13433 .fpu fpv5-d16 + 13435 HAL_I2C_GetError: + 13436 .LVL909: + 13437 .LFB189: +4586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** return hi2c->ErrorCode; + 13438 .loc 1 4586 1 is_stmt 1 view -0 + 13439 .cfi_startproc + 13440 @ args = 0, pretend = 0, frame = 0 + 13441 @ frame_needed = 0, uses_anonymous_args = 0 + 13442 @ link register save eliminated. +4587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13443 .loc 1 4587 3 view .LVU4479 +4587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** } + 13444 .loc 1 4587 14 is_stmt 0 view .LVU4480 + 13445 0000 406C ldr r0, [r0, #68] + 13446 .LVL910: +4588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c **** + 13447 .loc 1 4588 1 view .LVU4481 + 13448 0002 7047 bx lr + 13449 .cfi_endproc + 13450 .LFE189: + 13452 .text + 13453 .Letext0: + 13454 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 13455 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 13456 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 13457 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 13458 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 13459 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 13460 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h" + 13461 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccEimIdZ.s page 428 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_i2c.c + /tmp/ccEimIdZ.s:17 .text.I2C_Flush_TXDR:0000000000000000 $t + /tmp/ccEimIdZ.s:24 .text.I2C_Flush_TXDR:0000000000000000 I2C_Flush_TXDR + /tmp/ccEimIdZ.s:63 .text.I2C_TransferConfig:0000000000000000 $t + /tmp/ccEimIdZ.s:69 .text.I2C_TransferConfig:0000000000000000 I2C_TransferConfig + /tmp/ccEimIdZ.s:120 .text.I2C_Enable_IRQ:0000000000000000 $t + /tmp/ccEimIdZ.s:126 .text.I2C_Enable_IRQ:0000000000000000 I2C_Enable_IRQ + /tmp/ccEimIdZ.s:253 .text.I2C_Enable_IRQ:000000000000006c $d + /tmp/ccEimIdZ.s:12440 .text.I2C_Master_ISR_DMA:0000000000000000 I2C_Master_ISR_DMA + /tmp/ccEimIdZ.s:12002 .text.I2C_Slave_ISR_DMA:0000000000000000 I2C_Slave_ISR_DMA + /tmp/ccEimIdZ.s:259 .text.I2C_Disable_IRQ:0000000000000000 $t + /tmp/ccEimIdZ.s:265 .text.I2C_Disable_IRQ:0000000000000000 I2C_Disable_IRQ + /tmp/ccEimIdZ.s:389 .text.I2C_ConvertOtherXferOptions:0000000000000000 $t + /tmp/ccEimIdZ.s:395 .text.I2C_ConvertOtherXferOptions:0000000000000000 I2C_ConvertOtherXferOptions + /tmp/ccEimIdZ.s:436 .text.I2C_IsAcknowledgeFailed:0000000000000000 $t + /tmp/ccEimIdZ.s:442 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.text.I2C_DMAMasterReceiveCplt:0000000000000000 $t + /tmp/ccEimIdZ.s:13220 .text.HAL_I2C_ER_IRQHandler:0000000000000000 $t + /tmp/ccEimIdZ.s:13227 .text.HAL_I2C_ER_IRQHandler:0000000000000000 HAL_I2C_ER_IRQHandler + /tmp/ccEimIdZ.s:13326 .text.I2C_DMAAbort:0000000000000000 $t + /tmp/ccEimIdZ.s:13378 .text.HAL_I2C_GetState:0000000000000000 $t + /tmp/ccEimIdZ.s:13385 .text.HAL_I2C_GetState:0000000000000000 HAL_I2C_GetState + /tmp/ccEimIdZ.s:13403 .text.HAL_I2C_GetMode:0000000000000000 $t + /tmp/ccEimIdZ.s:13410 .text.HAL_I2C_GetMode:0000000000000000 HAL_I2C_GetMode + /tmp/ccEimIdZ.s:13428 .text.HAL_I2C_GetError:0000000000000000 $t + /tmp/ccEimIdZ.s:13435 .text.HAL_I2C_GetError:0000000000000000 HAL_I2C_GetError + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort_IT +HAL_DMA_GetState +HAL_DMA_GetError diff --git a/build/stm32h7xx_hal_i2c.o b/build/stm32h7xx_hal_i2c.o new file mode 100644 index 0000000..772b86b Binary files /dev/null and b/build/stm32h7xx_hal_i2c.o differ diff --git a/build/stm32h7xx_hal_i2c_ex.d b/build/stm32h7xx_hal_i2c_ex.d new file mode 100644 index 0000000..c347f56 --- /dev/null +++ b/build/stm32h7xx_hal_i2c_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_i2c_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_i2c_ex.lst b/build/stm32h7xx_hal_i2c_ex.lst new file mode 100644 index 0000000..7558a4d --- /dev/null +++ b/build/stm32h7xx_hal_i2c_ex.lst @@ -0,0 +1,885 @@ +ARM GAS /tmp/ccGdXrn9.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_i2c_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits + 17 .align 1 + 18 .global HAL_I2CEx_ConfigAnalogFilter + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_I2CEx_ConfigAnalogFilter: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @file stm32h7xx_hal_i2c_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * functionalities of I2C Extended peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * + Extended features functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** @verbatim + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ============================================================================== + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ##### I2C peripheral Extended features ##### + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32H7xx + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** devices contains the following additional features + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Possibility to disable or enable Analog Noise Filter + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Use of a configured Digital Noise Filter + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Disable or enable wakeup from Stop mode(s) + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Disable or enable Fast Mode Plus + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ##### How to use this driver ##### + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ============================================================================== + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** [..] This driver provides functions to configure Noise Filter and Wake Up Feature + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableWakeUp() + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableWakeUp() + ARM GAS /tmp/ccGdXrn9.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (#) Configure the enable or disable of fast mode plus driving capability using the functions : + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableFastModePlus() + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableFastModePlus() + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** @endverbatim + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ****************************************************************************** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @attention + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** *

© Copyright (c) 2017 STMicroelectronics. + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * All rights reserved.

+ 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * the "License"; You may not use this file except in compliance with the + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * License. You may obtain a copy of the License at: + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * opensource.org/licenses/BSD-3-Clause + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ****************************************************************************** + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/ + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** #include "stm32h7xx_hal.h" + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @{ + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @{ + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/ + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/ + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/ + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/ + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @{ + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Extended features functions + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** @verbatim + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** =============================================================================== + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** ##### Extended features functions ##### + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** =============================================================================== + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Configure Noise Filters + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Configure Wake Up Feature + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** @endverbatim + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @{ + ARM GAS /tmp/ccGdXrn9.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter. + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter. + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @retval HAL status + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 29 .loc 1 98 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Check the parameters */ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 34 .loc 1 100 3 view .LVU1 + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + 35 .loc 1 101 3 view .LVU2 + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 36 .loc 1 103 3 view .LVU3 + 37 .loc 1 103 11 is_stmt 0 view .LVU4 + 38 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 39 0004 DBB2 uxtb r3, r3 + 40 .loc 1 103 6 view .LVU5 + 41 0006 202B cmp r3, #32 + 42 0008 24D1 bne .L3 + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Locked */ + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 43 .loc 1 106 5 is_stmt 1 view .LVU6 + 44 .loc 1 106 5 view .LVU7 + 45 000a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 46 000e 012B cmp r3, #1 + 47 0010 22D0 beq .L4 + 48 .loc 1 106 5 discriminator 2 view .LVU8 + 49 0012 0123 movs r3, #1 + 50 0014 80F84030 strb r3, [r0, #64] + 51 .loc 1 106 5 discriminator 2 view .LVU9 + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 52 .loc 1 108 5 discriminator 2 view .LVU10 + 53 .loc 1 108 17 is_stmt 0 discriminator 2 view .LVU11 + 54 0018 2423 movs r3, #36 + 55 001a 80F84130 strb r3, [r0, #65] + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 56 .loc 1 111 5 is_stmt 1 discriminator 2 view .LVU12 + 57 001e 0268 ldr r2, [r0] + 58 0020 1368 ldr r3, [r2] + 59 0022 23F00103 bic r3, r3, #1 + 60 0026 1360 str r3, [r2] + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccGdXrn9.s page 4 + + + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */ + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 61 .loc 1 114 5 discriminator 2 view .LVU13 + 62 .loc 1 114 9 is_stmt 0 discriminator 2 view .LVU14 + 63 0028 0268 ldr r2, [r0] + 64 .loc 1 114 25 discriminator 2 view .LVU15 + 65 002a 1368 ldr r3, [r2] + 66 002c 23F48053 bic r3, r3, #4096 + 67 0030 1360 str r3, [r2] + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Set analog filter bit*/ + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter; + 68 .loc 1 117 5 is_stmt 1 discriminator 2 view .LVU16 + 69 .loc 1 117 9 is_stmt 0 discriminator 2 view .LVU17 + 70 0032 0268 ldr r2, [r0] + 71 .loc 1 117 25 discriminator 2 view .LVU18 + 72 0034 1368 ldr r3, [r2] + 73 0036 1943 orrs r1, r1, r3 + 74 .LVL1: + 75 .loc 1 117 25 discriminator 2 view .LVU19 + 76 0038 1160 str r1, [r2] + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 77 .loc 1 119 5 is_stmt 1 discriminator 2 view .LVU20 + 78 003a 0268 ldr r2, [r0] + 79 003c 1368 ldr r3, [r2] + 80 003e 43F00103 orr r3, r3, #1 + 81 0042 1360 str r3, [r2] + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 82 .loc 1 121 5 discriminator 2 view .LVU21 + 83 .loc 1 121 17 is_stmt 0 discriminator 2 view .LVU22 + 84 0044 2023 movs r3, #32 + 85 0046 80F84130 strb r3, [r0, #65] + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Unlocked */ + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 86 .loc 1 124 5 is_stmt 1 discriminator 2 view .LVU23 + 87 .loc 1 124 5 discriminator 2 view .LVU24 + 88 004a 0023 movs r3, #0 + 89 004c 80F84030 strb r3, [r0, #64] + 90 .loc 1 124 5 discriminator 2 view .LVU25 + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_OK; + 91 .loc 1 126 5 discriminator 2 view .LVU26 + 92 .loc 1 126 12 is_stmt 0 discriminator 2 view .LVU27 + 93 0050 1846 mov r0, r3 + 94 .LVL2: + 95 .loc 1 126 12 discriminator 2 view .LVU28 + 96 0052 7047 bx lr + 97 .LVL3: + 98 .L3: + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** else + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_BUSY; + 99 .loc 1 130 12 view .LVU29 + ARM GAS /tmp/ccGdXrn9.s page 5 + + + 100 0054 0220 movs r0, #2 + 101 .LVL4: + 102 .loc 1 130 12 view .LVU30 + 103 0056 7047 bx lr + 104 .LVL5: + 105 .L4: + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 106 .loc 1 106 5 view .LVU31 + 107 0058 0220 movs r0, #2 + 108 .LVL6: + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 109 .loc 1 132 1 view .LVU32 + 110 005a 7047 bx lr + 111 .cfi_endproc + 112 .LFE141: + 114 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits + 115 .align 1 + 116 .global HAL_I2CEx_ConfigDigitalFilter + 117 .syntax unified + 118 .thumb + 119 .thumb_func + 120 .fpu fpv5-d16 + 122 HAL_I2CEx_ConfigDigitalFilter: + 123 .LVL7: + 124 .LFB142: + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter. + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @retval HAL status + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 125 .loc 1 142 1 is_stmt 1 view -0 + 126 .cfi_startproc + 127 @ args = 0, pretend = 0, frame = 0 + 128 @ frame_needed = 0, uses_anonymous_args = 0 + 129 @ link register save eliminated. + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** uint32_t tmpreg; + 130 .loc 1 143 3 view .LVU34 + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Check the parameters */ + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 131 .loc 1 146 3 view .LVU35 + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + 132 .loc 1 147 3 view .LVU36 + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 133 .loc 1 149 3 view .LVU37 + 134 .loc 1 149 11 is_stmt 0 view .LVU38 + 135 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 136 0004 DBB2 uxtb r3, r3 + 137 .loc 1 149 6 view .LVU39 + 138 0006 202B cmp r3, #32 + ARM GAS /tmp/ccGdXrn9.s page 6 + + + 139 0008 22D1 bne .L7 + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Locked */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 140 .loc 1 152 5 is_stmt 1 view .LVU40 + 141 .loc 1 152 5 view .LVU41 + 142 000a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 143 000e 012B cmp r3, #1 + 144 0010 20D0 beq .L8 + 145 .loc 1 152 5 discriminator 2 view .LVU42 + 146 0012 0123 movs r3, #1 + 147 0014 80F84030 strb r3, [r0, #64] + 148 .loc 1 152 5 discriminator 2 view .LVU43 + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 149 .loc 1 154 5 discriminator 2 view .LVU44 + 150 .loc 1 154 17 is_stmt 0 discriminator 2 view .LVU45 + 151 0018 2423 movs r3, #36 + 152 001a 80F84130 strb r3, [r0, #65] + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 153 .loc 1 157 5 is_stmt 1 discriminator 2 view .LVU46 + 154 001e 0268 ldr r2, [r0] + 155 0020 1368 ldr r3, [r2] + 156 0022 23F00103 bic r3, r3, #1 + 157 0026 1360 str r3, [r2] + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Get the old register value */ + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1; + 158 .loc 1 160 5 discriminator 2 view .LVU47 + 159 .loc 1 160 18 is_stmt 0 discriminator 2 view .LVU48 + 160 0028 0268 ldr r2, [r0] + 161 .loc 1 160 12 discriminator 2 view .LVU49 + 162 002a 1368 ldr r3, [r2] + 163 .LVL8: + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */ + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF); + 164 .loc 1 163 5 is_stmt 1 discriminator 2 view .LVU50 + 165 .loc 1 163 12 is_stmt 0 discriminator 2 view .LVU51 + 166 002c 23F47063 bic r3, r3, #3840 + 167 .LVL9: + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U; + 168 .loc 1 166 5 is_stmt 1 discriminator 2 view .LVU52 + 169 .loc 1 166 12 is_stmt 0 discriminator 2 view .LVU53 + 170 0030 43EA0121 orr r1, r3, r1, lsl #8 + 171 .LVL10: + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Store the new register value */ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg; + 172 .loc 1 169 5 is_stmt 1 discriminator 2 view .LVU54 + 173 .loc 1 169 25 is_stmt 0 discriminator 2 view .LVU55 + 174 0034 1160 str r1, [r2] + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccGdXrn9.s page 7 + + + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 175 .loc 1 171 5 is_stmt 1 discriminator 2 view .LVU56 + 176 0036 0268 ldr r2, [r0] + 177 0038 1368 ldr r3, [r2] + 178 003a 43F00103 orr r3, r3, #1 + 179 003e 1360 str r3, [r2] + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 180 .loc 1 173 5 discriminator 2 view .LVU57 + 181 .loc 1 173 17 is_stmt 0 discriminator 2 view .LVU58 + 182 0040 2023 movs r3, #32 + 183 0042 80F84130 strb r3, [r0, #65] + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Unlocked */ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 184 .loc 1 176 5 is_stmt 1 discriminator 2 view .LVU59 + 185 .loc 1 176 5 discriminator 2 view .LVU60 + 186 0046 0023 movs r3, #0 + 187 0048 80F84030 strb r3, [r0, #64] + 188 .loc 1 176 5 discriminator 2 view .LVU61 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_OK; + 189 .loc 1 178 5 discriminator 2 view .LVU62 + 190 .loc 1 178 12 is_stmt 0 discriminator 2 view .LVU63 + 191 004c 1846 mov r0, r3 + 192 .LVL11: + 193 .loc 1 178 12 discriminator 2 view .LVU64 + 194 004e 7047 bx lr + 195 .LVL12: + 196 .L7: + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** else + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_BUSY; + 197 .loc 1 182 12 view .LVU65 + 198 0050 0220 movs r0, #2 + 199 .LVL13: + 200 .loc 1 182 12 view .LVU66 + 201 0052 7047 bx lr + 202 .LVL14: + 203 .L8: + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 204 .loc 1 152 5 view .LVU67 + 205 0054 0220 movs r0, #2 + 206 .LVL15: + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 207 .loc 1 184 1 view .LVU68 + 208 0056 7047 bx lr + 209 .cfi_endproc + 210 .LFE142: + 212 .section .text.HAL_I2CEx_EnableWakeUp,"ax",%progbits + 213 .align 1 + 214 .global HAL_I2CEx_EnableWakeUp + 215 .syntax unified + 216 .thumb + 217 .thumb_func + ARM GAS /tmp/ccGdXrn9.s page 8 + + + 218 .fpu fpv5-d16 + 220 HAL_I2CEx_EnableWakeUp: + 221 .LVL16: + 222 .LFB143: + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Enable I2C wakeup from Stop mode(s). + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @retval HAL status + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 223 .loc 1 193 1 is_stmt 1 view -0 + 224 .cfi_startproc + 225 @ args = 0, pretend = 0, frame = 0 + 226 @ frame_needed = 0, uses_anonymous_args = 0 + 227 @ link register save eliminated. + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Check the parameters */ + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 228 .loc 1 195 3 view .LVU70 + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 229 .loc 1 197 3 view .LVU71 + 230 .loc 1 197 11 is_stmt 0 view .LVU72 + 231 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 232 0004 DBB2 uxtb r3, r3 + 233 .loc 1 197 6 view .LVU73 + 234 0006 202B cmp r3, #32 + 235 0008 20D1 bne .L11 + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Locked */ + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 236 .loc 1 200 5 is_stmt 1 view .LVU74 + 237 .loc 1 200 5 view .LVU75 + 238 000a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 239 000e 012B cmp r3, #1 + 240 0010 1ED0 beq .L12 + 241 .loc 1 200 5 discriminator 2 view .LVU76 + 242 0012 0123 movs r3, #1 + 243 0014 80F84030 strb r3, [r0, #64] + 244 .loc 1 200 5 discriminator 2 view .LVU77 + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 245 .loc 1 202 5 discriminator 2 view .LVU78 + 246 .loc 1 202 17 is_stmt 0 discriminator 2 view .LVU79 + 247 0018 2423 movs r3, #36 + 248 001a 80F84130 strb r3, [r0, #65] + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 249 .loc 1 205 5 is_stmt 1 discriminator 2 view .LVU80 + 250 001e 0268 ldr r2, [r0] + 251 0020 1368 ldr r3, [r2] + 252 0022 23F00103 bic r3, r3, #1 + 253 0026 1360 str r3, [r2] + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccGdXrn9.s page 9 + + + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + 254 .loc 1 208 5 discriminator 2 view .LVU81 + 255 .loc 1 208 9 is_stmt 0 discriminator 2 view .LVU82 + 256 0028 0268 ldr r2, [r0] + 257 .loc 1 208 25 discriminator 2 view .LVU83 + 258 002a 1368 ldr r3, [r2] + 259 002c 43F48023 orr r3, r3, #262144 + 260 0030 1360 str r3, [r2] + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 261 .loc 1 210 5 is_stmt 1 discriminator 2 view .LVU84 + 262 0032 0268 ldr r2, [r0] + 263 0034 1368 ldr r3, [r2] + 264 0036 43F00103 orr r3, r3, #1 + 265 003a 1360 str r3, [r2] + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 266 .loc 1 212 5 discriminator 2 view .LVU85 + 267 .loc 1 212 17 is_stmt 0 discriminator 2 view .LVU86 + 268 003c 2023 movs r3, #32 + 269 003e 80F84130 strb r3, [r0, #65] + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Unlocked */ + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 270 .loc 1 215 5 is_stmt 1 discriminator 2 view .LVU87 + 271 .loc 1 215 5 discriminator 2 view .LVU88 + 272 0042 0023 movs r3, #0 + 273 0044 80F84030 strb r3, [r0, #64] + 274 .loc 1 215 5 discriminator 2 view .LVU89 + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_OK; + 275 .loc 1 217 5 discriminator 2 view .LVU90 + 276 .loc 1 217 12 is_stmt 0 discriminator 2 view .LVU91 + 277 0048 1846 mov r0, r3 + 278 .LVL17: + 279 .loc 1 217 12 discriminator 2 view .LVU92 + 280 004a 7047 bx lr + 281 .LVL18: + 282 .L11: + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** else + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_BUSY; + 283 .loc 1 221 12 view .LVU93 + 284 004c 0220 movs r0, #2 + 285 .LVL19: + 286 .loc 1 221 12 view .LVU94 + 287 004e 7047 bx lr + 288 .LVL20: + 289 .L12: + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 290 .loc 1 200 5 view .LVU95 + 291 0050 0220 movs r0, #2 + 292 .LVL21: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + ARM GAS /tmp/ccGdXrn9.s page 10 + + + 293 .loc 1 223 1 view .LVU96 + 294 0052 7047 bx lr + 295 .cfi_endproc + 296 .LFE143: + 298 .section .text.HAL_I2CEx_DisableWakeUp,"ax",%progbits + 299 .align 1 + 300 .global HAL_I2CEx_DisableWakeUp + 301 .syntax unified + 302 .thumb + 303 .thumb_func + 304 .fpu fpv5-d16 + 306 HAL_I2CEx_DisableWakeUp: + 307 .LVL22: + 308 .LFB144: + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Disable I2C wakeup from Stop mode(s). + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @retval HAL status + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 309 .loc 1 232 1 is_stmt 1 view -0 + 310 .cfi_startproc + 311 @ args = 0, pretend = 0, frame = 0 + 312 @ frame_needed = 0, uses_anonymous_args = 0 + 313 @ link register save eliminated. + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Check the parameters */ + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 314 .loc 1 234 3 view .LVU98 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 315 .loc 1 236 3 view .LVU99 + 316 .loc 1 236 11 is_stmt 0 view .LVU100 + 317 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 318 0004 DBB2 uxtb r3, r3 + 319 .loc 1 236 6 view .LVU101 + 320 0006 202B cmp r3, #32 + 321 0008 20D1 bne .L15 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Locked */ + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 322 .loc 1 239 5 is_stmt 1 view .LVU102 + 323 .loc 1 239 5 view .LVU103 + 324 000a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 325 000e 012B cmp r3, #1 + 326 0010 1ED0 beq .L16 + 327 .loc 1 239 5 discriminator 2 view .LVU104 + 328 0012 0123 movs r3, #1 + 329 0014 80F84030 strb r3, [r0, #64] + 330 .loc 1 239 5 discriminator 2 view .LVU105 + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 331 .loc 1 241 5 discriminator 2 view .LVU106 + 332 .loc 1 241 17 is_stmt 0 discriminator 2 view .LVU107 + 333 0018 2423 movs r3, #36 + ARM GAS /tmp/ccGdXrn9.s page 11 + + + 334 001a 80F84130 strb r3, [r0, #65] + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 335 .loc 1 244 5 is_stmt 1 discriminator 2 view .LVU108 + 336 001e 0268 ldr r2, [r0] + 337 0020 1368 ldr r3, [r2] + 338 0022 23F00103 bic r3, r3, #1 + 339 0026 1360 str r3, [r2] + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + 340 .loc 1 247 5 discriminator 2 view .LVU109 + 341 .loc 1 247 9 is_stmt 0 discriminator 2 view .LVU110 + 342 0028 0268 ldr r2, [r0] + 343 .loc 1 247 25 discriminator 2 view .LVU111 + 344 002a 1368 ldr r3, [r2] + 345 002c 23F48023 bic r3, r3, #262144 + 346 0030 1360 str r3, [r2] + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 347 .loc 1 249 5 is_stmt 1 discriminator 2 view .LVU112 + 348 0032 0268 ldr r2, [r0] + 349 0034 1368 ldr r3, [r2] + 350 0036 43F00103 orr r3, r3, #1 + 351 003a 1360 str r3, [r2] + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 352 .loc 1 251 5 discriminator 2 view .LVU113 + 353 .loc 1 251 17 is_stmt 0 discriminator 2 view .LVU114 + 354 003c 2023 movs r3, #32 + 355 003e 80F84130 strb r3, [r0, #65] + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Process Unlocked */ + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 356 .loc 1 254 5 is_stmt 1 discriminator 2 view .LVU115 + 357 .loc 1 254 5 discriminator 2 view .LVU116 + 358 0042 0023 movs r3, #0 + 359 0044 80F84030 strb r3, [r0, #64] + 360 .loc 1 254 5 discriminator 2 view .LVU117 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_OK; + 361 .loc 1 256 5 discriminator 2 view .LVU118 + 362 .loc 1 256 12 is_stmt 0 discriminator 2 view .LVU119 + 363 0048 1846 mov r0, r3 + 364 .LVL23: + 365 .loc 1 256 12 discriminator 2 view .LVU120 + 366 004a 7047 bx lr + 367 .LVL24: + 368 .L15: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** else + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** return HAL_BUSY; + 369 .loc 1 260 12 view .LVU121 + 370 004c 0220 movs r0, #2 + 371 .LVL25: + ARM GAS /tmp/ccGdXrn9.s page 12 + + + 372 .loc 1 260 12 view .LVU122 + 373 004e 7047 bx lr + 374 .LVL26: + 375 .L16: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 376 .loc 1 239 5 view .LVU123 + 377 0050 0220 movs r0, #2 + 378 .LVL27: + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 379 .loc 1 262 1 view .LVU124 + 380 0052 7047 bx lr + 381 .cfi_endproc + 382 .LFE144: + 384 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits + 385 .align 1 + 386 .global HAL_I2CEx_EnableFastModePlus + 387 .syntax unified + 388 .thumb + 389 .thumb_func + 390 .fpu fpv5-d16 + 392 HAL_I2CEx_EnableFastModePlus: + 393 .LVL28: + 394 .LFB145: + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability. + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C4 pins fast mode plus driving capability can be enabled + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C4 parameter. + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C5 pins fast mode plus driving capability can be enabled + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C5 parameter. + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @retval None + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 395 .loc 1 284 1 is_stmt 1 view -0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 8 + 398 @ frame_needed = 0, uses_anonymous_args = 0 + 399 @ link register save eliminated. + 400 .loc 1 284 1 is_stmt 0 view .LVU126 + 401 0000 82B0 sub sp, sp, #8 + 402 .LCFI0: + 403 .cfi_def_cfa_offset 8 + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Check the parameter */ + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + ARM GAS /tmp/ccGdXrn9.s page 13 + + + 404 .loc 1 286 3 is_stmt 1 view .LVU127 + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 405 .loc 1 289 3 view .LVU128 + 406 .LBB2: + 407 .loc 1 289 3 view .LVU129 + 408 .loc 1 289 3 view .LVU130 + 409 0002 094A ldr r2, .L19 + 410 0004 D2F8F410 ldr r1, [r2, #244] + 411 0008 41F00201 orr r1, r1, #2 + 412 000c C2F8F410 str r1, [r2, #244] + 413 .loc 1 289 3 view .LVU131 + 414 0010 D2F8F420 ldr r2, [r2, #244] + 415 0014 02F00202 and r2, r2, #2 + 416 0018 0192 str r2, [sp, #4] + 417 .loc 1 289 3 view .LVU132 + 418 001a 019B ldr r3, [sp, #4] + 419 .LBE2: + 420 .loc 1 289 3 view .LVU133 + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */ + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); + 421 .loc 1 292 3 view .LVU134 + 422 001c 034A ldr r2, .L19+4 + 423 001e 5368 ldr r3, [r2, #4] + 424 0020 0343 orrs r3, r3, r0 + 425 0022 5360 str r3, [r2, #4] + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + 426 .loc 1 293 1 is_stmt 0 view .LVU135 + 427 0024 02B0 add sp, sp, #8 + 428 .LCFI1: + 429 .cfi_def_cfa_offset 0 + 430 @ sp needed + 431 0026 7047 bx lr + 432 .L20: + 433 .align 2 + 434 .L19: + 435 0028 00440258 .word 1476543488 + 436 002c 00040058 .word 1476396032 + 437 .cfi_endproc + 438 .LFE145: + 440 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits + 441 .align 1 + 442 .global HAL_I2CEx_DisableFastModePlus + 443 .syntax unified + 444 .thumb + 445 .thumb_func + 446 .fpu fpv5-d16 + 448 HAL_I2CEx_DisableFastModePlus: + 449 .LVL29: + 450 .LFB146: + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /** + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability. + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + ARM GAS /tmp/ccGdXrn9.s page 14 + + + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C4 pins fast mode plus driving capability can be disabled + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C4 parameter. + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @note For all I2C5 pins fast mode plus driving capability can be disabled + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C5 parameter. + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** * @retval None + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** */ + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** { + 451 .loc 1 315 1 is_stmt 1 view -0 + 452 .cfi_startproc + 453 @ args = 0, pretend = 0, frame = 8 + 454 @ frame_needed = 0, uses_anonymous_args = 0 + 455 @ link register save eliminated. + 456 .loc 1 315 1 is_stmt 0 view .LVU137 + 457 0000 82B0 sub sp, sp, #8 + 458 .LCFI2: + 459 .cfi_def_cfa_offset 8 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Check the parameter */ + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 460 .loc 1 317 3 is_stmt 1 view .LVU138 + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 461 .loc 1 320 3 view .LVU139 + 462 .LBB3: + 463 .loc 1 320 3 view .LVU140 + 464 .loc 1 320 3 view .LVU141 + 465 0002 0A4A ldr r2, .L23 + 466 0004 D2F8F410 ldr r1, [r2, #244] + 467 0008 41F00201 orr r1, r1, #2 + 468 000c C2F8F410 str r1, [r2, #244] + 469 .loc 1 320 3 view .LVU142 + 470 0010 D2F8F420 ldr r2, [r2, #244] + 471 0014 02F00202 and r2, r2, #2 + 472 0018 0192 str r2, [sp, #4] + 473 .loc 1 320 3 view .LVU143 + 474 001a 019B ldr r3, [sp, #4] + 475 .LBE3: + 476 .loc 1 320 3 view .LVU144 + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); + 477 .loc 1 323 3 view .LVU145 + 478 001c 044A ldr r2, .L23+4 + 479 001e 5368 ldr r3, [r2, #4] + 480 0020 23EA0003 bic r3, r3, r0 + 481 0024 5360 str r3, [r2, #4] + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c **** } + ARM GAS /tmp/ccGdXrn9.s page 15 + + + 482 .loc 1 324 1 is_stmt 0 view .LVU146 + 483 0026 02B0 add sp, sp, #8 + 484 .LCFI3: + 485 .cfi_def_cfa_offset 0 + 486 @ sp needed + 487 0028 7047 bx lr + 488 .L24: + 489 002a 00BF .align 2 + 490 .L23: + 491 002c 00440258 .word 1476543488 + 492 0030 00040058 .word 1476396032 + 493 .cfi_endproc + 494 .LFE146: + 496 .text + 497 .Letext0: + 498 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 499 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 500 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 501 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 502 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 503 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h" + ARM GAS /tmp/ccGdXrn9.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_i2c_ex.c + /tmp/ccGdXrn9.s:17 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 $t + /tmp/ccGdXrn9.s:25 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 HAL_I2CEx_ConfigAnalogFilter + /tmp/ccGdXrn9.s:115 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 $t + /tmp/ccGdXrn9.s:122 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 HAL_I2CEx_ConfigDigitalFilter + /tmp/ccGdXrn9.s:213 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 $t + /tmp/ccGdXrn9.s:220 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 HAL_I2CEx_EnableWakeUp + /tmp/ccGdXrn9.s:299 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 $t + /tmp/ccGdXrn9.s:306 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 HAL_I2CEx_DisableWakeUp + /tmp/ccGdXrn9.s:385 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 $t + /tmp/ccGdXrn9.s:392 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 HAL_I2CEx_EnableFastModePlus + /tmp/ccGdXrn9.s:435 .text.HAL_I2CEx_EnableFastModePlus:0000000000000028 $d + /tmp/ccGdXrn9.s:441 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 $t + /tmp/ccGdXrn9.s:448 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 HAL_I2CEx_DisableFastModePlus + /tmp/ccGdXrn9.s:491 .text.HAL_I2CEx_DisableFastModePlus:000000000000002c $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_i2c_ex.o b/build/stm32h7xx_hal_i2c_ex.o new file mode 100644 index 0000000..cbc30f7 Binary files /dev/null and b/build/stm32h7xx_hal_i2c_ex.o differ diff --git a/build/stm32h7xx_hal_mdma.d b/build/stm32h7xx_hal_mdma.d new file mode 100644 index 0000000..deb2d33 --- /dev/null +++ b/build/stm32h7xx_hal_mdma.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_mdma.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_mdma.lst b/build/stm32h7xx_hal_mdma.lst new file mode 100644 index 0000000..2d7d383 --- /dev/null +++ b/build/stm32h7xx_hal_mdma.lst @@ -0,0 +1,6854 @@ +ARM GAS /tmp/ccBjdYa2.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_mdma.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.MDMA_SetConfig,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 MDMA_SetConfig: + 25 .LVL0: + 26 .LFB160: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @file stm32h7xx_hal_mdma.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief This file provides firmware functions to manage the following + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * functionalities of the Master Direct Memory Access (MDMA) peripheral: + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + Initialization/de-initialization functions + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + I/O operation functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + Peripheral State and errors functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @verbatim + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ============================================================================== + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ##### How to use this driver ##### + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (#) Enable and configure the peripheral to be connected to the MDMA Channel + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (except for internal SRAM/FLASH memories: no initialization is + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** necessary) please refer to Reference manual for connection between peripherals + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** and MDMA requests. + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (#) + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** For a given Channel use HAL_MDMA_Init function to program the required configuration through + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** transfer request , channel priority, data endianness, Source increment, destination incremen + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** source data size, destination data size, data alignment, source Burst, destination Burst , + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated blo + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** or full transfer) source and destination block address offset, mask address and data. + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fi + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** last node of the list to the first one in order to make the list circular. + ARM GAS /tmp/ccBjdYa2.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** In this case the linked list will loop on node 1 : first node connected after the initial tr + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -@- The initial transfer itself (node 0 corresponding to the Init). + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMo + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** the connection between last node and first one. + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the t + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** When a linked list is circular (last node connected to first one), if removing node1 (node + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** the linked list remains circular and node 2 becomes the first one. + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Note that if the linked list is made circular the transfer will loop infinitely (or until ab + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** transfer upon a request : + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength d + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** with BufferTransferLength defined within the HAL_MDMA_Init. + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** or within the current linked list node parameters. + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of bloc + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_ + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** or within the current linked list node parameters. + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) MDMA_FULL_TRANSFER : each request triggers a full transfer + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_ + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** *** Polling mode IO operation *** + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ================================= + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** address and destination address and the Length of data to be transferred. + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** In this case a fixed Timeout can be configured by User depending from his application. + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this AP + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** when the abort ends or timeout (should not be called from an interrupt service routin + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** *** Interrupt mode IO operation *** + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =================================== + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority() + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ() + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Source address and destination address and the Length of data to be transferred. In t + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case the MDMA interrupt is configured. + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** add his own function by customization of function pointer XferCpltCallback and + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** XferErrorCallback (i.e a member of MDMA handle structure). + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** then the callback XferAbortCallback (if specified by the user) is asserted once the + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (could be called from an interrupt service routine). + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** from the following list : + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) XferCpltCallback : transfer complete callback. + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) XferBufferCpltCallback : buffer transfer complete callback. + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) XferBlockCpltCallback : block transfer complete callback. + ARM GAS /tmp/ccBjdYa2.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback. + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) XferErrorCallback : transfer error callback. + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) XferAbortCallback : transfer abort complete callback. + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use func + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) This function returns an error if used while the Transfer has ended or not start + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) If used while the current request has not been served yet (current request trans + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** this function returns an error and the new request is ignored. + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Generally this function should be used in conjunctions with the MDMA callbacks: + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) example 1: + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode se + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) Register a callback for buffer transfer complete (using callback ID set to H + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) When the buffer transfer complete callback is asserted first buffer has been + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** request using HAL_MDMA_GenerateSWRequest. + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (++) example 2: + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode se + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_ + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+++) When the block transfer complete callback is asserted the first block has be + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** for a new block transfer request using HAL_MDMA_GenerateSWRequest. + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** *** MDMA HAL driver macros list *** + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ============================================= + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Below the list of most used macros in MDMA HAL driver. + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel. + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel. + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags. + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags. + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts. + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts. + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (@) You can refer to the header file of the MDMA HAL driver for more useful macros. + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @endverbatim + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ****************************************************************************** + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @attention + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * All rights reserved.

+ 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * This software component is licensed by ST under BSD 3-Clause license, + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the "License"; You may not use this file except in compliance with the + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * License. You may obtain a copy of the License at: + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * opensource.org/licenses/BSD-3-Clause + ARM GAS /tmp/ccBjdYa2.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ****************************************************************************** + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Includes ------------------------------------------------------------------*/ + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** #include "stm32h7xx_hal.h" + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup STM32H7xx_HAL_Driver + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @defgroup MDMA MDMA + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief MDMA HAL module driver + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** #ifdef HAL_MDMA_MODULE_ENABLED + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Private typedef -----------------------------------------------------------*/ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Private constants ---------------------------------------------------------*/ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Private_Constants + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** #define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** #define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */ + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Private macro -------------------------------------------------------------*/ + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Private variables ---------------------------------------------------------*/ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Private function prototypes -----------------------------------------------*/ + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Private_Functions_Prototypes + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uin + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** static void MDMA_Init(MDMA_HandleTypeDef *hmdma); + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Exported_Functions MDMA Exported Functions + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Exported_Functions_Group1 + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @verbatim + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ##### Initialization and de-initialization functions ##### + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** This section provides functions allowing to : + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Initialize and de-initialize the MDMA channel. + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Register and Unregister MDMA callbacks + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in + ARM GAS /tmp/ccBjdYa2.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** reference manual. + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel. + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** respectevely to register/unregister an MDMA callback function. + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @endverbatim + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Initializes the MDMA according to the specified + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * parameters in the MDMA_InitTypeDef and create the associated handle. + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart = HAL_GetTick(); + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance)); + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority)); + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness)); + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_REQUEST(hmdma->Init.Request)); + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc)); + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc)); + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize)); + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize)); + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment)); + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst)); + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst)); + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength)); + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode)); + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Allocate lock resource */ + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the MDMA channel */ + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check if the MDMA channel is effectively disabled */ + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check for the Timeout */ + ARM GAS /tmp/ccBjdYa2.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code */ + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT; + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change the MDMA state */ + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_ERROR; + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the MDMA channel registers */ + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_Init(hmdma); + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Reset the MDMA first/last linkedlist node addresses and node counter */ + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = 0; + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the error code */ + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the MDMA state */ + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief DeInitializes the MDMA peripheral + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma) + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the selected MDMA Channelx */ + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Reset MDMA Channel control register */ + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CCR = 0; + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR = 0; + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR = 0; + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CSAR = 0; + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CDAR = 0; + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = 0; + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = 0; + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR = 0; + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMAR = 0; + ARM GAS /tmp/ccBjdYa2.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = 0; + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear all flags */ + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_F + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Reset the MDMA first/last linkedlist node addresses and node counter */ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = 0; + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the error code */ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the MDMA state */ + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_RESET; + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Release Lock */ + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Config the Post request Mask address and Mask data + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param MaskAddress: specifies the address to be updated (written) with MaskData after a reques + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param MaskData: specifies the value to be written to MaskAddress after a request is served + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * MaskAddress and MaskData could be used to automatically clear a peripheral + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, u + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if HW request set Post Request MaskAddress and MaskData, */ + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U) + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request clear Mask and Data */ + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMAR = MaskAddress; + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = MaskData; + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -If the request is done by SW : BWM could be set to 1 or 0. + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -If the request is done by a peripheral : + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If mask address not set (0) => BWM must be set to 0 + ARM GAS /tmp/ccBjdYa2.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If mask address set (different than 0) => BWM could be set to 1 or 0 + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(MaskAddress == 0U) + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM; + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR |= MDMA_CTCR_BWM; + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** status = HAL_ERROR; + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** status = HAL_ERROR; + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Release Lock */ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return status; + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Register callbacks + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param CallbackID: User Callback identifier + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param pCallback: pointer to callbacsk function. + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef C + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** switch (CallbackID) + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_CPLT_CB_ID: + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferCpltCallback = pCallback; + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBufferCpltCallback = pCallback; + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBlockCpltCallback = pCallback; + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferRepeatBlockCpltCallback = pCallback; + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_ERROR_CB_ID: + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferErrorCallback = pCallback; + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_ABORT_CB_ID: + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferAbortCallback = pCallback; + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** default: + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** status = HAL_ERROR; + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Release Lock */ + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return status; + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief UnRegister callbacks + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param CallbackID: User Callback identifier + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * a HAL_MDMA_CallbackIDTypeDef ENUM as parameter. + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** switch (CallbackID) + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_CPLT_CB_ID: + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferCpltCallback = NULL; + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBufferCpltCallback = NULL; + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBlockCpltCallback = NULL; + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferRepeatBlockCpltCallback = NULL; + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_ERROR_CB_ID: + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferErrorCallback = NULL; + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_ABORT_CB_ID: + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferAbortCallback = NULL; + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** case HAL_MDMA_XFER_ALL_CB_ID: + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferCpltCallback = NULL; + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBufferCpltCallback = NULL; + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBlockCpltCallback = NULL; + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferRepeatBlockCpltCallback = NULL; + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferErrorCallback = NULL; + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferAbortCallback = NULL; + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** default: + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** status = HAL_ERROR; + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** status = HAL_ERROR; + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Release Lock */ + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return status; + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Exported_Functions_Group2 + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @verbatim + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ##### Linked list operation functions ##### + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] This section provides functions allowing to: + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Create a linked list node + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Add a node to the MDMA linked list + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Remove a node from the MDMA linked list + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Enable/Disable linked list circular mode + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @endverbatim + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Initializes an MDMA Link Node according to the specified + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * parameters in the pMDMA_LinkedListNodeConfig . + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * registers configurations. + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Linked List Node. + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfType + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t addressMask; + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t blockoffset; + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral state */ + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((pNode == NULL) || (pNodeConfig == NULL)) + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority)); + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness)); + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request)); + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc)); + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc)); + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize)); + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize)); + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment)); + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst)); + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst)); + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength)); + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode)); + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset)); + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset)); + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength)); + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure next Link node Address Register to zero */ + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CLAR = 0; + ARM GAS /tmp/ccBjdYa2.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure the Link Node registers*/ + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTBR = 0; + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMAR = 0; + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = 0; + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->Reserved = 0; + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CTCR Register value */ + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \ + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DestBurst | \ + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.TransferTriggerMode; + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* If SW request set the CTCR register to SW Request Mode*/ + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNodeConfig->Init.Request == MDMA_REQUEST_SW) + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTCR |= MDMA_CTCR_SWRM; + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -If the request is done by SW : BWM could be set to 1 or 0. + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -If the request is done by a peripheral : + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If mask address not set (0) => BWM must be set to 0 + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If mask address set (different than 0) => BWM could be set to 1 or 0 + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U)) + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTCR |= MDMA_CTCR_BWM; + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the new CBNDTR Register value */ + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC; + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if block source address offset is negative set the Block Repeat Source address Update Mode to + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNodeConfig->Init.SourceBlockAddressOffset < 0) + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBNDTR |= MDMA_CBNDTR_BRSUM; + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : source repeat block offset */ + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset); + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR = blockoffset & 0x0000FFFFU; + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : source repeat block offset */ + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if block destination address offset is negative set the Block Repeat destination address Updat + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNodeConfig->Init.DestBlockAddressOffset < 0) + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBNDTR |= MDMA_CBNDTR_BRDUM; + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : destination repeat block offset */ + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset); + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + ARM GAS /tmp/ccBjdYa2.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : destination repeat block offset */ + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_C + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure MDMA Link Node data length */ + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBNDTR |= pNodeConfig->BlockDataLength; + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure MDMA Link Node destination address */ + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CDAR = pNodeConfig->DstAddress; + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure MDMA Link Node Source address */ + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CSAR = pNodeConfig->SrcAddress; + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNodeConfig->Init.Request != MDMA_REQUEST_SW) + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request in CTBR register */ + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL; + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request clear Mask and Data */ + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMAR = pNodeConfig->PostRequestMaskAddress; + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = pNodeConfig->PostRequestMaskData; + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** addressMask = pNodeConfig->SrcAddress & 0xFF000000U; + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*The AHBSbus is used as source (read operation) on channel x */ + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTBR |= MDMA_CTBR_SBUS; + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** addressMask = pNodeConfig->DstAddress & 0xFF000000U; + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*The AHB bus is used as destination (write operation) on channel x */ + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CTBR |= MDMA_CTBR_DBUS; + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Connect a node to the linked list. + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * to be add to the list. + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the ne + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * at the end of the list + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNew + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_LinkNodeTypeDef *pNode; + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t counter = 0, nodeInserted = 0; + ARM GAS /tmp/ccBjdYa2.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((hmdma == NULL) || (pNewNode == NULL)) + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check if this is the first node (after the Inititlization node) */ + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pPrevNode == NULL) + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if this is the first node after the initialization + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** connect this node to the node 0 by updating + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** the MDMA channel CLAR register to this node address */ + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = (uint32_t)pNewNode; + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the MDMA handle First linked List node*/ + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = pNewNode; + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*reset New node link */ + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNewNode->CLAR = 0; + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle last node address */ + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = pNewNode; + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 1; + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else if(hmdma->FirstLinkedListNodeAddress != pNewNode) + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check if the node to insert already exists*/ + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode = hmdma->FirstLinkedListNodeAddress; + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK)) + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNode->CLAR == (uint32_t)pNewNode) + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** counter++; + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hal_status == HAL_OK) + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check if the previous node is the last one in the current list or zero */ + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL)) + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* insert the new node at the end of the list */ + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR; + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle last node address */ + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = pNewNode; + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Increment the linked list node counter */ + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter++; + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*insert the new node after the pPreviousNode node */ + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode = hmdma->FirstLinkedListNodeAddress; + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** counter = 0; + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U)) + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** counter++; + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNode == pPrevNode) + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*Insert the new node after the previous one */ + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNewNode->CLAR = pNode->CLAR; + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CLAR = (uint32_t)pNewNode; + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Increment the linked list node counter */ + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter++; + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeInserted = 1; + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(nodeInserted == 0U) + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hal_status; + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + ARM GAS /tmp/ccBjdYa2.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_BUSY; + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Disconnect/Remove a node from the transfer linked list. + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * to be removed from the list. + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *p + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_LinkNodeTypeDef *ptmpNode; + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t counter = 0, nodeDeleted = 0; + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((hmdma == NULL) || (pNode == NULL)) + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* If first and last node are null (no nodes in the list) : return error*/ + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeA + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */ + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Delete 1st node */ + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->LastLinkedListNodeAddress == pNode) + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*if the last node is at the same time the first one (1 single node after the init node 0) + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** then update the last node too */ + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = 0; + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = 0; + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR) + ARM GAS /tmp/ccBjdYa2.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if last node is looping to first (circular list) one update the last node connection * + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR; + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if deleting the first node after the initialization + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** connect the next node to the node 0 by updating + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** the MDMA channel CLAR register to this node address */ + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = pNode->CLAR; + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter--; + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else /* Deleting any other node */ + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*Deleted node is not the first one : find it */ + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ptmpNode = hmdma->FirstLinkedListNodeAddress; + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U)) + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** counter++; + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(ptmpNode->CLAR == ((uint32_t)pNode)) + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if deleting the last node */ + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNode == hmdma->LastLinkedListNodeAddress) + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*Update the linked list last node address in the handle*/ + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = ptmpNode; + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* update the next node link after deleting pMDMA_LinkedListNode */ + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ptmpNode->CLAR = pNode->CLAR; + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeDeleted = 1; + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter--; + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR; + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(nodeDeleted == 0U) + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* last node reashed without finding the node to delete : return error */ + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hal_status; + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_BUSY; + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Make the linked list circular by connecting the last node to the first. + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma) + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* If first and last node are null (no nodes in the list) : return error*/ + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeA + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* to enable circular mode Last Node should be connected to first node */ + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hal_status; + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Disable the linked list circular mode by setting the last node connection to null + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status + ARM GAS /tmp/ccBjdYa2.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma) +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* If first and last node are null (no nodes in the list) : return error*/ +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeA +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hal_status = HAL_ERROR; +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* to disable circular mode Last Node should be connected to NULL */ +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = 0; +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hal_status; +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Exported_Functions_Group3 +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @verbatim +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ##### IO operation functions ##### +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] This section provides functions allowing to: +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Configure the source, destination address and data length and Start MDMA transfer +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Configure the source, destination address and data length and +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Start MDMA transfer with interrupt +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Abort MDMA transfer +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Poll for transfer complete +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW) +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Handle MDMA interrupt request + ARM GAS /tmp/ccBjdYa2.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @endverbatim +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Starts the MDMA Transfer. +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param SrcAddress : The source memory Buffer address +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param DstAddress : The destination memory Buffer address +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param BlockDataLength : The length of a block transfer in bytes +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param BlockCount : The number of a blocks to be transfer +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddres +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the error code */ +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the peripheral */ +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure the source, destination address and the data length */ +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Enable the Peripheral */ +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_ENABLE(hmdma); +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->Init.Request == MDMA_REQUEST_SW) +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* activate If SW request mode*/ +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CCR |= MDMA_CCR_SWRQ; +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); + ARM GAS /tmp/ccBjdYa2.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_BUSY; +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Starts the MDMA Transfer with interrupts enabled. +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param SrcAddress : The source memory Buffer address +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param DstAddress : The destination memory Buffer address +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param BlockDataLength : The length of a block transfer in bytes +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param BlockCount : The number of a blocks to be transfer +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAdd +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process locked */ +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_LOCK(hmdma); +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_READY == hmdma->State) +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_BUSY; +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Initialize the error code */ +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the peripheral */ +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure the source, destination address and the data length */ +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/ +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC)); +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferBlockCpltCallback != NULL) +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if Block transfer complete Callback is set enable the corresponding IT*/ +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT); +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferRepeatBlockCpltCallback != NULL) + ARM GAS /tmp/ccBjdYa2.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/ +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT); +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferBufferCpltCallback != NULL) +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if buffer transfer complete Callback is set enable the corresponding IT*/ +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC); +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Enable the Peripheral */ +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_ENABLE(hmdma); +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->Init.Request == MDMA_REQUEST_SW) +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* activate If SW request mode*/ +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CCR |= MDMA_CCR_SWRQ; +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Return error status */ +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_BUSY; +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Aborts the MDMA Transfer. +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * effectively disabled is added. If a Channel is disabled +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * while a data transfer is ongoing, the current data will be transferred +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * and the Channel will be effectively disabled only after the transfer of +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * this single data is finished. +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart = HAL_GetTick(); +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_BUSY != hmdma->State) +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + ARM GAS /tmp/ccBjdYa2.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process Unlocked */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable all the transfer interrupts */ +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFT +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the channel */ +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check if the MDMA Channel is effectively disabled */ +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check for the Timeout */ +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code */ +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process Unlocked */ +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change the MDMA state */ +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_ERROR; +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear all interrupt flags */ +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDM +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process Unlocked */ +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change the MDMA state*/ +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Aborts the MDMA Transfer in Interrupt mode. +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma) +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_BUSY != hmdma->State) +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* No transfer ongoing */ +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set Abort State */ +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_ABORT; +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the stream */ +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Polling for transfer complete. +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param CompleteLevel: Specifies the MDMA level complete. +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param Timeout: Timeout duration. +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t levelFlag, errorFlag; +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart; +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel)); +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_BUSY != hmdma->State) +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* No transfer ongoing */ +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Get the level transfer complete flag */ +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \ +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_FLAG_BRT); + ARM GAS /tmp/ccBjdYa2.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Get timeout */ +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** tickstart = HAL_GetTick(); +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U) +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Get the transfer error source flag */ +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** errorFlag = hmdma->Instance->CESR; +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_TED) == 0U) +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Read Transfer error */ +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Write Transfer error */ +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_TEMD) != 0U) +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Error Mask Data */ +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_TELD) != 0U) +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Error Linked list */ +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_ASE) != 0U) +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Address/Size alignment error */ +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_BSE) != 0U) +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Block Size error */ +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */ +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Note that the Abort function will +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** - Clear all transfer flags +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** - Unlock +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** - Set the State +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; + ARM GAS /tmp/ccBjdYa2.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check for the Timeout */ +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(Timeout != HAL_MAX_DELAY) +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code */ +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */ +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** Note that the Abort function will +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** - Clear all transfer flags +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** - Unlock +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** - Set the State +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear the transfer level flag */ +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER) +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT)); +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER) +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT)); +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER) +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC)); +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process unlocked */ +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Generate an MDMA SW request trigger to activate the request on the given Channel. +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Stream. +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma) +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t request_mode; +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma == NULL) +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Get the softawre request mode */ +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM; +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U) +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if no Transfer on going (MDMA enable bit not set) retrun error */ +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U)) +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_ERROR; +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the SW request bit to activate the request on the Channel */ +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CCR |= MDMA_CCR_SWRQ; +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return HAL_OK; +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Handles MDMA interrupt request. +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval None +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __IO uint32_t count = 0; +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t timeout = SystemCoreClock / 9600U; +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t generalIntFlag, errorFlag; +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* General Interrupt Flag management ****************************************/ +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANN + ARM GAS /tmp/ccBjdYa2.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((MDMA->GISR0 & generalIntFlag) == 0U) +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return; /* the General interrupt flag for the current channel is down , nothing to do */ +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Transfer Error Interrupt management ***************************************/ +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U) +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the transfer error interrupt */ +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE); +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Get the transfer error source flag */ +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** errorFlag = hmdma->Instance->CESR; +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_TED) == 0U) +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Read Transfer error */ +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Write Transfer error */ +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_TEMD) != 0U) +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Error Mask Data */ +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_TELD) != 0U) +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Error Linked list */ +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_ASE) != 0U) +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Address/Size alignment error */ +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((errorFlag & MDMA_CESR_BSE) != 0U) +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update error code : Block Size error error */ +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear the transfer error flags */ +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Buffer Transfer Complete Interrupt management ******************************/ + ARM GAS /tmp/ccBjdYa2.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U)) +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U) +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear the buffer transfer complete flag */ +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferBufferCpltCallback != NULL) +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Buffer transfer callback */ +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBufferCpltCallback(hmdma); +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Block Transfer Complete Interrupt management ******************************/ +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U)) +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U) +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear the block transfer complete flag */ +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT); +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferBlockCpltCallback != NULL) +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Block transfer callback */ +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBlockCpltCallback(hmdma); +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Repeated Block Transfer Complete Interrupt management ******************************/ +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U)) +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U) +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear the repeat block transfer complete flag */ +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT); +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferRepeatBlockCpltCallback != NULL) +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Repeated Block transfer callback */ +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferRepeatBlockCpltCallback(hmdma); +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Channel Transfer Complete Interrupt management ***********************************/ +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U)) +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U) +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable all the transfer interrupts */ +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_B +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(HAL_MDMA_STATE_ABORT == hmdma->State) +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process Unlocked */ +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change the DMA state */ +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferAbortCallback != NULL) +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferAbortCallback(hmdma); +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return; +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear the Channel Transfer Complete flag */ +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC); +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process Unlocked */ +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change MDMA peripheral state */ +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->XferCpltCallback != NULL) +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Channel Transfer Complete callback */ +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferCpltCallback(hmdma); +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* manage error case */ +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE) +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_ABORT; +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Disable the channel */ +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_DISABLE(hmdma); +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** do +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if (++count > timeout) +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U); +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Process Unlocked */ +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_UNLOCK(hmdma); +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change the MDMA state to error if MDMA disable fails */ +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_ERROR; +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Change the MDMA state to Ready if MDMA disable success */ +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->State = HAL_MDMA_STATE_READY; +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if (hmdma->XferErrorCallback != NULL) +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Transfer error callback */ +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferErrorCallback(hmdma); +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Exported_Functions_Group4 +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @verbatim +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ##### State and Errors functions ##### +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** =============================================================================== +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** [..] +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** This subsection provides functions allowing to +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Check the MDMA state +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (+) Get error code +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** @endverbatim +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Returns the MDMA state. +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL state +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hmdma->State; +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Return the MDMA error code +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval MDMA Error Code +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hmdma->ErrorCode; +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ + ARM GAS /tmp/ccBjdYa2.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @} +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** @addtogroup MDMA_Private_Functions +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @{ +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Sets the MDMA Transfer parameter. +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param SrcAddress: The source memory Buffer address +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param DstAddress: The destination memory Buffer address +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param BlockDataLength : The length of a block transfer in bytes +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param BlockCount: The number of blocks to be transfered +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval HAL status +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uin +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 28 .loc 1 1762 1 view -0 + 29 .cfi_startproc + 30 @ args = 4, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 1762 1 is_stmt 0 view .LVU1 + 34 0000 70B4 push {r4, r5, r6} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 12 + 37 .cfi_offset 4, -12 + 38 .cfi_offset 5, -8 + 39 .cfi_offset 6, -4 +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t addressMask; + 40 .loc 1 1763 3 is_stmt 1 view .LVU2 +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure the MDMA Channel data length */ +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT)); + 41 .loc 1 1766 3 view .LVU3 + 42 0002 0568 ldr r5, [r0] + 43 0004 6E69 ldr r6, [r5, #20] + 44 0006 1F4C ldr r4, .L7 + 45 0008 3440 ands r4, r4, r6 + 46 000a C3F31003 ubfx r3, r3, #0, #17 + 47 .LVL1: + 48 .loc 1 1766 3 is_stmt 0 view .LVU4 + 49 000e 1C43 orrs r4, r4, r3 + 50 0010 6C61 str r4, [r5, #20] +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure the MDMA block repeat count */ +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) + 51 .loc 1 1769 3 is_stmt 1 view .LVU5 + 52 0012 0568 ldr r5, [r0] + 53 0014 6B69 ldr r3, [r5, #20] + 54 0016 C3F31303 ubfx r3, r3, #0, #20 + 55 001a 039C ldr r4, [sp, #12] + 56 001c 013C subs r4, r4, #1 + ARM GAS /tmp/ccBjdYa2.s page 33 + + + 57 001e 43EA0453 orr r3, r3, r4, lsl #20 + 58 0022 6B61 str r3, [r5, #20] +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Clear all interrupt flags */ +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MD + 59 .loc 1 1772 3 view .LVU6 + 60 0024 0368 ldr r3, [r0] + 61 0026 1F24 movs r4, #31 + 62 0028 5C60 str r4, [r3, #4] +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure MDMA Channel destination address */ +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CDAR = DstAddress; + 63 .loc 1 1775 3 view .LVU7 + 64 .loc 1 1775 8 is_stmt 0 view .LVU8 + 65 002a 0368 ldr r3, [r0] + 66 .loc 1 1775 25 view .LVU9 + 67 002c DA61 str r2, [r3, #28] +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Configure MDMA Channel Source address */ +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CSAR = SrcAddress; + 68 .loc 1 1778 3 is_stmt 1 view .LVU10 + 69 .loc 1 1778 8 is_stmt 0 view .LVU11 + 70 002e 0368 ldr r3, [r0] + 71 .loc 1 1778 25 view .LVU12 + 72 0030 9961 str r1, [r3, #24] +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** addressMask = SrcAddress & 0xFF000000U; + 73 .loc 1 1780 3 is_stmt 1 view .LVU13 + 74 .loc 1 1780 15 is_stmt 0 view .LVU14 + 75 0032 01F07F41 and r1, r1, #-16777216 + 76 .LVL2: +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 77 .loc 1 1781 3 is_stmt 1 view .LVU15 + 78 .loc 1 1781 5 is_stmt 0 view .LVU16 + 79 0036 0029 cmp r1, #0 + 80 0038 18BF it ne + 81 003a B1F1005F cmpne r1, #536870912 + 82 003e 15D1 bne .L2 +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*The AHBSbus is used as source (read operation) on channel x */ +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR |= MDMA_CTBR_SBUS; + 83 .loc 1 1784 5 is_stmt 1 view .LVU17 + 84 .loc 1 1784 10 is_stmt 0 view .LVU18 + 85 0040 0168 ldr r1, [r0] + 86 .LVL3: + 87 .loc 1 1784 27 view .LVU19 + 88 0042 8B6A ldr r3, [r1, #40] + 89 .LVL4: + 90 .loc 1 1784 27 view .LVU20 + 91 0044 43F48033 orr r3, r3, #65536 + 92 0048 8B62 str r3, [r1, #40] + 93 .L3: +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*The AXI bus is used as source (read operation) on channel x */ +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS); + ARM GAS /tmp/ccBjdYa2.s page 34 + + +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** addressMask = DstAddress & 0xFF000000U; + 94 .loc 1 1792 3 is_stmt 1 view .LVU21 + 95 .loc 1 1792 15 is_stmt 0 view .LVU22 + 96 004a 02F07F42 and r2, r2, #-16777216 + 97 .LVL5: +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 98 .loc 1 1793 3 is_stmt 1 view .LVU23 + 99 .loc 1 1793 5 is_stmt 0 view .LVU24 + 100 004e 002A cmp r2, #0 + 101 0050 18BF it ne + 102 0052 B2F1005F cmpne r2, #536870912 + 103 0056 0FD1 bne .L4 +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*The AHB bus is used as destination (write operation) on channel x */ +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR |= MDMA_CTBR_DBUS; + 104 .loc 1 1796 5 is_stmt 1 view .LVU25 + 105 .loc 1 1796 10 is_stmt 0 view .LVU26 + 106 0058 0268 ldr r2, [r0] + 107 .LVL6: + 108 .loc 1 1796 27 view .LVU27 + 109 005a 936A ldr r3, [r2, #40] + 110 005c 43F40033 orr r3, r3, #131072 + 111 0060 9362 str r3, [r2, #40] + 112 .L5: +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*The AXI bus is used as destination (write operation) on channel x */ +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS); +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the linked list register to the first node of the list */ +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; + 113 .loc 1 1805 3 is_stmt 1 view .LVU28 + 114 .loc 1 1805 42 is_stmt 0 view .LVU29 + 115 0062 C26D ldr r2, [r0, #92] + 116 .loc 1 1805 8 view .LVU30 + 117 0064 0368 ldr r3, [r0] + 118 .loc 1 1805 25 view .LVU31 + 119 0066 5A62 str r2, [r3, #36] +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 120 .loc 1 1806 1 view .LVU32 + 121 0068 70BC pop {r4, r5, r6} + 122 .LCFI1: + 123 .cfi_remember_state + 124 .cfi_restore 6 + 125 .cfi_restore 5 + 126 .cfi_restore 4 + 127 .cfi_def_cfa_offset 0 + 128 .LVL7: + 129 .loc 1 1806 1 view .LVU33 + 130 006a 7047 bx lr + 131 .LVL8: + 132 .L2: + 133 .LCFI2: + ARM GAS /tmp/ccBjdYa2.s page 35 + + + 134 .cfi_restore_state +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 135 .loc 1 1789 5 is_stmt 1 view .LVU34 +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 136 .loc 1 1789 10 is_stmt 0 view .LVU35 + 137 006c 0168 ldr r1, [r0] + 138 .LVL9: +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 139 .loc 1 1789 27 view .LVU36 + 140 006e 8B6A ldr r3, [r1, #40] + 141 .LVL10: +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 142 .loc 1 1789 27 view .LVU37 + 143 0070 23F48033 bic r3, r3, #65536 + 144 0074 8B62 str r3, [r1, #40] +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 145 .loc 1 1789 27 view .LVU38 + 146 0076 E8E7 b .L3 + 147 .LVL11: + 148 .L4: +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 149 .loc 1 1801 5 is_stmt 1 view .LVU39 +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 150 .loc 1 1801 10 is_stmt 0 view .LVU40 + 151 0078 0268 ldr r2, [r0] + 152 .LVL12: +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 153 .loc 1 1801 27 view .LVU41 + 154 007a 936A ldr r3, [r2, #40] + 155 007c 23F40033 bic r3, r3, #131072 + 156 0080 9362 str r3, [r2, #40] + 157 0082 EEE7 b .L5 + 158 .L8: + 159 .align 2 + 160 .L7: + 161 0084 0000FEFF .word -131072 + 162 .cfi_endproc + 163 .LFE160: + 165 .section .text.MDMA_Init,"ax",%progbits + 166 .align 1 + 167 .syntax unified + 168 .thumb + 169 .thumb_func + 170 .fpu fpv5-d16 + 172 MDMA_Init: + 173 .LVL13: + 174 .LFB161: +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /** +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @brief Initializes the MDMA handle according to the specified +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * parameters in the MDMA_InitTypeDef +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * the configuration information for the specified MDMA Channel. +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** * @retval None +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** static void MDMA_Init(MDMA_HandleTypeDef *hmdma) +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 36 + + + 175 .loc 1 1816 1 is_stmt 1 view -0 + 176 .cfi_startproc + 177 @ args = 0, pretend = 0, frame = 0 + 178 @ frame_needed = 0, uses_anonymous_args = 0 + 179 @ link register save eliminated. +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t blockoffset; + 180 .loc 1 1817 3 view .LVU43 +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Prepare the MDMA Channel configuration */ +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness; + 181 .loc 1 1820 3 view .LVU44 + 182 .loc 1 1820 37 is_stmt 0 view .LVU45 + 183 0000 C368 ldr r3, [r0, #12] + 184 .loc 1 1820 61 view .LVU46 + 185 0002 0169 ldr r1, [r0, #16] + 186 .loc 1 1820 8 view .LVU47 + 187 0004 0268 ldr r2, [r0] + 188 .loc 1 1820 48 view .LVU48 + 189 0006 0B43 orrs r3, r3, r1 + 190 .loc 1 1820 24 view .LVU49 + 191 0008 D360 str r3, [r2, #12] +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CTCR Register value */ +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ + 192 .loc 1 1823 3 is_stmt 1 view .LVU50 + 193 .loc 1 1823 39 is_stmt 0 view .LVU51 + 194 000a 4369 ldr r3, [r0, #20] + 195 .loc 1 1823 68 view .LVU52 + 196 000c 8269 ldr r2, [r0, #24] + 197 .loc 1 1823 55 view .LVU53 + 198 000e 1343 orrs r3, r3, r2 +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + 199 .loc 1 1824 39 view .LVU54 + 200 0010 C269 ldr r2, [r0, #28] +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + 201 .loc 1 1823 84 view .LVU55 + 202 0012 1343 orrs r3, r3, r2 + 203 .loc 1 1824 68 view .LVU56 + 204 0014 026A ldr r2, [r0, #32] + 205 .loc 1 1824 55 view .LVU57 + 206 0016 1343 orrs r3, r3, r2 +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ + 207 .loc 1 1825 39 view .LVU58 + 208 0018 426A ldr r2, [r0, #36] +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + 209 .loc 1 1824 84 view .LVU59 + 210 001a 1343 orrs r3, r3, r2 + 211 .loc 1 1825 68 view .LVU60 + 212 001c C26A ldr r2, [r0, #44] + 213 .loc 1 1825 55 view .LVU61 + 214 001e 1343 orrs r3, r3, r2 +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.DestBurst | \ + 215 .loc 1 1826 39 view .LVU62 + 216 0020 026B ldr r2, [r0, #48] +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ + 217 .loc 1 1825 84 view .LVU63 + 218 0022 1343 orrs r3, r3, r2 + ARM GAS /tmp/ccBjdYa2.s page 37 + + +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + 219 .loc 1 1827 41 view .LVU64 + 220 0024 826A ldr r2, [r0, #40] + 221 .loc 1 1827 63 view .LVU65 + 222 0026 013A subs r2, r2, #1 +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.DestBurst | \ + 223 .loc 1 1826 84 view .LVU66 + 224 0028 43EA8243 orr r3, r3, r2, lsl #18 +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.TransferTriggerMode; + 225 .loc 1 1828 39 view .LVU67 + 226 002c 8168 ldr r1, [r0, #8] +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + 227 .loc 1 1823 8 view .LVU68 + 228 002e 0268 ldr r2, [r0] +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + 229 .loc 1 1827 92 view .LVU69 + 230 0030 0B43 orrs r3, r3, r1 +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + 231 .loc 1 1823 25 view .LVU70 + 232 0032 1361 str r3, [r2, #16] +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* If SW request set the CTCR register to SW Request Mode */ +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->Init.Request == MDMA_REQUEST_SW) + 233 .loc 1 1831 3 is_stmt 1 view .LVU71 + 234 .loc 1 1831 17 is_stmt 0 view .LVU72 + 235 0034 4368 ldr r3, [r0, #4] + 236 .loc 1 1831 5 view .LVU73 + 237 0036 B3F1804F cmp r3, #1073741824 + 238 003a 1BD0 beq .L17 + 239 .L10: +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -If the request is done by SW : BWM could be set to 1 or 0. +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** -If the request is done by a peripheral : +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If mask address not set (0) => BWM must be set to 0 +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** If mask address set (different than 0) => BWM could be set to 1 or 0 +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** */ +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM); +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Reset CBNDTR Register */ +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR = 0; + 240 .loc 1 1843 3 is_stmt 1 view .LVU74 + 241 .loc 1 1843 8 is_stmt 0 view .LVU75 + 242 003c 0368 ldr r3, [r0] + 243 .loc 1 1843 27 view .LVU76 + 244 003e 0022 movs r2, #0 + 245 0040 5A61 str r2, [r3, #20] +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if block source address offset is negative set the Block Repeat Source address Update Mode to +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->Init.SourceBlockAddressOffset < 0) + 246 .loc 1 1846 3 is_stmt 1 view .LVU77 + 247 .loc 1 1846 17 is_stmt 0 view .LVU78 + 248 0042 436B ldr r3, [r0, #52] + 249 .loc 1 1846 5 view .LVU79 + 250 0044 9342 cmp r3, r2 + 251 0046 1BDB blt .L18 + ARM GAS /tmp/ccBjdYa2.s page 38 + + +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM; +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : source repeat block offset */ +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset); +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : source repeat block offset */ +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + 252 .loc 1 1856 5 is_stmt 1 view .LVU80 + 253 .loc 1 1856 10 is_stmt 0 view .LVU81 + 254 0048 0268 ldr r2, [r0] + 255 .loc 1 1856 80 view .LVU82 + 256 004a 9BB2 uxth r3, r3 + 257 .loc 1 1856 28 view .LVU83 + 258 004c 1362 str r3, [r2, #32] + 259 .L12: +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* If block destination address offset is negative set the Block Repeat destination address Updat +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->Init.DestBlockAddressOffset < 0) + 260 .loc 1 1860 3 is_stmt 1 view .LVU84 + 261 .loc 1 1860 17 is_stmt 0 view .LVU85 + 262 004e 836B ldr r3, [r0, #56] + 263 .loc 1 1860 5 view .LVU86 + 264 0050 002B cmp r3, #0 + 265 0052 20DB blt .L19 +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM; +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : destination repeat block offset */ +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset); +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : destination repeat block offset */ +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MD + 266 .loc 1 1870 5 is_stmt 1 view .LVU87 + 267 .loc 1 1870 10 is_stmt 0 view .LVU88 + 268 0054 0168 ldr r1, [r0] + 269 .loc 1 1870 28 view .LVU89 + 270 0056 0A6A ldr r2, [r1, #32] + 271 0058 42EA0343 orr r3, r2, r3, lsl #16 + 272 005c 0B62 str r3, [r1, #32] + 273 .L14: +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(hmdma->Init.Request != MDMA_REQUEST_SW) + 274 .loc 1 1874 3 is_stmt 1 view .LVU90 + 275 .loc 1 1874 17 is_stmt 0 view .LVU91 + 276 005e 4368 ldr r3, [r0, #4] + 277 .loc 1 1874 5 view .LVU92 + 278 0060 B3F1804F cmp r3, #1073741824 + 279 0064 24D0 beq .L15 +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 39 + + +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request in CTRB register */ +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; + 280 .loc 1 1877 5 is_stmt 1 view .LVU93 + 281 .loc 1 1877 10 is_stmt 0 view .LVU94 + 282 0066 0268 ldr r2, [r0] + 283 .loc 1 1877 49 view .LVU95 + 284 0068 DBB2 uxtb r3, r3 + 285 .loc 1 1877 27 view .LVU96 + 286 006a 9362 str r3, [r2, #40] + 287 .L16: +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** else /* SW request : reset the CTBR register */ +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR = 0; +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write Link Address Register */ +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = 0; + 288 .loc 1 1885 3 is_stmt 1 view .LVU97 + 289 .loc 1 1885 8 is_stmt 0 view .LVU98 + 290 006c 0368 ldr r3, [r0] + 291 .loc 1 1885 25 view .LVU99 + 292 006e 0022 movs r2, #0 + 293 0070 5A62 str r2, [r3, #36] +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 294 .loc 1 1886 1 view .LVU100 + 295 0072 7047 bx lr + 296 .L17: +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 297 .loc 1 1839 5 is_stmt 1 view .LVU101 +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 298 .loc 1 1839 10 is_stmt 0 view .LVU102 + 299 0074 0268 ldr r2, [r0] +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 300 .loc 1 1839 27 view .LVU103 + 301 0076 1369 ldr r3, [r2, #16] + 302 0078 43F04043 orr r3, r3, #-1073741824 + 303 007c 1361 str r3, [r2, #16] + 304 007e DDE7 b .L10 + 305 .L18: +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : source repeat block offset */ + 306 .loc 1 1848 5 is_stmt 1 view .LVU104 +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : source repeat block offset */ + 307 .loc 1 1848 10 is_stmt 0 view .LVU105 + 308 0080 0268 ldr r2, [r0] +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : source repeat block offset */ + 309 .loc 1 1848 29 view .LVU106 + 310 0082 5369 ldr r3, [r2, #20] + 311 0084 43F48023 orr r3, r3, #262144 + 312 0088 5361 str r3, [r2, #20] +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); + 313 .loc 1 1850 5 is_stmt 1 view .LVU107 +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); + 314 .loc 1 1850 43 is_stmt 0 view .LVU108 + 315 008a 436B ldr r3, [r0, #52] +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); + 316 .loc 1 1850 30 view .LVU109 + ARM GAS /tmp/ccBjdYa2.s page 40 + + + 317 008c 5B42 rsbs r3, r3, #0 + 318 .LVL14: +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 319 .loc 1 1851 5 is_stmt 1 view .LVU110 +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 320 .loc 1 1851 10 is_stmt 0 view .LVU111 + 321 008e 0268 ldr r2, [r0] +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 322 .loc 1 1851 43 view .LVU112 + 323 0090 9BB2 uxth r3, r3 + 324 .LVL15: +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 325 .loc 1 1851 28 view .LVU113 + 326 0092 1362 str r3, [r2, #32] + 327 .LVL16: +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 328 .loc 1 1851 28 view .LVU114 + 329 0094 DBE7 b .L12 + 330 .L19: +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : destination repeat block offset */ + 331 .loc 1 1862 5 is_stmt 1 view .LVU115 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : destination repeat block offset */ + 332 .loc 1 1862 10 is_stmt 0 view .LVU116 + 333 0096 0268 ldr r2, [r0] +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Write new CBRUR Register value : destination repeat block offset */ + 334 .loc 1 1862 29 view .LVU117 + 335 0098 5369 ldr r3, [r2, #20] + 336 009a 43F40023 orr r3, r3, #524288 + 337 009e 5361 str r3, [r2, #20] +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 338 .loc 1 1864 5 is_stmt 1 view .LVU118 +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 339 .loc 1 1864 43 is_stmt 0 view .LVU119 + 340 00a0 836B ldr r3, [r0, #56] +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 341 .loc 1 1864 30 view .LVU120 + 342 00a2 5A42 rsbs r2, r3, #0 + 343 .LVL17: +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 344 .loc 1 1865 5 is_stmt 1 view .LVU121 +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 345 .loc 1 1865 10 is_stmt 0 view .LVU122 + 346 00a4 0168 ldr r1, [r0] +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 347 .loc 1 1865 28 view .LVU123 + 348 00a6 0B6A ldr r3, [r1, #32] + 349 00a8 43EA0243 orr r3, r3, r2, lsl #16 + 350 00ac 0B62 str r3, [r1, #32] + 351 00ae D6E7 b .L14 + 352 .LVL18: + 353 .L15: +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 354 .loc 1 1881 5 is_stmt 1 view .LVU124 +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 355 .loc 1 1881 10 is_stmt 0 view .LVU125 + 356 00b0 0368 ldr r3, [r0] +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + ARM GAS /tmp/ccBjdYa2.s page 41 + + + 357 .loc 1 1881 27 view .LVU126 + 358 00b2 0022 movs r2, #0 + 359 00b4 9A62 str r2, [r3, #40] + 360 00b6 D9E7 b .L16 + 361 .cfi_endproc + 362 .LFE161: + 364 .section .text.HAL_MDMA_Init,"ax",%progbits + 365 .align 1 + 366 .global HAL_MDMA_Init + 367 .syntax unified + 368 .thumb + 369 .thumb_func + 370 .fpu fpv5-d16 + 372 HAL_MDMA_Init: + 373 .LVL19: + 374 .LFB141: + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart = HAL_GetTick(); + 375 .loc 1 220 1 is_stmt 1 view -0 + 376 .cfi_startproc + 377 @ args = 0, pretend = 0, frame = 0 + 378 @ frame_needed = 0, uses_anonymous_args = 0 + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart = HAL_GetTick(); + 379 .loc 1 220 1 is_stmt 0 view .LVU128 + 380 0000 38B5 push {r3, r4, r5, lr} + 381 .LCFI3: + 382 .cfi_def_cfa_offset 16 + 383 .cfi_offset 3, -16 + 384 .cfi_offset 4, -12 + 385 .cfi_offset 5, -8 + 386 .cfi_offset 14, -4 + 387 0002 0446 mov r4, r0 + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 388 .loc 1 221 3 is_stmt 1 view .LVU129 + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 389 .loc 1 221 24 is_stmt 0 view .LVU130 + 390 0004 FFF7FEFF bl HAL_GetTick + 391 .LVL20: + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 392 .loc 1 224 3 is_stmt 1 view .LVU131 + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 393 .loc 1 224 5 is_stmt 0 view .LVU132 + 394 0008 44B3 cbz r4, .L24 + 395 000a 0546 mov r5, r0 + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority)); + 396 .loc 1 230 3 is_stmt 1 view .LVU133 + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness)); + 397 .loc 1 231 3 view .LVU134 + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_REQUEST(hmdma->Init.Request)); + 398 .loc 1 232 3 view .LVU135 + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc)); + 399 .loc 1 233 3 view .LVU136 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc)); + 400 .loc 1 234 3 view .LVU137 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize)); + 401 .loc 1 235 3 view .LVU138 + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize)); + 402 .loc 1 236 3 view .LVU139 + ARM GAS /tmp/ccBjdYa2.s page 42 + + + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment)); + 403 .loc 1 237 3 view .LVU140 + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst)); + 404 .loc 1 238 3 view .LVU141 + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst)); + 405 .loc 1 239 3 view .LVU142 + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength)); + 406 .loc 1 240 3 view .LVU143 + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode)); + 407 .loc 1 241 3 view .LVU144 + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); + 408 .loc 1 242 3 view .LVU145 + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); + 409 .loc 1 243 3 view .LVU146 + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 410 .loc 1 244 3 view .LVU147 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 411 .loc 1 248 3 view .LVU148 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 412 .loc 1 248 3 view .LVU149 + 413 000c 0023 movs r3, #0 + 414 000e 84F83C30 strb r3, [r4, #60] + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 415 .loc 1 248 3 view .LVU150 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 416 .loc 1 251 3 view .LVU151 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 417 .loc 1 251 16 is_stmt 0 view .LVU152 + 418 0012 0223 movs r3, #2 + 419 0014 84F83D30 strb r3, [r4, #61] + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 420 .loc 1 254 3 is_stmt 1 view .LVU153 + 421 0018 2268 ldr r2, [r4] + 422 001a D368 ldr r3, [r2, #12] + 423 001c 23F00103 bic r3, r3, #1 + 424 0020 D360 str r3, [r2, #12] + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 425 .loc 1 257 3 view .LVU154 + 426 .LVL21: + 427 .L22: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 428 .loc 1 257 8 view .LVU155 + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 429 .loc 1 257 15 is_stmt 0 view .LVU156 + 430 0022 2368 ldr r3, [r4] + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 431 .loc 1 257 25 view .LVU157 + 432 0024 DB68 ldr r3, [r3, #12] + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 433 .loc 1 257 8 view .LVU158 + 434 0026 13F0010F tst r3, #1 + 435 002a 0BD0 beq .L26 + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 436 .loc 1 260 5 is_stmt 1 view .LVU159 + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 437 .loc 1 260 9 is_stmt 0 view .LVU160 + 438 002c FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccBjdYa2.s page 43 + + + 439 .LVL22: + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 440 .loc 1 260 23 view .LVU161 + 441 0030 431B subs r3, r0, r5 + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 442 .loc 1 260 7 view .LVU162 + 443 0032 052B cmp r3, #5 + 444 0034 F5D9 bls .L22 + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 445 .loc 1 263 7 is_stmt 1 view .LVU163 + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 446 .loc 1 263 24 is_stmt 0 view .LVU164 + 447 0036 4023 movs r3, #64 + 448 0038 A366 str r3, [r4, #104] + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 449 .loc 1 266 7 is_stmt 1 view .LVU165 + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 450 .loc 1 266 20 is_stmt 0 view .LVU166 + 451 003a 0323 movs r3, #3 + 452 003c 84F83D30 strb r3, [r4, #61] + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 453 .loc 1 268 7 is_stmt 1 view .LVU167 + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 454 .loc 1 268 14 is_stmt 0 view .LVU168 + 455 0040 0120 movs r0, #1 + 456 0042 0AE0 b .L21 + 457 .L26: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 458 .loc 1 273 3 is_stmt 1 view .LVU169 + 459 0044 2046 mov r0, r4 + 460 0046 FFF7FEFF bl MDMA_Init + 461 .LVL23: + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 462 .loc 1 276 3 view .LVU170 + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 463 .loc 1 276 38 is_stmt 0 view .LVU171 + 464 004a 0020 movs r0, #0 + 465 004c E065 str r0, [r4, #92] + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 466 .loc 1 277 3 is_stmt 1 view .LVU172 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 467 .loc 1 277 38 is_stmt 0 view .LVU173 + 468 004e 2066 str r0, [r4, #96] + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 469 .loc 1 278 3 is_stmt 1 view .LVU174 + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 470 .loc 1 278 33 is_stmt 0 view .LVU175 + 471 0050 6066 str r0, [r4, #100] + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 472 .loc 1 281 3 is_stmt 1 view .LVU176 + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 473 .loc 1 281 20 is_stmt 0 view .LVU177 + 474 0052 A066 str r0, [r4, #104] + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 475 .loc 1 284 3 is_stmt 1 view .LVU178 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 476 .loc 1 284 16 is_stmt 0 view .LVU179 + ARM GAS /tmp/ccBjdYa2.s page 44 + + + 477 0054 0123 movs r3, #1 + 478 0056 84F83D30 strb r3, [r4, #61] + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 479 .loc 1 286 3 is_stmt 1 view .LVU180 + 480 .LVL24: + 481 .L21: + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 482 .loc 1 287 1 is_stmt 0 view .LVU181 + 483 005a 38BD pop {r3, r4, r5, pc} + 484 .LVL25: + 485 .L24: + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 486 .loc 1 226 12 view .LVU182 + 487 005c 0120 movs r0, #1 + 488 .LVL26: + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 489 .loc 1 226 12 view .LVU183 + 490 005e FCE7 b .L21 + 491 .cfi_endproc + 492 .LFE141: + 494 .section .text.HAL_MDMA_DeInit,"ax",%progbits + 495 .align 1 + 496 .global HAL_MDMA_DeInit + 497 .syntax unified + 498 .thumb + 499 .thumb_func + 500 .fpu fpv5-d16 + 502 HAL_MDMA_DeInit: + 503 .LVL27: + 504 .LFB142: + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 505 .loc 1 296 1 is_stmt 1 view -0 + 506 .cfi_startproc + 507 @ args = 0, pretend = 0, frame = 0 + 508 @ frame_needed = 0, uses_anonymous_args = 0 + 509 @ link register save eliminated. + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 510 .loc 1 299 3 view .LVU185 + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 511 .loc 1 299 5 is_stmt 0 view .LVU186 + 512 0000 0346 mov r3, r0 + 513 0002 0028 cmp r0, #0 + 514 0004 25D0 beq .L29 + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 515 .loc 1 305 3 is_stmt 1 view .LVU187 + 516 0006 0168 ldr r1, [r0] + 517 0008 CA68 ldr r2, [r1, #12] + 518 000a 22F00102 bic r2, r2, #1 + 519 000e CA60 str r2, [r1, #12] + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR = 0; + 520 .loc 1 308 3 view .LVU188 + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR = 0; + 521 .loc 1 308 8 is_stmt 0 view .LVU189 + 522 0010 0268 ldr r2, [r0] + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR = 0; + 523 .loc 1 308 25 view .LVU190 + 524 0012 0020 movs r0, #0 + ARM GAS /tmp/ccBjdYa2.s page 45 + + + 525 .LVL28: + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTCR = 0; + 526 .loc 1 308 25 view .LVU191 + 527 0014 D060 str r0, [r2, #12] + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR = 0; + 528 .loc 1 309 3 is_stmt 1 view .LVU192 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR = 0; + 529 .loc 1 309 8 is_stmt 0 view .LVU193 + 530 0016 1A68 ldr r2, [r3] + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBNDTR = 0; + 531 .loc 1 309 25 view .LVU194 + 532 0018 1061 str r0, [r2, #16] + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CSAR = 0; + 533 .loc 1 310 3 is_stmt 1 view .LVU195 + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CSAR = 0; + 534 .loc 1 310 8 is_stmt 0 view .LVU196 + 535 001a 1A68 ldr r2, [r3] + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CSAR = 0; + 536 .loc 1 310 27 view .LVU197 + 537 001c 5061 str r0, [r2, #20] + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CDAR = 0; + 538 .loc 1 311 3 is_stmt 1 view .LVU198 + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CDAR = 0; + 539 .loc 1 311 8 is_stmt 0 view .LVU199 + 540 001e 1A68 ldr r2, [r3] + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CDAR = 0; + 541 .loc 1 311 25 view .LVU200 + 542 0020 9061 str r0, [r2, #24] + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = 0; + 543 .loc 1 312 3 is_stmt 1 view .LVU201 + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = 0; + 544 .loc 1 312 8 is_stmt 0 view .LVU202 + 545 0022 1A68 ldr r2, [r3] + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CBRUR = 0; + 546 .loc 1 312 25 view .LVU203 + 547 0024 D061 str r0, [r2, #28] + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = 0; + 548 .loc 1 313 3 is_stmt 1 view .LVU204 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = 0; + 549 .loc 1 313 8 is_stmt 0 view .LVU205 + 550 0026 1A68 ldr r2, [r3] + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CLAR = 0; + 551 .loc 1 313 26 view .LVU206 + 552 0028 1062 str r0, [r2, #32] + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR = 0; + 553 .loc 1 314 3 is_stmt 1 view .LVU207 + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR = 0; + 554 .loc 1 314 8 is_stmt 0 view .LVU208 + 555 002a 1A68 ldr r2, [r3] + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CTBR = 0; + 556 .loc 1 314 25 view .LVU209 + 557 002c 5062 str r0, [r2, #36] + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMAR = 0; + 558 .loc 1 315 3 is_stmt 1 view .LVU210 + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMAR = 0; + 559 .loc 1 315 8 is_stmt 0 view .LVU211 + 560 002e 1A68 ldr r2, [r3] + ARM GAS /tmp/ccBjdYa2.s page 46 + + + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMAR = 0; + 561 .loc 1 315 25 view .LVU212 + 562 0030 9062 str r0, [r2, #40] + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = 0; + 563 .loc 1 316 3 is_stmt 1 view .LVU213 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = 0; + 564 .loc 1 316 8 is_stmt 0 view .LVU214 + 565 0032 1A68 ldr r2, [r3] + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = 0; + 566 .loc 1 316 25 view .LVU215 + 567 0034 1063 str r0, [r2, #48] + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 568 .loc 1 317 3 is_stmt 1 view .LVU216 + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 569 .loc 1 317 8 is_stmt 0 view .LVU217 + 570 0036 1A68 ldr r2, [r3] + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 571 .loc 1 317 25 view .LVU218 + 572 0038 5063 str r0, [r2, #52] + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 573 .loc 1 320 3 is_stmt 1 view .LVU219 + 574 003a 1A68 ldr r2, [r3] + 575 003c 1F21 movs r1, #31 + 576 003e 5160 str r1, [r2, #4] + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 577 .loc 1 323 3 view .LVU220 + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 578 .loc 1 323 38 is_stmt 0 view .LVU221 + 579 0040 D865 str r0, [r3, #92] + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 580 .loc 1 324 3 is_stmt 1 view .LVU222 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 581 .loc 1 324 38 is_stmt 0 view .LVU223 + 582 0042 1866 str r0, [r3, #96] + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 583 .loc 1 325 3 is_stmt 1 view .LVU224 + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 584 .loc 1 325 33 is_stmt 0 view .LVU225 + 585 0044 5866 str r0, [r3, #100] + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 586 .loc 1 328 3 is_stmt 1 view .LVU226 + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 587 .loc 1 328 20 is_stmt 0 view .LVU227 + 588 0046 9866 str r0, [r3, #104] + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 589 .loc 1 331 3 is_stmt 1 view .LVU228 + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 590 .loc 1 331 16 is_stmt 0 view .LVU229 + 591 0048 83F83D00 strb r0, [r3, #61] + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 592 .loc 1 334 3 is_stmt 1 view .LVU230 + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 593 .loc 1 334 3 view .LVU231 + 594 004c 83F83C00 strb r0, [r3, #60] + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 595 .loc 1 334 3 view .LVU232 + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + ARM GAS /tmp/ccBjdYa2.s page 47 + + + 596 .loc 1 336 3 view .LVU233 + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 597 .loc 1 336 10 is_stmt 0 view .LVU234 + 598 0050 7047 bx lr + 599 .LVL29: + 600 .L29: + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 601 .loc 1 301 12 view .LVU235 + 602 0052 0120 movs r0, #1 + 603 .LVL30: + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 604 .loc 1 337 1 view .LVU236 + 605 0054 7047 bx lr + 606 .cfi_endproc + 607 .LFE142: + 609 .section .text.HAL_MDMA_ConfigPostRequestMask,"ax",%progbits + 610 .align 1 + 611 .global HAL_MDMA_ConfigPostRequestMask + 612 .syntax unified + 613 .thumb + 614 .thumb_func + 615 .fpu fpv5-d16 + 617 HAL_MDMA_ConfigPostRequestMask: + 618 .LVL31: + 619 .LFB143: + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 620 .loc 1 349 1 is_stmt 1 view -0 + 621 .cfi_startproc + 622 @ args = 0, pretend = 0, frame = 0 + 623 @ frame_needed = 0, uses_anonymous_args = 0 + 624 @ link register save eliminated. + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 625 .loc 1 350 3 view .LVU238 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 626 .loc 1 353 3 view .LVU239 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 627 .loc 1 353 5 is_stmt 0 view .LVU240 + 628 0000 68B3 cbz r0, .L34 + 629 0002 0346 mov r3, r0 + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 630 .loc 1 359 3 is_stmt 1 view .LVU241 + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 631 .loc 1 359 3 view .LVU242 + 632 0004 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 633 .LVL32: + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 634 .loc 1 359 3 is_stmt 0 view .LVU243 + 635 0008 0128 cmp r0, #1 + 636 000a 2AD0 beq .L35 + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 637 .loc 1 359 3 is_stmt 1 discriminator 2 view .LVU244 + 638 000c 0120 movs r0, #1 + 639 000e 83F83C00 strb r0, [r3, #60] + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 640 .loc 1 359 3 discriminator 2 view .LVU245 + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 641 .loc 1 361 3 discriminator 2 view .LVU246 + ARM GAS /tmp/ccBjdYa2.s page 48 + + + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 642 .loc 1 361 35 is_stmt 0 discriminator 2 view .LVU247 + 643 0012 93F83D00 ldrb r0, [r3, #61] @ zero_extendqisi2 + 644 0016 C0B2 uxtb r0, r0 + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 645 .loc 1 361 5 discriminator 2 view .LVU248 + 646 0018 0128 cmp r0, #1 + 647 001a 04D0 beq .L42 + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 648 .loc 1 394 12 view .LVU249 + 649 001c 0120 movs r0, #1 + 650 .LVL33: + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 651 .loc 1 397 3 is_stmt 1 view .LVU250 + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 652 .loc 1 397 3 view .LVU251 + 653 001e 0022 movs r2, #0 + 654 .LVL34: + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 655 .loc 1 397 3 is_stmt 0 view .LVU252 + 656 0020 83F83C20 strb r2, [r3, #60] + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 657 .loc 1 397 3 is_stmt 1 view .LVU253 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 658 .loc 1 399 3 view .LVU254 + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 659 .loc 1 400 1 is_stmt 0 view .LVU255 + 660 0024 7047 bx lr + 661 .LVL35: + 662 .L42: + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 663 .loc 1 349 1 view .LVU256 + 664 0026 30B4 push {r4, r5} + 665 .LCFI4: + 666 .cfi_def_cfa_offset 8 + 667 .cfi_offset 4, -8 + 668 .cfi_offset 5, -4 + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 669 .loc 1 364 5 is_stmt 1 view .LVU257 + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 670 .loc 1 364 14 is_stmt 0 view .LVU258 + 671 0028 1C68 ldr r4, [r3] + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 672 .loc 1 364 24 view .LVU259 + 673 002a 2569 ldr r5, [r4, #16] + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 674 .loc 1 364 7 view .LVU260 + 675 002c 15F0804F tst r5, #1073741824 + 676 0030 09D1 bne .L32 + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = MaskData; + 677 .loc 1 367 7 is_stmt 1 view .LVU261 + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->Instance->CMDR = MaskData; + 678 .loc 1 367 29 is_stmt 0 view .LVU262 + 679 0032 2163 str r1, [r4, #48] + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 680 .loc 1 368 7 is_stmt 1 view .LVU263 + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 49 + + + 681 .loc 1 368 12 is_stmt 0 view .LVU264 + 682 0034 1868 ldr r0, [r3] + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 683 .loc 1 368 29 view .LVU265 + 684 0036 4263 str r2, [r0, #52] + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 685 .loc 1 376 7 is_stmt 1 view .LVU266 + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 686 .loc 1 376 9 is_stmt 0 view .LVU267 + 687 0038 51B9 cbnz r1, .L33 + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 688 .loc 1 378 9 is_stmt 1 view .LVU268 + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 689 .loc 1 378 14 is_stmt 0 view .LVU269 + 690 003a 1968 ldr r1, [r3] + 691 .LVL36: + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 692 .loc 1 378 31 view .LVU270 + 693 003c 0A69 ldr r2, [r1, #16] + 694 .LVL37: + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 695 .loc 1 378 31 view .LVU271 + 696 003e 22F00042 bic r2, r2, #-2147483648 + 697 0042 0A61 str r2, [r1, #16] + 698 .LVL38: + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 699 .loc 1 350 22 view .LVU272 + 700 0044 0020 movs r0, #0 + 701 .L32: + 702 .LVL39: + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 703 .loc 1 397 3 is_stmt 1 view .LVU273 + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 704 .loc 1 397 3 view .LVU274 + 705 0046 0022 movs r2, #0 + 706 0048 83F83C20 strb r2, [r3, #60] + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 707 .loc 1 397 3 view .LVU275 + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 708 .loc 1 399 3 view .LVU276 + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 709 .loc 1 400 1 is_stmt 0 view .LVU277 + 710 004c 30BC pop {r4, r5} + 711 .LCFI5: + 712 .cfi_remember_state + 713 .cfi_restore 5 + 714 .cfi_restore 4 + 715 .cfi_def_cfa_offset 0 + 716 004e 7047 bx lr + 717 .LVL40: + 718 .L33: + 719 .LCFI6: + 720 .cfi_restore_state + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 721 .loc 1 382 9 is_stmt 1 view .LVU278 + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 722 .loc 1 382 14 is_stmt 0 view .LVU279 + ARM GAS /tmp/ccBjdYa2.s page 50 + + + 723 0050 1968 ldr r1, [r3] + 724 .LVL41: + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 725 .loc 1 382 31 view .LVU280 + 726 0052 0A69 ldr r2, [r1, #16] + 727 .LVL42: + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 728 .loc 1 382 31 view .LVU281 + 729 0054 42F00042 orr r2, r2, #-2147483648 + 730 0058 0A61 str r2, [r1, #16] + 731 .LVL43: + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 732 .loc 1 350 22 view .LVU282 + 733 005a 0020 movs r0, #0 + 734 005c F3E7 b .L32 + 735 .LVL44: + 736 .L34: + 737 .LCFI7: + 738 .cfi_def_cfa_offset 0 + 739 .cfi_restore 4 + 740 .cfi_restore 5 + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 741 .loc 1 355 12 view .LVU283 + 742 005e 0120 movs r0, #1 + 743 .LVL45: + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 744 .loc 1 355 12 view .LVU284 + 745 0060 7047 bx lr + 746 .LVL46: + 747 .L35: + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 748 .loc 1 359 3 view .LVU285 + 749 0062 0220 movs r0, #2 + 750 0064 7047 bx lr + 751 .cfi_endproc + 752 .LFE143: + 754 .section .text.HAL_MDMA_RegisterCallback,"ax",%progbits + 755 .align 1 + 756 .global HAL_MDMA_RegisterCallback + 757 .syntax unified + 758 .thumb + 759 .thumb_func + 760 .fpu fpv5-d16 + 762 HAL_MDMA_RegisterCallback: + 763 .LVL47: + 764 .LFB144: + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 765 .loc 1 411 1 is_stmt 1 view -0 + 766 .cfi_startproc + 767 @ args = 0, pretend = 0, frame = 0 + 768 @ frame_needed = 0, uses_anonymous_args = 0 + 769 @ link register save eliminated. + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 770 .loc 1 412 3 view .LVU287 + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 771 .loc 1 415 3 view .LVU288 + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 51 + + + 772 .loc 1 415 5 is_stmt 0 view .LVU289 + 773 0000 0346 mov r3, r0 + 774 0002 58B3 cbz r0, .L53 + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 775 .loc 1 421 3 is_stmt 1 view .LVU290 + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 776 .loc 1 421 3 view .LVU291 + 777 0004 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 778 .LVL48: + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 779 .loc 1 421 3 is_stmt 0 view .LVU292 + 780 0008 0128 cmp r0, #1 + 781 000a 29D0 beq .L54 + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 782 .loc 1 421 3 is_stmt 1 discriminator 2 view .LVU293 + 783 000c 0120 movs r0, #1 + 784 000e 83F83C00 strb r0, [r3, #60] + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 785 .loc 1 421 3 discriminator 2 view .LVU294 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 786 .loc 1 423 3 discriminator 2 view .LVU295 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 787 .loc 1 423 35 is_stmt 0 discriminator 2 view .LVU296 + 788 0012 93F83D00 ldrb r0, [r3, #61] @ zero_extendqisi2 + 789 0016 C0B2 uxtb r0, r0 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 790 .loc 1 423 5 discriminator 2 view .LVU297 + 791 0018 0128 cmp r0, #1 + 792 001a 04D0 beq .L57 + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 793 .loc 1 458 12 view .LVU298 + 794 001c 0120 movs r0, #1 + 795 .L45: + 796 .LVL49: + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 797 .loc 1 462 3 is_stmt 1 view .LVU299 + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 798 .loc 1 462 3 view .LVU300 + 799 001e 0022 movs r2, #0 + 800 .LVL50: + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 801 .loc 1 462 3 is_stmt 0 view .LVU301 + 802 0020 83F83C20 strb r2, [r3, #60] + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 803 .loc 1 462 3 is_stmt 1 view .LVU302 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 804 .loc 1 464 3 view .LVU303 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 805 .loc 1 464 10 is_stmt 0 view .LVU304 + 806 0024 7047 bx lr + 807 .LVL51: + 808 .L57: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 809 .loc 1 425 5 is_stmt 1 view .LVU305 + 810 0026 0529 cmp r1, #5 + 811 0028 16D8 bhi .L56 + 812 002a DFE801F0 tbb [pc, r1] + ARM GAS /tmp/ccBjdYa2.s page 52 + + + 813 .L47: + 814 002e 03 .byte (.L52-.L47)/2 + 815 002f 06 .byte (.L51-.L47)/2 + 816 0030 09 .byte (.L50-.L47)/2 + 817 0031 0C .byte (.L49-.L47)/2 + 818 0032 0F .byte (.L48-.L47)/2 + 819 0033 12 .byte (.L46-.L47)/2 + 820 .p2align 1 + 821 .L52: + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 822 .loc 1 428 7 view .LVU306 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 823 .loc 1 428 31 is_stmt 0 view .LVU307 + 824 0034 5A64 str r2, [r3, #68] + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 825 .loc 1 429 7 is_stmt 1 view .LVU308 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 826 .loc 1 412 21 is_stmt 0 view .LVU309 + 827 0036 0846 mov r0, r1 + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 828 .loc 1 429 7 view .LVU310 + 829 0038 F1E7 b .L45 + 830 .L51: + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 831 .loc 1 432 7 is_stmt 1 view .LVU311 + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 832 .loc 1 432 37 is_stmt 0 view .LVU312 + 833 003a 9A64 str r2, [r3, #72] + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 834 .loc 1 433 7 is_stmt 1 view .LVU313 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 835 .loc 1 412 21 is_stmt 0 view .LVU314 + 836 003c 0020 movs r0, #0 + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 837 .loc 1 433 7 view .LVU315 + 838 003e EEE7 b .L45 + 839 .L50: + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 840 .loc 1 436 7 is_stmt 1 view .LVU316 + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 841 .loc 1 436 36 is_stmt 0 view .LVU317 + 842 0040 DA64 str r2, [r3, #76] + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 843 .loc 1 437 7 is_stmt 1 view .LVU318 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 844 .loc 1 412 21 is_stmt 0 view .LVU319 + 845 0042 0020 movs r0, #0 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 846 .loc 1 437 7 view .LVU320 + 847 0044 EBE7 b .L45 + 848 .L49: + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 849 .loc 1 440 7 is_stmt 1 view .LVU321 + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 850 .loc 1 440 42 is_stmt 0 view .LVU322 + 851 0046 1A65 str r2, [r3, #80] + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 53 + + + 852 .loc 1 441 7 is_stmt 1 view .LVU323 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 853 .loc 1 412 21 is_stmt 0 view .LVU324 + 854 0048 0020 movs r0, #0 + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 855 .loc 1 441 7 view .LVU325 + 856 004a E8E7 b .L45 + 857 .L48: + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 858 .loc 1 444 7 is_stmt 1 view .LVU326 + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 859 .loc 1 444 32 is_stmt 0 view .LVU327 + 860 004c 5A65 str r2, [r3, #84] + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 861 .loc 1 445 7 is_stmt 1 view .LVU328 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 862 .loc 1 412 21 is_stmt 0 view .LVU329 + 863 004e 0020 movs r0, #0 + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 864 .loc 1 445 7 view .LVU330 + 865 0050 E5E7 b .L45 + 866 .L46: + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 867 .loc 1 448 7 is_stmt 1 view .LVU331 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 868 .loc 1 448 32 is_stmt 0 view .LVU332 + 869 0052 9A65 str r2, [r3, #88] + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 870 .loc 1 449 7 is_stmt 1 view .LVU333 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 871 .loc 1 412 21 is_stmt 0 view .LVU334 + 872 0054 0020 movs r0, #0 + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 873 .loc 1 449 7 view .LVU335 + 874 0056 E2E7 b .L45 + 875 .L56: + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 876 .loc 1 423 5 view .LVU336 + 877 0058 0020 movs r0, #0 + 878 005a E0E7 b .L45 + 879 .LVL52: + 880 .L53: + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 881 .loc 1 417 12 view .LVU337 + 882 005c 0120 movs r0, #1 + 883 .LVL53: + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 884 .loc 1 417 12 view .LVU338 + 885 005e 7047 bx lr + 886 .L54: + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 887 .loc 1 421 3 view .LVU339 + 888 0060 0220 movs r0, #2 + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 889 .loc 1 465 1 view .LVU340 + 890 0062 7047 bx lr + 891 .cfi_endproc + ARM GAS /tmp/ccBjdYa2.s page 54 + + + 892 .LFE144: + 894 .section .text.HAL_MDMA_UnRegisterCallback,"ax",%progbits + 895 .align 1 + 896 .global HAL_MDMA_UnRegisterCallback + 897 .syntax unified + 898 .thumb + 899 .thumb_func + 900 .fpu fpv5-d16 + 902 HAL_MDMA_UnRegisterCallback: + 903 .LVL54: + 904 .LFB145: + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef status = HAL_OK; + 905 .loc 1 476 1 is_stmt 1 view -0 + 906 .cfi_startproc + 907 @ args = 0, pretend = 0, frame = 0 + 908 @ frame_needed = 0, uses_anonymous_args = 0 + 909 @ link register save eliminated. + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 910 .loc 1 477 3 view .LVU342 + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 911 .loc 1 480 3 view .LVU343 + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 912 .loc 1 480 5 is_stmt 0 view .LVU344 + 913 0000 0346 mov r3, r0 + 914 0002 0028 cmp r0, #0 + 915 0004 33D0 beq .L69 + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 916 .loc 1 486 3 is_stmt 1 view .LVU345 + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 917 .loc 1 486 3 view .LVU346 + 918 0006 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 919 000a 012A cmp r2, #1 + 920 000c 31D0 beq .L70 + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 921 .loc 1 486 3 discriminator 2 view .LVU347 + 922 000e 0122 movs r2, #1 + 923 0010 80F83C20 strb r2, [r0, #60] + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 924 .loc 1 486 3 discriminator 2 view .LVU348 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 925 .loc 1 488 3 discriminator 2 view .LVU349 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 926 .loc 1 488 35 is_stmt 0 discriminator 2 view .LVU350 + 927 0014 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 928 .LVL55: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 929 .loc 1 488 35 discriminator 2 view .LVU351 + 930 0018 C0B2 uxtb r0, r0 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 931 .loc 1 488 5 discriminator 2 view .LVU352 + 932 001a 9042 cmp r0, r2 + 933 001c 04D0 beq .L72 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 934 .loc 1 532 12 view .LVU353 + 935 001e 0120 movs r0, #1 + 936 .L60: + 937 .LVL56: + ARM GAS /tmp/ccBjdYa2.s page 55 + + + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 938 .loc 1 536 3 is_stmt 1 view .LVU354 + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 939 .loc 1 536 3 view .LVU355 + 940 0020 0022 movs r2, #0 + 941 0022 83F83C20 strb r2, [r3, #60] + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 942 .loc 1 536 3 view .LVU356 + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 943 .loc 1 538 3 view .LVU357 + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 944 .loc 1 538 10 is_stmt 0 view .LVU358 + 945 0026 7047 bx lr + 946 .LVL57: + 947 .L72: + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 948 .loc 1 490 5 is_stmt 1 view .LVU359 + 949 0028 0629 cmp r1, #6 + 950 002a F9D8 bhi .L60 + 951 002c DFE801F0 tbb [pc, r1] + 952 .L62: + 953 0030 04 .byte (.L68-.L62)/2 + 954 0031 08 .byte (.L67-.L62)/2 + 955 0032 0B .byte (.L66-.L62)/2 + 956 0033 0E .byte (.L65-.L62)/2 + 957 0034 11 .byte (.L64-.L62)/2 + 958 0035 14 .byte (.L63-.L62)/2 + 959 0036 17 .byte (.L61-.L62)/2 + 960 0037 00 .p2align 1 + 961 .L68: + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 962 .loc 1 493 7 view .LVU360 + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 963 .loc 1 493 31 is_stmt 0 view .LVU361 + 964 0038 0022 movs r2, #0 + 965 003a 5A64 str r2, [r3, #68] + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 966 .loc 1 494 7 is_stmt 1 view .LVU362 + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 967 .loc 1 477 21 is_stmt 0 view .LVU363 + 968 003c 0846 mov r0, r1 + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 969 .loc 1 494 7 view .LVU364 + 970 003e EFE7 b .L60 + 971 .L67: + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 972 .loc 1 497 7 is_stmt 1 view .LVU365 + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 973 .loc 1 497 37 is_stmt 0 view .LVU366 + 974 0040 0020 movs r0, #0 + 975 0042 9864 str r0, [r3, #72] + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 976 .loc 1 498 7 is_stmt 1 view .LVU367 + 977 0044 ECE7 b .L60 + 978 .L66: + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 979 .loc 1 501 7 view .LVU368 + ARM GAS /tmp/ccBjdYa2.s page 56 + + + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 980 .loc 1 501 36 is_stmt 0 view .LVU369 + 981 0046 0020 movs r0, #0 + 982 0048 D864 str r0, [r3, #76] + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 983 .loc 1 502 7 is_stmt 1 view .LVU370 + 984 004a E9E7 b .L60 + 985 .L65: + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 986 .loc 1 505 7 view .LVU371 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 987 .loc 1 505 42 is_stmt 0 view .LVU372 + 988 004c 0020 movs r0, #0 + 989 004e 1865 str r0, [r3, #80] + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 990 .loc 1 506 7 is_stmt 1 view .LVU373 + 991 0050 E6E7 b .L60 + 992 .L64: + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 993 .loc 1 509 7 view .LVU374 + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 994 .loc 1 509 32 is_stmt 0 view .LVU375 + 995 0052 0020 movs r0, #0 + 996 0054 5865 str r0, [r3, #84] + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 997 .loc 1 510 7 is_stmt 1 view .LVU376 + 998 0056 E3E7 b .L60 + 999 .L63: + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 1000 .loc 1 513 7 view .LVU377 + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 1001 .loc 1 513 32 is_stmt 0 view .LVU378 + 1002 0058 0020 movs r0, #0 + 1003 005a 9865 str r0, [r3, #88] + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1004 .loc 1 514 7 is_stmt 1 view .LVU379 + 1005 005c E0E7 b .L60 + 1006 .L61: + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBufferCpltCallback = NULL; + 1007 .loc 1 517 7 view .LVU380 + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBufferCpltCallback = NULL; + 1008 .loc 1 517 31 is_stmt 0 view .LVU381 + 1009 005e 0020 movs r0, #0 + 1010 0060 5864 str r0, [r3, #68] + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBlockCpltCallback = NULL; + 1011 .loc 1 518 7 is_stmt 1 view .LVU382 + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferBlockCpltCallback = NULL; + 1012 .loc 1 518 37 is_stmt 0 view .LVU383 + 1013 0062 9864 str r0, [r3, #72] + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferRepeatBlockCpltCallback = NULL; + 1014 .loc 1 519 7 is_stmt 1 view .LVU384 + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferRepeatBlockCpltCallback = NULL; + 1015 .loc 1 519 36 is_stmt 0 view .LVU385 + 1016 0064 D864 str r0, [r3, #76] + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferErrorCallback = NULL; + 1017 .loc 1 520 7 is_stmt 1 view .LVU386 + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferErrorCallback = NULL; + ARM GAS /tmp/ccBjdYa2.s page 57 + + + 1018 .loc 1 520 42 is_stmt 0 view .LVU387 + 1019 0066 1865 str r0, [r3, #80] + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferAbortCallback = NULL; + 1020 .loc 1 521 7 is_stmt 1 view .LVU388 + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->XferAbortCallback = NULL; + 1021 .loc 1 521 32 is_stmt 0 view .LVU389 + 1022 0068 5865 str r0, [r3, #84] + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 1023 .loc 1 522 7 is_stmt 1 view .LVU390 + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** break; + 1024 .loc 1 522 32 is_stmt 0 view .LVU391 + 1025 006a 9865 str r0, [r3, #88] + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1026 .loc 1 523 7 is_stmt 1 view .LVU392 + 1027 006c D8E7 b .L60 + 1028 .LVL58: + 1029 .L69: + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1030 .loc 1 482 12 is_stmt 0 view .LVU393 + 1031 006e 0120 movs r0, #1 + 1032 .LVL59: + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1033 .loc 1 482 12 view .LVU394 + 1034 0070 7047 bx lr + 1035 .LVL60: + 1036 .L70: + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1037 .loc 1 486 3 view .LVU395 + 1038 0072 0220 movs r0, #2 + 1039 .LVL61: + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1040 .loc 1 539 1 view .LVU396 + 1041 0074 7047 bx lr + 1042 .cfi_endproc + 1043 .LFE145: + 1045 .section .text.HAL_MDMA_LinkedList_CreateNode,"ax",%progbits + 1046 .align 1 + 1047 .global HAL_MDMA_LinkedList_CreateNode + 1048 .syntax unified + 1049 .thumb + 1050 .thumb_func + 1051 .fpu fpv5-d16 + 1053 HAL_MDMA_LinkedList_CreateNode: + 1054 .LVL62: + 1055 .LFB146: + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t addressMask; + 1056 .loc 1 570 1 is_stmt 1 view -0 + 1057 .cfi_startproc + 1058 @ args = 0, pretend = 0, frame = 0 + 1059 @ frame_needed = 0, uses_anonymous_args = 0 + 1060 @ link register save eliminated. + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t blockoffset; + 1061 .loc 1 571 3 view .LVU398 + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1062 .loc 1 572 3 view .LVU399 + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1063 .loc 1 575 3 view .LVU400 + ARM GAS /tmp/ccBjdYa2.s page 58 + + + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1064 .loc 1 575 13 is_stmt 0 view .LVU401 + 1065 0000 0246 mov r2, r0 + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1066 .loc 1 575 38 view .LVU402 + 1067 0002 0B46 mov r3, r1 + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1068 .loc 1 575 5 view .LVU403 + 1069 0004 0029 cmp r1, #0 + 1070 0006 18BF it ne + 1071 0008 0028 cmpne r0, #0 + 1072 000a 7CD0 beq .L84 + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness)); + 1073 .loc 1 581 3 is_stmt 1 view .LVU404 + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request)); + 1074 .loc 1 582 3 view .LVU405 + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc)); + 1075 .loc 1 583 3 view .LVU406 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc)); + 1076 .loc 1 584 3 view .LVU407 + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize)); + 1077 .loc 1 585 3 view .LVU408 + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize)); + 1078 .loc 1 586 3 view .LVU409 + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment)); + 1079 .loc 1 587 3 view .LVU410 + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst)); + 1080 .loc 1 588 3 view .LVU411 + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst)); + 1081 .loc 1 589 3 view .LVU412 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength)); + 1082 .loc 1 590 3 view .LVU413 + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode)); + 1083 .loc 1 591 3 view .LVU414 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset)); + 1084 .loc 1 592 3 view .LVU415 + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset)); + 1085 .loc 1 593 3 view .LVU416 + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1086 .loc 1 594 3 view .LVU417 + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); + 1087 .loc 1 596 3 view .LVU418 + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1088 .loc 1 597 3 view .LVU419 + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1089 .loc 1 601 3 view .LVU420 + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1090 .loc 1 601 15 is_stmt 0 view .LVU421 + 1091 000c 0021 movs r1, #0 + 1092 .LVL63: + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1093 .loc 1 601 15 view .LVU422 + 1094 000e 4161 str r1, [r0, #20] + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMAR = 0; + 1095 .loc 1 604 3 is_stmt 1 view .LVU423 + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMAR = 0; + 1096 .loc 1 604 17 is_stmt 0 view .LVU424 + ARM GAS /tmp/ccBjdYa2.s page 59 + + + 1097 0010 8161 str r1, [r0, #24] + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = 0; + 1098 .loc 1 605 3 is_stmt 1 view .LVU425 + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = 0; + 1099 .loc 1 605 17 is_stmt 0 view .LVU426 + 1100 0012 0162 str r1, [r0, #32] + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->Reserved = 0; + 1101 .loc 1 606 3 is_stmt 1 view .LVU427 + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->Reserved = 0; + 1102 .loc 1 606 17 is_stmt 0 view .LVU428 + 1103 0014 4162 str r1, [r0, #36] + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1104 .loc 1 607 3 is_stmt 1 view .LVU429 + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1105 .loc 1 607 19 is_stmt 0 view .LVU430 + 1106 0016 C161 str r1, [r0, #28] + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 1107 .loc 1 610 3 is_stmt 1 view .LVU431 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 1108 .loc 1 610 35 is_stmt 0 view .LVU432 + 1109 0018 1969 ldr r1, [r3, #16] + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 1110 .loc 1 610 65 view .LVU433 + 1111 001a 5869 ldr r0, [r3, #20] + 1112 .LVL64: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 1113 .loc 1 610 46 view .LVU434 + 1114 001c 0143 orrs r1, r1, r0 + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + 1115 .loc 1 611 22 view .LVU435 + 1116 001e 9869 ldr r0, [r3, #24] + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 1117 .loc 1 610 81 view .LVU436 + 1118 0020 0143 orrs r1, r1, r0 + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + 1119 .loc 1 611 57 view .LVU437 + 1120 0022 D869 ldr r0, [r3, #28] + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + 1121 .loc 1 611 38 view .LVU438 + 1122 0024 0143 orrs r1, r1, r0 + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DestBurst | \ + 1123 .loc 1 612 24 view .LVU439 + 1124 0026 186A ldr r0, [r3, #32] + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + 1125 .loc 1 611 81 view .LVU440 + 1126 0028 0143 orrs r1, r1, r0 + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DestBurst | \ + 1127 .loc 1 612 57 view .LVU441 + 1128 002a 986A ldr r0, [r3, #40] + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DestBurst | \ + 1129 .loc 1 612 38 view .LVU442 + 1130 002c 0143 orrs r1, r1, r0 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + 1131 .loc 1 613 26 view .LVU443 + 1132 002e D86A ldr r0, [r3, #44] + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.DestBurst | \ + 1133 .loc 1 612 81 view .LVU444 + ARM GAS /tmp/ccBjdYa2.s page 60 + + + 1134 0030 0143 orrs r1, r1, r0 + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.TransferTriggerMode; + 1135 .loc 1 614 30 view .LVU445 + 1136 0032 586A ldr r0, [r3, #36] + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.TransferTriggerMode; + 1137 .loc 1 614 52 view .LVU446 + 1138 0034 0138 subs r0, r0, #1 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + 1139 .loc 1 613 81 view .LVU447 + 1140 0036 41EA8041 orr r1, r1, r0, lsl #18 + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1141 .loc 1 615 30 view .LVU448 + 1142 003a 5868 ldr r0, [r3, #4] + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.TransferTriggerMode; + 1143 .loc 1 614 81 view .LVU449 + 1144 003c 0143 orrs r1, r1, r0 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + 1145 .loc 1 610 15 view .LVU450 + 1146 003e 1160 str r1, [r2] + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1147 .loc 1 618 3 is_stmt 1 view .LVU451 + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1148 .loc 1 618 23 is_stmt 0 view .LVU452 + 1149 0040 1968 ldr r1, [r3] + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1150 .loc 1 618 5 view .LVU453 + 1151 0042 B1F1804F cmp r1, #1073741824 + 1152 0046 45D0 beq .L86 + 1153 .L75: + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1154 .loc 1 629 3 is_stmt 1 view .LVU454 + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1155 .loc 1 629 24 is_stmt 0 view .LVU455 + 1156 0048 1968 ldr r1, [r3] + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1157 .loc 1 629 5 view .LVU456 + 1158 004a B1F1804F cmp r1, #1073741824 + 1159 004e 01D0 beq .L76 + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1160 .loc 1 629 68 discriminator 1 view .LVU457 + 1161 0050 996C ldr r1, [r3, #72] + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1162 .loc 1 629 53 discriminator 1 view .LVU458 + 1163 0052 19B1 cbz r1, .L77 + 1164 .L76: + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1165 .loc 1 631 5 is_stmt 1 view .LVU459 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1166 .loc 1 631 17 is_stmt 0 view .LVU460 + 1167 0054 1168 ldr r1, [r2] + 1168 0056 41F00041 orr r1, r1, #-2147483648 + 1169 005a 1160 str r1, [r2] + 1170 .L77: + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1171 .loc 1 635 3 is_stmt 1 view .LVU461 + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1172 .loc 1 635 32 is_stmt 0 view .LVU462 + ARM GAS /tmp/ccBjdYa2.s page 61 + + + 1173 005c 596C ldr r1, [r3, #68] + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1174 .loc 1 635 45 view .LVU463 + 1175 005e 0139 subs r1, r1, #1 + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1176 .loc 1 635 75 view .LVU464 + 1177 0060 0905 lsls r1, r1, #20 + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1178 .loc 1 635 17 view .LVU465 + 1179 0062 5160 str r1, [r2, #4] + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1180 .loc 1 638 3 is_stmt 1 view .LVU466 + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1181 .loc 1 638 23 is_stmt 0 view .LVU467 + 1182 0064 196B ldr r1, [r3, #48] + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1183 .loc 1 638 5 view .LVU468 + 1184 0066 0029 cmp r1, #0 + 1185 0068 39DB blt .L87 + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1186 .loc 1 648 5 is_stmt 1 view .LVU469 + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1187 .loc 1 648 77 is_stmt 0 view .LVU470 + 1188 006a 89B2 uxth r1, r1 + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1189 .loc 1 648 18 view .LVU471 + 1190 006c 1161 str r1, [r2, #16] + 1191 .L79: + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1192 .loc 1 652 3 is_stmt 1 view .LVU472 + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1193 .loc 1 652 23 is_stmt 0 view .LVU473 + 1194 006e 596B ldr r1, [r3, #52] + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1195 .loc 1 652 5 view .LVU474 + 1196 0070 0029 cmp r1, #0 + 1197 0072 3DDB blt .L88 + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1198 .loc 1 662 5 is_stmt 1 view .LVU475 + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1199 .loc 1 662 18 is_stmt 0 view .LVU476 + 1200 0074 1069 ldr r0, [r2, #16] + 1201 0076 40EA0141 orr r1, r0, r1, lsl #16 + 1202 007a 1161 str r1, [r2, #16] + 1203 .L81: + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1204 .loc 1 666 3 is_stmt 1 view .LVU477 + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1205 .loc 1 666 17 is_stmt 0 view .LVU478 + 1206 007c 5168 ldr r1, [r2, #4] + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1207 .loc 1 666 32 view .LVU479 + 1208 007e 186C ldr r0, [r3, #64] + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1209 .loc 1 666 17 view .LVU480 + 1210 0080 0143 orrs r1, r1, r0 + 1211 0082 5160 str r1, [r2, #4] + ARM GAS /tmp/ccBjdYa2.s page 62 + + + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1212 .loc 1 669 3 is_stmt 1 view .LVU481 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1213 .loc 1 669 28 is_stmt 0 view .LVU482 + 1214 0084 D96B ldr r1, [r3, #60] + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1215 .loc 1 669 15 view .LVU483 + 1216 0086 D160 str r1, [r2, #12] + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1217 .loc 1 672 3 is_stmt 1 view .LVU484 + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1218 .loc 1 672 28 is_stmt 0 view .LVU485 + 1219 0088 996B ldr r1, [r3, #56] + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1220 .loc 1 672 15 view .LVU486 + 1221 008a 9160 str r1, [r2, #8] + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1222 .loc 1 675 3 is_stmt 1 view .LVU487 + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1223 .loc 1 675 23 is_stmt 0 view .LVU488 + 1224 008c 1968 ldr r1, [r3] + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1225 .loc 1 675 5 view .LVU489 + 1226 008e B1F1804F cmp r1, #1073741824 + 1227 0092 05D0 beq .L82 + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request clear Mask and Data */ + 1228 .loc 1 678 5 is_stmt 1 view .LVU490 + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request clear Mask and Data */ + 1229 .loc 1 678 45 is_stmt 0 view .LVU491 + 1230 0094 C9B2 uxtb r1, r1 + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the HW request clear Mask and Data */ + 1231 .loc 1 678 17 view .LVU492 + 1232 0096 9161 str r1, [r2, #24] + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = pNodeConfig->PostRequestMaskData; + 1233 .loc 1 680 5 is_stmt 1 view .LVU493 + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = pNodeConfig->PostRequestMaskData; + 1234 .loc 1 680 30 is_stmt 0 view .LVU494 + 1235 0098 996C ldr r1, [r3, #72] + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CMDR = pNodeConfig->PostRequestMaskData; + 1236 .loc 1 680 17 view .LVU495 + 1237 009a 1162 str r1, [r2, #32] + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1238 .loc 1 681 5 is_stmt 1 view .LVU496 + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1239 .loc 1 681 30 is_stmt 0 view .LVU497 + 1240 009c D96C ldr r1, [r3, #76] + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1241 .loc 1 681 17 view .LVU498 + 1242 009e 5162 str r1, [r2, #36] + 1243 .L82: + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 1244 .loc 1 684 3 is_stmt 1 view .LVU499 + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 1245 .loc 1 684 28 is_stmt 0 view .LVU500 + 1246 00a0 996B ldr r1, [r3, #56] + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 1247 .loc 1 684 15 view .LVU501 + ARM GAS /tmp/ccBjdYa2.s page 63 + + + 1248 00a2 01F07F41 and r1, r1, #-16777216 + 1249 .LVL65: + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1250 .loc 1 685 3 is_stmt 1 view .LVU502 + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1251 .loc 1 685 5 is_stmt 0 view .LVU503 + 1252 00a6 0029 cmp r1, #0 + 1253 00a8 18BF it ne + 1254 00aa B1F1005F cmpne r1, #536870912 + 1255 00ae 03D1 bne .L83 + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1256 .loc 1 688 5 is_stmt 1 view .LVU504 + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1257 .loc 1 688 17 is_stmt 0 view .LVU505 + 1258 00b0 9169 ldr r1, [r2, #24] + 1259 .LVL66: + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1260 .loc 1 688 17 view .LVU506 + 1261 00b2 41F48031 orr r1, r1, #65536 + 1262 00b6 9161 str r1, [r2, #24] + 1263 .LVL67: + 1264 .L83: + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 1265 .loc 1 691 3 is_stmt 1 view .LVU507 + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 1266 .loc 1 691 28 is_stmt 0 view .LVU508 + 1267 00b8 DB6B ldr r3, [r3, #60] + 1268 .LVL68: + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + 1269 .loc 1 691 15 view .LVU509 + 1270 00ba 03F07F43 and r3, r3, #-16777216 + 1271 .LVL69: + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1272 .loc 1 692 3 is_stmt 1 view .LVU510 + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1273 .loc 1 692 5 is_stmt 0 view .LVU511 + 1274 00be 002B cmp r3, #0 + 1275 00c0 18BF it ne + 1276 00c2 B3F1005F cmpne r3, #536870912 + 1277 00c6 20D1 bne .L85 + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1278 .loc 1 695 5 is_stmt 1 view .LVU512 + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1279 .loc 1 695 17 is_stmt 0 view .LVU513 + 1280 00c8 9369 ldr r3, [r2, #24] + 1281 .LVL70: + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1282 .loc 1 695 17 view .LVU514 + 1283 00ca 43F40033 orr r3, r3, #131072 + 1284 00ce 9361 str r3, [r2, #24] + 1285 .LVL71: + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1286 .loc 1 698 10 view .LVU515 + 1287 00d0 0020 movs r0, #0 + 1288 00d2 7047 bx lr + 1289 .LVL72: + 1290 .L86: + ARM GAS /tmp/ccBjdYa2.s page 64 + + + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1291 .loc 1 620 5 is_stmt 1 view .LVU516 + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1292 .loc 1 620 17 is_stmt 0 view .LVU517 + 1293 00d4 1168 ldr r1, [r2] + 1294 00d6 41F08041 orr r1, r1, #1073741824 + 1295 00da 1160 str r1, [r2] + 1296 00dc B4E7 b .L75 + 1297 .L87: + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : source repeat block offset */ + 1298 .loc 1 640 5 is_stmt 1 view .LVU518 + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : source repeat block offset */ + 1299 .loc 1 640 19 is_stmt 0 view .LVU519 + 1300 00de 5168 ldr r1, [r2, #4] + 1301 00e0 41F48021 orr r1, r1, #262144 + 1302 00e4 5160 str r1, [r2, #4] + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR = blockoffset & 0x0000FFFFU; + 1303 .loc 1 642 5 is_stmt 1 view .LVU520 + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR = blockoffset & 0x0000FFFFU; + 1304 .loc 1 642 49 is_stmt 0 view .LVU521 + 1305 00e6 196B ldr r1, [r3, #48] + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR = blockoffset & 0x0000FFFFU; + 1306 .loc 1 642 30 view .LVU522 + 1307 00e8 4942 rsbs r1, r1, #0 + 1308 .LVL73: + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1309 .loc 1 643 5 is_stmt 1 view .LVU523 + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1310 .loc 1 643 32 is_stmt 0 view .LVU524 + 1311 00ea 89B2 uxth r1, r1 + 1312 .LVL74: + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1313 .loc 1 643 18 view .LVU525 + 1314 00ec 1161 str r1, [r2, #16] + 1315 .LVL75: + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1316 .loc 1 643 18 view .LVU526 + 1317 00ee BEE7 b .L79 + 1318 .L88: + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : destination repeat block offset */ + 1319 .loc 1 654 5 is_stmt 1 view .LVU527 + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /*write new CBRUR Register value : destination repeat block offset */ + 1320 .loc 1 654 19 is_stmt 0 view .LVU528 + 1321 00f0 5168 ldr r1, [r2, #4] + 1322 00f2 41F40021 orr r1, r1, #524288 + 1323 00f6 5160 str r1, [r2, #4] + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 1324 .loc 1 656 5 is_stmt 1 view .LVU529 + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 1325 .loc 1 656 49 is_stmt 0 view .LVU530 + 1326 00f8 596B ldr r1, [r3, #52] + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + 1327 .loc 1 656 30 view .LVU531 + 1328 00fa 4842 rsbs r0, r1, #0 + 1329 .LVL76: + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1330 .loc 1 657 5 is_stmt 1 view .LVU532 + ARM GAS /tmp/ccBjdYa2.s page 65 + + + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1331 .loc 1 657 18 is_stmt 0 view .LVU533 + 1332 00fc 1169 ldr r1, [r2, #16] + 1333 00fe 41EA0041 orr r1, r1, r0, lsl #16 + 1334 0102 1161 str r1, [r2, #16] + 1335 0104 BAE7 b .L81 + 1336 .LVL77: + 1337 .L84: + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1338 .loc 1 577 12 view .LVU534 + 1339 0106 0120 movs r0, #1 + 1340 .LVL78: + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1341 .loc 1 577 12 view .LVU535 + 1342 0108 7047 bx lr + 1343 .LVL79: + 1344 .L85: + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1345 .loc 1 698 10 view .LVU536 + 1346 010a 0020 movs r0, #0 + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1347 .loc 1 699 1 view .LVU537 + 1348 010c 7047 bx lr + 1349 .cfi_endproc + 1350 .LFE146: + 1352 .section .text.HAL_MDMA_LinkedList_AddNode,"ax",%progbits + 1353 .align 1 + 1354 .global HAL_MDMA_LinkedList_AddNode + 1355 .syntax unified + 1356 .thumb + 1357 .thumb_func + 1358 .fpu fpv5-d16 + 1360 HAL_MDMA_LinkedList_AddNode: + 1361 .LVL80: + 1362 .LFB147: + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_LinkNodeTypeDef *pNode; + 1363 .loc 1 713 1 is_stmt 1 view -0 + 1364 .cfi_startproc + 1365 @ args = 0, pretend = 0, frame = 0 + 1366 @ frame_needed = 0, uses_anonymous_args = 0 + 1367 @ link register save eliminated. + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t counter = 0, nodeInserted = 0; + 1368 .loc 1 714 3 view .LVU539 + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1369 .loc 1 715 3 view .LVU540 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1370 .loc 1 716 3 view .LVU541 + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1371 .loc 1 719 3 view .LVU542 + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1372 .loc 1 719 5 is_stmt 0 view .LVU543 + 1373 0000 0029 cmp r1, #0 + 1374 0002 18BF it ne + 1375 0004 0028 cmpne r0, #0 + 1376 0006 6BD0 beq .L104 + 1377 0008 0346 mov r3, r0 + 1378 000a 8C46 mov ip, r1 + ARM GAS /tmp/ccBjdYa2.s page 66 + + + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1379 .loc 1 725 3 is_stmt 1 view .LVU544 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1380 .loc 1 725 3 view .LVU545 + 1381 000c 90F83C10 ldrb r1, [r0, #60] @ zero_extendqisi2 + 1382 .LVL81: + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1383 .loc 1 725 3 is_stmt 0 view .LVU546 + 1384 0010 0129 cmp r1, #1 + 1385 0012 67D0 beq .L105 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1386 .loc 1 725 3 is_stmt 1 discriminator 2 view .LVU547 + 1387 0014 0121 movs r1, #1 + 1388 0016 80F83C10 strb r1, [r0, #60] + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1389 .loc 1 725 3 discriminator 2 view .LVU548 + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1390 .loc 1 727 3 discriminator 2 view .LVU549 + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1391 .loc 1 727 35 is_stmt 0 discriminator 2 view .LVU550 + 1392 001a 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 1393 .LVL82: + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1394 .loc 1 727 35 discriminator 2 view .LVU551 + 1395 001e C0B2 uxtb r0, r0 + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1396 .loc 1 727 5 discriminator 2 view .LVU552 + 1397 0020 8842 cmp r0, r1 + 1398 0022 04D0 beq .L114 + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1399 .loc 1 829 5 is_stmt 1 view .LVU553 + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1400 .loc 1 829 5 view .LVU554 + 1401 0024 0022 movs r2, #0 + 1402 .LVL83: + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1403 .loc 1 829 5 is_stmt 0 view .LVU555 + 1404 0026 83F83C20 strb r2, [r3, #60] + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1405 .loc 1 829 5 is_stmt 1 view .LVU556 + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1406 .loc 1 832 5 view .LVU557 + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1407 .loc 1 832 12 is_stmt 0 view .LVU558 + 1408 002a 0220 movs r0, #2 + 1409 002c 7047 bx lr + 1410 .LVL84: + 1411 .L114: + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_LinkNodeTypeDef *pNode; + 1412 .loc 1 713 1 view .LVU559 + 1413 002e F0B4 push {r4, r5, r6, r7} + 1414 .LCFI8: + 1415 .cfi_def_cfa_offset 16 + 1416 .cfi_offset 4, -16 + 1417 .cfi_offset 5, -12 + 1418 .cfi_offset 6, -8 + 1419 .cfi_offset 7, -4 + ARM GAS /tmp/ccBjdYa2.s page 67 + + + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1420 .loc 1 730 5 is_stmt 1 view .LVU560 + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1421 .loc 1 730 18 is_stmt 0 view .LVU561 + 1422 0030 0221 movs r1, #2 + 1423 0032 83F83D10 strb r1, [r3, #61] + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1424 .loc 1 733 5 is_stmt 1 view .LVU562 + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1425 .loc 1 733 23 is_stmt 0 view .LVU563 + 1426 0036 DF6D ldr r7, [r3, #92] + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1427 .loc 1 733 7 view .LVU564 + 1428 0038 2FB1 cbz r7, .L115 + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1429 .loc 1 757 10 is_stmt 1 view .LVU565 + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1430 .loc 1 757 12 is_stmt 0 view .LVU566 + 1431 003a 6745 cmp r7, ip + 1432 003c 48D0 beq .L93 + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK)) + 1433 .loc 1 760 13 view .LVU567 + 1434 003e 3C46 mov r4, r7 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1435 .loc 1 716 21 view .LVU568 + 1436 0040 0026 movs r6, #0 + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1437 .loc 1 715 12 view .LVU569 + 1438 0042 3146 mov r1, r6 + 1439 0044 10E0 b .L94 + 1440 .L115: + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1441 .loc 1 735 7 is_stmt 1 view .LVU570 + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1442 .loc 1 735 9 is_stmt 0 view .LVU571 + 1443 0046 002A cmp r2, #0 + 1444 0048 42D1 bne .L93 + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the MDMA handle First linked List node*/ + 1445 .loc 1 740 9 is_stmt 1 view .LVU572 + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the MDMA handle First linked List node*/ + 1446 .loc 1 740 14 is_stmt 0 view .LVU573 + 1447 004a 1A68 ldr r2, [r3] + 1448 .LVL85: + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Set the MDMA handle First linked List node*/ + 1449 .loc 1 740 31 view .LVU574 + 1450 004c C2F824C0 str ip, [r2, #36] + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1451 .loc 1 742 9 is_stmt 1 view .LVU575 + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1452 .loc 1 742 43 is_stmt 0 view .LVU576 + 1453 0050 C3F85CC0 str ip, [r3, #92] + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1454 .loc 1 745 9 is_stmt 1 view .LVU577 + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1455 .loc 1 745 24 is_stmt 0 view .LVU578 + 1456 0054 0020 movs r0, #0 + 1457 0056 CCF81400 str r0, [ip, #20] + ARM GAS /tmp/ccBjdYa2.s page 68 + + + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1458 .loc 1 748 9 is_stmt 1 view .LVU579 + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1459 .loc 1 748 42 is_stmt 0 view .LVU580 + 1460 005a C3F860C0 str ip, [r3, #96] + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1461 .loc 1 750 9 is_stmt 1 view .LVU581 + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1462 .loc 1 750 38 is_stmt 0 view .LVU582 + 1463 005e 0122 movs r2, #1 + 1464 0060 5A66 str r2, [r3, #100] + 1465 0062 35E0 b .L93 + 1466 .LVL86: + 1467 .L95: + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** counter++; + 1468 .loc 1 767 9 is_stmt 1 view .LVU583 + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** counter++; + 1469 .loc 1 767 46 is_stmt 0 view .LVU584 + 1470 0064 6469 ldr r4, [r4, #20] + 1471 .LVL87: + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1472 .loc 1 768 9 is_stmt 1 view .LVU585 + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1473 .loc 1 768 16 is_stmt 0 view .LVU586 + 1474 0066 0131 adds r1, r1, #1 + 1475 .LVL88: + 1476 .L94: + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1477 .loc 1 761 12 is_stmt 1 view .LVU587 + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1478 .loc 1 761 29 is_stmt 0 view .LVU588 + 1479 0068 5D6E ldr r5, [r3, #100] + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1480 .loc 1 761 12 view .LVU589 + 1481 006a 8D42 cmp r5, r1 + 1482 006c 05D9 bls .L96 + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1483 .loc 1 761 54 discriminator 1 view .LVU590 + 1484 006e 26B9 cbnz r6, .L96 + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1485 .loc 1 763 9 is_stmt 1 view .LVU591 + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1486 .loc 1 763 17 is_stmt 0 view .LVU592 + 1487 0070 6569 ldr r5, [r4, #20] + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1488 .loc 1 763 11 view .LVU593 + 1489 0072 6545 cmp r5, ip + 1490 0074 F6D1 bne .L95 + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1491 .loc 1 765 22 view .LVU594 + 1492 0076 0646 mov r6, r0 + 1493 .LVL89: + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1494 .loc 1 765 22 view .LVU595 + 1495 0078 F4E7 b .L95 + 1496 .LVL90: + 1497 .L96: + ARM GAS /tmp/ccBjdYa2.s page 69 + + + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1498 .loc 1 771 7 is_stmt 1 view .LVU596 + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1499 .loc 1 771 9 is_stmt 0 view .LVU597 + 1500 007a 46BB cbnz r6, .L108 + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1501 .loc 1 774 9 is_stmt 1 view .LVU598 + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1502 .loc 1 774 31 is_stmt 0 view .LVU599 + 1503 007c 196E ldr r1, [r3, #96] + 1504 .LVL91: + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1505 .loc 1 774 11 view .LVU600 + 1506 007e 9142 cmp r1, r2 + 1507 0080 03D0 beq .L98 + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1508 .loc 1 774 60 discriminator 1 view .LVU601 + 1509 0082 12B1 cbz r2, .L98 + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1510 .loc 1 715 25 view .LVU602 + 1511 0084 0025 movs r5, #0 + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U)) + 1512 .loc 1 788 19 view .LVU603 + 1513 0086 2946 mov r1, r5 + 1514 0088 15E0 b .L99 + 1515 .L98: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + 1516 .loc 1 777 11 is_stmt 1 view .LVU604 + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + 1517 .loc 1 777 60 is_stmt 0 view .LVU605 + 1518 008a 4A69 ldr r2, [r1, #20] + 1519 .LVL92: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + 1520 .loc 1 777 26 view .LVU606 + 1521 008c CCF81420 str r2, [ip, #20] + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle last node address */ + 1522 .loc 1 778 11 is_stmt 1 view .LVU607 + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle last node address */ + 1523 .loc 1 778 16 is_stmt 0 view .LVU608 + 1524 0090 1A6E ldr r2, [r3, #96] + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle last node address */ + 1525 .loc 1 778 50 view .LVU609 + 1526 0092 C2F814C0 str ip, [r2, #20] + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Increment the linked list node counter */ + 1527 .loc 1 780 11 is_stmt 1 view .LVU610 + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Increment the linked list node counter */ + 1528 .loc 1 780 44 is_stmt 0 view .LVU611 + 1529 0096 C3F860C0 str ip, [r3, #96] + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1530 .loc 1 782 11 is_stmt 1 view .LVU612 + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1531 .loc 1 782 16 is_stmt 0 view .LVU613 + 1532 009a 5A6E ldr r2, [r3, #100] + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1533 .loc 1 782 39 view .LVU614 + 1534 009c 0132 adds r2, r2, #1 + 1535 009e 5A66 str r2, [r3, #100] + ARM GAS /tmp/ccBjdYa2.s page 70 + + + 1536 00a0 3046 mov r0, r6 + 1537 00a2 15E0 b .L93 + 1538 .LVL93: + 1539 .L116: + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CLAR = (uint32_t)pNewNode; + 1540 .loc 1 795 15 is_stmt 1 view .LVU615 + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CLAR = (uint32_t)pNewNode; + 1541 .loc 1 795 37 is_stmt 0 view .LVU616 + 1542 00a4 7C69 ldr r4, [r7, #20] + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** pNode->CLAR = (uint32_t)pNewNode; + 1543 .loc 1 795 30 view .LVU617 + 1544 00a6 CCF81440 str r4, [ip, #20] + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Increment the linked list node counter */ + 1545 .loc 1 796 15 is_stmt 1 view .LVU618 + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Increment the linked list node counter */ + 1546 .loc 1 796 27 is_stmt 0 view .LVU619 + 1547 00aa C7F814C0 str ip, [r7, #20] + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeInserted = 1; + 1548 .loc 1 798 15 is_stmt 1 view .LVU620 + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeInserted = 1; + 1549 .loc 1 798 20 is_stmt 0 view .LVU621 + 1550 00ae 5C6E ldr r4, [r3, #100] + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeInserted = 1; + 1551 .loc 1 798 43 view .LVU622 + 1552 00b0 0134 adds r4, r4, #1 + 1553 00b2 5C66 str r4, [r3, #100] + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1554 .loc 1 799 15 is_stmt 1 view .LVU623 + 1555 .LVL94: + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1556 .loc 1 799 28 is_stmt 0 view .LVU624 + 1557 00b4 0125 movs r5, #1 + 1558 .LVL95: + 1559 .L99: + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1560 .loc 1 789 16 is_stmt 1 view .LVU625 + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1561 .loc 1 789 33 is_stmt 0 view .LVU626 + 1562 00b6 5C6E ldr r4, [r3, #100] + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1563 .loc 1 789 16 view .LVU627 + 1564 00b8 8C42 cmp r4, r1 + 1565 00ba 05D9 bls .L102 + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1566 .loc 1 789 58 discriminator 1 view .LVU628 + 1567 00bc 25B9 cbnz r5, .L102 + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNode == pPrevNode) + 1568 .loc 1 791 13 is_stmt 1 view .LVU629 + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(pNode == pPrevNode) + 1569 .loc 1 791 20 is_stmt 0 view .LVU630 + 1570 00be 0131 adds r1, r1, #1 + 1571 .LVL96: + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1572 .loc 1 792 13 is_stmt 1 view .LVU631 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1573 .loc 1 792 15 is_stmt 0 view .LVU632 + 1574 00c0 9742 cmp r7, r2 + ARM GAS /tmp/ccBjdYa2.s page 71 + + + 1575 00c2 EFD0 beq .L116 + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1576 .loc 1 803 15 is_stmt 1 view .LVU633 + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1577 .loc 1 803 52 is_stmt 0 view .LVU634 + 1578 00c4 7F69 ldr r7, [r7, #20] + 1579 .LVL97: + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1580 .loc 1 803 52 view .LVU635 + 1581 00c6 F6E7 b .L99 + 1582 .L102: + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1583 .loc 1 807 11 is_stmt 1 view .LVU636 + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1584 .loc 1 807 13 is_stmt 0 view .LVU637 + 1585 00c8 15B1 cbz r5, .L93 + 1586 00ca 3046 mov r0, r6 + 1587 00cc 00E0 b .L93 + 1588 .LVL98: + 1589 .L108: + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1590 .loc 1 807 13 view .LVU638 + 1591 00ce 3046 mov r0, r6 + 1592 .LVL99: + 1593 .L93: + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1594 .loc 1 820 5 is_stmt 1 view .LVU639 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1595 .loc 1 820 5 view .LVU640 + 1596 00d0 0022 movs r2, #0 + 1597 00d2 83F83C20 strb r2, [r3, #60] + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1598 .loc 1 820 5 view .LVU641 + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1599 .loc 1 822 5 view .LVU642 + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1600 .loc 1 822 18 is_stmt 0 view .LVU643 + 1601 00d6 0122 movs r2, #1 + 1602 00d8 83F83D20 strb r2, [r3, #61] + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1603 .loc 1 824 5 is_stmt 1 view .LVU644 + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1604 .loc 1 834 1 is_stmt 0 view .LVU645 + 1605 00dc F0BC pop {r4, r5, r6, r7} + 1606 .LCFI9: + 1607 .cfi_restore 7 + 1608 .cfi_restore 6 + 1609 .cfi_restore 5 + 1610 .cfi_restore 4 + 1611 .cfi_def_cfa_offset 0 + 1612 00de 7047 bx lr + 1613 .LVL100: + 1614 .L104: + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1615 .loc 1 721 12 view .LVU646 + 1616 00e0 0120 movs r0, #1 + 1617 .LVL101: + ARM GAS /tmp/ccBjdYa2.s page 72 + + + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1618 .loc 1 721 12 view .LVU647 + 1619 00e2 7047 bx lr + 1620 .LVL102: + 1621 .L105: + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1622 .loc 1 725 3 view .LVU648 + 1623 00e4 0220 movs r0, #2 + 1624 .LVL103: + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1625 .loc 1 834 1 view .LVU649 + 1626 00e6 7047 bx lr + 1627 .cfi_endproc + 1628 .LFE147: + 1630 .section .text.HAL_MDMA_LinkedList_RemoveNode,"ax",%progbits + 1631 .align 1 + 1632 .global HAL_MDMA_LinkedList_RemoveNode + 1633 .syntax unified + 1634 .thumb + 1635 .thumb_func + 1636 .fpu fpv5-d16 + 1638 HAL_MDMA_LinkedList_RemoveNode: + 1639 .LVL104: + 1640 .LFB148: + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_LinkNodeTypeDef *ptmpNode; + 1641 .loc 1 846 1 is_stmt 1 view -0 + 1642 .cfi_startproc + 1643 @ args = 0, pretend = 0, frame = 0 + 1644 @ frame_needed = 0, uses_anonymous_args = 0 + 1645 @ link register save eliminated. + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t counter = 0, nodeDeleted = 0; + 1646 .loc 1 847 3 view .LVU651 + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1647 .loc 1 848 3 view .LVU652 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1648 .loc 1 849 3 view .LVU653 + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1649 .loc 1 852 3 view .LVU654 + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1650 .loc 1 852 5 is_stmt 0 view .LVU655 + 1651 0000 0029 cmp r1, #0 + 1652 0002 18BF it ne + 1653 0004 0028 cmpne r0, #0 + 1654 0006 60D0 beq .L129 + 1655 0008 0346 mov r3, r0 + 1656 000a 8C46 mov ip, r1 + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1657 .loc 1 858 3 is_stmt 1 view .LVU656 + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1658 .loc 1 858 3 view .LVU657 + 1659 000c 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 1660 0010 012A cmp r2, #1 + 1661 0012 5CD0 beq .L130 + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1662 .loc 1 858 3 discriminator 2 view .LVU658 + 1663 0014 0122 movs r2, #1 + 1664 0016 80F83C20 strb r2, [r0, #60] + ARM GAS /tmp/ccBjdYa2.s page 73 + + + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1665 .loc 1 858 3 discriminator 2 view .LVU659 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1666 .loc 1 860 3 discriminator 2 view .LVU660 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1667 .loc 1 860 35 is_stmt 0 discriminator 2 view .LVU661 + 1668 001a 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 1669 .LVL105: + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1670 .loc 1 860 35 discriminator 2 view .LVU662 + 1671 001e C0B2 uxtb r0, r0 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1672 .loc 1 860 5 discriminator 2 view .LVU663 + 1673 0020 9042 cmp r0, r2 + 1674 0022 04D0 beq .L136 + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1675 .loc 1 945 5 is_stmt 1 view .LVU664 + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1676 .loc 1 945 5 view .LVU665 + 1677 0024 0022 movs r2, #0 + 1678 0026 83F83C20 strb r2, [r3, #60] + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1679 .loc 1 945 5 view .LVU666 + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1680 .loc 1 948 5 view .LVU667 + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1681 .loc 1 948 12 is_stmt 0 view .LVU668 + 1682 002a 0220 movs r0, #2 + 1683 002c 7047 bx lr + 1684 .L136: + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_LinkNodeTypeDef *ptmpNode; + 1685 .loc 1 846 1 view .LVU669 + 1686 002e 30B4 push {r4, r5} + 1687 .LCFI10: + 1688 .cfi_def_cfa_offset 8 + 1689 .cfi_offset 4, -8 + 1690 .cfi_offset 5, -4 + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1691 .loc 1 863 5 is_stmt 1 view .LVU670 + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1692 .loc 1 863 18 is_stmt 0 view .LVU671 + 1693 0030 0222 movs r2, #2 + 1694 0032 83F83D20 strb r2, [r3, #61] + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1695 .loc 1 866 5 is_stmt 1 view .LVU672 + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1696 .loc 1 866 24 is_stmt 0 view .LVU673 + 1697 0036 DA6D ldr r2, [r3, #92] + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1698 .loc 1 866 7 view .LVU674 + 1699 0038 002A cmp r2, #0 + 1700 003a 3ED0 beq .L120 + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1701 .loc 1 866 79 discriminator 1 view .LVU675 + 1702 003c 196E ldr r1, [r3, #96] + 1703 .LVL106: + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 74 + + + 1704 .loc 1 866 60 discriminator 1 view .LVU676 + 1705 003e 0029 cmp r1, #0 + 1706 0040 3BD0 beq .L120 + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1707 .loc 1 866 123 discriminator 2 view .LVU677 + 1708 0042 5C6E ldr r4, [r3, #100] + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1709 .loc 1 866 114 discriminator 2 view .LVU678 + 1710 0044 002C cmp r4, #0 + 1711 0046 38D0 beq .L120 + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1712 .loc 1 870 10 is_stmt 1 view .LVU679 + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1713 .loc 1 870 12 is_stmt 0 view .LVU680 + 1714 0048 6245 cmp r2, ip + 1715 004a 02D0 beq .L137 + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1716 .loc 1 848 25 view .LVU681 + 1717 004c 0025 movs r5, #0 + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1718 .loc 1 848 12 view .LVU682 + 1719 004e 2946 mov r1, r5 + 1720 0050 25E0 b .L121 + 1721 .L137: + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1722 .loc 1 873 7 is_stmt 1 view .LVU683 + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1723 .loc 1 873 9 is_stmt 0 view .LVU684 + 1724 0052 6145 cmp r1, ip + 1725 0054 0ED0 beq .L138 + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1726 .loc 1 886 9 is_stmt 1 view .LVU685 + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1727 .loc 1 886 91 is_stmt 0 view .LVU686 + 1728 0056 4869 ldr r0, [r1, #20] + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1729 .loc 1 886 11 view .LVU687 + 1730 0058 8242 cmp r2, r0 + 1731 005a 12D0 beq .L139 + 1732 .L123: + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + 1733 .loc 1 895 9 is_stmt 1 view .LVU688 + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + 1734 .loc 1 895 14 is_stmt 0 view .LVU689 + 1735 005c 1A68 ldr r2, [r3] + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + 1736 .loc 1 895 38 view .LVU690 + 1737 005e DCF81410 ldr r1, [ip, #20] + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + 1738 .loc 1 895 31 view .LVU691 + 1739 0062 5162 str r1, [r2, #36] + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 1740 .loc 1 896 9 is_stmt 1 view .LVU692 + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 1741 .loc 1 896 74 is_stmt 0 view .LVU693 + 1742 0064 1A68 ldr r2, [r3] + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + ARM GAS /tmp/ccBjdYa2.s page 75 + + + 1743 .loc 1 896 84 view .LVU694 + 1744 0066 526A ldr r2, [r2, #36] + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 1745 .loc 1 896 43 view .LVU695 + 1746 0068 DA65 str r2, [r3, #92] + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1747 .loc 1 898 9 is_stmt 1 view .LVU696 + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1748 .loc 1 898 14 is_stmt 0 view .LVU697 + 1749 006a 5A6E ldr r2, [r3, #100] + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1750 .loc 1 898 37 view .LVU698 + 1751 006c 013A subs r2, r2, #1 + 1752 006e 5A66 str r2, [r3, #100] + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1753 .loc 1 849 21 view .LVU699 + 1754 0070 0020 movs r0, #0 + 1755 0072 22E0 b .L120 + 1756 .L138: + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 1757 .loc 1 878 9 is_stmt 1 view .LVU700 + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LastLinkedListNodeAddress = 0; + 1758 .loc 1 878 43 is_stmt 0 view .LVU701 + 1759 0074 0020 movs r0, #0 + 1760 0076 D865 str r0, [r3, #92] + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 1761 .loc 1 879 9 is_stmt 1 view .LVU702 + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** hmdma->LinkedListNodeCounter = 0; + 1762 .loc 1 879 43 is_stmt 0 view .LVU703 + 1763 0078 1866 str r0, [r3, #96] + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1764 .loc 1 880 9 is_stmt 1 view .LVU704 + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1765 .loc 1 880 38 is_stmt 0 view .LVU705 + 1766 007a 5866 str r0, [r3, #100] + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1767 .loc 1 882 9 is_stmt 1 view .LVU706 + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1768 .loc 1 882 14 is_stmt 0 view .LVU707 + 1769 007c 1A68 ldr r2, [r3] + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1770 .loc 1 882 31 view .LVU708 + 1771 007e 5062 str r0, [r2, #36] + 1772 0080 1BE0 b .L120 + 1773 .L139: + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1774 .loc 1 889 11 is_stmt 1 view .LVU709 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1775 .loc 1 889 57 is_stmt 0 view .LVU710 + 1776 0082 DCF81420 ldr r2, [ip, #20] + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1777 .loc 1 889 50 view .LVU711 + 1778 0086 4A61 str r2, [r1, #20] + 1779 0088 E8E7 b .L123 + 1780 .LVL107: + 1781 .L141: + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + ARM GAS /tmp/ccBjdYa2.s page 76 + + + 1782 .loc 1 911 11 is_stmt 1 view .LVU712 + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1783 .loc 1 911 28 is_stmt 0 view .LVU713 + 1784 008a 1C6E ldr r4, [r3, #96] + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1785 .loc 1 911 13 view .LVU714 + 1786 008c 6445 cmp r4, ip + 1787 008e 10D0 beq .L140 + 1788 .L125: + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeDeleted = 1; + 1789 .loc 1 917 11 is_stmt 1 view .LVU715 + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeDeleted = 1; + 1790 .loc 1 917 33 is_stmt 0 view .LVU716 + 1791 0090 DCF81440 ldr r4, [ip, #20] + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** nodeDeleted = 1; + 1792 .loc 1 917 26 view .LVU717 + 1793 0094 5461 str r4, [r2, #20] + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 1794 .loc 1 918 11 is_stmt 1 view .LVU718 + 1795 .LVL108: + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1796 .loc 1 920 11 view .LVU719 + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1797 .loc 1 920 16 is_stmt 0 view .LVU720 + 1798 0096 5C6E ldr r4, [r3, #100] + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1799 .loc 1 920 39 view .LVU721 + 1800 0098 013C subs r4, r4, #1 + 1801 009a 5C66 str r4, [r3, #100] + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Update the Handle node counter */ + 1802 .loc 1 918 23 view .LVU722 + 1803 009c 0125 movs r5, #1 + 1804 .LVL109: + 1805 .L121: + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1806 .loc 1 905 12 is_stmt 1 view .LVU723 + 1807 009e 5C6E ldr r4, [r3, #100] + 1808 00a0 8C42 cmp r4, r1 + 1809 00a2 08D9 bls .L127 + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1810 .loc 1 905 54 is_stmt 0 discriminator 1 view .LVU724 + 1811 00a4 3DB9 cbnz r5, .L127 + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(ptmpNode->CLAR == ((uint32_t)pNode)) + 1812 .loc 1 907 9 is_stmt 1 view .LVU725 + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if(ptmpNode->CLAR == ((uint32_t)pNode)) + 1813 .loc 1 907 16 is_stmt 0 view .LVU726 + 1814 00a6 0131 adds r1, r1, #1 + 1815 .LVL110: + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1816 .loc 1 908 9 is_stmt 1 view .LVU727 + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1817 .loc 1 908 20 is_stmt 0 view .LVU728 + 1818 00a8 5469 ldr r4, [r2, #20] + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1819 .loc 1 908 11 view .LVU729 + 1820 00aa 6445 cmp r4, ip + 1821 00ac EDD0 beq .L141 + ARM GAS /tmp/ccBjdYa2.s page 77 + + + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1822 .loc 1 924 11 is_stmt 1 view .LVU730 + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1823 .loc 1 924 54 is_stmt 0 view .LVU731 + 1824 00ae 5269 ldr r2, [r2, #20] + 1825 .LVL111: + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1826 .loc 1 924 54 view .LVU732 + 1827 00b0 F5E7 b .L121 + 1828 .L140: + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1829 .loc 1 914 13 is_stmt 1 view .LVU733 + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1830 .loc 1 914 46 is_stmt 0 view .LVU734 + 1831 00b2 1A66 str r2, [r3, #96] + 1832 00b4 ECE7 b .L125 + 1833 .L127: + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1834 .loc 1 928 7 is_stmt 1 view .LVU735 + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1835 .loc 1 928 9 is_stmt 0 view .LVU736 + 1836 00b6 05B1 cbz r5, .L120 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1837 .loc 1 849 21 view .LVU737 + 1838 00b8 0020 movs r0, #0 + 1839 .LVL112: + 1840 .L120: + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1841 .loc 1 936 5 is_stmt 1 view .LVU738 + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1842 .loc 1 936 5 view .LVU739 + 1843 00ba 0022 movs r2, #0 + 1844 00bc 83F83C20 strb r2, [r3, #60] + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1845 .loc 1 936 5 view .LVU740 + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1846 .loc 1 938 5 view .LVU741 + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1847 .loc 1 938 18 is_stmt 0 view .LVU742 + 1848 00c0 0122 movs r2, #1 + 1849 00c2 83F83D20 strb r2, [r3, #61] + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1850 .loc 1 940 5 is_stmt 1 view .LVU743 + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1851 .loc 1 950 1 is_stmt 0 view .LVU744 + 1852 00c6 30BC pop {r4, r5} + 1853 .LCFI11: + 1854 .cfi_restore 5 + 1855 .cfi_restore 4 + 1856 .cfi_def_cfa_offset 0 + 1857 00c8 7047 bx lr + 1858 .LVL113: + 1859 .L129: + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1860 .loc 1 854 12 view .LVU745 + 1861 00ca 0120 movs r0, #1 + 1862 .LVL114: + ARM GAS /tmp/ccBjdYa2.s page 78 + + + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1863 .loc 1 854 12 view .LVU746 + 1864 00cc 7047 bx lr + 1865 .LVL115: + 1866 .L130: + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1867 .loc 1 858 3 view .LVU747 + 1868 00ce 0220 movs r0, #2 + 1869 .LVL116: + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1870 .loc 1 950 1 view .LVU748 + 1871 00d0 7047 bx lr + 1872 .cfi_endproc + 1873 .LFE148: + 1875 .section .text.HAL_MDMA_LinkedList_EnableCircularMode,"ax",%progbits + 1876 .align 1 + 1877 .global HAL_MDMA_LinkedList_EnableCircularMode + 1878 .syntax unified + 1879 .thumb + 1880 .thumb_func + 1881 .fpu fpv5-d16 + 1883 HAL_MDMA_LinkedList_EnableCircularMode: + 1884 .LVL117: + 1885 .LFB149: + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1886 .loc 1 959 1 is_stmt 1 view -0 + 1887 .cfi_startproc + 1888 @ args = 0, pretend = 0, frame = 0 + 1889 @ frame_needed = 0, uses_anonymous_args = 0 + 1890 @ link register save eliminated. + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1891 .loc 1 960 3 view .LVU750 + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1892 .loc 1 963 3 view .LVU751 + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1893 .loc 1 963 5 is_stmt 0 view .LVU752 + 1894 0000 30B3 cbz r0, .L145 + 1895 0002 0346 mov r3, r0 + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1896 .loc 1 969 3 is_stmt 1 view .LVU753 + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1897 .loc 1 969 3 view .LVU754 + 1898 0004 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 1899 0008 012A cmp r2, #1 + 1900 000a 23D0 beq .L146 + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1901 .loc 1 959 1 is_stmt 0 discriminator 2 view .LVU755 + 1902 000c 10B4 push {r4} + 1903 .LCFI12: + 1904 .cfi_def_cfa_offset 4 + 1905 .cfi_offset 4, -4 + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1906 .loc 1 969 3 is_stmt 1 discriminator 2 view .LVU756 + 1907 000e 0122 movs r2, #1 + 1908 0010 80F83C20 strb r2, [r0, #60] + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1909 .loc 1 969 3 discriminator 2 view .LVU757 + ARM GAS /tmp/ccBjdYa2.s page 79 + + + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1910 .loc 1 971 3 discriminator 2 view .LVU758 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1911 .loc 1 971 35 is_stmt 0 discriminator 2 view .LVU759 + 1912 0014 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 1913 .LVL118: + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1914 .loc 1 971 35 discriminator 2 view .LVU760 + 1915 0018 C0B2 uxtb r0, r0 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1916 .loc 1 971 5 discriminator 2 view .LVU761 + 1917 001a 9042 cmp r0, r2 + 1918 001c 09D0 beq .L152 + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1919 .loc 1 960 21 view .LVU762 + 1920 001e 0020 movs r0, #0 + 1921 .L144: + 1922 .LVL119: + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1923 .loc 1 989 3 is_stmt 1 view .LVU763 + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1924 .loc 1 989 3 view .LVU764 + 1925 0020 0022 movs r2, #0 + 1926 0022 83F83C20 strb r2, [r3, #60] + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1927 .loc 1 989 3 view .LVU765 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1928 .loc 1 991 3 view .LVU766 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1929 .loc 1 991 16 is_stmt 0 view .LVU767 + 1930 0026 0122 movs r2, #1 + 1931 0028 83F83D20 strb r2, [r3, #61] + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1932 .loc 1 993 3 is_stmt 1 view .LVU768 + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1933 .loc 1 994 1 is_stmt 0 view .LVU769 + 1934 002c 5DF8044B ldr r4, [sp], #4 + 1935 .LCFI13: + 1936 .cfi_remember_state + 1937 .cfi_restore 4 + 1938 .cfi_def_cfa_offset 0 + 1939 0030 7047 bx lr + 1940 .LVL120: + 1941 .L152: + 1942 .LCFI14: + 1943 .cfi_restore_state + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1944 .loc 1 974 5 is_stmt 1 view .LVU770 + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1945 .loc 1 974 18 is_stmt 0 view .LVU771 + 1946 0032 0222 movs r2, #2 + 1947 0034 83F83D20 strb r2, [r3, #61] + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1948 .loc 1 977 5 is_stmt 1 view .LVU772 + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1949 .loc 1 977 24 is_stmt 0 view .LVU773 + 1950 0038 DA6D ldr r2, [r3, #92] + ARM GAS /tmp/ccBjdYa2.s page 80 + + + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1951 .loc 1 977 7 view .LVU774 + 1952 003a 002A cmp r2, #0 + 1953 003c F0D0 beq .L144 + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1954 .loc 1 977 79 discriminator 1 view .LVU775 + 1955 003e 196E ldr r1, [r3, #96] + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1956 .loc 1 977 60 discriminator 1 view .LVU776 + 1957 0040 0029 cmp r1, #0 + 1958 0042 EDD0 beq .L144 + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 1959 .loc 1 977 114 discriminator 2 view .LVU777 + 1960 0044 5C6E ldr r4, [r3, #100] + 1961 0046 002C cmp r4, #0 + 1962 0048 EAD0 beq .L144 + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1963 .loc 1 984 7 is_stmt 1 view .LVU778 + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1964 .loc 1 984 46 is_stmt 0 view .LVU779 + 1965 004a 4A61 str r2, [r1, #20] + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1966 .loc 1 960 21 view .LVU780 + 1967 004c 0020 movs r0, #0 + 1968 004e E7E7 b .L144 + 1969 .LVL121: + 1970 .L145: + 1971 .LCFI15: + 1972 .cfi_def_cfa_offset 0 + 1973 .cfi_restore 4 + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1974 .loc 1 965 12 view .LVU781 + 1975 0050 0120 movs r0, #1 + 1976 .LVL122: + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 1977 .loc 1 965 12 view .LVU782 + 1978 0052 7047 bx lr + 1979 .LVL123: + 1980 .L146: + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1981 .loc 1 969 3 view .LVU783 + 1982 0054 0220 movs r0, #2 + 1983 .LVL124: + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 1984 .loc 1 994 1 view .LVU784 + 1985 0056 7047 bx lr + 1986 .cfi_endproc + 1987 .LFE149: + 1989 .section .text.HAL_MDMA_LinkedList_DisableCircularMode,"ax",%progbits + 1990 .align 1 + 1991 .global HAL_MDMA_LinkedList_DisableCircularMode + 1992 .syntax unified + 1993 .thumb + 1994 .thumb_func + 1995 .fpu fpv5-d16 + 1997 HAL_MDMA_LinkedList_DisableCircularMode: + 1998 .LVL125: + ARM GAS /tmp/ccBjdYa2.s page 81 + + + 1999 .LFB150: +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 2000 .loc 1 1003 1 is_stmt 1 view -0 + 2001 .cfi_startproc + 2002 @ args = 0, pretend = 0, frame = 0 + 2003 @ frame_needed = 0, uses_anonymous_args = 0 + 2004 @ link register save eliminated. +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2005 .loc 1 1004 3 view .LVU786 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2006 .loc 1 1007 3 view .LVU787 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2007 .loc 1 1007 5 is_stmt 0 view .LVU788 + 2008 0000 0346 mov r3, r0 + 2009 0002 10B3 cbz r0, .L156 +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2010 .loc 1 1013 3 is_stmt 1 view .LVU789 +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2011 .loc 1 1013 3 view .LVU790 + 2012 0004 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 2013 0008 012A cmp r2, #1 + 2014 000a 20D0 beq .L157 +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2015 .loc 1 1013 3 discriminator 2 view .LVU791 + 2016 000c 0122 movs r2, #1 + 2017 000e 80F83C20 strb r2, [r0, #60] +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2018 .loc 1 1013 3 discriminator 2 view .LVU792 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2019 .loc 1 1015 3 discriminator 2 view .LVU793 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2020 .loc 1 1015 35 is_stmt 0 discriminator 2 view .LVU794 + 2021 0012 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 2022 .LVL126: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2023 .loc 1 1015 35 discriminator 2 view .LVU795 + 2024 0016 C0B2 uxtb r0, r0 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2025 .loc 1 1015 5 discriminator 2 view .LVU796 + 2026 0018 9042 cmp r0, r2 + 2027 001a 07D0 beq .L159 +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2028 .loc 1 1004 21 view .LVU797 + 2029 001c 0020 movs r0, #0 + 2030 .L155: + 2031 .LVL127: +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2032 .loc 1 1033 3 is_stmt 1 view .LVU798 +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2033 .loc 1 1033 3 view .LVU799 + 2034 001e 0022 movs r2, #0 + 2035 0020 83F83C20 strb r2, [r3, #60] +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2036 .loc 1 1033 3 view .LVU800 +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2037 .loc 1 1035 3 view .LVU801 +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 82 + + + 2038 .loc 1 1035 16 is_stmt 0 view .LVU802 + 2039 0024 0122 movs r2, #1 + 2040 0026 83F83D20 strb r2, [r3, #61] +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2041 .loc 1 1037 3 is_stmt 1 view .LVU803 +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2042 .loc 1 1037 10 is_stmt 0 view .LVU804 + 2043 002a 7047 bx lr + 2044 .LVL128: + 2045 .L159: +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2046 .loc 1 1018 5 is_stmt 1 view .LVU805 +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2047 .loc 1 1018 18 is_stmt 0 view .LVU806 + 2048 002c 0222 movs r2, #2 + 2049 002e 83F83D20 strb r2, [r3, #61] +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2050 .loc 1 1021 5 is_stmt 1 view .LVU807 +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2051 .loc 1 1021 24 is_stmt 0 view .LVU808 + 2052 0032 DA6D ldr r2, [r3, #92] +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2053 .loc 1 1021 7 view .LVU809 + 2054 0034 002A cmp r2, #0 + 2055 0036 F2D0 beq .L155 +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2056 .loc 1 1021 79 discriminator 1 view .LVU810 + 2057 0038 1A6E ldr r2, [r3, #96] +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2058 .loc 1 1021 60 discriminator 1 view .LVU811 + 2059 003a 002A cmp r2, #0 + 2060 003c EFD0 beq .L155 +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2061 .loc 1 1021 123 discriminator 2 view .LVU812 + 2062 003e 596E ldr r1, [r3, #100] +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2063 .loc 1 1021 114 discriminator 2 view .LVU813 + 2064 0040 0029 cmp r1, #0 + 2065 0042 ECD0 beq .L155 +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2066 .loc 1 1028 7 is_stmt 1 view .LVU814 +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2067 .loc 1 1028 46 is_stmt 0 view .LVU815 + 2068 0044 0020 movs r0, #0 + 2069 0046 5061 str r0, [r2, #20] + 2070 0048 E9E7 b .L155 + 2071 .LVL129: + 2072 .L156: +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2073 .loc 1 1009 12 view .LVU816 + 2074 004a 0120 movs r0, #1 + 2075 .LVL130: +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2076 .loc 1 1009 12 view .LVU817 + 2077 004c 7047 bx lr + 2078 .LVL131: + 2079 .L157: + ARM GAS /tmp/ccBjdYa2.s page 83 + + +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2080 .loc 1 1013 3 view .LVU818 + 2081 004e 0220 movs r0, #2 + 2082 .LVL132: +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2083 .loc 1 1038 1 view .LVU819 + 2084 0050 7047 bx lr + 2085 .cfi_endproc + 2086 .LFE150: + 2088 .section .text.HAL_MDMA_Start,"ax",%progbits + 2089 .align 1 + 2090 .global HAL_MDMA_Start + 2091 .syntax unified + 2092 .thumb + 2093 .thumb_func + 2094 .fpu fpv5-d16 + 2096 HAL_MDMA_Start: + 2097 .LVL133: + 2098 .LFB151: +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ + 2099 .loc 1 1074 1 is_stmt 1 view -0 + 2100 .cfi_startproc + 2101 @ args = 4, pretend = 0, frame = 0 + 2102 @ frame_needed = 0, uses_anonymous_args = 0 +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + 2103 .loc 1 1076 3 view .LVU821 +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2104 .loc 1 1077 3 view .LVU822 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2105 .loc 1 1080 3 view .LVU823 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2106 .loc 1 1080 5 is_stmt 0 view .LVU824 + 2107 0000 0028 cmp r0, #0 + 2108 0002 35D0 beq .L163 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ + 2109 .loc 1 1074 1 view .LVU825 + 2110 0004 30B5 push {r4, r5, lr} + 2111 .LCFI16: + 2112 .cfi_def_cfa_offset 12 + 2113 .cfi_offset 4, -12 + 2114 .cfi_offset 5, -8 + 2115 .cfi_offset 14, -4 + 2116 0006 83B0 sub sp, sp, #12 + 2117 .LCFI17: + 2118 .cfi_def_cfa_offset 24 + 2119 0008 0446 mov r4, r0 +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2120 .loc 1 1086 3 is_stmt 1 view .LVU826 +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2121 .loc 1 1086 3 view .LVU827 + 2122 000a 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 2123 .LVL134: +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2124 .loc 1 1086 3 is_stmt 0 view .LVU828 + 2125 000e 0128 cmp r0, #1 + 2126 0010 30D0 beq .L164 +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 84 + + + 2127 .loc 1 1086 3 is_stmt 1 discriminator 2 view .LVU829 + 2128 0012 0120 movs r0, #1 + 2129 0014 84F83C00 strb r0, [r4, #60] +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2130 .loc 1 1086 3 discriminator 2 view .LVU830 +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2131 .loc 1 1088 3 discriminator 2 view .LVU831 +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2132 .loc 1 1088 35 is_stmt 0 discriminator 2 view .LVU832 + 2133 0018 94F83D00 ldrb r0, [r4, #61] @ zero_extendqisi2 + 2134 001c C0B2 uxtb r0, r0 +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2135 .loc 1 1088 5 discriminator 2 view .LVU833 + 2136 001e 0128 cmp r0, #1 + 2137 0020 05D0 beq .L170 +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2138 .loc 1 1114 5 is_stmt 1 view .LVU834 +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2139 .loc 1 1114 5 view .LVU835 + 2140 0022 0023 movs r3, #0 + 2141 .LVL135: +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2142 .loc 1 1114 5 is_stmt 0 view .LVU836 + 2143 0024 84F83C30 strb r3, [r4, #60] +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2144 .loc 1 1114 5 is_stmt 1 view .LVU837 +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2145 .loc 1 1117 5 view .LVU838 +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2146 .loc 1 1117 12 is_stmt 0 view .LVU839 + 2147 0028 0220 movs r0, #2 + 2148 .LVL136: + 2149 .L161: +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2150 .loc 1 1121 1 view .LVU840 + 2151 002a 03B0 add sp, sp, #12 + 2152 .LCFI18: + 2153 .cfi_remember_state + 2154 .cfi_def_cfa_offset 12 + 2155 @ sp needed + 2156 002c 30BD pop {r4, r5, pc} + 2157 .LVL137: + 2158 .L170: + 2159 .LCFI19: + 2160 .cfi_restore_state +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2161 .loc 1 1091 5 is_stmt 1 view .LVU841 +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2162 .loc 1 1091 18 is_stmt 0 view .LVU842 + 2163 002e 0220 movs r0, #2 + 2164 0030 84F83D00 strb r0, [r4, #61] +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2165 .loc 1 1094 5 is_stmt 1 view .LVU843 +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2166 .loc 1 1094 22 is_stmt 0 view .LVU844 + 2167 0034 0020 movs r0, #0 + 2168 0036 A066 str r0, [r4, #104] + ARM GAS /tmp/ccBjdYa2.s page 85 + + +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2169 .loc 1 1097 5 is_stmt 1 view .LVU845 + 2170 0038 2568 ldr r5, [r4] + 2171 003a E868 ldr r0, [r5, #12] + 2172 003c 20F00100 bic r0, r0, #1 + 2173 0040 E860 str r0, [r5, #12] +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2174 .loc 1 1100 5 view .LVU846 + 2175 0042 0698 ldr r0, [sp, #24] + 2176 0044 0090 str r0, [sp] + 2177 0046 2046 mov r0, r4 + 2178 0048 FFF7FEFF bl MDMA_SetConfig + 2179 .LVL138: +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2180 .loc 1 1103 5 view .LVU847 + 2181 004c 2268 ldr r2, [r4] + 2182 004e D368 ldr r3, [r2, #12] + 2183 0050 43F00103 orr r3, r3, #1 + 2184 0054 D360 str r3, [r2, #12] +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2185 .loc 1 1105 5 view .LVU848 +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2186 .loc 1 1105 19 is_stmt 0 view .LVU849 + 2187 0056 6368 ldr r3, [r4, #4] +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2188 .loc 1 1105 7 view .LVU850 + 2189 0058 B3F1804F cmp r3, #1073741824 + 2190 005c 01D0 beq .L171 +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2191 .loc 1 1120 10 view .LVU851 + 2192 005e 0020 movs r0, #0 + 2193 0060 E3E7 b .L161 + 2194 .L171: +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2195 .loc 1 1108 7 is_stmt 1 view .LVU852 +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2196 .loc 1 1108 12 is_stmt 0 view .LVU853 + 2197 0062 2268 ldr r2, [r4] +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2198 .loc 1 1108 28 view .LVU854 + 2199 0064 D368 ldr r3, [r2, #12] + 2200 0066 43F48033 orr r3, r3, #65536 + 2201 006a D360 str r3, [r2, #12] +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2202 .loc 1 1120 10 view .LVU855 + 2203 006c 0020 movs r0, #0 + 2204 006e DCE7 b .L161 + 2205 .LVL139: + 2206 .L163: + 2207 .LCFI20: + 2208 .cfi_def_cfa_offset 0 + 2209 .cfi_restore 4 + 2210 .cfi_restore 5 + 2211 .cfi_restore 14 +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2212 .loc 1 1082 12 view .LVU856 + 2213 0070 0120 movs r0, #1 + ARM GAS /tmp/ccBjdYa2.s page 86 + + + 2214 .LVL140: +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2215 .loc 1 1121 1 view .LVU857 + 2216 0072 7047 bx lr + 2217 .LVL141: + 2218 .L164: + 2219 .LCFI21: + 2220 .cfi_def_cfa_offset 24 + 2221 .cfi_offset 4, -12 + 2222 .cfi_offset 5, -8 + 2223 .cfi_offset 14, -4 +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2224 .loc 1 1086 3 view .LVU858 + 2225 0074 0220 movs r0, #2 + 2226 0076 D8E7 b .L161 + 2227 .cfi_endproc + 2228 .LFE151: + 2230 .section .text.HAL_MDMA_Start_IT,"ax",%progbits + 2231 .align 1 + 2232 .global HAL_MDMA_Start_IT + 2233 .syntax unified + 2234 .thumb + 2235 .thumb_func + 2236 .fpu fpv5-d16 + 2238 HAL_MDMA_Start_IT: + 2239 .LVL142: + 2240 .LFB152: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ + 2241 .loc 1 1134 1 is_stmt 1 view -0 + 2242 .cfi_startproc + 2243 @ args = 4, pretend = 0, frame = 0 + 2244 @ frame_needed = 0, uses_anonymous_args = 0 +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + 2245 .loc 1 1136 3 view .LVU860 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2246 .loc 1 1137 3 view .LVU861 +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2247 .loc 1 1140 3 view .LVU862 +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2248 .loc 1 1140 5 is_stmt 0 view .LVU863 + 2249 0000 0028 cmp r0, #0 + 2250 0002 4FD0 beq .L178 +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the parameters */ + 2251 .loc 1 1134 1 view .LVU864 + 2252 0004 30B5 push {r4, r5, lr} + 2253 .LCFI22: + 2254 .cfi_def_cfa_offset 12 + 2255 .cfi_offset 4, -12 + 2256 .cfi_offset 5, -8 + 2257 .cfi_offset 14, -4 + 2258 0006 83B0 sub sp, sp, #12 + 2259 .LCFI23: + 2260 .cfi_def_cfa_offset 24 + 2261 0008 0446 mov r4, r0 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2262 .loc 1 1146 3 is_stmt 1 view .LVU865 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 87 + + + 2263 .loc 1 1146 3 view .LVU866 + 2264 000a 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 2265 .LVL143: +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2266 .loc 1 1146 3 is_stmt 0 view .LVU867 + 2267 000e 0128 cmp r0, #1 + 2268 0010 4AD0 beq .L179 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2269 .loc 1 1146 3 is_stmt 1 discriminator 2 view .LVU868 + 2270 0012 0120 movs r0, #1 + 2271 0014 84F83C00 strb r0, [r4, #60] +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2272 .loc 1 1146 3 discriminator 2 view .LVU869 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2273 .loc 1 1148 3 discriminator 2 view .LVU870 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2274 .loc 1 1148 35 is_stmt 0 discriminator 2 view .LVU871 + 2275 0018 94F83D00 ldrb r0, [r4, #61] @ zero_extendqisi2 + 2276 001c C0B2 uxtb r0, r0 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2277 .loc 1 1148 5 discriminator 2 view .LVU872 + 2278 001e 0128 cmp r0, #1 + 2279 0020 05D0 beq .L185 +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2280 .loc 1 1195 5 is_stmt 1 view .LVU873 +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2281 .loc 1 1195 5 view .LVU874 + 2282 0022 0023 movs r3, #0 + 2283 .LVL144: +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2284 .loc 1 1195 5 is_stmt 0 view .LVU875 + 2285 0024 84F83C30 strb r3, [r4, #60] +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2286 .loc 1 1195 5 is_stmt 1 view .LVU876 +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2287 .loc 1 1198 5 view .LVU877 +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2288 .loc 1 1198 12 is_stmt 0 view .LVU878 + 2289 0028 0220 movs r0, #2 + 2290 .LVL145: + 2291 .L173: +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2292 .loc 1 1202 1 view .LVU879 + 2293 002a 03B0 add sp, sp, #12 + 2294 .LCFI24: + 2295 .cfi_remember_state + 2296 .cfi_def_cfa_offset 12 + 2297 @ sp needed + 2298 002c 30BD pop {r4, r5, pc} + 2299 .LVL146: + 2300 .L185: + 2301 .LCFI25: + 2302 .cfi_restore_state +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2303 .loc 1 1151 5 is_stmt 1 view .LVU880 +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2304 .loc 1 1151 18 is_stmt 0 view .LVU881 + ARM GAS /tmp/ccBjdYa2.s page 88 + + + 2305 002e 0220 movs r0, #2 + 2306 0030 84F83D00 strb r0, [r4, #61] +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2307 .loc 1 1154 5 is_stmt 1 view .LVU882 +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2308 .loc 1 1154 22 is_stmt 0 view .LVU883 + 2309 0034 0020 movs r0, #0 + 2310 0036 A066 str r0, [r4, #104] +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2311 .loc 1 1157 5 is_stmt 1 view .LVU884 + 2312 0038 2568 ldr r5, [r4] + 2313 003a E868 ldr r0, [r5, #12] + 2314 003c 20F00100 bic r0, r0, #1 + 2315 0040 E860 str r0, [r5, #12] +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2316 .loc 1 1160 5 view .LVU885 + 2317 0042 0698 ldr r0, [sp, #24] + 2318 0044 0090 str r0, [sp] + 2319 0046 2046 mov r0, r4 + 2320 0048 FFF7FEFF bl MDMA_SetConfig + 2321 .LVL147: +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2322 .loc 1 1163 5 view .LVU886 + 2323 004c 2268 ldr r2, [r4] + 2324 004e D368 ldr r3, [r2, #12] + 2325 0050 43F00603 orr r3, r3, #6 + 2326 0054 D360 str r3, [r2, #12] +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2327 .loc 1 1165 5 view .LVU887 +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2328 .loc 1 1165 13 is_stmt 0 view .LVU888 + 2329 0056 E36C ldr r3, [r4, #76] +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2330 .loc 1 1165 7 view .LVU889 + 2331 0058 23B1 cbz r3, .L175 +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2332 .loc 1 1168 7 is_stmt 1 view .LVU890 + 2333 005a 2268 ldr r2, [r4] + 2334 005c D368 ldr r3, [r2, #12] + 2335 005e 43F01003 orr r3, r3, #16 + 2336 0062 D360 str r3, [r2, #12] + 2337 .L175: +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2338 .loc 1 1171 5 view .LVU891 +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2339 .loc 1 1171 13 is_stmt 0 view .LVU892 + 2340 0064 236D ldr r3, [r4, #80] +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2341 .loc 1 1171 7 view .LVU893 + 2342 0066 23B1 cbz r3, .L176 +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2343 .loc 1 1174 7 is_stmt 1 view .LVU894 + 2344 0068 2268 ldr r2, [r4] + 2345 006a D368 ldr r3, [r2, #12] + 2346 006c 43F00803 orr r3, r3, #8 + 2347 0070 D360 str r3, [r2, #12] + 2348 .L176: + ARM GAS /tmp/ccBjdYa2.s page 89 + + +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2349 .loc 1 1177 5 view .LVU895 +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2350 .loc 1 1177 13 is_stmt 0 view .LVU896 + 2351 0072 A36C ldr r3, [r4, #72] +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2352 .loc 1 1177 7 view .LVU897 + 2353 0074 23B1 cbz r3, .L177 +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2354 .loc 1 1180 7 is_stmt 1 view .LVU898 + 2355 0076 2268 ldr r2, [r4] + 2356 0078 D368 ldr r3, [r2, #12] + 2357 007a 43F02003 orr r3, r3, #32 + 2358 007e D360 str r3, [r2, #12] + 2359 .L177: +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2360 .loc 1 1184 5 view .LVU899 + 2361 0080 2268 ldr r2, [r4] + 2362 0082 D368 ldr r3, [r2, #12] + 2363 0084 43F00103 orr r3, r3, #1 + 2364 0088 D360 str r3, [r2, #12] +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2365 .loc 1 1186 5 view .LVU900 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2366 .loc 1 1186 19 is_stmt 0 view .LVU901 + 2367 008a 6368 ldr r3, [r4, #4] +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2368 .loc 1 1186 7 view .LVU902 + 2369 008c B3F1804F cmp r3, #1073741824 + 2370 0090 01D0 beq .L186 +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2371 .loc 1 1201 10 view .LVU903 + 2372 0092 0020 movs r0, #0 + 2373 0094 C9E7 b .L173 + 2374 .L186: +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2375 .loc 1 1189 7 is_stmt 1 view .LVU904 +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2376 .loc 1 1189 12 is_stmt 0 view .LVU905 + 2377 0096 2268 ldr r2, [r4] +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2378 .loc 1 1189 28 view .LVU906 + 2379 0098 D368 ldr r3, [r2, #12] + 2380 009a 43F48033 orr r3, r3, #65536 + 2381 009e D360 str r3, [r2, #12] +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2382 .loc 1 1201 10 view .LVU907 + 2383 00a0 0020 movs r0, #0 + 2384 00a2 C2E7 b .L173 + 2385 .LVL148: + 2386 .L178: + 2387 .LCFI26: + 2388 .cfi_def_cfa_offset 0 + 2389 .cfi_restore 4 + 2390 .cfi_restore 5 + 2391 .cfi_restore 14 +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + ARM GAS /tmp/ccBjdYa2.s page 90 + + + 2392 .loc 1 1142 12 view .LVU908 + 2393 00a4 0120 movs r0, #1 + 2394 .LVL149: +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2395 .loc 1 1202 1 view .LVU909 + 2396 00a6 7047 bx lr + 2397 .LVL150: + 2398 .L179: + 2399 .LCFI27: + 2400 .cfi_def_cfa_offset 24 + 2401 .cfi_offset 4, -12 + 2402 .cfi_offset 5, -8 + 2403 .cfi_offset 14, -4 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2404 .loc 1 1146 3 view .LVU910 + 2405 00a8 0220 movs r0, #2 + 2406 00aa BEE7 b .L173 + 2407 .cfi_endproc + 2408 .LFE152: + 2410 .section .text.HAL_MDMA_Abort,"ax",%progbits + 2411 .align 1 + 2412 .global HAL_MDMA_Abort + 2413 .syntax unified + 2414 .thumb + 2415 .thumb_func + 2416 .fpu fpv5-d16 + 2418 HAL_MDMA_Abort: + 2419 .LVL151: + 2420 .LFB153: +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart = HAL_GetTick(); + 2421 .loc 1 1217 1 is_stmt 1 view -0 + 2422 .cfi_startproc + 2423 @ args = 0, pretend = 0, frame = 0 + 2424 @ frame_needed = 0, uses_anonymous_args = 0 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart = HAL_GetTick(); + 2425 .loc 1 1217 1 is_stmt 0 view .LVU912 + 2426 0000 38B5 push {r3, r4, r5, lr} + 2427 .LCFI28: + 2428 .cfi_def_cfa_offset 16 + 2429 .cfi_offset 3, -16 + 2430 .cfi_offset 4, -12 + 2431 .cfi_offset 5, -8 + 2432 .cfi_offset 14, -4 + 2433 0002 0446 mov r4, r0 +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2434 .loc 1 1218 3 is_stmt 1 view .LVU913 +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2435 .loc 1 1218 25 is_stmt 0 view .LVU914 + 2436 0004 FFF7FEFF bl HAL_GetTick + 2437 .LVL152: +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2438 .loc 1 1221 3 is_stmt 1 view .LVU915 +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2439 .loc 1 1221 5 is_stmt 0 view .LVU916 + 2440 0008 002C cmp r4, #0 + 2441 000a 35D0 beq .L192 + 2442 000c 0546 mov r5, r0 + ARM GAS /tmp/ccBjdYa2.s page 91 + + +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2443 .loc 1 1226 3 is_stmt 1 view .LVU917 +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2444 .loc 1 1226 34 is_stmt 0 view .LVU918 + 2445 000e 94F83D30 ldrb r3, [r4, #61] @ zero_extendqisi2 + 2446 0012 DBB2 uxtb r3, r3 +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2447 .loc 1 1226 5 view .LVU919 + 2448 0014 022B cmp r3, #2 + 2449 0016 06D0 beq .L189 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2450 .loc 1 1228 5 is_stmt 1 view .LVU920 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2451 .loc 1 1228 22 is_stmt 0 view .LVU921 + 2452 0018 8023 movs r3, #128 + 2453 001a A366 str r3, [r4, #104] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2454 .loc 1 1231 5 is_stmt 1 view .LVU922 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2455 .loc 1 1231 5 view .LVU923 + 2456 001c 0023 movs r3, #0 + 2457 001e 84F83C30 strb r3, [r4, #60] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2458 .loc 1 1231 5 view .LVU924 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2459 .loc 1 1233 5 view .LVU925 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2460 .loc 1 1233 12 is_stmt 0 view .LVU926 + 2461 0022 0120 movs r0, #1 + 2462 .LVL153: + 2463 .L188: +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2464 .loc 1 1273 1 view .LVU927 + 2465 0024 38BD pop {r3, r4, r5, pc} + 2466 .LVL154: + 2467 .L189: +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2468 .loc 1 1238 5 is_stmt 1 view .LVU928 + 2469 0026 2268 ldr r2, [r4] + 2470 0028 D368 ldr r3, [r2, #12] + 2471 002a 23F03E03 bic r3, r3, #62 + 2472 002e D360 str r3, [r2, #12] +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2473 .loc 1 1241 5 view .LVU929 + 2474 0030 2268 ldr r2, [r4] + 2475 0032 D368 ldr r3, [r2, #12] + 2476 0034 23F00103 bic r3, r3, #1 + 2477 0038 D360 str r3, [r2, #12] +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2478 .loc 1 1244 5 view .LVU930 + 2479 .LVL155: + 2480 .L190: +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2481 .loc 1 1244 10 view .LVU931 +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2482 .loc 1 1244 17 is_stmt 0 view .LVU932 + 2483 003a 2368 ldr r3, [r4] + ARM GAS /tmp/ccBjdYa2.s page 92 + + +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2484 .loc 1 1244 27 view .LVU933 + 2485 003c DA68 ldr r2, [r3, #12] +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2486 .loc 1 1244 10 view .LVU934 + 2487 003e 12F0010F tst r2, #1 + 2488 0042 10D0 beq .L194 +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2489 .loc 1 1247 7 is_stmt 1 view .LVU935 +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2490 .loc 1 1247 12 is_stmt 0 view .LVU936 + 2491 0044 FFF7FEFF bl HAL_GetTick + 2492 .LVL156: +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2493 .loc 1 1247 27 view .LVU937 + 2494 0048 431B subs r3, r0, r5 +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2495 .loc 1 1247 9 view .LVU938 + 2496 004a 052B cmp r3, #5 + 2497 004c F5D9 bls .L190 +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2498 .loc 1 1250 9 is_stmt 1 view .LVU939 +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2499 .loc 1 1250 26 is_stmt 0 view .LVU940 + 2500 004e A36E ldr r3, [r4, #104] + 2501 0050 43F04003 orr r3, r3, #64 + 2502 0054 A366 str r3, [r4, #104] +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2503 .loc 1 1253 9 is_stmt 1 view .LVU941 +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2504 .loc 1 1253 9 view .LVU942 + 2505 0056 0023 movs r3, #0 + 2506 0058 84F83C30 strb r3, [r4, #60] +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2507 .loc 1 1253 9 view .LVU943 +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2508 .loc 1 1256 9 view .LVU944 +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2509 .loc 1 1256 22 is_stmt 0 view .LVU945 + 2510 005c 0323 movs r3, #3 + 2511 005e 84F83D30 strb r3, [r4, #61] +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2512 .loc 1 1258 9 is_stmt 1 view .LVU946 +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2513 .loc 1 1258 16 is_stmt 0 view .LVU947 + 2514 0062 0120 movs r0, #1 + 2515 0064 DEE7 b .L188 + 2516 .L194: +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2517 .loc 1 1263 5 is_stmt 1 view .LVU948 + 2518 0066 1F22 movs r2, #31 + 2519 0068 5A60 str r2, [r3, #4] +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2520 .loc 1 1266 5 view .LVU949 +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2521 .loc 1 1266 5 view .LVU950 + 2522 006a 0020 movs r0, #0 + ARM GAS /tmp/ccBjdYa2.s page 93 + + + 2523 006c 84F83C00 strb r0, [r4, #60] +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2524 .loc 1 1266 5 view .LVU951 +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2525 .loc 1 1269 5 view .LVU952 +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2526 .loc 1 1269 18 is_stmt 0 view .LVU953 + 2527 0070 0123 movs r3, #1 + 2528 0072 84F83D30 strb r3, [r4, #61] +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2529 .loc 1 1272 3 is_stmt 1 view .LVU954 +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2530 .loc 1 1272 10 is_stmt 0 view .LVU955 + 2531 0076 D5E7 b .L188 + 2532 .LVL157: + 2533 .L192: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2534 .loc 1 1223 12 view .LVU956 + 2535 0078 0120 movs r0, #1 + 2536 .LVL158: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2537 .loc 1 1223 12 view .LVU957 + 2538 007a D3E7 b .L188 + 2539 .cfi_endproc + 2540 .LFE153: + 2542 .section .text.HAL_MDMA_Abort_IT,"ax",%progbits + 2543 .align 1 + 2544 .global HAL_MDMA_Abort_IT + 2545 .syntax unified + 2546 .thumb + 2547 .thumb_func + 2548 .fpu fpv5-d16 + 2550 HAL_MDMA_Abort_IT: + 2551 .LVL159: + 2552 .LFB154: +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** /* Check the MDMA peripheral handle */ + 2553 .loc 1 1282 1 is_stmt 1 view -0 + 2554 .cfi_startproc + 2555 @ args = 0, pretend = 0, frame = 0 + 2556 @ frame_needed = 0, uses_anonymous_args = 0 + 2557 @ link register save eliminated. +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2558 .loc 1 1284 3 view .LVU959 +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2559 .loc 1 1284 5 is_stmt 0 view .LVU960 + 2560 0000 90B1 cbz r0, .L198 +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2561 .loc 1 1289 3 is_stmt 1 view .LVU961 +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2562 .loc 1 1289 34 is_stmt 0 view .LVU962 + 2563 0002 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + 2564 0006 DBB2 uxtb r3, r3 +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2565 .loc 1 1289 5 view .LVU963 + 2566 0008 022B cmp r3, #2 + 2567 000a 03D0 beq .L197 +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 94 + + + 2568 .loc 1 1292 5 is_stmt 1 view .LVU964 +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2569 .loc 1 1292 22 is_stmt 0 view .LVU965 + 2570 000c 8023 movs r3, #128 + 2571 000e 8366 str r3, [r0, #104] +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2572 .loc 1 1294 5 is_stmt 1 view .LVU966 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2573 .loc 1 1294 12 is_stmt 0 view .LVU967 + 2574 0010 0120 movs r0, #1 + 2575 .LVL160: +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2576 .loc 1 1294 12 view .LVU968 + 2577 0012 7047 bx lr + 2578 .LVL161: + 2579 .L197: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2580 .loc 1 1299 5 is_stmt 1 view .LVU969 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2581 .loc 1 1299 18 is_stmt 0 view .LVU970 + 2582 0014 0423 movs r3, #4 + 2583 0016 80F83D30 strb r3, [r0, #61] +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2584 .loc 1 1302 5 is_stmt 1 view .LVU971 + 2585 001a 0268 ldr r2, [r0] + 2586 001c D368 ldr r3, [r2, #12] + 2587 001e 23F00103 bic r3, r3, #1 + 2588 0022 D360 str r3, [r2, #12] +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2589 .loc 1 1305 3 view .LVU972 +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2590 .loc 1 1305 10 is_stmt 0 view .LVU973 + 2591 0024 0020 movs r0, #0 + 2592 .LVL162: +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2593 .loc 1 1305 10 view .LVU974 + 2594 0026 7047 bx lr + 2595 .LVL163: + 2596 .L198: +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2597 .loc 1 1286 12 view .LVU975 + 2598 0028 0120 movs r0, #1 + 2599 .LVL164: +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2600 .loc 1 1306 1 view .LVU976 + 2601 002a 7047 bx lr + 2602 .cfi_endproc + 2603 .LFE154: + 2605 .section .text.HAL_MDMA_PollForTransfer,"ax",%progbits + 2606 .align 1 + 2607 .global HAL_MDMA_PollForTransfer + 2608 .syntax unified + 2609 .thumb + 2610 .thumb_func + 2611 .fpu fpv5-d16 + 2613 HAL_MDMA_PollForTransfer: + 2614 .LVL165: + ARM GAS /tmp/ccBjdYa2.s page 95 + + + 2615 .LFB155: +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t levelFlag, errorFlag; + 2616 .loc 1 1317 1 is_stmt 1 view -0 + 2617 .cfi_startproc + 2618 @ args = 0, pretend = 0, frame = 0 + 2619 @ frame_needed = 0, uses_anonymous_args = 0 +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t tickstart; + 2620 .loc 1 1318 3 view .LVU978 +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2621 .loc 1 1319 3 view .LVU979 +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2622 .loc 1 1322 3 view .LVU980 +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2623 .loc 1 1325 3 view .LVU981 +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2624 .loc 1 1325 5 is_stmt 0 view .LVU982 + 2625 0000 0028 cmp r0, #0 + 2626 0002 00F08A80 beq .L217 +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t levelFlag, errorFlag; + 2627 .loc 1 1317 1 view .LVU983 + 2628 0006 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 2629 .LCFI29: + 2630 .cfi_def_cfa_offset 32 + 2631 .cfi_offset 3, -32 + 2632 .cfi_offset 4, -28 + 2633 .cfi_offset 5, -24 + 2634 .cfi_offset 6, -20 + 2635 .cfi_offset 7, -16 + 2636 .cfi_offset 8, -12 + 2637 .cfi_offset 9, -8 + 2638 .cfi_offset 14, -4 + 2639 000a 0F46 mov r7, r1 + 2640 000c 1646 mov r6, r2 + 2641 000e 0546 mov r5, r0 +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2642 .loc 1 1330 3 is_stmt 1 view .LVU984 +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2643 .loc 1 1330 34 is_stmt 0 view .LVU985 + 2644 0010 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + 2645 0014 DBB2 uxtb r3, r3 +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2646 .loc 1 1330 5 view .LVU986 + 2647 0016 022B cmp r3, #2 + 2648 0018 04D0 beq .L201 +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2649 .loc 1 1333 5 is_stmt 1 view .LVU987 +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2650 .loc 1 1333 22 is_stmt 0 view .LVU988 + 2651 001a 8023 movs r3, #128 + 2652 001c 8366 str r3, [r0, #104] +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2653 .loc 1 1335 5 is_stmt 1 view .LVU989 +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2654 .loc 1 1335 12 is_stmt 0 view .LVU990 + 2655 001e 0120 movs r0, #1 + 2656 .LVL166: + 2657 .L200: + ARM GAS /tmp/ccBjdYa2.s page 96 + + +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2658 .loc 1 1455 1 view .LVU991 + 2659 0020 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 2660 .LVL167: + 2661 .L201: +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ + 2662 .loc 1 1339 3 is_stmt 1 view .LVU992 +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ + 2663 .loc 1 1339 76 is_stmt 0 view .LVU993 + 2664 0024 49B1 cbz r1, .L218 +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ + 2665 .loc 1 1340 76 view .LVU994 + 2666 0026 0129 cmp r1, #1 + 2667 0028 29D0 beq .L219 +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** MDMA_FLAG_BRT); + 2668 .loc 1 1341 76 view .LVU995 + 2669 002a 0229 cmp r1, #2 + 2670 002c 02D0 beq .L226 + 2671 002e 4FF00408 mov r8, #4 + 2672 0032 04E0 b .L202 + 2673 .L226: + 2674 0034 4FF00808 mov r8, #8 + 2675 0038 01E0 b .L202 + 2676 .L218: +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ + 2677 .loc 1 1339 76 view .LVU996 + 2678 003a 4FF00208 mov r8, #2 + 2679 .L202: + 2680 .LVL168: +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2681 .loc 1 1346 3 is_stmt 1 discriminator 3 view .LVU997 +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2682 .loc 1 1346 15 is_stmt 0 discriminator 3 view .LVU998 + 2683 003e FFF7FEFF bl HAL_GetTick + 2684 .LVL169: +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2685 .loc 1 1346 15 discriminator 3 view .LVU999 + 2686 0042 8146 mov r9, r0 + 2687 .LVL170: +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2688 .loc 1 1348 3 is_stmt 1 discriminator 3 view .LVU1000 + 2689 .L211: +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2690 .loc 1 1348 8 view .LVU1001 +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2691 .loc 1 1348 9 is_stmt 0 view .LVU1002 + 2692 0044 2B68 ldr r3, [r5] + 2693 0046 1C68 ldr r4, [r3] +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2694 .loc 1 1348 8 view .LVU1003 + 2695 0048 14EA080F tst r4, r8 + 2696 004c 48D1 bne .L227 +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2697 .loc 1 1350 5 is_stmt 1 view .LVU1004 +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2698 .loc 1 1350 9 is_stmt 0 view .LVU1005 + 2699 004e 1C68 ldr r4, [r3] + ARM GAS /tmp/ccBjdYa2.s page 97 + + +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2700 .loc 1 1350 7 view .LVU1006 + 2701 0050 14F0010F tst r4, #1 + 2702 0054 16D1 bne .L228 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2703 .loc 1 1404 5 is_stmt 1 view .LVU1007 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2704 .loc 1 1404 7 is_stmt 0 view .LVU1008 + 2705 0056 B6F1FF3F cmp r6, #-1 + 2706 005a F3D0 beq .L211 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2707 .loc 1 1406 7 is_stmt 1 view .LVU1009 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2708 .loc 1 1406 12 is_stmt 0 view .LVU1010 + 2709 005c FFF7FEFF bl HAL_GetTick + 2710 .LVL171: +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2711 .loc 1 1406 26 view .LVU1011 + 2712 0060 A0EB0900 sub r0, r0, r9 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2713 .loc 1 1406 9 view .LVU1012 + 2714 0064 B042 cmp r0, r6 + 2715 0066 01D8 bhi .L212 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2716 .loc 1 1406 51 discriminator 1 view .LVU1013 + 2717 0068 002E cmp r6, #0 + 2718 006a EBD1 bne .L211 + 2719 .L212: +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2720 .loc 1 1409 9 is_stmt 1 view .LVU1014 +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2721 .loc 1 1409 26 is_stmt 0 view .LVU1015 + 2722 006c AB6E ldr r3, [r5, #104] + 2723 006e 43F04003 orr r3, r3, #64 + 2724 0072 AB66 str r3, [r5, #104] +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2725 .loc 1 1411 9 is_stmt 1 view .LVU1016 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2726 .loc 1 1411 16 is_stmt 0 view .LVU1017 + 2727 0074 2846 mov r0, r5 + 2728 0076 FFF7FEFF bl HAL_MDMA_Abort + 2729 .LVL172: +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2730 .loc 1 1420 9 is_stmt 1 view .LVU1018 +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2731 .loc 1 1420 16 is_stmt 0 view .LVU1019 + 2732 007a 0120 movs r0, #1 + 2733 007c D0E7 b .L200 + 2734 .LVL173: + 2735 .L219: +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ + 2736 .loc 1 1340 76 view .LVU1020 + 2737 007e 4FF01008 mov r8, #16 + 2738 0082 DCE7 b .L202 + 2739 .LVL174: + 2740 .L228: +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 98 + + + 2741 .loc 1 1353 7 is_stmt 1 view .LVU1021 +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2742 .loc 1 1353 17 is_stmt 0 view .LVU1022 + 2743 0084 9B68 ldr r3, [r3, #8] + 2744 .LVL175: +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2745 .loc 1 1355 7 is_stmt 1 view .LVU1023 +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2746 .loc 1 1355 9 is_stmt 0 view .LVU1024 + 2747 0086 13F0800F tst r3, #128 + 2748 008a 24D1 bne .L205 +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2749 .loc 1 1358 9 is_stmt 1 view .LVU1025 +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2750 .loc 1 1358 26 is_stmt 0 view .LVU1026 + 2751 008c AA6E ldr r2, [r5, #104] + 2752 008e 42F00102 orr r2, r2, #1 + 2753 0092 AA66 str r2, [r5, #104] + 2754 .L206: +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2755 .loc 1 1366 7 is_stmt 1 view .LVU1027 +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2756 .loc 1 1366 9 is_stmt 0 view .LVU1028 + 2757 0094 13F4007F tst r3, #512 + 2758 0098 03D0 beq .L207 +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2759 .loc 1 1369 9 is_stmt 1 view .LVU1029 +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2760 .loc 1 1369 26 is_stmt 0 view .LVU1030 + 2761 009a AA6E ldr r2, [r5, #104] + 2762 009c 42F00402 orr r2, r2, #4 + 2763 00a0 AA66 str r2, [r5, #104] + 2764 .L207: +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2765 .loc 1 1372 7 is_stmt 1 view .LVU1031 +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2766 .loc 1 1372 9 is_stmt 0 view .LVU1032 + 2767 00a2 13F4807F tst r3, #256 + 2768 00a6 03D0 beq .L208 +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2769 .loc 1 1375 9 is_stmt 1 view .LVU1033 +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2770 .loc 1 1375 26 is_stmt 0 view .LVU1034 + 2771 00a8 AA6E ldr r2, [r5, #104] + 2772 00aa 42F00802 orr r2, r2, #8 + 2773 00ae AA66 str r2, [r5, #104] + 2774 .L208: +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2775 .loc 1 1378 7 is_stmt 1 view .LVU1035 +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2776 .loc 1 1378 9 is_stmt 0 view .LVU1036 + 2777 00b0 13F4806F tst r3, #1024 + 2778 00b4 03D0 beq .L209 +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2779 .loc 1 1381 9 is_stmt 1 view .LVU1037 +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2780 .loc 1 1381 26 is_stmt 0 view .LVU1038 + ARM GAS /tmp/ccBjdYa2.s page 99 + + + 2781 00b6 AA6E ldr r2, [r5, #104] + 2782 00b8 42F01002 orr r2, r2, #16 + 2783 00bc AA66 str r2, [r5, #104] + 2784 .L209: +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2785 .loc 1 1384 7 is_stmt 1 view .LVU1039 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2786 .loc 1 1384 9 is_stmt 0 view .LVU1040 + 2787 00be 13F4006F tst r3, #2048 + 2788 00c2 03D0 beq .L210 +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2789 .loc 1 1387 9 is_stmt 1 view .LVU1041 +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2790 .loc 1 1387 26 is_stmt 0 view .LVU1042 + 2791 00c4 AB6E ldr r3, [r5, #104] + 2792 .LVL176: +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2793 .loc 1 1387 26 view .LVU1043 + 2794 00c6 43F02003 orr r3, r3, #32 + 2795 00ca AB66 str r3, [r5, #104] + 2796 .L210: +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2797 .loc 1 1390 7 is_stmt 1 view .LVU1044 +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2798 .loc 1 1390 14 is_stmt 0 view .LVU1045 + 2799 00cc 2846 mov r0, r5 + 2800 00ce FFF7FEFF bl HAL_MDMA_Abort + 2801 .LVL177: +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2802 .loc 1 1399 7 is_stmt 1 view .LVU1046 +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2803 .loc 1 1399 14 is_stmt 0 view .LVU1047 + 2804 00d2 0120 movs r0, #1 + 2805 00d4 A4E7 b .L200 + 2806 .LVL178: + 2807 .L205: +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2808 .loc 1 1363 9 is_stmt 1 view .LVU1048 +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2809 .loc 1 1363 26 is_stmt 0 view .LVU1049 + 2810 00d6 AA6E ldr r2, [r5, #104] + 2811 00d8 42F00202 orr r2, r2, #2 + 2812 00dc AA66 str r2, [r5, #104] + 2813 00de D9E7 b .L206 + 2814 .LVL179: + 2815 .L227: +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2816 .loc 1 1426 3 is_stmt 1 view .LVU1050 +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2817 .loc 1 1426 5 is_stmt 0 view .LVU1051 + 2818 00e0 012F cmp r7, #1 + 2819 00e2 0ED0 beq .L229 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2820 .loc 1 1431 8 is_stmt 1 view .LVU1052 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2821 .loc 1 1431 10 is_stmt 0 view .LVU1053 + 2822 00e4 022F cmp r7, #2 + ARM GAS /tmp/ccBjdYa2.s page 100 + + + 2823 00e6 10D0 beq .L230 +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2824 .loc 1 1436 8 is_stmt 1 view .LVU1054 +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2825 .loc 1 1436 10 is_stmt 0 view .LVU1055 + 2826 00e8 032F cmp r7, #3 + 2827 00ea 12D0 beq .L231 +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2828 .loc 1 1440 8 is_stmt 1 view .LVU1056 +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2829 .loc 1 1440 10 is_stmt 0 view .LVU1057 + 2830 00ec BFB9 cbnz r7, .L221 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2831 .loc 1 1442 5 is_stmt 1 view .LVU1058 + 2832 00ee 1E22 movs r2, #30 + 2833 00f0 5A60 str r2, [r3, #4] +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2834 .loc 1 1445 5 view .LVU1059 +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2835 .loc 1 1445 5 view .LVU1060 + 2836 00f2 0023 movs r3, #0 + 2837 00f4 85F83C30 strb r3, [r5, #60] +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2838 .loc 1 1445 5 view .LVU1061 +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2839 .loc 1 1447 5 view .LVU1062 +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2840 .loc 1 1447 18 is_stmt 0 view .LVU1063 + 2841 00f8 0123 movs r3, #1 + 2842 00fa 85F83D30 strb r3, [r5, #61] +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2843 .loc 1 1454 10 view .LVU1064 + 2844 00fe 3846 mov r0, r7 + 2845 0100 8EE7 b .L200 + 2846 .L229: +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2847 .loc 1 1428 5 is_stmt 1 view .LVU1065 + 2848 0102 1022 movs r2, #16 + 2849 0104 5A60 str r2, [r3, #4] +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2850 .loc 1 1454 10 is_stmt 0 view .LVU1066 + 2851 0106 0020 movs r0, #0 + 2852 0108 8AE7 b .L200 + 2853 .L230: +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2854 .loc 1 1433 5 is_stmt 1 view .LVU1067 + 2855 010a 1822 movs r2, #24 + 2856 010c 5A60 str r2, [r3, #4] +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2857 .loc 1 1454 10 is_stmt 0 view .LVU1068 + 2858 010e 0020 movs r0, #0 + 2859 0110 86E7 b .L200 + 2860 .L231: +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2861 .loc 1 1438 5 is_stmt 1 view .LVU1069 + 2862 0112 1C22 movs r2, #28 + 2863 0114 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccBjdYa2.s page 101 + + +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2864 .loc 1 1454 10 is_stmt 0 view .LVU1070 + 2865 0116 0020 movs r0, #0 + 2866 0118 82E7 b .L200 + 2867 .LVL180: + 2868 .L217: + 2869 .LCFI30: + 2870 .cfi_def_cfa_offset 0 + 2871 .cfi_restore 3 + 2872 .cfi_restore 4 + 2873 .cfi_restore 5 + 2874 .cfi_restore 6 + 2875 .cfi_restore 7 + 2876 .cfi_restore 8 + 2877 .cfi_restore 9 + 2878 .cfi_restore 14 +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2879 .loc 1 1327 12 view .LVU1071 + 2880 011a 0120 movs r0, #1 + 2881 .LVL181: +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2882 .loc 1 1455 1 view .LVU1072 + 2883 011c 7047 bx lr + 2884 .LVL182: + 2885 .L221: + 2886 .LCFI31: + 2887 .cfi_def_cfa_offset 32 + 2888 .cfi_offset 3, -32 + 2889 .cfi_offset 4, -28 + 2890 .cfi_offset 5, -24 + 2891 .cfi_offset 6, -20 + 2892 .cfi_offset 7, -16 + 2893 .cfi_offset 8, -12 + 2894 .cfi_offset 9, -8 + 2895 .cfi_offset 14, -4 +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2896 .loc 1 1451 12 view .LVU1073 + 2897 011e 0120 movs r0, #1 + 2898 0120 7EE7 b .L200 + 2899 .cfi_endproc + 2900 .LFE155: + 2902 .section .text.HAL_MDMA_GenerateSWRequest,"ax",%progbits + 2903 .align 1 + 2904 .global HAL_MDMA_GenerateSWRequest + 2905 .syntax unified + 2906 .thumb + 2907 .thumb_func + 2908 .fpu fpv5-d16 + 2910 HAL_MDMA_GenerateSWRequest: + 2911 .LVL183: + 2912 .LFB156: +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t request_mode; + 2913 .loc 1 1464 1 is_stmt 1 view -0 + 2914 .cfi_startproc + 2915 @ args = 0, pretend = 0, frame = 0 + 2916 @ frame_needed = 0, uses_anonymous_args = 0 + 2917 @ link register save eliminated. + ARM GAS /tmp/ccBjdYa2.s page 102 + + +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2918 .loc 1 1465 3 view .LVU1075 +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2919 .loc 1 1468 3 view .LVU1076 +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2920 .loc 1 1468 5 is_stmt 0 view .LVU1077 + 2921 0000 0146 mov r1, r0 + 2922 0002 D8B1 cbz r0, .L237 +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2923 .loc 1 1474 3 is_stmt 1 view .LVU1078 +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2924 .loc 1 1474 23 is_stmt 0 view .LVU1079 + 2925 0004 0368 ldr r3, [r0] +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2926 .loc 1 1474 33 view .LVU1080 + 2927 0006 1A69 ldr r2, [r3, #16] +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2928 .loc 1 1474 16 view .LVU1081 + 2929 0008 02F08042 and r2, r2, #1073741824 + 2930 .LVL184: +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2931 .loc 1 1476 3 is_stmt 1 view .LVU1082 +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2932 .loc 1 1476 22 is_stmt 0 view .LVU1083 + 2933 000c D868 ldr r0, [r3, #12] + 2934 .LVL185: +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2935 .loc 1 1476 5 view .LVU1084 + 2936 000e 10F0010F tst r0, #1 + 2937 0012 09D0 beq .L238 +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2938 .loc 1 1483 8 is_stmt 1 view .LVU1085 +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2939 .loc 1 1483 28 is_stmt 0 view .LVU1086 + 2940 0014 1868 ldr r0, [r3] +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2941 .loc 1 1483 10 view .LVU1087 + 2942 0016 10F4803F tst r0, #65536 + 2943 001a 00D1 bne .L235 +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 2944 .loc 1 1483 61 discriminator 1 view .LVU1088 + 2945 001c 42B9 cbnz r2, .L236 + 2946 .L235: +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2947 .loc 1 1486 5 is_stmt 1 view .LVU1089 +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2948 .loc 1 1486 22 is_stmt 0 view .LVU1090 + 2949 001e 4FF48073 mov r3, #256 + 2950 0022 8B66 str r3, [r1, #104] +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2951 .loc 1 1488 5 is_stmt 1 view .LVU1091 +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2952 .loc 1 1488 12 is_stmt 0 view .LVU1092 + 2953 0024 0120 movs r0, #1 + 2954 0026 7047 bx lr + 2955 .L238: +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 103 + + + 2956 .loc 1 1479 5 is_stmt 1 view .LVU1093 +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2957 .loc 1 1479 22 is_stmt 0 view .LVU1094 + 2958 0028 8023 movs r3, #128 + 2959 002a 8B66 str r3, [r1, #104] +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2960 .loc 1 1481 5 is_stmt 1 view .LVU1095 +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2961 .loc 1 1481 12 is_stmt 0 view .LVU1096 + 2962 002c 0120 movs r0, #1 + 2963 002e 7047 bx lr + 2964 .L236: +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2965 .loc 1 1493 5 is_stmt 1 view .LVU1097 +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2966 .loc 1 1493 26 is_stmt 0 view .LVU1098 + 2967 0030 DA68 ldr r2, [r3, #12] + 2968 .LVL186: +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2969 .loc 1 1493 26 view .LVU1099 + 2970 0032 42F48032 orr r2, r2, #65536 + 2971 0036 DA60 str r2, [r3, #12] +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2972 .loc 1 1495 5 is_stmt 1 view .LVU1100 +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2973 .loc 1 1495 12 is_stmt 0 view .LVU1101 + 2974 0038 0020 movs r0, #0 + 2975 003a 7047 bx lr + 2976 .LVL187: + 2977 .L237: +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 2978 .loc 1 1470 12 view .LVU1102 + 2979 003c 0120 movs r0, #1 + 2980 .LVL188: +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 2981 .loc 1 1497 1 view .LVU1103 + 2982 003e 7047 bx lr + 2983 .cfi_endproc + 2984 .LFE156: + 2986 .section .text.HAL_MDMA_IRQHandler,"ax",%progbits + 2987 .align 1 + 2988 .global HAL_MDMA_IRQHandler + 2989 .syntax unified + 2990 .thumb + 2991 .thumb_func + 2992 .fpu fpv5-d16 + 2994 HAL_MDMA_IRQHandler: + 2995 .LVL189: + 2996 .LFB157: +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __IO uint32_t count = 0; + 2997 .loc 1 1506 1 is_stmt 1 view -0 + 2998 .cfi_startproc + 2999 @ args = 0, pretend = 0, frame = 8 + 3000 @ frame_needed = 0, uses_anonymous_args = 0 +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** __IO uint32_t count = 0; + 3001 .loc 1 1506 1 is_stmt 0 view .LVU1105 + 3002 0000 30B5 push {r4, r5, lr} + ARM GAS /tmp/ccBjdYa2.s page 104 + + + 3003 .LCFI32: + 3004 .cfi_def_cfa_offset 12 + 3005 .cfi_offset 4, -12 + 3006 .cfi_offset 5, -8 + 3007 .cfi_offset 14, -4 + 3008 0002 83B0 sub sp, sp, #12 + 3009 .LCFI33: + 3010 .cfi_def_cfa_offset 24 +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t timeout = SystemCoreClock / 9600U; + 3011 .loc 1 1507 3 is_stmt 1 view .LVU1106 +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** uint32_t timeout = SystemCoreClock / 9600U; + 3012 .loc 1 1507 17 is_stmt 0 view .LVU1107 + 3013 0004 0023 movs r3, #0 + 3014 0006 0193 str r3, [sp, #4] +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3015 .loc 1 1508 3 is_stmt 1 view .LVU1108 +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3016 .loc 1 1508 38 is_stmt 0 view .LVU1109 + 3017 0008 674B ldr r3, .L260 + 3018 000a 1D68 ldr r5, [r3] +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3019 .loc 1 1508 12 view .LVU1110 + 3020 000c 674B ldr r3, .L260+4 + 3021 000e A3FB0535 umull r3, r5, r3, r5 + 3022 .LVL190: +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3023 .loc 1 1510 3 is_stmt 1 view .LVU1111 +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((MDMA->GISR0 & generalIntFlag) == 0U) + 3024 .loc 1 1513 3 view .LVU1112 +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((MDMA->GISR0 & generalIntFlag) == 0U) + 3025 .loc 1 1513 46 is_stmt 0 view .LVU1113 + 3026 0012 0168 ldr r1, [r0] +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((MDMA->GISR0 & generalIntFlag) == 0U) + 3027 .loc 1 1513 57 view .LVU1114 + 3028 0014 664B ldr r3, .L260+8 + 3029 0016 0B44 add r3, r3, r1 +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((MDMA->GISR0 & generalIntFlag) == 0U) + 3030 .loc 1 1513 109 view .LVU1115 + 3031 0018 C3F38413 ubfx r3, r3, #6, #5 +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** if((MDMA->GISR0 & generalIntFlag) == 0U) + 3032 .loc 1 1513 18 view .LVU1116 + 3033 001c 0122 movs r2, #1 + 3034 001e 02FA03F3 lsl r3, r2, r3 + 3035 .LVL191: +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3036 .loc 1 1514 3 is_stmt 1 view .LVU1117 +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3037 .loc 1 1514 11 is_stmt 0 view .LVU1118 + 3038 0022 4FF0A442 mov r2, #1375731712 + 3039 0026 1268 ldr r2, [r2] +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3040 .loc 1 1514 5 view .LVU1119 + 3041 0028 1A42 tst r2, r3 + 3042 002a 00F0A580 beq .L239 + 3043 002e 0446 mov r4, r0 + 3044 0030 AD0A lsrs r5, r5, #10 + 3045 .LVL192: + ARM GAS /tmp/ccBjdYa2.s page 105 + + +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3046 .loc 1 1520 3 is_stmt 1 view .LVU1120 +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3047 .loc 1 1520 7 is_stmt 0 view .LVU1121 + 3048 0032 0B68 ldr r3, [r1] + 3049 .LVL193: +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3050 .loc 1 1520 5 view .LVU1122 + 3051 0034 13F0010F tst r3, #1 + 3052 0038 2FD0 beq .L241 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3053 .loc 1 1522 5 is_stmt 1 view .LVU1123 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3054 .loc 1 1522 8 is_stmt 0 view .LVU1124 + 3055 003a CB68 ldr r3, [r1, #12] +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3056 .loc 1 1522 7 view .LVU1125 + 3057 003c 13F0020F tst r3, #2 + 3058 0040 2BD0 beq .L241 +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3059 .loc 1 1525 7 is_stmt 1 view .LVU1126 + 3060 0042 CB68 ldr r3, [r1, #12] + 3061 0044 23F00203 bic r3, r3, #2 + 3062 0048 CB60 str r3, [r1, #12] +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3063 .loc 1 1528 7 view .LVU1127 +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3064 .loc 1 1528 24 is_stmt 0 view .LVU1128 + 3065 004a 0268 ldr r2, [r0] +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3066 .loc 1 1528 17 view .LVU1129 + 3067 004c 9368 ldr r3, [r2, #8] + 3068 .LVL194: +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3069 .loc 1 1530 7 is_stmt 1 view .LVU1130 +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3070 .loc 1 1530 9 is_stmt 0 view .LVU1131 + 3071 004e 13F0800F tst r3, #128 + 3072 0052 40F09380 bne .L242 +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3073 .loc 1 1533 9 is_stmt 1 view .LVU1132 +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3074 .loc 1 1533 26 is_stmt 0 view .LVU1133 + 3075 0056 816E ldr r1, [r0, #104] + 3076 .LVL195: +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3077 .loc 1 1533 26 view .LVU1134 + 3078 0058 41F00101 orr r1, r1, #1 + 3079 005c 8166 str r1, [r0, #104] + 3080 .L243: +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3081 .loc 1 1541 7 is_stmt 1 view .LVU1135 +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3082 .loc 1 1541 9 is_stmt 0 view .LVU1136 + 3083 005e 13F4007F tst r3, #512 + 3084 0062 03D0 beq .L244 +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + ARM GAS /tmp/ccBjdYa2.s page 106 + + + 3085 .loc 1 1544 9 is_stmt 1 view .LVU1137 +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3086 .loc 1 1544 26 is_stmt 0 view .LVU1138 + 3087 0064 A16E ldr r1, [r4, #104] + 3088 0066 41F00401 orr r1, r1, #4 + 3089 006a A166 str r1, [r4, #104] + 3090 .L244: +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3091 .loc 1 1547 7 is_stmt 1 view .LVU1139 +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3092 .loc 1 1547 9 is_stmt 0 view .LVU1140 + 3093 006c 13F4807F tst r3, #256 + 3094 0070 03D0 beq .L245 +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3095 .loc 1 1550 9 is_stmt 1 view .LVU1141 +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3096 .loc 1 1550 26 is_stmt 0 view .LVU1142 + 3097 0072 A16E ldr r1, [r4, #104] + 3098 0074 41F00801 orr r1, r1, #8 + 3099 0078 A166 str r1, [r4, #104] + 3100 .L245: +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3101 .loc 1 1553 7 is_stmt 1 view .LVU1143 +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3102 .loc 1 1553 9 is_stmt 0 view .LVU1144 + 3103 007a 13F4806F tst r3, #1024 + 3104 007e 03D0 beq .L246 +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3105 .loc 1 1556 9 is_stmt 1 view .LVU1145 +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3106 .loc 1 1556 26 is_stmt 0 view .LVU1146 + 3107 0080 A16E ldr r1, [r4, #104] + 3108 0082 41F01001 orr r1, r1, #16 + 3109 0086 A166 str r1, [r4, #104] + 3110 .L246: +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3111 .loc 1 1559 7 is_stmt 1 view .LVU1147 +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3112 .loc 1 1559 9 is_stmt 0 view .LVU1148 + 3113 0088 13F4006F tst r3, #2048 + 3114 008c 03D0 beq .L247 +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3115 .loc 1 1562 9 is_stmt 1 view .LVU1149 +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3116 .loc 1 1562 26 is_stmt 0 view .LVU1150 + 3117 008e A36E ldr r3, [r4, #104] + 3118 .LVL196: +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3119 .loc 1 1562 26 view .LVU1151 + 3120 0090 43F02003 orr r3, r3, #32 + 3121 0094 A366 str r3, [r4, #104] + 3122 .L247: +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3123 .loc 1 1566 7 is_stmt 1 view .LVU1152 + 3124 0096 0123 movs r3, #1 +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3125 .loc 1 1566 7 is_stmt 0 view .LVU1153 + ARM GAS /tmp/ccBjdYa2.s page 107 + + + 3126 0098 5360 str r3, [r2, #4] + 3127 .L241: +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3128 .loc 1 1571 3 is_stmt 1 view .LVU1154 +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3129 .loc 1 1571 7 is_stmt 0 view .LVU1155 + 3130 009a 2368 ldr r3, [r4] + 3131 009c 1A68 ldr r2, [r3] +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3132 .loc 1 1571 5 view .LVU1156 + 3133 009e 12F0100F tst r2, #16 + 3134 00a2 09D0 beq .L248 +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3135 .loc 1 1573 5 is_stmt 1 view .LVU1157 +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3136 .loc 1 1573 8 is_stmt 0 view .LVU1158 + 3137 00a4 DA68 ldr r2, [r3, #12] +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3138 .loc 1 1573 7 view .LVU1159 + 3139 00a6 12F0200F tst r2, #32 + 3140 00aa 05D0 beq .L248 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3141 .loc 1 1576 7 is_stmt 1 view .LVU1160 + 3142 00ac 1022 movs r2, #16 + 3143 00ae 5A60 str r2, [r3, #4] +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3144 .loc 1 1578 7 view .LVU1161 +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3145 .loc 1 1578 15 is_stmt 0 view .LVU1162 + 3146 00b0 A36C ldr r3, [r4, #72] +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3147 .loc 1 1578 9 view .LVU1163 + 3148 00b2 0BB1 cbz r3, .L248 +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3149 .loc 1 1581 9 is_stmt 1 view .LVU1164 + 3150 00b4 2046 mov r0, r4 + 3151 .LVL197: +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3152 .loc 1 1581 9 is_stmt 0 view .LVU1165 + 3153 00b6 9847 blx r3 + 3154 .LVL198: + 3155 .L248: +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3156 .loc 1 1587 3 is_stmt 1 view .LVU1166 +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3157 .loc 1 1587 7 is_stmt 0 view .LVU1167 + 3158 00b8 2368 ldr r3, [r4] + 3159 00ba 1A68 ldr r2, [r3] +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3160 .loc 1 1587 5 view .LVU1168 + 3161 00bc 12F0080F tst r2, #8 + 3162 00c0 09D0 beq .L249 +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3163 .loc 1 1589 5 is_stmt 1 view .LVU1169 +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3164 .loc 1 1589 8 is_stmt 0 view .LVU1170 + 3165 00c2 DA68 ldr r2, [r3, #12] + ARM GAS /tmp/ccBjdYa2.s page 108 + + +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3166 .loc 1 1589 7 view .LVU1171 + 3167 00c4 12F0100F tst r2, #16 + 3168 00c8 05D0 beq .L249 +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3169 .loc 1 1592 7 is_stmt 1 view .LVU1172 + 3170 00ca 0822 movs r2, #8 + 3171 00cc 5A60 str r2, [r3, #4] +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3172 .loc 1 1594 7 view .LVU1173 +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3173 .loc 1 1594 15 is_stmt 0 view .LVU1174 + 3174 00ce E36C ldr r3, [r4, #76] +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3175 .loc 1 1594 9 view .LVU1175 + 3176 00d0 0BB1 cbz r3, .L249 +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3177 .loc 1 1597 9 is_stmt 1 view .LVU1176 + 3178 00d2 2046 mov r0, r4 + 3179 00d4 9847 blx r3 + 3180 .LVL199: + 3181 .L249: +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3182 .loc 1 1603 3 view .LVU1177 +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3183 .loc 1 1603 7 is_stmt 0 view .LVU1178 + 3184 00d6 2368 ldr r3, [r4] + 3185 00d8 1A68 ldr r2, [r3] +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3186 .loc 1 1603 5 view .LVU1179 + 3187 00da 12F0040F tst r2, #4 + 3188 00de 09D0 beq .L250 +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3189 .loc 1 1605 5 is_stmt 1 view .LVU1180 +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3190 .loc 1 1605 8 is_stmt 0 view .LVU1181 + 3191 00e0 DA68 ldr r2, [r3, #12] +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3192 .loc 1 1605 7 view .LVU1182 + 3193 00e2 12F0080F tst r2, #8 + 3194 00e6 05D0 beq .L250 +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3195 .loc 1 1608 7 is_stmt 1 view .LVU1183 + 3196 00e8 0422 movs r2, #4 + 3197 00ea 5A60 str r2, [r3, #4] +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3198 .loc 1 1610 7 view .LVU1184 +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3199 .loc 1 1610 15 is_stmt 0 view .LVU1185 + 3200 00ec 236D ldr r3, [r4, #80] +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3201 .loc 1 1610 9 view .LVU1186 + 3202 00ee 0BB1 cbz r3, .L250 +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3203 .loc 1 1613 9 is_stmt 1 view .LVU1187 + 3204 00f0 2046 mov r0, r4 + 3205 00f2 9847 blx r3 + ARM GAS /tmp/ccBjdYa2.s page 109 + + + 3206 .LVL200: + 3207 .L250: +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3208 .loc 1 1619 3 view .LVU1188 +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3209 .loc 1 1619 7 is_stmt 0 view .LVU1189 + 3210 00f4 2368 ldr r3, [r4] + 3211 00f6 1A68 ldr r2, [r3] +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3212 .loc 1 1619 5 view .LVU1190 + 3213 00f8 12F0020F tst r2, #2 + 3214 00fc 19D0 beq .L251 +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3215 .loc 1 1621 5 is_stmt 1 view .LVU1191 +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3216 .loc 1 1621 8 is_stmt 0 view .LVU1192 + 3217 00fe DA68 ldr r2, [r3, #12] +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3218 .loc 1 1621 7 view .LVU1193 + 3219 0100 12F0040F tst r2, #4 + 3220 0104 15D0 beq .L251 +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3221 .loc 1 1624 7 is_stmt 1 view .LVU1194 + 3222 0106 DA68 ldr r2, [r3, #12] + 3223 0108 22F03E02 bic r2, r2, #62 + 3224 010c DA60 str r2, [r3, #12] +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3225 .loc 1 1626 7 view .LVU1195 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3226 .loc 1 1626 39 is_stmt 0 view .LVU1196 + 3227 010e 94F83D30 ldrb r3, [r4, #61] @ zero_extendqisi2 + 3228 0112 DBB2 uxtb r3, r3 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3229 .loc 1 1626 9 view .LVU1197 + 3230 0114 042B cmp r3, #4 + 3231 0116 36D0 beq .L259 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3232 .loc 1 1642 7 is_stmt 1 view .LVU1198 + 3233 0118 2368 ldr r3, [r4] + 3234 011a 0222 movs r2, #2 + 3235 011c 5A60 str r2, [r3, #4] +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3236 .loc 1 1645 7 view .LVU1199 +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3237 .loc 1 1645 7 view .LVU1200 + 3238 011e 0023 movs r3, #0 + 3239 0120 84F83C30 strb r3, [r4, #60] +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3240 .loc 1 1645 7 view .LVU1201 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3241 .loc 1 1648 7 view .LVU1202 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3242 .loc 1 1648 20 is_stmt 0 view .LVU1203 + 3243 0124 0123 movs r3, #1 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3244 .loc 1 1648 20 view .LVU1204 + 3245 0126 84F83D30 strb r3, [r4, #61] + ARM GAS /tmp/ccBjdYa2.s page 110 + + +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3246 .loc 1 1650 7 is_stmt 1 view .LVU1205 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3247 .loc 1 1650 15 is_stmt 0 view .LVU1206 + 3248 012a 636C ldr r3, [r4, #68] +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3249 .loc 1 1650 9 view .LVU1207 + 3250 012c 0BB1 cbz r3, .L251 +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3251 .loc 1 1653 9 is_stmt 1 view .LVU1208 + 3252 012e 2046 mov r0, r4 + 3253 0130 9847 blx r3 + 3254 .LVL201: + 3255 .L251: +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3256 .loc 1 1659 3 view .LVU1209 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3257 .loc 1 1659 11 is_stmt 0 view .LVU1210 + 3258 0132 A36E ldr r3, [r4, #104] +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3259 .loc 1 1659 5 view .LVU1211 + 3260 0134 03B3 cbz r3, .L239 +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3261 .loc 1 1661 5 is_stmt 1 view .LVU1212 +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3262 .loc 1 1661 18 is_stmt 0 view .LVU1213 + 3263 0136 0423 movs r3, #4 + 3264 0138 84F83D30 strb r3, [r4, #61] +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3265 .loc 1 1664 5 is_stmt 1 view .LVU1214 + 3266 013c 2268 ldr r2, [r4] + 3267 013e D368 ldr r3, [r2, #12] + 3268 0140 23F00103 bic r3, r3, #1 + 3269 0144 D360 str r3, [r2, #12] + 3270 .L255: +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3271 .loc 1 1666 5 view .LVU1215 +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3272 .loc 1 1668 7 view .LVU1216 +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3273 .loc 1 1668 11 is_stmt 0 view .LVU1217 + 3274 0146 019B ldr r3, [sp, #4] + 3275 0148 0133 adds r3, r3, #1 +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3276 .loc 1 1668 10 view .LVU1218 + 3277 014a 0193 str r3, [sp, #4] + 3278 014c AB42 cmp r3, r5 + 3279 014e 04D8 bhi .L254 +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3280 .loc 1 1673 10 is_stmt 1 view .LVU1219 +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3281 .loc 1 1673 17 is_stmt 0 view .LVU1220 + 3282 0150 2368 ldr r3, [r4] +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3283 .loc 1 1673 27 view .LVU1221 + 3284 0152 DB68 ldr r3, [r3, #12] +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 111 + + + 3285 .loc 1 1673 5 view .LVU1222 + 3286 0154 13F0010F tst r3, #1 + 3287 0158 F5D1 bne .L255 + 3288 .L254: +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3289 .loc 1 1676 5 is_stmt 1 view .LVU1223 +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3290 .loc 1 1676 5 view .LVU1224 + 3291 015a 0023 movs r3, #0 + 3292 015c 84F83C30 strb r3, [r4, #60] +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3293 .loc 1 1676 5 view .LVU1225 +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3294 .loc 1 1678 5 view .LVU1226 +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3295 .loc 1 1678 14 is_stmt 0 view .LVU1227 + 3296 0160 2368 ldr r3, [r4] +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3297 .loc 1 1678 24 view .LVU1228 + 3298 0162 DB68 ldr r3, [r3, #12] +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3299 .loc 1 1678 7 view .LVU1229 + 3300 0164 13F0010F tst r3, #1 + 3301 0168 19D0 beq .L256 +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3302 .loc 1 1681 7 is_stmt 1 view .LVU1230 +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3303 .loc 1 1681 20 is_stmt 0 view .LVU1231 + 3304 016a 0323 movs r3, #3 + 3305 016c 84F83D30 strb r3, [r4, #61] + 3306 .L257: +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3307 .loc 1 1690 5 is_stmt 1 view .LVU1232 +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3308 .loc 1 1690 14 is_stmt 0 view .LVU1233 + 3309 0170 636D ldr r3, [r4, #84] +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3310 .loc 1 1690 8 view .LVU1234 + 3311 0172 0BB1 cbz r3, .L239 +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3312 .loc 1 1693 7 is_stmt 1 view .LVU1235 + 3313 0174 2046 mov r0, r4 + 3314 0176 9847 blx r3 + 3315 .LVL202: + 3316 .L239: +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3317 .loc 1 1696 1 is_stmt 0 view .LVU1236 + 3318 0178 03B0 add sp, sp, #12 + 3319 .LCFI34: + 3320 .cfi_remember_state + 3321 .cfi_def_cfa_offset 12 + 3322 @ sp needed + 3323 017a 30BD pop {r4, r5, pc} + 3324 .LVL203: + 3325 .L242: + 3326 .LCFI35: + 3327 .cfi_restore_state + ARM GAS /tmp/ccBjdYa2.s page 112 + + +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3328 .loc 1 1538 9 is_stmt 1 view .LVU1237 +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3329 .loc 1 1538 26 is_stmt 0 view .LVU1238 + 3330 017c 816E ldr r1, [r0, #104] + 3331 .LVL204: +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3332 .loc 1 1538 26 view .LVU1239 + 3333 017e 41F00201 orr r1, r1, #2 + 3334 0182 8166 str r1, [r0, #104] + 3335 0184 6BE7 b .L243 + 3336 .LVL205: + 3337 .L259: +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3338 .loc 1 1629 9 is_stmt 1 view .LVU1240 +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3339 .loc 1 1629 9 view .LVU1241 + 3340 0186 0023 movs r3, #0 + 3341 0188 84F83C30 strb r3, [r4, #60] +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3342 .loc 1 1629 9 view .LVU1242 +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3343 .loc 1 1632 9 view .LVU1243 +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3344 .loc 1 1632 22 is_stmt 0 view .LVU1244 + 3345 018c 0123 movs r3, #1 +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3346 .loc 1 1632 22 view .LVU1245 + 3347 018e 84F83D30 strb r3, [r4, #61] +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3348 .loc 1 1634 9 is_stmt 1 view .LVU1246 +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3349 .loc 1 1634 17 is_stmt 0 view .LVU1247 + 3350 0192 A36D ldr r3, [r4, #88] +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** { + 3351 .loc 1 1634 11 view .LVU1248 + 3352 0194 002B cmp r3, #0 + 3353 0196 EFD0 beq .L239 +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3354 .loc 1 1636 11 is_stmt 1 view .LVU1249 + 3355 0198 2046 mov r0, r4 + 3356 019a 9847 blx r3 + 3357 .LVL206: +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3358 .loc 1 1638 9 view .LVU1250 + 3359 019c ECE7 b .L239 + 3360 .L256: +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3361 .loc 1 1686 7 view .LVU1251 +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3362 .loc 1 1686 20 is_stmt 0 view .LVU1252 + 3363 019e 0123 movs r3, #1 +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3364 .loc 1 1686 20 view .LVU1253 + 3365 01a0 84F83D30 strb r3, [r4, #61] + 3366 01a4 E4E7 b .L257 + 3367 .L261: + ARM GAS /tmp/ccBjdYa2.s page 113 + + + 3368 01a6 00BF .align 2 + 3369 .L260: + 3370 01a8 00000000 .word SystemCoreClock + 3371 01ac B5814E1B .word 458129845 + 3372 01b0 C0FFFFAD .word -1375731776 + 3373 .cfi_endproc + 3374 .LFE157: + 3376 .section .text.HAL_MDMA_GetState,"ax",%progbits + 3377 .align 1 + 3378 .global HAL_MDMA_GetState + 3379 .syntax unified + 3380 .thumb + 3381 .thumb_func + 3382 .fpu fpv5-d16 + 3384 HAL_MDMA_GetState: + 3385 .LVL207: + 3386 .LFB158: +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hmdma->State; + 3387 .loc 1 1724 1 is_stmt 1 view -0 + 3388 .cfi_startproc + 3389 @ args = 0, pretend = 0, frame = 0 + 3390 @ frame_needed = 0, uses_anonymous_args = 0 + 3391 @ link register save eliminated. +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3392 .loc 1 1725 3 view .LVU1255 +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3393 .loc 1 1725 15 is_stmt 0 view .LVU1256 + 3394 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 3395 .LVL208: +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + 3396 .loc 1 1726 1 view .LVU1257 + 3397 0004 7047 bx lr + 3398 .cfi_endproc + 3399 .LFE158: + 3401 .section .text.HAL_MDMA_GetError,"ax",%progbits + 3402 .align 1 + 3403 .global HAL_MDMA_GetError + 3404 .syntax unified + 3405 .thumb + 3406 .thumb_func + 3407 .fpu fpv5-d16 + 3409 HAL_MDMA_GetError: + 3410 .LVL209: + 3411 .LFB159: +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** return hmdma->ErrorCode; + 3412 .loc 1 1735 1 is_stmt 1 view -0 + 3413 .cfi_startproc + 3414 @ args = 0, pretend = 0, frame = 0 + 3415 @ frame_needed = 0, uses_anonymous_args = 0 + 3416 @ link register save eliminated. +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3417 .loc 1 1736 3 view .LVU1259 +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** } + 3418 .loc 1 1736 15 is_stmt 0 view .LVU1260 + 3419 0000 806E ldr r0, [r0, #104] + 3420 .LVL210: +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c **** + ARM GAS /tmp/ccBjdYa2.s page 114 + + + 3421 .loc 1 1737 1 view .LVU1261 + 3422 0002 7047 bx lr + 3423 .cfi_endproc + 3424 .LFE159: + 3426 .text + 3427 .Letext0: + 3428 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3429 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3430 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 3431 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 3432 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 3433 .file 7 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + 3434 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccBjdYa2.s page 115 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_mdma.c + /tmp/ccBjdYa2.s:17 .text.MDMA_SetConfig:0000000000000000 $t + /tmp/ccBjdYa2.s:24 .text.MDMA_SetConfig:0000000000000000 MDMA_SetConfig + /tmp/ccBjdYa2.s:161 .text.MDMA_SetConfig:0000000000000084 $d + /tmp/ccBjdYa2.s:166 .text.MDMA_Init:0000000000000000 $t + /tmp/ccBjdYa2.s:172 .text.MDMA_Init:0000000000000000 MDMA_Init + /tmp/ccBjdYa2.s:365 .text.HAL_MDMA_Init:0000000000000000 $t + /tmp/ccBjdYa2.s:372 .text.HAL_MDMA_Init:0000000000000000 HAL_MDMA_Init + /tmp/ccBjdYa2.s:495 .text.HAL_MDMA_DeInit:0000000000000000 $t + /tmp/ccBjdYa2.s:502 .text.HAL_MDMA_DeInit:0000000000000000 HAL_MDMA_DeInit + /tmp/ccBjdYa2.s:610 .text.HAL_MDMA_ConfigPostRequestMask:0000000000000000 $t + /tmp/ccBjdYa2.s:617 .text.HAL_MDMA_ConfigPostRequestMask:0000000000000000 HAL_MDMA_ConfigPostRequestMask + /tmp/ccBjdYa2.s:755 .text.HAL_MDMA_RegisterCallback:0000000000000000 $t + /tmp/ccBjdYa2.s:762 .text.HAL_MDMA_RegisterCallback:0000000000000000 HAL_MDMA_RegisterCallback + /tmp/ccBjdYa2.s:814 .text.HAL_MDMA_RegisterCallback:000000000000002e $d + /tmp/ccBjdYa2.s:820 .text.HAL_MDMA_RegisterCallback:0000000000000034 $t + /tmp/ccBjdYa2.s:895 .text.HAL_MDMA_UnRegisterCallback:0000000000000000 $t + /tmp/ccBjdYa2.s:902 .text.HAL_MDMA_UnRegisterCallback:0000000000000000 HAL_MDMA_UnRegisterCallback + /tmp/ccBjdYa2.s:953 .text.HAL_MDMA_UnRegisterCallback:0000000000000030 $d + /tmp/ccBjdYa2.s:1046 .text.HAL_MDMA_LinkedList_CreateNode:0000000000000000 $t + /tmp/ccBjdYa2.s:1053 .text.HAL_MDMA_LinkedList_CreateNode:0000000000000000 HAL_MDMA_LinkedList_CreateNode + /tmp/ccBjdYa2.s:1353 .text.HAL_MDMA_LinkedList_AddNode:0000000000000000 $t + /tmp/ccBjdYa2.s:1360 .text.HAL_MDMA_LinkedList_AddNode:0000000000000000 HAL_MDMA_LinkedList_AddNode + /tmp/ccBjdYa2.s:1631 .text.HAL_MDMA_LinkedList_RemoveNode:0000000000000000 $t + /tmp/ccBjdYa2.s:1638 .text.HAL_MDMA_LinkedList_RemoveNode:0000000000000000 HAL_MDMA_LinkedList_RemoveNode + /tmp/ccBjdYa2.s:1876 .text.HAL_MDMA_LinkedList_EnableCircularMode:0000000000000000 $t + /tmp/ccBjdYa2.s:1883 .text.HAL_MDMA_LinkedList_EnableCircularMode:0000000000000000 HAL_MDMA_LinkedList_EnableCircularMode + /tmp/ccBjdYa2.s:1990 .text.HAL_MDMA_LinkedList_DisableCircularMode:0000000000000000 $t + /tmp/ccBjdYa2.s:1997 .text.HAL_MDMA_LinkedList_DisableCircularMode:0000000000000000 HAL_MDMA_LinkedList_DisableCircularMode + /tmp/ccBjdYa2.s:2089 .text.HAL_MDMA_Start:0000000000000000 $t + /tmp/ccBjdYa2.s:2096 .text.HAL_MDMA_Start:0000000000000000 HAL_MDMA_Start + /tmp/ccBjdYa2.s:2231 .text.HAL_MDMA_Start_IT:0000000000000000 $t + /tmp/ccBjdYa2.s:2238 .text.HAL_MDMA_Start_IT:0000000000000000 HAL_MDMA_Start_IT + /tmp/ccBjdYa2.s:2411 .text.HAL_MDMA_Abort:0000000000000000 $t + /tmp/ccBjdYa2.s:2418 .text.HAL_MDMA_Abort:0000000000000000 HAL_MDMA_Abort + /tmp/ccBjdYa2.s:2543 .text.HAL_MDMA_Abort_IT:0000000000000000 $t + /tmp/ccBjdYa2.s:2550 .text.HAL_MDMA_Abort_IT:0000000000000000 HAL_MDMA_Abort_IT + /tmp/ccBjdYa2.s:2606 .text.HAL_MDMA_PollForTransfer:0000000000000000 $t + /tmp/ccBjdYa2.s:2613 .text.HAL_MDMA_PollForTransfer:0000000000000000 HAL_MDMA_PollForTransfer + /tmp/ccBjdYa2.s:2903 .text.HAL_MDMA_GenerateSWRequest:0000000000000000 $t + /tmp/ccBjdYa2.s:2910 .text.HAL_MDMA_GenerateSWRequest:0000000000000000 HAL_MDMA_GenerateSWRequest + /tmp/ccBjdYa2.s:2987 .text.HAL_MDMA_IRQHandler:0000000000000000 $t + /tmp/ccBjdYa2.s:2994 .text.HAL_MDMA_IRQHandler:0000000000000000 HAL_MDMA_IRQHandler + /tmp/ccBjdYa2.s:3370 .text.HAL_MDMA_IRQHandler:00000000000001a8 $d + /tmp/ccBjdYa2.s:3377 .text.HAL_MDMA_GetState:0000000000000000 $t + /tmp/ccBjdYa2.s:3384 .text.HAL_MDMA_GetState:0000000000000000 HAL_MDMA_GetState + /tmp/ccBjdYa2.s:3402 .text.HAL_MDMA_GetError:0000000000000000 $t + /tmp/ccBjdYa2.s:3409 .text.HAL_MDMA_GetError:0000000000000000 HAL_MDMA_GetError + /tmp/ccBjdYa2.s:960 .text.HAL_MDMA_UnRegisterCallback:0000000000000037 $d + /tmp/ccBjdYa2.s:960 .text.HAL_MDMA_UnRegisterCallback:0000000000000038 $t + +UNDEFINED SYMBOLS +HAL_GetTick +SystemCoreClock diff --git a/build/stm32h7xx_hal_mdma.o b/build/stm32h7xx_hal_mdma.o new file mode 100644 index 0000000..a0b32da Binary files /dev/null and b/build/stm32h7xx_hal_mdma.o differ diff --git a/build/stm32h7xx_hal_msp.d b/build/stm32h7xx_hal_msp.d new file mode 100644 index 0000000..050b39d --- /dev/null +++ b/build/stm32h7xx_hal_msp.d @@ -0,0 +1,71 @@ +build/stm32h7xx_hal_msp.o: Core/Src/stm32h7xx_hal_msp.c Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: diff --git a/build/stm32h7xx_hal_msp.lst b/build/stm32h7xx_hal_msp.lst new file mode 100644 index 0000000..e5e4e5b --- /dev/null +++ b/build/stm32h7xx_hal_msp.lst @@ -0,0 +1,1055 @@ +ARM GAS /tmp/ccYeBZUP.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_msp.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_MspInit,"ax",%progbits + 17 .align 1 + 18 .global HAL_MspInit + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_MspInit: + 26 .LFB141: + 27 .file 1 "Core/Src/stm32h7xx_hal_msp.c" + 1:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32h7xx_hal_msp.c **** /** + 3:Core/Src/stm32h7xx_hal_msp.c **** ****************************************************************************** + 4:Core/Src/stm32h7xx_hal_msp.c **** * File Name : stm32h7xx_hal_msp.c + 5:Core/Src/stm32h7xx_hal_msp.c **** * Description : This file provides code for the MSP Initialization + 6:Core/Src/stm32h7xx_hal_msp.c **** * and de-Initialization codes. + 7:Core/Src/stm32h7xx_hal_msp.c **** ****************************************************************************** + 8:Core/Src/stm32h7xx_hal_msp.c **** * @attention + 9:Core/Src/stm32h7xx_hal_msp.c **** * + 10:Core/Src/stm32h7xx_hal_msp.c **** *

© Copyright (c) 2019 STMicroelectronics. + 11:Core/Src/stm32h7xx_hal_msp.c **** * All rights reserved.

+ 12:Core/Src/stm32h7xx_hal_msp.c **** * + 13:Core/Src/stm32h7xx_hal_msp.c **** * This software component is licensed by ST under BSD 3-Clause license, + 14:Core/Src/stm32h7xx_hal_msp.c **** * the "License"; You may not use this file except in compliance with the + 15:Core/Src/stm32h7xx_hal_msp.c **** * License. You may obtain a copy of the License at: + 16:Core/Src/stm32h7xx_hal_msp.c **** * opensource.org/licenses/BSD-3-Clause + 17:Core/Src/stm32h7xx_hal_msp.c **** * + 18:Core/Src/stm32h7xx_hal_msp.c **** ****************************************************************************** + 19:Core/Src/stm32h7xx_hal_msp.c **** */ + 20:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Header */ + 21:Core/Src/stm32h7xx_hal_msp.c **** + 22:Core/Src/stm32h7xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/ + 23:Core/Src/stm32h7xx_hal_msp.c **** #include "main.h" + 24:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Includes */ + 25:Core/Src/stm32h7xx_hal_msp.c **** + 26:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Includes */ + 27:Core/Src/stm32h7xx_hal_msp.c **** + 28:Core/Src/stm32h7xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/ + 29:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TD */ + 30:Core/Src/stm32h7xx_hal_msp.c **** + 31:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TD */ + ARM GAS /tmp/ccYeBZUP.s page 2 + + + 32:Core/Src/stm32h7xx_hal_msp.c **** + 33:Core/Src/stm32h7xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/ + 34:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Define */ + 35:Core/Src/stm32h7xx_hal_msp.c **** + 36:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Define */ + 37:Core/Src/stm32h7xx_hal_msp.c **** + 38:Core/Src/stm32h7xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/ + 39:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Macro */ + 40:Core/Src/stm32h7xx_hal_msp.c **** + 41:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Macro */ + 42:Core/Src/stm32h7xx_hal_msp.c **** + 43:Core/Src/stm32h7xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/ + 44:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN PV */ + 45:Core/Src/stm32h7xx_hal_msp.c **** + 46:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END PV */ + 47:Core/Src/stm32h7xx_hal_msp.c **** + 48:Core/Src/stm32h7xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/ + 49:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN PFP */ + 50:Core/Src/stm32h7xx_hal_msp.c **** + 51:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END PFP */ + 52:Core/Src/stm32h7xx_hal_msp.c **** + 53:Core/Src/stm32h7xx_hal_msp.c **** /* External functions --------------------------------------------------------*/ + 54:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */ + 55:Core/Src/stm32h7xx_hal_msp.c **** + 56:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ExternalFunctions */ + 57:Core/Src/stm32h7xx_hal_msp.c **** + 58:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN 0 */ + 59:Core/Src/stm32h7xx_hal_msp.c **** + 60:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END 0 */ + 61:Core/Src/stm32h7xx_hal_msp.c **** /** + 62:Core/Src/stm32h7xx_hal_msp.c **** * Initializes the Global MSP. + 63:Core/Src/stm32h7xx_hal_msp.c **** */ + 64:Core/Src/stm32h7xx_hal_msp.c **** void HAL_MspInit(void) + 65:Core/Src/stm32h7xx_hal_msp.c **** { + 28 .loc 1 65 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 00B5 push {lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 4 + 35 .cfi_offset 14, -4 + 36 0002 83B0 sub sp, sp, #12 + 37 .LCFI1: + 38 .cfi_def_cfa_offset 16 + 66:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */ + 67:Core/Src/stm32h7xx_hal_msp.c **** + 68:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END MspInit 0 */ + 69:Core/Src/stm32h7xx_hal_msp.c **** + 70:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 39 .loc 1 70 3 view .LVU1 + 40 .LBB2: + 41 .loc 1 70 3 view .LVU2 + 42 .loc 1 70 3 view .LVU3 + 43 0004 1B4B ldr r3, .L3 + 44 0006 D3F8F420 ldr r2, [r3, #244] + 45 000a 42F00202 orr r2, r2, #2 + ARM GAS /tmp/ccYeBZUP.s page 3 + + + 46 000e C3F8F420 str r2, [r3, #244] + 47 .loc 1 70 3 view .LVU4 + 48 0012 D3F8F430 ldr r3, [r3, #244] + 49 0016 03F00203 and r3, r3, #2 + 50 001a 0193 str r3, [sp, #4] + 51 .loc 1 70 3 view .LVU5 + 52 001c 019B ldr r3, [sp, #4] + 53 .LBE2: + 54 .loc 1 70 3 view .LVU6 + 71:Core/Src/stm32h7xx_hal_msp.c **** + 72:Core/Src/stm32h7xx_hal_msp.c **** /* System interrupt init*/ + 73:Core/Src/stm32h7xx_hal_msp.c **** + 74:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral interrupt init */ + 75:Core/Src/stm32h7xx_hal_msp.c **** /* PVD_AVD_IRQn interrupt configuration */ + 76:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(PVD_AVD_IRQn, 0, 0); + 55 .loc 1 76 3 view .LVU7 + 56 001e 0022 movs r2, #0 + 57 0020 1146 mov r1, r2 + 58 0022 0120 movs r0, #1 + 59 0024 FFF7FEFF bl HAL_NVIC_SetPriority + 60 .LVL0: + 77:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(PVD_AVD_IRQn); + 61 .loc 1 77 3 view .LVU8 + 62 0028 0120 movs r0, #1 + 63 002a FFF7FEFF bl HAL_NVIC_EnableIRQ + 64 .LVL1: + 78:Core/Src/stm32h7xx_hal_msp.c **** /* FLASH_IRQn interrupt configuration */ + 79:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(FLASH_IRQn, 0, 0); + 65 .loc 1 79 3 view .LVU9 + 66 002e 0022 movs r2, #0 + 67 0030 1146 mov r1, r2 + 68 0032 0420 movs r0, #4 + 69 0034 FFF7FEFF bl HAL_NVIC_SetPriority + 70 .LVL2: + 80:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(FLASH_IRQn); + 71 .loc 1 80 3 view .LVU10 + 72 0038 0420 movs r0, #4 + 73 003a FFF7FEFF bl HAL_NVIC_EnableIRQ + 74 .LVL3: + 81:Core/Src/stm32h7xx_hal_msp.c **** /* RCC_IRQn interrupt configuration */ + 82:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(RCC_IRQn, 0, 0); + 75 .loc 1 82 3 view .LVU11 + 76 003e 0022 movs r2, #0 + 77 0040 1146 mov r1, r2 + 78 0042 0520 movs r0, #5 + 79 0044 FFF7FEFF bl HAL_NVIC_SetPriority + 80 .LVL4: + 83:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(RCC_IRQn); + 81 .loc 1 83 3 view .LVU12 + 82 0048 0520 movs r0, #5 + 83 004a FFF7FEFF bl HAL_NVIC_EnableIRQ + 84 .LVL5: + 84:Core/Src/stm32h7xx_hal_msp.c **** /* FPU_IRQn interrupt configuration */ + 85:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(FPU_IRQn, 0, 0); + 85 .loc 1 85 3 view .LVU13 + 86 004e 0022 movs r2, #0 + 87 0050 1146 mov r1, r2 + ARM GAS /tmp/ccYeBZUP.s page 4 + + + 88 0052 5120 movs r0, #81 + 89 0054 FFF7FEFF bl HAL_NVIC_SetPriority + 90 .LVL6: + 86:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(FPU_IRQn); + 91 .loc 1 86 3 view .LVU14 + 92 0058 5120 movs r0, #81 + 93 005a FFF7FEFF bl HAL_NVIC_EnableIRQ + 94 .LVL7: + 87:Core/Src/stm32h7xx_hal_msp.c **** /* HSEM1_IRQn interrupt configuration */ + 88:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(HSEM1_IRQn, 0, 0); + 95 .loc 1 88 3 view .LVU15 + 96 005e 0022 movs r2, #0 + 97 0060 1146 mov r1, r2 + 98 0062 7D20 movs r0, #125 + 99 0064 FFF7FEFF bl HAL_NVIC_SetPriority + 100 .LVL8: + 89:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(HSEM1_IRQn); + 101 .loc 1 89 3 view .LVU16 + 102 0068 7D20 movs r0, #125 + 103 006a FFF7FEFF bl HAL_NVIC_EnableIRQ + 104 .LVL9: + 90:Core/Src/stm32h7xx_hal_msp.c **** + 91:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */ + 92:Core/Src/stm32h7xx_hal_msp.c **** + 93:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END MspInit 1 */ + 94:Core/Src/stm32h7xx_hal_msp.c **** } + 105 .loc 1 94 1 is_stmt 0 view .LVU17 + 106 006e 03B0 add sp, sp, #12 + 107 .LCFI2: + 108 .cfi_def_cfa_offset 4 + 109 @ sp needed + 110 0070 5DF804FB ldr pc, [sp], #4 + 111 .L4: + 112 .align 2 + 113 .L3: + 114 0074 00440258 .word 1476543488 + 115 .cfi_endproc + 116 .LFE141: + 118 .section .text.HAL_QSPI_MspInit,"ax",%progbits + 119 .align 1 + 120 .global HAL_QSPI_MspInit + 121 .syntax unified + 122 .thumb + 123 .thumb_func + 124 .fpu fpv5-d16 + 126 HAL_QSPI_MspInit: + 127 .LVL10: + 128 .LFB142: + 95:Core/Src/stm32h7xx_hal_msp.c **** + 96:Core/Src/stm32h7xx_hal_msp.c **** /** + 97:Core/Src/stm32h7xx_hal_msp.c **** * @brief QSPI MSP Initialization + 98:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example + 99:Core/Src/stm32h7xx_hal_msp.c **** * @param hqspi: QSPI handle pointer + 100:Core/Src/stm32h7xx_hal_msp.c **** * @retval None + 101:Core/Src/stm32h7xx_hal_msp.c **** */ + 102:Core/Src/stm32h7xx_hal_msp.c **** void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) + 103:Core/Src/stm32h7xx_hal_msp.c **** { + ARM GAS /tmp/ccYeBZUP.s page 5 + + + 129 .loc 1 103 1 is_stmt 1 view -0 + 130 .cfi_startproc + 131 @ args = 0, pretend = 0, frame = 40 + 132 @ frame_needed = 0, uses_anonymous_args = 0 + 133 .loc 1 103 1 is_stmt 0 view .LVU19 + 134 0000 F0B5 push {r4, r5, r6, r7, lr} + 135 .LCFI3: + 136 .cfi_def_cfa_offset 20 + 137 .cfi_offset 4, -20 + 138 .cfi_offset 5, -16 + 139 .cfi_offset 6, -12 + 140 .cfi_offset 7, -8 + 141 .cfi_offset 14, -4 + 142 0002 8BB0 sub sp, sp, #44 + 143 .LCFI4: + 144 .cfi_def_cfa_offset 64 + 104:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 145 .loc 1 104 3 is_stmt 1 view .LVU20 + 146 .loc 1 104 20 is_stmt 0 view .LVU21 + 147 0004 0023 movs r3, #0 + 148 0006 0593 str r3, [sp, #20] + 149 0008 0693 str r3, [sp, #24] + 150 000a 0793 str r3, [sp, #28] + 151 000c 0893 str r3, [sp, #32] + 152 000e 0993 str r3, [sp, #36] + 105:Core/Src/stm32h7xx_hal_msp.c **** if(hqspi->Instance==QUADSPI) + 153 .loc 1 105 3 is_stmt 1 view .LVU22 + 154 .loc 1 105 11 is_stmt 0 view .LVU23 + 155 0010 0268 ldr r2, [r0] + 156 .loc 1 105 5 view .LVU24 + 157 0012 354B ldr r3, .L9 + 158 0014 9A42 cmp r2, r3 + 159 0016 01D0 beq .L8 + 160 .LVL11: + 161 .L5: + 106:Core/Src/stm32h7xx_hal_msp.c **** { + 107:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspInit 0 */ + 108:Core/Src/stm32h7xx_hal_msp.c **** + 109:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspInit 0 */ + 110:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */ + 111:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_QSPI_CLK_ENABLE(); + 112:Core/Src/stm32h7xx_hal_msp.c **** + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 115:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 116:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 117:Core/Src/stm32h7xx_hal_msp.c **** PE2 ------> QUADSPI_BK1_IO2 + 118:Core/Src/stm32h7xx_hal_msp.c **** PB2 ------> QUADSPI_CLK + 119:Core/Src/stm32h7xx_hal_msp.c **** PD11 ------> QUADSPI_BK1_IO0 + 120:Core/Src/stm32h7xx_hal_msp.c **** PD12 ------> QUADSPI_BK1_IO1 + 121:Core/Src/stm32h7xx_hal_msp.c **** PD13 ------> QUADSPI_BK1_IO3 + 122:Core/Src/stm32h7xx_hal_msp.c **** PB6 ------> QUADSPI_BK1_NCS + 123:Core/Src/stm32h7xx_hal_msp.c **** */ + 124:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2; + 125:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 126:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 127:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + ARM GAS /tmp/ccYeBZUP.s page 6 + + + 128:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 129:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 130:Core/Src/stm32h7xx_hal_msp.c **** + 131:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2; + 132:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 133:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 134:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 135:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 136:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 137:Core/Src/stm32h7xx_hal_msp.c **** + 138:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13; + 139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 140:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 142:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 143:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 144:Core/Src/stm32h7xx_hal_msp.c **** + 145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_6; + 146:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 149:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + 150:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 151:Core/Src/stm32h7xx_hal_msp.c **** + 152:Core/Src/stm32h7xx_hal_msp.c **** /* QUADSPI interrupt Init */ + 153:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(QUADSPI_IRQn, 1, 0); + 154:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(QUADSPI_IRQn); + 155:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspInit 1 */ + 156:Core/Src/stm32h7xx_hal_msp.c **** + 157:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspInit 1 */ + 158:Core/Src/stm32h7xx_hal_msp.c **** } + 159:Core/Src/stm32h7xx_hal_msp.c **** + 160:Core/Src/stm32h7xx_hal_msp.c **** } + 162 .loc 1 160 1 view .LVU25 + 163 0018 0BB0 add sp, sp, #44 + 164 .LCFI5: + 165 .cfi_remember_state + 166 .cfi_def_cfa_offset 20 + 167 @ sp needed + 168 001a F0BD pop {r4, r5, r6, r7, pc} + 169 .LVL12: + 170 .L8: + 171 .LCFI6: + 172 .cfi_restore_state + 111:Core/Src/stm32h7xx_hal_msp.c **** + 173 .loc 1 111 5 is_stmt 1 view .LVU26 + 174 .LBB3: + 111:Core/Src/stm32h7xx_hal_msp.c **** + 175 .loc 1 111 5 view .LVU27 + 111:Core/Src/stm32h7xx_hal_msp.c **** + 176 .loc 1 111 5 view .LVU28 + 177 001c 334B ldr r3, .L9+4 + 178 001e D3F8D420 ldr r2, [r3, #212] + 179 0022 42F48042 orr r2, r2, #16384 + 180 0026 C3F8D420 str r2, [r3, #212] + 111:Core/Src/stm32h7xx_hal_msp.c **** + 181 .loc 1 111 5 view .LVU29 + ARM GAS /tmp/ccYeBZUP.s page 7 + + + 182 002a D3F8D420 ldr r2, [r3, #212] + 183 002e 02F48042 and r2, r2, #16384 + 184 0032 0192 str r2, [sp, #4] + 111:Core/Src/stm32h7xx_hal_msp.c **** + 185 .loc 1 111 5 view .LVU30 + 186 0034 019A ldr r2, [sp, #4] + 187 .LBE3: + 111:Core/Src/stm32h7xx_hal_msp.c **** + 188 .loc 1 111 5 view .LVU31 + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 189 .loc 1 113 5 view .LVU32 + 190 .LBB4: + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 191 .loc 1 113 5 view .LVU33 + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 192 .loc 1 113 5 view .LVU34 + 193 0036 D3F8E020 ldr r2, [r3, #224] + 194 003a 42F01002 orr r2, r2, #16 + 195 003e C3F8E020 str r2, [r3, #224] + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 196 .loc 1 113 5 view .LVU35 + 197 0042 D3F8E020 ldr r2, [r3, #224] + 198 0046 02F01002 and r2, r2, #16 + 199 004a 0292 str r2, [sp, #8] + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 200 .loc 1 113 5 view .LVU36 + 201 004c 029A ldr r2, [sp, #8] + 202 .LBE4: + 113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 203 .loc 1 113 5 view .LVU37 + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 204 .loc 1 114 5 view .LVU38 + 205 .LBB5: + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 206 .loc 1 114 5 view .LVU39 + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 207 .loc 1 114 5 view .LVU40 + 208 004e D3F8E020 ldr r2, [r3, #224] + 209 0052 42F00202 orr r2, r2, #2 + 210 0056 C3F8E020 str r2, [r3, #224] + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 211 .loc 1 114 5 view .LVU41 + 212 005a D3F8E020 ldr r2, [r3, #224] + 213 005e 02F00202 and r2, r2, #2 + 214 0062 0392 str r2, [sp, #12] + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 215 .loc 1 114 5 view .LVU42 + 216 0064 039A ldr r2, [sp, #12] + 217 .LBE5: + 114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 218 .loc 1 114 5 view .LVU43 + 115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 219 .loc 1 115 5 view .LVU44 + 220 .LBB6: + 115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 221 .loc 1 115 5 view .LVU45 + 115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + ARM GAS /tmp/ccYeBZUP.s page 8 + + + 222 .loc 1 115 5 view .LVU46 + 223 0066 D3F8E020 ldr r2, [r3, #224] + 224 006a 42F00802 orr r2, r2, #8 + 225 006e C3F8E020 str r2, [r3, #224] + 115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 226 .loc 1 115 5 view .LVU47 + 227 0072 D3F8E030 ldr r3, [r3, #224] + 228 0076 03F00803 and r3, r3, #8 + 229 007a 0493 str r3, [sp, #16] + 115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 230 .loc 1 115 5 view .LVU48 + 231 007c 049B ldr r3, [sp, #16] + 232 .LBE6: + 115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 233 .loc 1 115 5 view .LVU49 + 124:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 234 .loc 1 124 5 view .LVU50 + 124:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 235 .loc 1 124 25 is_stmt 0 view .LVU51 + 236 007e 0424 movs r4, #4 + 237 0080 0594 str r4, [sp, #20] + 125:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 238 .loc 1 125 5 is_stmt 1 view .LVU52 + 125:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 239 .loc 1 125 26 is_stmt 0 view .LVU53 + 240 0082 0225 movs r5, #2 + 241 0084 0695 str r5, [sp, #24] + 126:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 242 .loc 1 126 5 is_stmt 1 view .LVU54 + 127:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 243 .loc 1 127 5 view .LVU55 + 128:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 244 .loc 1 128 5 view .LVU56 + 128:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 245 .loc 1 128 31 is_stmt 0 view .LVU57 + 246 0086 0926 movs r6, #9 + 247 0088 0996 str r6, [sp, #36] + 129:Core/Src/stm32h7xx_hal_msp.c **** + 248 .loc 1 129 5 is_stmt 1 view .LVU58 + 249 008a 05A9 add r1, sp, #20 + 250 008c 1848 ldr r0, .L9+8 + 251 .LVL13: + 129:Core/Src/stm32h7xx_hal_msp.c **** + 252 .loc 1 129 5 is_stmt 0 view .LVU59 + 253 008e FFF7FEFF bl HAL_GPIO_Init + 254 .LVL14: + 131:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 255 .loc 1 131 5 is_stmt 1 view .LVU60 + 131:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 256 .loc 1 131 25 is_stmt 0 view .LVU61 + 257 0092 0594 str r4, [sp, #20] + 132:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 258 .loc 1 132 5 is_stmt 1 view .LVU62 + 132:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 259 .loc 1 132 26 is_stmt 0 view .LVU63 + 260 0094 0695 str r5, [sp, #24] + 133:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + ARM GAS /tmp/ccYeBZUP.s page 9 + + + 261 .loc 1 133 5 is_stmt 1 view .LVU64 + 133:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 262 .loc 1 133 26 is_stmt 0 view .LVU65 + 263 0096 0024 movs r4, #0 + 264 0098 0794 str r4, [sp, #28] + 134:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 265 .loc 1 134 5 is_stmt 1 view .LVU66 + 134:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 266 .loc 1 134 27 is_stmt 0 view .LVU67 + 267 009a 0894 str r4, [sp, #32] + 135:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 268 .loc 1 135 5 is_stmt 1 view .LVU68 + 135:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 269 .loc 1 135 31 is_stmt 0 view .LVU69 + 270 009c 0996 str r6, [sp, #36] + 136:Core/Src/stm32h7xx_hal_msp.c **** + 271 .loc 1 136 5 is_stmt 1 view .LVU70 + 272 009e 154F ldr r7, .L9+12 + 273 00a0 05A9 add r1, sp, #20 + 274 00a2 3846 mov r0, r7 + 275 00a4 FFF7FEFF bl HAL_GPIO_Init + 276 .LVL15: + 138:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 277 .loc 1 138 5 view .LVU71 + 138:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 278 .loc 1 138 25 is_stmt 0 view .LVU72 + 279 00a8 4FF46053 mov r3, #14336 + 280 00ac 0593 str r3, [sp, #20] + 139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 281 .loc 1 139 5 is_stmt 1 view .LVU73 + 139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 282 .loc 1 139 26 is_stmt 0 view .LVU74 + 283 00ae 0695 str r5, [sp, #24] + 140:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 284 .loc 1 140 5 is_stmt 1 view .LVU75 + 140:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 285 .loc 1 140 26 is_stmt 0 view .LVU76 + 286 00b0 0794 str r4, [sp, #28] + 141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 287 .loc 1 141 5 is_stmt 1 view .LVU77 + 141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + 288 .loc 1 141 27 is_stmt 0 view .LVU78 + 289 00b2 0894 str r4, [sp, #32] + 142:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 290 .loc 1 142 5 is_stmt 1 view .LVU79 + 142:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 291 .loc 1 142 31 is_stmt 0 view .LVU80 + 292 00b4 0996 str r6, [sp, #36] + 143:Core/Src/stm32h7xx_hal_msp.c **** + 293 .loc 1 143 5 is_stmt 1 view .LVU81 + 294 00b6 05A9 add r1, sp, #20 + 295 00b8 0F48 ldr r0, .L9+16 + 296 00ba FFF7FEFF bl HAL_GPIO_Init + 297 .LVL16: + 145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 298 .loc 1 145 5 view .LVU82 + 145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + ARM GAS /tmp/ccYeBZUP.s page 10 + + + 299 .loc 1 145 25 is_stmt 0 view .LVU83 + 300 00be 4023 movs r3, #64 + 301 00c0 0593 str r3, [sp, #20] + 146:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 302 .loc 1 146 5 is_stmt 1 view .LVU84 + 146:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 303 .loc 1 146 26 is_stmt 0 view .LVU85 + 304 00c2 0695 str r5, [sp, #24] + 147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 305 .loc 1 147 5 is_stmt 1 view .LVU86 + 147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 306 .loc 1 147 26 is_stmt 0 view .LVU87 + 307 00c4 0794 str r4, [sp, #28] + 148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + 308 .loc 1 148 5 is_stmt 1 view .LVU88 + 148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + 309 .loc 1 148 27 is_stmt 0 view .LVU89 + 310 00c6 0894 str r4, [sp, #32] + 149:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 311 .loc 1 149 5 is_stmt 1 view .LVU90 + 149:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 312 .loc 1 149 31 is_stmt 0 view .LVU91 + 313 00c8 0A23 movs r3, #10 + 314 00ca 0993 str r3, [sp, #36] + 150:Core/Src/stm32h7xx_hal_msp.c **** + 315 .loc 1 150 5 is_stmt 1 view .LVU92 + 316 00cc 05A9 add r1, sp, #20 + 317 00ce 3846 mov r0, r7 + 318 00d0 FFF7FEFF bl HAL_GPIO_Init + 319 .LVL17: + 153:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(QUADSPI_IRQn); + 320 .loc 1 153 5 view .LVU93 + 321 00d4 2246 mov r2, r4 + 322 00d6 0121 movs r1, #1 + 323 00d8 5C20 movs r0, #92 + 324 00da FFF7FEFF bl HAL_NVIC_SetPriority + 325 .LVL18: + 154:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspInit 1 */ + 326 .loc 1 154 5 view .LVU94 + 327 00de 5C20 movs r0, #92 + 328 00e0 FFF7FEFF bl HAL_NVIC_EnableIRQ + 329 .LVL19: + 330 .loc 1 160 1 is_stmt 0 view .LVU95 + 331 00e4 98E7 b .L5 + 332 .L10: + 333 00e6 00BF .align 2 + 334 .L9: + 335 00e8 00500052 .word 1375752192 + 336 00ec 00440258 .word 1476543488 + 337 00f0 00100258 .word 1476530176 + 338 00f4 00040258 .word 1476527104 + 339 00f8 000C0258 .word 1476529152 + 340 .cfi_endproc + 341 .LFE142: + 343 .section .text.HAL_QSPI_MspDeInit,"ax",%progbits + 344 .align 1 + 345 .global HAL_QSPI_MspDeInit + ARM GAS /tmp/ccYeBZUP.s page 11 + + + 346 .syntax unified + 347 .thumb + 348 .thumb_func + 349 .fpu fpv5-d16 + 351 HAL_QSPI_MspDeInit: + 352 .LVL20: + 353 .LFB143: + 161:Core/Src/stm32h7xx_hal_msp.c **** + 162:Core/Src/stm32h7xx_hal_msp.c **** /** + 163:Core/Src/stm32h7xx_hal_msp.c **** * @brief QSPI MSP De-Initialization + 164:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 165:Core/Src/stm32h7xx_hal_msp.c **** * @param hqspi: QSPI handle pointer + 166:Core/Src/stm32h7xx_hal_msp.c **** * @retval None + 167:Core/Src/stm32h7xx_hal_msp.c **** */ + 168:Core/Src/stm32h7xx_hal_msp.c **** void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) + 169:Core/Src/stm32h7xx_hal_msp.c **** { + 354 .loc 1 169 1 is_stmt 1 view -0 + 355 .cfi_startproc + 356 @ args = 0, pretend = 0, frame = 0 + 357 @ frame_needed = 0, uses_anonymous_args = 0 + 358 .loc 1 169 1 is_stmt 0 view .LVU97 + 359 0000 08B5 push {r3, lr} + 360 .LCFI7: + 361 .cfi_def_cfa_offset 8 + 362 .cfi_offset 3, -8 + 363 .cfi_offset 14, -4 + 170:Core/Src/stm32h7xx_hal_msp.c **** if(hqspi->Instance==QUADSPI) + 364 .loc 1 170 3 is_stmt 1 view .LVU98 + 365 .loc 1 170 11 is_stmt 0 view .LVU99 + 366 0002 0268 ldr r2, [r0] + 367 .loc 1 170 5 view .LVU100 + 368 0004 0D4B ldr r3, .L15 + 369 0006 9A42 cmp r2, r3 + 370 0008 00D0 beq .L14 + 371 .LVL21: + 372 .L11: + 171:Core/Src/stm32h7xx_hal_msp.c **** { + 172:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + 173:Core/Src/stm32h7xx_hal_msp.c **** + 174:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspDeInit 0 */ + 175:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */ + 176:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_QSPI_CLK_DISABLE(); + 177:Core/Src/stm32h7xx_hal_msp.c **** + 178:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration + 179:Core/Src/stm32h7xx_hal_msp.c **** PE2 ------> QUADSPI_BK1_IO2 + 180:Core/Src/stm32h7xx_hal_msp.c **** PB2 ------> QUADSPI_CLK + 181:Core/Src/stm32h7xx_hal_msp.c **** PD11 ------> QUADSPI_BK1_IO0 + 182:Core/Src/stm32h7xx_hal_msp.c **** PD12 ------> QUADSPI_BK1_IO1 + 183:Core/Src/stm32h7xx_hal_msp.c **** PD13 ------> QUADSPI_BK1_IO3 + 184:Core/Src/stm32h7xx_hal_msp.c **** PB6 ------> QUADSPI_BK1_NCS + 185:Core/Src/stm32h7xx_hal_msp.c **** */ + 186:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2); + 187:Core/Src/stm32h7xx_hal_msp.c **** + 188:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_6); + 189:Core/Src/stm32h7xx_hal_msp.c **** + 190:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13); + 191:Core/Src/stm32h7xx_hal_msp.c **** + ARM GAS /tmp/ccYeBZUP.s page 12 + + + 192:Core/Src/stm32h7xx_hal_msp.c **** /* QUADSPI interrupt DeInit */ + 193:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(QUADSPI_IRQn); + 194:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + 195:Core/Src/stm32h7xx_hal_msp.c **** + 196:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspDeInit 1 */ + 197:Core/Src/stm32h7xx_hal_msp.c **** } + 198:Core/Src/stm32h7xx_hal_msp.c **** + 199:Core/Src/stm32h7xx_hal_msp.c **** } + 373 .loc 1 199 1 view .LVU101 + 374 000a 08BD pop {r3, pc} + 375 .LVL22: + 376 .L14: + 176:Core/Src/stm32h7xx_hal_msp.c **** + 377 .loc 1 176 5 is_stmt 1 view .LVU102 + 378 000c 0C4A ldr r2, .L15+4 + 379 000e D2F8D430 ldr r3, [r2, #212] + 380 0012 23F48043 bic r3, r3, #16384 + 381 0016 C2F8D430 str r3, [r2, #212] + 186:Core/Src/stm32h7xx_hal_msp.c **** + 382 .loc 1 186 5 view .LVU103 + 383 001a 0421 movs r1, #4 + 384 001c 0948 ldr r0, .L15+8 + 385 .LVL23: + 186:Core/Src/stm32h7xx_hal_msp.c **** + 386 .loc 1 186 5 is_stmt 0 view .LVU104 + 387 001e FFF7FEFF bl HAL_GPIO_DeInit + 388 .LVL24: + 188:Core/Src/stm32h7xx_hal_msp.c **** + 389 .loc 1 188 5 is_stmt 1 view .LVU105 + 390 0022 4421 movs r1, #68 + 391 0024 0848 ldr r0, .L15+12 + 392 0026 FFF7FEFF bl HAL_GPIO_DeInit + 393 .LVL25: + 190:Core/Src/stm32h7xx_hal_msp.c **** + 394 .loc 1 190 5 view .LVU106 + 395 002a 4FF46051 mov r1, #14336 + 396 002e 0748 ldr r0, .L15+16 + 397 0030 FFF7FEFF bl HAL_GPIO_DeInit + 398 .LVL26: + 193:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + 399 .loc 1 193 5 view .LVU107 + 400 0034 5C20 movs r0, #92 + 401 0036 FFF7FEFF bl HAL_NVIC_DisableIRQ + 402 .LVL27: + 403 .loc 1 199 1 is_stmt 0 view .LVU108 + 404 003a E6E7 b .L11 + 405 .L16: + 406 .align 2 + 407 .L15: + 408 003c 00500052 .word 1375752192 + 409 0040 00440258 .word 1476543488 + 410 0044 00100258 .word 1476530176 + 411 0048 00040258 .word 1476527104 + 412 004c 000C0258 .word 1476529152 + 413 .cfi_endproc + 414 .LFE143: + 416 .section .text.HAL_UART_MspInit,"ax",%progbits + ARM GAS /tmp/ccYeBZUP.s page 13 + + + 417 .align 1 + 418 .global HAL_UART_MspInit + 419 .syntax unified + 420 .thumb + 421 .thumb_func + 422 .fpu fpv5-d16 + 424 HAL_UART_MspInit: + 425 .LVL28: + 426 .LFB144: + 200:Core/Src/stm32h7xx_hal_msp.c **** + 201:Core/Src/stm32h7xx_hal_msp.c **** /** + 202:Core/Src/stm32h7xx_hal_msp.c **** * @brief UART MSP Initialization + 203:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example + 204:Core/Src/stm32h7xx_hal_msp.c **** * @param huart: UART handle pointer + 205:Core/Src/stm32h7xx_hal_msp.c **** * @retval None + 206:Core/Src/stm32h7xx_hal_msp.c **** */ + 207:Core/Src/stm32h7xx_hal_msp.c **** void HAL_UART_MspInit(UART_HandleTypeDef* huart) + 208:Core/Src/stm32h7xx_hal_msp.c **** { + 427 .loc 1 208 1 is_stmt 1 view -0 + 428 .cfi_startproc + 429 @ args = 0, pretend = 0, frame = 32 + 430 @ frame_needed = 0, uses_anonymous_args = 0 + 431 .loc 1 208 1 is_stmt 0 view .LVU110 + 432 0000 00B5 push {lr} + 433 .LCFI8: + 434 .cfi_def_cfa_offset 4 + 435 .cfi_offset 14, -4 + 436 0002 89B0 sub sp, sp, #36 + 437 .LCFI9: + 438 .cfi_def_cfa_offset 40 + 209:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 439 .loc 1 209 3 is_stmt 1 view .LVU111 + 440 .loc 1 209 20 is_stmt 0 view .LVU112 + 441 0004 0023 movs r3, #0 + 442 0006 0393 str r3, [sp, #12] + 443 0008 0493 str r3, [sp, #16] + 444 000a 0593 str r3, [sp, #20] + 445 000c 0693 str r3, [sp, #24] + 446 000e 0793 str r3, [sp, #28] + 210:Core/Src/stm32h7xx_hal_msp.c **** if(huart->Instance==USART1) + 447 .loc 1 210 3 is_stmt 1 view .LVU113 + 448 .loc 1 210 11 is_stmt 0 view .LVU114 + 449 0010 0268 ldr r2, [r0] + 450 .loc 1 210 5 view .LVU115 + 451 0012 03F18043 add r3, r3, #1073741824 + 452 0016 03F58833 add r3, r3, #69632 + 453 001a 9A42 cmp r2, r3 + 454 001c 02D0 beq .L20 + 455 .LVL29: + 456 .L17: + 211:Core/Src/stm32h7xx_hal_msp.c **** { + 212:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 0 */ + 213:Core/Src/stm32h7xx_hal_msp.c **** + 214:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspInit 0 */ + 215:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */ + 216:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_USART1_CLK_ENABLE(); + 217:Core/Src/stm32h7xx_hal_msp.c **** + ARM GAS /tmp/ccYeBZUP.s page 14 + + + 218:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 219:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 220:Core/Src/stm32h7xx_hal_msp.c **** PA9 ------> USART1_TX + 221:Core/Src/stm32h7xx_hal_msp.c **** PA10 ------> USART1_RX + 222:Core/Src/stm32h7xx_hal_msp.c **** */ + 223:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + 224:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 225:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 226:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 227:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 228:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 229:Core/Src/stm32h7xx_hal_msp.c **** + 230:Core/Src/stm32h7xx_hal_msp.c **** /* USART1 interrupt Init */ + 231:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(USART1_IRQn, 1, 0); + 232:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USART1_IRQn); + 233:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 1 */ + 234:Core/Src/stm32h7xx_hal_msp.c **** + 235:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspInit 1 */ + 236:Core/Src/stm32h7xx_hal_msp.c **** } + 237:Core/Src/stm32h7xx_hal_msp.c **** + 238:Core/Src/stm32h7xx_hal_msp.c **** } + 457 .loc 1 238 1 view .LVU116 + 458 001e 09B0 add sp, sp, #36 + 459 .LCFI10: + 460 .cfi_remember_state + 461 .cfi_def_cfa_offset 4 + 462 @ sp needed + 463 0020 5DF804FB ldr pc, [sp], #4 + 464 .LVL30: + 465 .L20: + 466 .LCFI11: + 467 .cfi_restore_state + 216:Core/Src/stm32h7xx_hal_msp.c **** + 468 .loc 1 216 5 is_stmt 1 view .LVU117 + 469 .LBB7: + 216:Core/Src/stm32h7xx_hal_msp.c **** + 470 .loc 1 216 5 view .LVU118 + 216:Core/Src/stm32h7xx_hal_msp.c **** + 471 .loc 1 216 5 view .LVU119 + 472 0024 164B ldr r3, .L21 + 473 0026 D3F8F020 ldr r2, [r3, #240] + 474 002a 42F01002 orr r2, r2, #16 + 475 002e C3F8F020 str r2, [r3, #240] + 216:Core/Src/stm32h7xx_hal_msp.c **** + 476 .loc 1 216 5 view .LVU120 + 477 0032 D3F8F020 ldr r2, [r3, #240] + 478 0036 02F01002 and r2, r2, #16 + 479 003a 0192 str r2, [sp, #4] + 216:Core/Src/stm32h7xx_hal_msp.c **** + 480 .loc 1 216 5 view .LVU121 + 481 003c 019A ldr r2, [sp, #4] + 482 .LBE7: + 216:Core/Src/stm32h7xx_hal_msp.c **** + 483 .loc 1 216 5 view .LVU122 + 218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 484 .loc 1 218 5 view .LVU123 + 485 .LBB8: + ARM GAS /tmp/ccYeBZUP.s page 15 + + + 218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 486 .loc 1 218 5 view .LVU124 + 218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 487 .loc 1 218 5 view .LVU125 + 488 003e D3F8E020 ldr r2, [r3, #224] + 489 0042 42F00102 orr r2, r2, #1 + 490 0046 C3F8E020 str r2, [r3, #224] + 218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 491 .loc 1 218 5 view .LVU126 + 492 004a D3F8E030 ldr r3, [r3, #224] + 493 004e 03F00103 and r3, r3, #1 + 494 0052 0293 str r3, [sp, #8] + 218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 495 .loc 1 218 5 view .LVU127 + 496 0054 029B ldr r3, [sp, #8] + 497 .LBE8: + 218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 498 .loc 1 218 5 view .LVU128 + 223:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 499 .loc 1 223 5 view .LVU129 + 223:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 500 .loc 1 223 25 is_stmt 0 view .LVU130 + 501 0056 4FF4C063 mov r3, #1536 + 502 005a 0393 str r3, [sp, #12] + 224:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 503 .loc 1 224 5 is_stmt 1 view .LVU131 + 224:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 504 .loc 1 224 26 is_stmt 0 view .LVU132 + 505 005c 0223 movs r3, #2 + 506 005e 0493 str r3, [sp, #16] + 225:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 507 .loc 1 225 5 is_stmt 1 view .LVU133 + 226:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 508 .loc 1 226 5 view .LVU134 + 227:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 509 .loc 1 227 5 view .LVU135 + 227:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 510 .loc 1 227 31 is_stmt 0 view .LVU136 + 511 0060 0723 movs r3, #7 + 512 0062 0793 str r3, [sp, #28] + 228:Core/Src/stm32h7xx_hal_msp.c **** + 513 .loc 1 228 5 is_stmt 1 view .LVU137 + 514 0064 03A9 add r1, sp, #12 + 515 0066 0748 ldr r0, .L21+4 + 516 .LVL31: + 228:Core/Src/stm32h7xx_hal_msp.c **** + 517 .loc 1 228 5 is_stmt 0 view .LVU138 + 518 0068 FFF7FEFF bl HAL_GPIO_Init + 519 .LVL32: + 231:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USART1_IRQn); + 520 .loc 1 231 5 is_stmt 1 view .LVU139 + 521 006c 0022 movs r2, #0 + 522 006e 0121 movs r1, #1 + 523 0070 2520 movs r0, #37 + 524 0072 FFF7FEFF bl HAL_NVIC_SetPriority + 525 .LVL33: + 232:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 1 */ + ARM GAS /tmp/ccYeBZUP.s page 16 + + + 526 .loc 1 232 5 view .LVU140 + 527 0076 2520 movs r0, #37 + 528 0078 FFF7FEFF bl HAL_NVIC_EnableIRQ + 529 .LVL34: + 530 .loc 1 238 1 is_stmt 0 view .LVU141 + 531 007c CFE7 b .L17 + 532 .L22: + 533 007e 00BF .align 2 + 534 .L21: + 535 0080 00440258 .word 1476543488 + 536 0084 00000258 .word 1476526080 + 537 .cfi_endproc + 538 .LFE144: + 540 .section .text.HAL_UART_MspDeInit,"ax",%progbits + 541 .align 1 + 542 .global HAL_UART_MspDeInit + 543 .syntax unified + 544 .thumb + 545 .thumb_func + 546 .fpu fpv5-d16 + 548 HAL_UART_MspDeInit: + 549 .LVL35: + 550 .LFB145: + 239:Core/Src/stm32h7xx_hal_msp.c **** + 240:Core/Src/stm32h7xx_hal_msp.c **** /** + 241:Core/Src/stm32h7xx_hal_msp.c **** * @brief UART MSP De-Initialization + 242:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 243:Core/Src/stm32h7xx_hal_msp.c **** * @param huart: UART handle pointer + 244:Core/Src/stm32h7xx_hal_msp.c **** * @retval None + 245:Core/Src/stm32h7xx_hal_msp.c **** */ + 246:Core/Src/stm32h7xx_hal_msp.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) + 247:Core/Src/stm32h7xx_hal_msp.c **** { + 551 .loc 1 247 1 is_stmt 1 view -0 + 552 .cfi_startproc + 553 @ args = 0, pretend = 0, frame = 0 + 554 @ frame_needed = 0, uses_anonymous_args = 0 + 555 .loc 1 247 1 is_stmt 0 view .LVU143 + 556 0000 08B5 push {r3, lr} + 557 .LCFI12: + 558 .cfi_def_cfa_offset 8 + 559 .cfi_offset 3, -8 + 560 .cfi_offset 14, -4 + 248:Core/Src/stm32h7xx_hal_msp.c **** if(huart->Instance==USART1) + 561 .loc 1 248 3 is_stmt 1 view .LVU144 + 562 .loc 1 248 11 is_stmt 0 view .LVU145 + 563 0002 0268 ldr r2, [r0] + 564 .loc 1 248 5 view .LVU146 + 565 0004 094B ldr r3, .L27 + 566 0006 9A42 cmp r2, r3 + 567 0008 00D0 beq .L26 + 568 .LVL36: + 569 .L23: + 249:Core/Src/stm32h7xx_hal_msp.c **** { + 250:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 0 */ + 251:Core/Src/stm32h7xx_hal_msp.c **** + 252:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspDeInit 0 */ + 253:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */ + ARM GAS /tmp/ccYeBZUP.s page 17 + + + 254:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_USART1_CLK_DISABLE(); + 255:Core/Src/stm32h7xx_hal_msp.c **** + 256:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration + 257:Core/Src/stm32h7xx_hal_msp.c **** PA9 ------> USART1_TX + 258:Core/Src/stm32h7xx_hal_msp.c **** PA10 ------> USART1_RX + 259:Core/Src/stm32h7xx_hal_msp.c **** */ + 260:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + 261:Core/Src/stm32h7xx_hal_msp.c **** + 262:Core/Src/stm32h7xx_hal_msp.c **** /* USART1 interrupt DeInit */ + 263:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(USART1_IRQn); + 264:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */ + 265:Core/Src/stm32h7xx_hal_msp.c **** + 266:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspDeInit 1 */ + 267:Core/Src/stm32h7xx_hal_msp.c **** } + 268:Core/Src/stm32h7xx_hal_msp.c **** + 269:Core/Src/stm32h7xx_hal_msp.c **** } + 570 .loc 1 269 1 view .LVU147 + 571 000a 08BD pop {r3, pc} + 572 .LVL37: + 573 .L26: + 254:Core/Src/stm32h7xx_hal_msp.c **** + 574 .loc 1 254 5 is_stmt 1 view .LVU148 + 575 000c 084A ldr r2, .L27+4 + 576 000e D2F8F030 ldr r3, [r2, #240] + 577 0012 23F01003 bic r3, r3, #16 + 578 0016 C2F8F030 str r3, [r2, #240] + 260:Core/Src/stm32h7xx_hal_msp.c **** + 579 .loc 1 260 5 view .LVU149 + 580 001a 4FF4C061 mov r1, #1536 + 581 001e 0548 ldr r0, .L27+8 + 582 .LVL38: + 260:Core/Src/stm32h7xx_hal_msp.c **** + 583 .loc 1 260 5 is_stmt 0 view .LVU150 + 584 0020 FFF7FEFF bl HAL_GPIO_DeInit + 585 .LVL39: + 263:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */ + 586 .loc 1 263 5 is_stmt 1 view .LVU151 + 587 0024 2520 movs r0, #37 + 588 0026 FFF7FEFF bl HAL_NVIC_DisableIRQ + 589 .LVL40: + 590 .loc 1 269 1 is_stmt 0 view .LVU152 + 591 002a EEE7 b .L23 + 592 .L28: + 593 .align 2 + 594 .L27: + 595 002c 00100140 .word 1073811456 + 596 0030 00440258 .word 1476543488 + 597 0034 00000258 .word 1476526080 + 598 .cfi_endproc + 599 .LFE145: + 601 .text + 602 .Letext0: + 603 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 604 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 605 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 606 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 607 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + ARM GAS /tmp/ccYeBZUP.s page 18 + + + 608 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 609 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 610 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" + 611 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" + 612 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h" + ARM GAS /tmp/ccYeBZUP.s page 19 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_msp.c + /tmp/ccYeBZUP.s:17 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccYeBZUP.s:25 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccYeBZUP.s:114 .text.HAL_MspInit:0000000000000074 $d + /tmp/ccYeBZUP.s:119 .text.HAL_QSPI_MspInit:0000000000000000 $t + /tmp/ccYeBZUP.s:126 .text.HAL_QSPI_MspInit:0000000000000000 HAL_QSPI_MspInit + /tmp/ccYeBZUP.s:335 .text.HAL_QSPI_MspInit:00000000000000e8 $d + /tmp/ccYeBZUP.s:344 .text.HAL_QSPI_MspDeInit:0000000000000000 $t + /tmp/ccYeBZUP.s:351 .text.HAL_QSPI_MspDeInit:0000000000000000 HAL_QSPI_MspDeInit + /tmp/ccYeBZUP.s:408 .text.HAL_QSPI_MspDeInit:000000000000003c $d + /tmp/ccYeBZUP.s:417 .text.HAL_UART_MspInit:0000000000000000 $t + /tmp/ccYeBZUP.s:424 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit + /tmp/ccYeBZUP.s:535 .text.HAL_UART_MspInit:0000000000000080 $d + /tmp/ccYeBZUP.s:541 .text.HAL_UART_MspDeInit:0000000000000000 $t + /tmp/ccYeBZUP.s:548 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit + /tmp/ccYeBZUP.s:595 .text.HAL_UART_MspDeInit:000000000000002c $d + +UNDEFINED SYMBOLS +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +HAL_GPIO_Init +HAL_GPIO_DeInit +HAL_NVIC_DisableIRQ diff --git a/build/stm32h7xx_hal_msp.o b/build/stm32h7xx_hal_msp.o new file mode 100644 index 0000000..abd1507 Binary files /dev/null and b/build/stm32h7xx_hal_msp.o differ diff --git a/build/stm32h7xx_hal_pcd.d b/build/stm32h7xx_hal_pcd.d new file mode 100644 index 0000000..173cbfc --- /dev/null +++ b/build/stm32h7xx_hal_pcd.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_pcd.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_pcd.lst b/build/stm32h7xx_hal_pcd.lst new file mode 100644 index 0000000..ac0c89f --- /dev/null +++ b/build/stm32h7xx_hal_pcd.lst @@ -0,0 +1,6765 @@ +ARM GAS /tmp/ccjyOkyX.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_pcd.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.PCD_WriteEmptyTxFifo,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 PCD_WriteEmptyTxFifo: + 25 .LVL0: + 26 .LFB173: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @file stm32h7xx_hal_pcd.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief PCD HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * functionalities of the USB Peripheral Controller: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + IO operation functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + Peripheral Control functions + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + Peripheral State functions + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @verbatim + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ##### How to use this driver ##### + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ============================================================================== + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** [..] + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** The PCD HAL driver can be used as follows: + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (#) Declare a PCD_HandleTypeDef handle structure, for example: + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_HandleTypeDef hpcd; + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (#) Fill parameters of Init structure in HCD handle + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (##) Enable the PCD/USB Low Level interface clock using + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (##) Initialize the related GPIO clocks + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (##) Configure PCD pin-out + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (##) Configure PCD NVIC interrupt + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (#)Associate the Upper USB device stack to the HAL PCD Driver: + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (##) hpcd.pData = pdev; + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (#)Enable PCD transmission and reception: + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (##) HAL_PCD_Start(); + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @endverbatim + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ****************************************************************************** + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @attention + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** *

© Copyright (c) 2017 STMicroelectronics. + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * All rights reserved.

+ 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * This software component is licensed by ST under BSD 3-Clause license, + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * the "License"; You may not use this file except in compliance with the + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * License. You may obtain a copy of the License at: + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * opensource.org/licenses/BSD-3-Clause + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ****************************************************************************** + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Includes ------------------------------------------------------------------*/ + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #include "stm32h7xx_hal.h" + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @addtogroup STM32H7xx_HAL_Driver + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD PCD + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief PCD HAL module driver + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #ifdef HAL_PCD_MODULE_ENABLED + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Private types -------------------------------------------------------------*/ + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Private variables ---------------------------------------------------------*/ + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Private constants ---------------------------------------------------------*/ + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Private macros ------------------------------------------------------------*/ + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Private_Macros PCD Private Macros + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Private functions prototypes ----------------------------------------------*/ + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Private_Functions PCD Private Functions + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + ARM GAS /tmp/ccjyOkyX.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Exported functions --------------------------------------------------------*/ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions PCD Exported Functions + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Initialization and Configuration functions + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @verbatim + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ##### Initialization and de-initialization functions ##### + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** [..] This section provides functions allowing to: + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @endverbatim + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Initializes the PCD according to the specified + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * parameters in the PCD_InitTypeDef and initialize the associated handle. + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx; + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint8_t i; + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Check the PCD handle allocation */ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd == NULL) + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Check the parameters */ + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx = hpcd->Instance; + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_RESET) + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Allocate lock resource and initialize it */ + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->Lock = HAL_UNLOCKED; + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SOFCallback = HAL_PCD_SOFCallback; + ARM GAS /tmp/ccjyOkyX.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResetCallback = HAL_PCD_ResetCallback; + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->MspInitCallback == NULL) + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspInitCallback = HAL_PCD_MspInit; + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Init the low level hardware */ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspInitCallback(hpcd); + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_MspInit(hpcd); + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_BUSY; + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Disable DMA mode for FS instance */ + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((USBx->CID & (0x1U << 8)) == 0U) + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->Init.dma_enable = 0U; + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Disable the Interrupts */ + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /*Init the Core (common init.) */ + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_ERROR; + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Force Device Mode*/ + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Init endpoints structures */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Init ep structure */ + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].is_in = 1U; + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].num = i; + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].tx_fifo_num = i; + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Control until ep is activated */ + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].type = EP_TYPE_CTRL; + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].maxpacket = 0U; + ARM GAS /tmp/ccjyOkyX.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].xfer_buff = 0U; + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].xfer_len = 0U; + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].is_in = 0U; + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].num = i; + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Control until ep is activated */ + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].maxpacket = 0U; + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].xfer_buff = 0U; + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].xfer_len = 0U; + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Init Device */ + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_ERROR; + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = 0U; + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_READY; + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Activate LPM */ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->Init.lpm_enable == 1U) + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)HAL_PCDEx_ActivateLPM(hpcd); + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief DeInitializes the PCD peripheral. + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Check the PCD handle allocation */ + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd == NULL) + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_BUSY; + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Stop Device */ + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)HAL_PCD_Stop(hpcd); + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->MspDeInitCallback == NULL) + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* DeInit the low level hardware */ + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspDeInitCallback(hpcd); + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* DeInit the low level hardware: CLOCK, NVIC.*/ + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_MspDeInit(hpcd); + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_RESET; + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Initializes the PCD MSP. + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_MspInit could be implemented in the user file + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief DeInitializes PCD MSP. + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_MspDeInit could be implemented in the user file + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register a User USB PCD Callback + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak predefined callback + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd USB PCD handle + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param CallbackID ID of the callback to be registered + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * This parameter can be one of the following values: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + ARM GAS /tmp/ccjyOkyX.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the Callback function + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef Callb + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** switch (CallbackID) + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_SOF_CB_ID : + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SOFCallback = pCallback; + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_SETUPSTAGE_CB_ID : + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SetupStageCallback = pCallback; + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_RESET_CB_ID : + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResetCallback = pCallback; + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_SUSPEND_CB_ID : + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SuspendCallback = pCallback; + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_RESUME_CB_ID : + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResumeCallback = pCallback; + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_CONNECT_CB_ID : + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ConnectCallback = pCallback; + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_DISCONNECT_CB_ID : + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DisconnectCallback = pCallback; + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPINIT_CB_ID : + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspInitCallback = pCallback; + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPDEINIT_CB_ID : + ARM GAS /tmp/ccjyOkyX.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspDeInitCallback = pCallback; + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** default : + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else if (hpcd->State == HAL_PCD_STATE_RESET) + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** switch (CallbackID) + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPINIT_CB_ID : + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspInitCallback = pCallback; + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPDEINIT_CB_ID : + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspDeInitCallback = pCallback; + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** default : + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Unregister an USB PCD Callback + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB PCD callabck is redirected to the weak predefined callback + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd USB PCD handle + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param CallbackID ID of the callback to be unregistered + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * This parameter can be one of the following values: + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + ARM GAS /tmp/ccjyOkyX.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef Cal + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Setup Legacy weak Callbacks */ + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** switch (CallbackID) + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_SOF_CB_ID : + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SOFCallback = HAL_PCD_SOFCallback; + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_SETUPSTAGE_CB_ID : + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_RESET_CB_ID : + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResetCallback = HAL_PCD_ResetCallback; + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_SUSPEND_CB_ID : + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_RESUME_CB_ID : + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_CONNECT_CB_ID : + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_DISCONNECT_CB_ID : + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPINIT_CB_ID : + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspInitCallback = HAL_PCD_MspInit; + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPDEINIT_CB_ID : + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** default : + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + ARM GAS /tmp/ccjyOkyX.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else if (hpcd->State == HAL_PCD_STATE_RESET) + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** switch (CallbackID) + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPINIT_CB_ID : + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspInitCallback = HAL_PCD_MspInit; + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** case HAL_PCD_MSPDEINIT_CB_ID : + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** default : + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** break; + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register USB PCD Data OUT Stage Callback + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCa + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataOutStageCallback = pCallback; + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief UnRegister the USB PCD Data OUT Stage Callback + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback( + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register USB PCD Data IN Stage Callback + ARM GAS /tmp/ccjyOkyX.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the USB PCD Data IN Stage Callback function + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCall + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataInStageCallback = pCallback; + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief UnRegister the USB PCD Data IN Stage Callback + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + ARM GAS /tmp/ccjyOkyX.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register USB PCD Iso OUT incomplete Callback + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCa + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOOUTIncompleteCallback = pCallback; + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief UnRegister the USB PCD Iso OUT incomplete Callback + ARM GAS /tmp/ccjyOkyX.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteC + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompl + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register USB PCD Iso IN incomplete Callback + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCall + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOINIncompleteCallback = pCallback; + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + ARM GAS /tmp/ccjyOkyX.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief UnRegister the USB PCD Iso IN incomplete Callback + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCal + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncomplete + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register USB PCD BCD Callback + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the USB PCD BCD Callback function + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCal + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->BCDCallback = pCallback; + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief UnRegister the USB PCD BCD Callback + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + ARM GAS /tmp/ccjyOkyX.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Register USB PCD LPM Callback + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pCallback pointer to the USB PCD LPM Callback function + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCal + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (pCallback == NULL) + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPMCallback = pCallback; + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief UnRegister the USB PCD LPM Callback + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef status = HAL_OK; + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Process locked */ + ARM GAS /tmp/ccjyOkyX.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->State == HAL_PCD_STATE_READY) + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Update the error code */ + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Return error status */ + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** status = HAL_ERROR; + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Release Lock */ + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return status; + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Data transfers functions + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @verbatim + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ##### IO operation functions ##### + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** [..] + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** This subsection provides a set of functions allowing to manage the PCD data + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** transfers. + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @endverbatim + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Start the USB device + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((hpcd->Init.battery_charging_enable == 1U) && + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Enable USB Transceiver */ +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevConnect(hpcd->Instance); +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_ENABLE(hpcd); +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Stop the USB device. +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (USB_StopDevice(hpcd->Instance) != HAL_OK) +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Handles PCD interrupt request. +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t i, ep_intr, epint, epnum; +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t fifoemptymsk, temp; +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_EPTypeDef *ep; +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* ensure that we are in device mode */ +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* avoid spurious interrupt */ +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return; +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* incorrect mode, acknowledge the interrupt */ + ARM GAS /tmp/ccjyOkyX.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle RxQLevel Interrupt */ +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** temp = USBx->GRXSTSP; +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ReadPacket(USBx, ep->xfer_buff, +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* ... */ +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epnum = 0U; +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Read in the device interrupt bits */ +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** while (ep_intr != 0U) +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_intr & 0x1U) != 0U) +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + ARM GAS /tmp/ccjyOkyX.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Class B setup phase done for previous decoded setup */ +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Clear Status Phase Received interrupt */ +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Clear OUT NAK interrupt */ +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epnum++; +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr >>= 1U; +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Read in the device interrupt bits */ +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epnum = 0U; +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** while (ep_intr != 0U) +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_intr & 0x1U) != 0U) /* In ITR */ +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->Init.dma_enable == 1U) +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* this is ZLP, so prepare EP0 for next setup */ +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* prepare to rx more setup packets */ +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)PCD_WriteEmptyTxFifo(hpcd, epnum); +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epnum++; +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr >>= 1U; +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Resume Interrupt */ +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Clear the Remote Wake-up Signaling */ +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->LPM_State == LPM_L1) +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPM_State = LPM_L0; +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResumeCallback(hpcd); +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_ResumeCallback(hpcd); +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Suspend Interrupt */ +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SuspendCallback(hpcd); +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_SuspendCallback(hpcd); +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle LPM Interrupt */ +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->LPM_State == LPM_L0) +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPM_State = LPM_L1; +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SuspendCallback(hpcd); +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_SuspendCallback(hpcd); +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Reset Interrupt */ +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** for (i = 0U; i < hpcd->Init.dev_endpoints; i++) +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPINT = 0xFB7FU; +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + ARM GAS /tmp/ccjyOkyX.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DAINTMSK |= 0x10001U; +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->Init.use_dedicated_ep1 != 0U) +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_XFRCM | +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_EPDM; +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_XFRCM | +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_EPDM; +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_XFRCM | +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_EPDM | +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_OTEPSPRM | +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_NAKM; +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_XFRCM | +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_EPDM; +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Set Default Address to 0 */ +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* setup EP0 to receive SETUP packets */ +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint8_t *)hpcd->Setup); +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Enumeration done Interrupt */ +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateSetup(hpcd->Instance); +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Set USB Turnaround time */ +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_SetTurnaroundTime(hpcd->Instance, +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_RCC_GetHCLKFreq(), +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint8_t)hpcd->Init.speed); +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ResetCallback(hpcd); +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_ResetCallback(hpcd); +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle SOF Interrupt */ +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SOFCallback(hpcd); +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_SOFCallback(hpcd); +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Incomplete ISO IN Interrupt */ +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Keep application checking the corresponding Iso IN endpoint +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** causing the incomplete Interrupt */ +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epnum = 0U; +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Incomplete ISO OUT Interrupt */ +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Keep application checking the corresponding Iso OUT endpoint +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** causing the incomplete Interrupt */ +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** epnum = 0U; +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Connection event Interrupt */ +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->ConnectCallback(hpcd); +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_ConnectCallback(hpcd); +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Handle Disconnection event Interrupt */ + ARM GAS /tmp/ccjyOkyX.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** temp = hpcd->Instance->GOTGINT; +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DisconnectCallback(hpcd); +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_DisconnectCallback(hpcd); +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->Instance->GOTGINT |= temp; +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Data OUT stage callback. +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_DataOutStageCallback could be implemented in the user file +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Data IN stage callback +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_DataInStageCallback could be implemented in the user file +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Setup stage callback +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ + ARM GAS /tmp/ccjyOkyX.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_SetupStageCallback could be implemented in the user file +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief USB Start Of Frame callback. +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_SOFCallback could be implemented in the user file +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief USB Reset callback. +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_ResetCallback could be implemented in the user file +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Suspend event callback. +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_SuspendCallback could be implemented in the user file +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Resume event callback. + ARM GAS /tmp/ccjyOkyX.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_ResumeCallback could be implemented in the user file +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Incomplete ISO OUT callback. +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Incomplete ISO IN callback. +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Connection event callback. +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_ConnectCallback could be implemented in the user file +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Disconnection event callback. +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval None +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(hpcd); +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** the HAL_PCD_DisconnectCallback could be implemented in the user file +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief management functions +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @verbatim +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ##### Peripheral Control functions ##### +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** [..] +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** This subsection provides a set of functions allowing to control the PCD data +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** transfers. +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @endverbatim +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Connect the USB device +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((hpcd->Init.battery_charging_enable == 1U) && +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Enable USB Transceiver */ +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + ARM GAS /tmp/ccjyOkyX.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevConnect(hpcd->Instance); +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Disconnect the USB device. +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Set the USB Device address. +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param address new device address +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = address; +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_SetDevAddress(hpcd->Instance, address); +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Open and configure an endpoint. +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_mps endpoint max packet size +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_type endpoint type +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_ +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef ret = HAL_OK; +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & 0x80U) == 0x80U) +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->maxpacket = ep_mps; +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->type = ep_type; +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (ep->is_in != 0U) +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Assign a Tx FIFO */ +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->tx_fifo_num = ep->num; +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Set initial data PID. */ +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (ep_type == EP_TYPE_BULK) +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->data_pid_start = 0U; +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateEndpoint(hpcd->Instance, ep); +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return ret; +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Deactivate an endpoint. +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & 0x80U) == 0x80U) +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DeactivateEndpoint(hpcd->Instance, ep); +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Receive an amount of data. +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pBuf pointer to the reception buffer + ARM GAS /tmp/ccjyOkyX.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param len amount of data to be received +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint3 +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /*setup and start the Xfer */ +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_buff = pBuf; +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_len = len; +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count = 0U; +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->Init.dma_enable == 1U) +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->dma_addr = (uint32_t)pBuf; +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & EP_ADDR_MSK) == 0U) +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Get Received Data Size +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval Data Size +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Send an amount of data +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param pBuf pointer to the transmission buffer +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param len amount of data to be sent +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 33 + + +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /*setup and start the Xfer */ +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_buff = pBuf; +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_len = len; +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count = 0U; +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->Init.dma_enable == 1U) +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->dma_addr = (uint32_t)pBuf; +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & EP_ADDR_MSK) == 0U) +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Set a STALL condition over an endpoint +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((0x80U & ep_addr) == 0x80U) +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->OUT_ep[ep_addr]; +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_stall = 1U; +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPSetStall(hpcd->Instance, ep); +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & EP_ADDR_MSK) == 0U) + ARM GAS /tmp/ccjyOkyX.s page 34 + + +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Clear a STALL condition over in an endpoint +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((0x80U & ep_addr) == 0x80U) +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_stall = 0U; +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPClearStall(hpcd->Instance, ep); +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Flush an endpoint +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param ep_addr endpoint address +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & 0x80U) == 0x80U) +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + ARM GAS /tmp/ccjyOkyX.s page 35 + + +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_FlushRxFifo(hpcd->Instance); +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Activate remote wakeup signalling +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return (USB_ActivateRemoteWakeup(hpcd->Instance)); +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief De-activate remote wakeup signalling. +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Peripheral State functions +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @verbatim +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ##### Peripheral State functions ##### +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** =============================================================================== +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** [..] +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** This subsection permits to get in run-time the status of the peripheral +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** and the data flow. +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** @endverbatim +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Return the PCD handle state. +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL state +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 36 + + +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return hpcd->State; +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @} +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Private functions ---------------------------------------------------------*/ +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** @addtogroup PCD_Private_Functions +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @{ +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief Check FIFO for the next packet to be loaded. +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 28 .loc 1 1993 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 1993 1 is_stmt 0 view .LVU1 + 33 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 28 + 36 .cfi_offset 4, -28 + 37 .cfi_offset 5, -24 + 38 .cfi_offset 6, -20 + 39 .cfi_offset 7, -16 + 40 .cfi_offset 8, -12 + 41 .cfi_offset 9, -8 + 42 .cfi_offset 14, -4 + 43 0004 83B0 sub sp, sp, #12 + 44 .LCFI1: + 45 .cfi_def_cfa_offset 40 +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 46 .loc 1 1994 3 is_stmt 1 view .LVU2 + 47 .loc 1 1994 26 is_stmt 0 view .LVU3 + 48 0006 D0F80080 ldr r8, [r0] + 49 .LVL1: +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 50 .loc 1 1995 3 is_stmt 1 view .LVU4 +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_EPTypeDef *ep; + 51 .loc 1 1996 3 view .LVU5 +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t len; + 52 .loc 1 1997 3 view .LVU6 +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t len32b; + 53 .loc 1 1998 3 view .LVU7 +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t fifoemptymsk; + 54 .loc 1 1999 3 view .LVU8 + ARM GAS /tmp/ccjyOkyX.s page 37 + + +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep = &hpcd->IN_ep[epnum]; + 55 .loc 1 2001 3 view .LVU9 +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (ep->xfer_count > ep->xfer_len) + 56 .loc 1 2003 3 view .LVU10 + 57 .loc 1 2003 9 is_stmt 0 view .LVU11 + 58 000a C1EBC103 rsb r3, r1, r1, lsl #3 + 59 000e 00EB8303 add r3, r0, r3, lsl #2 + 60 0012 5A6D ldr r2, [r3, #84] + 61 .loc 1 2003 26 view .LVU12 + 62 0014 1B6D ldr r3, [r3, #80] + 63 .loc 1 2003 6 view .LVU13 + 64 0016 9A42 cmp r2, r3 + 65 0018 54D8 bhi .L8 + 66 001a 0746 mov r7, r0 + 67 001c 0C46 mov r4, r1 +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** len = ep->xfer_len - ep->xfer_count; + 68 .loc 1 2008 3 is_stmt 1 view .LVU14 + 69 .loc 1 2008 7 is_stmt 0 view .LVU15 + 70 001e 9B1A subs r3, r3, r2 + 71 .LVL2: +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (len > ep->maxpacket) + 72 .loc 1 2010 3 is_stmt 1 view .LVU16 + 73 .loc 1 2010 15 is_stmt 0 view .LVU17 + 74 0020 C1EBC102 rsb r2, r1, r1, lsl #3 + 75 0024 00EB8202 add r2, r0, r2, lsl #2 + 76 0028 526C ldr r2, [r2, #68] + 77 .loc 1 2010 6 view .LVU18 + 78 002a 9A42 cmp r2, r3 + 79 002c 00D3 bcc .L3 +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 80 .loc 1 2008 7 view .LVU19 + 81 002e 1A46 mov r2, r3 + 82 .L3: + 83 .LVL3: +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** len = ep->maxpacket; +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** len32b = (len + 3U) / 4U; + 84 .loc 1 2015 3 is_stmt 1 view .LVU20 + 85 .loc 1 2015 17 is_stmt 0 view .LVU21 + 86 0030 02F10309 add r9, r2, #3 + 87 .loc 1 2015 10 view .LVU22 + 88 0034 4FEA9909 lsr r9, r9, #2 + 89 .LVL4: +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + 90 .loc 1 2017 3 is_stmt 1 view .LVU23 + 91 .loc 1 2017 9 is_stmt 0 view .LVU24 + 92 0038 15E0 b .L4 + ARM GAS /tmp/ccjyOkyX.s page 38 + + + 93 .LVL5: + 94 .L5: +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Write the FIFO */ +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** len = ep->xfer_len - ep->xfer_count; +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (len > ep->maxpacket) +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** len = ep->maxpacket; +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** len32b = (len + 3U) / 4U; + 95 .loc 1 2027 5 is_stmt 1 view .LVU25 + 96 .loc 1 2027 19 is_stmt 0 view .LVU26 + 97 003a 06F10309 add r9, r6, #3 + 98 .LVL6: + 99 .loc 1 2027 12 view .LVU27 + 100 003e 4FEA9909 lsr r9, r9, #2 + 101 .LVL7: +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + 102 .loc 1 2029 5 is_stmt 1 view .LVU28 + 103 .loc 1 2029 11 is_stmt 0 view .LVU29 + 104 0042 C4EBC405 rsb r5, r4, r4, lsl #3 + 105 0046 07EB8505 add r5, r7, r5, lsl #2 + 106 004a A96C ldr r1, [r5, #72] + 107 004c 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 108 004e 0093 str r3, [sp] + 109 0050 B3B2 uxth r3, r6 + 110 0052 E2B2 uxtb r2, r4 + 111 0054 4046 mov r0, r8 + 112 0056 FFF7FEFF bl USB_WritePacket + 113 .LVL8: +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint8_t)hpcd->Init.dma_enable); +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_buff += len; + 114 .loc 1 2032 5 is_stmt 1 view .LVU30 + 115 .loc 1 2032 20 is_stmt 0 view .LVU31 + 116 005a AB6C ldr r3, [r5, #72] + 117 005c 3344 add r3, r3, r6 + 118 005e AB64 str r3, [r5, #72] +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += len; + 119 .loc 1 2033 5 is_stmt 1 view .LVU32 + 120 .loc 1 2033 20 is_stmt 0 view .LVU33 + 121 0060 6B6D ldr r3, [r5, #84] + 122 0062 3344 add r3, r3, r6 + 123 0064 6B65 str r3, [r5, #84] + 124 .LVL9: + 125 .L4: +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + 126 .loc 1 2017 9 is_stmt 1 view .LVU34 +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + 127 .loc 1 2017 12 is_stmt 0 view .LVU35 + 128 0066 08EB4413 add r3, r8, r4, lsl #5 + 129 006a 03F51063 add r3, r3, #2304 +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + 130 .loc 1 2017 28 view .LVU36 + ARM GAS /tmp/ccjyOkyX.s page 39 + + + 131 006e 9B69 ldr r3, [r3, #24] +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + 132 .loc 1 2017 38 view .LVU37 + 133 0070 9BB2 uxth r3, r3 +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + 134 .loc 1 2017 9 view .LVU38 + 135 0072 4B45 cmp r3, r9 + 136 0074 12D3 bcc .L6 +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 137 .loc 1 2018 13 discriminator 1 view .LVU39 + 138 0076 C4EBC402 rsb r2, r4, r4, lsl #3 + 139 007a 07EB8202 add r2, r7, r2, lsl #2 + 140 007e 516D ldr r1, [r2, #84] +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 141 .loc 1 2018 30 discriminator 1 view .LVU40 + 142 0080 136D ldr r3, [r2, #80] +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + 143 .loc 1 2017 78 discriminator 1 view .LVU41 + 144 0082 9942 cmp r1, r3 + 145 0084 0AD2 bcs .L6 +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 146 .loc 1 2018 42 view .LVU42 + 147 0086 4BB1 cbz r3, .L6 +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 148 .loc 1 2021 5 is_stmt 1 view .LVU43 +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 149 .loc 1 2021 9 is_stmt 0 view .LVU44 + 150 0088 5B1A subs r3, r3, r1 + 151 .LVL10: +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 152 .loc 1 2023 5 is_stmt 1 view .LVU45 +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 153 .loc 1 2023 17 is_stmt 0 view .LVU46 + 154 008a C4EBC402 rsb r2, r4, r4, lsl #3 + 155 008e 07EB8202 add r2, r7, r2, lsl #2 + 156 0092 566C ldr r6, [r2, #68] +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 157 .loc 1 2023 8 view .LVU47 + 158 0094 9E42 cmp r6, r3 + 159 0096 D0D3 bcc .L5 +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 160 .loc 1 2021 9 view .LVU48 + 161 0098 1E46 mov r6, r3 + 162 009a CEE7 b .L5 + 163 .LVL11: + 164 .L6: +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (ep->xfer_len <= ep->xfer_count) + 165 .loc 1 2036 3 is_stmt 1 view .LVU49 + 166 .loc 1 2036 9 is_stmt 0 view .LVU50 + 167 009c C4EBC400 rsb r0, r4, r4, lsl #3 + 168 00a0 07EB8007 add r7, r7, r0, lsl #2 + 169 .LVL12: + 170 .loc 1 2036 9 view .LVU51 + 171 00a4 3A6D ldr r2, [r7, #80] + 172 .loc 1 2036 25 view .LVU52 + ARM GAS /tmp/ccjyOkyX.s page 40 + + + 173 00a6 7B6D ldr r3, [r7, #84] + 174 .loc 1 2036 6 view .LVU53 + 175 00a8 9A42 cmp r2, r3 + 176 00aa 0FD8 bhi .L9 +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + 177 .loc 1 2038 5 is_stmt 1 view .LVU54 + 178 .loc 1 2038 47 is_stmt 0 view .LVU55 + 179 00ac 04F00F04 and r4, r4, #15 + 180 .LVL13: + 181 .loc 1 2038 18 view .LVU56 + 182 00b0 0123 movs r3, #1 + 183 00b2 A340 lsls r3, r3, r4 + 184 .LVL14: +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 185 .loc 1 2039 5 is_stmt 1 view .LVU57 + 186 .loc 1 2039 29 is_stmt 0 view .LVU58 + 187 00b4 D8F83448 ldr r4, [r8, #2100] + 188 00b8 24EA0304 bic r4, r4, r3 + 189 00bc C8F83448 str r4, [r8, #2100] +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 190 .loc 1 2042 10 view .LVU59 + 191 00c0 0020 movs r0, #0 + 192 00c2 00E0 b .L2 + 193 .LVL15: + 194 .L8: +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 195 .loc 1 2005 12 view .LVU60 + 196 00c4 0120 movs r0, #1 + 197 .LVL16: + 198 .L2: +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 199 .loc 1 2043 1 view .LVU61 + 200 00c6 03B0 add sp, sp, #12 + 201 .LCFI2: + 202 .cfi_remember_state + 203 .cfi_def_cfa_offset 28 + 204 @ sp needed + 205 00c8 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 206 .LVL17: + 207 .L9: + 208 .LCFI3: + 209 .cfi_restore_state +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 210 .loc 1 2042 10 view .LVU62 + 211 00cc 0020 movs r0, #0 + 212 00ce FAE7 b .L2 + 213 .cfi_endproc + 214 .LFE173: + 216 .section .text.HAL_PCD_MspInit,"ax",%progbits + 217 .align 1 + 218 .weak HAL_PCD_MspInit + 219 .syntax unified + 220 .thumb + 221 .thumb_func + ARM GAS /tmp/ccjyOkyX.s page 41 + + + 222 .fpu fpv5-d16 + 224 HAL_PCD_MspInit: + 225 .LVL18: + 226 .LFB143: + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 227 .loc 1 281 1 is_stmt 1 view -0 + 228 .cfi_startproc + 229 @ args = 0, pretend = 0, frame = 0 + 230 @ frame_needed = 0, uses_anonymous_args = 0 + 231 @ link register save eliminated. + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 232 .loc 1 283 3 view .LVU64 + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 233 .loc 1 288 1 is_stmt 0 view .LVU65 + 234 0000 7047 bx lr + 235 .cfi_endproc + 236 .LFE143: + 238 .section .text.HAL_PCD_Init,"ax",%progbits + 239 .align 1 + 240 .global HAL_PCD_Init + 241 .syntax unified + 242 .thumb + 243 .thumb_func + 244 .fpu fpv5-d16 + 246 HAL_PCD_Init: + 247 .LVL19: + 248 .LFB141: + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx; + 249 .loc 1 124 1 is_stmt 1 view -0 + 250 .cfi_startproc + 251 @ args = 0, pretend = 0, frame = 0 + 252 @ frame_needed = 0, uses_anonymous_args = 0 + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx; + 253 .loc 1 124 1 is_stmt 0 view .LVU67 + 254 0000 70B5 push {r4, r5, r6, lr} + 255 .LCFI4: + 256 .cfi_def_cfa_offset 16 + 257 .cfi_offset 4, -16 + 258 .cfi_offset 5, -12 + 259 .cfi_offset 6, -8 + 260 .cfi_offset 14, -4 + 261 0002 8AB0 sub sp, sp, #40 + 262 .LCFI5: + 263 .cfi_def_cfa_offset 56 + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint8_t i; + 264 .loc 1 125 3 is_stmt 1 view .LVU68 + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 265 .loc 1 126 3 view .LVU69 + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 266 .loc 1 129 3 view .LVU70 + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 267 .loc 1 129 6 is_stmt 0 view .LVU71 + 268 0004 0028 cmp r0, #0 + 269 0006 00F09780 beq .L23 + 270 000a 0546 mov r5, r0 + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 271 .loc 1 135 3 is_stmt 1 view .LVU72 + ARM GAS /tmp/ccjyOkyX.s page 42 + + + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 272 .loc 1 137 3 view .LVU73 + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 273 .loc 1 137 8 is_stmt 0 view .LVU74 + 274 000c 0468 ldr r4, [r0] + 275 .LVL20: + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 276 .loc 1 139 3 is_stmt 1 view .LVU75 + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 277 .loc 1 139 11 is_stmt 0 view .LVU76 + 278 000e 90F8BD33 ldrb r3, [r0, #957] @ zero_extendqisi2 + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 279 .loc 1 139 6 view .LVU77 + 280 0012 3BB3 cbz r3, .L25 + 281 .LVL21: + 282 .L14: + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 283 .loc 1 172 3 is_stmt 1 view .LVU78 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 284 .loc 1 172 15 is_stmt 0 view .LVU79 + 285 0014 0323 movs r3, #3 + 286 0016 85F8BD33 strb r3, [r5, #957] + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 287 .loc 1 175 3 is_stmt 1 view .LVU80 + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 288 .loc 1 175 12 is_stmt 0 view .LVU81 + 289 001a E36B ldr r3, [r4, #60] + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 290 .loc 1 175 6 view .LVU82 + 291 001c 13F4807F tst r3, #256 + 292 0020 01D1 bne .L15 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 293 .loc 1 177 5 is_stmt 1 view .LVU83 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 294 .loc 1 177 27 is_stmt 0 view .LVU84 + 295 0022 0023 movs r3, #0 + 296 0024 2B61 str r3, [r5, #16] + 297 .L15: + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 298 .loc 1 181 3 is_stmt 1 view .LVU85 + 299 0026 2868 ldr r0, [r5] + 300 0028 FFF7FEFF bl USB_DisableGlobalInt + 301 .LVL22: + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 302 .loc 1 184 3 view .LVU86 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 303 .loc 1 184 24 is_stmt 0 view .LVU87 + 304 002c 2C46 mov r4, r5 + 305 .LVL23: + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 306 .loc 1 184 24 view .LVU88 + 307 002e 54F8106B ldr r6, [r4], #16 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 308 .loc 1 184 7 view .LVU89 + 309 0032 EC46 mov ip, sp + 310 0034 0FCC ldmia r4!, {r0, r1, r2, r3} + 311 0036 ACE80F00 stmia ip!, {r0, r1, r2, r3} + ARM GAS /tmp/ccjyOkyX.s page 43 + + + 312 003a 0FCC ldmia r4!, {r0, r1, r2, r3} + 313 003c ACE80F00 stmia ip!, {r0, r1, r2, r3} + 314 0040 94E80300 ldm r4, {r0, r1} + 315 0044 8CE80300 stm ip, {r0, r1} + 316 0048 2B1D adds r3, r5, #4 + 317 004a 0ECB ldm r3, {r1, r2, r3} + 318 004c 3046 mov r0, r6 + 319 004e FFF7FEFF bl USB_CoreInit + 320 .LVL24: + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 321 .loc 1 184 6 view .LVU90 + 322 0052 0446 mov r4, r0 + 323 0054 58B1 cbz r0, .L16 + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 324 .loc 1 186 5 is_stmt 1 view .LVU91 + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 325 .loc 1 186 17 is_stmt 0 view .LVU92 + 326 0056 0223 movs r3, #2 + 327 0058 85F8BD33 strb r3, [r5, #957] + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 328 .loc 1 187 5 is_stmt 1 view .LVU93 + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 329 .loc 1 187 12 is_stmt 0 view .LVU94 + 330 005c 0124 movs r4, #1 + 331 .LVL25: + 332 .L13: + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 333 .loc 1 237 1 view .LVU95 + 334 005e 2046 mov r0, r4 + 335 0060 0AB0 add sp, sp, #40 + 336 .LCFI6: + 337 .cfi_remember_state + 338 .cfi_def_cfa_offset 16 + 339 @ sp needed + 340 0062 70BD pop {r4, r5, r6, pc} + 341 .LVL26: + 342 .L25: + 343 .LCFI7: + 344 .cfi_restore_state + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 345 .loc 1 142 5 is_stmt 1 view .LVU96 + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 346 .loc 1 142 16 is_stmt 0 view .LVU97 + 347 0064 80F8BC33 strb r3, [r0, #956] + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + 348 .loc 1 168 5 is_stmt 1 view .LVU98 + 349 0068 FFF7FEFF bl HAL_PCD_MspInit + 350 .LVL27: + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + 351 .loc 1 168 5 is_stmt 0 view .LVU99 + 352 006c D2E7 b .L14 + 353 .LVL28: + 354 .L16: + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 355 .loc 1 191 3 is_stmt 1 view .LVU100 + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 356 .loc 1 191 9 is_stmt 0 view .LVU101 + ARM GAS /tmp/ccjyOkyX.s page 44 + + + 357 006e 0021 movs r1, #0 + 358 0070 2868 ldr r0, [r5] + 359 0072 FFF7FEFF bl USB_SetCurrentMode + 360 .LVL29: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 361 .loc 1 194 3 is_stmt 1 view .LVU102 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 362 .loc 1 194 10 is_stmt 0 view .LVU103 + 363 0076 2346 mov r3, r4 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 364 .loc 1 194 3 view .LVU104 + 365 0078 16E0 b .L17 + 366 .LVL30: + 367 .L18: + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].num = i; + 368 .loc 1 197 5 is_stmt 1 discriminator 3 view .LVU105 + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].num = i; + 369 .loc 1 197 26 is_stmt 0 discriminator 3 view .LVU106 + 370 007a C3EBC302 rsb r2, r3, r3, lsl #3 + 371 007e 05EB8202 add r2, r5, r2, lsl #2 + 372 0082 0121 movs r1, #1 + 373 0084 82F83D10 strb r1, [r2, #61] + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].tx_fifo_num = i; + 374 .loc 1 198 5 is_stmt 1 discriminator 3 view .LVU107 + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].tx_fifo_num = i; + 375 .loc 1 198 24 is_stmt 0 discriminator 3 view .LVU108 + 376 0088 82F83C30 strb r3, [r2, #60] + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Control until ep is activated */ + 377 .loc 1 199 5 is_stmt 1 discriminator 3 view .LVU109 + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Control until ep is activated */ + 378 .loc 1 199 32 is_stmt 0 discriminator 3 view .LVU110 + 379 008c A2F84230 strh r3, [r2, #66] @ movhi + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].maxpacket = 0U; + 380 .loc 1 201 5 is_stmt 1 discriminator 3 view .LVU111 + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].maxpacket = 0U; + 381 .loc 1 201 25 is_stmt 0 discriminator 3 view .LVU112 + 382 0090 0021 movs r1, #0 + 383 0092 82F83F10 strb r1, [r2, #63] + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].xfer_buff = 0U; + 384 .loc 1 202 5 is_stmt 1 discriminator 3 view .LVU113 + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].xfer_buff = 0U; + 385 .loc 1 202 30 is_stmt 0 discriminator 3 view .LVU114 + 386 0096 5164 str r1, [r2, #68] + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].xfer_len = 0U; + 387 .loc 1 203 5 is_stmt 1 discriminator 3 view .LVU115 + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->IN_ep[i].xfer_len = 0U; + 388 .loc 1 203 30 is_stmt 0 discriminator 3 view .LVU116 + 389 0098 9164 str r1, [r2, #72] + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 390 .loc 1 204 5 is_stmt 1 discriminator 3 view .LVU117 + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 391 .loc 1 204 29 is_stmt 0 discriminator 3 view .LVU118 + 392 009a C3EBC302 rsb r2, r3, r3, lsl #3 + 393 009e 05EB8202 add r2, r5, r2, lsl #2 + 394 00a2 1165 str r1, [r2, #80] + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 395 .loc 1 194 46 is_stmt 1 discriminator 3 view .LVU119 + ARM GAS /tmp/ccjyOkyX.s page 45 + + + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 396 .loc 1 194 47 is_stmt 0 discriminator 3 view .LVU120 + 397 00a4 0133 adds r3, r3, #1 + 398 .LVL31: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 399 .loc 1 194 47 discriminator 3 view .LVU121 + 400 00a6 DBB2 uxtb r3, r3 + 401 .LVL32: + 402 .L17: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 403 .loc 1 194 16 is_stmt 1 discriminator 1 view .LVU122 + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 404 .loc 1 194 30 is_stmt 0 discriminator 1 view .LVU123 + 405 00a8 6968 ldr r1, [r5, #4] + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 406 .loc 1 194 3 discriminator 1 view .LVU124 + 407 00aa 8B42 cmp r3, r1 + 408 00ac E5D3 bcc .L18 + 409 00ae 16E0 b .L19 + 410 .LVL33: + 411 .L20: + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].num = i; + 412 .loc 1 209 5 is_stmt 1 discriminator 3 view .LVU125 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].num = i; + 413 .loc 1 209 27 is_stmt 0 discriminator 3 view .LVU126 + 414 00b0 C4EBC403 rsb r3, r4, r4, lsl #3 + 415 00b4 05EB8303 add r3, r5, r3, lsl #2 + 416 00b8 0022 movs r2, #0 + 417 00ba 83F8FD21 strb r2, [r3, #509] + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Control until ep is activated */ + 418 .loc 1 210 5 is_stmt 1 discriminator 3 view .LVU127 + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Control until ep is activated */ + 419 .loc 1 210 25 is_stmt 0 discriminator 3 view .LVU128 + 420 00be 83F8FC41 strb r4, [r3, #508] + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].maxpacket = 0U; + 421 .loc 1 212 5 is_stmt 1 discriminator 3 view .LVU129 + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].maxpacket = 0U; + 422 .loc 1 212 26 is_stmt 0 discriminator 3 view .LVU130 + 423 00c2 83F8FF21 strb r2, [r3, #511] + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].xfer_buff = 0U; + 424 .loc 1 213 5 is_stmt 1 discriminator 3 view .LVU131 + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].xfer_buff = 0U; + 425 .loc 1 213 31 is_stmt 0 discriminator 3 view .LVU132 + 426 00c6 C3F80422 str r2, [r3, #516] + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].xfer_len = 0U; + 427 .loc 1 214 5 is_stmt 1 discriminator 3 view .LVU133 + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[i].xfer_len = 0U; + 428 .loc 1 214 31 is_stmt 0 discriminator 3 view .LVU134 + 429 00ca C3F80822 str r2, [r3, #520] + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 430 .loc 1 215 5 is_stmt 1 discriminator 3 view .LVU135 + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 431 .loc 1 215 30 is_stmt 0 discriminator 3 view .LVU136 + 432 00ce C4EBC403 rsb r3, r4, r4, lsl #3 + 433 00d2 05EB8303 add r3, r5, r3, lsl #2 + 434 00d6 C3F81022 str r2, [r3, #528] + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 46 + + + 435 .loc 1 207 46 is_stmt 1 discriminator 3 view .LVU137 + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 436 .loc 1 207 47 is_stmt 0 discriminator 3 view .LVU138 + 437 00da 0134 adds r4, r4, #1 + 438 .LVL34: + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 439 .loc 1 207 47 discriminator 3 view .LVU139 + 440 00dc E4B2 uxtb r4, r4 + 441 .LVL35: + 442 .L19: + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 443 .loc 1 207 16 is_stmt 1 discriminator 1 view .LVU140 + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 444 .loc 1 207 3 is_stmt 0 discriminator 1 view .LVU141 + 445 00de A142 cmp r1, r4 + 446 00e0 E6D8 bhi .L20 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 447 .loc 1 219 3 is_stmt 1 view .LVU142 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 448 .loc 1 219 23 is_stmt 0 view .LVU143 + 449 00e2 2C46 mov r4, r5 + 450 .LVL36: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 451 .loc 1 219 23 view .LVU144 + 452 00e4 54F8106B ldr r6, [r4], #16 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 453 .loc 1 219 7 view .LVU145 + 454 00e8 EC46 mov ip, sp + 455 00ea 0FCC ldmia r4!, {r0, r1, r2, r3} + 456 00ec ACE80F00 stmia ip!, {r0, r1, r2, r3} + 457 00f0 0FCC ldmia r4!, {r0, r1, r2, r3} + 458 00f2 ACE80F00 stmia ip!, {r0, r1, r2, r3} + 459 00f6 94E80300 ldm r4, {r0, r1} + 460 00fa 8CE80300 stm ip, {r0, r1} + 461 00fe 2B1D adds r3, r5, #4 + 462 0100 0ECB ldm r3, {r1, r2, r3} + 463 0102 3046 mov r0, r6 + 464 0104 FFF7FEFF bl USB_DevInit + 465 .LVL37: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 466 .loc 1 219 6 view .LVU146 + 467 0108 0446 mov r4, r0 + 468 010a 60B9 cbnz r0, .L26 + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_READY; + 469 .loc 1 225 3 is_stmt 1 view .LVU147 + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->State = HAL_PCD_STATE_READY; + 470 .loc 1 225 21 is_stmt 0 view .LVU148 + 471 010c 0023 movs r3, #0 + 472 010e 85F83830 strb r3, [r5, #56] + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 473 .loc 1 226 3 is_stmt 1 view .LVU149 + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 474 .loc 1 226 15 is_stmt 0 view .LVU150 + 475 0112 0123 movs r3, #1 + 476 0114 85F8BD33 strb r3, [r5, #957] + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 477 .loc 1 229 3 is_stmt 1 view .LVU151 + ARM GAS /tmp/ccjyOkyX.s page 47 + + + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 478 .loc 1 229 17 is_stmt 0 view .LVU152 + 479 0118 6B6A ldr r3, [r5, #36] + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 480 .loc 1 229 6 view .LVU153 + 481 011a 012B cmp r3, #1 + 482 011c 08D0 beq .L27 + 483 .L22: + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 484 .loc 1 234 3 is_stmt 1 view .LVU154 + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 485 .loc 1 234 9 is_stmt 0 view .LVU155 + 486 011e 2868 ldr r0, [r5] + 487 0120 FFF7FEFF bl USB_DevDisconnect + 488 .LVL38: + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 489 .loc 1 236 3 is_stmt 1 view .LVU156 + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 490 .loc 1 236 10 is_stmt 0 view .LVU157 + 491 0124 9BE7 b .L13 + 492 .L26: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 493 .loc 1 221 5 is_stmt 1 view .LVU158 + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 494 .loc 1 221 17 is_stmt 0 view .LVU159 + 495 0126 0223 movs r3, #2 + 496 0128 85F8BD33 strb r3, [r5, #957] + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 497 .loc 1 222 5 is_stmt 1 view .LVU160 + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 498 .loc 1 222 12 is_stmt 0 view .LVU161 + 499 012c 0124 movs r4, #1 + 500 012e 96E7 b .L13 + 501 .L27: + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 502 .loc 1 231 5 is_stmt 1 view .LVU162 + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 503 .loc 1 231 11 is_stmt 0 view .LVU163 + 504 0130 2846 mov r0, r5 + 505 0132 FFF7FEFF bl HAL_PCDEx_ActivateLPM + 506 .LVL39: + 507 0136 F2E7 b .L22 + 508 .LVL40: + 509 .L23: + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 510 .loc 1 131 12 view .LVU164 + 511 0138 0124 movs r4, #1 + 512 013a 90E7 b .L13 + 513 .cfi_endproc + 514 .LFE141: + 516 .section .text.HAL_PCD_MspDeInit,"ax",%progbits + 517 .align 1 + 518 .weak HAL_PCD_MspDeInit + 519 .syntax unified + 520 .thumb + 521 .thumb_func + 522 .fpu fpv5-d16 + ARM GAS /tmp/ccjyOkyX.s page 48 + + + 524 HAL_PCD_MspDeInit: + 525 .LVL41: + 526 .LFB144: + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 527 .loc 1 296 1 is_stmt 1 view -0 + 528 .cfi_startproc + 529 @ args = 0, pretend = 0, frame = 0 + 530 @ frame_needed = 0, uses_anonymous_args = 0 + 531 @ link register save eliminated. + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 532 .loc 1 298 3 view .LVU166 + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 533 .loc 1 303 1 is_stmt 0 view .LVU167 + 534 0000 7047 bx lr + 535 .cfi_endproc + 536 .LFE144: + 538 .section .text.HAL_PCD_Start,"ax",%progbits + 539 .align 1 + 540 .global HAL_PCD_Start + 541 .syntax unified + 542 .thumb + 543 .thumb_func + 544 .fpu fpv5-d16 + 546 HAL_PCD_Start: + 547 .LVL42: + 548 .LFB145: + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 549 .loc 1 991 1 is_stmt 1 view -0 + 550 .cfi_startproc + 551 @ args = 0, pretend = 0, frame = 0 + 552 @ frame_needed = 0, uses_anonymous_args = 0 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 553 .loc 1 993 3 view .LVU169 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 554 .loc 1 993 26 is_stmt 0 view .LVU170 + 555 0000 0268 ldr r2, [r0] + 556 .LVL43: + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 557 .loc 1 996 3 is_stmt 1 view .LVU171 + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 558 .loc 1 996 3 view .LVU172 + 559 0002 90F8BC33 ldrb r3, [r0, #956] @ zero_extendqisi2 + 560 0006 012B cmp r3, #1 + 561 0008 19D0 beq .L32 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 562 .loc 1 991 1 is_stmt 0 discriminator 2 view .LVU173 + 563 000a 10B5 push {r4, lr} + 564 .LCFI8: + 565 .cfi_def_cfa_offset 8 + 566 .cfi_offset 4, -8 + 567 .cfi_offset 14, -4 + 568 000c 0446 mov r4, r0 + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 569 .loc 1 996 3 is_stmt 1 discriminator 2 view .LVU174 + 570 000e 0123 movs r3, #1 + 571 0010 80F8BC33 strb r3, [r0, #956] + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + ARM GAS /tmp/ccjyOkyX.s page 49 + + + 572 .loc 1 996 3 discriminator 2 view .LVU175 + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 573 .loc 1 998 3 discriminator 2 view .LVU176 + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 574 .loc 1 998 18 is_stmt 0 discriminator 2 view .LVU177 + 575 0014 836A ldr r3, [r0, #40] + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 576 .loc 1 998 6 discriminator 2 view .LVU178 + 577 0016 012B cmp r3, #1 + 578 0018 09D0 beq .L37 + 579 .L31: +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_ENABLE(hpcd); + 580 .loc 1 1005 3 is_stmt 1 view .LVU179 +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_ENABLE(hpcd); + 581 .loc 1 1005 9 is_stmt 0 view .LVU180 + 582 001a 2068 ldr r0, [r4] + 583 .LVL44: +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_ENABLE(hpcd); + 584 .loc 1 1005 9 view .LVU181 + 585 001c FFF7FEFF bl USB_DevConnect + 586 .LVL45: +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 587 .loc 1 1006 3 is_stmt 1 view .LVU182 + 588 0020 2068 ldr r0, [r4] + 589 0022 FFF7FEFF bl USB_EnableGlobalInt + 590 .LVL46: +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 591 .loc 1 1007 3 view .LVU183 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 592 .loc 1 1007 3 view .LVU184 + 593 0026 0020 movs r0, #0 + 594 0028 84F8BC03 strb r0, [r4, #956] +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 595 .loc 1 1007 3 view .LVU185 +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 596 .loc 1 1008 3 view .LVU186 +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 597 .loc 1 1009 1 is_stmt 0 view .LVU187 + 598 002c 10BD pop {r4, pc} + 599 .LVL47: + 600 .L37: + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 601 .loc 1 999 18 discriminator 1 view .LVU188 + 602 002e 8369 ldr r3, [r0, #24] + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 603 .loc 1 998 50 discriminator 1 view .LVU189 + 604 0030 012B cmp r3, #1 + 605 0032 F2D0 beq .L31 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 606 .loc 1 1002 5 is_stmt 1 view .LVU190 +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 607 .loc 1 1002 17 is_stmt 0 view .LVU191 + 608 0034 936B ldr r3, [r2, #56] + 609 0036 43F48033 orr r3, r3, #65536 + 610 003a 9363 str r3, [r2, #56] + 611 003c EDE7 b .L31 + 612 .L32: + ARM GAS /tmp/ccjyOkyX.s page 50 + + + 613 .LCFI9: + 614 .cfi_def_cfa_offset 0 + 615 .cfi_restore 4 + 616 .cfi_restore 14 + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 617 .loc 1 996 3 view .LVU192 + 618 003e 0220 movs r0, #2 + 619 .LVL48: +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 620 .loc 1 1009 1 view .LVU193 + 621 0040 7047 bx lr + 622 .cfi_endproc + 623 .LFE145: + 625 .section .text.HAL_PCD_Stop,"ax",%progbits + 626 .align 1 + 627 .global HAL_PCD_Stop + 628 .syntax unified + 629 .thumb + 630 .thumb_func + 631 .fpu fpv5-d16 + 633 HAL_PCD_Stop: + 634 .LVL49: + 635 .LFB146: +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 636 .loc 1 1017 1 is_stmt 1 view -0 + 637 .cfi_startproc + 638 @ args = 0, pretend = 0, frame = 0 + 639 @ frame_needed = 0, uses_anonymous_args = 0 +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 640 .loc 1 1017 1 is_stmt 0 view .LVU195 + 641 0000 38B5 push {r3, r4, r5, lr} + 642 .LCFI10: + 643 .cfi_def_cfa_offset 16 + 644 .cfi_offset 3, -16 + 645 .cfi_offset 4, -12 + 646 .cfi_offset 5, -8 + 647 .cfi_offset 14, -4 +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); + 648 .loc 1 1018 3 is_stmt 1 view .LVU196 +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); + 649 .loc 1 1018 3 view .LVU197 + 650 0002 90F8BC33 ldrb r3, [r0, #956] @ zero_extendqisi2 + 651 0006 012B cmp r3, #1 + 652 0008 18D0 beq .L41 + 653 000a 0446 mov r4, r0 +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); + 654 .loc 1 1018 3 discriminator 2 view .LVU198 + 655 000c 0123 movs r3, #1 + 656 000e 80F8BC33 strb r3, [r0, #956] +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); + 657 .loc 1 1018 3 discriminator 2 view .LVU199 +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 658 .loc 1 1019 3 discriminator 2 view .LVU200 + 659 0012 0068 ldr r0, [r0] + 660 .LVL50: +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 661 .loc 1 1019 3 is_stmt 0 discriminator 2 view .LVU201 + ARM GAS /tmp/ccjyOkyX.s page 51 + + + 662 0014 FFF7FEFF bl USB_DisableGlobalInt + 663 .LVL51: +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 664 .loc 1 1021 3 is_stmt 1 discriminator 2 view .LVU202 +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 665 .loc 1 1021 7 is_stmt 0 discriminator 2 view .LVU203 + 666 0018 2068 ldr r0, [r4] + 667 001a FFF7FEFF bl USB_StopDevice + 668 .LVL52: +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 669 .loc 1 1021 6 discriminator 2 view .LVU204 + 670 001e 0546 mov r5, r0 + 671 0020 28B1 cbz r0, .L40 +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 672 .loc 1 1023 5 is_stmt 1 view .LVU205 +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 673 .loc 1 1023 5 view .LVU206 + 674 0022 0023 movs r3, #0 + 675 0024 84F8BC33 strb r3, [r4, #956] +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_ERROR; + 676 .loc 1 1023 5 view .LVU207 +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 677 .loc 1 1024 5 view .LVU208 +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 678 .loc 1 1024 12 is_stmt 0 view .LVU209 + 679 0028 0125 movs r5, #1 + 680 .LVL53: + 681 .L39: +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 682 .loc 1 1031 1 view .LVU210 + 683 002a 2846 mov r0, r5 + 684 002c 38BD pop {r3, r4, r5, pc} + 685 .LVL54: + 686 .L40: +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 687 .loc 1 1027 3 is_stmt 1 view .LVU211 +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 688 .loc 1 1027 9 is_stmt 0 view .LVU212 + 689 002e 2068 ldr r0, [r4] + 690 0030 FFF7FEFF bl USB_DevDisconnect + 691 .LVL55: +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 692 .loc 1 1028 3 is_stmt 1 view .LVU213 +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 693 .loc 1 1028 3 view .LVU214 + 694 0034 0023 movs r3, #0 + 695 0036 84F8BC33 strb r3, [r4, #956] +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 696 .loc 1 1028 3 view .LVU215 +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 697 .loc 1 1030 3 view .LVU216 +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 698 .loc 1 1030 10 is_stmt 0 view .LVU217 + 699 003a F6E7 b .L39 + 700 .LVL56: + 701 .L41: +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_PCD_DISABLE(hpcd); + ARM GAS /tmp/ccjyOkyX.s page 52 + + + 702 .loc 1 1018 3 view .LVU218 + 703 003c 0225 movs r5, #2 + 704 003e F4E7 b .L39 + 705 .cfi_endproc + 706 .LFE146: + 708 .section .text.HAL_PCD_DeInit,"ax",%progbits + 709 .align 1 + 710 .global HAL_PCD_DeInit + 711 .syntax unified + 712 .thumb + 713 .thumb_func + 714 .fpu fpv5-d16 + 716 HAL_PCD_DeInit: + 717 .LVL57: + 718 .LFB142: + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Check the PCD handle allocation */ + 719 .loc 1 245 1 is_stmt 1 view -0 + 720 .cfi_startproc + 721 @ args = 0, pretend = 0, frame = 0 + 722 @ frame_needed = 0, uses_anonymous_args = 0 + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 723 .loc 1 247 3 view .LVU220 + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 724 .loc 1 247 6 is_stmt 0 view .LVU221 + 725 0000 68B1 cbz r0, .L45 + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Check the PCD handle allocation */ + 726 .loc 1 245 1 view .LVU222 + 727 0002 10B5 push {r4, lr} + 728 .LCFI11: + 729 .cfi_def_cfa_offset 8 + 730 .cfi_offset 4, -8 + 731 .cfi_offset 14, -4 + 732 0004 0446 mov r4, r0 + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 733 .loc 1 252 3 is_stmt 1 view .LVU223 + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 734 .loc 1 252 15 is_stmt 0 view .LVU224 + 735 0006 0323 movs r3, #3 + 736 0008 80F8BD33 strb r3, [r0, #957] + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 737 .loc 1 255 3 is_stmt 1 view .LVU225 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 738 .loc 1 255 9 is_stmt 0 view .LVU226 + 739 000c FFF7FEFF bl HAL_PCD_Stop + 740 .LVL58: + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 741 .loc 1 267 3 is_stmt 1 view .LVU227 + 742 0010 2046 mov r0, r4 + 743 0012 FFF7FEFF bl HAL_PCD_MspDeInit + 744 .LVL59: + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 745 .loc 1 270 3 view .LVU228 + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 746 .loc 1 270 15 is_stmt 0 view .LVU229 + 747 0016 0020 movs r0, #0 + 748 0018 84F8BD03 strb r0, [r4, #957] + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 53 + + + 749 .loc 1 272 3 is_stmt 1 view .LVU230 + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 750 .loc 1 273 1 is_stmt 0 view .LVU231 + 751 001c 10BD pop {r4, pc} + 752 .LVL60: + 753 .L45: + 754 .LCFI12: + 755 .cfi_def_cfa_offset 0 + 756 .cfi_restore 4 + 757 .cfi_restore 14 + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 758 .loc 1 249 12 view .LVU232 + 759 001e 0120 movs r0, #1 + 760 .LVL61: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 761 .loc 1 273 1 view .LVU233 + 762 0020 7047 bx lr + 763 .cfi_endproc + 764 .LFE142: + 766 .section .text.HAL_PCD_DataOutStageCallback,"ax",%progbits + 767 .align 1 + 768 .weak HAL_PCD_DataOutStageCallback + 769 .syntax unified + 770 .thumb + 771 .thumb_func + 772 .fpu fpv5-d16 + 774 HAL_PCD_DataOutStageCallback: + 775 .LVL62: + 776 .LFB148: +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 777 .loc 1 1426 1 is_stmt 1 view -0 + 778 .cfi_startproc + 779 @ args = 0, pretend = 0, frame = 0 + 780 @ frame_needed = 0, uses_anonymous_args = 0 + 781 @ link register save eliminated. +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); + 782 .loc 1 1428 3 view .LVU235 +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 783 .loc 1 1429 3 view .LVU236 +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 784 .loc 1 1434 1 is_stmt 0 view .LVU237 + 785 0000 7047 bx lr + 786 .cfi_endproc + 787 .LFE148: + 789 .section .text.PCD_EP_OutXfrComplete_int,"ax",%progbits + 790 .align 1 + 791 .syntax unified + 792 .thumb + 793 .thumb_func + 794 .fpu fpv5-d16 + 796 PCD_EP_OutXfrComplete_int: + 797 .LVL63: + 798 .LFB174: +2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief process EP OUT transfer complete interrupt. + ARM GAS /tmp/ccjyOkyX.s page 54 + + +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 799 .loc 1 2053 1 is_stmt 1 view -0 + 800 .cfi_startproc + 801 @ args = 0, pretend = 0, frame = 0 + 802 @ frame_needed = 0, uses_anonymous_args = 0 + 803 .loc 1 2053 1 is_stmt 0 view .LVU239 + 804 0000 70B5 push {r4, r5, r6, lr} + 805 .LCFI13: + 806 .cfi_def_cfa_offset 16 + 807 .cfi_offset 4, -16 + 808 .cfi_offset 5, -12 + 809 .cfi_offset 6, -8 + 810 .cfi_offset 14, -4 + 811 0002 0446 mov r4, r0 + 812 0004 0D46 mov r5, r1 +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 813 .loc 1 2054 3 is_stmt 1 view .LVU240 + 814 .loc 1 2054 26 is_stmt 0 view .LVU241 + 815 0006 0068 ldr r0, [r0] + 816 .LVL64: +2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 817 .loc 1 2055 3 is_stmt 1 view .LVU242 +2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + 818 .loc 1 2056 3 view .LVU243 + 819 .loc 1 2056 12 is_stmt 0 view .LVU244 + 820 0008 066C ldr r6, [r0, #64] + 821 .LVL65: +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + 822 .loc 1 2057 3 is_stmt 1 view .LVU245 + 823 .loc 1 2057 25 is_stmt 0 view .LVU246 + 824 000a 00EB4113 add r3, r0, r1, lsl #5 + 825 000e 03F53063 add r3, r3, #2816 + 826 .loc 1 2057 12 view .LVU247 + 827 0012 9A68 ldr r2, [r3, #8] + 828 .LVL66: +2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (hpcd->Init.dma_enable == 1U) + 829 .loc 1 2059 3 is_stmt 1 view .LVU248 + 830 .loc 1 2059 17 is_stmt 0 view .LVU249 + 831 0014 2169 ldr r1, [r4, #16] + 832 .LVL67: + 833 .loc 1 2059 6 view .LVU250 + 834 0016 0129 cmp r1, #1 + 835 0018 11D0 beq .L63 +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* StupPktRcvd = 1 this is a setup packet */ +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((gSNPSiD > USB_OTG_CORE_ID_300A) && +2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + ARM GAS /tmp/ccjyOkyX.s page 55 + + +2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ +2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); +2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* StupPktRcvd = 1 this is a setup packet */ +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((gSNPSiD > USB_OTG_CORE_ID_300A) && +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* out data packet received over EP0 */ +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[epnum].xfer_count = +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[epnum].maxpacket - +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* this is ZLP, so prepare EP0 for next setup */ +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* ... */ +2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if (gSNPSiD == USB_OTG_CORE_ID_310A) + 836 .loc 1 2110 5 is_stmt 1 view .LVU251 + 837 .loc 1 2110 8 is_stmt 0 view .LVU252 + 838 001a 3449 ldr r1, .L67 + 839 001c 8E42 cmp r6, r1 + 840 001e 4ED0 beq .L64 +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* StupPktRcvd = 1 this is a setup packet */ +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + ARM GAS /tmp/ccjyOkyX.s page 56 + + +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); +2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** else +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + 841 .loc 1 2133 7 is_stmt 1 view .LVU253 + 842 .loc 1 2133 10 is_stmt 0 view .LVU254 + 843 0020 3DB9 cbnz r5, .L61 + 844 .loc 1 2133 48 discriminator 1 view .LVU255 + 845 0022 C5EBC503 rsb r3, r5, r5, lsl #3 + 846 0026 04EB8303 add r3, r4, r3, lsl #2 + 847 002a D3F81032 ldr r3, [r3, #528] + 848 .loc 1 2133 25 discriminator 1 view .LVU256 + 849 002e 002B cmp r3, #0 + 850 0030 56D0 beq .L65 + 851 .LVL68: + 852 .L61: +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* this is ZLP, so prepare EP0 for next setup */ +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); +2137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +2141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); + 853 .loc 1 2142 7 is_stmt 1 view .LVU257 + 854 0032 E9B2 uxtb r1, r5 + 855 0034 2046 mov r0, r4 + 856 0036 FFF7FEFF bl HAL_PCD_DataOutStageCallback + 857 .LVL69: + 858 .L54: +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +2144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 859 .loc 1 2147 3 view .LVU258 +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 860 .loc 1 2148 1 is_stmt 0 view .LVU259 + 861 003a 0020 movs r0, #0 + 862 003c 70BD pop {r4, r5, r6, pc} + 863 .LVL70: + 864 .L63: +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 865 .loc 1 2061 5 is_stmt 1 view .LVU260 +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 866 .loc 1 2061 8 is_stmt 0 view .LVU261 + ARM GAS /tmp/ccjyOkyX.s page 57 + + + 867 003e 12F0080F tst r2, #8 + 868 0042 09D0 beq .L53 +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + 869 .loc 1 2064 7 is_stmt 1 view .LVU262 +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + 870 .loc 1 2064 10 is_stmt 0 view .LVU263 + 871 0044 2A49 ldr r1, .L67+4 + 872 0046 8E42 cmp r6, r1 + 873 0048 F7D9 bls .L54 +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + 874 .loc 1 2064 44 discriminator 1 view .LVU264 + 875 004a 12F4004F tst r2, #32768 + 876 004e F4D0 beq .L54 +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 877 .loc 1 2067 9 is_stmt 1 view .LVU265 + 878 0050 4FF40042 mov r2, #32768 + 879 .LVL71: +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 880 .loc 1 2067 9 is_stmt 0 view .LVU266 + 881 0054 9A60 str r2, [r3, #8] + 882 0056 F0E7 b .L54 + 883 .LVL72: + 884 .L53: +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 885 .loc 1 2070 10 is_stmt 1 view .LVU267 +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 886 .loc 1 2070 13 is_stmt 0 view .LVU268 + 887 0058 12F0200F tst r2, #32 + 888 005c 02D0 beq .L55 +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 889 .loc 1 2072 7 is_stmt 1 view .LVU269 + 890 005e 2022 movs r2, #32 + 891 .LVL73: +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 892 .loc 1 2072 7 is_stmt 0 view .LVU270 + 893 0060 9A60 str r2, [r3, #8] + 894 0062 EAE7 b .L54 + 895 .LVL74: + 896 .L55: +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 897 .loc 1 2074 10 is_stmt 1 view .LVU271 +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 898 .loc 1 2074 13 is_stmt 0 view .LVU272 + 899 0064 12F0280F tst r2, #40 + 900 0068 E7D1 bne .L54 +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + 901 .loc 1 2077 7 is_stmt 1 view .LVU273 +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + 902 .loc 1 2077 10 is_stmt 0 view .LVU274 + 903 006a 2149 ldr r1, .L67+4 + 904 006c 8E42 cmp r6, r1 + 905 006e 06D9 bls .L56 +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + 906 .loc 1 2077 44 discriminator 1 view .LVU275 + 907 0070 12F4004F tst r2, #32768 + 908 0074 03D0 beq .L56 +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 58 + + + 909 .loc 1 2080 9 is_stmt 1 view .LVU276 + 910 0076 4FF40042 mov r2, #32768 + 911 .LVL75: +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 912 .loc 1 2080 9 is_stmt 0 view .LVU277 + 913 007a 9A60 str r2, [r3, #8] + 914 007c DDE7 b .L54 + 915 .LVL76: + 916 .L56: +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[epnum].maxpacket - + 917 .loc 1 2085 9 is_stmt 1 view .LVU278 +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + 918 .loc 1 2086 30 is_stmt 0 view .LVU279 + 919 007e C5EBC502 rsb r2, r5, r5, lsl #3 + 920 .LVL77: +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + 921 .loc 1 2086 30 view .LVU280 + 922 0082 04EB8202 add r2, r4, r2, lsl #2 + 923 0086 D2F80412 ldr r1, [r2, #516] +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 924 .loc 1 2087 29 view .LVU281 + 925 008a 1B69 ldr r3, [r3, #16] +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 926 .loc 1 2087 40 view .LVU282 + 927 008c C3F31203 ubfx r3, r3, #0, #19 +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + 928 .loc 1 2086 41 view .LVU283 + 929 0090 CB1A subs r3, r1, r3 +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->OUT_ep[epnum].maxpacket - + 930 .loc 1 2085 40 view .LVU284 + 931 0092 C2F81432 str r3, [r2, #532] +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 932 .loc 1 2089 9 is_stmt 1 view .LVU285 +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 933 .loc 1 2089 39 is_stmt 0 view .LVU286 + 934 0096 D2F80832 ldr r3, [r2, #520] + 935 009a 0B44 add r3, r3, r1 + 936 009c C2F80832 str r3, [r2, #520] +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 937 .loc 1 2091 9 is_stmt 1 view .LVU287 +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 938 .loc 1 2091 12 is_stmt 0 view .LVU288 + 939 00a0 15B9 cbnz r5, .L57 +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 940 .loc 1 2091 50 discriminator 1 view .LVU289 + 941 00a2 D2F81032 ldr r3, [r2, #528] +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 942 .loc 1 2091 27 discriminator 1 view .LVU290 + 943 00a6 23B1 cbz r3, .L66 + 944 .LVL78: + 945 .L57: +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 946 .loc 1 2099 9 is_stmt 1 view .LVU291 + 947 00a8 E9B2 uxtb r1, r5 + 948 00aa 2046 mov r0, r4 + 949 00ac FFF7FEFF bl HAL_PCD_DataOutStageCallback + 950 .LVL79: + ARM GAS /tmp/ccjyOkyX.s page 59 + + + 951 00b0 C3E7 b .L54 + 952 .LVL80: + 953 .L66: +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 954 .loc 1 2094 11 view .LVU292 +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 955 .loc 1 2094 17 is_stmt 0 view .LVU293 + 956 00b2 04F57172 add r2, r4, #964 + 957 00b6 0121 movs r1, #1 + 958 00b8 FFF7FEFF bl USB_EP0_OutStart + 959 .LVL81: +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 960 .loc 1 2094 17 view .LVU294 + 961 00bc F4E7 b .L57 + 962 .LVL82: + 963 .L64: +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 964 .loc 1 2113 7 is_stmt 1 view .LVU295 +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 965 .loc 1 2113 10 is_stmt 0 view .LVU296 + 966 00be 12F4004F tst r2, #32768 + 967 00c2 03D0 beq .L59 +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 968 .loc 1 2115 9 is_stmt 1 view .LVU297 + 969 00c4 4FF40042 mov r2, #32768 + 970 .LVL83: +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 971 .loc 1 2115 9 is_stmt 0 view .LVU298 + 972 00c8 9A60 str r2, [r3, #8] + 973 00ca B6E7 b .L54 + 974 .LVL84: + 975 .L59: +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 976 .loc 1 2119 9 is_stmt 1 view .LVU299 +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 977 .loc 1 2119 12 is_stmt 0 view .LVU300 + 978 00cc 12F0200F tst r2, #32 + 979 00d0 01D0 beq .L60 +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 980 .loc 1 2121 11 is_stmt 1 view .LVU301 + 981 00d2 2022 movs r2, #32 + 982 .LVL85: +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 983 .loc 1 2121 11 is_stmt 0 view .LVU302 + 984 00d4 9A60 str r2, [r3, #8] + 985 .L60: +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 986 .loc 1 2127 9 is_stmt 1 view .LVU303 + 987 00d6 E9B2 uxtb r1, r5 + 988 00d8 2046 mov r0, r4 + 989 .LVL86: +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 990 .loc 1 2127 9 is_stmt 0 view .LVU304 + 991 00da FFF7FEFF bl HAL_PCD_DataOutStageCallback + 992 .LVL87: + 993 00de ACE7 b .L54 + 994 .LVL88: + ARM GAS /tmp/ccjyOkyX.s page 60 + + + 995 .L65: +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 996 .loc 1 2136 9 is_stmt 1 view .LVU305 +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 997 .loc 1 2136 15 is_stmt 0 view .LVU306 + 998 00e0 04F57172 add r2, r4, #964 + 999 .LVL89: +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1000 .loc 1 2136 15 view .LVU307 + 1001 00e4 0021 movs r1, #0 + 1002 00e6 FFF7FEFF bl USB_EP0_OutStart + 1003 .LVL90: +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1004 .loc 1 2136 15 view .LVU308 + 1005 00ea A2E7 b .L61 + 1006 .L68: + 1007 .align 2 + 1008 .L67: + 1009 00ec 0A31544F .word 1330917642 + 1010 00f0 0A30544F .word 1330917386 + 1011 .cfi_endproc + 1012 .LFE174: + 1014 .section .text.HAL_PCD_DataInStageCallback,"ax",%progbits + 1015 .align 1 + 1016 .weak HAL_PCD_DataInStageCallback + 1017 .syntax unified + 1018 .thumb + 1019 .thumb_func + 1020 .fpu fpv5-d16 + 1022 HAL_PCD_DataInStageCallback: + 1023 .LVL91: + 1024 .LFB149: +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1025 .loc 1 1443 1 is_stmt 1 view -0 + 1026 .cfi_startproc + 1027 @ args = 0, pretend = 0, frame = 0 + 1028 @ frame_needed = 0, uses_anonymous_args = 0 + 1029 @ link register save eliminated. +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); + 1030 .loc 1 1445 3 view .LVU310 +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1031 .loc 1 1446 3 view .LVU311 +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 1032 .loc 1 1451 1 is_stmt 0 view .LVU312 + 1033 0000 7047 bx lr + 1034 .cfi_endproc + 1035 .LFE149: + 1037 .section .text.HAL_PCD_SetupStageCallback,"ax",%progbits + 1038 .align 1 + 1039 .weak HAL_PCD_SetupStageCallback + 1040 .syntax unified + 1041 .thumb + 1042 .thumb_func + 1043 .fpu fpv5-d16 + 1045 HAL_PCD_SetupStageCallback: + 1046 .LVL92: + 1047 .LFB150: + ARM GAS /tmp/ccjyOkyX.s page 61 + + +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1048 .loc 1 1458 1 is_stmt 1 view -0 + 1049 .cfi_startproc + 1050 @ args = 0, pretend = 0, frame = 0 + 1051 @ frame_needed = 0, uses_anonymous_args = 0 + 1052 @ link register save eliminated. +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1053 .loc 1 1460 3 view .LVU314 +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1054 .loc 1 1465 1 is_stmt 0 view .LVU315 + 1055 0000 7047 bx lr + 1056 .cfi_endproc + 1057 .LFE150: + 1059 .section .text.PCD_EP_OutSetupPacket_int,"ax",%progbits + 1060 .align 1 + 1061 .syntax unified + 1062 .thumb + 1063 .thumb_func + 1064 .fpu fpv5-d16 + 1066 PCD_EP_OutSetupPacket_int: + 1067 .LVL93: + 1068 .LFB175: +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @brief process EP OUT setup packet received interrupt. +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param hpcd PCD handle +2154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @param epnum endpoint number +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** * @retval HAL status +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** */ +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +2158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1069 .loc 1 2158 1 is_stmt 1 view -0 + 1070 .cfi_startproc + 1071 @ args = 0, pretend = 0, frame = 0 + 1072 @ frame_needed = 0, uses_anonymous_args = 0 + 1073 .loc 1 2158 1 is_stmt 0 view .LVU317 + 1074 0000 38B5 push {r3, r4, r5, lr} + 1075 .LCFI14: + 1076 .cfi_def_cfa_offset 16 + 1077 .cfi_offset 3, -16 + 1078 .cfi_offset 4, -12 + 1079 .cfi_offset 5, -8 + 1080 .cfi_offset 14, -4 + 1081 0002 0446 mov r4, r0 +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 1082 .loc 1 2159 3 is_stmt 1 view .LVU318 + 1083 .loc 1 2159 26 is_stmt 0 view .LVU319 + 1084 0004 0368 ldr r3, [r0] + 1085 .LVL94: +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1086 .loc 1 2160 3 is_stmt 1 view .LVU320 +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + 1087 .loc 1 2161 3 view .LVU321 + 1088 .loc 1 2161 12 is_stmt 0 view .LVU322 + 1089 0006 1D6C ldr r5, [r3, #64] + 1090 .LVL95: + ARM GAS /tmp/ccjyOkyX.s page 62 + + +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + 1091 .loc 1 2162 3 is_stmt 1 view .LVU323 + 1092 .loc 1 2162 25 is_stmt 0 view .LVU324 + 1093 0008 03EB4113 add r3, r3, r1, lsl #5 + 1094 .LVL96: + 1095 .loc 1 2162 12 view .LVU325 + 1096 000c D3F8081B ldr r1, [r3, #2824] + 1097 .LVL97: +2163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + 1098 .loc 1 2164 3 is_stmt 1 view .LVU326 + 1099 .loc 1 2164 6 is_stmt 0 view .LVU327 + 1100 0010 0E4A ldr r2, .L76 + 1101 0012 9542 cmp r5, r2 + 1102 0014 07D9 bls .L72 + 1103 0016 03F53063 add r3, r3, #2816 + 1104 .loc 1 2164 40 discriminator 1 view .LVU328 + 1105 001a 11F4004F tst r1, #32768 + 1106 001e 02D0 beq .L72 +2165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) +2166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + 1107 .loc 1 2167 5 is_stmt 1 view .LVU329 + 1108 0020 4FF40042 mov r2, #32768 + 1109 0024 9A60 str r2, [r3, #8] + 1110 .LVL98: + 1111 .L72: +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Inform the upper layer that a setup packet is available */ +2171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->SetupStageCallback(hpcd); +2173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #else +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_PCD_SetupStageCallback(hpcd); + 1112 .loc 1 2174 3 view .LVU330 + 1113 0026 2046 mov r0, r4 + 1114 .LVL99: + 1115 .loc 1 2174 3 is_stmt 0 view .LVU331 + 1116 0028 FFF7FEFF bl HAL_PCD_SetupStageCallback + 1117 .LVL100: +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +2176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + 1118 .loc 1 2177 3 is_stmt 1 view .LVU332 + 1119 .loc 1 2177 6 is_stmt 0 view .LVU333 + 1120 002c 074B ldr r3, .L76 + 1121 002e 9D42 cmp r5, r3 + 1122 0030 02D9 bls .L73 + 1123 .loc 1 2177 54 discriminator 1 view .LVU334 + 1124 0032 2369 ldr r3, [r4, #16] + 1125 .loc 1 2177 40 discriminator 1 view .LVU335 + 1126 0034 012B cmp r3, #1 + 1127 0036 01D0 beq .L75 + 1128 .L73: +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 63 + + +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 1129 .loc 1 2182 3 is_stmt 1 view .LVU336 +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1130 .loc 1 2183 1 is_stmt 0 view .LVU337 + 1131 0038 0020 movs r0, #0 + 1132 003a 38BD pop {r3, r4, r5, pc} + 1133 .LVL101: + 1134 .L75: +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1135 .loc 1 2179 5 is_stmt 1 view .LVU338 +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1136 .loc 1 2179 11 is_stmt 0 view .LVU339 + 1137 003c 04F57172 add r2, r4, #964 + 1138 0040 0121 movs r1, #1 + 1139 0042 2068 ldr r0, [r4] + 1140 0044 FFF7FEFF bl USB_EP0_OutStart + 1141 .LVL102: + 1142 0048 F6E7 b .L73 + 1143 .L77: + 1144 004a 00BF .align 2 + 1145 .L76: + 1146 004c 0A30544F .word 1330917386 + 1147 .cfi_endproc + 1148 .LFE175: + 1150 .section .text.HAL_PCD_SOFCallback,"ax",%progbits + 1151 .align 1 + 1152 .weak HAL_PCD_SOFCallback + 1153 .syntax unified + 1154 .thumb + 1155 .thumb_func + 1156 .fpu fpv5-d16 + 1158 HAL_PCD_SOFCallback: + 1159 .LVL103: + 1160 .LFB151: +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1161 .loc 1 1473 1 is_stmt 1 view -0 + 1162 .cfi_startproc + 1163 @ args = 0, pretend = 0, frame = 0 + 1164 @ frame_needed = 0, uses_anonymous_args = 0 + 1165 @ link register save eliminated. +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1166 .loc 1 1475 3 view .LVU341 +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1167 .loc 1 1480 1 is_stmt 0 view .LVU342 + 1168 0000 7047 bx lr + 1169 .cfi_endproc + 1170 .LFE151: + 1172 .section .text.HAL_PCD_ResetCallback,"ax",%progbits + 1173 .align 1 + 1174 .weak HAL_PCD_ResetCallback + 1175 .syntax unified + 1176 .thumb + 1177 .thumb_func + 1178 .fpu fpv5-d16 + 1180 HAL_PCD_ResetCallback: + 1181 .LVL104: + ARM GAS /tmp/ccjyOkyX.s page 64 + + + 1182 .LFB152: +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1183 .loc 1 1488 1 is_stmt 1 view -0 + 1184 .cfi_startproc + 1185 @ args = 0, pretend = 0, frame = 0 + 1186 @ frame_needed = 0, uses_anonymous_args = 0 + 1187 @ link register save eliminated. +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1188 .loc 1 1490 3 view .LVU344 +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1189 .loc 1 1495 1 is_stmt 0 view .LVU345 + 1190 0000 7047 bx lr + 1191 .cfi_endproc + 1192 .LFE152: + 1194 .section .text.HAL_PCD_SuspendCallback,"ax",%progbits + 1195 .align 1 + 1196 .weak HAL_PCD_SuspendCallback + 1197 .syntax unified + 1198 .thumb + 1199 .thumb_func + 1200 .fpu fpv5-d16 + 1202 HAL_PCD_SuspendCallback: + 1203 .LVL105: + 1204 .LFB153: +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1205 .loc 1 1503 1 is_stmt 1 view -0 + 1206 .cfi_startproc + 1207 @ args = 0, pretend = 0, frame = 0 + 1208 @ frame_needed = 0, uses_anonymous_args = 0 + 1209 @ link register save eliminated. +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1210 .loc 1 1505 3 view .LVU347 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1211 .loc 1 1510 1 is_stmt 0 view .LVU348 + 1212 0000 7047 bx lr + 1213 .cfi_endproc + 1214 .LFE153: + 1216 .section .text.HAL_PCD_ResumeCallback,"ax",%progbits + 1217 .align 1 + 1218 .weak HAL_PCD_ResumeCallback + 1219 .syntax unified + 1220 .thumb + 1221 .thumb_func + 1222 .fpu fpv5-d16 + 1224 HAL_PCD_ResumeCallback: + 1225 .LVL106: + 1226 .LFB154: +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1227 .loc 1 1518 1 is_stmt 1 view -0 + 1228 .cfi_startproc + 1229 @ args = 0, pretend = 0, frame = 0 + 1230 @ frame_needed = 0, uses_anonymous_args = 0 + 1231 @ link register save eliminated. +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1232 .loc 1 1520 3 view .LVU350 +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1233 .loc 1 1525 1 is_stmt 0 view .LVU351 + ARM GAS /tmp/ccjyOkyX.s page 65 + + + 1234 0000 7047 bx lr + 1235 .cfi_endproc + 1236 .LFE154: + 1238 .section .text.HAL_PCD_ISOOUTIncompleteCallback,"ax",%progbits + 1239 .align 1 + 1240 .weak HAL_PCD_ISOOUTIncompleteCallback + 1241 .syntax unified + 1242 .thumb + 1243 .thumb_func + 1244 .fpu fpv5-d16 + 1246 HAL_PCD_ISOOUTIncompleteCallback: + 1247 .LVL107: + 1248 .LFB155: +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1249 .loc 1 1534 1 is_stmt 1 view -0 + 1250 .cfi_startproc + 1251 @ args = 0, pretend = 0, frame = 0 + 1252 @ frame_needed = 0, uses_anonymous_args = 0 + 1253 @ link register save eliminated. +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); + 1254 .loc 1 1536 3 view .LVU353 +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1255 .loc 1 1537 3 view .LVU354 +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1256 .loc 1 1542 1 is_stmt 0 view .LVU355 + 1257 0000 7047 bx lr + 1258 .cfi_endproc + 1259 .LFE155: + 1261 .section .text.HAL_PCD_ISOINIncompleteCallback,"ax",%progbits + 1262 .align 1 + 1263 .weak HAL_PCD_ISOINIncompleteCallback + 1264 .syntax unified + 1265 .thumb + 1266 .thumb_func + 1267 .fpu fpv5-d16 + 1269 HAL_PCD_ISOINIncompleteCallback: + 1270 .LVL108: + 1271 .LFB156: +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1272 .loc 1 1551 1 is_stmt 1 view -0 + 1273 .cfi_startproc + 1274 @ args = 0, pretend = 0, frame = 0 + 1275 @ frame_needed = 0, uses_anonymous_args = 0 + 1276 @ link register save eliminated. +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** UNUSED(epnum); + 1277 .loc 1 1553 3 view .LVU357 +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1278 .loc 1 1554 3 view .LVU358 +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1279 .loc 1 1559 1 is_stmt 0 view .LVU359 + 1280 0000 7047 bx lr + 1281 .cfi_endproc + 1282 .LFE156: + 1284 .section .text.HAL_PCD_ConnectCallback,"ax",%progbits + 1285 .align 1 + 1286 .weak HAL_PCD_ConnectCallback + 1287 .syntax unified + ARM GAS /tmp/ccjyOkyX.s page 66 + + + 1288 .thumb + 1289 .thumb_func + 1290 .fpu fpv5-d16 + 1292 HAL_PCD_ConnectCallback: + 1293 .LVL109: + 1294 .LFB157: +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1295 .loc 1 1567 1 is_stmt 1 view -0 + 1296 .cfi_startproc + 1297 @ args = 0, pretend = 0, frame = 0 + 1298 @ frame_needed = 0, uses_anonymous_args = 0 + 1299 @ link register save eliminated. +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1300 .loc 1 1569 3 view .LVU361 +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1301 .loc 1 1574 1 is_stmt 0 view .LVU362 + 1302 0000 7047 bx lr + 1303 .cfi_endproc + 1304 .LFE157: + 1306 .section .text.HAL_PCD_DisconnectCallback,"ax",%progbits + 1307 .align 1 + 1308 .weak HAL_PCD_DisconnectCallback + 1309 .syntax unified + 1310 .thumb + 1311 .thumb_func + 1312 .fpu fpv5-d16 + 1314 HAL_PCD_DisconnectCallback: + 1315 .LVL110: + 1316 .LFB158: +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Prevent unused argument(s) compilation warning */ + 1317 .loc 1 1582 1 is_stmt 1 view -0 + 1318 .cfi_startproc + 1319 @ args = 0, pretend = 0, frame = 0 + 1320 @ frame_needed = 0, uses_anonymous_args = 0 + 1321 @ link register save eliminated. +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1322 .loc 1 1584 3 view .LVU364 +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1323 .loc 1 1589 1 is_stmt 0 view .LVU365 + 1324 0000 7047 bx lr + 1325 .cfi_endproc + 1326 .LFE158: + 1328 .section .text.HAL_PCD_IRQHandler,"ax",%progbits + 1329 .align 1 + 1330 .global HAL_PCD_IRQHandler + 1331 .syntax unified + 1332 .thumb + 1333 .thumb_func + 1334 .fpu fpv5-d16 + 1336 HAL_PCD_IRQHandler: + 1337 .LVL111: + 1338 .LFB147: +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 1339 .loc 1 1039 1 is_stmt 1 view -0 + 1340 .cfi_startproc + 1341 @ args = 0, pretend = 0, frame = 0 + 1342 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccjyOkyX.s page 67 + + +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 1343 .loc 1 1039 1 is_stmt 0 view .LVU367 + 1344 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr} + 1345 .LCFI15: + 1346 .cfi_def_cfa_offset 40 + 1347 .cfi_offset 3, -40 + 1348 .cfi_offset 4, -36 + 1349 .cfi_offset 5, -32 + 1350 .cfi_offset 6, -28 + 1351 .cfi_offset 7, -24 + 1352 .cfi_offset 8, -20 + 1353 .cfi_offset 9, -16 + 1354 .cfi_offset 10, -12 + 1355 .cfi_offset 11, -8 + 1356 .cfi_offset 14, -4 + 1357 0004 0446 mov r4, r0 +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1358 .loc 1 1040 3 is_stmt 1 view .LVU368 +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1359 .loc 1 1040 26 is_stmt 0 view .LVU369 + 1360 0006 0568 ldr r5, [r0] + 1361 .LVL112: +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t i, ep_intr, epint, epnum; + 1362 .loc 1 1041 3 is_stmt 1 view .LVU370 +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** uint32_t fifoemptymsk, temp; + 1363 .loc 1 1042 3 view .LVU371 +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_EPTypeDef *ep; + 1364 .loc 1 1043 3 view .LVU372 +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1365 .loc 1 1044 3 view .LVU373 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1366 .loc 1 1047 3 view .LVU374 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1367 .loc 1 1047 7 is_stmt 0 view .LVU375 + 1368 0008 2846 mov r0, r5 + 1369 .LVL113: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1370 .loc 1 1047 7 view .LVU376 + 1371 000a FFF7FEFF bl USB_GetMode + 1372 .LVL114: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1373 .loc 1 1047 6 view .LVU377 + 1374 000e 08B1 cbz r0, .L129 + 1375 .LVL115: + 1376 .L86: +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 1377 .loc 1 1415 1 view .LVU378 + 1378 0010 BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc} + 1379 .LVL116: + 1380 .L129: +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 1381 .loc 1 1415 1 view .LVU379 + 1382 0014 0646 mov r6, r0 +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1383 .loc 1 1050 5 is_stmt 1 view .LVU380 +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1384 .loc 1 1050 9 is_stmt 0 view .LVU381 + ARM GAS /tmp/ccjyOkyX.s page 68 + + + 1385 0016 2068 ldr r0, [r4] + 1386 0018 FFF7FEFF bl USB_ReadInterrupts + 1387 .LVL117: +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1388 .loc 1 1050 8 view .LVU382 + 1389 001c 0028 cmp r0, #0 + 1390 001e F7D0 beq .L86 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1391 .loc 1 1055 5 is_stmt 1 view .LVU383 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1392 .loc 1 1055 9 is_stmt 0 view .LVU384 + 1393 0020 2068 ldr r0, [r4] + 1394 0022 FFF7FEFF bl USB_ReadInterrupts + 1395 .LVL118: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1396 .loc 1 1055 8 view .LVU385 + 1397 0026 10F0020F tst r0, #2 + 1398 002a 04D0 beq .L88 +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1399 .loc 1 1058 7 is_stmt 1 view .LVU386 + 1400 002c 2268 ldr r2, [r4] + 1401 002e 5369 ldr r3, [r2, #20] + 1402 0030 03F00203 and r3, r3, #2 + 1403 0034 5361 str r3, [r2, #20] + 1404 .L88: +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1405 .loc 1 1062 5 view .LVU387 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1406 .loc 1 1062 9 is_stmt 0 view .LVU388 + 1407 0036 2068 ldr r0, [r4] + 1408 0038 FFF7FEFF bl USB_ReadInterrupts + 1409 .LVL119: +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1410 .loc 1 1062 8 view .LVU389 + 1411 003c 10F0100F tst r0, #16 + 1412 0040 14D0 beq .L89 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1413 .loc 1 1064 7 is_stmt 1 view .LVU390 + 1414 0042 2268 ldr r2, [r4] + 1415 0044 9369 ldr r3, [r2, #24] + 1416 0046 23F01003 bic r3, r3, #16 + 1417 004a 9361 str r3, [r2, #24] +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1418 .loc 1 1066 7 view .LVU391 +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1419 .loc 1 1066 12 is_stmt 0 view .LVU392 + 1420 004c 2F6A ldr r7, [r5, #32] + 1421 .LVL120: +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1422 .loc 1 1068 7 is_stmt 1 view .LVU393 +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1423 .loc 1 1068 31 is_stmt 0 view .LVU394 + 1424 004e 07F00F08 and r8, r7, #15 + 1425 .LVL121: +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1426 .loc 1 1070 7 is_stmt 1 view .LVU395 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 69 + + + 1427 .loc 1 1070 44 is_stmt 0 view .LVU396 + 1428 0052 C7F34343 ubfx r3, r7, #17, #4 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1429 .loc 1 1070 10 view .LVU397 + 1430 0056 022B cmp r3, #2 + 1431 0058 00F08580 beq .L130 +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1432 .loc 1 1081 12 is_stmt 1 view .LVU398 +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1433 .loc 1 1081 15 is_stmt 0 view .LVU399 + 1434 005c 062B cmp r3, #6 + 1435 005e 00F0A180 beq .L131 + 1436 .LVL122: + 1437 .L91: +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + 1438 .loc 1 1089 7 is_stmt 1 view .LVU400 +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1439 .loc 1 1090 7 view .LVU401 + 1440 0062 2268 ldr r2, [r4] + 1441 0064 9369 ldr r3, [r2, #24] + 1442 0066 43F01003 orr r3, r3, #16 + 1443 006a 9361 str r3, [r2, #24] + 1444 .LVL123: + 1445 .L89: +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1446 .loc 1 1093 5 view .LVU402 +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1447 .loc 1 1093 9 is_stmt 0 view .LVU403 + 1448 006c 2068 ldr r0, [r4] + 1449 006e FFF7FEFF bl USB_ReadInterrupts + 1450 .LVL124: +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1451 .loc 1 1093 8 view .LVU404 + 1452 0072 10F4002F tst r0, #524288 + 1453 0076 40F0A780 bne .L132 + 1454 .L92: +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1455 .loc 1 1141 5 is_stmt 1 view .LVU405 +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1456 .loc 1 1141 9 is_stmt 0 view .LVU406 + 1457 007a 2068 ldr r0, [r4] + 1458 007c FFF7FEFF bl USB_ReadInterrupts + 1459 .LVL125: +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1460 .loc 1 1141 8 view .LVU407 + 1461 0080 10F4802F tst r0, #262144 + 1462 0084 40F0E980 bne .L133 + 1463 .L100: +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1464 .loc 1 1206 5 is_stmt 1 view .LVU408 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1465 .loc 1 1206 9 is_stmt 0 view .LVU409 + 1466 0088 2068 ldr r0, [r4] + 1467 008a FFF7FEFF bl USB_ReadInterrupts + 1468 .LVL126: +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1469 .loc 1 1206 8 view .LVU410 + ARM GAS /tmp/ccjyOkyX.s page 70 + + + 1470 008e 0028 cmp r0, #0 + 1471 0090 C0F25381 blt .L134 + 1472 .L110: +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1473 .loc 1 1234 5 is_stmt 1 view .LVU411 +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1474 .loc 1 1234 9 is_stmt 0 view .LVU412 + 1475 0094 2068 ldr r0, [r4] + 1476 0096 FFF7FEFF bl USB_ReadInterrupts + 1477 .LVL127: +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1478 .loc 1 1234 8 view .LVU413 + 1479 009a 10F4006F tst r0, #2048 + 1480 009e 0AD0 beq .L113 +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1481 .loc 1 1236 7 is_stmt 1 view .LVU414 +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1482 .loc 1 1236 23 is_stmt 0 view .LVU415 + 1483 00a0 D5F80838 ldr r3, [r5, #2056] +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1484 .loc 1 1236 10 view .LVU416 + 1485 00a4 13F0010F tst r3, #1 + 1486 00a8 40F06181 bne .L135 + 1487 .L114: +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1488 .loc 1 1244 7 is_stmt 1 view .LVU417 + 1489 00ac 2268 ldr r2, [r4] + 1490 00ae 5369 ldr r3, [r2, #20] + 1491 00b0 03F40063 and r3, r3, #2048 + 1492 00b4 5361 str r3, [r2, #20] + 1493 .L113: +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1494 .loc 1 1248 5 view .LVU418 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1495 .loc 1 1248 9 is_stmt 0 view .LVU419 + 1496 00b6 2068 ldr r0, [r4] + 1497 00b8 FFF7FEFF bl USB_ReadInterrupts + 1498 .LVL128: +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1499 .loc 1 1248 8 view .LVU420 + 1500 00bc 10F0006F tst r0, #134217728 + 1501 00c0 15D0 beq .L115 +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1502 .loc 1 1250 7 is_stmt 1 view .LVU421 + 1503 00c2 2268 ldr r2, [r4] + 1504 00c4 5369 ldr r3, [r2, #20] + 1505 00c6 03F00063 and r3, r3, #134217728 + 1506 00ca 5361 str r3, [r2, #20] +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1507 .loc 1 1252 7 view .LVU422 +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1508 .loc 1 1252 15 is_stmt 0 view .LVU423 + 1509 00cc 94F8F433 ldrb r3, [r4, #1012] @ zero_extendqisi2 +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1510 .loc 1 1252 10 view .LVU424 + 1511 00d0 002B cmp r3, #0 + 1512 00d2 40F05081 bne .L116 + ARM GAS /tmp/ccjyOkyX.s page 71 + + +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + 1513 .loc 1 1254 9 is_stmt 1 view .LVU425 +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + 1514 .loc 1 1254 25 is_stmt 0 view .LVU426 + 1515 00d6 0121 movs r1, #1 + 1516 00d8 84F8F413 strb r1, [r4, #1012] +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1517 .loc 1 1255 9 is_stmt 1 view .LVU427 +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1518 .loc 1 1255 27 is_stmt 0 view .LVU428 + 1519 00dc 2368 ldr r3, [r4] +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1520 .loc 1 1255 37 view .LVU429 + 1521 00de 5B6D ldr r3, [r3, #84] +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1522 .loc 1 1255 71 view .LVU430 + 1523 00e0 C3F38303 ubfx r3, r3, #2, #4 +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1524 .loc 1 1255 20 view .LVU431 + 1525 00e4 C4F8F833 str r3, [r4, #1016] +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 1526 .loc 1 1260 9 is_stmt 1 view .LVU432 + 1527 00e8 2046 mov r0, r4 + 1528 00ea FFF7FEFF bl HAL_PCDEx_LPM_Callback + 1529 .LVL129: + 1530 .L115: +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1531 .loc 1 1274 5 view .LVU433 +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1532 .loc 1 1274 9 is_stmt 0 view .LVU434 + 1533 00ee 2068 ldr r0, [r4] + 1534 00f0 FFF7FEFF bl USB_ReadInterrupts + 1535 .LVL130: +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1536 .loc 1 1274 8 view .LVU435 + 1537 00f4 10F4805F tst r0, #4096 + 1538 00f8 40F04181 bne .L136 + 1539 .L117: +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1540 .loc 1 1324 5 is_stmt 1 view .LVU436 +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1541 .loc 1 1324 9 is_stmt 0 view .LVU437 + 1542 00fc 2068 ldr r0, [r4] + 1543 00fe FFF7FEFF bl USB_ReadInterrupts + 1544 .LVL131: +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1545 .loc 1 1324 8 view .LVU438 + 1546 0102 10F4005F tst r0, #8192 + 1547 0106 40F09581 bne .L137 + 1548 .LVL132: + 1549 .L122: +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1550 .loc 1 1344 5 is_stmt 1 view .LVU439 +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1551 .loc 1 1344 9 is_stmt 0 view .LVU440 + 1552 010a 2068 ldr r0, [r4] + 1553 010c FFF7FEFF bl USB_ReadInterrupts + ARM GAS /tmp/ccjyOkyX.s page 72 + + + 1554 .LVL133: +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1555 .loc 1 1344 8 view .LVU441 + 1556 0110 10F0080F tst r0, #8 + 1557 0114 40F0A681 bne .L138 + 1558 .L123: +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1559 .loc 1 1356 5 is_stmt 1 view .LVU442 +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1560 .loc 1 1356 9 is_stmt 0 view .LVU443 + 1561 0118 2068 ldr r0, [r4] + 1562 011a FFF7FEFF bl USB_ReadInterrupts + 1563 .LVL134: +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1564 .loc 1 1356 8 view .LVU444 + 1565 011e 10F4801F tst r0, #1048576 + 1566 0122 40F0A881 bne .L139 + 1567 .L124: +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1568 .loc 1 1372 5 is_stmt 1 view .LVU445 +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1569 .loc 1 1372 9 is_stmt 0 view .LVU446 + 1570 0126 2068 ldr r0, [r4] + 1571 0128 FFF7FEFF bl USB_ReadInterrupts + 1572 .LVL135: +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1573 .loc 1 1372 8 view .LVU447 + 1574 012c 10F4001F tst r0, #2097152 + 1575 0130 40F0AB81 bne .L140 + 1576 .L125: +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1577 .loc 1 1388 5 is_stmt 1 view .LVU448 +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1578 .loc 1 1388 9 is_stmt 0 view .LVU449 + 1579 0134 2068 ldr r0, [r4] + 1580 0136 FFF7FEFF bl USB_ReadInterrupts + 1581 .LVL136: +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1582 .loc 1 1388 8 view .LVU450 + 1583 013a 10F0804F tst r0, #1073741824 + 1584 013e 40F0AE81 bne .L141 + 1585 .L126: +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1586 .loc 1 1400 5 is_stmt 1 view .LVU451 +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1587 .loc 1 1400 9 is_stmt 0 view .LVU452 + 1588 0142 2068 ldr r0, [r4] + 1589 0144 FFF7FEFF bl USB_ReadInterrupts + 1590 .LVL137: +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1591 .loc 1 1400 8 view .LVU453 + 1592 0148 10F0040F tst r0, #4 + 1593 014c 3FF460AF beq .L86 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1594 .loc 1 1402 7 is_stmt 1 view .LVU454 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1595 .loc 1 1402 18 is_stmt 0 view .LVU455 + ARM GAS /tmp/ccjyOkyX.s page 73 + + + 1596 0150 2368 ldr r3, [r4] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1597 .loc 1 1402 12 view .LVU456 + 1598 0152 5D68 ldr r5, [r3, #4] + 1599 .LVL138: +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1600 .loc 1 1404 7 is_stmt 1 view .LVU457 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1601 .loc 1 1404 10 is_stmt 0 view .LVU458 + 1602 0154 15F0040F tst r5, #4 + 1603 0158 40F0AA81 bne .L142 + 1604 .L127: +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1605 .loc 1 1412 7 is_stmt 1 view .LVU459 +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1606 .loc 1 1412 11 is_stmt 0 view .LVU460 + 1607 015c 2268 ldr r2, [r4] +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1608 .loc 1 1412 31 view .LVU461 + 1609 015e 5368 ldr r3, [r2, #4] + 1610 0160 2B43 orrs r3, r3, r5 + 1611 0162 5360 str r3, [r2, #4] + 1612 0164 54E7 b .L86 + 1613 .LVL139: + 1614 .L130: +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1615 .loc 1 1072 9 is_stmt 1 view .LVU462 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1616 .loc 1 1072 12 is_stmt 0 view .LVU463 + 1617 0166 47F6F073 movw r3, #32752 + 1618 016a 1F42 tst r7, r3 + 1619 016c 3FF479AF beq .L91 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + 1620 .loc 1 1074 11 is_stmt 1 view .LVU464 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1621 .loc 1 1075 73 is_stmt 0 view .LVU465 + 1622 0170 4FEA171B lsr fp, r7, #4 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + 1623 .loc 1 1074 17 view .LVU466 + 1624 0174 C8EBC809 rsb r9, r8, r8, lsl #3 + 1625 0178 04EB8909 add r9, r4, r9, lsl #2 + 1626 017c C7F30A12 ubfx r2, r7, #4, #11 + 1627 0180 D9F80812 ldr r1, [r9, #520] + 1628 0184 2846 mov r0, r5 + 1629 0186 FFF7FEFF bl USB_ReadPacket + 1630 .LVL140: +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + 1631 .loc 1 1077 11 is_stmt 1 view .LVU467 +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + 1632 .loc 1 1077 58 is_stmt 0 view .LVU468 + 1633 018a CBF30A02 ubfx r2, fp, #0, #11 +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + 1634 .loc 1 1077 25 view .LVU469 + 1635 018e D9F80832 ldr r3, [r9, #520] + 1636 0192 1344 add r3, r3, r2 + 1637 0194 C9F80832 str r3, [r9, #520] +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 74 + + + 1638 .loc 1 1078 11 is_stmt 1 view .LVU470 +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1639 .loc 1 1078 26 is_stmt 0 view .LVU471 + 1640 0198 D9F81432 ldr r3, [r9, #532] + 1641 019c 1A44 add r2, r2, r3 + 1642 019e C9F81422 str r2, [r9, #532] + 1643 01a2 5EE7 b .L91 + 1644 .L131: +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + 1645 .loc 1 1083 9 is_stmt 1 view .LVU472 +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + 1646 .loc 1 1083 15 is_stmt 0 view .LVU473 + 1647 01a4 0822 movs r2, #8 + 1648 01a6 04F57171 add r1, r4, #964 + 1649 01aa 2846 mov r0, r5 + 1650 01ac FFF7FEFF bl USB_ReadPacket + 1651 .LVL141: +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1652 .loc 1 1084 9 is_stmt 1 view .LVU474 +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1653 .loc 1 1084 57 is_stmt 0 view .LVU475 + 1654 01b0 C7F30A17 ubfx r7, r7, #4, #11 + 1655 .LVL142: +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1656 .loc 1 1084 24 view .LVU476 + 1657 01b4 C8EBC802 rsb r2, r8, r8, lsl #3 + 1658 01b8 04EB8202 add r2, r4, r2, lsl #2 + 1659 01bc D2F81432 ldr r3, [r2, #532] + 1660 01c0 1F44 add r7, r7, r3 + 1661 01c2 C2F81472 str r7, [r2, #532] + 1662 01c6 4CE7 b .L91 + 1663 .LVL143: + 1664 .L132: +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1665 .loc 1 1095 7 is_stmt 1 view .LVU477 +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1666 .loc 1 1098 7 view .LVU478 +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1667 .loc 1 1098 17 is_stmt 0 view .LVU479 + 1668 01c8 2068 ldr r0, [r4] + 1669 01ca FFF7FEFF bl USB_ReadDevAllOutEpInterrupt + 1670 .LVL144: + 1671 01ce 0746 mov r7, r0 + 1672 .LVL145: +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1673 .loc 1 1100 7 is_stmt 1 view .LVU480 +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1674 .loc 1 1095 13 is_stmt 0 view .LVU481 + 1675 01d0 B046 mov r8, r6 +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1676 .loc 1 1100 13 view .LVU482 + 1677 01d2 16E0 b .L93 + 1678 .LVL146: + 1679 .L143: +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + 1680 .loc 1 1108 13 is_stmt 1 view .LVU483 + 1681 01d4 05EB4813 add r3, r5, r8, lsl #5 + ARM GAS /tmp/ccjyOkyX.s page 75 + + + 1682 01d8 0122 movs r2, #1 + 1683 01da C3F8082B str r2, [r3, #2824] +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1684 .loc 1 1109 13 view .LVU484 +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1685 .loc 1 1109 19 is_stmt 0 view .LVU485 + 1686 01de 4146 mov r1, r8 + 1687 01e0 2046 mov r0, r4 + 1688 .LVL147: +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1689 .loc 1 1109 19 view .LVU486 + 1690 01e2 FFF7FEFF bl PCD_EP_OutXfrComplete_int + 1691 .LVL148: + 1692 01e6 1BE0 b .L95 + 1693 .L144: +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /* Class B setup phase done for previous decoded setup */ + 1694 .loc 1 1114 13 is_stmt 1 view .LVU487 + 1695 01e8 05EB4813 add r3, r5, r8, lsl #5 + 1696 01ec 0822 movs r2, #8 + 1697 01ee C3F8082B str r2, [r3, #2824] +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1698 .loc 1 1116 13 view .LVU488 +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1699 .loc 1 1116 19 is_stmt 0 view .LVU489 + 1700 01f2 4146 mov r1, r8 + 1701 01f4 2046 mov r0, r4 + 1702 01f6 FFF7FEFF bl PCD_EP_OutSetupPacket_int + 1703 .LVL149: + 1704 01fa 14E0 b .L96 + 1705 .LVL150: + 1706 .L94: +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr >>= 1U; + 1707 .loc 1 1136 9 is_stmt 1 view .LVU490 +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr >>= 1U; + 1708 .loc 1 1136 14 is_stmt 0 view .LVU491 + 1709 01fc 08F10108 add r8, r8, #1 + 1710 .LVL151: +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1711 .loc 1 1137 9 is_stmt 1 view .LVU492 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1712 .loc 1 1137 17 is_stmt 0 view .LVU493 + 1713 0200 7F08 lsrs r7, r7, #1 + 1714 .LVL152: + 1715 .L93: +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1716 .loc 1 1100 13 is_stmt 1 view .LVU494 + 1717 0202 002F cmp r7, #0 + 1718 0204 3FF439AF beq .L92 +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1719 .loc 1 1102 9 view .LVU495 +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1720 .loc 1 1102 12 is_stmt 0 view .LVU496 + 1721 0208 17F0010F tst r7, #1 + 1722 020c F6D0 beq .L94 +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1723 .loc 1 1104 11 is_stmt 1 view .LVU497 +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 76 + + + 1724 .loc 1 1104 19 is_stmt 0 view .LVU498 + 1725 020e 5FFA88F1 uxtb r1, r8 + 1726 0212 2068 ldr r0, [r4] + 1727 0214 FFF7FEFF bl USB_ReadDevOutEPInterrupt + 1728 .LVL153: + 1729 0218 8146 mov r9, r0 + 1730 .LVL154: +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1731 .loc 1 1106 11 is_stmt 1 view .LVU499 +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1732 .loc 1 1106 14 is_stmt 0 view .LVU500 + 1733 021a 10F0010F tst r0, #1 + 1734 021e D9D1 bne .L143 + 1735 .LVL155: + 1736 .L95: +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1737 .loc 1 1112 11 is_stmt 1 view .LVU501 +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1738 .loc 1 1112 14 is_stmt 0 view .LVU502 + 1739 0220 19F0080F tst r9, #8 + 1740 0224 E0D1 bne .L144 + 1741 .L96: +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1742 .loc 1 1119 11 is_stmt 1 view .LVU503 +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1743 .loc 1 1119 14 is_stmt 0 view .LVU504 + 1744 0226 19F0100F tst r9, #16 + 1745 022a 04D0 beq .L97 +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1746 .loc 1 1121 13 is_stmt 1 view .LVU505 + 1747 022c 05EB4813 add r3, r5, r8, lsl #5 + 1748 0230 1022 movs r2, #16 + 1749 0232 C3F8082B str r2, [r3, #2824] + 1750 .L97: +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1751 .loc 1 1125 11 view .LVU506 +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1752 .loc 1 1125 14 is_stmt 0 view .LVU507 + 1753 0236 19F0200F tst r9, #32 + 1754 023a 04D0 beq .L98 +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1755 .loc 1 1127 13 is_stmt 1 view .LVU508 + 1756 023c 05EB4813 add r3, r5, r8, lsl #5 + 1757 0240 2022 movs r2, #32 + 1758 0242 C3F8082B str r2, [r3, #2824] + 1759 .L98: +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1760 .loc 1 1131 11 view .LVU509 +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1761 .loc 1 1131 14 is_stmt 0 view .LVU510 + 1762 0246 19F4005F tst r9, #8192 + 1763 024a D7D0 beq .L94 +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1764 .loc 1 1133 13 is_stmt 1 view .LVU511 + 1765 024c 05EB4813 add r3, r5, r8, lsl #5 + 1766 0250 4FF40052 mov r2, #8192 + 1767 0254 C3F8082B str r2, [r3, #2824] + ARM GAS /tmp/ccjyOkyX.s page 77 + + + 1768 0258 D0E7 b .L94 + 1769 .LVL156: + 1770 .L133: +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1771 .loc 1 1144 7 view .LVU512 +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1772 .loc 1 1144 17 is_stmt 0 view .LVU513 + 1773 025a 2068 ldr r0, [r4] + 1774 025c FFF7FEFF bl USB_ReadDevAllInEpInterrupt + 1775 .LVL157: + 1776 0260 0746 mov r7, r0 + 1777 .LVL158: +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1778 .loc 1 1146 7 is_stmt 1 view .LVU514 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1779 .loc 1 1148 7 view .LVU515 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1780 .loc 1 1146 13 is_stmt 0 view .LVU516 + 1781 0262 B046 mov r8, r6 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1782 .loc 1 1148 13 view .LVU517 + 1783 0264 29E0 b .L101 + 1784 .LVL159: + 1785 .L104: +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 1786 .loc 1 1176 13 is_stmt 1 view .LVU518 + 1787 0266 5146 mov r1, r10 + 1788 0268 2046 mov r0, r4 + 1789 026a FFF7FEFF bl HAL_PCD_DataInStageCallback + 1790 .LVL160: + 1791 .L103: +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1792 .loc 1 1179 11 view .LVU519 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1793 .loc 1 1179 14 is_stmt 0 view .LVU520 + 1794 026e 19F0080F tst r9, #8 + 1795 0272 04D0 beq .L105 +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1796 .loc 1 1181 13 is_stmt 1 view .LVU521 + 1797 0274 05EB4813 add r3, r5, r8, lsl #5 + 1798 0278 0822 movs r2, #8 + 1799 027a C3F80829 str r2, [r3, #2312] + 1800 .L105: +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1801 .loc 1 1183 11 view .LVU522 +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1802 .loc 1 1183 14 is_stmt 0 view .LVU523 + 1803 027e 19F0100F tst r9, #16 + 1804 0282 04D0 beq .L106 +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1805 .loc 1 1185 13 is_stmt 1 view .LVU524 + 1806 0284 05EB4813 add r3, r5, r8, lsl #5 + 1807 0288 1022 movs r2, #16 + 1808 028a C3F80829 str r2, [r3, #2312] + 1809 .L106: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1810 .loc 1 1187 11 view .LVU525 + ARM GAS /tmp/ccjyOkyX.s page 78 + + +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1811 .loc 1 1187 14 is_stmt 0 view .LVU526 + 1812 028e 19F0400F tst r9, #64 + 1813 0292 04D0 beq .L107 +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1814 .loc 1 1189 13 is_stmt 1 view .LVU527 + 1815 0294 05EB4813 add r3, r5, r8, lsl #5 + 1816 0298 4022 movs r2, #64 + 1817 029a C3F80829 str r2, [r3, #2312] + 1818 .L107: +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1819 .loc 1 1191 11 view .LVU528 +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1820 .loc 1 1191 14 is_stmt 0 view .LVU529 + 1821 029e 19F0020F tst r9, #2 + 1822 02a2 04D0 beq .L108 +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1823 .loc 1 1193 13 is_stmt 1 view .LVU530 + 1824 02a4 05EB4813 add r3, r5, r8, lsl #5 + 1825 02a8 0222 movs r2, #2 + 1826 02aa C3F80829 str r2, [r3, #2312] + 1827 .L108: +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1828 .loc 1 1195 11 view .LVU531 +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1829 .loc 1 1195 14 is_stmt 0 view .LVU532 + 1830 02ae 19F0800F tst r9, #128 + 1831 02b2 3DD1 bne .L145 + 1832 .LVL161: + 1833 .L102: +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr >>= 1U; + 1834 .loc 1 1200 9 is_stmt 1 view .LVU533 +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep_intr >>= 1U; + 1835 .loc 1 1200 14 is_stmt 0 view .LVU534 + 1836 02b4 08F10108 add r8, r8, #1 + 1837 .LVL162: +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1838 .loc 1 1201 9 is_stmt 1 view .LVU535 +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1839 .loc 1 1201 17 is_stmt 0 view .LVU536 + 1840 02b8 7F08 lsrs r7, r7, #1 + 1841 .LVL163: + 1842 .L101: +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1843 .loc 1 1148 13 is_stmt 1 view .LVU537 + 1844 02ba 002F cmp r7, #0 + 1845 02bc 3FF4E4AE beq .L100 +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1846 .loc 1 1150 9 view .LVU538 +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1847 .loc 1 1150 12 is_stmt 0 view .LVU539 + 1848 02c0 17F0010F tst r7, #1 + 1849 02c4 F6D0 beq .L102 +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1850 .loc 1 1152 11 is_stmt 1 view .LVU540 +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1851 .loc 1 1152 19 is_stmt 0 view .LVU541 + ARM GAS /tmp/ccjyOkyX.s page 79 + + + 1852 02c6 5FFA88FA uxtb r10, r8 + 1853 02ca 5146 mov r1, r10 + 1854 02cc 2068 ldr r0, [r4] + 1855 02ce FFF7FEFF bl USB_ReadDevInEPInterrupt + 1856 .LVL164: + 1857 02d2 8146 mov r9, r0 + 1858 .LVL165: +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1859 .loc 1 1154 11 is_stmt 1 view .LVU542 +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1860 .loc 1 1154 14 is_stmt 0 view .LVU543 + 1861 02d4 10F0010F tst r0, #1 + 1862 02d8 C9D0 beq .L103 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 1863 .loc 1 1156 13 is_stmt 1 view .LVU544 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 1864 .loc 1 1156 55 is_stmt 0 view .LVU545 + 1865 02da 08F00F03 and r3, r8, #15 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + 1866 .loc 1 1156 26 view .LVU546 + 1867 02de 0121 movs r1, #1 + 1868 02e0 01FA03F2 lsl r2, r1, r3 + 1869 .LVL166: +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1870 .loc 1 1157 13 is_stmt 1 view .LVU547 +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1871 .loc 1 1157 37 is_stmt 0 view .LVU548 + 1872 02e4 D5F83438 ldr r3, [r5, #2100] + 1873 02e8 23EA0203 bic r3, r3, r2 + 1874 02ec C5F83438 str r3, [r5, #2100] +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1875 .loc 1 1159 13 is_stmt 1 view .LVU549 + 1876 02f0 05EB4813 add r3, r5, r8, lsl #5 + 1877 02f4 C3F80819 str r1, [r3, #2312] +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1878 .loc 1 1161 13 view .LVU550 +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1879 .loc 1 1161 27 is_stmt 0 view .LVU551 + 1880 02f8 2369 ldr r3, [r4, #16] +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1881 .loc 1 1161 16 view .LVU552 + 1882 02fa 8B42 cmp r3, r1 + 1883 02fc B3D1 bne .L104 +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1884 .loc 1 1163 15 is_stmt 1 view .LVU553 +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1885 .loc 1 1163 65 is_stmt 0 view .LVU554 + 1886 02fe C8EBC803 rsb r3, r8, r8, lsl #3 + 1887 0302 04EB8303 add r3, r4, r3, lsl #2 + 1888 0306 596C ldr r1, [r3, #68] +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1889 .loc 1 1163 44 view .LVU555 + 1890 0308 9A6C ldr r2, [r3, #72] + 1891 .LVL167: +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1892 .loc 1 1163 44 view .LVU556 + 1893 030a 0A44 add r2, r2, r1 + ARM GAS /tmp/ccjyOkyX.s page 80 + + + 1894 030c 9A64 str r2, [r3, #72] + 1895 .LVL168: +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1896 .loc 1 1166 15 is_stmt 1 view .LVU557 +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1897 .loc 1 1166 18 is_stmt 0 view .LVU558 + 1898 030e B8F1000F cmp r8, #0 + 1899 0312 A8D1 bne .L104 +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1900 .loc 1 1166 55 discriminator 1 view .LVU559 + 1901 0314 C8EBC803 rsb r3, r8, r8, lsl #3 + 1902 0318 04EB8303 add r3, r4, r3, lsl #2 + 1903 031c 1B6D ldr r3, [r3, #80] +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1904 .loc 1 1166 33 discriminator 1 view .LVU560 + 1905 031e 002B cmp r3, #0 + 1906 0320 A1D1 bne .L104 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1907 .loc 1 1169 17 is_stmt 1 view .LVU561 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1908 .loc 1 1169 23 is_stmt 0 view .LVU562 + 1909 0322 04F57172 add r2, r4, #964 + 1910 0326 0121 movs r1, #1 + 1911 .LVL169: +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1912 .loc 1 1169 23 view .LVU563 + 1913 0328 2068 ldr r0, [r4] + 1914 .LVL170: +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1915 .loc 1 1169 23 view .LVU564 + 1916 032a FFF7FEFF bl USB_EP0_OutStart + 1917 .LVL171: +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1918 .loc 1 1169 23 view .LVU565 + 1919 032e 9AE7 b .L104 + 1920 .LVL172: + 1921 .L145: +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1922 .loc 1 1197 13 is_stmt 1 view .LVU566 +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1923 .loc 1 1197 19 is_stmt 0 view .LVU567 + 1924 0330 4146 mov r1, r8 + 1925 0332 2046 mov r0, r4 + 1926 0334 FFF7FEFF bl PCD_WriteEmptyTxFifo + 1927 .LVL173: + 1928 0338 BCE7 b .L102 + 1929 .LVL174: + 1930 .L134: +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1931 .loc 1 1209 7 is_stmt 1 view .LVU568 +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1932 .loc 1 1209 25 is_stmt 0 view .LVU569 + 1933 033a D5F80438 ldr r3, [r5, #2052] + 1934 033e 23F00103 bic r3, r3, #1 + 1935 0342 C5F80438 str r3, [r5, #2052] +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1936 .loc 1 1211 7 is_stmt 1 view .LVU570 + ARM GAS /tmp/ccjyOkyX.s page 81 + + +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1937 .loc 1 1211 15 is_stmt 0 view .LVU571 + 1938 0346 94F8F433 ldrb r3, [r4, #1012] @ zero_extendqisi2 +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1939 .loc 1 1211 10 view .LVU572 + 1940 034a 012B cmp r3, #1 + 1941 034c 08D0 beq .L146 +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 1942 .loc 1 1226 9 is_stmt 1 view .LVU573 + 1943 034e 2046 mov r0, r4 + 1944 0350 FFF7FEFF bl HAL_PCD_ResumeCallback + 1945 .LVL175: + 1946 .L112: +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 1947 .loc 1 1230 7 view .LVU574 + 1948 0354 2268 ldr r2, [r4] + 1949 0356 5369 ldr r3, [r2, #20] + 1950 0358 03F00043 and r3, r3, #-2147483648 + 1951 035c 5361 str r3, [r2, #20] + 1952 035e 99E6 b .L110 + 1953 .L146: +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1954 .loc 1 1213 9 view .LVU575 +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1955 .loc 1 1213 25 is_stmt 0 view .LVU576 + 1956 0360 0021 movs r1, #0 + 1957 0362 84F8F413 strb r1, [r4, #1012] +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 1958 .loc 1 1218 9 is_stmt 1 view .LVU577 + 1959 0366 2046 mov r0, r4 + 1960 0368 FFF7FEFF bl HAL_PCDEx_LPM_Callback + 1961 .LVL176: + 1962 036c F2E7 b .L112 + 1963 .L135: +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 1964 .loc 1 1241 9 view .LVU578 + 1965 036e 2046 mov r0, r4 + 1966 0370 FFF7FEFF bl HAL_PCD_SuspendCallback + 1967 .LVL177: + 1968 0374 9AE6 b .L114 + 1969 .L116: +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 1970 .loc 1 1268 9 view .LVU579 + 1971 0376 2046 mov r0, r4 + 1972 0378 FFF7FEFF bl HAL_PCD_SuspendCallback + 1973 .LVL178: + 1974 037c B7E6 b .L115 + 1975 .L136: +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + 1976 .loc 1 1276 7 view .LVU580 +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + 1977 .loc 1 1276 25 is_stmt 0 view .LVU581 + 1978 037e 05F50067 add r7, r5, #2048 + 1979 0382 7B68 ldr r3, [r7, #4] + 1980 0384 23F00103 bic r3, r3, #1 + 1981 0388 7B60 str r3, [r7, #4] +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 82 + + + 1982 .loc 1 1277 7 is_stmt 1 view .LVU582 +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 1983 .loc 1 1277 13 is_stmt 0 view .LVU583 + 1984 038a 1021 movs r1, #16 + 1985 038c 2068 ldr r0, [r4] + 1986 038e FFF7FEFF bl USB_FlushTxFifo + 1987 .LVL179: +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1988 .loc 1 1279 7 is_stmt 1 view .LVU584 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 1989 .loc 1 1279 7 is_stmt 0 view .LVU585 + 1990 0392 20E0 b .L118 + 1991 .LVL180: + 1992 .L119: +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + 1993 .loc 1 1281 9 is_stmt 1 discriminator 3 view .LVU586 + 1994 0394 05EB4613 add r3, r5, r6, lsl #5 +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + 1995 .loc 1 1281 31 is_stmt 0 discriminator 3 view .LVU587 + 1996 0398 4FF67F31 movw r1, #64383 + 1997 039c C3F80819 str r1, [r3, #2312] +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + 1998 .loc 1 1282 9 is_stmt 1 discriminator 3 view .LVU588 +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + 1999 .loc 1 1282 31 is_stmt 0 discriminator 3 view .LVU589 + 2000 03a0 D3F80029 ldr r2, [r3, #2304] + 2001 03a4 22F40012 bic r2, r2, #2097152 + 2002 03a8 C3F80029 str r2, [r3, #2304] +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 2003 .loc 1 1283 9 is_stmt 1 discriminator 3 view .LVU590 +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 2004 .loc 1 1283 31 is_stmt 0 discriminator 3 view .LVU591 + 2005 03ac D3F80029 ldr r2, [r3, #2304] + 2006 03b0 42F00062 orr r2, r2, #134217728 + 2007 03b4 C3F80029 str r2, [r3, #2304] +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + 2008 .loc 1 1284 9 is_stmt 1 discriminator 3 view .LVU592 +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + 2009 .loc 1 1284 32 is_stmt 0 discriminator 3 view .LVU593 + 2010 03b8 C3F8081B str r1, [r3, #2824] +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + 2011 .loc 1 1285 9 is_stmt 1 discriminator 3 view .LVU594 +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + 2012 .loc 1 1285 32 is_stmt 0 discriminator 3 view .LVU595 + 2013 03bc D3F8002B ldr r2, [r3, #2816] + 2014 03c0 22F40012 bic r2, r2, #2097152 + 2015 03c4 C3F8002B str r2, [r3, #2816] +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2016 .loc 1 1286 9 is_stmt 1 discriminator 3 view .LVU596 +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2017 .loc 1 1286 32 is_stmt 0 discriminator 3 view .LVU597 + 2018 03c8 D3F8002B ldr r2, [r3, #2816] + 2019 03cc 42F00062 orr r2, r2, #134217728 + 2020 03d0 C3F8002B str r2, [r3, #2816] +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2021 .loc 1 1279 50 is_stmt 1 discriminator 3 view .LVU598 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 83 + + + 2022 .loc 1 1279 51 is_stmt 0 discriminator 3 view .LVU599 + 2023 03d4 0136 adds r6, r6, #1 + 2024 .LVL181: + 2025 .L118: +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2026 .loc 1 1279 20 is_stmt 1 discriminator 1 view .LVU600 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2027 .loc 1 1279 34 is_stmt 0 discriminator 1 view .LVU601 + 2028 03d6 6368 ldr r3, [r4, #4] +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2029 .loc 1 1279 7 discriminator 1 view .LVU602 + 2030 03d8 B342 cmp r3, r6 + 2031 03da DBD8 bhi .L119 +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2032 .loc 1 1288 7 is_stmt 1 view .LVU603 +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2033 .loc 1 1288 29 is_stmt 0 view .LVU604 + 2034 03dc FB69 ldr r3, [r7, #28] + 2035 03de 43F00113 orr r3, r3, #65537 + 2036 03e2 FB61 str r3, [r7, #28] +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2037 .loc 1 1290 7 is_stmt 1 view .LVU605 +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2038 .loc 1 1290 21 is_stmt 0 view .LVU606 + 2039 03e4 236B ldr r3, [r4, #48] +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2040 .loc 1 1290 10 view .LVU607 + 2041 03e6 DBB1 cbz r3, .L120 +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_XFRCM | + 2042 .loc 1 1292 9 is_stmt 1 view .LVU608 +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_XFRCM | + 2043 .loc 1 1292 33 is_stmt 0 view .LVU609 + 2044 03e8 D7F88430 ldr r3, [r7, #132] + 2045 03ec 43F00B03 orr r3, r3, #11 + 2046 03f0 C7F88430 str r3, [r7, #132] +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_XFRCM | + 2047 .loc 1 1296 9 is_stmt 1 view .LVU610 +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_XFRCM | + 2048 .loc 1 1296 32 is_stmt 0 view .LVU611 + 2049 03f4 7B6C ldr r3, [r7, #68] + 2050 03f6 43F00B03 orr r3, r3, #11 + 2051 03fa 7B64 str r3, [r7, #68] + 2052 .L121: +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2053 .loc 1 1314 7 is_stmt 1 view .LVU612 +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2054 .loc 1 1314 25 is_stmt 0 view .LVU613 + 2055 03fc D5F80038 ldr r3, [r5, #2048] + 2056 0400 23F4FE63 bic r3, r3, #2032 + 2057 0404 C5F80038 str r3, [r5, #2048] +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint8_t *)hpcd->Setup); + 2058 .loc 1 1317 7 is_stmt 1 view .LVU614 +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (uint8_t *)hpcd->Setup); + 2059 .loc 1 1317 13 is_stmt 0 view .LVU615 + 2060 0408 04F57172 add r2, r4, #964 + 2061 040c 217C ldrb r1, [r4, #16] @ zero_extendqisi2 + 2062 040e 2068 ldr r0, [r4] + ARM GAS /tmp/ccjyOkyX.s page 84 + + + 2063 0410 FFF7FEFF bl USB_EP0_OutStart + 2064 .LVL182: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2065 .loc 1 1320 7 is_stmt 1 view .LVU616 + 2066 0414 2268 ldr r2, [r4] + 2067 0416 5369 ldr r3, [r2, #20] + 2068 0418 03F48053 and r3, r3, #4096 + 2069 041c 5361 str r3, [r2, #20] + 2070 041e 6DE6 b .L117 + 2071 .L120: +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_XFRCM | + 2072 .loc 1 1302 9 view .LVU617 +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DOEPMSK_XFRCM | + 2073 .loc 1 1302 30 is_stmt 0 view .LVU618 + 2074 0420 7A69 ldr r2, [r7, #20] + 2075 0422 42F22B03 movw r3, #8235 + 2076 0426 1343 orrs r3, r3, r2 + 2077 0428 7B61 str r3, [r7, #20] +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_XFRCM | + 2078 .loc 1 1308 9 is_stmt 1 view .LVU619 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** USB_OTG_DIEPMSK_XFRCM | + 2079 .loc 1 1308 30 is_stmt 0 view .LVU620 + 2080 042a 3B69 ldr r3, [r7, #16] + 2081 042c 43F00B03 orr r3, r3, #11 + 2082 0430 3B61 str r3, [r7, #16] + 2083 0432 E3E7 b .L121 + 2084 .LVL183: + 2085 .L137: +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + 2086 .loc 1 1326 7 is_stmt 1 view .LVU621 +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + 2087 .loc 1 1326 13 is_stmt 0 view .LVU622 + 2088 0434 2068 ldr r0, [r4] + 2089 0436 FFF7FEFF bl USB_ActivateSetup + 2090 .LVL184: +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2091 .loc 1 1327 7 is_stmt 1 view .LVU623 +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2092 .loc 1 1327 26 is_stmt 0 view .LVU624 + 2093 043a 2068 ldr r0, [r4] + 2094 043c FFF7FEFF bl USB_GetDevSpeed + 2095 .LVL185: +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2096 .loc 1 1327 24 view .LVU625 + 2097 0440 E060 str r0, [r4, #12] +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_RCC_GetHCLKFreq(), + 2098 .loc 1 1330 7 is_stmt 1 view .LVU626 +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_RCC_GetHCLKFreq(), + 2099 .loc 1 1330 39 is_stmt 0 view .LVU627 + 2100 0442 2568 ldr r5, [r4] + 2101 .LVL186: +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_RCC_GetHCLKFreq(), + 2102 .loc 1 1330 13 view .LVU628 + 2103 0444 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2104 .LVL187: + 2105 0448 0146 mov r1, r0 + 2106 044a 227B ldrb r2, [r4, #12] @ zero_extendqisi2 + ARM GAS /tmp/ccjyOkyX.s page 85 + + + 2107 044c 2846 mov r0, r5 + 2108 044e FFF7FEFF bl USB_SetTurnaroundTime + 2109 .LVL188: +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 2110 .loc 1 1337 7 is_stmt 1 view .LVU629 + 2111 0452 2046 mov r0, r4 + 2112 0454 FFF7FEFF bl HAL_PCD_ResetCallback + 2113 .LVL189: +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2114 .loc 1 1340 7 view .LVU630 + 2115 0458 2268 ldr r2, [r4] + 2116 045a 5369 ldr r3, [r2, #20] + 2117 045c 03F40053 and r3, r3, #8192 + 2118 0460 5361 str r3, [r2, #20] + 2119 0462 52E6 b .L122 + 2120 .L138: +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 2121 .loc 1 1349 7 view .LVU631 + 2122 0464 2046 mov r0, r4 + 2123 0466 FFF7FEFF bl HAL_PCD_SOFCallback + 2124 .LVL190: +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2125 .loc 1 1352 7 view .LVU632 + 2126 046a 2268 ldr r2, [r4] + 2127 046c 5369 ldr r3, [r2, #20] + 2128 046e 03F00803 and r3, r3, #8 + 2129 0472 5361 str r3, [r2, #20] + 2130 0474 50E6 b .L123 + 2131 .L139: +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2132 .loc 1 1360 7 view .LVU633 + 2133 .LVL191: +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 2134 .loc 1 1365 7 view .LVU634 + 2135 0476 0021 movs r1, #0 + 2136 0478 2046 mov r0, r4 + 2137 047a FFF7FEFF bl HAL_PCD_ISOINIncompleteCallback + 2138 .LVL192: +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2139 .loc 1 1368 7 view .LVU635 + 2140 047e 2268 ldr r2, [r4] + 2141 0480 5369 ldr r3, [r2, #20] + 2142 0482 03F48013 and r3, r3, #1048576 + 2143 0486 5361 str r3, [r2, #20] + 2144 0488 4DE6 b .L124 + 2145 .LVL193: + 2146 .L140: +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2147 .loc 1 1376 7 view .LVU636 +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 2148 .loc 1 1381 7 view .LVU637 + 2149 048a 0021 movs r1, #0 + 2150 048c 2046 mov r0, r4 + 2151 048e FFF7FEFF bl HAL_PCD_ISOOUTIncompleteCallback + 2152 .LVL194: +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2153 .loc 1 1384 7 view .LVU638 + ARM GAS /tmp/ccjyOkyX.s page 86 + + + 2154 0492 2268 ldr r2, [r4] + 2155 0494 5369 ldr r3, [r2, #20] + 2156 0496 03F40013 and r3, r3, #2097152 + 2157 049a 5361 str r3, [r2, #20] + 2158 049c 4AE6 b .L125 + 2159 .LVL195: + 2160 .L141: +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 2161 .loc 1 1393 7 view .LVU639 + 2162 049e 2046 mov r0, r4 + 2163 04a0 FFF7FEFF bl HAL_PCD_ConnectCallback + 2164 .LVL196: +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2165 .loc 1 1396 7 view .LVU640 + 2166 04a4 2268 ldr r2, [r4] + 2167 04a6 5369 ldr r3, [r2, #20] + 2168 04a8 03F08043 and r3, r3, #1073741824 + 2169 04ac 5361 str r3, [r2, #20] + 2170 04ae 48E6 b .L126 + 2171 .LVL197: + 2172 .L142: +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 2173 .loc 1 1409 9 view .LVU641 + 2174 04b0 2046 mov r0, r4 + 2175 04b2 FFF7FEFF bl HAL_PCD_DisconnectCallback + 2176 .LVL198: + 2177 04b6 51E6 b .L127 + 2178 .cfi_endproc + 2179 .LFE147: + 2181 .section .text.HAL_PCD_DevConnect,"ax",%progbits + 2182 .align 1 + 2183 .global HAL_PCD_DevConnect + 2184 .syntax unified + 2185 .thumb + 2186 .thumb_func + 2187 .fpu fpv5-d16 + 2189 HAL_PCD_DevConnect: + 2190 .LVL199: + 2191 .LFB159: +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2192 .loc 1 1616 1 view -0 + 2193 .cfi_startproc + 2194 @ args = 0, pretend = 0, frame = 0 + 2195 @ frame_needed = 0, uses_anonymous_args = 0 +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 2196 .loc 1 1618 3 view .LVU643 +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 2197 .loc 1 1618 26 is_stmt 0 view .LVU644 + 2198 0000 0268 ldr r2, [r0] + 2199 .LVL200: +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2200 .loc 1 1621 3 is_stmt 1 view .LVU645 +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2201 .loc 1 1621 3 view .LVU646 + 2202 0002 90F8BC33 ldrb r3, [r0, #956] @ zero_extendqisi2 + 2203 0006 012B cmp r3, #1 + 2204 0008 16D0 beq .L150 + ARM GAS /tmp/ccjyOkyX.s page 87 + + +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2205 .loc 1 1616 1 is_stmt 0 discriminator 2 view .LVU647 + 2206 000a 10B5 push {r4, lr} + 2207 .LCFI16: + 2208 .cfi_def_cfa_offset 8 + 2209 .cfi_offset 4, -8 + 2210 .cfi_offset 14, -4 + 2211 000c 0446 mov r4, r0 +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2212 .loc 1 1621 3 is_stmt 1 discriminator 2 view .LVU648 + 2213 000e 0123 movs r3, #1 + 2214 0010 80F8BC33 strb r3, [r0, #956] +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2215 .loc 1 1621 3 discriminator 2 view .LVU649 +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 2216 .loc 1 1623 3 discriminator 2 view .LVU650 +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 2217 .loc 1 1623 18 is_stmt 0 discriminator 2 view .LVU651 + 2218 0014 836A ldr r3, [r0, #40] +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 2219 .loc 1 1623 6 discriminator 2 view .LVU652 + 2220 0016 012B cmp r3, #1 + 2221 0018 06D0 beq .L155 + 2222 .L149: +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2223 .loc 1 1630 3 is_stmt 1 view .LVU653 +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2224 .loc 1 1630 9 is_stmt 0 view .LVU654 + 2225 001a 2068 ldr r0, [r4] + 2226 .LVL201: +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2227 .loc 1 1630 9 view .LVU655 + 2228 001c FFF7FEFF bl USB_DevConnect + 2229 .LVL202: +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2230 .loc 1 1631 3 is_stmt 1 view .LVU656 +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2231 .loc 1 1631 3 view .LVU657 + 2232 0020 0020 movs r0, #0 + 2233 0022 84F8BC03 strb r0, [r4, #956] +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2234 .loc 1 1631 3 view .LVU658 +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2235 .loc 1 1632 3 view .LVU659 +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2236 .loc 1 1633 1 is_stmt 0 view .LVU660 + 2237 0026 10BD pop {r4, pc} + 2238 .LVL203: + 2239 .L155: +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2240 .loc 1 1624 18 discriminator 1 view .LVU661 + 2241 0028 8369 ldr r3, [r0, #24] +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + 2242 .loc 1 1623 50 discriminator 1 view .LVU662 + 2243 002a 012B cmp r3, #1 + 2244 002c F5D0 beq .L149 +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 88 + + + 2245 .loc 1 1627 5 is_stmt 1 view .LVU663 +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2246 .loc 1 1627 17 is_stmt 0 view .LVU664 + 2247 002e 936B ldr r3, [r2, #56] + 2248 0030 43F48033 orr r3, r3, #65536 + 2249 0034 9363 str r3, [r2, #56] + 2250 0036 F0E7 b .L149 + 2251 .L150: + 2252 .LCFI17: + 2253 .cfi_def_cfa_offset 0 + 2254 .cfi_restore 4 + 2255 .cfi_restore 14 +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 2256 .loc 1 1621 3 view .LVU665 + 2257 0038 0220 movs r0, #2 + 2258 .LVL204: +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2259 .loc 1 1633 1 view .LVU666 + 2260 003a 7047 bx lr + 2261 .cfi_endproc + 2262 .LFE159: + 2264 .section .text.HAL_PCD_DevDisconnect,"ax",%progbits + 2265 .align 1 + 2266 .global HAL_PCD_DevDisconnect + 2267 .syntax unified + 2268 .thumb + 2269 .thumb_func + 2270 .fpu fpv5-d16 + 2272 HAL_PCD_DevDisconnect: + 2273 .LVL205: + 2274 .LFB160: +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 2275 .loc 1 1641 1 is_stmt 1 view -0 + 2276 .cfi_startproc + 2277 @ args = 0, pretend = 0, frame = 0 + 2278 @ frame_needed = 0, uses_anonymous_args = 0 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); + 2279 .loc 1 1642 3 view .LVU668 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); + 2280 .loc 1 1642 3 view .LVU669 + 2281 0000 90F8BC33 ldrb r3, [r0, #956] @ zero_extendqisi2 + 2282 0004 012B cmp r3, #1 + 2283 0006 0BD0 beq .L158 +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 2284 .loc 1 1641 1 is_stmt 0 discriminator 2 view .LVU670 + 2285 0008 10B5 push {r4, lr} + 2286 .LCFI18: + 2287 .cfi_def_cfa_offset 8 + 2288 .cfi_offset 4, -8 + 2289 .cfi_offset 14, -4 + 2290 000a 0446 mov r4, r0 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); + 2291 .loc 1 1642 3 is_stmt 1 discriminator 2 view .LVU671 + 2292 000c 0123 movs r3, #1 + 2293 000e 80F8BC33 strb r3, [r0, #956] +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); + 2294 .loc 1 1642 3 discriminator 2 view .LVU672 + ARM GAS /tmp/ccjyOkyX.s page 89 + + +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2295 .loc 1 1643 3 discriminator 2 view .LVU673 +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2296 .loc 1 1643 9 is_stmt 0 discriminator 2 view .LVU674 + 2297 0012 0068 ldr r0, [r0] + 2298 .LVL206: +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2299 .loc 1 1643 9 discriminator 2 view .LVU675 + 2300 0014 FFF7FEFF bl USB_DevDisconnect + 2301 .LVL207: +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2302 .loc 1 1644 3 is_stmt 1 discriminator 2 view .LVU676 +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2303 .loc 1 1644 3 discriminator 2 view .LVU677 + 2304 0018 0020 movs r0, #0 + 2305 001a 84F8BC03 strb r0, [r4, #956] +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2306 .loc 1 1644 3 discriminator 2 view .LVU678 +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2307 .loc 1 1645 3 discriminator 2 view .LVU679 +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2308 .loc 1 1646 1 is_stmt 0 discriminator 2 view .LVU680 + 2309 001e 10BD pop {r4, pc} + 2310 .LVL208: + 2311 .L158: + 2312 .LCFI19: + 2313 .cfi_def_cfa_offset 0 + 2314 .cfi_restore 4 + 2315 .cfi_restore 14 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DevDisconnect(hpcd->Instance); + 2316 .loc 1 1642 3 view .LVU681 + 2317 0020 0220 movs r0, #2 + 2318 .LVL209: +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2319 .loc 1 1646 1 view .LVU682 + 2320 0022 7047 bx lr + 2321 .cfi_endproc + 2322 .LFE160: + 2324 .section .text.HAL_PCD_SetAddress,"ax",%progbits + 2325 .align 1 + 2326 .global HAL_PCD_SetAddress + 2327 .syntax unified + 2328 .thumb + 2329 .thumb_func + 2330 .fpu fpv5-d16 + 2332 HAL_PCD_SetAddress: + 2333 .LVL210: + 2334 .LFB161: +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 2335 .loc 1 1655 1 is_stmt 1 view -0 + 2336 .cfi_startproc + 2337 @ args = 0, pretend = 0, frame = 0 + 2338 @ frame_needed = 0, uses_anonymous_args = 0 +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = address; + 2339 .loc 1 1656 3 view .LVU684 +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = address; + 2340 .loc 1 1656 3 view .LVU685 + ARM GAS /tmp/ccjyOkyX.s page 90 + + + 2341 0000 90F8BC33 ldrb r3, [r0, #956] @ zero_extendqisi2 + 2342 0004 012B cmp r3, #1 + 2343 0006 0DD0 beq .L165 +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 2344 .loc 1 1655 1 is_stmt 0 discriminator 2 view .LVU686 + 2345 0008 10B5 push {r4, lr} + 2346 .LCFI20: + 2347 .cfi_def_cfa_offset 8 + 2348 .cfi_offset 4, -8 + 2349 .cfi_offset 14, -4 + 2350 000a 0446 mov r4, r0 +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = address; + 2351 .loc 1 1656 3 is_stmt 1 discriminator 2 view .LVU687 + 2352 000c 0123 movs r3, #1 + 2353 000e 80F8BC33 strb r3, [r0, #956] +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = address; + 2354 .loc 1 1656 3 discriminator 2 view .LVU688 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_SetDevAddress(hpcd->Instance, address); + 2355 .loc 1 1657 3 discriminator 2 view .LVU689 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_SetDevAddress(hpcd->Instance, address); + 2356 .loc 1 1657 21 is_stmt 0 discriminator 2 view .LVU690 + 2357 0012 80F83810 strb r1, [r0, #56] +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2358 .loc 1 1658 3 is_stmt 1 discriminator 2 view .LVU691 +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2359 .loc 1 1658 9 is_stmt 0 discriminator 2 view .LVU692 + 2360 0016 0068 ldr r0, [r0] + 2361 .LVL211: +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2362 .loc 1 1658 9 discriminator 2 view .LVU693 + 2363 0018 FFF7FEFF bl USB_SetDevAddress + 2364 .LVL212: +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2365 .loc 1 1659 3 is_stmt 1 discriminator 2 view .LVU694 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2366 .loc 1 1659 3 discriminator 2 view .LVU695 + 2367 001c 0020 movs r0, #0 + 2368 001e 84F8BC03 strb r0, [r4, #956] +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2369 .loc 1 1659 3 discriminator 2 view .LVU696 +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2370 .loc 1 1660 3 discriminator 2 view .LVU697 +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 2371 .loc 1 1661 1 is_stmt 0 discriminator 2 view .LVU698 + 2372 0022 10BD pop {r4, pc} + 2373 .LVL213: + 2374 .L165: + 2375 .LCFI21: + 2376 .cfi_def_cfa_offset 0 + 2377 .cfi_restore 4 + 2378 .cfi_restore 14 +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** hpcd->USB_Address = address; + 2379 .loc 1 1656 3 view .LVU699 + 2380 0024 0220 movs r0, #2 + 2381 .LVL214: +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 2382 .loc 1 1661 1 view .LVU700 + ARM GAS /tmp/ccjyOkyX.s page 91 + + + 2383 0026 7047 bx lr + 2384 .cfi_endproc + 2385 .LFE161: + 2387 .section .text.HAL_PCD_EP_Open,"ax",%progbits + 2388 .align 1 + 2389 .global HAL_PCD_EP_Open + 2390 .syntax unified + 2391 .thumb + 2392 .thumb_func + 2393 .fpu fpv5-d16 + 2395 HAL_PCD_EP_Open: + 2396 .LVL215: + 2397 .LFB162: +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef ret = HAL_OK; + 2398 .loc 1 1671 1 is_stmt 1 view -0 + 2399 .cfi_startproc + 2400 @ args = 0, pretend = 0, frame = 0 + 2401 @ frame_needed = 0, uses_anonymous_args = 0 +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** HAL_StatusTypeDef ret = HAL_OK; + 2402 .loc 1 1671 1 is_stmt 0 view .LVU702 + 2403 0000 38B5 push {r3, r4, r5, lr} + 2404 .LCFI22: + 2405 .cfi_def_cfa_offset 16 + 2406 .cfi_offset 3, -16 + 2407 .cfi_offset 4, -12 + 2408 .cfi_offset 5, -8 + 2409 .cfi_offset 14, -4 + 2410 0002 0546 mov r5, r0 + 2411 0004 8C46 mov ip, r1 +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2412 .loc 1 1672 3 is_stmt 1 view .LVU703 + 2413 .LVL216: +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2414 .loc 1 1673 3 view .LVU704 +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2415 .loc 1 1675 3 view .LVU705 +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2416 .loc 1 1675 6 is_stmt 0 view .LVU706 + 2417 0006 11F0800F tst r1, #128 + 2418 000a 29D1 bne .L178 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2419 .loc 1 1682 5 is_stmt 1 view .LVU707 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2420 .loc 1 1682 32 is_stmt 0 view .LVU708 + 2421 000c 01F00F0E and lr, r1, #15 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2422 .loc 1 1682 8 view .LVU709 + 2423 0010 CEEBCE04 rsb r4, lr, lr, lsl #3 + 2424 0014 A400 lsls r4, r4, #2 + 2425 0016 04F5FC74 add r4, r4, #504 + 2426 001a 0444 add r4, r4, r0 + 2427 001c 211D adds r1, r4, #4 + 2428 .LVL217: +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2429 .loc 1 1683 5 is_stmt 1 view .LVU710 +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2430 .loc 1 1683 15 is_stmt 0 view .LVU711 + ARM GAS /tmp/ccjyOkyX.s page 92 + + + 2431 001e CEEBCE0E rsb lr, lr, lr, lsl #3 + 2432 0022 00EB8E0E add lr, r0, lr, lsl #2 + 2433 0026 0020 movs r0, #0 + 2434 .LVL218: +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2435 .loc 1 1683 15 view .LVU712 + 2436 0028 8EF8FD01 strb r0, [lr, #509] + 2437 .L172: +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->maxpacket = ep_mps; + 2438 .loc 1 1686 3 is_stmt 1 view .LVU713 +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->maxpacket = ep_mps; + 2439 .loc 1 1686 21 is_stmt 0 view .LVU714 + 2440 002c 0CF00F0C and ip, ip, #15 +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->maxpacket = ep_mps; + 2441 .loc 1 1686 11 view .LVU715 + 2442 0030 81F800C0 strb ip, [r1] +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->type = ep_type; + 2443 .loc 1 1687 3 is_stmt 1 view .LVU716 +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->type = ep_type; + 2444 .loc 1 1687 17 is_stmt 0 view .LVU717 + 2445 0034 8A60 str r2, [r1, #8] +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2446 .loc 1 1688 3 is_stmt 1 view .LVU718 +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2447 .loc 1 1688 12 is_stmt 0 view .LVU719 + 2448 0036 CB70 strb r3, [r1, #3] +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2449 .loc 1 1690 3 is_stmt 1 view .LVU720 +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2450 .loc 1 1690 9 is_stmt 0 view .LVU721 + 2451 0038 4A78 ldrb r2, [r1, #1] @ zero_extendqisi2 + 2452 .LVL219: +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2453 .loc 1 1690 6 view .LVU722 + 2454 003a 0AB1 cbz r2, .L173 +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2455 .loc 1 1693 5 is_stmt 1 view .LVU723 +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2456 .loc 1 1693 21 is_stmt 0 view .LVU724 + 2457 003c A1F806C0 strh ip, [r1, #6] @ movhi + 2458 .L173: +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2459 .loc 1 1696 3 is_stmt 1 view .LVU725 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2460 .loc 1 1696 6 is_stmt 0 view .LVU726 + 2461 0040 022B cmp r3, #2 + 2462 0042 1DD0 beq .L179 + 2463 .LVL220: + 2464 .L174: +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateEndpoint(hpcd->Instance, ep); + 2465 .loc 1 1701 3 is_stmt 1 view .LVU727 +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateEndpoint(hpcd->Instance, ep); + 2466 .loc 1 1701 3 view .LVU728 + 2467 0044 95F8BC33 ldrb r3, [r5, #956] @ zero_extendqisi2 + 2468 0048 012B cmp r3, #1 + 2469 004a 1CD0 beq .L176 +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateEndpoint(hpcd->Instance, ep); + ARM GAS /tmp/ccjyOkyX.s page 93 + + + 2470 .loc 1 1701 3 discriminator 2 view .LVU729 + 2471 004c 0123 movs r3, #1 + 2472 004e 85F8BC33 strb r3, [r5, #956] + 2473 .LVL221: +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateEndpoint(hpcd->Instance, ep); + 2474 .loc 1 1701 3 discriminator 2 view .LVU730 +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2475 .loc 1 1702 3 discriminator 2 view .LVU731 +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2476 .loc 1 1702 9 is_stmt 0 discriminator 2 view .LVU732 + 2477 0052 2868 ldr r0, [r5] + 2478 0054 FFF7FEFF bl USB_ActivateEndpoint + 2479 .LVL222: +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2480 .loc 1 1703 3 is_stmt 1 discriminator 2 view .LVU733 +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2481 .loc 1 1703 3 discriminator 2 view .LVU734 + 2482 0058 0020 movs r0, #0 + 2483 005a 85F8BC03 strb r0, [r5, #956] +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2484 .loc 1 1703 3 discriminator 2 view .LVU735 +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2485 .loc 1 1705 3 discriminator 2 view .LVU736 + 2486 .L175: +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2487 .loc 1 1706 1 is_stmt 0 view .LVU737 + 2488 005e 38BD pop {r3, r4, r5, pc} + 2489 .LVL223: + 2490 .L178: +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2491 .loc 1 1677 5 is_stmt 1 view .LVU738 +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2492 .loc 1 1677 31 is_stmt 0 view .LVU739 + 2493 0060 01F00F00 and r0, r1, #15 + 2494 .LVL224: +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2495 .loc 1 1677 8 view .LVU740 + 2496 0064 C0EBC001 rsb r1, r0, r0, lsl #3 + 2497 .LVL225: +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2498 .loc 1 1677 8 view .LVU741 + 2499 0068 8900 lsls r1, r1, #2 + 2500 006a 3831 adds r1, r1, #56 + 2501 006c 2944 add r1, r1, r5 + 2502 006e 0431 adds r1, r1, #4 + 2503 .LVL226: +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2504 .loc 1 1678 5 is_stmt 1 view .LVU742 +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2505 .loc 1 1678 15 is_stmt 0 view .LVU743 + 2506 0070 C0EBC000 rsb r0, r0, r0, lsl #3 + 2507 0074 05EB8000 add r0, r5, r0, lsl #2 + 2508 0078 0124 movs r4, #1 + 2509 007a 80F83D40 strb r4, [r0, #61] + 2510 007e D5E7 b .L172 + 2511 .LVL227: + 2512 .L179: + ARM GAS /tmp/ccjyOkyX.s page 94 + + +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2513 .loc 1 1698 5 is_stmt 1 view .LVU744 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2514 .loc 1 1698 24 is_stmt 0 view .LVU745 + 2515 0080 0023 movs r3, #0 + 2516 .LVL228: +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2517 .loc 1 1698 24 view .LVU746 + 2518 0082 0B71 strb r3, [r1, #4] + 2519 0084 DEE7 b .L174 + 2520 .L176: +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_ActivateEndpoint(hpcd->Instance, ep); + 2521 .loc 1 1701 3 view .LVU747 + 2522 0086 0220 movs r0, #2 + 2523 0088 E9E7 b .L175 + 2524 .cfi_endproc + 2525 .LFE162: + 2527 .section .text.HAL_PCD_EP_Close,"ax",%progbits + 2528 .align 1 + 2529 .global HAL_PCD_EP_Close + 2530 .syntax unified + 2531 .thumb + 2532 .thumb_func + 2533 .fpu fpv5-d16 + 2535 HAL_PCD_EP_Close: + 2536 .LVL229: + 2537 .LFB163: +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2538 .loc 1 1715 1 is_stmt 1 view -0 + 2539 .cfi_startproc + 2540 @ args = 0, pretend = 0, frame = 0 + 2541 @ frame_needed = 0, uses_anonymous_args = 0 +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2542 .loc 1 1715 1 is_stmt 0 view .LVU749 + 2543 0000 10B5 push {r4, lr} + 2544 .LCFI23: + 2545 .cfi_def_cfa_offset 8 + 2546 .cfi_offset 4, -8 + 2547 .cfi_offset 14, -4 + 2548 0002 0446 mov r4, r0 + 2549 0004 0A46 mov r2, r1 +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2550 .loc 1 1716 3 is_stmt 1 view .LVU750 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2551 .loc 1 1718 3 view .LVU751 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2552 .loc 1 1718 6 is_stmt 0 view .LVU752 + 2553 0006 11F0800F tst r1, #128 + 2554 000a 20D1 bne .L186 +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2555 .loc 1 1725 5 is_stmt 1 view .LVU753 +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2556 .loc 1 1725 32 is_stmt 0 view .LVU754 + 2557 000c 01F00F00 and r0, r1, #15 + 2558 .LVL230: +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2559 .loc 1 1725 8 view .LVU755 + ARM GAS /tmp/ccjyOkyX.s page 95 + + + 2560 0010 C0EBC003 rsb r3, r0, r0, lsl #3 + 2561 0014 9B00 lsls r3, r3, #2 + 2562 0016 03F5FC73 add r3, r3, #504 + 2563 001a 2344 add r3, r3, r4 + 2564 001c 191D adds r1, r3, #4 + 2565 .LVL231: +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2566 .loc 1 1726 5 is_stmt 1 view .LVU756 +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2567 .loc 1 1726 15 is_stmt 0 view .LVU757 + 2568 001e C0EBC000 rsb r0, r0, r0, lsl #3 + 2569 0022 04EB8000 add r0, r4, r0, lsl #2 + 2570 0026 0023 movs r3, #0 + 2571 0028 80F8FD31 strb r3, [r0, #509] + 2572 .L182: +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2573 .loc 1 1728 3 is_stmt 1 view .LVU758 +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2574 .loc 1 1728 23 is_stmt 0 view .LVU759 + 2575 002c 02F00F02 and r2, r2, #15 +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2576 .loc 1 1728 13 view .LVU760 + 2577 0030 0A70 strb r2, [r1] +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + 2578 .loc 1 1730 3 is_stmt 1 view .LVU761 +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + 2579 .loc 1 1730 3 view .LVU762 + 2580 0032 94F8BC33 ldrb r3, [r4, #956] @ zero_extendqisi2 + 2581 0036 012B cmp r3, #1 + 2582 0038 19D0 beq .L184 +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + 2583 .loc 1 1730 3 discriminator 2 view .LVU763 + 2584 003a 0123 movs r3, #1 + 2585 003c 84F8BC33 strb r3, [r4, #956] +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + 2586 .loc 1 1730 3 discriminator 2 view .LVU764 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2587 .loc 1 1731 3 discriminator 2 view .LVU765 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 2588 .loc 1 1731 9 is_stmt 0 discriminator 2 view .LVU766 + 2589 0040 2068 ldr r0, [r4] + 2590 0042 FFF7FEFF bl USB_DeactivateEndpoint + 2591 .LVL232: +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2592 .loc 1 1732 3 is_stmt 1 discriminator 2 view .LVU767 +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2593 .loc 1 1732 3 discriminator 2 view .LVU768 + 2594 0046 0020 movs r0, #0 + 2595 0048 84F8BC03 strb r0, [r4, #956] +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return HAL_OK; + 2596 .loc 1 1732 3 discriminator 2 view .LVU769 +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2597 .loc 1 1733 3 discriminator 2 view .LVU770 + 2598 .L183: +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2599 .loc 1 1734 1 is_stmt 0 view .LVU771 + 2600 004c 10BD pop {r4, pc} + ARM GAS /tmp/ccjyOkyX.s page 96 + + + 2601 .LVL233: + 2602 .L186: +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2603 .loc 1 1720 5 is_stmt 1 view .LVU772 +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2604 .loc 1 1720 31 is_stmt 0 view .LVU773 + 2605 004e 01F00F00 and r0, r1, #15 + 2606 .LVL234: +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2607 .loc 1 1720 8 view .LVU774 + 2608 0052 C0EBC003 rsb r3, r0, r0, lsl #3 + 2609 0056 9B00 lsls r3, r3, #2 + 2610 0058 3833 adds r3, r3, #56 + 2611 005a 2344 add r3, r3, r4 + 2612 005c 191D adds r1, r3, #4 + 2613 .LVL235: +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2614 .loc 1 1721 5 is_stmt 1 view .LVU775 +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2615 .loc 1 1721 15 is_stmt 0 view .LVU776 + 2616 005e C0EBC000 rsb r0, r0, r0, lsl #3 + 2617 0062 04EB8000 add r0, r4, r0, lsl #2 + 2618 0066 0123 movs r3, #1 + 2619 0068 80F83D30 strb r3, [r0, #61] + 2620 006c DEE7 b .L182 + 2621 .L184: +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + 2622 .loc 1 1730 3 view .LVU777 + 2623 006e 0220 movs r0, #2 + 2624 0070 ECE7 b .L183 + 2625 .cfi_endproc + 2626 .LFE163: + 2628 .section .text.HAL_PCD_EP_Receive,"ax",%progbits + 2629 .align 1 + 2630 .global HAL_PCD_EP_Receive + 2631 .syntax unified + 2632 .thumb + 2633 .thumb_func + 2634 .fpu fpv5-d16 + 2636 HAL_PCD_EP_Receive: + 2637 .LVL236: + 2638 .LFB164: +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2639 .loc 1 1746 1 is_stmt 1 view -0 + 2640 .cfi_startproc + 2641 @ args = 0, pretend = 0, frame = 0 + 2642 @ frame_needed = 0, uses_anonymous_args = 0 +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2643 .loc 1 1746 1 is_stmt 0 view .LVU779 + 2644 0000 10B5 push {r4, lr} + 2645 .LCFI24: + 2646 .cfi_def_cfa_offset 8 + 2647 .cfi_offset 4, -8 + 2648 .cfi_offset 14, -4 +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2649 .loc 1 1747 3 is_stmt 1 view .LVU780 +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 97 + + + 2650 .loc 1 1749 3 view .LVU781 + 2651 0002 01F00F04 and r4, r1, #15 +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2652 .loc 1 1749 6 is_stmt 0 view .LVU782 + 2653 0006 C4EBC401 rsb r1, r4, r4, lsl #3 + 2654 .LVL237: +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2655 .loc 1 1749 6 view .LVU783 + 2656 000a 8900 lsls r1, r1, #2 + 2657 000c 01F5FC71 add r1, r1, #504 + 2658 0010 0144 add r1, r1, r0 + 2659 0012 0431 adds r1, r1, #4 + 2660 .LVL238: +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_len = len; + 2661 .loc 1 1752 3 is_stmt 1 view .LVU784 +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_len = len; + 2662 .loc 1 1752 17 is_stmt 0 view .LVU785 + 2663 0014 C4EBC40C rsb ip, r4, r4, lsl #3 + 2664 0018 00EB8C0C add ip, r0, ip, lsl #2 + 2665 001c CCF80822 str r2, [ip, #520] +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count = 0U; + 2666 .loc 1 1753 3 is_stmt 1 view .LVU786 +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count = 0U; + 2667 .loc 1 1753 16 is_stmt 0 view .LVU787 + 2668 0020 CCF81032 str r3, [ip, #528] +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2669 .loc 1 1754 3 is_stmt 1 view .LVU788 +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2670 .loc 1 1754 18 is_stmt 0 view .LVU789 + 2671 0024 0023 movs r3, #0 + 2672 .LVL239: +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2673 .loc 1 1754 18 view .LVU790 + 2674 0026 CCF81432 str r3, [ip, #532] +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 2675 .loc 1 1755 3 is_stmt 1 view .LVU791 +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 2676 .loc 1 1755 13 is_stmt 0 view .LVU792 + 2677 002a 8CF8FD31 strb r3, [ip, #509] +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2678 .loc 1 1756 3 is_stmt 1 view .LVU793 +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2679 .loc 1 1756 11 is_stmt 0 view .LVU794 + 2680 002e 8CF8FC41 strb r4, [ip, #508] +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2681 .loc 1 1758 3 is_stmt 1 view .LVU795 +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2682 .loc 1 1758 17 is_stmt 0 view .LVU796 + 2683 0032 0369 ldr r3, [r0, #16] +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2684 .loc 1 1758 6 view .LVU797 + 2685 0034 012B cmp r3, #1 + 2686 0036 06D0 beq .L192 + 2687 .LVL240: + 2688 .L188: +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2689 .loc 1 1763 3 is_stmt 1 view .LVU798 + ARM GAS /tmp/ccjyOkyX.s page 98 + + +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2690 .loc 1 1763 6 is_stmt 0 view .LVU799 + 2691 0038 64B9 cbnz r4, .L189 +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2692 .loc 1 1765 5 is_stmt 1 view .LVU800 +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2693 .loc 1 1765 11 is_stmt 0 view .LVU801 + 2694 003a DAB2 uxtb r2, r3 + 2695 .LVL241: +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2696 .loc 1 1765 11 view .LVU802 + 2697 003c 0068 ldr r0, [r0] + 2698 .LVL242: +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2699 .loc 1 1765 11 view .LVU803 + 2700 003e FFF7FEFF bl USB_EP0StartXfer + 2701 .LVL243: + 2702 .L190: +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2703 .loc 1 1772 3 is_stmt 1 view .LVU804 +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2704 .loc 1 1773 1 is_stmt 0 view .LVU805 + 2705 0042 0020 movs r0, #0 + 2706 0044 10BD pop {r4, pc} + 2707 .LVL244: + 2708 .L192: +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2709 .loc 1 1760 5 is_stmt 1 view .LVU806 +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2710 .loc 1 1760 18 is_stmt 0 view .LVU807 + 2711 0046 C4EBC40C rsb ip, r4, r4, lsl #3 + 2712 .LVL245: +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2713 .loc 1 1760 18 view .LVU808 + 2714 004a 00EB8C0C add ip, r0, ip, lsl #2 + 2715 004e CCF80C22 str r2, [ip, #524] + 2716 .LVL246: +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2717 .loc 1 1760 18 view .LVU809 + 2718 0052 F1E7 b .L188 + 2719 .L189: +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2720 .loc 1 1769 5 is_stmt 1 view .LVU810 +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2721 .loc 1 1769 11 is_stmt 0 view .LVU811 + 2722 0054 DAB2 uxtb r2, r3 + 2723 .LVL247: +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2724 .loc 1 1769 11 view .LVU812 + 2725 0056 0068 ldr r0, [r0] + 2726 .LVL248: +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2727 .loc 1 1769 11 view .LVU813 + 2728 0058 FFF7FEFF bl USB_EPStartXfer + 2729 .LVL249: +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2730 .loc 1 1769 11 view .LVU814 + ARM GAS /tmp/ccjyOkyX.s page 99 + + + 2731 005c F1E7 b .L190 + 2732 .cfi_endproc + 2733 .LFE164: + 2735 .section .text.HAL_PCD_EP_GetRxCount,"ax",%progbits + 2736 .align 1 + 2737 .global HAL_PCD_EP_GetRxCount + 2738 .syntax unified + 2739 .thumb + 2740 .thumb_func + 2741 .fpu fpv5-d16 + 2743 HAL_PCD_EP_GetRxCount: + 2744 .LVL250: + 2745 .LFB165: +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; + 2746 .loc 1 1782 1 is_stmt 1 view -0 + 2747 .cfi_startproc + 2748 @ args = 0, pretend = 0, frame = 0 + 2749 @ frame_needed = 0, uses_anonymous_args = 0 + 2750 @ link register save eliminated. +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2751 .loc 1 1783 3 view .LVU816 +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2752 .loc 1 1783 31 is_stmt 0 view .LVU817 + 2753 0000 01F00F01 and r1, r1, #15 + 2754 .LVL251: +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2755 .loc 1 1783 45 view .LVU818 + 2756 0004 C1EBC101 rsb r1, r1, r1, lsl #3 + 2757 0008 00EB8101 add r1, r0, r1, lsl #2 +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 2758 .loc 1 1784 1 view .LVU819 + 2759 000c D1F81402 ldr r0, [r1, #532] + 2760 .LVL252: +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** /** + 2761 .loc 1 1784 1 view .LVU820 + 2762 0010 7047 bx lr + 2763 .cfi_endproc + 2764 .LFE165: + 2766 .section .text.HAL_PCD_EP_Transmit,"ax",%progbits + 2767 .align 1 + 2768 .global HAL_PCD_EP_Transmit + 2769 .syntax unified + 2770 .thumb + 2771 .thumb_func + 2772 .fpu fpv5-d16 + 2774 HAL_PCD_EP_Transmit: + 2775 .LVL253: + 2776 .LFB166: +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2777 .loc 1 1794 1 is_stmt 1 view -0 + 2778 .cfi_startproc + 2779 @ args = 0, pretend = 0, frame = 0 + 2780 @ frame_needed = 0, uses_anonymous_args = 0 +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2781 .loc 1 1794 1 is_stmt 0 view .LVU822 + 2782 0000 10B5 push {r4, lr} + 2783 .LCFI25: + ARM GAS /tmp/ccjyOkyX.s page 100 + + + 2784 .cfi_def_cfa_offset 8 + 2785 .cfi_offset 4, -8 + 2786 .cfi_offset 14, -4 +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2787 .loc 1 1795 3 is_stmt 1 view .LVU823 +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2788 .loc 1 1797 3 view .LVU824 + 2789 0002 01F00F04 and r4, r1, #15 +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2790 .loc 1 1797 6 is_stmt 0 view .LVU825 + 2791 0006 C4EBC401 rsb r1, r4, r4, lsl #3 + 2792 .LVL254: +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2793 .loc 1 1797 6 view .LVU826 + 2794 000a 8900 lsls r1, r1, #2 + 2795 000c 3831 adds r1, r1, #56 + 2796 000e 0144 add r1, r1, r0 + 2797 0010 0431 adds r1, r1, #4 + 2798 .LVL255: +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_len = len; + 2799 .loc 1 1800 3 is_stmt 1 view .LVU827 +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_len = len; + 2800 .loc 1 1800 17 is_stmt 0 view .LVU828 + 2801 0012 C4EBC40C rsb ip, r4, r4, lsl #3 + 2802 0016 00EB8C0C add ip, r0, ip, lsl #2 + 2803 001a CCF84820 str r2, [ip, #72] +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count = 0U; + 2804 .loc 1 1801 3 is_stmt 1 view .LVU829 +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->xfer_count = 0U; + 2805 .loc 1 1801 16 is_stmt 0 view .LVU830 + 2806 001e CCF85030 str r3, [ip, #80] +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2807 .loc 1 1802 3 is_stmt 1 view .LVU831 +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2808 .loc 1 1802 18 is_stmt 0 view .LVU832 + 2809 0022 0023 movs r3, #0 + 2810 .LVL256: +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2811 .loc 1 1802 18 view .LVU833 + 2812 0024 CCF85430 str r3, [ip, #84] +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 2813 .loc 1 1803 3 is_stmt 1 view .LVU834 +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 2814 .loc 1 1803 13 is_stmt 0 view .LVU835 + 2815 0028 0123 movs r3, #1 + 2816 002a 8CF83D30 strb r3, [ip, #61] +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2817 .loc 1 1804 3 is_stmt 1 view .LVU836 +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2818 .loc 1 1804 11 is_stmt 0 view .LVU837 + 2819 002e 8CF83C40 strb r4, [ip, #60] +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2820 .loc 1 1806 3 is_stmt 1 view .LVU838 +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2821 .loc 1 1806 17 is_stmt 0 view .LVU839 + 2822 0032 0369 ldr r3, [r0, #16] +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + ARM GAS /tmp/ccjyOkyX.s page 101 + + + 2823 .loc 1 1806 6 view .LVU840 + 2824 0034 012B cmp r3, #1 + 2825 0036 06D0 beq .L199 + 2826 .LVL257: + 2827 .L195: +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2828 .loc 1 1811 3 is_stmt 1 view .LVU841 +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2829 .loc 1 1811 6 is_stmt 0 view .LVU842 + 2830 0038 64B9 cbnz r4, .L196 +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2831 .loc 1 1813 5 is_stmt 1 view .LVU843 +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2832 .loc 1 1813 11 is_stmt 0 view .LVU844 + 2833 003a DAB2 uxtb r2, r3 + 2834 .LVL258: +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2835 .loc 1 1813 11 view .LVU845 + 2836 003c 0068 ldr r0, [r0] + 2837 .LVL259: +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2838 .loc 1 1813 11 view .LVU846 + 2839 003e FFF7FEFF bl USB_EP0StartXfer + 2840 .LVL260: + 2841 .L197: +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2842 .loc 1 1820 3 is_stmt 1 view .LVU847 +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2843 .loc 1 1821 1 is_stmt 0 view .LVU848 + 2844 0042 0020 movs r0, #0 + 2845 0044 10BD pop {r4, pc} + 2846 .LVL261: + 2847 .L199: +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2848 .loc 1 1808 5 is_stmt 1 view .LVU849 +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2849 .loc 1 1808 18 is_stmt 0 view .LVU850 + 2850 0046 C4EBC40C rsb ip, r4, r4, lsl #3 + 2851 .LVL262: +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2852 .loc 1 1808 18 view .LVU851 + 2853 004a 00EB8C0C add ip, r0, ip, lsl #2 + 2854 004e CCF84C20 str r2, [ip, #76] + 2855 .LVL263: +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2856 .loc 1 1808 18 view .LVU852 + 2857 0052 F1E7 b .L195 + 2858 .L196: +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2859 .loc 1 1817 5 is_stmt 1 view .LVU853 +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2860 .loc 1 1817 11 is_stmt 0 view .LVU854 + 2861 0054 DAB2 uxtb r2, r3 + 2862 .LVL264: +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2863 .loc 1 1817 11 view .LVU855 + 2864 0056 0068 ldr r0, [r0] + ARM GAS /tmp/ccjyOkyX.s page 102 + + + 2865 .LVL265: +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2866 .loc 1 1817 11 view .LVU856 + 2867 0058 FFF7FEFF bl USB_EPStartXfer + 2868 .LVL266: +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2869 .loc 1 1817 11 view .LVU857 + 2870 005c F1E7 b .L197 + 2871 .cfi_endproc + 2872 .LFE166: + 2874 .section .text.HAL_PCD_EP_SetStall,"ax",%progbits + 2875 .align 1 + 2876 .global HAL_PCD_EP_SetStall + 2877 .syntax unified + 2878 .thumb + 2879 .thumb_func + 2880 .fpu fpv5-d16 + 2882 HAL_PCD_EP_SetStall: + 2883 .LVL267: + 2884 .LFB167: +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2885 .loc 1 1830 1 is_stmt 1 view -0 + 2886 .cfi_startproc + 2887 @ args = 0, pretend = 0, frame = 0 + 2888 @ frame_needed = 0, uses_anonymous_args = 0 +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 2889 .loc 1 1830 1 is_stmt 0 view .LVU859 + 2890 0000 38B5 push {r3, r4, r5, lr} + 2891 .LCFI26: + 2892 .cfi_def_cfa_offset 16 + 2893 .cfi_offset 3, -16 + 2894 .cfi_offset 4, -12 + 2895 .cfi_offset 5, -8 + 2896 .cfi_offset 14, -4 +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2897 .loc 1 1831 3 is_stmt 1 view .LVU860 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2898 .loc 1 1833 3 view .LVU861 + 2899 0002 01F00F05 and r5, r1, #15 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2900 .loc 1 1833 53 is_stmt 0 view .LVU862 + 2901 0006 4268 ldr r2, [r0, #4] +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2902 .loc 1 1833 6 view .LVU863 + 2903 0008 9542 cmp r5, r2 + 2904 000a 39D8 bhi .L205 + 2905 000c 0446 mov r4, r0 + 2906 000e 0B46 mov r3, r1 +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2907 .loc 1 1838 3 is_stmt 1 view .LVU864 +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2908 .loc 1 1838 6 is_stmt 0 view .LVU865 + 2909 0010 11F0800F tst r1, #128 + 2910 0014 1FD1 bne .L208 +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2911 .loc 1 1845 5 is_stmt 1 view .LVU866 +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + ARM GAS /tmp/ccjyOkyX.s page 103 + + + 2912 .loc 1 1845 8 is_stmt 0 view .LVU867 + 2913 0016 C1EBC101 rsb r1, r1, r1, lsl #3 + 2914 .LVL268: +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 2915 .loc 1 1845 8 view .LVU868 + 2916 001a 8900 lsls r1, r1, #2 + 2917 001c 01F5FC71 add r1, r1, #504 + 2918 0020 0144 add r1, r1, r0 + 2919 0022 0431 adds r1, r1, #4 + 2920 .LVL269: +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2921 .loc 1 1846 5 is_stmt 1 view .LVU869 +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2922 .loc 1 1846 15 is_stmt 0 view .LVU870 + 2923 0024 C3EBC303 rsb r3, r3, r3, lsl #3 + 2924 0028 00EB8303 add r3, r0, r3, lsl #2 + 2925 002c 0022 movs r2, #0 + 2926 002e 83F8FD21 strb r2, [r3, #509] + 2927 .L203: +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 2928 .loc 1 1849 3 is_stmt 1 view .LVU871 +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 2929 .loc 1 1849 16 is_stmt 0 view .LVU872 + 2930 0032 0123 movs r3, #1 + 2931 0034 8B70 strb r3, [r1, #2] +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2932 .loc 1 1850 3 is_stmt 1 view .LVU873 +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2933 .loc 1 1850 11 is_stmt 0 view .LVU874 + 2934 0036 0D70 strb r5, [r1] +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2935 .loc 1 1852 3 is_stmt 1 view .LVU875 +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2936 .loc 1 1852 3 view .LVU876 + 2937 0038 94F8BC33 ldrb r3, [r4, #956] @ zero_extendqisi2 + 2938 003c 012B cmp r3, #1 + 2939 003e 21D0 beq .L206 +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2940 .loc 1 1852 3 discriminator 2 view .LVU877 + 2941 0040 0123 movs r3, #1 + 2942 0042 84F8BC33 strb r3, [r4, #956] +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2943 .loc 1 1852 3 discriminator 2 view .LVU878 +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & EP_ADDR_MSK) == 0U) + 2944 .loc 1 1854 3 discriminator 2 view .LVU879 +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & EP_ADDR_MSK) == 0U) + 2945 .loc 1 1854 9 is_stmt 0 discriminator 2 view .LVU880 + 2946 0046 2068 ldr r0, [r4] + 2947 .LVL270: +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** if ((ep_addr & EP_ADDR_MSK) == 0U) + 2948 .loc 1 1854 9 discriminator 2 view .LVU881 + 2949 0048 FFF7FEFF bl USB_EPSetStall + 2950 .LVL271: +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2951 .loc 1 1855 3 is_stmt 1 discriminator 2 view .LVU882 +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 2952 .loc 1 1855 6 is_stmt 0 discriminator 2 view .LVU883 + ARM GAS /tmp/ccjyOkyX.s page 104 + + + 2953 004c 8DB1 cbz r5, .L209 + 2954 .L204: +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2955 .loc 1 1859 3 is_stmt 1 view .LVU884 +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2956 .loc 1 1859 3 view .LVU885 + 2957 004e 0020 movs r0, #0 + 2958 0050 84F8BC03 strb r0, [r4, #956] +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2959 .loc 1 1859 3 view .LVU886 +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2960 .loc 1 1861 3 view .LVU887 + 2961 .LVL272: + 2962 .L201: +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 2963 .loc 1 1862 1 is_stmt 0 view .LVU888 + 2964 0054 38BD pop {r3, r4, r5, pc} + 2965 .LVL273: + 2966 .L208: +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2967 .loc 1 1840 5 is_stmt 1 view .LVU889 +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2968 .loc 1 1840 8 is_stmt 0 view .LVU890 + 2969 0056 C5EBC501 rsb r1, r5, r5, lsl #3 + 2970 .LVL274: +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 2971 .loc 1 1840 8 view .LVU891 + 2972 005a 8900 lsls r1, r1, #2 + 2973 005c 3831 adds r1, r1, #56 + 2974 005e 0144 add r1, r1, r0 + 2975 0060 0431 adds r1, r1, #4 + 2976 .LVL275: +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2977 .loc 1 1841 5 is_stmt 1 view .LVU892 +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2978 .loc 1 1841 15 is_stmt 0 view .LVU893 + 2979 0062 C5EBC503 rsb r3, r5, r5, lsl #3 + 2980 0066 00EB8303 add r3, r0, r3, lsl #2 + 2981 006a 0122 movs r2, #1 + 2982 006c 83F83D20 strb r2, [r3, #61] + 2983 0070 DFE7 b .L203 + 2984 .LVL276: + 2985 .L209: +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2986 .loc 1 1857 5 is_stmt 1 view .LVU894 +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2987 .loc 1 1857 11 is_stmt 0 view .LVU895 + 2988 0072 04F57172 add r2, r4, #964 + 2989 0076 217C ldrb r1, [r4, #16] @ zero_extendqisi2 + 2990 0078 2068 ldr r0, [r4] + 2991 007a FFF7FEFF bl USB_EP0_OutStart + 2992 .LVL277: + 2993 007e E6E7 b .L204 + 2994 .LVL278: + 2995 .L205: +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2996 .loc 1 1835 12 view .LVU896 + ARM GAS /tmp/ccjyOkyX.s page 105 + + + 2997 0080 0120 movs r0, #1 + 2998 .LVL279: +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 2999 .loc 1 1835 12 view .LVU897 + 3000 0082 E7E7 b .L201 + 3001 .LVL280: + 3002 .L206: +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3003 .loc 1 1852 3 view .LVU898 + 3004 0084 0220 movs r0, #2 + 3005 .LVL281: +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3006 .loc 1 1852 3 view .LVU899 + 3007 0086 E5E7 b .L201 + 3008 .cfi_endproc + 3009 .LFE167: + 3011 .section .text.HAL_PCD_EP_ClrStall,"ax",%progbits + 3012 .align 1 + 3013 .global HAL_PCD_EP_ClrStall + 3014 .syntax unified + 3015 .thumb + 3016 .thumb_func + 3017 .fpu fpv5-d16 + 3019 HAL_PCD_EP_ClrStall: + 3020 .LVL282: + 3021 .LFB168: +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 3022 .loc 1 1871 1 is_stmt 1 view -0 + 3023 .cfi_startproc + 3024 @ args = 0, pretend = 0, frame = 0 + 3025 @ frame_needed = 0, uses_anonymous_args = 0 +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3026 .loc 1 1872 3 view .LVU901 +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3027 .loc 1 1874 3 view .LVU902 + 3028 0000 01F00F03 and r3, r1, #15 +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3029 .loc 1 1874 47 is_stmt 0 view .LVU903 + 3030 0004 4268 ldr r2, [r0, #4] +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3031 .loc 1 1874 6 view .LVU904 + 3032 0006 9342 cmp r3, r2 + 3033 0008 31D8 bhi .L214 +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** PCD_EPTypeDef *ep; + 3034 .loc 1 1871 1 view .LVU905 + 3035 000a 10B5 push {r4, lr} + 3036 .LCFI27: + 3037 .cfi_def_cfa_offset 8 + 3038 .cfi_offset 4, -8 + 3039 .cfi_offset 14, -4 + 3040 000c 0446 mov r4, r0 +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3041 .loc 1 1879 3 is_stmt 1 view .LVU906 +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3042 .loc 1 1879 6 is_stmt 0 view .LVU907 + 3043 000e 11F0800F tst r1, #128 + 3044 0012 1ED1 bne .L220 + ARM GAS /tmp/ccjyOkyX.s page 106 + + +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 3045 .loc 1 1886 5 is_stmt 1 view .LVU908 +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 3046 .loc 1 1886 8 is_stmt 0 view .LVU909 + 3047 0014 C3EBC301 rsb r1, r3, r3, lsl #3 + 3048 .LVL283: +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 0U; + 3049 .loc 1 1886 8 view .LVU910 + 3050 0018 8900 lsls r1, r1, #2 + 3051 001a 01F5FC71 add r1, r1, #504 + 3052 001e 0144 add r1, r1, r0 + 3053 0020 0431 adds r1, r1, #4 + 3054 .LVL284: +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3055 .loc 1 1887 5 is_stmt 1 view .LVU911 +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3056 .loc 1 1887 15 is_stmt 0 view .LVU912 + 3057 0022 C3EBC302 rsb r2, r3, r3, lsl #3 + 3058 0026 00EB8202 add r2, r0, r2, lsl #2 + 3059 002a 0020 movs r0, #0 + 3060 .LVL285: +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3061 .loc 1 1887 15 view .LVU913 + 3062 002c 82F8FD01 strb r0, [r2, #509] + 3063 .L213: +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 3064 .loc 1 1890 3 is_stmt 1 view .LVU914 +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->num = ep_addr & EP_ADDR_MSK; + 3065 .loc 1 1890 16 is_stmt 0 view .LVU915 + 3066 0030 0022 movs r2, #0 + 3067 0032 8A70 strb r2, [r1, #2] +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3068 .loc 1 1891 3 is_stmt 1 view .LVU916 +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3069 .loc 1 1891 11 is_stmt 0 view .LVU917 + 3070 0034 0B70 strb r3, [r1] +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPClearStall(hpcd->Instance, ep); + 3071 .loc 1 1893 3 is_stmt 1 view .LVU918 +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPClearStall(hpcd->Instance, ep); + 3072 .loc 1 1893 3 view .LVU919 + 3073 0036 94F8BC33 ldrb r3, [r4, #956] @ zero_extendqisi2 + 3074 003a 012B cmp r3, #1 + 3075 003c 19D0 beq .L215 +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPClearStall(hpcd->Instance, ep); + 3076 .loc 1 1893 3 discriminator 2 view .LVU920 + 3077 003e 0123 movs r3, #1 + 3078 0040 84F8BC33 strb r3, [r4, #956] +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPClearStall(hpcd->Instance, ep); + 3079 .loc 1 1893 3 discriminator 2 view .LVU921 +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 3080 .loc 1 1894 3 discriminator 2 view .LVU922 +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_UNLOCK(hpcd); + 3081 .loc 1 1894 9 is_stmt 0 discriminator 2 view .LVU923 + 3082 0044 2068 ldr r0, [r4] + 3083 0046 FFF7FEFF bl USB_EPClearStall + 3084 .LVL286: +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + ARM GAS /tmp/ccjyOkyX.s page 107 + + + 3085 .loc 1 1895 3 is_stmt 1 discriminator 2 view .LVU924 +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3086 .loc 1 1895 3 discriminator 2 view .LVU925 + 3087 004a 0020 movs r0, #0 + 3088 004c 84F8BC03 strb r0, [r4, #956] +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3089 .loc 1 1895 3 discriminator 2 view .LVU926 +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3090 .loc 1 1897 3 discriminator 2 view .LVU927 + 3091 .L211: +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3092 .loc 1 1898 1 is_stmt 0 view .LVU928 + 3093 0050 10BD pop {r4, pc} + 3094 .LVL287: + 3095 .L220: +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 3096 .loc 1 1881 5 is_stmt 1 view .LVU929 +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 3097 .loc 1 1881 8 is_stmt 0 view .LVU930 + 3098 0052 C3EBC301 rsb r1, r3, r3, lsl #3 + 3099 .LVL288: +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** ep->is_in = 1U; + 3100 .loc 1 1881 8 view .LVU931 + 3101 0056 8900 lsls r1, r1, #2 + 3102 0058 3831 adds r1, r1, #56 + 3103 005a 0144 add r1, r1, r0 + 3104 005c 0431 adds r1, r1, #4 + 3105 .LVL289: +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3106 .loc 1 1882 5 is_stmt 1 view .LVU932 +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3107 .loc 1 1882 15 is_stmt 0 view .LVU933 + 3108 005e C3EBC302 rsb r2, r3, r3, lsl #3 + 3109 0062 00EB8202 add r2, r0, r2, lsl #2 + 3110 0066 0120 movs r0, #1 + 3111 .LVL290: +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3112 .loc 1 1882 15 view .LVU934 + 3113 0068 82F83D00 strb r0, [r2, #61] + 3114 006c E0E7 b .L213 + 3115 .LVL291: + 3116 .L214: + 3117 .LCFI28: + 3118 .cfi_def_cfa_offset 0 + 3119 .cfi_restore 4 + 3120 .cfi_restore 14 +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3121 .loc 1 1876 12 view .LVU935 + 3122 006e 0120 movs r0, #1 + 3123 .LVL292: +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3124 .loc 1 1898 1 view .LVU936 + 3125 0070 7047 bx lr + 3126 .LVL293: + 3127 .L215: + 3128 .LCFI29: + 3129 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccjyOkyX.s page 108 + + + 3130 .cfi_offset 4, -8 + 3131 .cfi_offset 14, -4 +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** (void)USB_EPClearStall(hpcd->Instance, ep); + 3132 .loc 1 1893 3 view .LVU937 + 3133 0072 0220 movs r0, #2 + 3134 0074 ECE7 b .L211 + 3135 .cfi_endproc + 3136 .LFE168: + 3138 .section .text.HAL_PCD_EP_Flush,"ax",%progbits + 3139 .align 1 + 3140 .global HAL_PCD_EP_Flush + 3141 .syntax unified + 3142 .thumb + 3143 .thumb_func + 3144 .fpu fpv5-d16 + 3146 HAL_PCD_EP_Flush: + 3147 .LVL294: + 3148 .LFB169: +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 3149 .loc 1 1907 1 is_stmt 1 view -0 + 3150 .cfi_startproc + 3151 @ args = 0, pretend = 0, frame = 0 + 3152 @ frame_needed = 0, uses_anonymous_args = 0 +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3153 .loc 1 1908 3 view .LVU939 +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3154 .loc 1 1908 3 view .LVU940 + 3155 0000 90F8BC33 ldrb r3, [r0, #956] @ zero_extendqisi2 + 3156 0004 012B cmp r3, #1 + 3157 0006 14D0 beq .L225 +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** __HAL_LOCK(hpcd); + 3158 .loc 1 1907 1 is_stmt 0 discriminator 2 view .LVU941 + 3159 0008 10B5 push {r4, lr} + 3160 .LCFI30: + 3161 .cfi_def_cfa_offset 8 + 3162 .cfi_offset 4, -8 + 3163 .cfi_offset 14, -4 + 3164 000a 0446 mov r4, r0 +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3165 .loc 1 1908 3 is_stmt 1 discriminator 2 view .LVU942 + 3166 000c 0123 movs r3, #1 + 3167 000e 80F8BC33 strb r3, [r0, #956] +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3168 .loc 1 1908 3 discriminator 2 view .LVU943 +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3169 .loc 1 1910 3 discriminator 2 view .LVU944 +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** { + 3170 .loc 1 1910 6 is_stmt 0 discriminator 2 view .LVU945 + 3171 0012 11F0800F tst r1, #128 + 3172 0016 06D1 bne .L230 +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3173 .loc 1 1916 5 is_stmt 1 view .LVU946 +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3174 .loc 1 1916 11 is_stmt 0 view .LVU947 + 3175 0018 0068 ldr r0, [r0] + 3176 .LVL295: +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + ARM GAS /tmp/ccjyOkyX.s page 109 + + + 3177 .loc 1 1916 11 view .LVU948 + 3178 001a FFF7FEFF bl USB_FlushRxFifo + 3179 .LVL296: + 3180 .L224: +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3181 .loc 1 1919 3 is_stmt 1 view .LVU949 +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3182 .loc 1 1919 3 view .LVU950 + 3183 001e 0020 movs r0, #0 + 3184 0020 84F8BC03 strb r0, [r4, #956] +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3185 .loc 1 1919 3 view .LVU951 +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3186 .loc 1 1921 3 view .LVU952 +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3187 .loc 1 1922 1 is_stmt 0 view .LVU953 + 3188 0024 10BD pop {r4, pc} + 3189 .LVL297: + 3190 .L230: +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3191 .loc 1 1912 5 is_stmt 1 view .LVU954 +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3192 .loc 1 1912 11 is_stmt 0 view .LVU955 + 3193 0026 01F00F01 and r1, r1, #15 + 3194 .LVL298: +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3195 .loc 1 1912 11 view .LVU956 + 3196 002a 0068 ldr r0, [r0] + 3197 .LVL299: +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3198 .loc 1 1912 11 view .LVU957 + 3199 002c FFF7FEFF bl USB_FlushTxFifo + 3200 .LVL300: + 3201 0030 F5E7 b .L224 + 3202 .LVL301: + 3203 .L225: + 3204 .LCFI31: + 3205 .cfi_def_cfa_offset 0 + 3206 .cfi_restore 4 + 3207 .cfi_restore 14 +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3208 .loc 1 1908 3 view .LVU958 + 3209 0032 0220 movs r0, #2 + 3210 .LVL302: +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3211 .loc 1 1922 1 view .LVU959 + 3212 0034 7047 bx lr + 3213 .cfi_endproc + 3214 .LFE169: + 3216 .section .text.HAL_PCD_ActivateRemoteWakeup,"ax",%progbits + 3217 .align 1 + 3218 .global HAL_PCD_ActivateRemoteWakeup + 3219 .syntax unified + 3220 .thumb + 3221 .thumb_func + 3222 .fpu fpv5-d16 + 3224 HAL_PCD_ActivateRemoteWakeup: + ARM GAS /tmp/ccjyOkyX.s page 110 + + + 3225 .LVL303: + 3226 .LFB170: +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return (USB_ActivateRemoteWakeup(hpcd->Instance)); + 3227 .loc 1 1930 1 is_stmt 1 view -0 + 3228 .cfi_startproc + 3229 @ args = 0, pretend = 0, frame = 0 + 3230 @ frame_needed = 0, uses_anonymous_args = 0 +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return (USB_ActivateRemoteWakeup(hpcd->Instance)); + 3231 .loc 1 1930 1 is_stmt 0 view .LVU961 + 3232 0000 08B5 push {r3, lr} + 3233 .LCFI32: + 3234 .cfi_def_cfa_offset 8 + 3235 .cfi_offset 3, -8 + 3236 .cfi_offset 14, -4 +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3237 .loc 1 1931 3 is_stmt 1 view .LVU962 +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3238 .loc 1 1931 11 is_stmt 0 view .LVU963 + 3239 0002 0068 ldr r0, [r0] + 3240 .LVL304: +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3241 .loc 1 1931 11 view .LVU964 + 3242 0004 FFF7FEFF bl USB_ActivateRemoteWakeup + 3243 .LVL305: +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3244 .loc 1 1932 1 view .LVU965 + 3245 0008 08BD pop {r3, pc} + 3246 .cfi_endproc + 3247 .LFE170: + 3249 .section .text.HAL_PCD_DeActivateRemoteWakeup,"ax",%progbits + 3250 .align 1 + 3251 .global HAL_PCD_DeActivateRemoteWakeup + 3252 .syntax unified + 3253 .thumb + 3254 .thumb_func + 3255 .fpu fpv5-d16 + 3257 HAL_PCD_DeActivateRemoteWakeup: + 3258 .LVL306: + 3259 .LFB171: +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return (USB_DeActivateRemoteWakeup(hpcd->Instance)); + 3260 .loc 1 1940 1 is_stmt 1 view -0 + 3261 .cfi_startproc + 3262 @ args = 0, pretend = 0, frame = 0 + 3263 @ frame_needed = 0, uses_anonymous_args = 0 +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return (USB_DeActivateRemoteWakeup(hpcd->Instance)); + 3264 .loc 1 1940 1 is_stmt 0 view .LVU967 + 3265 0000 08B5 push {r3, lr} + 3266 .LCFI33: + 3267 .cfi_def_cfa_offset 8 + 3268 .cfi_offset 3, -8 + 3269 .cfi_offset 14, -4 +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3270 .loc 1 1941 3 is_stmt 1 view .LVU968 +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3271 .loc 1 1941 11 is_stmt 0 view .LVU969 + 3272 0002 0068 ldr r0, [r0] + 3273 .LVL307: + ARM GAS /tmp/ccjyOkyX.s page 111 + + +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3274 .loc 1 1941 11 view .LVU970 + 3275 0004 FFF7FEFF bl USB_DeActivateRemoteWakeup + 3276 .LVL308: +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3277 .loc 1 1942 1 view .LVU971 + 3278 0008 08BD pop {r3, pc} + 3279 .cfi_endproc + 3280 .LFE171: + 3282 .section .text.HAL_PCD_GetState,"ax",%progbits + 3283 .align 1 + 3284 .global HAL_PCD_GetState + 3285 .syntax unified + 3286 .thumb + 3287 .thumb_func + 3288 .fpu fpv5-d16 + 3290 HAL_PCD_GetState: + 3291 .LVL309: + 3292 .LFB172: +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** return hpcd->State; + 3293 .loc 1 1969 1 is_stmt 1 view -0 + 3294 .cfi_startproc + 3295 @ args = 0, pretend = 0, frame = 0 + 3296 @ frame_needed = 0, uses_anonymous_args = 0 + 3297 @ link register save eliminated. +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3298 .loc 1 1970 3 view .LVU973 +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** } + 3299 .loc 1 1970 14 is_stmt 0 view .LVU974 + 3300 0000 90F8BD03 ldrb r0, [r0, #957] @ zero_extendqisi2 + 3301 .LVL310: +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c **** + 3302 .loc 1 1971 1 view .LVU975 + 3303 0004 7047 bx lr + 3304 .cfi_endproc + 3305 .LFE172: + 3307 .text + 3308 .Letext0: + 3309 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3310 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3311 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 3312 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 3313 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h" + 3314 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h" + 3315 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h" + 3316 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" + ARM GAS /tmp/ccjyOkyX.s page 112 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_pcd.c + /tmp/ccjyOkyX.s:17 .text.PCD_WriteEmptyTxFifo:0000000000000000 $t + /tmp/ccjyOkyX.s:24 .text.PCD_WriteEmptyTxFifo:0000000000000000 PCD_WriteEmptyTxFifo + /tmp/ccjyOkyX.s:217 .text.HAL_PCD_MspInit:0000000000000000 $t + /tmp/ccjyOkyX.s:224 .text.HAL_PCD_MspInit:0000000000000000 HAL_PCD_MspInit + /tmp/ccjyOkyX.s:239 .text.HAL_PCD_Init:0000000000000000 $t + /tmp/ccjyOkyX.s:246 .text.HAL_PCD_Init:0000000000000000 HAL_PCD_Init + /tmp/ccjyOkyX.s:517 .text.HAL_PCD_MspDeInit:0000000000000000 $t + /tmp/ccjyOkyX.s:524 .text.HAL_PCD_MspDeInit:0000000000000000 HAL_PCD_MspDeInit + /tmp/ccjyOkyX.s:539 .text.HAL_PCD_Start:0000000000000000 $t + /tmp/ccjyOkyX.s:546 .text.HAL_PCD_Start:0000000000000000 HAL_PCD_Start + /tmp/ccjyOkyX.s:626 .text.HAL_PCD_Stop:0000000000000000 $t + /tmp/ccjyOkyX.s:633 .text.HAL_PCD_Stop:0000000000000000 HAL_PCD_Stop + /tmp/ccjyOkyX.s:709 .text.HAL_PCD_DeInit:0000000000000000 $t + /tmp/ccjyOkyX.s:716 .text.HAL_PCD_DeInit:0000000000000000 HAL_PCD_DeInit + /tmp/ccjyOkyX.s:767 .text.HAL_PCD_DataOutStageCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:774 .text.HAL_PCD_DataOutStageCallback:0000000000000000 HAL_PCD_DataOutStageCallback + /tmp/ccjyOkyX.s:790 .text.PCD_EP_OutXfrComplete_int:0000000000000000 $t + /tmp/ccjyOkyX.s:796 .text.PCD_EP_OutXfrComplete_int:0000000000000000 PCD_EP_OutXfrComplete_int + /tmp/ccjyOkyX.s:1009 .text.PCD_EP_OutXfrComplete_int:00000000000000ec $d + /tmp/ccjyOkyX.s:1015 .text.HAL_PCD_DataInStageCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1022 .text.HAL_PCD_DataInStageCallback:0000000000000000 HAL_PCD_DataInStageCallback + /tmp/ccjyOkyX.s:1038 .text.HAL_PCD_SetupStageCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1045 .text.HAL_PCD_SetupStageCallback:0000000000000000 HAL_PCD_SetupStageCallback + /tmp/ccjyOkyX.s:1060 .text.PCD_EP_OutSetupPacket_int:0000000000000000 $t + /tmp/ccjyOkyX.s:1066 .text.PCD_EP_OutSetupPacket_int:0000000000000000 PCD_EP_OutSetupPacket_int + /tmp/ccjyOkyX.s:1146 .text.PCD_EP_OutSetupPacket_int:000000000000004c $d + /tmp/ccjyOkyX.s:1151 .text.HAL_PCD_SOFCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1158 .text.HAL_PCD_SOFCallback:0000000000000000 HAL_PCD_SOFCallback + /tmp/ccjyOkyX.s:1173 .text.HAL_PCD_ResetCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1180 .text.HAL_PCD_ResetCallback:0000000000000000 HAL_PCD_ResetCallback + /tmp/ccjyOkyX.s:1195 .text.HAL_PCD_SuspendCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1202 .text.HAL_PCD_SuspendCallback:0000000000000000 HAL_PCD_SuspendCallback + /tmp/ccjyOkyX.s:1217 .text.HAL_PCD_ResumeCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1224 .text.HAL_PCD_ResumeCallback:0000000000000000 HAL_PCD_ResumeCallback + /tmp/ccjyOkyX.s:1239 .text.HAL_PCD_ISOOUTIncompleteCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1246 .text.HAL_PCD_ISOOUTIncompleteCallback:0000000000000000 HAL_PCD_ISOOUTIncompleteCallback + /tmp/ccjyOkyX.s:1262 .text.HAL_PCD_ISOINIncompleteCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1269 .text.HAL_PCD_ISOINIncompleteCallback:0000000000000000 HAL_PCD_ISOINIncompleteCallback + /tmp/ccjyOkyX.s:1285 .text.HAL_PCD_ConnectCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1292 .text.HAL_PCD_ConnectCallback:0000000000000000 HAL_PCD_ConnectCallback + /tmp/ccjyOkyX.s:1307 .text.HAL_PCD_DisconnectCallback:0000000000000000 $t + /tmp/ccjyOkyX.s:1314 .text.HAL_PCD_DisconnectCallback:0000000000000000 HAL_PCD_DisconnectCallback + /tmp/ccjyOkyX.s:1329 .text.HAL_PCD_IRQHandler:0000000000000000 $t + /tmp/ccjyOkyX.s:1336 .text.HAL_PCD_IRQHandler:0000000000000000 HAL_PCD_IRQHandler + /tmp/ccjyOkyX.s:2182 .text.HAL_PCD_DevConnect:0000000000000000 $t + /tmp/ccjyOkyX.s:2189 .text.HAL_PCD_DevConnect:0000000000000000 HAL_PCD_DevConnect + /tmp/ccjyOkyX.s:2265 .text.HAL_PCD_DevDisconnect:0000000000000000 $t + /tmp/ccjyOkyX.s:2272 .text.HAL_PCD_DevDisconnect:0000000000000000 HAL_PCD_DevDisconnect + /tmp/ccjyOkyX.s:2325 .text.HAL_PCD_SetAddress:0000000000000000 $t + /tmp/ccjyOkyX.s:2332 .text.HAL_PCD_SetAddress:0000000000000000 HAL_PCD_SetAddress + /tmp/ccjyOkyX.s:2388 .text.HAL_PCD_EP_Open:0000000000000000 $t + /tmp/ccjyOkyX.s:2395 .text.HAL_PCD_EP_Open:0000000000000000 HAL_PCD_EP_Open + /tmp/ccjyOkyX.s:2528 .text.HAL_PCD_EP_Close:0000000000000000 $t + /tmp/ccjyOkyX.s:2535 .text.HAL_PCD_EP_Close:0000000000000000 HAL_PCD_EP_Close + /tmp/ccjyOkyX.s:2629 .text.HAL_PCD_EP_Receive:0000000000000000 $t + ARM GAS /tmp/ccjyOkyX.s page 113 + + + /tmp/ccjyOkyX.s:2636 .text.HAL_PCD_EP_Receive:0000000000000000 HAL_PCD_EP_Receive + /tmp/ccjyOkyX.s:2736 .text.HAL_PCD_EP_GetRxCount:0000000000000000 $t + /tmp/ccjyOkyX.s:2743 .text.HAL_PCD_EP_GetRxCount:0000000000000000 HAL_PCD_EP_GetRxCount + /tmp/ccjyOkyX.s:2767 .text.HAL_PCD_EP_Transmit:0000000000000000 $t + /tmp/ccjyOkyX.s:2774 .text.HAL_PCD_EP_Transmit:0000000000000000 HAL_PCD_EP_Transmit + /tmp/ccjyOkyX.s:2875 .text.HAL_PCD_EP_SetStall:0000000000000000 $t + /tmp/ccjyOkyX.s:2882 .text.HAL_PCD_EP_SetStall:0000000000000000 HAL_PCD_EP_SetStall + /tmp/ccjyOkyX.s:3012 .text.HAL_PCD_EP_ClrStall:0000000000000000 $t + /tmp/ccjyOkyX.s:3019 .text.HAL_PCD_EP_ClrStall:0000000000000000 HAL_PCD_EP_ClrStall + /tmp/ccjyOkyX.s:3139 .text.HAL_PCD_EP_Flush:0000000000000000 $t + /tmp/ccjyOkyX.s:3146 .text.HAL_PCD_EP_Flush:0000000000000000 HAL_PCD_EP_Flush + /tmp/ccjyOkyX.s:3217 .text.HAL_PCD_ActivateRemoteWakeup:0000000000000000 $t + /tmp/ccjyOkyX.s:3224 .text.HAL_PCD_ActivateRemoteWakeup:0000000000000000 HAL_PCD_ActivateRemoteWakeup + /tmp/ccjyOkyX.s:3250 .text.HAL_PCD_DeActivateRemoteWakeup:0000000000000000 $t + /tmp/ccjyOkyX.s:3257 .text.HAL_PCD_DeActivateRemoteWakeup:0000000000000000 HAL_PCD_DeActivateRemoteWakeup + /tmp/ccjyOkyX.s:3283 .text.HAL_PCD_GetState:0000000000000000 $t + /tmp/ccjyOkyX.s:3290 .text.HAL_PCD_GetState:0000000000000000 HAL_PCD_GetState + +UNDEFINED SYMBOLS +USB_WritePacket +USB_DisableGlobalInt +USB_CoreInit +USB_SetCurrentMode +USB_DevInit +USB_DevDisconnect +HAL_PCDEx_ActivateLPM +USB_DevConnect +USB_EnableGlobalInt +USB_StopDevice +USB_EP0_OutStart +USB_GetMode +USB_ReadInterrupts +HAL_PCDEx_LPM_Callback +USB_ReadPacket +USB_ReadDevAllOutEpInterrupt +USB_ReadDevOutEPInterrupt +USB_ReadDevAllInEpInterrupt +USB_ReadDevInEPInterrupt +USB_FlushTxFifo +USB_ActivateSetup +USB_GetDevSpeed +HAL_RCC_GetHCLKFreq +USB_SetTurnaroundTime +USB_SetDevAddress +USB_ActivateEndpoint +USB_DeactivateEndpoint +USB_EP0StartXfer +USB_EPStartXfer +USB_EPSetStall +USB_EPClearStall +USB_FlushRxFifo +USB_ActivateRemoteWakeup +USB_DeActivateRemoteWakeup diff --git a/build/stm32h7xx_hal_pcd.o b/build/stm32h7xx_hal_pcd.o new file mode 100644 index 0000000..33f9b24 Binary files /dev/null and b/build/stm32h7xx_hal_pcd.o differ diff --git a/build/stm32h7xx_hal_pcd_ex.d b/build/stm32h7xx_hal_pcd_ex.d new file mode 100644 index 0000000..69f7f76 --- /dev/null +++ b/build/stm32h7xx_hal_pcd_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_pcd_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_pcd_ex.lst b/build/stm32h7xx_hal_pcd_ex.lst new file mode 100644 index 0000000..4d9d2fc --- /dev/null +++ b/build/stm32h7xx_hal_pcd_ex.lst @@ -0,0 +1,1040 @@ +ARM GAS /tmp/ccmPatq2.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_pcd_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_PCDEx_SetTxFiFo,"ax",%progbits + 17 .align 1 + 18 .global HAL_PCDEx_SetTxFiFo + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_PCDEx_SetTxFiFo: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @file stm32h7xx_hal_pcd_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief PCD Extended HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * functionalities of the USB Peripheral Controller: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * + Extended features functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** ****************************************************************************** + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @attention + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** *

© Copyright (c) 2017 STMicroelectronics. + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * All rights reserved.

+ 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * the "License"; You may not use this file except in compliance with the + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * License. You may obtain a copy of the License at: + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * opensource.org/licenses/BSD-3-Clause + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** ****************************************************************************** + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #include "stm32h7xx_hal.h" + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @{ + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + ARM GAS /tmp/ccmPatq2.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** @defgroup PCDEx PCDEx + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief PCD Extended HAL module driver + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @{ + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #ifdef HAL_PCD_MODULE_ENABLED + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Private types -------------------------------------------------------------*/ + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Private variables ---------------------------------------------------------*/ + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Private constants ---------------------------------------------------------*/ + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Private macros ------------------------------------------------------------*/ + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Private functions ---------------------------------------------------------*/ + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Exported functions --------------------------------------------------------*/ + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @{ + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief PCDEx control functions + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** @verbatim + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** =============================================================================== + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** ##### Extended features functions ##### + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** =============================================================================== + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** [..] This section provides functions allowing to: + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** (+) Update FIFO configuration + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** @endverbatim + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @{ + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Set Tx FIFO + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param fifo The number of Tx fifo + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param size Fifo size + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 29 .loc 1 72 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 .loc 1 72 1 is_stmt 0 view .LVU1 + 35 0000 10B4 push {r4} + 36 .LCFI0: + 37 .cfi_def_cfa_offset 4 + 38 .cfi_offset 4, -4 + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** uint8_t i; + 39 .loc 1 73 3 is_stmt 1 view .LVU2 + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** uint32_t Tx_Offset; + 40 .loc 1 74 3 view .LVU3 + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + ARM GAS /tmp/ccmPatq2.s page 3 + + + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* TXn min size = 16 words. (n : Transmit FIFO index) + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** When a TxFIFO is not used, the Configuration should be as follows: + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** --> Txm can use the space allocated for Txn. + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** --> Txn should be configured with the minimum space of 16 words + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** The FIFO is used optimally when used TxFIFOs are allocated in the top + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** Tx_Offset = hpcd->Instance->GRXFSIZ; + 41 .loc 1 86 3 view .LVU4 + 42 .loc 1 86 19 is_stmt 0 view .LVU5 + 43 0002 0468 ldr r4, [r0] + 44 .loc 1 86 13 view .LVU6 + 45 0004 606A ldr r0, [r4, #36] + 46 .LVL1: + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** if (fifo == 0U) + 47 .loc 1 88 3 is_stmt 1 view .LVU7 + 48 .loc 1 88 6 is_stmt 0 view .LVU8 + 49 0006 31B9 cbnz r1, .L2 + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + 50 .loc 1 90 5 is_stmt 1 view .LVU9 + 51 .loc 1 90 65 is_stmt 0 view .LVU10 + 52 0008 40EA0240 orr r0, r0, r2, lsl #16 + 53 .LVL2: + 54 .loc 1 90 40 view .LVU11 + 55 000c A062 str r0, [r4, #40] + 56 .LVL3: + 57 .L3: + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** else + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** for (i = 0U; i < (fifo - 1U); i++) + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Multiply Tx_Size by 2 to get higher performance */ + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return HAL_OK; + 58 .loc 1 104 3 is_stmt 1 view .LVU12 + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 59 .loc 1 105 1 is_stmt 0 view .LVU13 + 60 000e 0020 movs r0, #0 + 61 0010 5DF8044B ldr r4, [sp], #4 + 62 .LCFI1: + 63 .cfi_remember_state + 64 .cfi_restore 4 + 65 .cfi_def_cfa_offset 0 + 66 0014 7047 bx lr + 67 .LVL4: + ARM GAS /tmp/ccmPatq2.s page 4 + + + 68 .L2: + 69 .LCFI2: + 70 .cfi_restore_state + 71 .loc 1 105 1 view .LVU14 + 72 0016 8C46 mov ip, r1 + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** for (i = 0U; i < (fifo - 1U); i++) + 73 .loc 1 94 5 is_stmt 1 view .LVU15 + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** for (i = 0U; i < (fifo - 1U); i++) + 74 .loc 1 94 33 is_stmt 0 view .LVU16 + 75 0018 A36A ldr r3, [r4, #40] + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** for (i = 0U; i < (fifo - 1U); i++) + 76 .loc 1 94 15 view .LVU17 + 77 001a 00EB1340 add r0, r0, r3, lsr #16 + 78 .LVL5: + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 79 .loc 1 95 5 is_stmt 1 view .LVU18 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 80 .loc 1 95 12 is_stmt 0 view .LVU19 + 81 001e 0023 movs r3, #0 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 82 .loc 1 95 5 view .LVU20 + 83 0020 08E0 b .L4 + 84 .LVL6: + 85 .L5: + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 86 .loc 1 97 7 is_stmt 1 discriminator 3 view .LVU21 + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 87 .loc 1 97 44 is_stmt 0 discriminator 3 view .LVU22 + 88 0022 03F14001 add r1, r3, #64 + 89 0026 04EB8101 add r1, r4, r1, lsl #2 + 90 002a 4968 ldr r1, [r1, #4] + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 91 .loc 1 97 17 discriminator 3 view .LVU23 + 92 002c 00EB1140 add r0, r0, r1, lsr #16 + 93 .LVL7: + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 94 .loc 1 95 35 is_stmt 1 discriminator 3 view .LVU24 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 95 .loc 1 95 36 is_stmt 0 discriminator 3 view .LVU25 + 96 0030 0133 adds r3, r3, #1 + 97 .LVL8: + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 98 .loc 1 95 36 discriminator 3 view .LVU26 + 99 0032 DBB2 uxtb r3, r3 + 100 .LVL9: + 101 .L4: + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 102 .loc 1 95 18 is_stmt 1 discriminator 1 view .LVU27 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 103 .loc 1 95 28 is_stmt 0 discriminator 1 view .LVU28 + 104 0034 0CF1FF31 add r1, ip, #-1 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 105 .loc 1 95 5 discriminator 1 view .LVU29 + 106 0038 8B42 cmp r3, r1 + 107 003a F2D3 bcc .L5 + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 108 .loc 1 101 5 is_stmt 1 view .LVU30 + ARM GAS /tmp/ccmPatq2.s page 5 + + + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 109 .loc 1 101 65 is_stmt 0 view .LVU31 + 110 003c 40EA0240 orr r0, r0, r2, lsl #16 + 111 .LVL10: + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 112 .loc 1 101 40 view .LVU32 + 113 0040 0CF13F01 add r1, ip, #63 + 114 0044 04EB8101 add r1, r4, r1, lsl #2 + 115 0048 4860 str r0, [r1, #4] + 116 004a E0E7 b .L3 + 117 .cfi_endproc + 118 .LFE141: + 120 .section .text.HAL_PCDEx_SetRxFiFo,"ax",%progbits + 121 .align 1 + 122 .global HAL_PCDEx_SetRxFiFo + 123 .syntax unified + 124 .thumb + 125 .thumb_func + 126 .fpu fpv5-d16 + 128 HAL_PCDEx_SetRxFiFo: + 129 .LVL11: + 130 .LFB142: + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Set Rx FIFO + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param size Size of Rx fifo + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 131 .loc 1 114 1 is_stmt 1 view -0 + 132 .cfi_startproc + 133 @ args = 0, pretend = 0, frame = 0 + 134 @ frame_needed = 0, uses_anonymous_args = 0 + 135 @ link register save eliminated. + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->Instance->GRXFSIZ = size; + 136 .loc 1 115 3 view .LVU34 + 137 .loc 1 115 7 is_stmt 0 view .LVU35 + 138 0000 0368 ldr r3, [r0] + 139 .loc 1 115 27 view .LVU36 + 140 0002 5962 str r1, [r3, #36] + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return HAL_OK; + 141 .loc 1 117 3 is_stmt 1 view .LVU37 + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 142 .loc 1 118 1 is_stmt 0 view .LVU38 + 143 0004 0020 movs r0, #0 + 144 .LVL12: + 145 .loc 1 118 1 view .LVU39 + 146 0006 7047 bx lr + 147 .cfi_endproc + 148 .LFE142: + 150 .section .text.HAL_PCDEx_ActivateLPM,"ax",%progbits + 151 .align 1 + 152 .global HAL_PCDEx_ActivateLPM + 153 .syntax unified + ARM GAS /tmp/ccmPatq2.s page 6 + + + 154 .thumb + 155 .thumb_func + 156 .fpu fpv5-d16 + 158 HAL_PCDEx_ActivateLPM: + 159 .LVL13: + 160 .LFB143: + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Activate LPM feature. + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 161 .loc 1 126 1 is_stmt 1 view -0 + 162 .cfi_startproc + 163 @ args = 0, pretend = 0, frame = 0 + 164 @ frame_needed = 0, uses_anonymous_args = 0 + 165 @ link register save eliminated. + 166 .loc 1 126 1 is_stmt 0 view .LVU41 + 167 0000 0346 mov r3, r0 + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 168 .loc 1 127 3 is_stmt 1 view .LVU42 + 169 .loc 1 127 26 is_stmt 0 view .LVU43 + 170 0002 0268 ldr r2, [r0] + 171 .LVL14: + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->lpm_active = 1U; + 172 .loc 1 129 3 is_stmt 1 view .LVU44 + 173 .loc 1 129 20 is_stmt 0 view .LVU45 + 174 0004 0121 movs r1, #1 + 175 0006 C0F8FC13 str r1, [r0, #1020] + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->LPM_State = LPM_L0; + 176 .loc 1 130 3 is_stmt 1 view .LVU46 + 177 .loc 1 130 19 is_stmt 0 view .LVU47 + 178 000a 0020 movs r0, #0 + 179 .LVL15: + 180 .loc 1 130 19 view .LVU48 + 181 000c 83F8F403 strb r0, [r3, #1012] + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + 182 .loc 1 131 3 is_stmt 1 view .LVU49 + 183 .loc 1 131 17 is_stmt 0 view .LVU50 + 184 0010 9369 ldr r3, [r2, #24] + 185 .LVL16: + 186 .loc 1 131 17 view .LVU51 + 187 0012 43F00063 orr r3, r3, #134217728 + 188 0016 9361 str r3, [r2, #24] + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + 189 .loc 1 132 3 is_stmt 1 view .LVU52 + 190 .loc 1 132 17 is_stmt 0 view .LVU53 + 191 0018 516D ldr r1, [r2, #84] + 192 001a 024B ldr r3, .L9 + 193 001c 0B43 orrs r3, r3, r1 + 194 001e 5365 str r3, [r2, #84] + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return HAL_OK; + 195 .loc 1 134 3 is_stmt 1 view .LVU54 + ARM GAS /tmp/ccmPatq2.s page 7 + + + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 196 .loc 1 135 1 is_stmt 0 view .LVU55 + 197 0020 7047 bx lr + 198 .L10: + 199 0022 00BF .align 2 + 200 .L9: + 201 0024 03000010 .word 268435459 + 202 .cfi_endproc + 203 .LFE143: + 205 .section .text.HAL_PCDEx_DeActivateLPM,"ax",%progbits + 206 .align 1 + 207 .global HAL_PCDEx_DeActivateLPM + 208 .syntax unified + 209 .thumb + 210 .thumb_func + 211 .fpu fpv5-d16 + 213 HAL_PCDEx_DeActivateLPM: + 214 .LVL17: + 215 .LFB144: + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Deactivate LPM feature. + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 216 .loc 1 143 1 is_stmt 1 view -0 + 217 .cfi_startproc + 218 @ args = 0, pretend = 0, frame = 0 + 219 @ frame_needed = 0, uses_anonymous_args = 0 + 220 @ link register save eliminated. + 221 .loc 1 143 1 is_stmt 0 view .LVU57 + 222 0000 0246 mov r2, r0 + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 223 .loc 1 144 3 is_stmt 1 view .LVU58 + 224 .loc 1 144 26 is_stmt 0 view .LVU59 + 225 0002 0368 ldr r3, [r0] + 226 .LVL18: + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->lpm_active = 0U; + 227 .loc 1 146 3 is_stmt 1 view .LVU60 + 228 .loc 1 146 20 is_stmt 0 view .LVU61 + 229 0004 0020 movs r0, #0 + 230 .LVL19: + 231 .loc 1 146 20 view .LVU62 + 232 0006 C2F8FC03 str r0, [r2, #1020] + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + 233 .loc 1 147 3 is_stmt 1 view .LVU63 + 234 .loc 1 147 17 is_stmt 0 view .LVU64 + 235 000a 9A69 ldr r2, [r3, #24] + 236 .LVL20: + 237 .loc 1 147 17 view .LVU65 + 238 000c 22F00062 bic r2, r2, #134217728 + 239 0010 9A61 str r2, [r3, #24] + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + 240 .loc 1 148 3 is_stmt 1 view .LVU66 + ARM GAS /tmp/ccmPatq2.s page 8 + + + 241 .loc 1 148 17 is_stmt 0 view .LVU67 + 242 0012 596D ldr r1, [r3, #84] + 243 0014 014A ldr r2, .L12 + 244 0016 0A40 ands r2, r2, r1 + 245 0018 5A65 str r2, [r3, #84] + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return HAL_OK; + 246 .loc 1 150 3 is_stmt 1 view .LVU68 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 247 .loc 1 151 1 is_stmt 0 view .LVU69 + 248 001a 7047 bx lr + 249 .L13: + 250 .align 2 + 251 .L12: + 252 001c FCFFFFEF .word -268435460 + 253 .cfi_endproc + 254 .LFE144: + 256 .section .text.HAL_PCDEx_ActivateBCD,"ax",%progbits + 257 .align 1 + 258 .global HAL_PCDEx_ActivateBCD + 259 .syntax unified + 260 .thumb + 261 .thumb_func + 262 .fpu fpv5-d16 + 264 HAL_PCDEx_ActivateBCD: + 265 .LVL21: + 266 .LFB146: + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Handle BatteryCharging Process. + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** uint32_t tickstart = HAL_GetTick(); + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Enable DCD : Data Contact Detect */ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Wait Detect flag or a timeout is happen*/ + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Check for the Timeout */ + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** if ((HAL_GetTick() - tickstart) > 1000U) + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #else + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return; + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + ARM GAS /tmp/ccmPatq2.s page 9 + + + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Right response got */ + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(200U); + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Check Detect flag*/ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #else + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /*Primary detection: checks if connected to Standard Downstream Port + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** (without charging capability) */ + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Case of Standard Downstream Port */ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #else + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** else + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* start secondary detection to check connection to Charging Downstream + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** Port or Dedicated Charging Port */ + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* case Dedicated Charging Port */ + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #else + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** else + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* case Charging Downstream Port */ + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #else + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + ARM GAS /tmp/ccmPatq2.s page 10 + + + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Battery Charging capability discovery finished */ + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** (void)HAL_PCDEx_DeActivateBCD(hpcd); + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #else + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Activate BatteryCharging feature. + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 267 .loc 1 257 1 is_stmt 1 view -0 + 268 .cfi_startproc + 269 @ args = 0, pretend = 0, frame = 0 + 270 @ frame_needed = 0, uses_anonymous_args = 0 + 271 @ link register save eliminated. + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 272 .loc 1 258 3 view .LVU71 + 273 .loc 1 258 26 is_stmt 0 view .LVU72 + 274 0000 0368 ldr r3, [r0] + 275 .LVL22: + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + 276 .loc 1 260 3 is_stmt 1 view .LVU73 + 277 .loc 1 260 15 is_stmt 0 view .LVU74 + 278 0002 9A6B ldr r2, [r3, #56] + 279 0004 22F40022 bic r2, r2, #524288 + 280 0008 9A63 str r2, [r3, #56] + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + 281 .loc 1 261 3 is_stmt 1 view .LVU75 + 282 .loc 1 261 15 is_stmt 0 view .LVU76 + 283 000a 9A6B ldr r2, [r3, #56] + 284 000c 22F48012 bic r2, r2, #1048576 + 285 0010 9A63 str r2, [r3, #56] + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Power Down USB tranceiver */ + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + 286 .loc 1 264 3 is_stmt 1 view .LVU77 + 287 .loc 1 264 15 is_stmt 0 view .LVU78 + 288 0012 9A6B ldr r2, [r3, #56] + 289 0014 22F48032 bic r2, r2, #65536 + 290 0018 9A63 str r2, [r3, #56] + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Enable Battery charging */ + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + 291 .loc 1 267 3 is_stmt 1 view .LVU79 + 292 .loc 1 267 15 is_stmt 0 view .LVU80 + 293 001a 9A6B ldr r2, [r3, #56] + 294 001c 42F40032 orr r2, r2, #131072 + ARM GAS /tmp/ccmPatq2.s page 11 + + + 295 0020 9A63 str r2, [r3, #56] + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->battery_charging_active = 1U; + 296 .loc 1 269 3 is_stmt 1 view .LVU81 + 297 .loc 1 269 33 is_stmt 0 view .LVU82 + 298 0022 0123 movs r3, #1 + 299 .LVL23: + 300 .loc 1 269 33 view .LVU83 + 301 0024 C0F80034 str r3, [r0, #1024] + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return HAL_OK; + 302 .loc 1 271 3 is_stmt 1 view .LVU84 + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 303 .loc 1 272 1 is_stmt 0 view .LVU85 + 304 0028 0020 movs r0, #0 + 305 .LVL24: + 306 .loc 1 272 1 view .LVU86 + 307 002a 7047 bx lr + 308 .cfi_endproc + 309 .LFE146: + 311 .section .text.HAL_PCDEx_DeActivateBCD,"ax",%progbits + 312 .align 1 + 313 .global HAL_PCDEx_DeActivateBCD + 314 .syntax unified + 315 .thumb + 316 .thumb_func + 317 .fpu fpv5-d16 + 319 HAL_PCDEx_DeActivateBCD: + 320 .LVL25: + 321 .LFB147: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Deactivate BatteryCharging feature. + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 322 .loc 1 280 1 is_stmt 1 view -0 + 323 .cfi_startproc + 324 @ args = 0, pretend = 0, frame = 0 + 325 @ frame_needed = 0, uses_anonymous_args = 0 + 326 @ link register save eliminated. + 327 .loc 1 280 1 is_stmt 0 view .LVU88 + 328 0000 0246 mov r2, r0 + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 329 .loc 1 281 3 is_stmt 1 view .LVU89 + 330 .loc 1 281 26 is_stmt 0 view .LVU90 + 331 0002 0368 ldr r3, [r0] + 332 .LVL26: + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + 333 .loc 1 283 3 is_stmt 1 view .LVU91 + 334 .loc 1 283 15 is_stmt 0 view .LVU92 + 335 0004 996B ldr r1, [r3, #56] + 336 0006 21F48011 bic r1, r1, #1048576 + 337 000a 9963 str r1, [r3, #56] + ARM GAS /tmp/ccmPatq2.s page 12 + + + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + 338 .loc 1 284 3 is_stmt 1 view .LVU93 + 339 .loc 1 284 15 is_stmt 0 view .LVU94 + 340 000c 996B ldr r1, [r3, #56] + 341 000e 21F40021 bic r1, r1, #524288 + 342 0012 9963 str r1, [r3, #56] + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Disable Battery charging */ + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + 343 .loc 1 287 3 is_stmt 1 view .LVU95 + 344 .loc 1 287 15 is_stmt 0 view .LVU96 + 345 0014 996B ldr r1, [r3, #56] + 346 0016 21F40031 bic r1, r1, #131072 + 347 001a 9963 str r1, [r3, #56] + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** hpcd->battery_charging_active = 0U; + 348 .loc 1 289 3 is_stmt 1 view .LVU97 + 349 .loc 1 289 33 is_stmt 0 view .LVU98 + 350 001c 0020 movs r0, #0 + 351 .LVL27: + 352 .loc 1 289 33 view .LVU99 + 353 001e C2F80004 str r0, [r2, #1024] + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** return HAL_OK; + 354 .loc 1 291 3 is_stmt 1 view .LVU100 + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 355 .loc 1 292 1 is_stmt 0 view .LVU101 + 356 0022 7047 bx lr + 357 .cfi_endproc + 358 .LFE147: + 360 .section .text.HAL_PCDEx_LPM_Callback,"ax",%progbits + 361 .align 1 + 362 .weak HAL_PCDEx_LPM_Callback + 363 .syntax unified + 364 .thumb + 365 .thumb_func + 366 .fpu fpv5-d16 + 368 HAL_PCDEx_LPM_Callback: + 369 .LVL28: + 370 .LFB148: + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Send LPM message to user layer callback. + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param msg LPM message + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 371 .loc 1 303 1 is_stmt 1 view -0 + 372 .cfi_startproc + 373 @ args = 0, pretend = 0, frame = 0 + 374 @ frame_needed = 0, uses_anonymous_args = 0 + 375 @ link register save eliminated. + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccmPatq2.s page 13 + + + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** UNUSED(hpcd); + 376 .loc 1 305 3 view .LVU103 + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** UNUSED(msg); + 377 .loc 1 306 3 view .LVU104 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** the HAL_PCDEx_LPM_Callback could be implemented in the user file + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 378 .loc 1 311 1 is_stmt 0 view .LVU105 + 379 0000 7047 bx lr + 380 .cfi_endproc + 381 .LFE148: + 383 .section .text.HAL_PCDEx_BCD_Callback,"ax",%progbits + 384 .align 1 + 385 .weak HAL_PCDEx_BCD_Callback + 386 .syntax unified + 387 .thumb + 388 .thumb_func + 389 .fpu fpv5-d16 + 391 HAL_PCDEx_BCD_Callback: + 392 .LVL29: + 393 .LFB149: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /** + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @brief Send BatteryCharging message to user layer callback. + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param hpcd PCD handle + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @param msg LPM message + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** * @retval HAL status + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 394 .loc 1 320 1 is_stmt 1 view -0 + 395 .cfi_startproc + 396 @ args = 0, pretend = 0, frame = 0 + 397 @ frame_needed = 0, uses_anonymous_args = 0 + 398 @ link register save eliminated. + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* Prevent unused argument(s) compilation warning */ + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** UNUSED(hpcd); + 399 .loc 1 322 3 view .LVU107 + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** UNUSED(msg); + 400 .loc 1 323 3 view .LVU108 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** the HAL_PCDEx_BCD_Callback could be implemented in the user file + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** */ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 401 .loc 1 328 1 is_stmt 0 view .LVU109 + 402 0000 7047 bx lr + 403 .cfi_endproc + 404 .LFE149: + 406 .section .text.HAL_PCDEx_BCD_VBUSDetect,"ax",%progbits + 407 .align 1 + 408 .global HAL_PCDEx_BCD_VBUSDetect + 409 .syntax unified + 410 .thumb + 411 .thumb_func + ARM GAS /tmp/ccmPatq2.s page 14 + + + 412 .fpu fpv5-d16 + 414 HAL_PCDEx_BCD_VBUSDetect: + 415 .LVL30: + 416 .LFB145: + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 417 .loc 1 160 1 is_stmt 1 view -0 + 418 .cfi_startproc + 419 @ args = 0, pretend = 0, frame = 0 + 420 @ frame_needed = 0, uses_anonymous_args = 0 + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + 421 .loc 1 160 1 is_stmt 0 view .LVU111 + 422 0000 70B5 push {r4, r5, r6, lr} + 423 .LCFI3: + 424 .cfi_def_cfa_offset 16 + 425 .cfi_offset 4, -16 + 426 .cfi_offset 5, -12 + 427 .cfi_offset 6, -8 + 428 .cfi_offset 14, -4 + 429 0002 0646 mov r6, r0 + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** uint32_t tickstart = HAL_GetTick(); + 430 .loc 1 161 3 is_stmt 1 view .LVU112 + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** uint32_t tickstart = HAL_GetTick(); + 431 .loc 1 161 26 is_stmt 0 view .LVU113 + 432 0004 0468 ldr r4, [r0] + 433 .LVL31: + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 434 .loc 1 162 3 is_stmt 1 view .LVU114 + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 435 .loc 1 162 24 is_stmt 0 view .LVU115 + 436 0006 FFF7FEFF bl HAL_GetTick + 437 .LVL32: + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 438 .loc 1 162 24 view .LVU116 + 439 000a 0546 mov r5, r0 + 440 .LVL33: + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 441 .loc 1 165 3 is_stmt 1 view .LVU117 + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 442 .loc 1 165 15 is_stmt 0 view .LVU118 + 443 000c A36B ldr r3, [r4, #56] + 444 000e 43F48023 orr r3, r3, #262144 + 445 0012 A363 str r3, [r4, #56] + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 446 .loc 1 168 3 is_stmt 1 view .LVU119 + 447 .LVL34: + 448 .L19: + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 449 .loc 1 168 9 view .LVU120 + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 450 .loc 1 168 15 is_stmt 0 view .LVU121 + 451 0014 A36B ldr r3, [r4, #56] + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 452 .loc 1 168 9 view .LVU122 + 453 0016 13F0010F tst r3, #1 + 454 001a 0AD1 bne .L27 + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 455 .loc 1 171 5 is_stmt 1 view .LVU123 + ARM GAS /tmp/ccmPatq2.s page 15 + + + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 456 .loc 1 171 10 is_stmt 0 view .LVU124 + 457 001c FFF7FEFF bl HAL_GetTick + 458 .LVL35: + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 459 .loc 1 171 24 view .LVU125 + 460 0020 401B subs r0, r0, r5 + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 461 .loc 1 171 8 view .LVU126 + 462 0022 B0F57A7F cmp r0, #1000 + 463 0026 F5D9 bls .L19 + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 464 .loc 1 176 7 is_stmt 1 view .LVU127 + 465 0028 FF21 movs r1, #255 + 466 002a 3046 mov r0, r6 + 467 002c FFF7FEFF bl HAL_PCDEx_BCD_Callback + 468 .LVL36: + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** } + 469 .loc 1 179 7 view .LVU128 + 470 0030 23E0 b .L18 + 471 .L27: + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 472 .loc 1 184 3 view .LVU129 + 473 0032 C820 movs r0, #200 + 474 0034 FFF7FEFF bl HAL_Delay + 475 .LVL37: + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 476 .loc 1 187 3 view .LVU130 + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 477 .loc 1 187 12 is_stmt 0 view .LVU131 + 478 0038 A36B ldr r3, [r4, #56] + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 479 .loc 1 187 6 view .LVU132 + 480 003a 13F0010F tst r3, #1 + 481 003e 1DD1 bne .L28 + 482 .L22: + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 483 .loc 1 198 3 is_stmt 1 view .LVU133 + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 484 .loc 1 198 15 is_stmt 0 view .LVU134 + 485 0040 A36B ldr r3, [r4, #56] + 486 0042 23F48023 bic r3, r3, #262144 + 487 0046 A363 str r3, [r4, #56] + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + 488 .loc 1 199 3 is_stmt 1 view .LVU135 + 489 0048 3220 movs r0, #50 + 490 004a FFF7FEFF bl HAL_Delay + 491 .LVL38: + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 492 .loc 1 200 3 view .LVU136 + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 493 .loc 1 200 15 is_stmt 0 view .LVU137 + 494 004e A36B ldr r3, [r4, #56] + 495 0050 43F40023 orr r3, r3, #524288 + 496 0054 A363 str r3, [r4, #56] + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 497 .loc 1 201 3 is_stmt 1 view .LVU138 + ARM GAS /tmp/ccmPatq2.s page 16 + + + 498 0056 3220 movs r0, #50 + 499 0058 FFF7FEFF bl HAL_Delay + 500 .LVL39: + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 501 .loc 1 203 3 view .LVU139 + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 502 .loc 1 203 12 is_stmt 0 view .LVU140 + 503 005c A36B ldr r3, [r4, #56] + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 504 .loc 1 203 6 view .LVU141 + 505 005e 13F0020F tst r3, #2 + 506 0062 10D1 bne .L23 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 507 .loc 1 209 5 is_stmt 1 view .LVU142 + 508 0064 FD21 movs r1, #253 + 509 0066 3046 mov r0, r6 + 510 0068 FFF7FEFF bl HAL_PCDEx_BCD_Callback + 511 .LVL40: + 512 .L24: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 513 .loc 1 242 3 view .LVU143 + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 514 .loc 1 242 9 is_stmt 0 view .LVU144 + 515 006c 3046 mov r0, r6 + 516 006e FFF7FEFF bl HAL_PCDEx_DeActivateBCD + 517 .LVL41: + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 518 .loc 1 247 3 is_stmt 1 view .LVU145 + 519 0072 0021 movs r1, #0 + 520 0074 3046 mov r0, r6 + 521 0076 FFF7FEFF bl HAL_PCDEx_BCD_Callback + 522 .LVL42: + 523 .L18: + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 524 .loc 1 249 1 is_stmt 0 view .LVU146 + 525 007a 70BD pop {r4, r5, r6, pc} + 526 .LVL43: + 527 .L28: + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 528 .loc 1 192 5 is_stmt 1 view .LVU147 + 529 007c FE21 movs r1, #254 + 530 007e 3046 mov r0, r6 + 531 0080 FFF7FEFF bl HAL_PCDEx_BCD_Callback + 532 .LVL44: + 533 0084 DCE7 b .L22 + 534 .L23: + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 535 .loc 1 216 5 view .LVU148 + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 536 .loc 1 216 17 is_stmt 0 view .LVU149 + 537 0086 A36B ldr r3, [r4, #56] + 538 0088 23F40023 bic r3, r3, #524288 + 539 008c A363 str r3, [r4, #56] + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + 540 .loc 1 217 5 is_stmt 1 view .LVU150 + 541 008e 3220 movs r0, #50 + 542 0090 FFF7FEFF bl HAL_Delay + ARM GAS /tmp/ccmPatq2.s page 17 + + + 543 .LVL45: + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 544 .loc 1 218 5 view .LVU151 + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** HAL_Delay(50U); + 545 .loc 1 218 17 is_stmt 0 view .LVU152 + 546 0094 A36B ldr r3, [r4, #56] + 547 0096 43F48013 orr r3, r3, #1048576 + 548 009a A363 str r3, [r4, #56] + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** + 549 .loc 1 219 5 is_stmt 1 view .LVU153 + 550 009c 3220 movs r0, #50 + 551 009e FFF7FEFF bl HAL_Delay + 552 .LVL46: + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 553 .loc 1 221 5 view .LVU154 + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 554 .loc 1 221 14 is_stmt 0 view .LVU155 + 555 00a2 A36B ldr r3, [r4, #56] + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** { + 556 .loc 1 221 8 view .LVU156 + 557 00a4 13F0040F tst r3, #4 + 558 00a8 04D0 beq .L25 + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 559 .loc 1 227 7 is_stmt 1 view .LVU157 + 560 00aa FB21 movs r1, #251 + 561 00ac 3046 mov r0, r6 + 562 00ae FFF7FEFF bl HAL_PCDEx_BCD_Callback + 563 .LVL47: + 564 00b2 DBE7 b .L24 + 565 .L25: + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 566 .loc 1 236 7 view .LVU158 + 567 00b4 FC21 movs r1, #252 + 568 00b6 3046 mov r0, r6 + 569 00b8 FFF7FEFF bl HAL_PCDEx_BCD_Callback + 570 .LVL48: + 571 00bc D6E7 b .L24 + 572 .cfi_endproc + 573 .LFE145: + 575 .text + 576 .Letext0: + 577 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 578 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 579 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 580 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 581 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h" + 582 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h" + 583 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccmPatq2.s page 18 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_pcd_ex.c + /tmp/ccmPatq2.s:17 .text.HAL_PCDEx_SetTxFiFo:0000000000000000 $t + /tmp/ccmPatq2.s:25 .text.HAL_PCDEx_SetTxFiFo:0000000000000000 HAL_PCDEx_SetTxFiFo + /tmp/ccmPatq2.s:121 .text.HAL_PCDEx_SetRxFiFo:0000000000000000 $t + /tmp/ccmPatq2.s:128 .text.HAL_PCDEx_SetRxFiFo:0000000000000000 HAL_PCDEx_SetRxFiFo + /tmp/ccmPatq2.s:151 .text.HAL_PCDEx_ActivateLPM:0000000000000000 $t + /tmp/ccmPatq2.s:158 .text.HAL_PCDEx_ActivateLPM:0000000000000000 HAL_PCDEx_ActivateLPM + /tmp/ccmPatq2.s:201 .text.HAL_PCDEx_ActivateLPM:0000000000000024 $d + /tmp/ccmPatq2.s:206 .text.HAL_PCDEx_DeActivateLPM:0000000000000000 $t + /tmp/ccmPatq2.s:213 .text.HAL_PCDEx_DeActivateLPM:0000000000000000 HAL_PCDEx_DeActivateLPM + /tmp/ccmPatq2.s:252 .text.HAL_PCDEx_DeActivateLPM:000000000000001c $d + /tmp/ccmPatq2.s:257 .text.HAL_PCDEx_ActivateBCD:0000000000000000 $t + /tmp/ccmPatq2.s:264 .text.HAL_PCDEx_ActivateBCD:0000000000000000 HAL_PCDEx_ActivateBCD + /tmp/ccmPatq2.s:312 .text.HAL_PCDEx_DeActivateBCD:0000000000000000 $t + /tmp/ccmPatq2.s:319 .text.HAL_PCDEx_DeActivateBCD:0000000000000000 HAL_PCDEx_DeActivateBCD + /tmp/ccmPatq2.s:361 .text.HAL_PCDEx_LPM_Callback:0000000000000000 $t + /tmp/ccmPatq2.s:368 .text.HAL_PCDEx_LPM_Callback:0000000000000000 HAL_PCDEx_LPM_Callback + /tmp/ccmPatq2.s:384 .text.HAL_PCDEx_BCD_Callback:0000000000000000 $t + /tmp/ccmPatq2.s:391 .text.HAL_PCDEx_BCD_Callback:0000000000000000 HAL_PCDEx_BCD_Callback + /tmp/ccmPatq2.s:407 .text.HAL_PCDEx_BCD_VBUSDetect:0000000000000000 $t + /tmp/ccmPatq2.s:414 .text.HAL_PCDEx_BCD_VBUSDetect:0000000000000000 HAL_PCDEx_BCD_VBUSDetect + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_Delay diff --git a/build/stm32h7xx_hal_pcd_ex.o b/build/stm32h7xx_hal_pcd_ex.o new file mode 100644 index 0000000..cdfe78a Binary files /dev/null and b/build/stm32h7xx_hal_pcd_ex.o differ diff --git a/build/stm32h7xx_hal_pwr.d b/build/stm32h7xx_hal_pwr.d new file mode 100644 index 0000000..e08f5db --- /dev/null +++ b/build/stm32h7xx_hal_pwr.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_pwr.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_pwr.lst b/build/stm32h7xx_hal_pwr.lst new file mode 100644 index 0000000..a757827 --- /dev/null +++ b/build/stm32h7xx_hal_pwr.lst @@ -0,0 +1,2646 @@ +ARM GAS /tmp/cc1wCtPf.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_pwr.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_PWR_DeInit,"ax",%progbits + 17 .align 1 + 18 .global HAL_PWR_DeInit + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_PWR_DeInit: + 26 .LFB141: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @file stm32h7xx_hal_pwr.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief PWR HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + Initialization and de-initialization functions. + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + Peripheral Control functions. + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + Interrupt Handling functions. + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @verbatim + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ##### PWR peripheral overview ##### + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) The Power control (PWR) provides an overview of the supply architecture + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** for the different power domains and of the supply configuration + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** controller. + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** In the H7 family, the number of power domains is different between + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** device lines. This difference is due to characteristics of each device. + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Domain architecture overview for the different H7 lines: + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757. + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** These devices have 3 power domains (D1, D2 and D3). + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** peripherals. The D2 domain contains peripherals and a CPU + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (Cortex-M4). The D3 domain contains the system control, I/O logic + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** and low-power peripherals. + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753 + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** devices have 3 power domains (D1, D2 and D3). + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + ARM GAS /tmp/cc1wCtPf.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** peripherals. The D2 domain contains peripherals. The D3 domains + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** contains the system control, I/O logic and low-power peripherals. + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD). + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The core domain (CD) contains a CPU (Cortex-M7), a Flash + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** memory and peripherals. The SmartRun domain contains the system + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** control, I/O logic and low-power peripherals. + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Every entity have low power mode as decribed below : + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) The CPU low power modes are : + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) CPU CRUN. + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) CPU CSLEEP. + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) CPU CSTOP. + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) The domain low power modes are : + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) DRUN. + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) DSTOP. + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) DSTANDBY. + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) The SYSTEM low power modes are : + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Standby. In Run* mode, the performance is limited and the + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** system supply configuration shall be programmed. The system + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** enters Run mode only when the ACTVOSRDY bit in PWR control + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** status register 1 (PWR_CSR1) is set to 1. + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) RUN. + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) STOP. + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) STANDBY. + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ============================================================================== + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ##### How to use this driver ##### + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ============================================================================== + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Power management peripheral is active by default at startup level in + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** STM32h7xx lines. + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** to enable/disable access to the backup domain (RTC registers, RTC backup + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** data registers and backup SRAM). + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** mode and voltage threshold) in order to set up the Power Voltage Detector, + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** and stop the PVD detection. + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) PVD level could be one of the following values : + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 1V95 + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 2V1 + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 2V25 + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 2V4 + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 2V55 + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 2V7 + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) 2V85 + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) External voltage level + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** with the right parameter to configure the wake up pin polarity (Low or + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** High) and to enable and disable it. + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** mode. Wake-up from SLEEP mode could be following to an event or an + ARM GAS /tmp/cc1wCtPf.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** interrupt according to low power mode intrinsic request called (__WFI() + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** or __WFE()). + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Please ensure to clear all CPU pending events by calling + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** in SLEEP mode with __WFE() entry. + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** mode for single core devices. For dual core devices, this API will enter + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** the domain (containing Cortex-Mx that executing this function) in DSTOP + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** mode. According to the used parameter, user could select the regulator to + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** be kept actif in low power mode and wake-up event type. + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Please ensure to clear all CPU pending events by calling + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** in CSTOP mode with __WFE() entry. + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** STANDBY mode for single core devices. For dual core devices, this API + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** will enter the domain (containing Cortex-Mx that executing this function) + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** in DSTANDBY mode. + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** enable and disable the Cortex-Mx re-entring in SLEEP mode after an + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** interruption handling is over. + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** to configure the Cortex-Mx to wake-up after any pending event / interrupt + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** even if it's disabled or has insufficient priority to cause exception + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** entry. + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** request. + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** PWR HAL driver macros list *** + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ============================================= + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Below the list of most used macros in PWR HAL driver. + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** regulator output voltage. + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @endverbatim + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ****************************************************************************** + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @attention + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * All rights reserved.

+ 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * License. You may obtain a copy of the License at: + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ****************************************************************************** + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + ARM GAS /tmp/cc1wCtPf.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #include "stm32h7xx_hal.h" + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @addtogroup STM32H7xx_HAL_Driver + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @defgroup PWR PWR + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief PWR HAL module driver + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants PWR Private Constants + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if !defined (DUAL_CORE) + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #define PVD_MODE_IT (0x00010000U) + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #define PVD_MODE_EVT (0x00020000U) + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* !defined (DUAL_CORE) */ + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #define PVD_RISING_EDGE (0x00000001U) + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #define PVD_FALLING_EDGE (0x00000002U) + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #define PVD_RISING_FALLING_EDGE (0x00000003U) + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @} + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @} + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Initialization and De-Initialization functions + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @verbatim + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** =============================================================================== + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ##### Initialization and De-Initialization Functions ##### + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** =============================================================================== + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + ARM GAS /tmp/cc1wCtPf.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** This section provides functions allowing to deinitialize power peripheral. + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** After system reset, the backup domain (RTC registers, RTC backup data + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted write + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** accesses. + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** domain. + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** domain. + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @endverbatim + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Deinitialize the HAL PWR peripheral registers to their default reset + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * values. + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note This functionality is not available in this product. + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * The prototype is kept just to maintain compatibility with other + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * products. + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_DeInit (void) + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 28 .loc 1 227 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 33 .loc 1 228 1 view .LVU1 + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE141: + 38 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits + 39 .align 1 + 40 .global HAL_PWR_EnableBkUpAccess + 41 .syntax unified + 42 .thumb + 43 .thumb_func + 44 .fpu fpv5-d16 + 46 HAL_PWR_EnableBkUpAccess: + 47 .LFB142: + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enable access to the backup domain (RTC registers, RTC backup data + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * registers and backup SRAM). + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess (void) + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 48 .loc 1 238 1 view -0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/cc1wCtPf.s page 6 + + + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Enable access to RTC and backup registers */ + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CR1, PWR_CR1_DBP); + 53 .loc 1 240 3 view .LVU3 + 54 0000 024A ldr r2, .L3 + 55 0002 1368 ldr r3, [r2] + 56 0004 43F48073 orr r3, r3, #256 + 57 0008 1360 str r3, [r2] + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 58 .loc 1 241 1 is_stmt 0 view .LVU4 + 59 000a 7047 bx lr + 60 .L4: + 61 .align 2 + 62 .L3: + 63 000c 00480258 .word 1476544512 + 64 .cfi_endproc + 65 .LFE142: + 67 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits + 68 .align 1 + 69 .global HAL_PWR_DisableBkUpAccess + 70 .syntax unified + 71 .thumb + 72 .thumb_func + 73 .fpu fpv5-d16 + 75 HAL_PWR_DisableBkUpAccess: + 76 .LFB143: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Disable access to the backup domain (RTC registers, RTC backup data + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * registers and backup SRAM). + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess (void) + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 77 .loc 1 251 1 is_stmt 1 view -0 + 78 .cfi_startproc + 79 @ args = 0, pretend = 0, frame = 0 + 80 @ frame_needed = 0, uses_anonymous_args = 0 + 81 @ link register save eliminated. + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Disable access to RTC and backup registers */ + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_DBP); + 82 .loc 1 253 3 view .LVU6 + 83 0000 024A ldr r2, .L6 + 84 0002 1368 ldr r3, [r2] + 85 0004 23F48073 bic r3, r3, #256 + 86 0008 1360 str r3, [r2] + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 87 .loc 1 254 1 is_stmt 0 view .LVU7 + 88 000a 7047 bx lr + 89 .L7: + 90 .align 2 + 91 .L6: + 92 000c 00480258 .word 1476544512 + 93 .cfi_endproc + ARM GAS /tmp/cc1wCtPf.s page 7 + + + 94 .LFE143: + 96 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits + 97 .align 1 + 98 .global HAL_PWR_ConfigPVD + 99 .syntax unified + 100 .thumb + 101 .thumb_func + 102 .fpu fpv5-d16 + 104 HAL_PWR_ConfigPVD: + 105 .LVL0: + 106 .LFB144: + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @} + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Power Control functions + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @verbatim + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** =============================================================================== + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ##### Peripheral Control Functions ##### + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** =============================================================================== + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** This section provides functions allowing to control power peripheral. + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** PVD configuration *** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ========================= + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** register). + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD is higher or lower + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** line 16 to generate an interrupt if enabled. + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) The PVD is stopped in STANDBY mode. + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** Wake-up pin configuration *** + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ================================= + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) Wake-up pin is used to wake up the system from STANDBY mode. + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The pin pull is configurable through the WKUPEPR register to be in + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** No-pull, Pull-up and Pull-down. + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The pin polarity is configurable through the WKUPEPR register to be + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** active on rising or falling edges. + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) There are up to six Wake-up pin in the STM32H7 devices family. + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** Low Power modes configuration *** + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ===================================== + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The device present 3 principles low-power modes features: + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** active (Powered and Clocked). + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + ARM GAS /tmp/cc1wCtPf.s page 8 + + + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** regulator is running. The Main regulator or the LP + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** regulator could be selected. + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** supply regulator is powered off. + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** SLEEP mode *** + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ================== + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) Entry: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SLEEPEntry) function. + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction. + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction. + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** -@@- The Regulator parameter is not used for the STM32H7 family + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** and is kept as parameter just to maintain compatibility with the + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** lower power families (STM32L). + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) Exit: + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Any peripheral interrupt acknowledged by the nested vectored interrupt + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** controller (NVIC) can wake up the device from SLEEP mode. + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** STOP mode *** + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ================= + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL, + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** the HSI, and the HSE RC oscillators are disabled. Internal SRAM and + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** register contents are preserved. + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode. + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** To minimize the consumption in STOP mode, FLASH can be powered off before + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** It can be switched on again by software after exiting the STOP mode using + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** the HAL_PWREx_DisableFlashPowerDown() function. + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) Entry: + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** STOPEntry) function with: + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) Regulator: + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+++) PWR_MAINREGULATOR_ON: Main regulator ON. + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) STOPEntry: + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction. + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction. + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) Exit: + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** STANDBY mode *** + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ==================== + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The system STANDBY mode allows to achieve the lowest power consumption. + ARM GAS /tmp/cc1wCtPf.s page 9 + + + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** disabled. The system is consequently powered off. The PLL, the HSI + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** oscillator and the HSE oscillator are also switched off. SRAM and register + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** contents are lost except for the RTC registers, RTC backup registers, + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** backup SRAM and standby circuitry. + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** The voltage regulator is OFF. + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) Entry: + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** function. + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) Exit: + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** RTC wakeup, tamper event, time stamp event, external reset in NRST + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** pin, IWDG reset. + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ============================================= + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** RTC Wakeup event, a tamper event or a time-stamp event, without + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** depending on an external interrupt (Auto-wakeup mode). + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) To wake up from the STOP mode with an RTC alarm event, it is + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** necessary to configure the RTC to generate the RTC alarm using the + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_RTC_SetAlarm_IT() function. + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** it is necessary to configure the RTC to detect the tamper or time + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_RTCEx_SetTamper_IT() functions. + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** (++) To wake up from the STOP mode with an RTC WakeUp event, it is + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** necessary to configure the RTC to generate the RTC WakeUp event + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** using the HAL_RTCEx_SetWakeUpTimer_IT() function. + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @endverbatim + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Configure the event mode and the voltage threshold detected by the + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Programmable Voltage Detector(PVD). + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * the configuration information for the PVD. + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * detection level. + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note For dual core devices, please ensure to configure the EXTI lines for + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * the different Cortex-Mx through PWR_Exported_Macro provided by this + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * driver. All combination are allowed: wake up only Cortex-M7, wake up + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + ARM GAS /tmp/cc1wCtPf.s page 10 + + + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 107 .loc 1 417 1 is_stmt 1 view -0 + 108 .cfi_startproc + 109 @ args = 0, pretend = 0, frame = 0 + 110 @ frame_needed = 0, uses_anonymous_args = 0 + 111 @ link register save eliminated. + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check the PVD configuration parameter */ + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (sConfigPVD == NULL) + 112 .loc 1 419 3 view .LVU9 + 113 .loc 1 419 6 is_stmt 0 view .LVU10 + 114 0000 0246 mov r2, r0 + 115 0002 0028 cmp r0, #0 + 116 0004 48D0 beq .L8 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** return; + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check the parameters */ + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); + 117 .loc 1 425 3 is_stmt 1 view .LVU11 + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); + 118 .loc 1 426 3 view .LVU12 + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + 119 .loc 1 429 3 view .LVU13 + 120 0006 2549 ldr r1, .L13 + 121 0008 0B68 ldr r3, [r1] + 122 000a 23F0E003 bic r3, r3, #224 + 123 000e 0068 ldr r0, [r0] + 124 .LVL1: + 125 .loc 1 429 3 is_stmt 0 view .LVU14 + 126 0010 0343 orrs r3, r3, r0 + 127 0012 0B60 str r3, [r1] + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear previous config */ + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if !defined (DUAL_CORE) + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); + 128 .loc 1 433 3 is_stmt 1 view .LVU15 + 129 0014 4FF0B043 mov r3, #1476395008 + 130 0018 D3F88410 ldr r1, [r3, #132] + 131 001c 21F48031 bic r1, r1, #65536 + 132 0020 C3F88410 str r1, [r3, #132] + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT (); + 133 .loc 1 434 3 view .LVU16 + 134 0024 D3F88010 ldr r1, [r3, #128] + 135 0028 21F48031 bic r1, r1, #65536 + 136 002c C3F88010 str r1, [r3, #128] + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* !defined (DUAL_CORE) */ + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); + 137 .loc 1 437 3 view .LVU17 + 138 0030 1968 ldr r1, [r3] + 139 0032 21F48031 bic r1, r1, #65536 + 140 0036 1960 str r1, [r3] + ARM GAS /tmp/cc1wCtPf.s page 11 + + + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); + 141 .loc 1 438 3 view .LVU18 + 142 0038 5968 ldr r1, [r3, #4] + 143 003a 21F48031 bic r1, r1, #65536 + 144 003e 5960 str r1, [r3, #4] + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if !defined (DUAL_CORE) + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Interrupt mode configuration */ + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + 145 .loc 1 442 3 view .LVU19 + 146 .loc 1 442 18 is_stmt 0 view .LVU20 + 147 0040 5368 ldr r3, [r2, #4] + 148 .loc 1 442 6 view .LVU21 + 149 0042 13F4803F tst r3, #65536 + 150 0046 07D0 beq .L10 + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT (); + 151 .loc 1 444 5 is_stmt 1 view .LVU22 + 152 0048 4FF0B041 mov r1, #1476395008 + 153 004c D1F88030 ldr r3, [r1, #128] + 154 0050 43F48033 orr r3, r3, #65536 + 155 0054 C1F88030 str r3, [r1, #128] + 156 .L10: + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Event mode configuration */ + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + 157 .loc 1 448 3 view .LVU23 + 158 .loc 1 448 18 is_stmt 0 view .LVU24 + 159 0058 5368 ldr r3, [r2, #4] + 160 .loc 1 448 6 view .LVU25 + 161 005a 13F4003F tst r3, #131072 + 162 005e 07D0 beq .L11 + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); + 163 .loc 1 450 5 is_stmt 1 view .LVU26 + 164 0060 4FF0B041 mov r1, #1476395008 + 165 0064 D1F88430 ldr r3, [r1, #132] + 166 0068 43F48033 orr r3, r3, #65536 + 167 006c C1F88430 str r3, [r1, #132] + 168 .L11: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* !defined (DUAL_CORE) */ + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Rising edge configuration */ + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + 169 .loc 1 455 3 view .LVU27 + 170 .loc 1 455 18 is_stmt 0 view .LVU28 + 171 0070 5368 ldr r3, [r2, #4] + 172 .loc 1 455 6 view .LVU29 + 173 0072 13F0010F tst r3, #1 + 174 0076 05D0 beq .L12 + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); + 175 .loc 1 457 5 is_stmt 1 view .LVU30 + 176 0078 4FF0B041 mov r1, #1476395008 + 177 007c 0B68 ldr r3, [r1] + ARM GAS /tmp/cc1wCtPf.s page 12 + + + 178 007e 43F48033 orr r3, r3, #65536 + 179 0082 0B60 str r3, [r1] + 180 .L12: + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Falling edge configuration */ + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + 181 .loc 1 461 3 view .LVU31 + 182 .loc 1 461 18 is_stmt 0 view .LVU32 + 183 0084 5368 ldr r3, [r2, #4] + 184 .loc 1 461 6 view .LVU33 + 185 0086 13F0020F tst r3, #2 + 186 008a 05D0 beq .L8 + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); + 187 .loc 1 463 5 is_stmt 1 view .LVU34 + 188 008c 4FF0B042 mov r2, #1476395008 + 189 .LVL2: + 190 .loc 1 463 5 is_stmt 0 view .LVU35 + 191 0090 5368 ldr r3, [r2, #4] + 192 0092 43F48033 orr r3, r3, #65536 + 193 0096 5360 str r3, [r2, #4] + 194 .L8: + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 195 .loc 1 465 1 view .LVU36 + 196 0098 7047 bx lr + 197 .L14: + 198 009a 00BF .align 2 + 199 .L13: + 200 009c 00480258 .word 1476544512 + 201 .cfi_endproc + 202 .LFE144: + 204 .section .text.HAL_PWR_EnablePVD,"ax",%progbits + 205 .align 1 + 206 .global HAL_PWR_EnablePVD + 207 .syntax unified + 208 .thumb + 209 .thumb_func + 210 .fpu fpv5-d16 + 212 HAL_PWR_EnablePVD: + 213 .LFB145: + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enable the Programmable Voltage Detector (PVD). + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnablePVD (void) + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 214 .loc 1 472 1 is_stmt 1 view -0 + 215 .cfi_startproc + 216 @ args = 0, pretend = 0, frame = 0 + 217 @ frame_needed = 0, uses_anonymous_args = 0 + 218 @ link register save eliminated. + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Enable the power voltage detector */ + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CR1, PWR_CR1_PVDEN); + 219 .loc 1 474 3 view .LVU38 + ARM GAS /tmp/cc1wCtPf.s page 13 + + + 220 0000 024A ldr r2, .L16 + 221 0002 1368 ldr r3, [r2] + 222 0004 43F01003 orr r3, r3, #16 + 223 0008 1360 str r3, [r2] + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 224 .loc 1 475 1 is_stmt 0 view .LVU39 + 225 000a 7047 bx lr + 226 .L17: + 227 .align 2 + 228 .L16: + 229 000c 00480258 .word 1476544512 + 230 .cfi_endproc + 231 .LFE145: + 233 .section .text.HAL_PWR_DisablePVD,"ax",%progbits + 234 .align 1 + 235 .global HAL_PWR_DisablePVD + 236 .syntax unified + 237 .thumb + 238 .thumb_func + 239 .fpu fpv5-d16 + 241 HAL_PWR_DisablePVD: + 242 .LFB146: + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Disable the Programmable Voltage Detector (PVD). + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_DisablePVD (void) + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 243 .loc 1 482 1 is_stmt 1 view -0 + 244 .cfi_startproc + 245 @ args = 0, pretend = 0, frame = 0 + 246 @ frame_needed = 0, uses_anonymous_args = 0 + 247 @ link register save eliminated. + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Disable the power voltage detector */ + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN); + 248 .loc 1 484 3 view .LVU41 + 249 0000 024A ldr r2, .L19 + 250 0002 1368 ldr r3, [r2] + 251 0004 23F01003 bic r3, r3, #16 + 252 0008 1360 str r3, [r2] + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 253 .loc 1 485 1 is_stmt 0 view .LVU42 + 254 000a 7047 bx lr + 255 .L20: + 256 .align 2 + 257 .L19: + 258 000c 00480258 .word 1476544512 + 259 .cfi_endproc + 260 .LFE146: + 262 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits + 263 .align 1 + 264 .global HAL_PWR_EnableWakeUpPin + 265 .syntax unified + 266 .thumb + 267 .thumb_func + 268 .fpu fpv5-d16 + ARM GAS /tmp/cc1wCtPf.s page 14 + + + 270 HAL_PWR_EnableWakeUpPin: + 271 .LVL3: + 272 .LFB147: + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enable the WakeUp PINx functionality. + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This parameter can be one of the following legacy values, which + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * sets the default (rising edge): + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6. + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * or one of the following values where the user can explicitly states + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * the enabled pin and the chosen polarity: + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * GPIOI port. + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity) + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 273 .loc 1 509 1 is_stmt 1 view -0 + 274 .cfi_startproc + 275 @ args = 0, pretend = 0, frame = 0 + 276 @ frame_needed = 0, uses_anonymous_args = 0 + 277 @ link register save eliminated. + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check the parameters */ + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity)); + 278 .loc 1 511 3 view .LVU44 + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** Enable and Specify the Wake-Up pin polarity and the pull configuration + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** for the event detection (rising or falling edge). + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity); + 279 .loc 1 517 3 view .LVU45 + 280 0000 034A ldr r2, .L22 + 281 0002 916A ldr r1, [r2, #40] + 282 0004 034B ldr r3, .L22+4 + 283 0006 0B40 ands r3, r3, r1 + 284 0008 0343 orrs r3, r3, r0 + 285 000a 9362 str r3, [r2, #40] + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 286 .loc 1 518 1 is_stmt 0 view .LVU46 + 287 000c 7047 bx lr + 288 .L23: + 289 000e 00BF .align 2 + 290 .L22: + 291 0010 00480258 .word 1476544512 + 292 0014 C0C000F0 .word -268386112 + 293 .cfi_endproc + ARM GAS /tmp/cc1wCtPf.s page 15 + + + 294 .LFE147: + 296 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits + 297 .align 1 + 298 .global HAL_PWR_DisableWakeUpPin + 299 .syntax unified + 300 .thumb + 301 .thumb_func + 302 .fpu fpv5-d16 + 304 HAL_PWR_DisableWakeUpPin: + 305 .LVL4: + 306 .LFB148: + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Disable the WakeUp PINx functionality. + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This parameter can be one of the following values: + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * GPIOI port. + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx) + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 307 .loc 1 538 1 is_stmt 1 view -0 + 308 .cfi_startproc + 309 @ args = 0, pretend = 0, frame = 0 + 310 @ frame_needed = 0, uses_anonymous_args = 0 + 311 @ link register save eliminated. + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check the parameters */ + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx)); + 312 .loc 1 540 3 view .LVU48 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Disable the wake up pin selected */ + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); + 313 .loc 1 543 3 view .LVU49 + 314 0000 034A ldr r2, .L25 + 315 0002 936A ldr r3, [r2, #40] + 316 0004 00F03F00 and r0, r0, #63 + 317 .LVL5: + 318 .loc 1 543 3 is_stmt 0 view .LVU50 + 319 0008 23EA0003 bic r3, r3, r0 + 320 000c 9362 str r3, [r2, #40] + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 321 .loc 1 544 1 view .LVU51 + 322 000e 7047 bx lr + 323 .L26: + 324 .align 2 + 325 .L25: + 326 0010 00480258 .word 1476544512 + ARM GAS /tmp/cc1wCtPf.s page 16 + + + 327 .cfi_endproc + 328 .LFE148: + 330 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits + 331 .align 1 + 332 .global HAL_PWR_EnterSLEEPMode + 333 .syntax unified + 334 .thumb + 335 .thumb_func + 336 .fpu fpv5-d16 + 338 HAL_PWR_EnterSLEEPMode: + 339 .LVL6: + 340 .LFB149: + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enter the current core in SLEEP mode (CSLEEP). + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param Regulator : Specifies the regulator state in SLEEP mode. + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This parameter can be one of the following values: + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON. + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * regulator ON. + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note This parameter is not used for the STM32H7 family and is kept as + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * parameter just to maintain compatibility with the lower power + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * families. + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * intrinsic instruction. + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This parameter can be one of the following values: + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction. + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction. + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note Ensure to clear pending events before calling this API through + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE. + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry) + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 341 .loc 1 566 1 is_stmt 1 view -0 + 342 .cfi_startproc + 343 @ args = 0, pretend = 0, frame = 0 + 344 @ frame_needed = 0, uses_anonymous_args = 0 + 345 @ link register save eliminated. + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check the parameters */ + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_REGULATOR (Regulator)); + 346 .loc 1 568 3 view .LVU53 + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry)); + 347 .loc 1 569 3 view .LVU54 + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 348 .loc 1 572 3 view .LVU55 + 349 0000 054A ldr r2, .L31 + 350 0002 1369 ldr r3, [r2, #16] + 351 0004 23F00403 bic r3, r3, #4 + 352 0008 1361 str r3, [r2, #16] + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Select SLEEP mode entry */ + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + 353 .loc 1 575 3 view .LVU56 + 354 .loc 1 575 6 is_stmt 0 view .LVU57 + ARM GAS /tmp/cc1wCtPf.s page 17 + + + 355 000a 0129 cmp r1, #1 + 356 000c 01D0 beq .L30 + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __WFI (); + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** else + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Request Wait For Event */ + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __WFE (); + 357 .loc 1 583 5 is_stmt 1 view .LVU58 + 358 .syntax unified + 359 @ 583 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c" 1 + 360 000e 20BF wfe + 361 @ 0 "" 2 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 362 .loc 1 585 1 is_stmt 0 view .LVU59 + 363 .thumb + 364 .syntax unified + 365 0010 7047 bx lr + 366 .L30: + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 367 .loc 1 578 5 is_stmt 1 view .LVU60 + 368 .syntax unified + 369 @ 578 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c" 1 + 370 0012 30BF wfi + 371 @ 0 "" 2 + 372 .thumb + 373 .syntax unified + 374 0014 7047 bx lr + 375 .L32: + 376 0016 00BF .align 2 + 377 .L31: + 378 0018 00ED00E0 .word -536810240 + 379 .cfi_endproc + 380 .LFE149: + 382 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits + 383 .align 1 + 384 .global HAL_PWR_EnterSTOPMode + 385 .syntax unified + 386 .thumb + 387 .thumb_func + 388 .fpu fpv5-d16 + 390 HAL_PWR_EnterSTOPMode: + 391 .LVL7: + 392 .LFB150: + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enter STOP mode. + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note For single core devices, this API will enter the system in STOP mode + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * cleared. + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * For dual core devices, this API will enter the domain (containing + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Cortex-Mx that executing this function) in DSTOP mode. If all + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * cleared, all the system will enter in STOP mode. + ARM GAS /tmp/cc1wCtPf.s page 18 + + + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param Regulator : Specifies the regulator state in STOP mode. + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This parameter can be one of the following values: + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * regulator ON. + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * intrinsic instruction. + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * This parameter can be one of the following values: + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note When exiting System STOP mode by issuing an interrupt or a wakeup + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * event, the HSI RC oscillator is selected as default system wakeup + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * clock. + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note In System STOP mode, when the voltage regulator operates in low + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * power mode, an additional startup delay is incurred when the system + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * is waking up. By keeping the internal regulator ON during STOP mode, + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * the consumption is higher although the startup time is reduced. + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry) + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 393 .loc 1 617 1 view -0 + 394 .cfi_startproc + 395 @ args = 0, pretend = 0, frame = 0 + 396 @ frame_needed = 0, uses_anonymous_args = 0 + 397 @ link register save eliminated. + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check the parameters */ + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_REGULATOR (Regulator)); + 398 .loc 1 619 3 view .LVU62 + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + 399 .loc 1 620 3 view .LVU63 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Select the regulator state in STOP mode */ + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + 400 .loc 1 623 3 view .LVU64 + 401 0000 104B ldr r3, .L37 + 402 0002 1A68 ldr r2, [r3] + 403 0004 22F00102 bic r2, r2, #1 + 404 0008 0243 orrs r2, r2, r0 + 405 000a 1A60 str r2, [r3] + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Configure the PWR mode for the different Domains */ + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (DUAL_CORE) + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check CPU ID */ + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */ + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** else + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */ + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #else /* Single core devices */ + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + ARM GAS /tmp/cc1wCtPf.s page 19 + + + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + 406 .loc 1 640 3 view .LVU65 + 407 000c 1A69 ldr r2, [r3, #16] + 408 000e 22F00502 bic r2, r2, #5 + 409 0012 1A61 str r2, [r3, #16] + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (PWR_CPUCR_PDDS_D2) + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); + 410 .loc 1 644 3 view .LVU66 + 411 0014 1A69 ldr r2, [r3, #16] + 412 0016 22F00202 bic r2, r2, #2 + 413 001a 1A61 str r2, [r3, #16] + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* PWR_CPUCR_PDDS_D2 */ + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* defined (DUAL_CORE) */ + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 414 .loc 1 649 3 view .LVU67 + 415 001c 0A4A ldr r2, .L37+4 + 416 001e 1369 ldr r3, [r2, #16] + 417 0020 43F00403 orr r3, r3, #4 + 418 0024 1361 str r3, [r2, #16] + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Ensure that all instructions are done before entering STOP mode */ + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __DSB (); + 419 .loc 1 652 3 view .LVU68 + 420 .LBB10: + 421 .LBI10: + 422 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc1wCtPf.s page 20 + + + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + ARM GAS /tmp/cc1wCtPf.s page 21 + + + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/cc1wCtPf.s page 22 + + + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc1wCtPf.s page 23 + + + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc1wCtPf.s page 24 + + + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + ARM GAS /tmp/cc1wCtPf.s page 25 + + + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc1wCtPf.s page 26 + + + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + ARM GAS /tmp/cc1wCtPf.s page 27 + + + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/cc1wCtPf.s page 28 + + + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + ARM GAS /tmp/cc1wCtPf.s page 29 + + + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + ARM GAS /tmp/cc1wCtPf.s page 30 + + + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc1wCtPf.s page 31 + + + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/cc1wCtPf.s page 32 + + + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + ARM GAS /tmp/cc1wCtPf.s page 33 + + + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + ARM GAS /tmp/cc1wCtPf.s page 34 + + + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 423 .loc 2 877 27 view .LVU69 + 424 .LBB11: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 425 .loc 2 879 3 view .LVU70 + ARM GAS /tmp/cc1wCtPf.s page 35 + + + 426 .syntax unified + 427 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 428 0026 BFF34F8F dsb 0xF + 429 @ 0 "" 2 + 430 .thumb + 431 .syntax unified + 432 .LBE11: + 433 .LBE10: + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __ISB (); + 434 .loc 1 653 3 view .LVU71 + 435 .LBB12: + 436 .LBI12: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 437 .loc 2 866 27 view .LVU72 + 438 .LBB13: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 439 .loc 2 868 3 view .LVU73 + 440 .syntax unified + 441 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 442 002a BFF36F8F isb 0xF + 443 @ 0 "" 2 + 444 .thumb + 445 .syntax unified + 446 .LBE13: + 447 .LBE12: + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Select STOP mode entry */ + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (STOPEntry == PWR_STOPENTRY_WFI) + 448 .loc 1 656 3 view .LVU74 + 449 .loc 1 656 6 is_stmt 0 view .LVU75 + 450 002e 0129 cmp r1, #1 + 451 0030 06D0 beq .L36 + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __WFI (); + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** else + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Request Wait For Event */ + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __WFE (); + 452 .loc 1 664 5 is_stmt 1 view .LVU76 + 453 .syntax unified + 454 @ 664 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c" 1 + 455 0032 20BF wfe + 456 @ 0 "" 2 + 457 .thumb + 458 .syntax unified + 459 .L35: + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 460 .loc 1 668 3 view .LVU77 + 461 0034 044A ldr r2, .L37+4 + 462 0036 1369 ldr r3, [r2, #16] + 463 0038 23F00403 bic r3, r3, #4 + 464 003c 1361 str r3, [r2, #16] + ARM GAS /tmp/cc1wCtPf.s page 36 + + + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 465 .loc 1 669 1 is_stmt 0 view .LVU78 + 466 003e 7047 bx lr + 467 .L36: + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 468 .loc 1 659 5 is_stmt 1 view .LVU79 + 469 .syntax unified + 470 @ 659 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c" 1 + 471 0040 30BF wfi + 472 @ 0 "" 2 + 473 .thumb + 474 .syntax unified + 475 0042 F7E7 b .L35 + 476 .L38: + 477 .align 2 + 478 .L37: + 479 0044 00480258 .word 1476544512 + 480 0048 00ED00E0 .word -536810240 + 481 .cfi_endproc + 482 .LFE150: + 484 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits + 485 .align 1 + 486 .global HAL_PWR_EnterSTANDBYMode + 487 .syntax unified + 488 .thumb + 489 .thumb_func + 490 .fpu fpv5-d16 + 492 HAL_PWR_EnterSTANDBYMode: + 493 .LFB151: + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enter STANDBY mode. + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note For single core devices, this API will enter the system in STANDBY + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * regiter is cleared. + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * For dual core devices, this API will enter the domain (containing + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Cortex-Mx that executing this function) in DSTANDBY mode. If all + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * is cleared, all the system will enter in STANDBY mode. + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note The system enters Standby mode only when all domains are in DSTANDBY. + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note When the System exit STANDBY mode by issuing an interrupt or a + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * wakeup event, the HSI RC oscillator is selected as system clock. + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note It is recommended to disable all regulators before entring STANDBY + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * mode for power consumption saving purpose. + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode (void) + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 494 .loc 1 688 1 view -0 + 495 .cfi_startproc + 496 @ args = 0, pretend = 0, frame = 0 + 497 @ frame_needed = 0, uses_anonymous_args = 0 + 498 @ link register save eliminated. + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Configure the PWR mode for the different Domains */ + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (DUAL_CORE) + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check CPU ID */ + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) + ARM GAS /tmp/cc1wCtPf.s page 37 + + + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3)); + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** else + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */ + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3)); + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #else /* Single core devices */ + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + 499 .loc 1 706 3 view .LVU81 + 500 0000 094B ldr r3, .L40 + 501 0002 1A69 ldr r2, [r3, #16] + 502 0004 42F00502 orr r2, r2, #5 + 503 0008 1A61 str r2, [r3, #16] + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (PWR_CPUCR_PDDS_D2) + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); + 504 .loc 1 710 3 view .LVU82 + 505 000a 1A69 ldr r2, [r3, #16] + 506 000c 42F00202 orr r2, r2, #2 + 507 0010 1A61 str r2, [r3, #16] + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* PWR_CPUCR_PDDS_D2 */ + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* defined (DUAL_CORE) */ + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 508 .loc 1 715 3 view .LVU83 + 509 0012 064A ldr r2, .L40+4 + 510 0014 1369 ldr r3, [r2, #16] + 511 0016 43F00403 orr r3, r3, #4 + 512 001a 1361 str r3, [r2, #16] + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Ensure that all instructions are done before entering STOP mode */ + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __DSB (); + 513 .loc 1 718 3 view .LVU84 + 514 .LBB14: + 515 .LBI14: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 516 .loc 2 877 27 view .LVU85 + 517 .LBB15: + 518 .loc 2 879 3 view .LVU86 + 519 .syntax unified + 520 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 521 001c BFF34F8F dsb 0xF + 522 @ 0 "" 2 + 523 .thumb + 524 .syntax unified + 525 .LBE15: + 526 .LBE14: + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __ISB (); + 527 .loc 1 719 3 view .LVU87 + ARM GAS /tmp/cc1wCtPf.s page 38 + + + 528 .LBB16: + 529 .LBI16: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 530 .loc 2 866 27 view .LVU88 + 531 .LBB17: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 532 .loc 2 868 3 view .LVU89 + 533 .syntax unified + 534 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 535 0020 BFF36F8F isb 0xF + 536 @ 0 "" 2 + 537 .thumb + 538 .syntax unified + 539 .LBE17: + 540 .LBE16: + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (__CC_ARM) + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __force_stores(); + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* defined (__CC_ARM) */ + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __WFI (); + 541 .loc 1 727 3 view .LVU90 + 542 .syntax unified + 543 @ 727 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c" 1 + 544 0024 30BF wfi + 545 @ 0 "" 2 + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 546 .loc 1 728 1 is_stmt 0 view .LVU91 + 547 .thumb + 548 .syntax unified + 549 0026 7047 bx lr + 550 .L41: + 551 .align 2 + 552 .L40: + 553 0028 00480258 .word 1476544512 + 554 002c 00ED00E0 .word -536810240 + 555 .cfi_endproc + 556 .LFE151: + 558 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits + 559 .align 1 + 560 .global HAL_PWR_EnableSleepOnExit + 561 .syntax unified + 562 .thumb + 563 .thumb_func + 564 .fpu fpv5-d16 + 566 HAL_PWR_EnableSleepOnExit: + 567 .LFB152: + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Thread mode. + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * processor re-enters SLEEP mode when an interruption handling is over. + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * only on interruptions handling. + ARM GAS /tmp/cc1wCtPf.s page 39 + + + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit (void) + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 568 .loc 1 740 1 is_stmt 1 view -0 + 569 .cfi_startproc + 570 @ args = 0, pretend = 0, frame = 0 + 571 @ frame_needed = 0, uses_anonymous_args = 0 + 572 @ link register save eliminated. + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */ + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); + 573 .loc 1 742 3 view .LVU93 + 574 0000 024A ldr r2, .L43 + 575 0002 1369 ldr r3, [r2, #16] + 576 0004 43F00203 orr r3, r3, #2 + 577 0008 1361 str r3, [r2, #16] + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 578 .loc 1 743 1 is_stmt 0 view .LVU94 + 579 000a 7047 bx lr + 580 .L44: + 581 .align 2 + 582 .L43: + 583 000c 00ED00E0 .word -536810240 + 584 .cfi_endproc + 585 .LFE152: + 587 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits + 588 .align 1 + 589 .global HAL_PWR_DisableSleepOnExit + 590 .syntax unified + 591 .thumb + 592 .thumb_func + 593 .fpu fpv5-d16 + 595 HAL_PWR_DisableSleepOnExit: + 596 .LFB153: + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Disable Sleep-On-Exit feature when returning from Handler mode to + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * Thread mode. + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * processor re-enters SLEEP mode when an interruption handling is over. + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit (void) + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 597 .loc 1 753 1 is_stmt 1 view -0 + 598 .cfi_startproc + 599 @ args = 0, pretend = 0, frame = 0 + 600 @ frame_needed = 0, uses_anonymous_args = 0 + 601 @ link register save eliminated. + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */ + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); + 602 .loc 1 755 3 view .LVU96 + 603 0000 024A ldr r2, .L46 + 604 0002 1369 ldr r3, [r2, #16] + 605 0004 23F00203 bic r3, r3, #2 + 606 0008 1361 str r3, [r2, #16] + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + ARM GAS /tmp/cc1wCtPf.s page 40 + + + 607 .loc 1 756 1 is_stmt 0 view .LVU97 + 608 000a 7047 bx lr + 609 .L47: + 610 .align 2 + 611 .L46: + 612 000c 00ED00E0 .word -536810240 + 613 .cfi_endproc + 614 .LFE153: + 616 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits + 617 .align 1 + 618 .global HAL_PWR_EnableSEVOnPend + 619 .syntax unified + 620 .thumb + 621 .thumb_func + 622 .fpu fpv5-d16 + 624 HAL_PWR_EnableSEVOnPend: + 625 .LFB154: + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Enable CORTEX SEVONPEND feature. + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * pending event / interrupt even if it's disabled or has insufficient + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * priority to cause exception entry wakes up the Cortex-Mx. + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend (void) + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 626 .loc 1 766 1 is_stmt 1 view -0 + 627 .cfi_startproc + 628 @ args = 0, pretend = 0, frame = 0 + 629 @ frame_needed = 0, uses_anonymous_args = 0 + 630 @ link register save eliminated. + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex-Mx System Control Register */ + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); + 631 .loc 1 768 3 view .LVU99 + 632 0000 024A ldr r2, .L49 + 633 0002 1369 ldr r3, [r2, #16] + 634 0004 43F01003 orr r3, r3, #16 + 635 0008 1361 str r3, [r2, #16] + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 636 .loc 1 769 1 is_stmt 0 view .LVU100 + 637 000a 7047 bx lr + 638 .L50: + 639 .align 2 + 640 .L49: + 641 000c 00ED00E0 .word -536810240 + 642 .cfi_endproc + 643 .LFE154: + 645 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits + 646 .align 1 + 647 .global HAL_PWR_DisableSEVOnPend + 648 .syntax unified + 649 .thumb + 650 .thumb_func + 651 .fpu fpv5-d16 + 653 HAL_PWR_DisableSEVOnPend: + 654 .LFB155: + ARM GAS /tmp/cc1wCtPf.s page 41 + + + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Disable CORTEX SEVONPEND feature. + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * enabled pending causes exception entry wakes up the Cortex-Mx. + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend (void) + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 655 .loc 1 778 1 is_stmt 1 view -0 + 656 .cfi_startproc + 657 @ args = 0, pretend = 0, frame = 0 + 658 @ frame_needed = 0, uses_anonymous_args = 0 + 659 @ link register save eliminated. + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); + 660 .loc 1 780 3 view .LVU102 + 661 0000 024A ldr r2, .L52 + 662 0002 1369 ldr r3, [r2, #16] + 663 0004 23F01003 bic r3, r3, #16 + 664 0008 1361 str r3, [r2, #16] + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 665 .loc 1 781 1 is_stmt 0 view .LVU103 + 666 000a 7047 bx lr + 667 .L53: + 668 .align 2 + 669 .L52: + 670 000c 00ED00E0 .word -536810240 + 671 .cfi_endproc + 672 .LFE155: + 674 .section .text.HAL_PWR_PVDCallback,"ax",%progbits + 675 .align 1 + 676 .weak HAL_PWR_PVDCallback + 677 .syntax unified + 678 .thumb + 679 .thumb_func + 680 .fpu fpv5-d16 + 682 HAL_PWR_PVDCallback: + 683 .LFB157: + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @} + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief Interrupt Handling functions + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @verbatim + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** =============================================================================== + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** ##### Interrupt Handling Functions ##### + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** =============================================================================== + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** [..] + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** This section provides functions allowing to handle the PVD pending + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** interrupts. + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** @endverbatim + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @{ + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + ARM GAS /tmp/cc1wCtPf.s page 42 + + + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @note This API should be called under the PVD_AVD_IRQHandler(). + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler (void) + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (DUAL_CORE) + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check Cortex-Mx ID */ + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check PWR EXTI D1 flag */ + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear PWR EXTI D1 pending bit */ + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_PWR_PVDCallback (); + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** else + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Check PWR EXTI D2 flag */ + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear PWR EXTI D2 pending bit */ + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTID2_CLEAR_FLAG (); + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_PWR_PVDCallback (); + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #else /* Single core devices */ + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* PVD EXTI line interrupt detected */ + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* Clear PWR EXTI pending bit */ + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** HAL_PWR_PVDCallback (); + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #endif /* defined (DUAL_CORE) */ + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /** + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @brief PWR PVD interrupt callback. + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** * @retval None. + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback (void) + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 684 .loc 1 852 1 is_stmt 1 view -0 + 685 .cfi_startproc + 686 @ args = 0, pretend = 0, frame = 0 + 687 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc1wCtPf.s page 43 + + + 688 @ link register save eliminated. + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** /* NOTE : This function should not be modified, when the callback is needed, + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** the HAL_PWR_PVDCallback can be implemented in the user file + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** */ + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 689 .loc 1 856 1 view .LVU105 + 690 0000 7047 bx lr + 691 .cfi_endproc + 692 .LFE157: + 694 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits + 695 .align 1 + 696 .global HAL_PWR_PVD_IRQHandler + 697 .syntax unified + 698 .thumb + 699 .thumb_func + 700 .fpu fpv5-d16 + 702 HAL_PWR_PVD_IRQHandler: + 703 .LFB156: + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** #if defined (DUAL_CORE) + 704 .loc 1 807 1 view -0 + 705 .cfi_startproc + 706 @ args = 0, pretend = 0, frame = 0 + 707 @ frame_needed = 0, uses_anonymous_args = 0 + 708 0000 08B5 push {r3, lr} + 709 .LCFI0: + 710 .cfi_def_cfa_offset 8 + 711 .cfi_offset 3, -8 + 712 .cfi_offset 14, -4 + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 713 .loc 1 836 3 view .LVU107 + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 714 .loc 1 836 7 is_stmt 0 view .LVU108 + 715 0002 4FF0B043 mov r3, #1476395008 + 716 0006 D3F88830 ldr r3, [r3, #136] + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** { + 717 .loc 1 836 6 view .LVU109 + 718 000a 13F4803F tst r3, #65536 + 719 000e 00D1 bne .L58 + 720 .L55: + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 721 .loc 1 845 1 view .LVU110 + 722 0010 08BD pop {r3, pc} + 723 .L58: + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 724 .loc 1 839 5 is_stmt 1 view .LVU111 + 725 0012 4FF0B042 mov r2, #1476395008 + 726 0016 D2F88830 ldr r3, [r2, #136] + 727 001a 43F48033 orr r3, r3, #65536 + 728 001e C2F88830 str r3, [r2, #136] + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** } + 729 .loc 1 842 5 view .LVU112 + 730 0022 FFF7FEFF bl HAL_PWR_PVDCallback + 731 .LVL8: + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c **** + 732 .loc 1 845 1 is_stmt 0 view .LVU113 + 733 0026 F3E7 b .L55 + 734 .cfi_endproc + ARM GAS /tmp/cc1wCtPf.s page 44 + + + 735 .LFE156: + 737 .text + 738 .Letext0: + 739 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 740 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 741 .file 5 "Drivers/CMSIS/Include/core_cm7.h" + 742 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 743 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h" + ARM GAS /tmp/cc1wCtPf.s page 45 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_pwr.c + /tmp/cc1wCtPf.s:17 .text.HAL_PWR_DeInit:0000000000000000 $t + /tmp/cc1wCtPf.s:25 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit + /tmp/cc1wCtPf.s:39 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t + /tmp/cc1wCtPf.s:46 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess + /tmp/cc1wCtPf.s:63 .text.HAL_PWR_EnableBkUpAccess:000000000000000c $d + /tmp/cc1wCtPf.s:68 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t + /tmp/cc1wCtPf.s:75 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess + /tmp/cc1wCtPf.s:92 .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d + /tmp/cc1wCtPf.s:97 .text.HAL_PWR_ConfigPVD:0000000000000000 $t + /tmp/cc1wCtPf.s:104 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD + /tmp/cc1wCtPf.s:200 .text.HAL_PWR_ConfigPVD:000000000000009c $d + /tmp/cc1wCtPf.s:205 .text.HAL_PWR_EnablePVD:0000000000000000 $t + /tmp/cc1wCtPf.s:212 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD + /tmp/cc1wCtPf.s:229 .text.HAL_PWR_EnablePVD:000000000000000c $d + /tmp/cc1wCtPf.s:234 .text.HAL_PWR_DisablePVD:0000000000000000 $t + /tmp/cc1wCtPf.s:241 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD + /tmp/cc1wCtPf.s:258 .text.HAL_PWR_DisablePVD:000000000000000c $d + /tmp/cc1wCtPf.s:263 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t + /tmp/cc1wCtPf.s:270 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin + /tmp/cc1wCtPf.s:291 .text.HAL_PWR_EnableWakeUpPin:0000000000000010 $d + /tmp/cc1wCtPf.s:297 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t + /tmp/cc1wCtPf.s:304 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin + /tmp/cc1wCtPf.s:326 .text.HAL_PWR_DisableWakeUpPin:0000000000000010 $d + /tmp/cc1wCtPf.s:331 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t + /tmp/cc1wCtPf.s:338 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode + /tmp/cc1wCtPf.s:378 .text.HAL_PWR_EnterSLEEPMode:0000000000000018 $d + /tmp/cc1wCtPf.s:383 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t + /tmp/cc1wCtPf.s:390 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode + /tmp/cc1wCtPf.s:479 .text.HAL_PWR_EnterSTOPMode:0000000000000044 $d + /tmp/cc1wCtPf.s:485 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t + /tmp/cc1wCtPf.s:492 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode + /tmp/cc1wCtPf.s:553 .text.HAL_PWR_EnterSTANDBYMode:0000000000000028 $d + /tmp/cc1wCtPf.s:559 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t + /tmp/cc1wCtPf.s:566 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit + /tmp/cc1wCtPf.s:583 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d + /tmp/cc1wCtPf.s:588 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t + /tmp/cc1wCtPf.s:595 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit + /tmp/cc1wCtPf.s:612 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d + /tmp/cc1wCtPf.s:617 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t + /tmp/cc1wCtPf.s:624 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend + /tmp/cc1wCtPf.s:641 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d + /tmp/cc1wCtPf.s:646 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t + /tmp/cc1wCtPf.s:653 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend + /tmp/cc1wCtPf.s:670 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d + /tmp/cc1wCtPf.s:675 .text.HAL_PWR_PVDCallback:0000000000000000 $t + /tmp/cc1wCtPf.s:682 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback + /tmp/cc1wCtPf.s:695 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t + /tmp/cc1wCtPf.s:702 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_pwr.o b/build/stm32h7xx_hal_pwr.o new file mode 100644 index 0000000..69699e4 Binary files /dev/null and b/build/stm32h7xx_hal_pwr.o differ diff --git a/build/stm32h7xx_hal_pwr_ex.d b/build/stm32h7xx_hal_pwr_ex.d new file mode 100644 index 0000000..548b648 --- /dev/null +++ b/build/stm32h7xx_hal_pwr_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_pwr_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_pwr_ex.lst b/build/stm32h7xx_hal_pwr_ex.lst new file mode 100644 index 0000000..6349d36 --- /dev/null +++ b/build/stm32h7xx_hal_pwr_ex.lst @@ -0,0 +1,5671 @@ +ARM GAS /tmp/ccMGXY28.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_pwr_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_PWREx_ConfigSupply,"ax",%progbits + 17 .align 1 + 18 .global HAL_PWREx_ConfigSupply + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_PWREx_ConfigSupply: + 26 .LVL0: + 27 .LFB141: + 28 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @file stm32h7xx_hal_pwr_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * functionalities of PWR extension peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + Peripheral Extended features functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ============================================================================== + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### How to use this driver ##### + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** with the following different setups according to hardware (support SMPS): + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_DIRECT_SMPS_SUPPLY + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_1V8_SUPPLIES_LDO + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_2V5_SUPPLIES_LDO + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_1V8_SUPPLIES_EXT + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_SMPS_2V5_SUPPLIES_EXT + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_LDO_SUPPLY + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_EXTERNAL_SOURCE_SUPPLY + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** internal regulator output voltage. The voltage scaling could be one of + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the following scales : + ARM GAS /tmp/ccMGXY28.s page 2 + + + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE0 + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE1 + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE2 + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_VOLTAGE_SCALE3 + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** voltage applied to the main regulator. + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** main internal regulator output voltage in STOP mode. The voltage scaling + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in STOP mode could be one of the following scales : + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_SVOS_SCALE3 + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_SVOS_SCALE4 + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) PWR_REGULATOR_SVOS_SCALE5 + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** output voltage applied to the main regulator in STOP mode. + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** with core domain in D2STOP mode. This API is used only for STM32H7Axxx + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** and STM32H7Bxxx devices. + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Please ensure to clear all CPU pending events by calling + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in DEEP-SLEEP mode with __WFE() entry. + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** DSTOP mode. Call this API with all available power domains to enter the + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** system in STOP mode. + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Please ensure to clear all CPU pending events by calling + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in DEEP-SLEEP mode with __WFE() entry. + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry. + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in DSTANDBY mode. Call this API with all available power domains to enter + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the system in STANDBY mode. + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (RUN/STOP) when the system enter to low power mode. + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** selected power domain. This API is used only for dual core devices. + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** and release the selected CPU and and their domain peripherals when + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** exiting STOP mode. These APIs are used only for dual core devices. + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableFlashPowerDown() and + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Flash Power Down in STOP mode. + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableMemoryShutOff() and + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** memory block shut-off in DStop or DStop2. These APIs are used only for + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** STM32H7Axxx and STM32H7Bxxx lines. + ARM GAS /tmp/ccMGXY28.s page 3 + + + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin() + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to enable and disable the Wake-up pin functionality for + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the selected pin. + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to manage wake-up flag for the selected pin. + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** pins interrupts. + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** to enable and disable the backup domain regulator. + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableUSBVoltageDetector() and + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regulation functionnalities. + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableBatteryCharging() and + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableBatteryCharging() functions to enable and disable the + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** battery charging feature with the selected resistor. + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableAnalogBooster() and + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableAnalogBooster() functions to enable and disable the + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** AVD boost feature when the VDD supply voltage is below 2V7. + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to enable and disable the VBAT and Temperature monitoring. + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When VBAT and Temperature monitoring feature is enables, use + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** respectively the Temperature level and VBAT level. + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring() + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function to get VDDMMC voltage level. This API is used only for + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** STM32H7Axxx and STM32H7Bxxx lines + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (event mode and voltage threshold) in order to set up the Analog Voltage + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD() + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** functions to start and stop the AVD detection. + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) AVD level could be one of the following values : + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 1V7 + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 2V1 + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 2V5 + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) 2V8 + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** AVD interrupt request. + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ****************************************************************************** + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @attention + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * All rights reserved.

+ 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + ARM GAS /tmp/ccMGXY28.s page 4 + + + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the "License"; You may not use this file except in compliance with the + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * License. You may obtain a copy of the License at: + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * opensource.org/licenses/BSD-3-Clause + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ****************************************************************************** + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/ + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #include "stm32h7xx_hal.h" + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR Extended HAL module driver + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private_Constants + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_MODE_IT (0x00010000U) + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_MODE_EVT (0x00020000U) + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_RISING_EDGE (0x00000001U) + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_FALLING_EDGE (0x00000002U) + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_RISING_FALLING_EDGE (0x00000003U) + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_FLAG_SETTING_DELAY (1000U) + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wake-Up Pins EXTI register mask */ + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (EXTI_IMR2_IM57) + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\ + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EXTI_IMR2_IM59 | EXTI_IMR2_IM60) + ARM GAS /tmp/ccMGXY28.s page 5 + + + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EXTI_IMR2_IM58 | EXTI_IMR2_IM60) + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (EXTI_IMR2_IM57) */ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wake-Up Pins PWR Pin Pull shift offsets */ + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/ + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/ + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private functions ---------------------------------------------------------*/ + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Exported types ------------------------------------------------------------*/ + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Exported functions --------------------------------------------------------*/ + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWREx Exported Functions + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Power supply control functions + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Power supply control functions ##### + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (#) When the system is powered on, the POR monitors VDD supply. Once VDD is + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** above the POR threshold level, the voltage regulator is enabled in the + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** default supply configuration: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The Voltage converter output level is set at 1V0 in accordance with + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the VOS3 level configured in PWR (D3/SRD) domain control register + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_D3CR/PWR_SRDCR). + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The system is kept in reset mode as long as VCORE is not ok. + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Once VCORE is ok, the system is taken out of reset and the HSI + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** oscillator is enabled. + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Once the oscillator is stable, the system is initialized: Flash memory + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** and option bytes are loaded and the CPU starts in Run* mode. + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The software shall then initialize the system including supply + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** configuration programming using the HAL_PWREx_ConfigSupply(). + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Once the supply configuration has been configured, the + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** control status register 1 (PWR_CSR1) to guarantee a valid voltage + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** levels: + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** system is in limited Run* mode, write accesses to the RAMs are not + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** permitted and VOS shall not be changed. + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Once ACTVOSRDY indicates that voltage levels are valid, the system + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** is in normal Run mode, write accesses to RAMs are allowed and VOS + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** can be changed. + ARM GAS /tmp/ccMGXY28.s page 6 + + + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the system Power Supply. + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param SupplySource : Specifies the Power Supply source to set after a + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * system startup. + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values : + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains. The LDO is Bypassed. + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the LDO. The Vcore Power Domains + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the LDO. + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the LDO. The Vcore Power Domains + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the LDO. + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * supplies external + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * circuits and the LDO. + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * The Vcore Power Domains + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * LDO. + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * supplies external + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * circuits and the LDO. + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * The Vcore Power Domains + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * are supplied from the + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * LDO. + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external circuits. The LDO is + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Bypassed. The Vcore Power + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains are supplied from + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external source. + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external circuits. The LDO is + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Bypassed. The Vcore Power + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains are supplied from + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external source. + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains. The SMPS regulator is Bypassed. + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Bypassed. The Vcore Power + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Domains are supplied from + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * external source. + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * H7 lines. + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator. + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 7 + + + 29 .loc 1 315 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 33 .loc 1 316 3 view .LVU1 + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_SUPPLY (SupplySource)); + 34 .loc 1 319 3 view .LVU2 + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if supply source was configured */ + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_FLAG_SCUEN) + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) + 35 .loc 1 323 3 view .LVU3 + 36 .loc 1 323 7 is_stmt 0 view .LVU4 + 37 0000 134B ldr r3, .L12 + 38 0002 DB68 ldr r3, [r3, #12] + 39 .loc 1 323 6 view .LVU5 + 40 0004 13F0040F tst r3, #4 + 41 0008 07D1 bne .L2 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_L + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_FLAG_SCUEN) */ + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check supply configuration */ + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + 42 .loc 1 329 5 is_stmt 1 view .LVU6 + 43 .loc 1 329 13 is_stmt 0 view .LVU7 + 44 000a 114B ldr r3, .L12 + 45 000c DB68 ldr r3, [r3, #12] + 46 .loc 1 329 19 view .LVU8 + 47 000e 03F00703 and r3, r3, #7 + 48 .loc 1 329 8 view .LVU9 + 49 0012 8342 cmp r3, r0 + 50 0014 1AD0 beq .L6 + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Supply configuration update locked, can't apply a new supply config */ + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 51 .loc 1 332 14 view .LVU10 + 52 0016 0120 movs r0, #1 + 53 .LVL1: + 54 .loc 1 332 14 view .LVU11 + 55 0018 7047 bx lr + 56 .LVL2: + 57 .L2: + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 58 .loc 1 315 1 view .LVU12 + 59 001a 10B5 push {r4, lr} + 60 .LCFI0: + 61 .cfi_def_cfa_offset 8 + 62 .cfi_offset 4, -8 + 63 .cfi_offset 14, -4 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Supply configuration update locked, but new supply configuration + ARM GAS /tmp/ccMGXY28.s page 8 + + + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** matches with old supply configuration : nothing to do + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the power supply configuration */ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); + 64 .loc 1 344 3 is_stmt 1 view .LVU13 + 65 001c 0C4A ldr r2, .L12 + 66 001e D368 ldr r3, [r2, #12] + 67 0020 23F00703 bic r3, r3, #7 + 68 0024 1843 orrs r0, r0, r3 + 69 .LVL3: + 70 .loc 1 344 3 is_stmt 0 view .LVU14 + 71 0026 D060 str r0, [r2, #12] + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 72 .loc 1 347 3 is_stmt 1 view .LVU15 + 73 .loc 1 347 15 is_stmt 0 view .LVU16 + 74 0028 FFF7FEFF bl HAL_GetTick + 75 .LVL4: + 76 002c 0446 mov r4, r0 + 77 .LVL5: + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */ + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + 78 .loc 1 350 3 is_stmt 1 view .LVU17 + 79 .L4: + 80 .loc 1 350 9 view .LVU18 + 81 .loc 1 350 10 is_stmt 0 view .LVU19 + 82 002e 084B ldr r3, .L12 + 83 0030 5B68 ldr r3, [r3, #4] + 84 .loc 1 350 9 view .LVU20 + 85 0032 13F4005F tst r3, #8192 + 86 0036 07D1 bne .L11 + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + 87 .loc 1 352 5 is_stmt 1 view .LVU21 + 88 .loc 1 352 10 is_stmt 0 view .LVU22 + 89 0038 FFF7FEFF bl HAL_GetTick + 90 .LVL6: + 91 .loc 1 352 25 view .LVU23 + 92 003c 001B subs r0, r0, r4 + 93 .loc 1 352 8 view .LVU24 + 94 003e B0F57A7F cmp r0, #1000 + 95 0042 F4D9 bls .L4 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 96 .loc 1 354 14 view .LVU25 + 97 0044 0120 movs r0, #1 + 98 0046 00E0 b .L3 + 99 .L11: + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccMGXY28.s page 9 + + + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (SMPS) + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get the current tick number */ + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till SMPS external supply ready flag is set */ + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (SMPS) */ + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 100 .loc 1 379 10 view .LVU26 + 101 0048 0020 movs r0, #0 + 102 .L3: + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 103 .loc 1 380 1 view .LVU27 + 104 004a 10BD pop {r4, pc} + 105 .LVL7: + 106 .L6: + 107 .LCFI1: + 108 .cfi_def_cfa_offset 0 + 109 .cfi_restore 4 + 110 .cfi_restore 14 + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 111 .loc 1 339 14 view .LVU28 + 112 004c 0020 movs r0, #0 + 113 .LVL8: + 114 .loc 1 380 1 view .LVU29 + 115 004e 7047 bx lr + 116 .L13: + 117 .align 2 + 118 .L12: + 119 0050 00480258 .word 1476544512 + 120 .cfi_endproc + 121 .LFE141: + 123 .section .text.HAL_PWREx_GetSupplyConfig,"ax",%progbits + 124 .align 1 + 125 .global HAL_PWREx_GetSupplyConfig + 126 .syntax unified + 127 .thumb + 128 .thumb_func + 129 .fpu fpv5-d16 + 131 HAL_PWREx_GetSupplyConfig: + 132 .LFB142: + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + ARM GAS /tmp/ccMGXY28.s page 10 + + + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the power supply configuration. + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The supply configuration. + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetSupplyConfig (void) + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 133 .loc 1 387 1 is_stmt 1 view -0 + 134 .cfi_startproc + 135 @ args = 0, pretend = 0, frame = 0 + 136 @ frame_needed = 0, uses_anonymous_args = 0 + 137 @ link register save eliminated. + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK); + 138 .loc 1 388 3 view .LVU31 + 139 .loc 1 388 14 is_stmt 0 view .LVU32 + 140 0000 024B ldr r3, .L15 + 141 0002 D868 ldr r0, [r3, #12] + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 142 .loc 1 389 1 view .LVU33 + 143 0004 00F00700 and r0, r0, #7 + 144 0008 7047 bx lr + 145 .L16: + 146 000a 00BF .align 2 + 147 .L15: + 148 000c 00480258 .word 1476544512 + 149 .cfi_endproc + 150 .LFE142: + 152 .section .text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits + 153 .align 1 + 154 .global HAL_PWREx_ControlVoltageScaling + 155 .syntax unified + 156 .thumb + 157 .thumb_func + 158 .fpu fpv5-d16 + 160 HAL_PWREx_ControlVoltageScaling: + 161 .LVL9: + 162 .LFB143: + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the main internal regulator output voltage. + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param VoltageScaling : Specifies the regulator output voltage to achieve + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * a tradeoff between performance and power + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * consumption. + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values : + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Scale 0 mode. + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * range 1 mode. + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * range 2 mode. + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * range 3 mode. + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * only possible when Vcore is supplied from LDO (Low DropOut). The + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * macro before configuring Voltage Scale 0. + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * To enter low power mode , and if current regulator voltage is + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * low power mode. + ARM GAS /tmp/ccMGXY28.s page 11 + + + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL Status + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling) + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 163 .loc 1 415 1 is_stmt 1 view -0 + 164 .cfi_startproc + 165 @ args = 0, pretend = 0, frame = 0 + 166 @ frame_needed = 0, uses_anonymous_args = 0 + 167 .loc 1 415 1 is_stmt 0 view .LVU35 + 168 0000 38B5 push {r3, r4, r5, lr} + 169 .LCFI2: + 170 .cfi_def_cfa_offset 16 + 171 .cfi_offset 3, -16 + 172 .cfi_offset 4, -12 + 173 .cfi_offset 5, -8 + 174 .cfi_offset 14, -4 + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 175 .loc 1 416 3 is_stmt 1 view .LVU36 + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling)); + 176 .loc 1 419 3 view .LVU37 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get the voltage scaling */ + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling) + 177 .loc 1 422 3 view .LVU38 + 178 .loc 1 422 11 is_stmt 0 view .LVU39 + 179 0002 324B ldr r3, .L38 + 180 0004 5B68 ldr r3, [r3, #4] + 181 .loc 1 422 18 view .LVU40 + 182 0006 03F44043 and r3, r3, #49152 + 183 .loc 1 422 6 view .LVU41 + 184 000a 8342 cmp r3, r0 + 185 000c 5CD0 beq .L28 + 186 000e 0446 mov r4, r0 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Old and new voltage scaling configuration match : nothing to do */ + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_SRDCR_VOS) + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */ + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0) + 187 .loc 1 433 3 is_stmt 1 view .LVU42 + 188 .loc 1 433 6 is_stmt 0 view .LVU43 + 189 0010 08BB cbnz r0, .L19 + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN) + 190 .loc 1 435 5 is_stmt 1 view .LVU44 + 191 .loc 1 435 13 is_stmt 0 view .LVU45 + 192 0012 2E4B ldr r3, .L38 + 193 0014 DB68 ldr r3, [r3, #12] + 194 .loc 1 435 8 view .LVU46 + 195 0016 13F0020F tst r3, #2 + ARM GAS /tmp/ccMGXY28.s page 12 + + + 196 001a 01D1 bne .L34 + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */ + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */ + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the PWR overdrive */ + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* The voltage scale 0 is only possible when LDO regulator is enabled */ + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 197 .loc 1 458 14 view .LVU47 + 198 001c 0120 movs r0, #1 + 199 .LVL10: + 200 .loc 1 458 14 view .LVU48 + 201 001e 52E0 b .L18 + 202 .LVL11: + 203 .L34: + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 204 .loc 1 438 7 is_stmt 1 view .LVU49 + 205 0020 2A4A ldr r2, .L38 + 206 0022 9369 ldr r3, [r2, #24] + 207 0024 43F44043 orr r3, r3, #49152 + 208 0028 9361 str r3, [r2, #24] + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 209 .loc 1 441 7 view .LVU50 + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 210 .loc 1 441 19 is_stmt 0 view .LVU51 + 211 002a FFF7FEFF bl HAL_GetTick + 212 .LVL12: + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 213 .loc 1 441 19 view .LVU52 + 214 002e 0446 mov r4, r0 + 215 .LVL13: + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 216 .loc 1 444 7 is_stmt 1 view .LVU53 + 217 .L20: + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 218 .loc 1 444 13 view .LVU54 + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 219 .loc 1 444 14 is_stmt 0 view .LVU55 + 220 0030 264B ldr r3, .L38 + 221 0032 5B68 ldr r3, [r3, #4] + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 13 + + + 222 .loc 1 444 13 view .LVU56 + 223 0034 13F4005F tst r3, #8192 + 224 0038 07D1 bne .L35 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 225 .loc 1 446 9 is_stmt 1 view .LVU57 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 226 .loc 1 446 14 is_stmt 0 view .LVU58 + 227 003a FFF7FEFF bl HAL_GetTick + 228 .LVL14: + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 229 .loc 1 446 29 view .LVU59 + 230 003e 001B subs r0, r0, r4 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 231 .loc 1 446 12 view .LVU60 + 232 0040 B0F57A7F cmp r0, #1000 + 233 0044 F4D9 bls .L20 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 234 .loc 1 448 18 view .LVU61 + 235 0046 0120 movs r0, #1 + 236 0048 3DE0 b .L18 + 237 .L35: + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 238 .loc 1 453 7 is_stmt 1 view .LVU62 + 239 004a 214A ldr r2, .L38+4 + 240 004c D36A ldr r3, [r2, #44] + 241 004e 43F00103 orr r3, r3, #1 + 242 0052 D362 str r3, [r2, #44] + 243 0054 0CE0 b .L22 + 244 .LVL15: + 245 .L19: + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1) + 246 .loc 1 463 5 view .LVU63 + 247 .loc 1 463 13 is_stmt 0 view .LVU64 + 248 0056 1D4B ldr r3, .L38 + 249 0058 5B68 ldr r3, [r3, #4] + 250 .loc 1 463 20 view .LVU65 + 251 005a 03F44043 and r3, r3, #49152 + 252 .loc 1 463 8 view .LVU66 + 253 005e B3F5404F cmp r3, #49152 + 254 0062 15D0 beq .L36 + 255 .LVL16: + 256 .L23: + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U) + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the PWR overdrive */ + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */ + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + ARM GAS /tmp/ccMGXY28.s page 14 + + + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */ + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); + 257 .loc 1 485 5 is_stmt 1 view .LVU67 + 258 0064 194B ldr r3, .L38 + 259 0066 9869 ldr r0, [r3, #24] + 260 0068 20F44040 bic r0, r0, #49152 + 261 006c 0443 orrs r4, r4, r0 + 262 .LVL17: + 263 .loc 1 485 5 is_stmt 0 view .LVU68 + 264 006e 9C61 str r4, [r3, #24] + 265 .L22: + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else /* STM32H72xxx and STM32H73xxx lines */ + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the voltage range */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (SYSCFG_PWRCR_ODEN) */ + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_SRDCR_VOS) */ + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 266 .loc 1 494 3 is_stmt 1 view .LVU69 + 267 .loc 1 494 15 is_stmt 0 view .LVU70 + 268 0070 FFF7FEFF bl HAL_GetTick + 269 .LVL18: + 270 0074 0446 mov r4, r0 + 271 .LVL19: + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till voltage level flag is set */ + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + 272 .loc 1 497 3 is_stmt 1 view .LVU71 + 273 .L26: + 274 .loc 1 497 9 view .LVU72 + 275 .loc 1 497 10 is_stmt 0 view .LVU73 + 276 0076 154B ldr r3, .L38 + 277 0078 5B68 ldr r3, [r3, #4] + 278 .loc 1 497 9 view .LVU74 + 279 007a 13F4005F tst r3, #8192 + 280 007e 21D1 bne .L37 + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + 281 .loc 1 499 5 is_stmt 1 view .LVU75 + 282 .loc 1 499 10 is_stmt 0 view .LVU76 + 283 0080 FFF7FEFF bl HAL_GetTick + 284 .LVL20: + 285 .loc 1 499 24 view .LVU77 + 286 0084 001B subs r0, r0, r4 + 287 .loc 1 499 8 view .LVU78 + 288 0086 B0F57A7F cmp r0, #1000 + ARM GAS /tmp/ccMGXY28.s page 15 + + + 289 008a F4D9 bls .L26 + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 290 .loc 1 501 14 view .LVU79 + 291 008c 0120 movs r0, #1 + 292 008e 1AE0 b .L18 + 293 .LVL21: + 294 .L36: + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 295 .loc 1 465 7 is_stmt 1 view .LVU80 + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 296 .loc 1 465 18 is_stmt 0 view .LVU81 + 297 0090 0F4B ldr r3, .L38+4 + 298 0092 DB6A ldr r3, [r3, #44] + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 299 .loc 1 465 10 view .LVU82 + 300 0094 13F0010F tst r3, #1 + 301 0098 E4D0 beq .L23 + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 302 .loc 1 468 9 is_stmt 1 view .LVU83 + 303 009a 0D4A ldr r2, .L38+4 + 304 009c D36A ldr r3, [r2, #44] + 305 009e 23F00103 bic r3, r3, #1 + 306 00a2 D362 str r3, [r2, #44] + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 307 .loc 1 471 9 view .LVU84 + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 308 .loc 1 471 21 is_stmt 0 view .LVU85 + 309 00a4 FFF7FEFF bl HAL_GetTick + 310 .LVL22: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 311 .loc 1 471 21 view .LVU86 + 312 00a8 0546 mov r5, r0 + 313 .LVL23: + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 314 .loc 1 474 9 is_stmt 1 view .LVU87 + 315 .L24: + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 316 .loc 1 474 15 view .LVU88 + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 317 .loc 1 474 16 is_stmt 0 view .LVU89 + 318 00aa 084B ldr r3, .L38 + 319 00ac 5B68 ldr r3, [r3, #4] + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 320 .loc 1 474 15 view .LVU90 + 321 00ae 13F4005F tst r3, #8192 + 322 00b2 D7D1 bne .L23 + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 323 .loc 1 476 11 is_stmt 1 view .LVU91 + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 324 .loc 1 476 16 is_stmt 0 view .LVU92 + 325 00b4 FFF7FEFF bl HAL_GetTick + 326 .LVL24: + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 327 .loc 1 476 31 view .LVU93 + 328 00b8 401B subs r0, r0, r5 + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 16 + + + 329 .loc 1 476 14 view .LVU94 + 330 00ba B0F57A7F cmp r0, #1000 + 331 00be F4D9 bls .L24 + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 332 .loc 1 478 20 view .LVU95 + 333 00c0 0120 movs r0, #1 + 334 00c2 00E0 b .L18 + 335 .LVL25: + 336 .L37: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 337 .loc 1 505 10 view .LVU96 + 338 00c4 0020 movs r0, #0 + 339 .LVL26: + 340 .L18: + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 341 .loc 1 506 1 view .LVU97 + 342 00c6 38BD pop {r3, r4, r5, pc} + 343 .LVL27: + 344 .L28: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 345 .loc 1 425 12 view .LVU98 + 346 00c8 0020 movs r0, #0 + 347 .LVL28: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 348 .loc 1 425 12 view .LVU99 + 349 00ca FCE7 b .L18 + 350 .L39: + 351 .align 2 + 352 .L38: + 353 00cc 00480258 .word 1476544512 + 354 00d0 00040058 .word 1476396032 + 355 .cfi_endproc + 356 .LFE143: + 358 .section .text.HAL_PWREx_GetVoltageRange,"ax",%progbits + 359 .align 1 + 360 .global HAL_PWREx_GetVoltageRange + 361 .syntax unified + 362 .thumb + 363 .thumb_func + 364 .fpu fpv5-d16 + 366 HAL_PWREx_GetVoltageRange: + 367 .LFB144: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the main internal regulator output voltage. Reflecting the last + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * VOS value applied to the PMU. + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The current applied VOS selection. + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange (void) + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 368 .loc 1 514 1 is_stmt 1 view -0 + 369 .cfi_startproc + 370 @ args = 0, pretend = 0, frame = 0 + 371 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccMGXY28.s page 17 + + + 372 @ link register save eliminated. + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get the active voltage scaling */ + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->CSR1 & PWR_CSR1_ACTVOS); + 373 .loc 1 516 3 view .LVU101 + 374 .loc 1 516 14 is_stmt 0 view .LVU102 + 375 0000 024B ldr r3, .L41 + 376 0002 5868 ldr r0, [r3, #4] + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 377 .loc 1 517 1 view .LVU103 + 378 0004 00F44040 and r0, r0, #49152 + 379 0008 7047 bx lr + 380 .L42: + 381 000a 00BF .align 2 + 382 .L41: + 383 000c 00480258 .word 1476544512 + 384 .cfi_endproc + 385 .LFE144: + 387 .section .text.HAL_PWREx_ControlStopModeVoltageScaling,"ax",%progbits + 388 .align 1 + 389 .global HAL_PWREx_ControlStopModeVoltageScaling + 390 .syntax unified + 391 .thumb + 392 .thumb_func + 393 .fpu fpv5-d16 + 395 HAL_PWREx_ControlStopModeVoltageScaling: + 396 .LVL29: + 397 .LFB145: + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the main internal regulator output voltage in STOP mode. + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param VoltageScaling : Specifies the regulator output voltage when the + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * system enters Stop mode to achieve a tradeoff between performance + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * and power consumption. + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * 3 mode. + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * 4 mode. + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * 5 mode. + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator in Low-power (LP) mode to further reduce power consumption. + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * When preselecting SVOS3, the use of the voltage regulator low-power + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode (LP) can be selected by LPDS register bit. + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The selected SVOS4 and SVOS5 levels add an additional startup delay + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * when exiting from system Stop mode. + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL Status. + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling) + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 398 .loc 1 540 1 is_stmt 1 view -0 + 399 .cfi_startproc + 400 @ args = 0, pretend = 0, frame = 0 + 401 @ frame_needed = 0, uses_anonymous_args = 0 + 402 @ link register save eliminated. + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling)); + ARM GAS /tmp/ccMGXY28.s page 18 + + + 403 .loc 1 542 3 view .LVU105 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Return the stop mode voltage range */ + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling); + 404 .loc 1 545 3 view .LVU106 + 405 0000 034A ldr r2, .L44 + 406 0002 1368 ldr r3, [r2] + 407 0004 23F44043 bic r3, r3, #49152 + 408 0008 0343 orrs r3, r3, r0 + 409 000a 1360 str r3, [r2] + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 410 .loc 1 547 3 view .LVU107 + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 411 .loc 1 548 1 is_stmt 0 view .LVU108 + 412 000c 0020 movs r0, #0 + 413 .LVL30: + 414 .loc 1 548 1 view .LVU109 + 415 000e 7047 bx lr + 416 .L45: + 417 .align 2 + 418 .L44: + 419 0010 00480258 .word 1476544512 + 420 .cfi_endproc + 421 .LFE145: + 423 .section .text.HAL_PWREx_GetStopModeVoltageRange,"ax",%progbits + 424 .align 1 + 425 .global HAL_PWREx_GetStopModeVoltageRange + 426 .syntax unified + 427 .thumb + 428 .thumb_func + 429 .fpu fpv5-d16 + 431 HAL_PWREx_GetStopModeVoltageRange: + 432 .LFB146: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the main internal regulator output voltage in STOP mode. + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The actual applied VOS selection. + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetStopModeVoltageRange (void) + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 433 .loc 1 555 1 is_stmt 1 view -0 + 434 .cfi_startproc + 435 @ args = 0, pretend = 0, frame = 0 + 436 @ frame_needed = 0, uses_anonymous_args = 0 + 437 @ link register save eliminated. + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Return the stop voltage scaling */ + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->CR1 & PWR_CR1_SVOS); + 438 .loc 1 557 3 view .LVU111 + 439 .loc 1 557 14 is_stmt 0 view .LVU112 + 440 0000 024B ldr r3, .L47 + 441 0002 1868 ldr r0, [r3] + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 442 .loc 1 558 1 view .LVU113 + 443 0004 00F44040 and r0, r0, #49152 + 444 0008 7047 bx lr + 445 .L48: + ARM GAS /tmp/ccMGXY28.s page 19 + + + 446 000a 00BF .align 2 + 447 .L47: + 448 000c 00480258 .word 1476544512 + 449 .cfi_endproc + 450 .LFE146: + 452 .section .text.HAL_PWREx_EnterSTOPMode,"ax",%progbits + 453 .align 1 + 454 .global HAL_PWREx_EnterSTOPMode + 455 .syntax unified + 456 .thumb + 457 .thumb_func + 458 .fpu fpv5-d16 + 460 HAL_PWREx_EnterSTOPMode: + 461 .LVL31: + 462 .LFB147: + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Low power control functions + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Low power control functions ##### + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Domains Low Power modes configuration *** + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ============================================= + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** This section provides the extended low power mode control APIs. + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The system presents 3 principles domains (D1, D2 and D3) that can be + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** operated in low-power modes (DSTOP or DSTANDBY mode): + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) DSTOP mode to enters a domain to STOP mode: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** subsystem is in CSTOP mode and has allocated peripheral in the + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** domain. + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DSTOP mode the domain bus matrix clock is stopped. + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) The system enters STOP mode using one of the following scenarios: + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter DSTOP mode. + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter DSTOP mode. + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter DSTOP mode. + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enters DSTOP mode. + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enters DSTOP mode. + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enters DSTOP mode. + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) D1, D2 and D3 domains enter DSTOP mode. + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) When the system enters STOP mode, the clocks are stopped and the + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regulator is running in main or low power mode. + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) D3 domain can be kept in Run mode regardless of the CPU status when + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function. + ARM GAS /tmp/ccMGXY28.s page 20 + + + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) DSTANDBY mode to enters a domain to STANDBY mode: + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** register (PWR_CPUCR) for the Dn domain selects Standby mode. + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** DSTANDBY mode. Consequently the VCORE supply regulator is powered + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** off. + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** DSTOP mode *** + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ================== + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DStop mode the domain bus matrix clock is stopped. + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The Flash memory can enter low-power Stop mode when it is enabled through + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** FLPS in PWR_CR1 register. This allows a trade-off between domain DStop + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** restart time and low power consumption. + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DStop mode domain peripherals using the LSI or LSE clock and + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** peripherals having a kernel clock request are still able to operate. + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Before entering DSTOP mode it is recommended to call SCB_CleanDCache + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function in order to clean the D-Cache and guarantee the data integrity + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** for the SRAM memories. + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Entry: + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** STOPEntry, Domain) function with: + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Regulator: + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_MAINREGULATOR_ON : Main regulator ON. + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON. + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) STOPEntry: + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Domain: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode. + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode. + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode. + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Exit: + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** DSTANDBY mode *** + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ===================== + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** In DStandby mode: + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The domain bus matrix clock is stopped. + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The domain is powered down and the domain RAM and register contents + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** are lost. + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function in order to clean the D-Cache and guarantee the data integrity + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** for the SRAM memories. + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Entry: + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (Domain) function with: + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) Domain: + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode. + ARM GAS /tmp/ccMGXY28.s page 21 + + + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode. + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode. + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) Exit: + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** wakeup, tamper event, time stamp event, external reset in NRST pin, + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** IWDG reset. + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Keep D3/SRD in RUN mode *** + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================== + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** D3/SRD domain can be kept in Run mode regardless of the CPU status when + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** with : + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) D3State: + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode. + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** of CPU subsystem mode. + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** FLASH Power Down configuration **** + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ======================================= + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** By setting the FLPS bit in the PWR_CR1 register using the + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** power down mode when the device enters STOP mode. When the Flash memory is + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in power down mode, an additional startup delay is incurred when waking up + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** from STOP mode. + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Wakeup Pins configuration **** + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =================================== + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** Wakeup pins allow the system to exit from Standby mode. The configuration + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function with: + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) sPinParams: structure to enable and configure a wakeup pin: + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) WakeUpPin: Wakeup pin to be enabled. + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PinPolarity: Wakeup pin polarity (rising or falling edge). + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The wakeup pins are internally connected to the EXTI lines [55-60] to + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** generate an interrupt if enabled. The EXTI lines configuration is done by + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** file. + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** called and the appropriate flag is set in the PWR_WKUPFR register. Then in + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** cleared and the appropriate user callback will be called. The user can add + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_RETDS_CD) + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + ARM GAS /tmp/ccMGXY28.s page 22 + + + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enter the system to STOP mode with main domain in DSTOP2. + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In STOP mode, the domain bus matrix clock is stalled. + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In STOP mode, memories and registers are maintained and peripherals + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * in CPU domain are no longer operational. + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * HSE oscillators are disabled. Only Peripherals that have wakeup + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * capability can switch on the HSI to receive a frame, and switch off + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the HSI after receiving the frame if it is not a wakeup frame. In + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * this case the HSI clock is propagated only to the peripheral + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * requesting it. + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When exiting STOP mode by issuing an interrupt or a wakeup event, + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the HSI RC oscillator is selected as system clock if STOPWUCK bit in + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * RCC_CFGR register is set. + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Regulator : Specifies the regulator state in STOP mode. + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator ON. + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * intrinsic instruction. + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry) + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_REGULATOR (Regulator)); + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the regulator state in Stop mode */ + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */ + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD); + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when SmartRun domain enters Deepsleep */ + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD); + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Ensure that all instructions are done before entering STOP mode */ + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __ISB (); + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __DSB (); + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select Stop mode entry */ + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (STOPEntry == PWR_STOPENTRY_WFI) + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI (); + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Event */ + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE (); + ARM GAS /tmp/ccMGXY28.s page 23 + + + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_RETDS_CD) */ + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enter a Domain to DSTOP mode. + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API gives flexibility to manage independently each domain STOP + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode. For dual core lines, this API should be executed with the + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * executed by all available Cortex-Mx, the system enter to STOP mode. + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * For single core lines, calling this API with domain parameter set to + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * CPUCR_RUN_D3 is cleared. + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In DStop mode the domain bus matrix clock is stopped. + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * is in CStop mode, the EXTI wakeup sources are inactive and at least + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * any domain request Stop. + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * function in order to clean the D-Cache and guarantee the data + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * integrity for the SRAM memories. + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In System Stop mode, the domain peripherals that use the LSI or LSE + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * clock, and the peripherals that have a kernel clock request to + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * select HSI or CSI as source, are still able to operate. + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Regulator : Specifies the regulator state in STOP mode. + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regulator ON. + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * intrinsic instruction. + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Domain : Specifies the Domain to enter in DSTOP mode. + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode. + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode. + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode. + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain) + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 463 .loc 1 818 1 is_stmt 1 view -0 + 464 .cfi_startproc + 465 @ args = 0, pretend = 0, frame = 0 + 466 @ frame_needed = 0, uses_anonymous_args = 0 + 467 @ link register save eliminated. + 468 .loc 1 818 1 is_stmt 0 view .LVU115 + 469 0000 10B4 push {r4} + 470 .LCFI3: + 471 .cfi_def_cfa_offset 4 + 472 .cfi_offset 4, -4 + ARM GAS /tmp/ccMGXY28.s page 24 + + + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_REGULATOR (Regulator)); + 473 .loc 1 820 3 is_stmt 1 view .LVU116 + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + 474 .loc 1 821 3 view .LVU117 + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_DOMAIN (Domain)); + 475 .loc 1 822 3 view .LVU118 + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the regulator state in Stop mode */ + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + 476 .loc 1 825 3 view .LVU119 + 477 0002 174C ldr r4, .L58 + 478 0004 2368 ldr r3, [r4] + 479 0006 23F00103 bic r3, r3, #1 + 480 000a 0343 orrs r3, r3, r0 + 481 000c 2360 str r3, [r4] + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the domain Power Down DeepSleep */ + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (Domain == PWR_D1_DOMAIN) + 482 .loc 1 828 3 view .LVU120 + 483 .loc 1 828 6 is_stmt 0 view .LVU121 + 484 000e CAB9 cbnz r2, .L50 + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */ + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM7_CPUID) + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering stop + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode will not be performed + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return; + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D1/CD domain enters Deepsleep */ + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1); + 485 .loc 1 843 5 is_stmt 1 view .LVU122 + 486 0010 2369 ldr r3, [r4, #16] + 487 0012 23F00103 bic r3, r3, #1 + 488 0016 2361 str r3, [r4, #16] + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 489 .loc 1 846 5 view .LVU123 + 490 0018 124A ldr r2, .L58+4 + 491 .LVL32: + 492 .loc 1 846 5 is_stmt 0 view .LVU124 + 493 001a 1369 ldr r3, [r2, #16] + 494 001c 43F00403 orr r3, r3, #4 + 495 0020 1361 str r3, [r2, #16] + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Ensure that all instructions are done before entering STOP mode */ + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __DSB (); + 496 .loc 1 849 5 is_stmt 1 view .LVU125 + 497 .LBB14: + 498 .LBI14: + ARM GAS /tmp/ccMGXY28.s page 25 + + + 499 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + ARM GAS /tmp/ccMGXY28.s page 26 + + + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + ARM GAS /tmp/ccMGXY28.s page 27 + + + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + ARM GAS /tmp/ccMGXY28.s page 28 + + + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMGXY28.s page 29 + + + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccMGXY28.s page 30 + + + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + ARM GAS /tmp/ccMGXY28.s page 31 + + + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccMGXY28.s page 32 + + + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMGXY28.s page 33 + + + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + ARM GAS /tmp/ccMGXY28.s page 34 + + + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + ARM GAS /tmp/ccMGXY28.s page 35 + + + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMGXY28.s page 36 + + + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + ARM GAS /tmp/ccMGXY28.s page 37 + + + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + ARM GAS /tmp/ccMGXY28.s page 38 + + + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + ARM GAS /tmp/ccMGXY28.s page 39 + + + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + ARM GAS /tmp/ccMGXY28.s page 40 + + + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 500 .loc 2 877 27 view .LVU126 + 501 .LBB15: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 502 .loc 2 879 3 view .LVU127 + 503 .syntax unified + 504 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 505 0022 BFF34F8F dsb 0xF + 506 @ 0 "" 2 + 507 .thumb + 508 .syntax unified + 509 .LBE15: + 510 .LBE14: + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __ISB (); + 511 .loc 1 850 5 view .LVU128 + 512 .LBB16: + 513 .LBI16: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 514 .loc 2 866 27 view .LVU129 + 515 .LBB17: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 516 .loc 2 868 3 view .LVU130 + 517 .syntax unified + 518 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 519 0026 BFF36F8F isb 0xF + 520 @ 0 "" 2 + 521 .thumb + 522 .syntax unified + 523 .LBE17: + 524 .LBE16: + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select Stop mode entry */ + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (STOPEntry == PWR_STOPENTRY_WFI) + 525 .loc 1 853 5 view .LVU131 + ARM GAS /tmp/ccMGXY28.s page 41 + + + 526 .loc 1 853 8 is_stmt 0 view .LVU132 + 527 002a 0129 cmp r1, #1 + 528 002c 08D0 beq .L56 + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI (); + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Event */ + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE (); + 529 .loc 1 861 7 is_stmt 1 view .LVU133 + 530 .syntax unified + 531 @ 861 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1 + 532 002e 20BF wfe + 533 @ 0 "" 2 + 534 .thumb + 535 .syntax unified + 536 .L52: + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 537 .loc 1 865 5 view .LVU134 + 538 0030 0C4A ldr r2, .L58+4 + 539 0032 1369 ldr r3, [r2, #16] + 540 0034 23F00403 bic r3, r3, #4 + 541 0038 1361 str r3, [r2, #16] + 542 .L49: + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_PDDS_D2) + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (Domain == PWR_D2_DOMAIN) + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */ + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM4_CPUID) + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering stop + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode will not be performed + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return; + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D2 domain enters Deepsleep */ + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Ensure that all instructions are done before entering STOP mode */ + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __DSB (); + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __ISB (); + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select Stop mode entry */ + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (STOPEntry == PWR_STOPENTRY_WFI) + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 42 + + + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI (); + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Event */ + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE (); + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D2 domain enters Deepsleep */ + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_PDDS_D2) */ + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */ + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D3 domain enters Deepsleep */ + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D3 domain enters Deepsleep */ + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */ + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 543 .loc 1 930 1 is_stmt 0 view .LVU135 + 544 003a 5DF8044B ldr r4, [sp], #4 + 545 .LCFI4: + 546 .cfi_remember_state + 547 .cfi_restore 4 + 548 .cfi_def_cfa_offset 0 + 549 003e 7047 bx lr + 550 .L56: + 551 .LCFI5: + 552 .cfi_restore_state + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 553 .loc 1 856 7 is_stmt 1 view .LVU136 + 554 .syntax unified + 555 @ 856 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1 + 556 0040 30BF wfi + 557 @ 0 "" 2 + 558 .thumb + 559 .syntax unified + 560 0042 F5E7 b .L52 + 561 .LVL33: + ARM GAS /tmp/ccMGXY28.s page 43 + + + 562 .L50: + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 563 .loc 1 868 8 view .LVU137 + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 564 .loc 1 868 11 is_stmt 0 view .LVU138 + 565 0044 012A cmp r2, #1 + 566 0046 05D0 beq .L57 + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 567 .loc 1 927 5 is_stmt 1 view .LVU139 + 568 0048 054A ldr r2, .L58 + 569 .LVL34: + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 570 .loc 1 927 5 is_stmt 0 view .LVU140 + 571 004a 1369 ldr r3, [r2, #16] + 572 004c 23F00403 bic r3, r3, #4 + 573 0050 1361 str r3, [r2, #16] + 574 .loc 1 930 1 view .LVU141 + 575 0052 F2E7 b .L49 + 576 .LVL35: + 577 .L57: + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 578 .loc 1 907 5 is_stmt 1 view .LVU142 + 579 0054 024A ldr r2, .L58 + 580 .LVL36: + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 581 .loc 1 907 5 is_stmt 0 view .LVU143 + 582 0056 1369 ldr r3, [r2, #16] + 583 0058 23F00203 bic r3, r3, #2 + 584 005c 1361 str r3, [r2, #16] + 585 005e ECE7 b .L49 + 586 .L59: + 587 .align 2 + 588 .L58: + 589 0060 00480258 .word 1476544512 + 590 0064 00ED00E0 .word -536810240 + 591 .cfi_endproc + 592 .LFE147: + 594 .section .text.HAL_PWREx_ClearPendingEvent,"ax",%progbits + 595 .align 1 + 596 .global HAL_PWREx_ClearPendingEvent + 597 .syntax unified + 598 .thumb + 599 .thumb_func + 600 .fpu fpv5-d16 + 602 HAL_PWREx_ClearPendingEvent: + 603 .LFB148: + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Clear pending event. + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API clears the pending event in order to enter a given CPU + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * to CSLEEP or CSTOP. It should be called just before APIs performing + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * enter low power mode using Wait For Event request. + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4. + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ClearPendingEvent (void) + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 44 + + + 604 .loc 1 941 1 is_stmt 1 view -0 + 605 .cfi_startproc + 606 @ args = 0, pretend = 0, frame = 0 + 607 @ frame_needed = 0, uses_anonymous_args = 0 + 608 @ link register save eliminated. + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the current Core */ + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE (); + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __SEV (); + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE (); + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFE (); + 609 .loc 1 954 3 view .LVU145 + 610 .syntax unified + 611 @ 954 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1 + 612 0000 20BF wfe + 613 @ 0 "" 2 + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 614 .loc 1 956 1 is_stmt 0 view .LVU146 + 615 .thumb + 616 .syntax unified + 617 0002 7047 bx lr + 618 .cfi_endproc + 619 .LFE148: + 621 .section .text.HAL_PWREx_EnterSTANDBYMode,"ax",%progbits + 622 .align 1 + 623 .global HAL_PWREx_EnterSTANDBYMode + 624 .syntax unified + 625 .thumb + 626 .thumb_func + 627 .fpu fpv5-d16 + 629 HAL_PWREx_EnterSTANDBYMode: + 630 .LVL37: + 631 .LFB149: + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enter a Domain to DSTANDBY mode. + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API gives flexibility to manage independently each domain + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * STANDBY mode. For dual core lines, this API should be executed with + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * it is executed by all available Cortex-Mx, the system enter STANDBY + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode. + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * For single core lines, calling this API with D1/SRD the selected + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1. + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the Dn domain select Standby mode. When the system enters Standby + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode, the voltage regulator is disabled. + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When D2 or D3 domain is in DStandby mode and the CPU sets the + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * domain PDDS_Dn bit to select Stop mode, the domain remains in + ARM GAS /tmp/ccMGXY28.s page 45 + + + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * DStandby mode. The domain will only exit DStandby when the CPU + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * allocates a peripheral in the domain. + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The system D3/SRD domain enters Standby mode only when the D1 and D2 + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * domain are in DStandby. + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Before entering DSTANDBY mode it is recommended to call + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * SCB_CleanDCache function in order to clean the D-Cache and guarantee + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the data integrity for the SRAM memories. + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param Domain : Specifies the Domain to enter to STANDBY mode. + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode. + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode. + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode. + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain) + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 632 .loc 1 988 1 is_stmt 1 view -0 + 633 .cfi_startproc + 634 @ args = 0, pretend = 0, frame = 0 + 635 @ frame_needed = 0, uses_anonymous_args = 0 + 636 @ link register save eliminated. + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_DOMAIN (Domain)); + 637 .loc 1 990 3 view .LVU148 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Select the domain Power Down DeepSleep */ + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (Domain == PWR_D1_DOMAIN) + 638 .loc 1 993 3 view .LVU149 + 639 .loc 1 993 6 is_stmt 0 view .LVU150 + 640 0000 58B9 cbnz r0, .L62 + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */ + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM7_CPUID) + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** standby mode will not be performed +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return; +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1); + 641 .loc 1 1008 5 is_stmt 1 view .LVU151 + 642 0002 0D4A ldr r2, .L66 + 643 0004 1369 ldr r3, [r2, #16] + 644 0006 43F00103 orr r3, r3, #1 + 645 000a 1361 str r3, [r2, #16] +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /*DUAL_CORE*/ +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + ARM GAS /tmp/ccMGXY28.s page 46 + + +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + 646 .loc 1 1016 5 view .LVU152 + 647 000c 0B4A ldr r2, .L66+4 + 648 000e 1369 ldr r3, [r2, #16] + 649 0010 43F00403 orr r3, r3, #4 + 650 0014 1361 str r3, [r2, #16] +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* This option is used to ensure that store operations are completed */ +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (__CC_ARM) +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __force_stores (); +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (__CC_ARM) */ +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI (); + 651 .loc 1 1024 5 view .LVU153 + 652 .syntax unified + 653 @ 1024 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1 + 654 0016 30BF wfi + 655 @ 0 "" 2 + 656 .thumb + 657 .syntax unified + 658 0018 7047 bx lr + 659 .L62: +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_PDDS_D2) +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (Domain == PWR_D2_DOMAIN) + 660 .loc 1 1027 8 view .LVU154 + 661 .loc 1 1027 11 is_stmt 0 view .LVU155 + 662 001a 0128 cmp r0, #1 + 663 001c 05D0 beq .L65 +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2); +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check current core */ +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () != CM4_CPUID) +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** When the domain selected and the cortex-mx don't match, entering +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** standby mode will not be performed +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return; +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* This option is used to ensure that store operations are completed */ +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (__CC_ARM) +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __force_stores (); +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (__CC_ARM) */ +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ + ARM GAS /tmp/ccMGXY28.s page 47 + + +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __WFI (); +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_PDDS_D2) */ +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + 664 .loc 1 1062 5 is_stmt 1 view .LVU156 + 665 001e 064A ldr r2, .L66 + 666 0020 1369 ldr r3, [r2, #16] + 667 0022 43F00403 orr r3, r3, #4 + 668 0026 1361 str r3, [r2, #16] +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 669 .loc 1 1069 1 is_stmt 0 view .LVU157 + 670 0028 7047 bx lr + 671 .L65: +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 672 .loc 1 1030 5 is_stmt 1 view .LVU158 + 673 002a 034A ldr r2, .L66 + 674 002c 1369 ldr r3, [r2, #16] + 675 002e 43F00203 orr r3, r3, #2 + 676 0032 1361 str r3, [r2, #16] + 677 0034 7047 bx lr + 678 .L67: + 679 0036 00BF .align 2 + 680 .L66: + 681 0038 00480258 .word 1476544512 + 682 003c 00ED00E0 .word -536810240 + 683 .cfi_endproc + 684 .LFE149: + 686 .section .text.HAL_PWREx_ConfigD3Domain,"ax",%progbits + 687 .align 1 + 688 .global HAL_PWREx_ConfigD3Domain + 689 .syntax unified + 690 .thumb + 691 .thumb_func + 692 .fpu fpv5-d16 + 694 HAL_PWREx_ConfigD3Domain: + 695 .LVL38: + 696 .LFB150: +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the D3/SRD Domain state when the System in low power mode. +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param D3State : Specifies the D3/SRD state. +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values : +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * CPU sub-system low power mode. +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * regardless of the CPU sub-system low +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * power mode. + ARM GAS /tmp/ccMGXY28.s page 48 + + +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ConfigD3Domain (uint32_t D3State) +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 697 .loc 1 1083 1 view -0 + 698 .cfi_startproc + 699 @ args = 0, pretend = 0, frame = 0 + 700 @ frame_needed = 0, uses_anonymous_args = 0 + 701 @ link register save eliminated. +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_D3_STATE (D3State)); + 702 .loc 1 1085 3 view .LVU160 +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Keep D3/SRD in run mode */ +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); + 703 .loc 1 1088 3 view .LVU161 + 704 0000 034A ldr r2, .L69 + 705 0002 1369 ldr r3, [r2, #16] + 706 0004 23F40063 bic r3, r3, #2048 + 707 0008 0343 orrs r3, r3, r0 + 708 000a 1361 str r3, [r2, #16] +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 709 .loc 1 1089 1 is_stmt 0 view .LVU162 + 710 000c 7047 bx lr + 711 .L70: + 712 000e 00BF .align 2 + 713 .L69: + 714 0010 00480258 .word 1476544512 + 715 .cfi_endproc + 716 .LFE150: + 718 .section .text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits + 719 .align 1 + 720 .global HAL_PWREx_EnableFlashPowerDown + 721 .syntax unified + 722 .thumb + 723 .thumb_func + 724 .fpu fpv5-d16 + 726 HAL_PWREx_EnableFlashPowerDown: + 727 .LFB151: +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * given domain. +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param DomainFlags : Specifies the Domain flags to be cleared. +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags. +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags. +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags. +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags) +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags)); +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* D1 CPU flags */ + ARM GAS /tmp/ccMGXY28.s page 49 + + +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (DomainFlags == PWR_D1_DOMAIN_FLAGS) +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* D2 CPU flags */ +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (DomainFlags == PWR_D2_DOMAIN_FLAGS) +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Hold the CPU and their domain peripherals when exiting STOP mode. +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param CPU : Specifies the core to be held. +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master. +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master. +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU) +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_CORE (CPU)); +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check CPU index */ +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (CPU == PWR_CORE_CPU2) +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* If CPU1 is not held */ +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1) +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set HOLD2 bit */ +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** status = HAL_ERROR; +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* If CPU2 is not held */ +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2) +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set HOLD1 bit */ +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccMGXY28.s page 50 + + +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** status = HAL_ERROR; +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return status; +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Release the CPU and their domain peripherals after a wake-up from +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * STOP mode. +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param CPU: Specifies the core to be released. +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU1: Release the CPU1 and their domain +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * peripherals from holding. +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_CORE_CPU2: Release the CPU2 and their domain +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * peripherals from holding. +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ReleaseCore (uint32_t CPU) +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_CORE (CPU)); +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check CPU index */ +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (CPU == PWR_CORE_CPU2) +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Reset HOLD2 bit */ +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Reset HOLD1 bit */ +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Flash Power Down in Stop mode. +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When Flash Power Down is enabled the Flash memory enters low-power +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode when D1/SRD domain is in DStop mode. This feature allows to +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * obtain the best trade-off between low-power consumption and restart +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * time when exiting from DStop mode. +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown (void) +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 728 .loc 1 1214 1 is_stmt 1 view -0 + 729 .cfi_startproc + 730 @ args = 0, pretend = 0, frame = 0 + 731 @ frame_needed = 0, uses_anonymous_args = 0 + 732 @ link register save eliminated. +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Flash Power Down */ +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_FLPS); + ARM GAS /tmp/ccMGXY28.s page 51 + + + 733 .loc 1 1216 3 view .LVU164 + 734 0000 024A ldr r2, .L72 + 735 0002 1368 ldr r3, [r2] + 736 0004 43F40073 orr r3, r3, #512 + 737 0008 1360 str r3, [r2] +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 738 .loc 1 1217 1 is_stmt 0 view .LVU165 + 739 000a 7047 bx lr + 740 .L73: + 741 .align 2 + 742 .L72: + 743 000c 00480258 .word 1476544512 + 744 .cfi_endproc + 745 .LFE151: + 747 .section .text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits + 748 .align 1 + 749 .global HAL_PWREx_DisableFlashPowerDown + 750 .syntax unified + 751 .thumb + 752 .thumb_func + 753 .fpu fpv5-d16 + 755 HAL_PWREx_DisableFlashPowerDown: + 756 .LFB152: +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Flash Power Down in Stop mode. +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When Flash Power Down is disabled the Flash memory is kept on +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * normal mode when D1/SRD domain is in DStop mode. This feature allows +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * to obtain the best trade-off between low-power consumption and +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * restart time when exiting from DStop mode. +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown (void) +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 757 .loc 1 1228 1 is_stmt 1 view -0 + 758 .cfi_startproc + 759 @ args = 0, pretend = 0, frame = 0 + 760 @ frame_needed = 0, uses_anonymous_args = 0 + 761 @ link register save eliminated. +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Flash Power Down */ +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS); + 762 .loc 1 1230 3 view .LVU167 + 763 0000 024A ldr r2, .L75 + 764 0002 1368 ldr r3, [r2] + 765 0004 23F40073 bic r3, r3, #512 + 766 0008 1360 str r3, [r2] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 767 .loc 1 1231 1 is_stmt 0 view .LVU168 + 768 000a 7047 bx lr + 769 .L76: + 770 .align 2 + 771 .L75: + 772 000c 00480258 .word 1476544512 + 773 .cfi_endproc + 774 .LFE152: + 776 .section .text.HAL_PWREx_EnableWakeUpPin,"ax",%progbits + 777 .align 1 + ARM GAS /tmp/ccMGXY28.s page 52 + + + 778 .global HAL_PWREx_EnableWakeUpPin + 779 .syntax unified + 780 .thumb + 781 .thumb_func + 782 .fpu fpv5-d16 + 784 HAL_PWREx_EnableWakeUpPin: + 785 .LVL39: + 786 .LFB153: +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CR1_SRDRAMSO) +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable memory block shut-off in DStop or DStop2 modes +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note In DStop or DStop2 mode, the content of the memory blocks is +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * maintained. Further power optimization can be obtained by switching +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * off some memory blocks. This optimization implies loss of the memory +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * content. The user can select which memory is discarded during STOP +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * mode by means of xxSO bits. +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param MemoryBlock : Specifies the memory block to shut-off during DStop or +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * DStop2 mode. +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * FDCAN memories. +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock) +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable memory block shut-off */ +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, MemoryBlock); +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable memory block shut-off in DStop or DStop2 modes +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param MemoryBlock : Specifies the memory block to keep content during +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * DStop or DStop2 mode. +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * FDCAN memories. +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. + ARM GAS /tmp/ccMGXY28.s page 53 + + +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable memory block shut-off */ +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, MemoryBlock); +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CR1_SRDRAMSO) */ +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Wake-up PINx functionality. +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * contains the configuration information for the wake-up +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Pin. +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note For dual core devices, please ensure to configure the EXTI lines for +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the different Cortex-Mx. All combination are allowed: wake up only +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Cortex-M4. +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 787 .loc 1 1304 1 is_stmt 1 view -0 + 788 .cfi_startproc + 789 @ args = 0, pretend = 0, frame = 0 + 790 @ frame_needed = 0, uses_anonymous_args = 0 + 791 @ link register save eliminated. + 792 .loc 1 1304 1 is_stmt 0 view .LVU170 + 793 0000 10B4 push {r4} + 794 .LCFI6: + 795 .cfi_def_cfa_offset 4 + 796 .cfi_offset 4, -4 +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t pinConfig; + 797 .loc 1 1305 3 is_stmt 1 view .LVU171 +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t regMask; + 798 .loc 1 1306 3 view .LVU172 +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; + 799 .loc 1 1307 3 view .LVU173 + 800 .LVL40: +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin)); + 801 .loc 1 1310 3 view .LVU174 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity)); + 802 .loc 1 1311 3 view .LVU175 +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull)); + 803 .loc 1 1312 3 view .LVU176 +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** pinConfig = sPinParams->WakeUpPin | \ + 804 .loc 1 1314 3 view .LVU177 + 805 .loc 1 1314 25 is_stmt 0 view .LVU178 + 806 0002 0368 ldr r3, [r0] +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP + 807 .loc 1 1315 26 view .LVU179 + 808 0004 4168 ldr r1, [r0, #4] + ARM GAS /tmp/ccMGXY28.s page 54 + + + 809 .LVL41: + 810 .LBB18: + 811 .LBI18: + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccMGXY28.s page 55 + + + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 812 .loc 2 981 31 is_stmt 1 view .LVU180 + 813 .LBB19: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 814 .loc 2 983 3 view .LVU181 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + ARM GAS /tmp/ccMGXY28.s page 56 + + + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 815 .loc 2 988 4 view .LVU182 + 816 .syntax unified + 817 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 818 0006 93FAA3F2 rbit r2, r3 + 819 @ 0 "" 2 + 820 .LVL42: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 821 .loc 2 1001 3 view .LVU183 + 822 .loc 2 1001 3 is_stmt 0 view .LVU184 + 823 .thumb + 824 .syntax unified + 825 .LBE19: + 826 .LBE18: + 827 .loc 1 1315 45 view .LVU185 + 828 000a B2FA82F2 clz r2, r2 + 829 .loc 1 1315 81 view .LVU186 + 830 000e 0832 adds r2, r2, #8 + 831 .loc 1 1315 107 view .LVU187 + 832 0010 02F01F02 and r2, r2, #31 + 833 .loc 1 1315 40 view .LVU188 + 834 0014 01FA02F2 lsl r2, r1, r2 +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP + 835 .loc 1 1314 37 view .LVU189 + 836 0018 43EA0201 orr r1, r3, r2 + 837 .LVL43: + 838 .LBB20: + 839 .LBI20: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 840 .loc 2 981 31 is_stmt 1 view .LVU190 + 841 .LBB21: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 842 .loc 2 983 3 view .LVU191 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 843 .loc 2 988 4 view .LVU192 + 844 .syntax unified + 845 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 846 001c 93FAA3F2 rbit r2, r3 + 847 @ 0 "" 2 + 848 .LVL44: + 849 .loc 2 1001 3 view .LVU193 + 850 .loc 2 1001 3 is_stmt 0 view .LVU194 + 851 .thumb + 852 .syntax unified + 853 .LBE21: + ARM GAS /tmp/ccMGXY28.s page 57 + + + 854 .LBE20: +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL + 855 .loc 1 1316 42 view .LVU195 + 856 0020 B2FA82F2 clz r2, r2 + 857 .loc 1 1316 115 view .LVU196 + 858 0024 0832 adds r2, r2, #8 + 859 0026 5200 lsls r2, r2, #1 + 860 .loc 1 1316 144 view .LVU197 + 861 0028 02F01E02 and r2, r2, #30 + 862 .loc 1 1316 36 view .LVU198 + 863 002c 8468 ldr r4, [r0, #8] + 864 002e 04FA02F2 lsl r2, r4, r2 +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP + 865 .loc 1 1314 13 view .LVU199 + 866 0032 0A43 orrs r2, r2, r1 + 867 .LVL45: +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regMask = sPinParams->WakeUpPin | \ + 868 .loc 1 1318 3 is_stmt 1 view .LVU200 + 869 .LBB22: + 870 .LBI22: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 871 .loc 2 981 31 view .LVU201 + 872 .LBB23: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 873 .loc 2 983 3 view .LVU202 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 874 .loc 2 988 4 view .LVU203 + 875 .syntax unified + 876 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 877 0034 93FAA3F1 rbit r1, r3 + 878 @ 0 "" 2 + 879 .LVL46: + 880 .loc 2 1001 3 view .LVU204 + 881 .loc 2 1001 3 is_stmt 0 view .LVU205 + 882 .thumb + 883 .syntax unified + 884 .LBE23: + 885 .LBE22: +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + 886 .loc 1 1319 75 view .LVU206 + 887 0038 B1FA81F1 clz r1, r1 + 888 003c 01F01F0C and ip, r1, #31 + 889 .loc 1 1319 35 view .LVU207 + 890 0040 4FF48071 mov r1, #256 + 891 0044 01FA0CF1 lsl r1, r1, ip +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + 892 .loc 1 1318 37 view .LVU208 + 893 0048 1943 orrs r1, r1, r3 + 894 .LVL47: + 895 .LBB24: + 896 .LBI24: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 897 .loc 2 981 31 is_stmt 1 view .LVU209 + 898 .LBB25: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 899 .loc 2 983 3 view .LVU210 + ARM GAS /tmp/ccMGXY28.s page 58 + + + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 900 .loc 2 988 4 view .LVU211 + 901 .syntax unified + 902 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 903 004a 93FAA3F3 rbit r3, r3 + 904 @ 0 "" 2 + 905 .LVL48: + 906 .loc 2 1001 3 view .LVU212 + 907 .loc 2 1001 3 is_stmt 0 view .LVU213 + 908 .thumb + 909 .syntax unified + 910 .LBE25: + 911 .LBE24: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSE + 912 .loc 1 1320 30 view .LVU214 + 913 004e B3FA83F3 clz r3, r3 + 914 .loc 1 1320 66 view .LVU215 + 915 0052 5B00 lsls r3, r3, #1 + 916 .loc 1 1320 103 view .LVU216 + 917 0054 03F01E03 and r3, r3, #30 + 918 .loc 1 1320 25 view .LVU217 + 919 0058 4FF4403C mov ip, #196608 + 920 005c 0CFA03F3 lsl r3, ip, r3 +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + 921 .loc 1 1318 13 view .LVU218 + 922 0060 0B43 orrs r3, r3, r1 + 923 .LVL49: +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable and Specify the Wake-Up pin polarity and the pull configuration +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** for the event detection (rising or falling edge) */ +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig); + 924 .loc 1 1324 3 is_stmt 1 view .LVU219 + 925 0062 0A4C ldr r4, .L79 + 926 0064 A16A ldr r1, [r4, #40] + 927 0066 21EA0303 bic r3, r1, r3 + 928 .LVL50: + 929 .loc 1 1324 3 is_stmt 0 view .LVU220 + 930 006a 1A43 orrs r2, r2, r3 + 931 .LVL51: + 932 .loc 1 1324 3 view .LVU221 + 933 006c A262 str r2, [r4, #40] +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #ifndef DUAL_CORE +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Configure the Wakeup Pin EXTI Line */ +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)) + 934 .loc 1 1327 3 is_stmt 1 view .LVU222 + 935 006e 4FF0B042 mov r2, #1476395008 + 936 0072 D2F89030 ldr r3, [r2, #144] + 937 0076 23F0FC53 bic r3, r3, #528482304 + 938 007a 0168 ldr r1, [r0] + 939 007c 43EAC153 orr r3, r3, r1, lsl #23 + 940 0080 C2F89030 str r3, [r2, #144] +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !DUAL_CORE */ +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 941 .loc 1 1329 1 is_stmt 0 view .LVU223 + 942 0084 5DF8044B ldr r4, [sp], #4 + 943 .LCFI7: + 944 .cfi_restore 4 + ARM GAS /tmp/ccMGXY28.s page 59 + + + 945 .cfi_def_cfa_offset 0 + 946 0088 7047 bx lr + 947 .L80: + 948 008a 00BF .align 2 + 949 .L79: + 950 008c 00480258 .word 1476544512 + 951 .cfi_endproc + 952 .LFE153: + 954 .section .text.HAL_PWREx_DisableWakeUpPin,"ax",%progbits + 955 .align 1 + 956 .global HAL_PWREx_DisableWakeUpPin + 957 .syntax unified + 958 .thumb + 959 .thumb_func + 960 .fpu fpv5-d16 + 962 HAL_PWREx_DisableWakeUpPin: + 963 .LVL52: + 964 .LFB154: +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Wake-up PINx functionality. +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param WakeUpPin : Specifies the Wake-Up pin to be disabled. +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN. +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN. +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN. +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN. +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN. +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN. +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * devices that support GPIOI port. +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin) +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 965 .loc 1 1346 1 is_stmt 1 view -0 + 966 .cfi_startproc + 967 @ args = 0, pretend = 0, frame = 0 + 968 @ frame_needed = 0, uses_anonymous_args = 0 + 969 @ link register save eliminated. +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin)); + 970 .loc 1 1348 3 view .LVU225 +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the WakeUpPin */ +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->WKUPEPR, WakeUpPin); + 971 .loc 1 1351 3 view .LVU226 + 972 0000 024A ldr r2, .L82 + 973 0002 936A ldr r3, [r2, #40] + 974 0004 23EA0003 bic r3, r3, r0 + 975 0008 9362 str r3, [r2, #40] +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 976 .loc 1 1352 1 is_stmt 0 view .LVU227 + 977 000a 7047 bx lr + 978 .L83: + 979 .align 2 + 980 .L82: + ARM GAS /tmp/ccMGXY28.s page 60 + + + 981 000c 00480258 .word 1476544512 + 982 .cfi_endproc + 983 .LFE154: + 985 .section .text.HAL_PWREx_GetWakeupFlag,"ax",%progbits + 986 .align 1 + 987 .global HAL_PWREx_GetWakeupFlag + 988 .syntax unified + 989 .thumb + 990 .thumb_func + 991 .fpu fpv5-d16 + 993 HAL_PWREx_GetWakeupFlag: + 994 .LVL53: + 995 .LFB155: +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the Wake-Up Pin pending flags. +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8. +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13. +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11. +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1. +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * wake up pins. +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * devices that support GPIOI port. +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The Wake-Up pin flag. +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag) +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 996 .loc 1 1371 1 is_stmt 1 view -0 + 997 .cfi_startproc + 998 @ args = 0, pretend = 0, frame = 0 + 999 @ frame_needed = 0, uses_anonymous_args = 0 + 1000 @ link register save eliminated. +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + 1001 .loc 1 1373 3 view .LVU229 +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Return the wake up pin flag */ +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return (PWR->WKUPFR & WakeUpFlag); + 1002 .loc 1 1376 3 view .LVU230 + 1003 .loc 1 1376 14 is_stmt 0 view .LVU231 + 1004 0000 014B ldr r3, .L85 + 1005 0002 5B6A ldr r3, [r3, #36] +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1006 .loc 1 1377 1 view .LVU232 + 1007 0004 1840 ands r0, r0, r3 + 1008 .LVL54: + 1009 .loc 1 1377 1 view .LVU233 + 1010 0006 7047 bx lr + 1011 .L86: + 1012 .align 2 + 1013 .L85: + 1014 0008 00480258 .word 1476544512 + ARM GAS /tmp/ccMGXY28.s page 61 + + + 1015 .cfi_endproc + 1016 .LFE155: + 1018 .section .text.HAL_PWREx_ClearWakeupFlag,"ax",%progbits + 1019 .align 1 + 1020 .global HAL_PWREx_ClearWakeupFlag + 1021 .syntax unified + 1022 .thumb + 1023 .thumb_func + 1024 .fpu fpv5-d16 + 1026 HAL_PWREx_ClearWakeupFlag: + 1027 .LVL55: + 1028 .LFB156: +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Clear the Wake-Up pin pending flag. +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8. +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13. +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11. +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1. +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * all wake up pins. +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * devices that support GPIOI port. +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag) +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1029 .loc 1 1396 1 is_stmt 1 view -0 + 1030 .cfi_startproc + 1031 @ args = 0, pretend = 0, frame = 0 + 1032 @ frame_needed = 0, uses_anonymous_args = 0 + 1033 @ link register save eliminated. +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + 1034 .loc 1 1398 3 view .LVU235 +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear the wake up event received from wake up pin x */ +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->WKUPCR, WakeUpFlag); + 1035 .loc 1 1401 3 view .LVU236 + 1036 0000 054B ldr r3, .L90 + 1037 0002 1A6A ldr r2, [r3, #32] + 1038 0004 0243 orrs r2, r2, r0 + 1039 0006 1A62 str r2, [r3, #32] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the wake up event is well cleared */ +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->WKUPFR & WakeUpFlag) != 0U) + 1040 .loc 1 1404 3 view .LVU237 + 1041 .loc 1 1404 11 is_stmt 0 view .LVU238 + 1042 0008 5B6A ldr r3, [r3, #36] + 1043 .loc 1 1404 6 view .LVU239 + 1044 000a 0342 tst r3, r0 + 1045 000c 01D1 bne .L89 +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 62 + + +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 1046 .loc 1 1409 10 view .LVU240 + 1047 000e 0020 movs r0, #0 + 1048 .LVL56: + 1049 .loc 1 1409 10 view .LVU241 + 1050 0010 7047 bx lr + 1051 .LVL57: + 1052 .L89: +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1053 .loc 1 1406 12 view .LVU242 + 1054 0012 0120 movs r0, #1 + 1055 .LVL58: +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1056 .loc 1 1410 1 view .LVU243 + 1057 0014 7047 bx lr + 1058 .L91: + 1059 0016 00BF .align 2 + 1060 .L90: + 1061 0018 00480258 .word 1476544512 + 1062 .cfi_endproc + 1063 .LFE156: + 1065 .section .text.HAL_PWREx_WKUP1_Callback,"ax",%progbits + 1066 .align 1 + 1067 .weak HAL_PWREx_WKUP1_Callback + 1068 .syntax unified + 1069 .thumb + 1070 .thumb_func + 1071 .fpu fpv5-d16 + 1073 HAL_PWREx_WKUP1_Callback: + 1074 .LFB158: +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief This function handles the PWR WAKEUP PIN interrupt request. +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API should be called under the WAKEUP_PIN_IRQHandler(). +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_WAKEUP_PIN_IRQHandler (void) +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wakeup pin EXTI line interrupt detected */ +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF1 flag */ +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1); +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP1 interrupt user callback */ +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP1_Callback (); +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF2 flag */ +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2); +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP2 interrupt user callback */ +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP2_Callback (); + ARM GAS /tmp/ccMGXY28.s page 63 + + +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF3) +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF3 flag */ +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3); +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP3 interrupt user callback */ +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP3_Callback (); +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF3) */ +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF4 flag */ +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4); +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP4 interrupt user callback */ +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP4_Callback (); +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF5) +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U) +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF5 flag */ +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5); +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP5 interrupt user callback */ +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP5_Callback (); +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF5) */ +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR WKUPF6 flag */ +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6); +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR WKUP6 interrupt user callback */ +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_WKUP6_Callback (); +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP1 interrupt callback. +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP1_Callback (void) +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1075 .loc 1 1479 1 is_stmt 1 view -0 + 1076 .cfi_startproc + 1077 @ args = 0, pretend = 0, frame = 0 + 1078 @ frame_needed = 0, uses_anonymous_args = 0 + 1079 @ link register save eliminated. +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP1Callback can be implemented in the user file +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1080 .loc 1 1483 1 view .LVU245 + 1081 0000 7047 bx lr + 1082 .cfi_endproc + ARM GAS /tmp/ccMGXY28.s page 64 + + + 1083 .LFE158: + 1085 .section .text.HAL_PWREx_WKUP2_Callback,"ax",%progbits + 1086 .align 1 + 1087 .weak HAL_PWREx_WKUP2_Callback + 1088 .syntax unified + 1089 .thumb + 1090 .thumb_func + 1091 .fpu fpv5-d16 + 1093 HAL_PWREx_WKUP2_Callback: + 1094 .LFB159: +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP2 interrupt callback. +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP2_Callback (void) +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1095 .loc 1 1490 1 view -0 + 1096 .cfi_startproc + 1097 @ args = 0, pretend = 0, frame = 0 + 1098 @ frame_needed = 0, uses_anonymous_args = 0 + 1099 @ link register save eliminated. +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP2Callback can be implemented in the user file +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1100 .loc 1 1494 1 view .LVU247 + 1101 0000 7047 bx lr + 1102 .cfi_endproc + 1103 .LFE159: + 1105 .section .text.HAL_PWREx_WKUP3_Callback,"ax",%progbits + 1106 .align 1 + 1107 .weak HAL_PWREx_WKUP3_Callback + 1108 .syntax unified + 1109 .thumb + 1110 .thumb_func + 1111 .fpu fpv5-d16 + 1113 HAL_PWREx_WKUP3_Callback: + 1114 .LFB160: +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF3) +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP3 interrupt callback. +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP3_Callback (void) +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1115 .loc 1 1502 1 view -0 + 1116 .cfi_startproc + 1117 @ args = 0, pretend = 0, frame = 0 + 1118 @ frame_needed = 0, uses_anonymous_args = 0 + 1119 @ link register save eliminated. +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP3Callback can be implemented in the user file +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1120 .loc 1 1506 1 view .LVU249 + ARM GAS /tmp/ccMGXY28.s page 65 + + + 1121 0000 7047 bx lr + 1122 .cfi_endproc + 1123 .LFE160: + 1125 .section .text.HAL_PWREx_WKUP4_Callback,"ax",%progbits + 1126 .align 1 + 1127 .weak HAL_PWREx_WKUP4_Callback + 1128 .syntax unified + 1129 .thumb + 1130 .thumb_func + 1131 .fpu fpv5-d16 + 1133 HAL_PWREx_WKUP4_Callback: + 1134 .LFB161: +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF3) */ +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP4 interrupt callback. +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP4_Callback (void) +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1135 .loc 1 1514 1 view -0 + 1136 .cfi_startproc + 1137 @ args = 0, pretend = 0, frame = 0 + 1138 @ frame_needed = 0, uses_anonymous_args = 0 + 1139 @ link register save eliminated. +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP4Callback can be implemented in the user file +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1140 .loc 1 1518 1 view .LVU251 + 1141 0000 7047 bx lr + 1142 .cfi_endproc + 1143 .LFE161: + 1145 .section .text.HAL_PWREx_WKUP5_Callback,"ax",%progbits + 1146 .align 1 + 1147 .weak HAL_PWREx_WKUP5_Callback + 1148 .syntax unified + 1149 .thumb + 1150 .thumb_func + 1151 .fpu fpv5-d16 + 1153 HAL_PWREx_WKUP5_Callback: + 1154 .LFB162: +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF5) +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP5 interrupt callback. +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP5_Callback (void) +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1155 .loc 1 1526 1 view -0 + 1156 .cfi_startproc + 1157 @ args = 0, pretend = 0, frame = 0 + 1158 @ frame_needed = 0, uses_anonymous_args = 0 + 1159 @ link register save eliminated. +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP5Callback can be implemented in the user file + ARM GAS /tmp/ccMGXY28.s page 66 + + +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1160 .loc 1 1530 1 view .LVU253 + 1161 0000 7047 bx lr + 1162 .cfi_endproc + 1163 .LFE162: + 1165 .section .text.HAL_PWREx_WKUP6_Callback,"ax",%progbits + 1166 .align 1 + 1167 .weak HAL_PWREx_WKUP6_Callback + 1168 .syntax unified + 1169 .thumb + 1170 .thumb_func + 1171 .fpu fpv5-d16 + 1173 HAL_PWREx_WKUP6_Callback: + 1174 .LFB163: +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF5) */ +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR WKUP6 interrupt callback. +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP6_Callback (void) +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1175 .loc 1 1538 1 view -0 + 1176 .cfi_startproc + 1177 @ args = 0, pretend = 0, frame = 0 + 1178 @ frame_needed = 0, uses_anonymous_args = 0 + 1179 @ link register save eliminated. +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWREx_WKUP6Callback can be implemented in the user file +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1180 .loc 1 1542 1 view .LVU255 + 1181 0000 7047 bx lr + 1182 .cfi_endproc + 1183 .LFE163: + 1185 .section .text.HAL_PWREx_WAKEUP_PIN_IRQHandler,"ax",%progbits + 1186 .align 1 + 1187 .global HAL_PWREx_WAKEUP_PIN_IRQHandler + 1188 .syntax unified + 1189 .thumb + 1190 .thumb_func + 1191 .fpu fpv5-d16 + 1193 HAL_PWREx_WAKEUP_PIN_IRQHandler: + 1194 .LFB157: +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wakeup pin EXTI line interrupt detected */ + 1195 .loc 1 1418 1 view -0 + 1196 .cfi_startproc + 1197 @ args = 0, pretend = 0, frame = 0 + 1198 @ frame_needed = 0, uses_anonymous_args = 0 + 1199 0000 08B5 push {r3, lr} + 1200 .LCFI8: + 1201 .cfi_def_cfa_offset 8 + 1202 .cfi_offset 3, -8 + 1203 .cfi_offset 14, -4 +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1204 .loc 1 1420 3 view .LVU257 + ARM GAS /tmp/ccMGXY28.s page 67 + + +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1205 .loc 1 1420 7 is_stmt 0 view .LVU258 + 1206 0002 244B ldr r3, .L110 + 1207 0004 5B6A ldr r3, [r3, #36] +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1208 .loc 1 1420 6 view .LVU259 + 1209 0006 13F0010F tst r3, #1 + 1210 000a 1BD1 bne .L106 +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1211 .loc 1 1428 8 is_stmt 1 view .LVU260 +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1212 .loc 1 1428 12 is_stmt 0 view .LVU261 + 1213 000c 214B ldr r3, .L110 + 1214 000e 5B6A ldr r3, [r3, #36] +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1215 .loc 1 1428 11 view .LVU262 + 1216 0010 13F0020F tst r3, #2 + 1217 0014 1ED1 bne .L107 +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1218 .loc 1 1437 8 is_stmt 1 view .LVU263 +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1219 .loc 1 1437 12 is_stmt 0 view .LVU264 + 1220 0016 1F4B ldr r3, .L110 + 1221 0018 5B6A ldr r3, [r3, #36] +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1222 .loc 1 1437 11 view .LVU265 + 1223 001a 13F0040F tst r3, #4 + 1224 001e 21D1 bne .L108 +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1225 .loc 1 1446 8 is_stmt 1 view .LVU266 +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1226 .loc 1 1446 12 is_stmt 0 view .LVU267 + 1227 0020 1C4B ldr r3, .L110 + 1228 0022 5B6A ldr r3, [r3, #36] +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1229 .loc 1 1446 11 view .LVU268 + 1230 0024 13F0080F tst r3, #8 + 1231 0028 24D1 bne .L109 +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1232 .loc 1 1455 8 is_stmt 1 view .LVU269 +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1233 .loc 1 1455 12 is_stmt 0 view .LVU270 + 1234 002a 1A4B ldr r3, .L110 + 1235 002c 5B6A ldr r3, [r3, #36] +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1236 .loc 1 1455 11 view .LVU271 + 1237 002e 13F0100F tst r3, #16 + 1238 0032 27D0 beq .L104 +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1239 .loc 1 1458 5 is_stmt 1 view .LVU272 + 1240 0034 174A ldr r2, .L110 + 1241 0036 136A ldr r3, [r2, #32] + 1242 0038 43F01003 orr r3, r3, #16 + 1243 003c 1362 str r3, [r2, #32] +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1244 .loc 1 1461 5 view .LVU273 + 1245 003e FFF7FEFF bl HAL_PWREx_WKUP5_Callback + ARM GAS /tmp/ccMGXY28.s page 68 + + + 1246 .LVL59: + 1247 0042 06E0 b .L98 + 1248 .L106: +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1249 .loc 1 1423 5 view .LVU274 + 1250 0044 134A ldr r2, .L110 + 1251 0046 136A ldr r3, [r2, #32] + 1252 0048 43F00103 orr r3, r3, #1 + 1253 004c 1362 str r3, [r2, #32] +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1254 .loc 1 1426 5 view .LVU275 + 1255 004e FFF7FEFF bl HAL_PWREx_WKUP1_Callback + 1256 .LVL60: + 1257 .L98: +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1258 .loc 1 1472 1 is_stmt 0 view .LVU276 + 1259 0052 08BD pop {r3, pc} + 1260 .L107: +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1261 .loc 1 1431 5 is_stmt 1 view .LVU277 + 1262 0054 0F4A ldr r2, .L110 + 1263 0056 136A ldr r3, [r2, #32] + 1264 0058 43F00203 orr r3, r3, #2 + 1265 005c 1362 str r3, [r2, #32] +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1266 .loc 1 1434 5 view .LVU278 + 1267 005e FFF7FEFF bl HAL_PWREx_WKUP2_Callback + 1268 .LVL61: + 1269 0062 F6E7 b .L98 + 1270 .L108: +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1271 .loc 1 1440 5 view .LVU279 + 1272 0064 0B4A ldr r2, .L110 + 1273 0066 136A ldr r3, [r2, #32] + 1274 0068 43F00403 orr r3, r3, #4 + 1275 006c 1362 str r3, [r2, #32] +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1276 .loc 1 1443 5 view .LVU280 + 1277 006e FFF7FEFF bl HAL_PWREx_WKUP3_Callback + 1278 .LVL62: + 1279 0072 EEE7 b .L98 + 1280 .L109: +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1281 .loc 1 1449 5 view .LVU281 + 1282 0074 074A ldr r2, .L110 + 1283 0076 136A ldr r3, [r2, #32] + 1284 0078 43F00803 orr r3, r3, #8 + 1285 007c 1362 str r3, [r2, #32] +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1286 .loc 1 1452 5 view .LVU282 + 1287 007e FFF7FEFF bl HAL_PWREx_WKUP4_Callback + 1288 .LVL63: + 1289 0082 E6E7 b .L98 + 1290 .L104: +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1291 .loc 1 1467 5 view .LVU283 + 1292 0084 034A ldr r2, .L110 + ARM GAS /tmp/ccMGXY28.s page 69 + + + 1293 0086 136A ldr r3, [r2, #32] + 1294 0088 43F02003 orr r3, r3, #32 + 1295 008c 1362 str r3, [r2, #32] +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1296 .loc 1 1470 5 view .LVU284 + 1297 008e FFF7FEFF bl HAL_PWREx_WKUP6_Callback + 1298 .LVL64: +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 1299 .loc 1 1472 1 is_stmt 0 view .LVU285 + 1300 0092 DEE7 b .L98 + 1301 .L111: + 1302 .align 2 + 1303 .L110: + 1304 0094 00480258 .word 1476544512 + 1305 .cfi_endproc + 1306 .LFE157: + 1308 .section .text.HAL_PWREx_EnableBkUpReg,"ax",%progbits + 1309 .align 1 + 1310 .global HAL_PWREx_EnableBkUpReg + 1311 .syntax unified + 1312 .thumb + 1313 .thumb_func + 1314 .fpu fpv5-d16 + 1316 HAL_PWREx_EnableBkUpReg: + 1317 .LFB164: +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Peripherals control functions +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Peripherals control functions ##### +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** Main and Backup Regulators configuration *** +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ================================================ +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The backup domain includes 4 Kbytes of backup SRAM accessible only +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** content is retained even in Standby or VBAT mode when the low power +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** backup regulator is enabled. It can be considered as an internal +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** EEPROM when VBAT is always present. You can use the +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableBkUpReg() function to enable the low power backup +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regulator. +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) When the backup domain is supplied by VDD (analog switch connected to +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VDD) the backup SRAM is powered from VDD which replaces the VBAT power +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** supply to save battery life. +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** protected to prevent confidential data, such as cryptographic private +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** key, from being accessed. The backup SRAM can be erased only through +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the Flash interface when a protection level change from level 1 to +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** level 0 is requested. +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** -@- Refer to the description of Read protection (RDP) in the Flash +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** programming manual. + ARM GAS /tmp/ccMGXY28.s page 70 + + +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The main internal regulator can be configured to have a tradeoff +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** between performance and power consumption when the device does not +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** operate at the maximum frequency. This is done through +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** bit in PWR_D3CR register. +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The main internal regulator can be configured to operate in Low Power +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mode when the system enters STOP mode to further reduce power +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** consumption. +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS) +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function which configure the SVOS bit in PWR_CR1 register. +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** The selected SVOS4 and SVOS5 levels add an additional startup delay +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** when exiting from system Stop mode. +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** -@- Refer to the product datasheets for more details. +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** USB Regulator configuration *** +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =================================== +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The USB transceivers are supplied from a dedicated VDD33USB supply +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** that can be provided either by the integrated USB regulator, or by an +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** external USB supply. +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VDD33USB is then provided from the USB regulator. +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) When the USB regulator is enabled, the VDD33USB supply level detector +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** shall be enabled through HAL_PWREx_EnableUSBVoltageDetector() +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function. +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function and VDD33USB can be provided from an external supply. In this +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** case VDD33USB and VDD50USB shall be connected together. +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** VBAT battery charging *** +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ============================= +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) When VDD is present, the external battery connected to VBAT can be +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** charged through an internal resistance. VBAT charging can be performed +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** either through a 5 KOhm resistor or through a 1.5 KOhm resistor. +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (ResistorValue) function with: +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (++) ResistorValue: +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** function. +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Backup Regulator. +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void) +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1318 .loc 1 1627 1 is_stmt 1 view -0 + 1319 .cfi_startproc + 1320 @ args = 0, pretend = 0, frame = 0 + 1321 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccMGXY28.s page 71 + + + 1322 0000 10B5 push {r4, lr} + 1323 .LCFI9: + 1324 .cfi_def_cfa_offset 8 + 1325 .cfi_offset 4, -8 + 1326 .cfi_offset 14, -4 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 1327 .loc 1 1628 3 view .LVU287 +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Backup regulator */ +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR2, PWR_CR2_BREN); + 1328 .loc 1 1631 3 view .LVU288 + 1329 0002 0B4A ldr r2, .L119 + 1330 0004 9368 ldr r3, [r2, #8] + 1331 0006 43F00103 orr r3, r3, #1 + 1332 000a 9360 str r3, [r2, #8] +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 1333 .loc 1 1634 3 view .LVU289 + 1334 .loc 1 1634 15 is_stmt 0 view .LVU290 + 1335 000c FFF7FEFF bl HAL_GetTick + 1336 .LVL65: + 1337 0010 0446 mov r4, r0 + 1338 .LVL66: +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is set */ +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U) + 1339 .loc 1 1637 3 is_stmt 1 view .LVU291 + 1340 .L113: + 1341 .loc 1 1637 9 view .LVU292 + 1342 .loc 1 1637 10 is_stmt 0 view .LVU293 + 1343 0012 074B ldr r3, .L119 + 1344 0014 9B68 ldr r3, [r3, #8] + 1345 .loc 1 1637 9 view .LVU294 + 1346 0016 13F4803F tst r3, #65536 + 1347 001a 07D1 bne .L118 +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + 1348 .loc 1 1639 5 is_stmt 1 view .LVU295 + 1349 .loc 1 1639 10 is_stmt 0 view .LVU296 + 1350 001c FFF7FEFF bl HAL_GetTick + 1351 .LVL67: + 1352 .loc 1 1639 24 view .LVU297 + 1353 0020 001B subs r0, r0, r4 + 1354 .loc 1 1639 8 view .LVU298 + 1355 0022 B0F57A7F cmp r0, #1000 + 1356 0026 F4D9 bls .L113 +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 1357 .loc 1 1641 14 view .LVU299 + 1358 0028 0120 movs r0, #1 + 1359 002a 00E0 b .L114 + 1360 .L118: +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + ARM GAS /tmp/ccMGXY28.s page 72 + + + 1361 .loc 1 1645 10 view .LVU300 + 1362 002c 0020 movs r0, #0 + 1363 .L114: +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1364 .loc 1 1646 1 view .LVU301 + 1365 002e 10BD pop {r4, pc} + 1366 .LVL68: + 1367 .L120: + 1368 .loc 1 1646 1 view .LVU302 + 1369 .align 2 + 1370 .L119: + 1371 0030 00480258 .word 1476544512 + 1372 .cfi_endproc + 1373 .LFE164: + 1375 .section .text.HAL_PWREx_DisableBkUpReg,"ax",%progbits + 1376 .align 1 + 1377 .global HAL_PWREx_DisableBkUpReg + 1378 .syntax unified + 1379 .thumb + 1380 .thumb_func + 1381 .fpu fpv5-d16 + 1383 HAL_PWREx_DisableBkUpReg: + 1384 .LFB165: +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Backup Regulator. +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void) +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1385 .loc 1 1653 1 is_stmt 1 view -0 + 1386 .cfi_startproc + 1387 @ args = 0, pretend = 0, frame = 0 + 1388 @ frame_needed = 0, uses_anonymous_args = 0 + 1389 0000 10B5 push {r4, lr} + 1390 .LCFI10: + 1391 .cfi_def_cfa_offset 8 + 1392 .cfi_offset 4, -8 + 1393 .cfi_offset 14, -4 +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 1394 .loc 1 1654 3 view .LVU304 +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Backup regulator */ +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR2, PWR_CR2_BREN); + 1395 .loc 1 1657 3 view .LVU305 + 1396 0002 0B4A ldr r2, .L128 + 1397 0004 9368 ldr r3, [r2, #8] + 1398 0006 23F00103 bic r3, r3, #1 + 1399 000a 9360 str r3, [r2, #8] +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 1400 .loc 1 1660 3 view .LVU306 + 1401 .loc 1 1660 15 is_stmt 0 view .LVU307 + 1402 000c FFF7FEFF bl HAL_GetTick + 1403 .LVL69: + 1404 0010 0446 mov r4, r0 + ARM GAS /tmp/ccMGXY28.s page 73 + + + 1405 .LVL70: +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is reset */ +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U) + 1406 .loc 1 1663 3 is_stmt 1 view .LVU308 + 1407 .L122: + 1408 .loc 1 1663 9 view .LVU309 + 1409 .loc 1 1663 10 is_stmt 0 view .LVU310 + 1410 0012 074B ldr r3, .L128 + 1411 0014 9B68 ldr r3, [r3, #8] + 1412 .loc 1 1663 9 view .LVU311 + 1413 0016 13F4803F tst r3, #65536 + 1414 001a 07D0 beq .L127 +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + 1415 .loc 1 1665 5 is_stmt 1 view .LVU312 + 1416 .loc 1 1665 10 is_stmt 0 view .LVU313 + 1417 001c FFF7FEFF bl HAL_GetTick + 1418 .LVL71: + 1419 .loc 1 1665 24 view .LVU314 + 1420 0020 001B subs r0, r0, r4 + 1421 .loc 1 1665 8 view .LVU315 + 1422 0022 B0F57A7F cmp r0, #1000 + 1423 0026 F4D9 bls .L122 +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 1424 .loc 1 1667 14 view .LVU316 + 1425 0028 0120 movs r0, #1 + 1426 002a 00E0 b .L123 + 1427 .L127: +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 1428 .loc 1 1671 10 view .LVU317 + 1429 002c 0020 movs r0, #0 + 1430 .L123: +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1431 .loc 1 1672 1 view .LVU318 + 1432 002e 10BD pop {r4, pc} + 1433 .LVL72: + 1434 .L129: + 1435 .loc 1 1672 1 view .LVU319 + 1436 .align 2 + 1437 .L128: + 1438 0030 00480258 .word 1476544512 + 1439 .cfi_endproc + 1440 .LFE165: + 1442 .section .text.HAL_PWREx_EnableUSBReg,"ax",%progbits + 1443 .align 1 + 1444 .global HAL_PWREx_EnableUSBReg + 1445 .syntax unified + 1446 .thumb + 1447 .thumb_func + 1448 .fpu fpv5-d16 + 1450 HAL_PWREx_EnableUSBReg: + 1451 .LFB166: + ARM GAS /tmp/ccMGXY28.s page 74 + + +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the USB Regulator. +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void) +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1452 .loc 1 1679 1 is_stmt 1 view -0 + 1453 .cfi_startproc + 1454 @ args = 0, pretend = 0, frame = 0 + 1455 @ frame_needed = 0, uses_anonymous_args = 0 + 1456 0000 10B5 push {r4, lr} + 1457 .LCFI11: + 1458 .cfi_def_cfa_offset 8 + 1459 .cfi_offset 4, -8 + 1460 .cfi_offset 14, -4 +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 1461 .loc 1 1680 3 view .LVU321 +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the USB regulator */ +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR3, PWR_CR3_USBREGEN); + 1462 .loc 1 1683 3 view .LVU322 + 1463 0002 0B4A ldr r2, .L137 + 1464 0004 D368 ldr r3, [r2, #12] + 1465 0006 43F00073 orr r3, r3, #33554432 + 1466 000a D360 str r3, [r2, #12] +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 1467 .loc 1 1686 3 view .LVU323 + 1468 .loc 1 1686 15 is_stmt 0 view .LVU324 + 1469 000c FFF7FEFF bl HAL_GetTick + 1470 .LVL73: + 1471 0010 0446 mov r4, r0 + 1472 .LVL74: +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till the USB regulator ready flag is set */ +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U) + 1473 .loc 1 1689 3 is_stmt 1 view .LVU325 + 1474 .L131: + 1475 .loc 1 1689 9 view .LVU326 + 1476 .loc 1 1689 10 is_stmt 0 view .LVU327 + 1477 0012 074B ldr r3, .L137 + 1478 0014 DB68 ldr r3, [r3, #12] + 1479 .loc 1 1689 9 view .LVU328 + 1480 0016 13F0806F tst r3, #67108864 + 1481 001a 07D1 bne .L136 +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + 1482 .loc 1 1691 5 is_stmt 1 view .LVU329 + 1483 .loc 1 1691 10 is_stmt 0 view .LVU330 + 1484 001c FFF7FEFF bl HAL_GetTick + 1485 .LVL75: + 1486 .loc 1 1691 24 view .LVU331 + 1487 0020 001B subs r0, r0, r4 + 1488 .loc 1 1691 8 view .LVU332 + 1489 0022 B0F57A7F cmp r0, #1000 + ARM GAS /tmp/ccMGXY28.s page 75 + + + 1490 0026 F4D9 bls .L131 +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 1491 .loc 1 1693 14 view .LVU333 + 1492 0028 0120 movs r0, #1 + 1493 002a 00E0 b .L132 + 1494 .L136: +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 1495 .loc 1 1697 10 view .LVU334 + 1496 002c 0020 movs r0, #0 + 1497 .L132: +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1498 .loc 1 1698 1 view .LVU335 + 1499 002e 10BD pop {r4, pc} + 1500 .LVL76: + 1501 .L138: + 1502 .loc 1 1698 1 view .LVU336 + 1503 .align 2 + 1504 .L137: + 1505 0030 00480258 .word 1476544512 + 1506 .cfi_endproc + 1507 .LFE166: + 1509 .section .text.HAL_PWREx_DisableUSBReg,"ax",%progbits + 1510 .align 1 + 1511 .global HAL_PWREx_DisableUSBReg + 1512 .syntax unified + 1513 .thumb + 1514 .thumb_func + 1515 .fpu fpv5-d16 + 1517 HAL_PWREx_DisableUSBReg: + 1518 .LFB167: +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the USB Regulator. +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void) +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1519 .loc 1 1705 1 is_stmt 1 view -0 + 1520 .cfi_startproc + 1521 @ args = 0, pretend = 0, frame = 0 + 1522 @ frame_needed = 0, uses_anonymous_args = 0 + 1523 0000 10B5 push {r4, lr} + 1524 .LCFI12: + 1525 .cfi_def_cfa_offset 8 + 1526 .cfi_offset 4, -8 + 1527 .cfi_offset 14, -4 +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tickstart; + 1528 .loc 1 1706 3 view .LVU338 +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the USB regulator */ +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN); + 1529 .loc 1 1709 3 view .LVU339 + 1530 0002 0B4A ldr r2, .L146 + ARM GAS /tmp/ccMGXY28.s page 76 + + + 1531 0004 D368 ldr r3, [r2, #12] + 1532 0006 23F00073 bic r3, r3, #33554432 + 1533 000a D360 str r3, [r2, #12] +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Get tick */ +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick (); + 1534 .loc 1 1712 3 view .LVU340 + 1535 .loc 1 1712 15 is_stmt 0 view .LVU341 + 1536 000c FFF7FEFF bl HAL_GetTick + 1537 .LVL77: + 1538 0010 0446 mov r4, r0 + 1539 .LVL78: +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wait till the USB regulator ready flag is reset */ +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U) + 1540 .loc 1 1715 3 is_stmt 1 view .LVU342 + 1541 .L140: + 1542 .loc 1 1715 8 view .LVU343 + 1543 .loc 1 1715 9 is_stmt 0 view .LVU344 + 1544 0012 074B ldr r3, .L146 + 1545 0014 DB68 ldr r3, [r3, #12] + 1546 .loc 1 1715 8 view .LVU345 + 1547 0016 13F0806F tst r3, #67108864 + 1548 001a 07D0 beq .L145 +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + 1549 .loc 1 1717 5 is_stmt 1 view .LVU346 + 1550 .loc 1 1717 10 is_stmt 0 view .LVU347 + 1551 001c FFF7FEFF bl HAL_GetTick + 1552 .LVL79: + 1553 .loc 1 1717 24 view .LVU348 + 1554 0020 001B subs r0, r0, r4 + 1555 .loc 1 1717 8 view .LVU349 + 1556 0022 B0F57A7F cmp r0, #1000 + 1557 0026 F4D9 bls .L140 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_ERROR; + 1558 .loc 1 1719 14 view .LVU350 + 1559 0028 0120 movs r0, #1 + 1560 002a 00E0 b .L141 + 1561 .L145: +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return HAL_OK; + 1562 .loc 1 1723 10 view .LVU351 + 1563 002c 0020 movs r0, #0 + 1564 .L141: +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1565 .loc 1 1724 1 view .LVU352 + 1566 002e 10BD pop {r4, pc} + 1567 .LVL80: + 1568 .L147: + 1569 .loc 1 1724 1 view .LVU353 + 1570 .align 2 + 1571 .L146: + 1572 0030 00480258 .word 1476544512 + ARM GAS /tmp/ccMGXY28.s page 77 + + + 1573 .cfi_endproc + 1574 .LFE167: + 1576 .section .text.HAL_PWREx_EnableUSBVoltageDetector,"ax",%progbits + 1577 .align 1 + 1578 .global HAL_PWREx_EnableUSBVoltageDetector + 1579 .syntax unified + 1580 .thumb + 1581 .thumb_func + 1582 .fpu fpv5-d16 + 1584 HAL_PWREx_EnableUSBVoltageDetector: + 1585 .LFB168: +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the USB voltage level detector. +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableUSBVoltageDetector (void) +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1586 .loc 1 1731 1 is_stmt 1 view -0 + 1587 .cfi_startproc + 1588 @ args = 0, pretend = 0, frame = 0 + 1589 @ frame_needed = 0, uses_anonymous_args = 0 + 1590 @ link register save eliminated. +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the USB voltage detector */ +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); + 1591 .loc 1 1733 3 view .LVU355 + 1592 0000 024A ldr r2, .L149 + 1593 0002 D368 ldr r3, [r2, #12] + 1594 0004 43F08073 orr r3, r3, #16777216 + 1595 0008 D360 str r3, [r2, #12] +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1596 .loc 1 1734 1 is_stmt 0 view .LVU356 + 1597 000a 7047 bx lr + 1598 .L150: + 1599 .align 2 + 1600 .L149: + 1601 000c 00480258 .word 1476544512 + 1602 .cfi_endproc + 1603 .LFE168: + 1605 .section .text.HAL_PWREx_DisableUSBVoltageDetector,"ax",%progbits + 1606 .align 1 + 1607 .global HAL_PWREx_DisableUSBVoltageDetector + 1608 .syntax unified + 1609 .thumb + 1610 .thumb_func + 1611 .fpu fpv5-d16 + 1613 HAL_PWREx_DisableUSBVoltageDetector: + 1614 .LFB169: +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the USB voltage level detector. +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableUSBVoltageDetector (void) +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1615 .loc 1 1741 1 is_stmt 1 view -0 + 1616 .cfi_startproc + ARM GAS /tmp/ccMGXY28.s page 78 + + + 1617 @ args = 0, pretend = 0, frame = 0 + 1618 @ frame_needed = 0, uses_anonymous_args = 0 + 1619 @ link register save eliminated. +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the USB voltage detector */ +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN); + 1620 .loc 1 1743 3 view .LVU358 + 1621 0000 024A ldr r2, .L152 + 1622 0002 D368 ldr r3, [r2, #12] + 1623 0004 23F08073 bic r3, r3, #16777216 + 1624 0008 D360 str r3, [r2, #12] +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1625 .loc 1 1744 1 is_stmt 0 view .LVU359 + 1626 000a 7047 bx lr + 1627 .L153: + 1628 .align 2 + 1629 .L152: + 1630 000c 00480258 .word 1476544512 + 1631 .cfi_endproc + 1632 .LFE169: + 1634 .section .text.HAL_PWREx_EnableBatteryCharging,"ax",%progbits + 1635 .align 1 + 1636 .global HAL_PWREx_EnableBatteryCharging + 1637 .syntax unified + 1638 .thumb + 1639 .thumb_func + 1640 .fpu fpv5-d16 + 1642 HAL_PWREx_EnableBatteryCharging: + 1643 .LVL81: + 1644 .LFB170: +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Battery charging. +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note When VDD is present, charge the external battery through an internal +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * resistor. +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param ResistorValue : Specifies the charging resistor. +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * This parameter can be one of the following values : +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue) +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1645 .loc 1 1757 1 is_stmt 1 view -0 + 1646 .cfi_startproc + 1647 @ args = 0, pretend = 0, frame = 0 + 1648 @ frame_needed = 0, uses_anonymous_args = 0 + 1649 @ link register save eliminated. +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameter */ +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue)); + 1650 .loc 1 1759 3 view .LVU361 +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Specify the charging resistor */ +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue); + 1651 .loc 1 1762 3 view .LVU362 + 1652 0000 054A ldr r2, .L155 + 1653 0002 D368 ldr r3, [r2, #12] + 1654 0004 23F40073 bic r3, r3, #512 + ARM GAS /tmp/ccMGXY28.s page 79 + + + 1655 0008 0343 orrs r3, r3, r0 + 1656 000a D360 str r3, [r2, #12] +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Battery charging */ +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR3, PWR_CR3_VBE); + 1657 .loc 1 1765 3 view .LVU363 + 1658 000c D368 ldr r3, [r2, #12] + 1659 000e 43F48073 orr r3, r3, #256 + 1660 0012 D360 str r3, [r2, #12] +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1661 .loc 1 1766 1 is_stmt 0 view .LVU364 + 1662 0014 7047 bx lr + 1663 .L156: + 1664 0016 00BF .align 2 + 1665 .L155: + 1666 0018 00480258 .word 1476544512 + 1667 .cfi_endproc + 1668 .LFE170: + 1670 .section .text.HAL_PWREx_DisableBatteryCharging,"ax",%progbits + 1671 .align 1 + 1672 .global HAL_PWREx_DisableBatteryCharging + 1673 .syntax unified + 1674 .thumb + 1675 .thumb_func + 1676 .fpu fpv5-d16 + 1678 HAL_PWREx_DisableBatteryCharging: + 1679 .LFB171: +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Battery charging. +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableBatteryCharging (void) +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1680 .loc 1 1773 1 is_stmt 1 view -0 + 1681 .cfi_startproc + 1682 @ args = 0, pretend = 0, frame = 0 + 1683 @ frame_needed = 0, uses_anonymous_args = 0 + 1684 @ link register save eliminated. +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Battery charging */ +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR3, PWR_CR3_VBE); + 1685 .loc 1 1775 3 view .LVU366 + 1686 0000 024A ldr r2, .L158 + 1687 0002 D368 ldr r3, [r2, #12] + 1688 0004 23F48073 bic r3, r3, #256 + 1689 0008 D360 str r3, [r2, #12] +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1690 .loc 1 1776 1 is_stmt 0 view .LVU367 + 1691 000a 7047 bx lr + 1692 .L159: + 1693 .align 2 + 1694 .L158: + 1695 000c 00480258 .word 1476544512 + 1696 .cfi_endproc + 1697 .LFE171: + 1699 .section .text.HAL_PWREx_EnableMonitoring,"ax",%progbits + 1700 .align 1 + ARM GAS /tmp/ccMGXY28.s page 80 + + + 1701 .global HAL_PWREx_EnableMonitoring + 1702 .syntax unified + 1703 .thumb + 1704 .thumb_func + 1705 .fpu fpv5-d16 + 1707 HAL_PWREx_EnableMonitoring: + 1708 .LFB172: +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CR1_BOOSTE) +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the booster to guarantee the analog switch AC performance when +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the VDD supply voltage is below 2V7. +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note The VDD supply voltage can be monitored through the PVD and the PLS +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * field bits. +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableAnalogBooster (void) +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Analog voltage */ +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_AVD_READY); +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable VDDA booster */ +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_BOOSTE); +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the analog booster. +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableAnalogBooster (void) +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable VDDA booster */ +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE); +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Analog voltage */ +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY); +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CR1_BOOSTE) */ +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @} +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Power Monitoring functions +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ##### Power Monitoring functions ##### +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** =============================================================================== +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** VBAT and Temperature supervision *** +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ======================================== +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The VBAT battery voltage supply can be monitored by comparing it with +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** lower than the threshold. + ARM GAS /tmp/ccMGXY28.s page 81 + + +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The temperature can be monitored by comparing it with two threshold +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** control register 2 (PWR_CR2), indicate whether the device temperature +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** is higher or lower than the threshold. +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The VBAT and the temperature monitoring is enabled by +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_EnableMonitoring() function and disabled by +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_DisableMonitoring() function. +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** level which can be : +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** *** AVD configuration *** +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** ========================= +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** [..] +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The AVD is used to monitor the VDDA power supply by comparing it to a +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** register). +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) A AVDO flag is available to indicate if VDDA is higher or lower +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** than the AVD threshold. This event is internally connected to the EXTI +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** line 16 to generate an interrupt if enabled. +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro. +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** (+) The AVD is stopped in System Standby mode. +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @{ +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the VBAT and temperature monitoring. +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMonitoring (void) +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1709 .loc 1 1863 1 is_stmt 1 view -0 + 1710 .cfi_startproc + 1711 @ args = 0, pretend = 0, frame = 0 + 1712 @ frame_needed = 0, uses_anonymous_args = 0 + 1713 @ link register save eliminated. +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the VBAT and Temperature monitoring */ +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR2, PWR_CR2_MONEN); + 1714 .loc 1 1865 3 view .LVU369 + 1715 0000 024A ldr r2, .L161 + 1716 0002 9368 ldr r3, [r2, #8] + 1717 0004 43F01003 orr r3, r3, #16 + 1718 0008 9360 str r3, [r2, #8] +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1719 .loc 1 1866 1 is_stmt 0 view .LVU370 + 1720 000a 7047 bx lr + 1721 .L162: + 1722 .align 2 + 1723 .L161: + 1724 000c 00480258 .word 1476544512 + 1725 .cfi_endproc + ARM GAS /tmp/ccMGXY28.s page 82 + + + 1726 .LFE172: + 1728 .section .text.HAL_PWREx_DisableMonitoring,"ax",%progbits + 1729 .align 1 + 1730 .global HAL_PWREx_DisableMonitoring + 1731 .syntax unified + 1732 .thumb + 1733 .thumb_func + 1734 .fpu fpv5-d16 + 1736 HAL_PWREx_DisableMonitoring: + 1737 .LFB173: +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the VBAT and temperature monitoring. +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval HAL status. +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMonitoring (void) +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1738 .loc 1 1873 1 is_stmt 1 view -0 + 1739 .cfi_startproc + 1740 @ args = 0, pretend = 0, frame = 0 + 1741 @ frame_needed = 0, uses_anonymous_args = 0 + 1742 @ link register save eliminated. +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the VBAT and Temperature monitoring */ +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN); + 1743 .loc 1 1875 3 view .LVU372 + 1744 0000 024A ldr r2, .L164 + 1745 0002 9368 ldr r3, [r2, #8] + 1746 0004 23F01003 bic r3, r3, #16 + 1747 0008 9360 str r3, [r2, #8] +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1748 .loc 1 1876 1 is_stmt 0 view .LVU373 + 1749 000a 7047 bx lr + 1750 .L165: + 1751 .align 2 + 1752 .L164: + 1753 000c 00480258 .word 1476544512 + 1754 .cfi_endproc + 1755 .LFE173: + 1757 .section .text.HAL_PWREx_GetTemperatureLevel,"ax",%progbits + 1758 .align 1 + 1759 .global HAL_PWREx_GetTemperatureLevel + 1760 .syntax unified + 1761 .thumb + 1762 .thumb_func + 1763 .fpu fpv5-d16 + 1765 HAL_PWREx_GetTemperatureLevel: + 1766 .LFB174: +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Indicate whether the junction temperature is between, above or below +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the thresholds. +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval Temperature level. +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetTemperatureLevel (void) +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1767 .loc 1 1884 1 is_stmt 1 view -0 + 1768 .cfi_startproc + ARM GAS /tmp/ccMGXY28.s page 83 + + + 1769 @ args = 0, pretend = 0, frame = 0 + 1770 @ frame_needed = 0, uses_anonymous_args = 0 + 1771 @ link register save eliminated. +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t tempLevel, regValue; + 1772 .loc 1 1885 3 view .LVU375 +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Read the temperature flags */ +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL)); + 1773 .loc 1 1888 3 view .LVU376 + 1774 .loc 1 1888 14 is_stmt 0 view .LVU377 + 1775 0000 054B ldr r3, .L169 + 1776 0002 9868 ldr r0, [r3, #8] + 1777 .loc 1 1888 12 view .LVU378 + 1778 0004 00F44000 and r0, r0, #12582912 + 1779 .LVL82: +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the temperature is below the threshold */ +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (regValue == PWR_CR2_TEMPL) + 1780 .loc 1 1891 3 is_stmt 1 view .LVU379 + 1781 .loc 1 1891 6 is_stmt 0 view .LVU380 + 1782 0008 B0F5800F cmp r0, #4194304 + 1783 000c 03D0 beq .L166 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the temperature is above the threshold */ +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (regValue == PWR_CR2_TEMPH) + 1784 .loc 1 1896 8 is_stmt 1 view .LVU381 + 1785 .loc 1 1896 11 is_stmt 0 view .LVU382 + 1786 000e B0F5000F cmp r0, #8388608 + 1787 0012 00D0 beq .L166 +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* The temperature is between the thresholds */ +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; + 1788 .loc 1 1903 15 view .LVU383 + 1789 0014 0020 movs r0, #0 + 1790 .LVL83: +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return tempLevel; + 1791 .loc 1 1906 3 is_stmt 1 view .LVU384 + 1792 .L166: +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1793 .loc 1 1907 1 is_stmt 0 view .LVU385 + 1794 0016 7047 bx lr + 1795 .L170: + 1796 .align 2 + 1797 .L169: + 1798 0018 00480258 .word 1476544512 + 1799 .cfi_endproc + 1800 .LFE174: + 1802 .section .text.HAL_PWREx_GetVBATLevel,"ax",%progbits + 1803 .align 1 + ARM GAS /tmp/ccMGXY28.s page 84 + + + 1804 .global HAL_PWREx_GetVBATLevel + 1805 .syntax unified + 1806 .thumb + 1807 .thumb_func + 1808 .fpu fpv5-d16 + 1810 HAL_PWREx_GetVBATLevel: + 1811 .LFB175: +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Indicate whether the Battery voltage level is between, above or below +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the thresholds. +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval VBAT level. +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVBATLevel (void) +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1812 .loc 1 1915 1 is_stmt 1 view -0 + 1813 .cfi_startproc + 1814 @ args = 0, pretend = 0, frame = 0 + 1815 @ frame_needed = 0, uses_anonymous_args = 0 + 1816 @ link register save eliminated. +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t VBATLevel, regValue; + 1817 .loc 1 1916 3 view .LVU387 +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Read the VBAT flags */ +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL)); + 1818 .loc 1 1919 3 view .LVU388 + 1819 .loc 1 1919 14 is_stmt 0 view .LVU389 + 1820 0000 054B ldr r3, .L174 + 1821 0002 9868 ldr r0, [r3, #8] + 1822 .loc 1 1919 12 view .LVU390 + 1823 0004 00F44010 and r0, r0, #3145728 + 1824 .LVL84: +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the VBAT is below the threshold */ +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (regValue == PWR_CR2_VBATL) + 1825 .loc 1 1922 3 is_stmt 1 view .LVU391 + 1826 .loc 1 1922 6 is_stmt 0 view .LVU392 + 1827 0008 B0F5801F cmp r0, #1048576 + 1828 000c 03D0 beq .L171 +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the VBAT is above the threshold */ +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else if (regValue == PWR_CR2_VBATH) + 1829 .loc 1 1927 8 is_stmt 1 view .LVU393 + 1830 .loc 1 1927 11 is_stmt 0 view .LVU394 + 1831 000e B0F5001F cmp r0, #2097152 + 1832 0012 00D0 beq .L171 +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* The VBAT is between the thresholds */ +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; + 1833 .loc 1 1934 15 view .LVU395 + 1834 0014 0020 movs r0, #0 + ARM GAS /tmp/ccMGXY28.s page 85 + + + 1835 .LVL85: +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return VBATLevel; + 1836 .loc 1 1937 3 is_stmt 1 view .LVU396 + 1837 .L171: +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1838 .loc 1 1938 1 is_stmt 0 view .LVU397 + 1839 0016 7047 bx lr + 1840 .L175: + 1841 .align 2 + 1842 .L174: + 1843 0018 00480258 .word 1476544512 + 1844 .cfi_endproc + 1845 .LFE175: + 1847 .section .text.HAL_PWREx_ConfigAVD,"ax",%progbits + 1848 .align 1 + 1849 .global HAL_PWREx_ConfigAVD + 1850 .syntax unified + 1851 .thumb + 1852 .thumb_func + 1853 .fpu fpv5-d16 + 1855 HAL_PWREx_ConfigAVD: + 1856 .LVL86: + 1857 .LFB176: +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CSR1_MMCVDO) +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Get the VDDMMC voltage level. +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval The VDDMMC voltage level. +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWREx_MMC_VoltageLevel mmc_voltage; +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check voltage detector output on VDDMMC value */ +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U) +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2; +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2; +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** return mmc_voltage; +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CSR1_MMCVDO) */ +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Configure the event mode and the voltage threshold detected by the +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * Analog Voltage Detector (AVD). +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the configuration information for the AVD. +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * more details about the voltage threshold corresponding to each +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * detection level. + ARM GAS /tmp/ccMGXY28.s page 86 + + +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note For dual core devices, please ensure to configure the EXTI lines for +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * the different Cortex-Mx through PWR_Exported_Macro provided by this +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * driver. All combination are allowed: wake up only Cortex-M7, wake up +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1858 .loc 1 1978 1 is_stmt 1 view -0 + 1859 .cfi_startproc + 1860 @ args = 0, pretend = 0, frame = 0 + 1861 @ frame_needed = 0, uses_anonymous_args = 0 + 1862 @ link register save eliminated. +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check the parameters */ +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); + 1863 .loc 1 1980 3 view .LVU399 +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); + 1864 .loc 1 1981 3 view .LVU400 +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Set the ALS[18:17] bits according to AVDLevel value */ +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); + 1865 .loc 1 1984 3 view .LVU401 + 1866 0000 244A ldr r2, .L181 + 1867 0002 1368 ldr r3, [r2] + 1868 0004 23F4C023 bic r3, r3, #393216 + 1869 0008 0168 ldr r1, [r0] + 1870 000a 0B43 orrs r3, r3, r1 + 1871 000c 1360 str r3, [r2] +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear any previous config */ +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if !defined (DUAL_CORE) +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); + 1872 .loc 1 1988 3 view .LVU402 + 1873 000e 4FF0B043 mov r3, #1476395008 + 1874 0012 D3F88420 ldr r2, [r3, #132] + 1875 0016 22F48032 bic r2, r2, #65536 + 1876 001a C3F88420 str r2, [r3, #132] +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_IT (); + 1877 .loc 1 1989 3 view .LVU403 + 1878 001e D3F88020 ldr r2, [r3, #128] + 1879 0022 22F48032 bic r2, r2, #65536 + 1880 0026 C3F88020 str r2, [r3, #128] +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !defined (DUAL_CORE) */ +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); + 1881 .loc 1 1992 3 view .LVU404 + 1882 002a 1A68 ldr r2, [r3] + 1883 002c 22F48032 bic r2, r2, #65536 + 1884 0030 1A60 str r2, [r3] +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); + 1885 .loc 1 1993 3 view .LVU405 + 1886 0032 5A68 ldr r2, [r3, #4] + 1887 0034 22F48032 bic r2, r2, #65536 + 1888 0038 5A60 str r2, [r3, #4] +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if !defined (DUAL_CORE) +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Configure the interrupt mode */ + ARM GAS /tmp/ccMGXY28.s page 87 + + +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) + 1889 .loc 1 1997 3 view .LVU406 + 1890 .loc 1 1997 18 is_stmt 0 view .LVU407 + 1891 003a 4368 ldr r3, [r0, #4] + 1892 .loc 1 1997 6 view .LVU408 + 1893 003c 13F4803F tst r3, #65536 + 1894 0040 07D0 beq .L177 +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_IT (); + 1895 .loc 1 1999 5 is_stmt 1 view .LVU409 + 1896 0042 4FF0B042 mov r2, #1476395008 + 1897 0046 D2F88030 ldr r3, [r2, #128] + 1898 004a 43F48033 orr r3, r3, #65536 + 1899 004e C2F88030 str r3, [r2, #128] + 1900 .L177: +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Configure the event mode */ +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) + 1901 .loc 1 2003 3 view .LVU410 + 1902 .loc 1 2003 18 is_stmt 0 view .LVU411 + 1903 0052 4368 ldr r3, [r0, #4] + 1904 .loc 1 2003 6 view .LVU412 + 1905 0054 13F4003F tst r3, #131072 + 1906 0058 07D0 beq .L178 +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); + 1907 .loc 1 2005 5 is_stmt 1 view .LVU413 + 1908 005a 4FF0B042 mov r2, #1476395008 + 1909 005e D2F88430 ldr r3, [r2, #132] + 1910 0062 43F48033 orr r3, r3, #65536 + 1911 0066 C2F88430 str r3, [r2, #132] + 1912 .L178: +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !defined (DUAL_CORE) */ +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Rising edge configuration */ +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) + 1913 .loc 1 2010 3 view .LVU414 + 1914 .loc 1 2010 18 is_stmt 0 view .LVU415 + 1915 006a 4368 ldr r3, [r0, #4] + 1916 .loc 1 2010 6 view .LVU416 + 1917 006c 13F0010F tst r3, #1 + 1918 0070 05D0 beq .L179 +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); + 1919 .loc 1 2012 5 is_stmt 1 view .LVU417 + 1920 0072 4FF0B042 mov r2, #1476395008 + 1921 0076 1368 ldr r3, [r2] + 1922 0078 43F48033 orr r3, r3, #65536 + 1923 007c 1360 str r3, [r2] + 1924 .L179: +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Falling edge configuration */ +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) + 1925 .loc 1 2016 3 view .LVU418 + ARM GAS /tmp/ccMGXY28.s page 88 + + + 1926 .loc 1 2016 18 is_stmt 0 view .LVU419 + 1927 007e 4368 ldr r3, [r0, #4] + 1928 .loc 1 2016 6 view .LVU420 + 1929 0080 13F0020F tst r3, #2 + 1930 0084 05D0 beq .L176 +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); + 1931 .loc 1 2018 5 is_stmt 1 view .LVU421 + 1932 0086 4FF0B042 mov r2, #1476395008 + 1933 008a 5368 ldr r3, [r2, #4] + 1934 008c 43F48033 orr r3, r3, #65536 + 1935 0090 5360 str r3, [r2, #4] + 1936 .L176: +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1937 .loc 1 2020 1 is_stmt 0 view .LVU422 + 1938 0092 7047 bx lr + 1939 .L182: + 1940 .align 2 + 1941 .L181: + 1942 0094 00480258 .word 1476544512 + 1943 .cfi_endproc + 1944 .LFE176: + 1946 .section .text.HAL_PWREx_EnableAVD,"ax",%progbits + 1947 .align 1 + 1948 .global HAL_PWREx_EnableAVD + 1949 .syntax unified + 1950 .thumb + 1951 .thumb_func + 1952 .fpu fpv5-d16 + 1954 HAL_PWREx_EnableAVD: + 1955 .LFB177: +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Enable the Analog Voltage Detector (AVD). +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableAVD (void) +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1956 .loc 1 2027 1 is_stmt 1 view -0 + 1957 .cfi_startproc + 1958 @ args = 0, pretend = 0, frame = 0 + 1959 @ frame_needed = 0, uses_anonymous_args = 0 + 1960 @ link register save eliminated. +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Enable the Analog Voltage Detector */ +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** SET_BIT (PWR->CR1, PWR_CR1_AVDEN); + 1961 .loc 1 2029 3 view .LVU424 + 1962 0000 024A ldr r2, .L184 + 1963 0002 1368 ldr r3, [r2] + 1964 0004 43F48033 orr r3, r3, #65536 + 1965 0008 1360 str r3, [r2] +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1966 .loc 1 2030 1 is_stmt 0 view .LVU425 + 1967 000a 7047 bx lr + 1968 .L185: + 1969 .align 2 + 1970 .L184: + ARM GAS /tmp/ccMGXY28.s page 89 + + + 1971 000c 00480258 .word 1476544512 + 1972 .cfi_endproc + 1973 .LFE177: + 1975 .section .text.HAL_PWREx_DisableAVD,"ax",%progbits + 1976 .align 1 + 1977 .global HAL_PWREx_DisableAVD + 1978 .syntax unified + 1979 .thumb + 1980 .thumb_func + 1981 .fpu fpv5-d16 + 1983 HAL_PWREx_DisableAVD: + 1984 .LFB178: +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief Disable the Analog Voltage Detector(AVD). +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableAVD (void) +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 1985 .loc 1 2037 1 is_stmt 1 view -0 + 1986 .cfi_startproc + 1987 @ args = 0, pretend = 0, frame = 0 + 1988 @ frame_needed = 0, uses_anonymous_args = 0 + 1989 @ link register save eliminated. +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Disable the Analog Voltage Detector */ +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN); + 1990 .loc 1 2039 3 view .LVU427 + 1991 0000 024A ldr r2, .L187 + 1992 0002 1368 ldr r3, [r2] + 1993 0004 23F48033 bic r3, r3, #65536 + 1994 0008 1360 str r3, [r2] +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 1995 .loc 1 2040 1 is_stmt 0 view .LVU428 + 1996 000a 7047 bx lr + 1997 .L188: + 1998 .align 2 + 1999 .L187: + 2000 000c 00480258 .word 1476544512 + 2001 .cfi_endproc + 2002 .LFE178: + 2004 .section .text.HAL_PWREx_AVDCallback,"ax",%progbits + 2005 .align 1 + 2006 .weak HAL_PWREx_AVDCallback + 2007 .syntax unified + 2008 .thumb + 2009 .thumb_func + 2010 .fpu fpv5-d16 + 2012 HAL_PWREx_AVDCallback: + 2013 .LFB180: +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD/AVD interrupt request. +2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_AVD_IRQHandler(). +2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_PVD_AVD_IRQHandler (void) +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccMGXY28.s page 90 + + +2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the Programmable Voltage Detector is enabled (PVD) */ +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U) +2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR D1/CD EXTI flag */ +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) +2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */ +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback (); +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D1/CD pending bit */ +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR EXTI D2 flag */ +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) +2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */ +2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback (); +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D2 pending bit */ +2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTID2_CLEAR_FLAG(); +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the Analog Voltage Detector is enabled (AVD) */ +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U) +2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (HAL_GetCurrentCPUID () == CM7_CPUID) +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR EXTI D1/CD flag */ +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U) +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR AVD interrupt user callback */ +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_AVDCallback (); +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D1/CD pending bit */ +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTI_CLEAR_FLAG (); +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE) +2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** else +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check PWR EXTI D2 flag */ +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U) +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { +2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* PWR AVD interrupt user callback */ + ARM GAS /tmp/ccMGXY28.s page 91 + + +2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_PWREx_AVDCallback (); +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Clear PWR EXTI D2 pending bit */ +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __HAL_PWR_AVD_EXTID2_CLEAR_FLAG (); +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */ +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @brief PWR AVD interrupt callback. +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** * @retval None. +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_AVDCallback (void) +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2014 .loc 1 2121 1 is_stmt 1 view -0 + 2015 .cfi_startproc + 2016 @ args = 0, pretend = 0, frame = 0 + 2017 @ frame_needed = 0, uses_anonymous_args = 0 + 2018 @ link register save eliminated. +2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** the HAL_PWR_AVDCallback can be implemented in the user file +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** */ +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 2019 .loc 1 2125 1 view .LVU430 + 2020 0000 7047 bx lr + 2021 .cfi_endproc + 2022 .LFE180: + 2024 .section .text.HAL_PWREx_PVD_AVD_IRQHandler,"ax",%progbits + 2025 .align 1 + 2026 .global HAL_PWREx_PVD_AVD_IRQHandler + 2027 .syntax unified + 2028 .thumb + 2029 .thumb_func + 2030 .fpu fpv5-d16 + 2032 HAL_PWREx_PVD_AVD_IRQHandler: + 2033 .LFB179: +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Check if the Programmable Voltage Detector is enabled (PVD) */ + 2034 .loc 1 2048 1 view -0 + 2035 .cfi_startproc + 2036 @ args = 0, pretend = 0, frame = 0 + 2037 @ frame_needed = 0, uses_anonymous_args = 0 + 2038 0000 08B5 push {r3, lr} + 2039 .LCFI13: + 2040 .cfi_def_cfa_offset 8 + 2041 .cfi_offset 3, -8 + 2042 .cfi_offset 14, -4 +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2043 .loc 1 2050 3 view .LVU432 +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2044 .loc 1 2050 7 is_stmt 0 view .LVU433 + 2045 0002 174B ldr r3, .L196 + 2046 0004 1B68 ldr r3, [r3] +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2047 .loc 1 2050 6 view .LVU434 + 2048 0006 13F0100F tst r3, #16 + ARM GAS /tmp/ccMGXY28.s page 92 + + + 2049 000a 06D0 beq .L191 +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2050 .loc 1 2057 7 is_stmt 1 view .LVU435 +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2051 .loc 1 2057 11 is_stmt 0 view .LVU436 + 2052 000c 4FF0B043 mov r3, #1476395008 + 2053 0010 D3F88830 ldr r3, [r3, #136] +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2054 .loc 1 2057 10 view .LVU437 + 2055 0014 13F4803F tst r3, #65536 + 2056 0018 0CD1 bne .L194 + 2057 .L191: +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2058 .loc 1 2083 3 is_stmt 1 view .LVU438 +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2059 .loc 1 2083 7 is_stmt 0 view .LVU439 + 2060 001a 114B ldr r3, .L196 + 2061 001c 1B68 ldr r3, [r3] +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2062 .loc 1 2083 6 view .LVU440 + 2063 001e 13F4803F tst r3, #65536 + 2064 0022 06D0 beq .L190 +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2065 .loc 1 2090 7 is_stmt 1 view .LVU441 +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2066 .loc 1 2090 11 is_stmt 0 view .LVU442 + 2067 0024 4FF0B043 mov r3, #1476395008 + 2068 0028 D3F88830 ldr r3, [r3, #136] +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** { + 2069 .loc 1 2090 10 view .LVU443 + 2070 002c 13F4803F tst r3, #65536 + 2071 0030 0BD1 bne .L195 + 2072 .L190: +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 2073 .loc 1 2114 1 view .LVU444 + 2074 0032 08BD pop {r3, pc} + 2075 .L194: +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 2076 .loc 1 2060 9 is_stmt 1 view .LVU445 + 2077 0034 FFF7FEFF bl HAL_PWR_PVDCallback + 2078 .LVL87: +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 2079 .loc 1 2063 9 view .LVU446 + 2080 0038 4FF0B042 mov r2, #1476395008 + 2081 003c D2F88830 ldr r3, [r2, #136] + 2082 0040 43F48033 orr r3, r3, #65536 + 2083 0044 C2F88830 str r3, [r2, #136] + 2084 0048 E7E7 b .L191 + 2085 .L195: +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 2086 .loc 1 2093 9 view .LVU447 + 2087 004a FFF7FEFF bl HAL_PWREx_AVDCallback + 2088 .LVL88: +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** } + 2089 .loc 1 2096 9 view .LVU448 + 2090 004e 4FF0B042 mov r2, #1476395008 + 2091 0052 D2F88830 ldr r3, [r2, #136] + ARM GAS /tmp/ccMGXY28.s page 93 + + + 2092 0056 43F48033 orr r3, r3, #65536 + 2093 005a C2F88830 str r3, [r2, #136] +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** + 2094 .loc 1 2114 1 is_stmt 0 view .LVU449 + 2095 005e E8E7 b .L190 + 2096 .L197: + 2097 .align 2 + 2098 .L196: + 2099 0060 00480258 .word 1476544512 + 2100 .cfi_endproc + 2101 .LFE179: + 2103 .text + 2104 .Letext0: + 2105 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2106 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2107 .file 5 "Drivers/CMSIS/Include/core_cm7.h" + 2108 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 2109 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 2110 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h" + 2111 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h" + 2112 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccMGXY28.s page 94 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_pwr_ex.c + /tmp/ccMGXY28.s:17 .text.HAL_PWREx_ConfigSupply:0000000000000000 $t + /tmp/ccMGXY28.s:25 .text.HAL_PWREx_ConfigSupply:0000000000000000 HAL_PWREx_ConfigSupply + /tmp/ccMGXY28.s:119 .text.HAL_PWREx_ConfigSupply:0000000000000050 $d + /tmp/ccMGXY28.s:124 .text.HAL_PWREx_GetSupplyConfig:0000000000000000 $t + /tmp/ccMGXY28.s:131 .text.HAL_PWREx_GetSupplyConfig:0000000000000000 HAL_PWREx_GetSupplyConfig + /tmp/ccMGXY28.s:148 .text.HAL_PWREx_GetSupplyConfig:000000000000000c $d + /tmp/ccMGXY28.s:153 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 $t + /tmp/ccMGXY28.s:160 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 HAL_PWREx_ControlVoltageScaling + /tmp/ccMGXY28.s:353 .text.HAL_PWREx_ControlVoltageScaling:00000000000000cc $d + /tmp/ccMGXY28.s:359 .text.HAL_PWREx_GetVoltageRange:0000000000000000 $t + /tmp/ccMGXY28.s:366 .text.HAL_PWREx_GetVoltageRange:0000000000000000 HAL_PWREx_GetVoltageRange + /tmp/ccMGXY28.s:383 .text.HAL_PWREx_GetVoltageRange:000000000000000c $d + /tmp/ccMGXY28.s:388 .text.HAL_PWREx_ControlStopModeVoltageScaling:0000000000000000 $t + /tmp/ccMGXY28.s:395 .text.HAL_PWREx_ControlStopModeVoltageScaling:0000000000000000 HAL_PWREx_ControlStopModeVoltageScaling + /tmp/ccMGXY28.s:419 .text.HAL_PWREx_ControlStopModeVoltageScaling:0000000000000010 $d + /tmp/ccMGXY28.s:424 .text.HAL_PWREx_GetStopModeVoltageRange:0000000000000000 $t + /tmp/ccMGXY28.s:431 .text.HAL_PWREx_GetStopModeVoltageRange:0000000000000000 HAL_PWREx_GetStopModeVoltageRange + /tmp/ccMGXY28.s:448 .text.HAL_PWREx_GetStopModeVoltageRange:000000000000000c $d + /tmp/ccMGXY28.s:453 .text.HAL_PWREx_EnterSTOPMode:0000000000000000 $t + /tmp/ccMGXY28.s:460 .text.HAL_PWREx_EnterSTOPMode:0000000000000000 HAL_PWREx_EnterSTOPMode + /tmp/ccMGXY28.s:589 .text.HAL_PWREx_EnterSTOPMode:0000000000000060 $d + /tmp/ccMGXY28.s:595 .text.HAL_PWREx_ClearPendingEvent:0000000000000000 $t + /tmp/ccMGXY28.s:602 .text.HAL_PWREx_ClearPendingEvent:0000000000000000 HAL_PWREx_ClearPendingEvent + /tmp/ccMGXY28.s:622 .text.HAL_PWREx_EnterSTANDBYMode:0000000000000000 $t + /tmp/ccMGXY28.s:629 .text.HAL_PWREx_EnterSTANDBYMode:0000000000000000 HAL_PWREx_EnterSTANDBYMode + /tmp/ccMGXY28.s:681 .text.HAL_PWREx_EnterSTANDBYMode:0000000000000038 $d + /tmp/ccMGXY28.s:687 .text.HAL_PWREx_ConfigD3Domain:0000000000000000 $t + /tmp/ccMGXY28.s:694 .text.HAL_PWREx_ConfigD3Domain:0000000000000000 HAL_PWREx_ConfigD3Domain + /tmp/ccMGXY28.s:714 .text.HAL_PWREx_ConfigD3Domain:0000000000000010 $d + /tmp/ccMGXY28.s:719 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 $t + /tmp/ccMGXY28.s:726 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 HAL_PWREx_EnableFlashPowerDown + /tmp/ccMGXY28.s:743 .text.HAL_PWREx_EnableFlashPowerDown:000000000000000c $d + /tmp/ccMGXY28.s:748 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 $t + /tmp/ccMGXY28.s:755 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 HAL_PWREx_DisableFlashPowerDown + /tmp/ccMGXY28.s:772 .text.HAL_PWREx_DisableFlashPowerDown:000000000000000c $d + /tmp/ccMGXY28.s:777 .text.HAL_PWREx_EnableWakeUpPin:0000000000000000 $t + /tmp/ccMGXY28.s:784 .text.HAL_PWREx_EnableWakeUpPin:0000000000000000 HAL_PWREx_EnableWakeUpPin + /tmp/ccMGXY28.s:950 .text.HAL_PWREx_EnableWakeUpPin:000000000000008c $d + /tmp/ccMGXY28.s:955 .text.HAL_PWREx_DisableWakeUpPin:0000000000000000 $t + /tmp/ccMGXY28.s:962 .text.HAL_PWREx_DisableWakeUpPin:0000000000000000 HAL_PWREx_DisableWakeUpPin + /tmp/ccMGXY28.s:981 .text.HAL_PWREx_DisableWakeUpPin:000000000000000c $d + /tmp/ccMGXY28.s:986 .text.HAL_PWREx_GetWakeupFlag:0000000000000000 $t + /tmp/ccMGXY28.s:993 .text.HAL_PWREx_GetWakeupFlag:0000000000000000 HAL_PWREx_GetWakeupFlag + /tmp/ccMGXY28.s:1014 .text.HAL_PWREx_GetWakeupFlag:0000000000000008 $d + /tmp/ccMGXY28.s:1019 .text.HAL_PWREx_ClearWakeupFlag:0000000000000000 $t + /tmp/ccMGXY28.s:1026 .text.HAL_PWREx_ClearWakeupFlag:0000000000000000 HAL_PWREx_ClearWakeupFlag + /tmp/ccMGXY28.s:1061 .text.HAL_PWREx_ClearWakeupFlag:0000000000000018 $d + /tmp/ccMGXY28.s:1066 .text.HAL_PWREx_WKUP1_Callback:0000000000000000 $t + /tmp/ccMGXY28.s:1073 .text.HAL_PWREx_WKUP1_Callback:0000000000000000 HAL_PWREx_WKUP1_Callback + /tmp/ccMGXY28.s:1086 .text.HAL_PWREx_WKUP2_Callback:0000000000000000 $t + /tmp/ccMGXY28.s:1093 .text.HAL_PWREx_WKUP2_Callback:0000000000000000 HAL_PWREx_WKUP2_Callback + /tmp/ccMGXY28.s:1106 .text.HAL_PWREx_WKUP3_Callback:0000000000000000 $t + /tmp/ccMGXY28.s:1113 .text.HAL_PWREx_WKUP3_Callback:0000000000000000 HAL_PWREx_WKUP3_Callback + /tmp/ccMGXY28.s:1126 .text.HAL_PWREx_WKUP4_Callback:0000000000000000 $t + /tmp/ccMGXY28.s:1133 .text.HAL_PWREx_WKUP4_Callback:0000000000000000 HAL_PWREx_WKUP4_Callback + ARM GAS /tmp/ccMGXY28.s page 95 + + + /tmp/ccMGXY28.s:1146 .text.HAL_PWREx_WKUP5_Callback:0000000000000000 $t + /tmp/ccMGXY28.s:1153 .text.HAL_PWREx_WKUP5_Callback:0000000000000000 HAL_PWREx_WKUP5_Callback + /tmp/ccMGXY28.s:1166 .text.HAL_PWREx_WKUP6_Callback:0000000000000000 $t + /tmp/ccMGXY28.s:1173 .text.HAL_PWREx_WKUP6_Callback:0000000000000000 HAL_PWREx_WKUP6_Callback + /tmp/ccMGXY28.s:1186 .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:0000000000000000 $t + /tmp/ccMGXY28.s:1193 .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:0000000000000000 HAL_PWREx_WAKEUP_PIN_IRQHandler + /tmp/ccMGXY28.s:1304 .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:0000000000000094 $d + /tmp/ccMGXY28.s:1309 .text.HAL_PWREx_EnableBkUpReg:0000000000000000 $t + /tmp/ccMGXY28.s:1316 .text.HAL_PWREx_EnableBkUpReg:0000000000000000 HAL_PWREx_EnableBkUpReg + /tmp/ccMGXY28.s:1371 .text.HAL_PWREx_EnableBkUpReg:0000000000000030 $d + /tmp/ccMGXY28.s:1376 .text.HAL_PWREx_DisableBkUpReg:0000000000000000 $t + /tmp/ccMGXY28.s:1383 .text.HAL_PWREx_DisableBkUpReg:0000000000000000 HAL_PWREx_DisableBkUpReg + /tmp/ccMGXY28.s:1438 .text.HAL_PWREx_DisableBkUpReg:0000000000000030 $d + /tmp/ccMGXY28.s:1443 .text.HAL_PWREx_EnableUSBReg:0000000000000000 $t + /tmp/ccMGXY28.s:1450 .text.HAL_PWREx_EnableUSBReg:0000000000000000 HAL_PWREx_EnableUSBReg + /tmp/ccMGXY28.s:1505 .text.HAL_PWREx_EnableUSBReg:0000000000000030 $d + /tmp/ccMGXY28.s:1510 .text.HAL_PWREx_DisableUSBReg:0000000000000000 $t + /tmp/ccMGXY28.s:1517 .text.HAL_PWREx_DisableUSBReg:0000000000000000 HAL_PWREx_DisableUSBReg + /tmp/ccMGXY28.s:1572 .text.HAL_PWREx_DisableUSBReg:0000000000000030 $d + /tmp/ccMGXY28.s:1577 .text.HAL_PWREx_EnableUSBVoltageDetector:0000000000000000 $t + /tmp/ccMGXY28.s:1584 .text.HAL_PWREx_EnableUSBVoltageDetector:0000000000000000 HAL_PWREx_EnableUSBVoltageDetector + /tmp/ccMGXY28.s:1601 .text.HAL_PWREx_EnableUSBVoltageDetector:000000000000000c $d + /tmp/ccMGXY28.s:1606 .text.HAL_PWREx_DisableUSBVoltageDetector:0000000000000000 $t + /tmp/ccMGXY28.s:1613 .text.HAL_PWREx_DisableUSBVoltageDetector:0000000000000000 HAL_PWREx_DisableUSBVoltageDetector + /tmp/ccMGXY28.s:1630 .text.HAL_PWREx_DisableUSBVoltageDetector:000000000000000c $d + /tmp/ccMGXY28.s:1635 .text.HAL_PWREx_EnableBatteryCharging:0000000000000000 $t + /tmp/ccMGXY28.s:1642 .text.HAL_PWREx_EnableBatteryCharging:0000000000000000 HAL_PWREx_EnableBatteryCharging + /tmp/ccMGXY28.s:1666 .text.HAL_PWREx_EnableBatteryCharging:0000000000000018 $d + /tmp/ccMGXY28.s:1671 .text.HAL_PWREx_DisableBatteryCharging:0000000000000000 $t + /tmp/ccMGXY28.s:1678 .text.HAL_PWREx_DisableBatteryCharging:0000000000000000 HAL_PWREx_DisableBatteryCharging + /tmp/ccMGXY28.s:1695 .text.HAL_PWREx_DisableBatteryCharging:000000000000000c $d + /tmp/ccMGXY28.s:1700 .text.HAL_PWREx_EnableMonitoring:0000000000000000 $t + /tmp/ccMGXY28.s:1707 .text.HAL_PWREx_EnableMonitoring:0000000000000000 HAL_PWREx_EnableMonitoring + /tmp/ccMGXY28.s:1724 .text.HAL_PWREx_EnableMonitoring:000000000000000c $d + /tmp/ccMGXY28.s:1729 .text.HAL_PWREx_DisableMonitoring:0000000000000000 $t + /tmp/ccMGXY28.s:1736 .text.HAL_PWREx_DisableMonitoring:0000000000000000 HAL_PWREx_DisableMonitoring + /tmp/ccMGXY28.s:1753 .text.HAL_PWREx_DisableMonitoring:000000000000000c $d + /tmp/ccMGXY28.s:1758 .text.HAL_PWREx_GetTemperatureLevel:0000000000000000 $t + /tmp/ccMGXY28.s:1765 .text.HAL_PWREx_GetTemperatureLevel:0000000000000000 HAL_PWREx_GetTemperatureLevel + /tmp/ccMGXY28.s:1798 .text.HAL_PWREx_GetTemperatureLevel:0000000000000018 $d + /tmp/ccMGXY28.s:1803 .text.HAL_PWREx_GetVBATLevel:0000000000000000 $t + /tmp/ccMGXY28.s:1810 .text.HAL_PWREx_GetVBATLevel:0000000000000000 HAL_PWREx_GetVBATLevel + /tmp/ccMGXY28.s:1843 .text.HAL_PWREx_GetVBATLevel:0000000000000018 $d + /tmp/ccMGXY28.s:1848 .text.HAL_PWREx_ConfigAVD:0000000000000000 $t + /tmp/ccMGXY28.s:1855 .text.HAL_PWREx_ConfigAVD:0000000000000000 HAL_PWREx_ConfigAVD + /tmp/ccMGXY28.s:1942 .text.HAL_PWREx_ConfigAVD:0000000000000094 $d + /tmp/ccMGXY28.s:1947 .text.HAL_PWREx_EnableAVD:0000000000000000 $t + /tmp/ccMGXY28.s:1954 .text.HAL_PWREx_EnableAVD:0000000000000000 HAL_PWREx_EnableAVD + /tmp/ccMGXY28.s:1971 .text.HAL_PWREx_EnableAVD:000000000000000c $d + /tmp/ccMGXY28.s:1976 .text.HAL_PWREx_DisableAVD:0000000000000000 $t + /tmp/ccMGXY28.s:1983 .text.HAL_PWREx_DisableAVD:0000000000000000 HAL_PWREx_DisableAVD + /tmp/ccMGXY28.s:2000 .text.HAL_PWREx_DisableAVD:000000000000000c $d + /tmp/ccMGXY28.s:2005 .text.HAL_PWREx_AVDCallback:0000000000000000 $t + /tmp/ccMGXY28.s:2012 .text.HAL_PWREx_AVDCallback:0000000000000000 HAL_PWREx_AVDCallback + /tmp/ccMGXY28.s:2025 .text.HAL_PWREx_PVD_AVD_IRQHandler:0000000000000000 $t + /tmp/ccMGXY28.s:2032 .text.HAL_PWREx_PVD_AVD_IRQHandler:0000000000000000 HAL_PWREx_PVD_AVD_IRQHandler + /tmp/ccMGXY28.s:2099 .text.HAL_PWREx_PVD_AVD_IRQHandler:0000000000000060 $d + ARM GAS /tmp/ccMGXY28.s page 96 + + + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_PWR_PVDCallback diff --git a/build/stm32h7xx_hal_pwr_ex.o b/build/stm32h7xx_hal_pwr_ex.o new file mode 100644 index 0000000..dd48df5 Binary files /dev/null and b/build/stm32h7xx_hal_pwr_ex.o differ diff --git a/build/stm32h7xx_hal_qspi.d b/build/stm32h7xx_hal_qspi.d new file mode 100644 index 0000000..5332660 --- /dev/null +++ b/build/stm32h7xx_hal_qspi.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_qspi.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_qspi.lst b/build/stm32h7xx_hal_qspi.lst new file mode 100644 index 0000000..0aa2fdc --- /dev/null +++ b/build/stm32h7xx_hal_qspi.lst @@ -0,0 +1,8503 @@ +ARM GAS /tmp/ccNpZKQO.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_qspi.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.QSPI_DMARxCplt,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 QSPI_DMARxCplt: + 25 .LVL0: + 26 .LFB173: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @file stm32h7xx_hal_qspi.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief QSPI HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * functionalities of the QuadSPI interface (QSPI). + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + Indirect functional mode management + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + Memory-mapped functional mode management + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + Auto-polling functional mode management + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + Interrupts and flags management + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + MDMA channel configuration for indirect functional mode + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + Errors management and abort functionality + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** @verbatim + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** =============================================================================== + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ##### How to use this driver ##### + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** =============================================================================== + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Initialization *** + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ====================== + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) As prerequisite, fill in the HAL_QSPI_MspInit() : + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_ + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) If interrupt mode is used, enable and configure QuadSPI global + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + ARM GAS /tmp/ccNpZKQO.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(), + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) Configure the flash size, the clock prescaler, the fifo threshold, the + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function. + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Indirect functional mode *** + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ================================ + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** functions : + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Instruction phase : the mode used and if present the instruction opcode. + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Address phase : the mode used and if present the size and the address value. + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Alternate-bytes phase : the mode used and if present the size and the alternate + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** bytes values. + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Data phase : the mode used and if present the number of bytes. + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if activated. + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) If no data is required for the command, it is sent directly to the memory : + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In polling mode, the output of the function is done when the transfer is complete. + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is com + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_Transmit_IT() after the command configuration : + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In polling mode, the output of the function is done when the transfer is complete. + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo thre + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In DMA mode,HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_Receive_IT() after the command configuration : + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In polling mode, the output of the function is done when the transfer is complete. + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo thre + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Auto-polling functional mode *** + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ==================================== + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) Configure the command sequence and the auto-polling functional mode using the + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions : + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Instruction phase : the mode used and if present the instruction opcode. + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Address phase : the mode used and if present the size and the address value. + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Alternate-bytes phase : the mode used and if present the size and the alternate + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** bytes values. + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Data phase : the mode used. + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if activated. + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND) + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the polling interval and the automatic stop activation. + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) After the configuration : + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In polling mode, the output of the function is done when the status match is reached. + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** automatic stop is activated to avoid an infinite loop. + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status + ARM GAS /tmp/ccNpZKQO.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** MDMA functional mode *** + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ==================================== + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() fu + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) MDMA settings for write operation : + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The DestinationInc should be MDMA_DEST_INC_DISABLE + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** aligned with @ref MDMA_Source_increment_mode . + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) MDMA settings for read operation : + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The SourceInc should be MDMA_SRC_INC_DISABLE + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except th + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_ + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** aligned with @ref MDMA_Destination_increment_mode. + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoT + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#)In case of wrong MDMA setting + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) For write operation : + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by t + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) For read operation : + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_Q + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Memory-mapped functional mode *** + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ===================================== + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) Configure the command sequence and the memory-mapped functional mode using the + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_MemoryMapped() functions : + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Instruction phase : the mode used and if present the instruction opcode. + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Address phase : the mode used and the size. + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Alternate-bytes phase : the mode used and if present the size and the alternate + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** bytes values. + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Data phase : the mode used. + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if activated. + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) The timeout activation and the timeout period. + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Errors management and abort functionality *** + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ================================================= + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_GetError() function gives the error raised during the last operation. + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** flushes the fifo : + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In polling mode, the output of the function is done when the transfer + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** complete bit is set and the busy bit cleared. + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the transfer complete bit is set. + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Control functions *** + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ========================= + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. + ARM GAS /tmp/ccNpZKQO.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Callback registration *** + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ============================================= + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** allows the user to configure dynamically the driver callbacks. + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** it allows to register following callbacks: + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) ErrorCallback : callback when error occurs. + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) AbortCpltCallback : callback when abort is completed. + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) FifoThresholdCallback : callback when the fifo threshold is reached. + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) CmdCpltCallback : callback when a command without data is completed. + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) RxCpltCallback : callback when a reception transfer is completed. + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) TxCpltCallback : callback when a transmission transfer is completed. + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) StatusMatchCallback : callback when a status match occurs. + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) TimeOutCallback : callback when the timeout perioed expires. + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) MspInitCallback : QSPI MspInit. + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) MspDeInitCallback : QSPI MspDeInit. + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** and a pointer to the user callback function. + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** weak (surcharged) function. It allows to reset following callbacks: + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) ErrorCallback : callback when error occurs. + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) AbortCpltCallback : callback when abort is completed. + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) FifoThresholdCallback : callback when the fifo threshold is reached. + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) CmdCpltCallback : callback when a command without data is completed. + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) RxCpltCallback : callback when a reception transfer is completed. + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) TxCpltCallback : callback when a transmission transfer is completed. + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) StatusMatchCallback : callback when a status match occurs. + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) TimeOutCallback : callback when the timeout perioed expires. + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) MspInitCallback : QSPI MspInit. + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) MspDeInitCallback : QSPI MspDeInit. + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** This function) takes as parameters the HAL peripheral handle and the Callback ID. + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** all callbacks are reset to the corresponding legacy weak (surcharged) functions. + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** Exception done for MspInit and MspDeInit callbacks that are respectively + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** Callbacks can be registered/unregistered in READY state only. + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** during the Init/DeInit. + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** In that case first register the MspInit/MspDeInit user callbacks + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** or @ref HAL_QSPI_Init function. + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or + ARM GAS /tmp/ccNpZKQO.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** not defined, the callback registering feature is not available + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** and weak (surcharged) callbacks are used. + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *** Workarounds linked to Silicon Limitation *** + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ==================================================== + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (#) Workarounds Implemented inside HAL Driver + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (++) Extra data written in the FIFO at the end of a read transfer + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** @endverbatim + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ****************************************************************************** + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @attention + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *

© Copyright (c) 2017 STMicroelectronics. + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * All rights reserved.

+ 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * This software component is licensed by ST under BSD 3-Clause license, + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * the "License"; You may not use this file except in compliance with the + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * License. You may obtain a copy of the License at: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * opensource.org/licenses/BSD-3-Clause + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ****************************************************************************** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Includes ------------------------------------------------------------------*/ + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #include "stm32h7xx_hal.h" + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if defined(QUADSPI) + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @addtogroup STM32H7xx_HAL_Driver + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @{ + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @defgroup QSPI QSPI + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief QSPI HAL module driver + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @{ + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #ifdef HAL_QSPI_MODULE_ENABLED + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Private typedef -----------------------------------------------------------*/ + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Private define ------------------------------------------------------------*/ + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @defgroup QSPI_Private_Constants QSPI Private Constants + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @{ + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!Instance)); + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_RESET) + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->MspInitCallback == NULL) + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspInitCallback = HAL_QSPI_MspInit; + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Init the low level hardware */ + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspInitCallback(hqspi); + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Init the low level hardware : GPIO, CLOCK */ + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_MspInit(hqspi); + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure the default timeout for the QSPI memory access */ + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI FIFO Threshold */ + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait till BUSY flag reset */ + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(status == HAL_OK) + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI Clock Prescaler and Sample Shift */ + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | Q + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + ARM GAS /tmp/ccNpZKQO.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI Flash Size, CS High Time and Clock Mode */ + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI peripheral */ + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE(hqspi); + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set QSPI error code to none */ + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Initialize the QSPI state */ + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief De-Initialize the QSPI peripheral. + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the QSPI handle allocation */ + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi == NULL) + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return HAL_ERROR; + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the QSPI Peripheral Clock */ + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE(hqspi); + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->MspDeInitCallback == NULL) + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* DeInit the low level hardware */ + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspDeInitCallback(hqspi); + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_MspDeInit(hqspi); + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set QSPI error code to none */ + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Initialize the QSPI state */ + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_RESET; + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return HAL_OK; + ARM GAS /tmp/ccNpZKQO.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Initialize the QSPI MSP. + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE : This function should not be modified, when the callback is needed, + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_MspInit can be implemented in the user file + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief DeInitialize the QSPI MSP. + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE : This function should not be modified, when the callback is needed, + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_MspDeInit can be implemented in the user file + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @} + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief QSPI Transmit/Receive functions + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** @verbatim + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** =============================================================================== + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ##### IO operation functions ##### + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** =============================================================================== + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** This subsection provides a set of functions allowing to : + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Handle the interrupts. + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Handle the command sequence. + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Transmit data in blocking, interrupt or DMA mode. + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Receive data in blocking, interrupt or DMA mode. + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Manage the auto-polling functional mode. + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Manage the memory-mapped functional mode. + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** @endverbatim + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @{ + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + ARM GAS /tmp/ccNpZKQO.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Handle QSPI interrupt request. + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg; + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t flag = READ_REG(hqspi->Instance->SR); + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t itsource = READ_REG(hqspi->Instance->CR); + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** data_reg = &hqspi->Instance->DR; + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Transmission process */ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->TxXferCount > 0U) + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Fill the FIFO until the threshold is reached */ + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* No more data available for the transfer */ + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the QSPI FIFO Threshold Interrupt */ + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Receiving Process */ + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->RxXferCount > 0U) + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Read the FIFO until the threshold is reached */ + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* All data have been received for the transfer */ + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the QSPI FIFO Threshold Interrupt */ + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Nothing to do */ + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* FIFO Threshold callback */ + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->FifoThresholdCallback(hqspi); + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_FifoThresholdCallback(hqspi); + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* QSPI Transfer Complete interrupt occurred -------------------------------*/ + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Transfer complete callback */ + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the MDMA channel */ + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_MDMA_DISABLE(hqspi->hmdma); + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* TX Complete callback */ + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxCpltCallback(hqspi); + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_TxCpltCallback(hqspi); + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the MDMA channel */ + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_MDMA_DISABLE(hqspi->hmdma); + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** data_reg = &hqspi->Instance->DR; + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->RxXferCount > 0U) + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Read the last data received in the FIFO until it is empty */ + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* All data have been received for the transfer */ + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* RX Complete callback */ + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxCpltCallback(hqspi); + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_RxCpltCallback(hqspi); + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(hqspi->State == HAL_QSPI_STATE_BUSY) + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Command Complete callback */ + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->CmdCpltCallback(hqspi); + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_CmdCpltCallback(hqspi); + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(hqspi->State == HAL_QSPI_STATE_ABORT) + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Reset functional mode configuration to indirect write mode by default */ + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort called by the user */ + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort Complete callback */ + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->AbortCpltCallback(hqspi); + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + ARM GAS /tmp/ccNpZKQO.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_AbortCpltCallback(hqspi); + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort due to an error (eg : MDMA error) */ + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Error callback */ + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback(hqspi); + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_ErrorCallback(hqspi); + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Nothing to do */ + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* QSPI Status Match interrupt occurred ------------------------------------*/ + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check if the automatic poll mode stop is activated */ + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the QSPI Transfer Error and Status Match Interrupts */ + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Status match callback */ + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->StatusMatchCallback(hqspi); + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_StatusMatchCallback(hqspi); + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* QSPI Transfer Error interrupt occurred ----------------------------------*/ + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable all the QSPI Interrupts */ + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set error code */ + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the MDMA channel */ + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set error code to DMA */ + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Error callback */ + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback(hqspi); + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_ErrorCallback(hqspi); + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Error callback */ + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback(hqspi); + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_ErrorCallback(hqspi); + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* QSPI Timeout interrupt occurred -----------------------------------------*/ + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Timeout callback */ + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TimeOutCallback(hqspi); + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_TimeOutCallback(hqspi); + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Nothing to do */ + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Set the command configuration. + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cmd : structure that contains the command configuration information + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Timeout : Timeout duration + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Read or Write Modes + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the parameters */ + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY; + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait till BUSY flag reset */ + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Call the configuration function */ + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->DataMode == QSPI_DATA_NONE) + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* When there is no data phase, the transfer start as soon as the configuration is done + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** so wait until TC flag is set to go back in idle state */ + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Set the command configuration in interrupt mode. + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cmd : structure that contains the command configuration information + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Read or Write Modes + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the parameters */ + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY; + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait till BUSY flag reset */ + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->DataMode == QSPI_DATA_NONE) + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Call the configuration function */ + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->DataMode == QSPI_DATA_NONE) + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* When there is no data phase, the transfer start as soon as the configuration is done + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** so activate TC and TE interrupts */ + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI Transfer Error Interrupt */ + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Transmit an amount of data in blocking mode. + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pData : pointer to data buffer + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Timeout : Timeout duration + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Write Mode + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pData != NULL ) + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure counters and size of the handle */ + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with functional as indirect write */ + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** while(hqspi->TxXferCount > 0U) + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until FT flag is set to send data */ +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); + ARM GAS /tmp/ccNpZKQO.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status != HAL_OK) +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until TC flag is set to go back in idle state */ +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear Transfer Complete bit */ +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Receive an amount of data in blocking mode. +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pData : pointer to data buffer +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Timeout : Timeout duration +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Read Mode +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + ARM GAS /tmp/ccNpZKQO.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pData != NULL ) +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure counters and size of the handle */ +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with functional as indirect read */ +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Start the transfer by re-writing the address in AR register */ +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, addr_reg); +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** while(hqspi->RxXferCount > 0U) +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until FT or TC flag is set to read received data */ +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstar +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status != HAL_OK) +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until TC flag is set to go back in idle state */ +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear Transfer Complete bit */ +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Send an amount of data in non-blocking mode with interrupt. +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pData : pointer to data buffer +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Write Mode +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pData != NULL ) +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure counters and size of the handle */ +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with functional as indirect write */ +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Receive an amount of data in non-blocking mode with interrupt. +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pData : pointer to data buffer +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Read Mode +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pData != NULL ) +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure counters and size of the handle */ +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with functional as indirect read */ +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Start the transfer by re-writing the address in AR register */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, addr_reg); + ARM GAS /tmp/ccNpZKQO.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Send an amount of data in non-blocking mode with DMA. +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pData : pointer to data buffer +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Write Mode +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear the error code */ +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pData != NULL ) +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure counters of the handle */ +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = data_size; +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + ARM GAS /tmp/ccNpZKQO.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure size and pointer of the handle */ +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = hqspi->TxXferCount; +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with functional mode as indirect write */ +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set the QSPI MDMA transfer complete callback */ +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set the MDMA error callback */ +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferErrorCallback = QSPI_DMAError; +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear the MDMA abort callback */ +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferAbortCallback = NULL; +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destina +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update MDMA configuration with the correct SourceInc field for Write operation */ +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_I +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_I +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_I +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* in case of incorrect source data size */ +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transmit MDMA */ +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi- +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transfer error Interrupt */ +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + ARM GAS /tmp/ccNpZKQO.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Receive an amount of data in non-blocking mode with DMA. +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pData : pointer to data buffer. +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Indirect Read Mode +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear the error code */ +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pData != NULL ) +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure counters of the handle */ +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount = data_size; +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure size and pointer of the handle */ + ARM GAS /tmp/ccNpZKQO.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = hqspi->RxXferCount; +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set the QSPI MDMA transfer complete callback */ +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Set the MDMA error callback */ +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferErrorCallback = QSPI_DMAError; +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear the MDMA abort callback */ +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferAbortCallback = NULL; +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Incremen +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_D +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update MDMA configuration with the correct DestinationInc field for read operation */ +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE) +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_IN +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD) +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_IN +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD) +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_IN +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* in case of incorrect destination data size */ +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with functional as indirect read */ +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Start the transfer by re-writing the address in AR register */ +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, addr_reg); +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the MDMA */ +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi- +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transfer error Interrupt */ +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + ARM GAS /tmp/ccNpZKQO.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cmd : structure that contains the command configuration information. +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cfg : structure that contains the polling configuration information. +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Timeout : Timeout duration +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Automatic Polling Mode +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the parameters */ +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INTERVAL(cfg->Interval)); +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait till BUSY flag reset */ +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: PSMAR register with the status match value */ +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: PSMKR register with the status mask value */ +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: PIR register with the interval value */ +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->PIR, cfg->Interval); +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CR register with Match mode and Automatic stop enabled +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (otherwise there will be an infinite loop in blocking mode) */ +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Call the configuration function */ +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->NbData = cfg->StatusBytesSize; +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until SM flag is set to go back in idle state */ +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cmd : structure that contains the command configuration information. +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cfg : structure that contains the polling configuration information. +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Automatic Polling Mode +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the parameters */ +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INTERVAL(cfg->Interval)); +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ + ARM GAS /tmp/ccNpZKQO.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait till BUSY flag reset */ +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: PSMAR register with the status match value */ +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: PSMKR register with the status mask value */ +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: PIR register with the interval value */ +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->PIR, cfg->Interval); +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CR register with Match mode and Automatic stop mode */ +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (cfg->MatchMode | cfg->AutomaticStop)); +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Call the configuration function */ +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->NbData = cfg->StatusBytesSize; +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI Transfer Error and status match Interrupt */ +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; + ARM GAS /tmp/ccNpZKQO.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Configure the Memory Mapped mode. +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cmd : structure that contains the command configuration information. +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cfg : structure that contains the memory mapped configuration information. +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note This function is used only in Memory mapped Mode +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the parameters */ +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait till BUSY flag reset */ +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) + ARM GAS /tmp/ccNpZKQO.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CR register with timeout counter enable */ +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: LPTR register with the low-power timeout value */ +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI TimeOut Interrupt */ +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Call the configuration function */ +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Transfer Error callback. +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE : This function should not be modified, when the callback is needed, +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_ErrorCallback could be implemented in the user file +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Abort completed callback. +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccNpZKQO.s page 33 + + +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE: This function should not be modified, when the callback is needed, +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_AbortCpltCallback could be implemented in the user file +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Command completed callback. +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE: This function should not be modified, when the callback is needed, +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_CmdCpltCallback could be implemented in the user file +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Rx Transfer completed callback. +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE: This function should not be modified, when the callback is needed, +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_RxCpltCallback could be implemented in the user file +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Tx Transfer completed callback. +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE: This function should not be modified, when the callback is needed, +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_TxCpltCallback could be implemented in the user file +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief FIFO Threshold callback. +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None + ARM GAS /tmp/ccNpZKQO.s page 34 + + +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE : This function should not be modified, when the callback is needed, +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Status Match callback. +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE : This function should not be modified, when the callback is needed, +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_StatusMatchCallback could be implemented in the user file +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Timeout callback. +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** UNUSED(hqspi); +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* NOTE : This function should not be modified, when the callback is needed, +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** the HAL_QSPI_TimeOutCallback could be implemented in the user file +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Register a User QSPI Callback +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * To be used instead of the weak (surcharged) predefined callback +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param CallbackId : ID of the callback to be registered +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * This parameter can be one of the following values: +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + ARM GAS /tmp/ccNpZKQO.s page 35 + + +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param pCallback : pointer to the Callback function +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval status +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(pCallback == NULL) +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return HAL_ERROR; +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** switch (CallbackId) +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_ERROR_CB_ID : +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback = pCallback; +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_ABORT_CB_ID : +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->AbortCpltCallback = pCallback; +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_FIFO_THRESHOLD_CB_ID : +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->FifoThresholdCallback = pCallback; +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_CMD_CPLT_CB_ID : +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->CmdCpltCallback = pCallback; +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_RX_CPLT_CB_ID : +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxCpltCallback = pCallback; +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_TX_CPLT_CB_ID : +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxCpltCallback = pCallback; +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_STATUS_MATCH_CB_ID : +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->StatusMatchCallback = pCallback; +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_TIMEOUT_CB_ID : +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TimeOutCallback = pCallback; +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_INIT_CB_ID : +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspInitCallback = pCallback; +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_DEINIT_CB_ID : +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspDeInitCallback = pCallback; +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** default : +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* update return status */ +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + ARM GAS /tmp/ccNpZKQO.s page 36 + + +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if (hqspi->State == HAL_QSPI_STATE_RESET) +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** switch (CallbackId) +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_INIT_CB_ID : +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspInitCallback = pCallback; +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_DEINIT_CB_ID : +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspDeInitCallback = pCallback; +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** default : +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* update return status */ +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* update return status */ +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Release Lock */ +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Unregister a User QSPI Callback +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * QSPI Callback is redirected to the weak (surcharged) predefined callback +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param CallbackId : ID of the callback to be unregistered +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * This parameter can be one of the following values: +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval status +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); + ARM GAS /tmp/ccNpZKQO.s page 37 + + +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** switch (CallbackId) +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_ERROR_CB_ID : +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_ABORT_CB_ID : +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_FIFO_THRESHOLD_CB_ID : +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_CMD_CPLT_CB_ID : +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_RX_CPLT_CB_ID : +2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_TX_CPLT_CB_ID : +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; +2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_STATUS_MATCH_CB_ID : +2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; +2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_TIMEOUT_CB_ID : +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; +2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_INIT_CB_ID : +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspInitCallback = HAL_QSPI_MspInit; +2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_DEINIT_CB_ID : +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** default : +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* update return status */ +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else if (hqspi->State == HAL_QSPI_STATE_RESET) +2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** switch (CallbackId) +2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_INIT_CB_ID : +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspInitCallback = HAL_QSPI_MspInit; +2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** case HAL_QSPI_MSP_DEINIT_CB_ID : +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** default : +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* update return status */ + ARM GAS /tmp/ccNpZKQO.s page 38 + + +2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update the error code */ +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* update return status */ +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Release Lock */ +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @} +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief QSPI control and State functions +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** @verbatim +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** =============================================================================== +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ##### Peripheral Control and State functions ##### +2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** =============================================================================== +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** [..] +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** This subsection provides a set of functions allowing to : +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Check in run-time the state of the driver. +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Check the error code set during last operation. +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (+) Abort any operation. +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** @endverbatim +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @{ +2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Return the QSPI handle state. +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL state +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return QSPI handle state */ +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return hqspi->State; +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Return the QSPI error code. +2137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval QSPI Error Code +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) + ARM GAS /tmp/ccNpZKQO.s page 39 + + +2141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return hqspi->ErrorCode; +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Abort the current transmission. +2147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); +2154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check if the state is in one of the busy states */ +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (((uint32_t)hqspi->State & 0x2U) != 0U) +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); +2165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort MDMA */ +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_MDMA_Abort(hqspi->hmdma); +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(status != HAL_OK) +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; +2171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CR register with Abort request */ +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); +2176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until TC flag is set to go back in idle state */ +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until BUSY flag is reset */ +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeo +2186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (status == HAL_OK) +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Reset functional mode configuration to indirect write mode by default */ +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); +2192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 40 + + +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Abort the current transmission (non-blocking function) +2203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +2205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +2209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check if the state is in one of the busy states */ +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (((uint32_t)hqspi->State & 0x2U) != 0U) +2212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +2215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update QSPI state */ +2217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_ABORT; +2218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable all interrupts */ +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); +2221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ +2225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort MDMA channel */ +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) +2230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; +2233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort Complete callback */ +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +2236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->AbortCpltCallback(hqspi); +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else +2238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_AbortCpltCallback(hqspi); +2239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif +2240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI Transfer Complete Interrupt */ +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CR register with Abort request */ +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); +2252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; + ARM GAS /tmp/ccNpZKQO.s page 41 + + +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @brief Set QSPI timeout. +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle. +2259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Timeout : Timeout for the QSPI memory access. +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +2261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->Timeout = Timeout; +2265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @brief Set QSPI Fifo threshold. +2268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle. +2269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Threshold : Threshold of the Fifo (value between 1 and 16). +2270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +2271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +2275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +2278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +2280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Synchronize init structure with new FIFO threshold value */ +2282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->Init.FifoThreshold = Threshold; +2283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI FIFO Threshold */ +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); +2287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +2291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ +2297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @brief Get QSPI Fifo threshold. +2301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle. +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval Fifo threshold (value between 1 and 16) +2303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) +2305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); +2307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @brief Set FlashID. +2310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle. +2311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param FlashID : Index of the flash memory to be accessed. + ARM GAS /tmp/ccNpZKQO.s page 42 + + +2312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * This parameter can be a value of @ref QSPI_Flash_Select. +2313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @note The FlashID is ignored when dual flash mode is enabled. +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +2315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) +2317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the parameter */ +2321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FLASH_ID(FlashID)); +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process locked */ +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_LOCK(hqspi); +2325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_READY) +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Synchronize init structure with new FlashID value */ +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->Init.FlashID = FlashID; +2330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI FlashID */ +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); +2333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_BUSY; +2337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Process unlocked */ +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_UNLOCK(hqspi); +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return function status */ +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return status; +2344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @} +2348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @} +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** @defgroup QSPI_Private_Functions QSPI Private Functions +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @{ +2356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief DMA QSPI receive process complete callback. +2360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hmdma : MDMA handle +2361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) +2364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 28 .loc 1 2364 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccNpZKQO.s page 43 + + + 32 @ link register save eliminated. +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); + 33 .loc 1 2365 3 view .LVU1 + 34 .loc 1 2365 23 is_stmt 0 view .LVU2 + 35 0000 036C ldr r3, [r0, #64] + 36 .LVL1: +2366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount = 0U; + 37 .loc 1 2366 3 is_stmt 1 view .LVU3 + 38 .loc 1 2366 22 is_stmt 0 view .LVU4 + 39 0002 0022 movs r2, #0 + 40 0004 9A63 str r2, [r3, #56] +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transfer complete Interrupt */ +2369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + 41 .loc 1 2369 3 is_stmt 1 view .LVU5 + 42 0006 1A68 ldr r2, [r3] + 43 0008 1368 ldr r3, [r2] + 44 .LVL2: + 45 .loc 1 2369 3 is_stmt 0 view .LVU6 + 46 000a 43F40033 orr r3, r3, #131072 + 47 000e 1360 str r3, [r2] +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 48 .loc 1 2370 1 view .LVU7 + 49 0010 7047 bx lr + 50 .cfi_endproc + 51 .LFE173: + 53 .section .text.QSPI_DMATxCplt,"ax",%progbits + 54 .align 1 + 55 .syntax unified + 56 .thumb + 57 .thumb_func + 58 .fpu fpv5-d16 + 60 QSPI_DMATxCplt: + 61 .LVL3: + 62 .LFB174: +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief DMA QSPI transmit process complete callback. +2374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hmdma : MDMA handle +2375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) +2378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 63 .loc 1 2378 1 is_stmt 1 view -0 + 64 .cfi_startproc + 65 @ args = 0, pretend = 0, frame = 0 + 66 @ frame_needed = 0, uses_anonymous_args = 0 + 67 @ link register save eliminated. +2379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); + 68 .loc 1 2379 3 view .LVU9 + 69 .loc 1 2379 23 is_stmt 0 view .LVU10 + 70 0000 036C ldr r3, [r0, #64] + 71 .LVL4: +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; + 72 .loc 1 2380 3 is_stmt 1 view .LVU11 + 73 .loc 1 2380 22 is_stmt 0 view .LVU12 + 74 0002 0022 movs r2, #0 + ARM GAS /tmp/ccNpZKQO.s page 44 + + + 75 0004 DA62 str r2, [r3, #44] +2381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI transfer complete Interrupt */ +2383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + 76 .loc 1 2383 3 is_stmt 1 view .LVU13 + 77 0006 1A68 ldr r2, [r3] + 78 0008 1368 ldr r3, [r2] + 79 .LVL5: + 80 .loc 1 2383 3 is_stmt 0 view .LVU14 + 81 000a 43F40033 orr r3, r3, #131072 + 82 000e 1360 str r3, [r2] +2384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 83 .loc 1 2384 1 view .LVU15 + 84 0010 7047 bx lr + 85 .cfi_endproc + 86 .LFE174: + 88 .section .text.QSPI_Config,"ax",%progbits + 89 .align 1 + 90 .syntax unified + 91 .thumb + 92 .thumb_func + 93 .fpu fpv5-d16 + 95 QSPI_Config: + 96 .LVL6: + 97 .LFB178: +2385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief DMA QSPI communication error callback. +2388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hmdma : MDMA handle +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +2390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount = 0U; +2396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; +2398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */ +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); +2401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Abort the QSPI */ +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (void)HAL_QSPI_Abort_IT(hqspi); +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief MDMA QSPI abort complete callback. +2409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hmdma : MDMA handle +2410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +2411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) +2413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); +2415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount = 0U; + ARM GAS /tmp/ccNpZKQO.s page 45 + + +2417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; +2418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(hqspi->State == HAL_QSPI_STATE_ABORT) +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* MDMA Abort called by QSPI abort */ +2422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Clear interrupt */ +2423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); +2424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Enable the QSPI Transfer Complete Interrupt */ +2426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CR register with Abort request */ +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* MDMA Abort called due to a transfer error interrupt */ +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Change state of QSPI */ +2435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; +2436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Error callback */ +2438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCallback(hqspi); +2440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #else +2441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_QSPI_ErrorCallback(hqspi); +2442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif +2443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Wait for a flag state until timeout. +2448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Flag : Flag checked +2450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param State : Value of the flag expected +2451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Tickstart : Tick start value +2452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param Timeout : Duration of the timeout +2453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval HAL status +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, +2456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** FlagStatus State, uint32_t Tickstart, uint3 +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until flag is in expected state */ +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) +2460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check for the Timeout */ +2462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (Timeout != HAL_MAX_DELAY) +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +2465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_ERROR; +2467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; +2468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return HAL_ERROR; +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return HAL_OK; + ARM GAS /tmp/ccNpZKQO.s page 46 + + +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /** +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @brief Configure the communication registers. +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param hqspi : QSPI handle +2479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param cmd : structure that contains the command configuration information +2480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @param FunctionalMode : functional mode to configured +2481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * This parameter can be one of the following values: +2482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode +2484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode +2485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** * @retval None +2487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** */ +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 98 .loc 1 2489 1 is_stmt 1 view -0 + 99 .cfi_startproc + 100 @ args = 0, pretend = 0, frame = 0 + 101 @ frame_needed = 0, uses_anonymous_args = 0 + 102 @ link register save eliminated. + 103 .loc 1 2489 1 is_stmt 0 view .LVU17 + 104 0000 F0B4 push {r4, r5, r6, r7} + 105 .LCFI0: + 106 .cfi_def_cfa_offset 16 + 107 .cfi_offset 4, -16 + 108 .cfi_offset 5, -12 + 109 .cfi_offset 6, -8 + 110 .cfi_offset 7, -4 +2490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode)); + 111 .loc 1 2490 3 is_stmt 1 view .LVU18 +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + 112 .loc 1 2492 3 view .LVU19 + 113 .loc 1 2492 11 is_stmt 0 view .LVU20 + 114 0002 4B6A ldr r3, [r1, #36] + 115 .loc 1 2492 6 view .LVU21 + 116 0004 33B1 cbz r3, .L4 + 117 .loc 1 2492 41 discriminator 1 view .LVU22 + 118 0006 B2F1406F cmp r2, #201326592 + 119 000a 03D0 beq .L4 +2493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: DLR register with the number of data to read or write */ +2495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); + 120 .loc 1 2495 5 is_stmt 1 view .LVU23 + 121 000c 8B6A ldr r3, [r1, #40] + 122 000e 0468 ldr r4, [r0] + 123 0010 013B subs r3, r3, #1 + 124 0012 2361 str r3, [r4, #16] + 125 .L4: +2496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 126 .loc 1 2498 3 view .LVU24 + 127 .loc 1 2498 10 is_stmt 0 view .LVU25 + 128 0014 8C69 ldr r4, [r1, #24] + 129 .loc 1 2498 6 view .LVU26 + ARM GAS /tmp/ccNpZKQO.s page 47 + + + 130 0016 002C cmp r4, #0 + 131 0018 6ED0 beq .L5 +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 132 .loc 1 2500 5 is_stmt 1 view .LVU27 + 133 .loc 1 2500 12 is_stmt 0 view .LVU28 + 134 001a 0E6A ldr r6, [r1, #32] + 135 .loc 1 2500 8 view .LVU29 + 136 001c 002E cmp r6, #0 + 137 001e 3BD0 beq .L6 +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: ABR register with alternate bytes value */ +2503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); + 138 .loc 1 2503 7 is_stmt 1 view .LVU30 + 139 0020 0368 ldr r3, [r0] + 140 0022 8C68 ldr r4, [r1, #8] + 141 0024 DC61 str r4, [r3, #28] +2504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 142 .loc 1 2505 7 view .LVU31 + 143 .loc 1 2505 14 is_stmt 0 view .LVU32 + 144 0026 CC69 ldr r4, [r1, #28] + 145 .loc 1 2505 10 view .LVU33 + 146 0028 F4B1 cbz r4, .L7 +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with instruction, address and alternate bytes ----*/ +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + 147 .loc 1 2509 9 is_stmt 1 view .LVU34 + 148 002a CB6A ldr r3, [r1, #44] + 149 002c 0D6B ldr r5, [r1, #48] + 150 002e 2B43 orrs r3, r3, r5 + 151 0030 4D6B ldr r5, [r1, #52] + 152 0032 2B43 orrs r3, r3, r5 + 153 0034 4D6A ldr r5, [r1, #36] + 154 0036 2B43 orrs r3, r3, r5 + 155 0038 4D69 ldr r5, [r1, #20] + 156 003a 43EA8543 orr r3, r3, r5, lsl #18 + 157 003e 0D69 ldr r5, [r1, #16] + 158 0040 2B43 orrs r3, r3, r5 + 159 0042 0D6A ldr r5, [r1, #32] + 160 0044 2B43 orrs r3, r3, r5 + 161 0046 CD68 ldr r5, [r1, #12] + 162 0048 2B43 orrs r3, r3, r5 + 163 004a 2343 orrs r3, r3, r4 + 164 004c 8C69 ldr r4, [r1, #24] + 165 004e 2343 orrs r3, r3, r4 + 166 0050 0C68 ldr r4, [r1] + 167 0052 2343 orrs r3, r3, r4 + 168 0054 0468 ldr r4, [r0] + 169 0056 1343 orrs r3, r3, r2 + 170 0058 6361 str r3, [r4, #20] +2510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateBytesSize | cmd->AlternateByteMode | +2512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode +2513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->Instruction | FunctionalMode)); +2514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 48 + + +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) + 171 .loc 1 2515 9 view .LVU35 + 172 .loc 1 2515 12 is_stmt 0 view .LVU36 + 173 005a B2F1406F cmp r2, #201326592 + 174 005e 19D0 beq .L3 +2516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: AR register with address value */ +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, cmd->Address); + 175 .loc 1 2518 11 is_stmt 1 view .LVU37 + 176 0060 0368 ldr r3, [r0] + 177 0062 4A68 ldr r2, [r1, #4] + 178 .LVL7: + 179 .loc 1 2518 11 is_stmt 0 view .LVU38 + 180 0064 9A61 str r2, [r3, #24] + 181 0066 15E0 b .L3 + 182 .LVL8: + 183 .L7: +2519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with instruction and alternate bytes ----*/ +2524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + 184 .loc 1 2525 9 is_stmt 1 view .LVU39 + 185 0068 CB6A ldr r3, [r1, #44] + 186 006a 0D6B ldr r5, [r1, #48] + 187 006c 2B43 orrs r3, r3, r5 + 188 006e 4D6B ldr r5, [r1, #52] + 189 0070 2B43 orrs r3, r3, r5 + 190 0072 4D6A ldr r5, [r1, #36] + 191 0074 2B43 orrs r3, r3, r5 + 192 0076 4D69 ldr r5, [r1, #20] + 193 0078 43EA8543 orr r3, r3, r5, lsl #18 + 194 007c 0D69 ldr r5, [r1, #16] + 195 007e 2B43 orrs r3, r3, r5 + 196 0080 0D6A ldr r5, [r1, #32] + 197 0082 2B43 orrs r3, r3, r5 + 198 0084 2343 orrs r3, r3, r4 + 199 0086 8C69 ldr r4, [r1, #24] + 200 0088 2343 orrs r3, r3, r4 + 201 008a 0C68 ldr r4, [r1] + 202 008c 2343 orrs r3, r3, r4 + 203 008e 0168 ldr r1, [r0] + 204 .LVL9: + 205 .loc 1 2525 9 is_stmt 0 view .LVU40 + 206 0090 1A43 orrs r2, r2, r3 + 207 .LVL10: + 208 .loc 1 2525 9 view .LVU41 + 209 0092 4A61 str r2, [r1, #20] + 210 .L3: +2526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) +2527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateBytesSize | cmd->AlternateByteMode | +2528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AddressMode | cmd->InstructionMode | +2529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->Instruction | FunctionalMode)); +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 49 + + +2532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) +2535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with instruction and address ----*/ +2537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | +2539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) +2540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMo +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->InstructionMode | cmd->Instruction | FunctionalMode)) +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) +2544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: AR register with address value */ +2546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, cmd->Address); +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with only instruction ----*/ +2552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | +2554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) +2555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateByteMode | cmd->AddressMode | +2556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->InstructionMode | cmd->Instruction | FunctionalMode)) +2557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) +2563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: ABR register with alternate bytes value */ +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); +2566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with address and alternate bytes ----*/ +2570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | +2572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateBytesSize | cmd->AlternateByteMode | +2574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AddressSize | cmd->AddressMode | +2575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->InstructionMode | FunctionalMode)); +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: AR register with address value */ +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, cmd->Address); +2581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with only alternate bytes ----*/ +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + ARM GAS /tmp/ccNpZKQO.s page 50 + + +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateBytesSize | cmd->AlternateByteMode | +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AddressMode | cmd->InstructionMode | FunctionalMode)) +2591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) +2596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with only address ----*/ +2598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateByteMode | cmd->AddressSize | +2602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AddressMode | cmd->InstructionMode | FunctionalMode)) +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: AR register with address value */ +2607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->AR, cmd->Address); +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** else +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /*---- Command with only data phase ----*/ +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->DataMode != QSPI_DATA_NONE) +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { +2615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Configure QSPI: CCR register with all communications parameters */ +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | +2617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Po +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->AlternateByteMode | cmd->AddressMode | +2619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->InstructionMode | FunctionalMode)); +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } +2624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 211 .loc 1 2624 1 view .LVU42 + 212 0094 F0BC pop {r4, r5, r6, r7} + 213 .LCFI1: + 214 .cfi_remember_state + 215 .cfi_restore 7 + 216 .cfi_restore 6 + 217 .cfi_restore 5 + 218 .cfi_restore 4 + 219 .cfi_def_cfa_offset 0 + 220 0096 7047 bx lr + 221 .LVL11: + 222 .L6: + 223 .LCFI2: + 224 .cfi_restore_state +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 225 .loc 1 2534 7 is_stmt 1 view .LVU43 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 226 .loc 1 2534 14 is_stmt 0 view .LVU44 + 227 0098 CD69 ldr r5, [r1, #28] +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 228 .loc 1 2534 10 view .LVU45 + ARM GAS /tmp/ccNpZKQO.s page 51 + + + 229 009a D5B1 cbz r5, .L9 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 230 .loc 1 2538 9 is_stmt 1 view .LVU46 + 231 009c CB6A ldr r3, [r1, #44] + 232 009e 0F6B ldr r7, [r1, #48] + 233 00a0 3B43 orrs r3, r3, r7 + 234 00a2 4F6B ldr r7, [r1, #52] + 235 00a4 3B43 orrs r3, r3, r7 + 236 00a6 4F6A ldr r7, [r1, #36] + 237 00a8 3B43 orrs r3, r3, r7 + 238 00aa 4F69 ldr r7, [r1, #20] + 239 00ac 43EA8743 orr r3, r3, r7, lsl #18 + 240 00b0 3343 orrs r3, r3, r6 + 241 00b2 CE68 ldr r6, [r1, #12] + 242 00b4 3343 orrs r3, r3, r6 + 243 00b6 2B43 orrs r3, r3, r5 + 244 00b8 2343 orrs r3, r3, r4 + 245 00ba 0C68 ldr r4, [r1] + 246 00bc 2343 orrs r3, r3, r4 + 247 00be 0468 ldr r4, [r0] + 248 00c0 1343 orrs r3, r3, r2 + 249 00c2 6361 str r3, [r4, #20] +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 250 .loc 1 2543 9 view .LVU47 +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 251 .loc 1 2543 12 is_stmt 0 view .LVU48 + 252 00c4 B2F1406F cmp r2, #201326592 + 253 00c8 E4D0 beq .L3 +2546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 254 .loc 1 2546 11 is_stmt 1 view .LVU49 + 255 00ca 0368 ldr r3, [r0] + 256 00cc 4A68 ldr r2, [r1, #4] + 257 .LVL12: +2546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 258 .loc 1 2546 11 is_stmt 0 view .LVU50 + 259 00ce 9A61 str r2, [r3, #24] + 260 00d0 E0E7 b .L3 + 261 .LVL13: + 262 .L9: +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 263 .loc 1 2553 9 is_stmt 1 view .LVU51 + 264 00d2 CB6A ldr r3, [r1, #44] + 265 00d4 0F6B ldr r7, [r1, #48] + 266 00d6 3B43 orrs r3, r3, r7 + 267 00d8 4F6B ldr r7, [r1, #52] + 268 00da 3B43 orrs r3, r3, r7 + 269 00dc 4F6A ldr r7, [r1, #36] + 270 00de 3B43 orrs r3, r3, r7 + 271 00e0 4F69 ldr r7, [r1, #20] + 272 00e2 43EA8743 orr r3, r3, r7, lsl #18 + 273 00e6 3343 orrs r3, r3, r6 + 274 00e8 2B43 orrs r3, r3, r5 + 275 00ea 2343 orrs r3, r3, r4 + 276 00ec 0C68 ldr r4, [r1] + 277 00ee 2343 orrs r3, r3, r4 + 278 00f0 0168 ldr r1, [r0] + 279 .LVL14: + ARM GAS /tmp/ccNpZKQO.s page 52 + + +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 280 .loc 1 2553 9 is_stmt 0 view .LVU52 + 281 00f2 1A43 orrs r2, r2, r3 + 282 .LVL15: +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 283 .loc 1 2553 9 view .LVU53 + 284 00f4 4A61 str r2, [r1, #20] + 285 00f6 CDE7 b .L3 + 286 .LVL16: + 287 .L5: +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 288 .loc 1 2562 5 is_stmt 1 view .LVU54 +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 289 .loc 1 2562 12 is_stmt 0 view .LVU55 + 290 00f8 0D6A ldr r5, [r1, #32] +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 291 .loc 1 2562 8 view .LVU56 + 292 00fa 002D cmp r5, #0 + 293 00fc 37D0 beq .L10 +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 294 .loc 1 2565 7 is_stmt 1 view .LVU57 + 295 00fe 0368 ldr r3, [r0] + 296 0100 8C68 ldr r4, [r1, #8] + 297 0102 DC61 str r4, [r3, #28] +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 298 .loc 1 2567 7 view .LVU58 +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 299 .loc 1 2567 14 is_stmt 0 view .LVU59 + 300 0104 CD69 ldr r5, [r1, #28] +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 301 .loc 1 2567 10 view .LVU60 + 302 0106 E5B1 cbz r5, .L11 +2571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 303 .loc 1 2571 9 is_stmt 1 view .LVU61 + 304 0108 CB6A ldr r3, [r1, #44] + 305 010a 0C6B ldr r4, [r1, #48] + 306 010c 2343 orrs r3, r3, r4 + 307 010e 4C6B ldr r4, [r1, #52] + 308 0110 2343 orrs r3, r3, r4 + 309 0112 4C6A ldr r4, [r1, #36] + 310 0114 2343 orrs r3, r3, r4 + 311 0116 4C69 ldr r4, [r1, #20] + 312 0118 43EA8443 orr r3, r3, r4, lsl #18 + 313 011c 0C69 ldr r4, [r1, #16] + 314 011e 2343 orrs r3, r3, r4 + 315 0120 0C6A ldr r4, [r1, #32] + 316 0122 2343 orrs r3, r3, r4 + 317 0124 CC68 ldr r4, [r1, #12] + 318 0126 2343 orrs r3, r3, r4 + 319 0128 2B43 orrs r3, r3, r5 + 320 012a 8C69 ldr r4, [r1, #24] + 321 012c 2343 orrs r3, r3, r4 + 322 012e 0468 ldr r4, [r0] + 323 0130 1343 orrs r3, r3, r2 + 324 0132 6361 str r3, [r4, #20] +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 325 .loc 1 2577 9 view .LVU62 + ARM GAS /tmp/ccNpZKQO.s page 53 + + +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 326 .loc 1 2577 12 is_stmt 0 view .LVU63 + 327 0134 B2F1406F cmp r2, #201326592 + 328 0138 ACD0 beq .L3 +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 329 .loc 1 2580 11 is_stmt 1 view .LVU64 + 330 013a 0368 ldr r3, [r0] + 331 013c 4A68 ldr r2, [r1, #4] + 332 .LVL17: +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 333 .loc 1 2580 11 is_stmt 0 view .LVU65 + 334 013e 9A61 str r2, [r3, #24] + 335 0140 A8E7 b .L3 + 336 .LVL18: + 337 .L11: +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 338 .loc 1 2587 9 is_stmt 1 view .LVU66 + 339 0142 CC6A ldr r4, [r1, #44] + 340 0144 0B6B ldr r3, [r1, #48] + 341 0146 1C43 orrs r4, r4, r3 + 342 0148 4B6B ldr r3, [r1, #52] + 343 014a 1C43 orrs r4, r4, r3 + 344 014c 4B6A ldr r3, [r1, #36] + 345 014e 1C43 orrs r4, r4, r3 + 346 0150 4B69 ldr r3, [r1, #20] + 347 0152 44EA8344 orr r4, r4, r3, lsl #18 + 348 0156 0B69 ldr r3, [r1, #16] + 349 0158 1C43 orrs r4, r4, r3 + 350 015a 0B6A ldr r3, [r1, #32] + 351 015c 1C43 orrs r4, r4, r3 + 352 015e 45EA0403 orr r3, r5, r4 + 353 0162 8C69 ldr r4, [r1, #24] + 354 0164 2343 orrs r3, r3, r4 + 355 0166 0168 ldr r1, [r0] + 356 .LVL19: +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 357 .loc 1 2587 9 is_stmt 0 view .LVU67 + 358 0168 1A43 orrs r2, r2, r3 + 359 .LVL20: +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 360 .loc 1 2587 9 view .LVU68 + 361 016a 4A61 str r2, [r1, #20] + 362 016c 92E7 b .L3 + 363 .LVL21: + 364 .L10: +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 365 .loc 1 2595 7 is_stmt 1 view .LVU69 +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 366 .loc 1 2595 14 is_stmt 0 view .LVU70 + 367 016e CE69 ldr r6, [r1, #28] +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 368 .loc 1 2595 10 view .LVU71 + 369 0170 CEB1 cbz r6, .L12 +2599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) + 370 .loc 1 2599 9 is_stmt 1 view .LVU72 + 371 0172 0B6B ldr r3, [r1, #48] + 372 0174 CF6A ldr r7, [r1, #44] + ARM GAS /tmp/ccNpZKQO.s page 54 + + + 373 0176 3B43 orrs r3, r3, r7 + 374 0178 4F6B ldr r7, [r1, #52] + 375 017a 3B43 orrs r3, r3, r7 + 376 017c 4F6A ldr r7, [r1, #36] + 377 017e 3B43 orrs r3, r3, r7 + 378 0180 4F69 ldr r7, [r1, #20] + 379 0182 43EA8743 orr r3, r3, r7, lsl #18 + 380 0186 2B43 orrs r3, r3, r5 + 381 0188 CD68 ldr r5, [r1, #12] + 382 018a 2B43 orrs r3, r3, r5 + 383 018c 3343 orrs r3, r3, r6 + 384 018e 2343 orrs r3, r3, r4 + 385 0190 0468 ldr r4, [r0] + 386 0192 1343 orrs r3, r3, r2 + 387 0194 6361 str r3, [r4, #20] +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 388 .loc 1 2604 9 view .LVU73 +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 389 .loc 1 2604 12 is_stmt 0 view .LVU74 + 390 0196 B2F1406F cmp r2, #201326592 + 391 019a 3FF47BAF beq .L3 +2607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 392 .loc 1 2607 11 is_stmt 1 view .LVU75 + 393 019e 0368 ldr r3, [r0] + 394 01a0 4A68 ldr r2, [r1, #4] + 395 .LVL22: +2607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 396 .loc 1 2607 11 is_stmt 0 view .LVU76 + 397 01a2 9A61 str r2, [r3, #24] + 398 01a4 76E7 b .L3 + 399 .LVL23: + 400 .L12: +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 401 .loc 1 2613 9 is_stmt 1 view .LVU77 +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 402 .loc 1 2613 16 is_stmt 0 view .LVU78 + 403 01a6 D1F824C0 ldr ip, [r1, #36] +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 404 .loc 1 2613 12 view .LVU79 + 405 01aa BCF1000F cmp ip, #0 + 406 01ae 3FF471AF beq .L3 +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Po + 407 .loc 1 2616 11 is_stmt 1 view .LVU80 + 408 01b2 CB6A ldr r3, [r1, #44] + 409 01b4 0F6B ldr r7, [r1, #48] + 410 01b6 3B43 orrs r3, r3, r7 + 411 01b8 4F6B ldr r7, [r1, #52] + 412 01ba 3B43 orrs r3, r3, r7 + 413 01bc 4CEA0307 orr r7, ip, r3 + 414 01c0 4B69 ldr r3, [r1, #20] + 415 01c2 47EA8343 orr r3, r7, r3, lsl #18 + 416 01c6 1D43 orrs r5, r5, r3 + 417 01c8 46EA0503 orr r3, r6, r5 + 418 01cc 2343 orrs r3, r3, r4 + 419 01ce 0168 ldr r1, [r0] + 420 .LVL24: +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Po + ARM GAS /tmp/ccNpZKQO.s page 55 + + + 421 .loc 1 2616 11 is_stmt 0 view .LVU81 + 422 01d0 1A43 orrs r2, r2, r3 + 423 .LVL25: +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Po + 424 .loc 1 2616 11 view .LVU82 + 425 01d2 4A61 str r2, [r1, #20] + 426 .loc 1 2624 1 view .LVU83 + 427 01d4 5EE7 b .L3 + 428 .cfi_endproc + 429 .LFE178: + 431 .section .text.QSPI_WaitFlagStateUntilTimeout,"ax",%progbits + 432 .align 1 + 433 .syntax unified + 434 .thumb + 435 .thumb_func + 436 .fpu fpv5-d16 + 438 QSPI_WaitFlagStateUntilTimeout: + 439 .LVL26: + 440 .LFB177: +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until flag is in expected state */ + 441 .loc 1 2457 1 is_stmt 1 view -0 + 442 .cfi_startproc + 443 @ args = 4, pretend = 0, frame = 0 + 444 @ frame_needed = 0, uses_anonymous_args = 0 +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Wait until flag is in expected state */ + 445 .loc 1 2457 1 is_stmt 0 view .LVU85 + 446 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 447 .LCFI3: + 448 .cfi_def_cfa_offset 32 + 449 .cfi_offset 3, -32 + 450 .cfi_offset 4, -28 + 451 .cfi_offset 5, -24 + 452 .cfi_offset 6, -20 + 453 .cfi_offset 7, -16 + 454 .cfi_offset 8, -12 + 455 .cfi_offset 9, -8 + 456 .cfi_offset 14, -4 + 457 0004 0546 mov r5, r0 + 458 0006 0F46 mov r7, r1 + 459 0008 1646 mov r6, r2 + 460 000a 9946 mov r9, r3 + 461 000c DDF82080 ldr r8, [sp, #32] +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 462 .loc 1 2459 3 is_stmt 1 view .LVU86 + 463 .LVL27: + 464 .L16: +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 465 .loc 1 2459 8 view .LVU87 +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 466 .loc 1 2459 10 is_stmt 0 view .LVU88 + 467 0010 2C68 ldr r4, [r5] + 468 0012 A468 ldr r4, [r4, #8] + 469 0014 3C42 tst r4, r7 + 470 0016 14BF ite ne + 471 0018 4FF0010C movne ip, #1 + 472 001c 4FF0000C moveq ip, #0 +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 56 + + + 473 .loc 1 2459 8 view .LVU89 + 474 0020 B445 cmp ip, r6 + 475 0022 14D0 beq .L21 +2462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 476 .loc 1 2462 5 is_stmt 1 view .LVU90 +2462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 477 .loc 1 2462 8 is_stmt 0 view .LVU91 + 478 0024 B8F1FF3F cmp r8, #-1 + 479 0028 F2D0 beq .L16 +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 480 .loc 1 2464 7 is_stmt 1 view .LVU92 +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 481 .loc 1 2464 12 is_stmt 0 view .LVU93 + 482 002a FFF7FEFF bl HAL_GetTick + 483 .LVL28: +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 484 .loc 1 2464 26 view .LVU94 + 485 002e A0EB0900 sub r0, r0, r9 +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 486 .loc 1 2464 9 view .LVU95 + 487 0032 4045 cmp r0, r8 + 488 0034 02D8 bhi .L17 +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 489 .loc 1 2464 50 discriminator 1 view .LVU96 + 490 0036 B8F1000F cmp r8, #0 + 491 003a E9D1 bne .L16 + 492 .L17: +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; + 493 .loc 1 2466 9 is_stmt 1 view .LVU97 +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; + 494 .loc 1 2466 26 is_stmt 0 view .LVU98 + 495 003c 0423 movs r3, #4 + 496 003e 85F84130 strb r3, [r5, #65] +2467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 497 .loc 1 2467 9 is_stmt 1 view .LVU99 +2467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 498 .loc 1 2467 26 is_stmt 0 view .LVU100 + 499 0042 6B6C ldr r3, [r5, #68] + 500 0044 43F00103 orr r3, r3, #1 + 501 0048 6B64 str r3, [r5, #68] +2469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 502 .loc 1 2469 9 is_stmt 1 view .LVU101 +2469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 503 .loc 1 2469 16 is_stmt 0 view .LVU102 + 504 004a 0120 movs r0, #1 + 505 004c 00E0 b .L18 + 506 .L21: +2473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 507 .loc 1 2473 10 view .LVU103 + 508 004e 0020 movs r0, #0 + 509 .L18: +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 510 .loc 1 2474 1 view .LVU104 + 511 0050 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 512 .loc 1 2474 1 view .LVU105 + 513 .cfi_endproc + ARM GAS /tmp/ccNpZKQO.s page 57 + + + 514 .LFE177: + 516 .section .text.HAL_QSPI_MspInit,"ax",%progbits + 517 .align 1 + 518 .weak HAL_QSPI_MspInit + 519 .syntax unified + 520 .thumb + 521 .thumb_func + 522 .fpu fpv5-d16 + 524 HAL_QSPI_MspInit: + 525 .LVL29: + 526 .LFB143: + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 527 .loc 1 439 1 is_stmt 1 view -0 + 528 .cfi_startproc + 529 @ args = 0, pretend = 0, frame = 0 + 530 @ frame_needed = 0, uses_anonymous_args = 0 + 531 @ link register save eliminated. + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 532 .loc 1 441 3 view .LVU107 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 533 .loc 1 446 1 is_stmt 0 view .LVU108 + 534 0000 7047 bx lr + 535 .cfi_endproc + 536 .LFE143: + 538 .section .text.HAL_QSPI_MspDeInit,"ax",%progbits + 539 .align 1 + 540 .weak HAL_QSPI_MspDeInit + 541 .syntax unified + 542 .thumb + 543 .thumb_func + 544 .fpu fpv5-d16 + 546 HAL_QSPI_MspDeInit: + 547 .LVL30: + 548 .LFB144: + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 549 .loc 1 454 1 is_stmt 1 view -0 + 550 .cfi_startproc + 551 @ args = 0, pretend = 0, frame = 0 + 552 @ frame_needed = 0, uses_anonymous_args = 0 + 553 @ link register save eliminated. + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 554 .loc 1 456 3 view .LVU110 + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 555 .loc 1 461 1 is_stmt 0 view .LVU111 + 556 0000 7047 bx lr + 557 .cfi_endproc + 558 .LFE144: + 560 .section .text.HAL_QSPI_DeInit,"ax",%progbits + 561 .align 1 + 562 .global HAL_QSPI_DeInit + 563 .syntax unified + 564 .thumb + 565 .thumb_func + 566 .fpu fpv5-d16 + 568 HAL_QSPI_DeInit: + 569 .LVL31: + 570 .LFB142: + ARM GAS /tmp/ccNpZKQO.s page 58 + + + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the QSPI handle allocation */ + 571 .loc 1 401 1 is_stmt 1 view -0 + 572 .cfi_startproc + 573 @ args = 0, pretend = 0, frame = 0 + 574 @ frame_needed = 0, uses_anonymous_args = 0 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 575 .loc 1 403 3 view .LVU113 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 576 .loc 1 403 5 is_stmt 0 view .LVU114 + 577 0000 68B1 cbz r0, .L26 + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Check the QSPI handle allocation */ + 578 .loc 1 401 1 view .LVU115 + 579 0002 10B5 push {r4, lr} + 580 .LCFI4: + 581 .cfi_def_cfa_offset 8 + 582 .cfi_offset 4, -8 + 583 .cfi_offset 14, -4 + 584 0004 0446 mov r4, r0 + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 585 .loc 1 409 3 is_stmt 1 view .LVU116 + 586 0006 0268 ldr r2, [r0] + 587 0008 1368 ldr r3, [r2] + 588 000a 23F00103 bic r3, r3, #1 + 589 000e 1360 str r3, [r2] + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 590 .loc 1 421 3 view .LVU117 + 591 0010 FFF7FEFF bl HAL_QSPI_MspDeInit + 592 .LVL32: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 593 .loc 1 425 3 view .LVU118 + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 594 .loc 1 425 20 is_stmt 0 view .LVU119 + 595 0014 0020 movs r0, #0 + 596 0016 6064 str r0, [r4, #68] + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 597 .loc 1 428 3 is_stmt 1 view .LVU120 + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 598 .loc 1 428 16 is_stmt 0 view .LVU121 + 599 0018 84F84100 strb r0, [r4, #65] + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 600 .loc 1 430 3 is_stmt 1 view .LVU122 + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 601 .loc 1 431 1 is_stmt 0 view .LVU123 + 602 001c 10BD pop {r4, pc} + 603 .LVL33: + 604 .L26: + 605 .LCFI5: + 606 .cfi_def_cfa_offset 0 + 607 .cfi_restore 4 + 608 .cfi_restore 14 + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 609 .loc 1 405 12 view .LVU124 + 610 001e 0120 movs r0, #1 + 611 .LVL34: + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 612 .loc 1 431 1 view .LVU125 + 613 0020 7047 bx lr + ARM GAS /tmp/ccNpZKQO.s page 59 + + + 614 .cfi_endproc + 615 .LFE142: + 617 .section .text.HAL_QSPI_Command,"ax",%progbits + 618 .align 1 + 619 .global HAL_QSPI_Command + 620 .syntax unified + 621 .thumb + 622 .thumb_func + 623 .fpu fpv5-d16 + 625 HAL_QSPI_Command: + 626 .LVL35: + 627 .LFB146: + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 628 .loc 1 782 1 is_stmt 1 view -0 + 629 .cfi_startproc + 630 @ args = 0, pretend = 0, frame = 0 + 631 @ frame_needed = 0, uses_anonymous_args = 0 + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 632 .loc 1 782 1 is_stmt 0 view .LVU127 + 633 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 634 .LCFI6: + 635 .cfi_def_cfa_offset 24 + 636 .cfi_offset 4, -24 + 637 .cfi_offset 5, -20 + 638 .cfi_offset 6, -16 + 639 .cfi_offset 7, -12 + 640 .cfi_offset 8, -8 + 641 .cfi_offset 14, -4 + 642 0004 82B0 sub sp, sp, #8 + 643 .LCFI7: + 644 .cfi_def_cfa_offset 32 + 645 0006 0446 mov r4, r0 + 646 0008 0F46 mov r7, r1 + 647 000a 1646 mov r6, r2 + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 648 .loc 1 783 3 is_stmt 1 view .LVU128 + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 649 .loc 1 784 3 view .LVU129 + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 650 .loc 1 784 24 is_stmt 0 view .LVU130 + 651 000c FFF7FEFF bl HAL_GetTick + 652 .LVL36: + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 653 .loc 1 787 3 is_stmt 1 view .LVU131 + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 654 .loc 1 788 3 view .LVU132 + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 655 .loc 1 790 5 view .LVU133 + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 656 .loc 1 793 3 view .LVU134 + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 657 .loc 1 794 3 view .LVU135 + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 658 .loc 1 796 5 view .LVU136 + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 659 .loc 1 799 3 view .LVU137 + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 60 + + + 660 .loc 1 800 3 view .LVU138 + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 661 .loc 1 802 5 view .LVU139 + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 662 .loc 1 805 3 view .LVU140 + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 663 .loc 1 806 3 view .LVU141 + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 664 .loc 1 808 3 view .LVU142 + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 665 .loc 1 809 3 view .LVU143 + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 666 .loc 1 810 3 view .LVU144 + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 667 .loc 1 813 3 view .LVU145 + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 668 .loc 1 813 3 view .LVU146 + 669 0010 94F840C0 ldrb ip, [r4, #64] @ zero_extendqisi2 + 670 0014 5FFA8CFC uxtb ip, ip + 671 0018 BCF1010F cmp ip, #1 + 672 001c 3CD0 beq .L35 + 673 001e 0546 mov r5, r0 + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 674 .loc 1 813 3 discriminator 2 view .LVU147 + 675 0020 0123 movs r3, #1 + 676 0022 84F84030 strb r3, [r4, #64] + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 677 .loc 1 813 3 discriminator 2 view .LVU148 + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 678 .loc 1 815 3 discriminator 2 view .LVU149 + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 679 .loc 1 815 11 is_stmt 0 discriminator 2 view .LVU150 + 680 0026 94F841C0 ldrb ip, [r4, #65] @ zero_extendqisi2 + 681 002a 5FFA8CFC uxtb ip, ip + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 682 .loc 1 815 5 discriminator 2 view .LVU151 + 683 002e 9C45 cmp ip, r3 + 684 0030 08D0 beq .L38 + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 685 .loc 1 853 12 view .LVU152 + 686 0032 4FF00208 mov r8, #2 + 687 .LVL37: + 688 .L33: + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 689 .loc 1 857 3 is_stmt 1 view .LVU153 + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 690 .loc 1 857 3 view .LVU154 + 691 0036 0023 movs r3, #0 + 692 0038 84F84030 strb r3, [r4, #64] + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 693 .loc 1 857 3 view .LVU155 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 694 .loc 1 860 3 view .LVU156 + 695 .LVL38: + 696 .L32: + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 697 .loc 1 861 1 is_stmt 0 view .LVU157 + ARM GAS /tmp/ccNpZKQO.s page 61 + + + 698 003c 4046 mov r0, r8 + 699 003e 02B0 add sp, sp, #8 + 700 .LCFI8: + 701 .cfi_remember_state + 702 .cfi_def_cfa_offset 24 + 703 @ sp needed + 704 0040 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 705 .LVL39: + 706 .L38: + 707 .LCFI9: + 708 .cfi_restore_state + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 709 .loc 1 817 5 is_stmt 1 view .LVU158 + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 710 .loc 1 817 22 is_stmt 0 view .LVU159 + 711 0044 0022 movs r2, #0 + 712 0046 6264 str r2, [r4, #68] + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 713 .loc 1 820 5 is_stmt 1 view .LVU160 + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 714 .loc 1 820 18 is_stmt 0 view .LVU161 + 715 0048 0223 movs r3, #2 + 716 004a 84F84130 strb r3, [r4, #65] + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 717 .loc 1 823 5 is_stmt 1 view .LVU162 + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 718 .loc 1 823 14 is_stmt 0 view .LVU163 + 719 004e 0096 str r6, [sp] + 720 0050 0346 mov r3, r0 + 721 0052 2021 movs r1, #32 + 722 0054 2046 mov r0, r4 + 723 .LVL40: + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 724 .loc 1 823 14 view .LVU164 + 725 0056 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 726 .LVL41: + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 727 .loc 1 825 5 is_stmt 1 view .LVU165 + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 728 .loc 1 825 8 is_stmt 0 view .LVU166 + 729 005a 8046 mov r8, r0 + 730 005c 0028 cmp r0, #0 + 731 005e EAD1 bne .L33 + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 732 .loc 1 828 7 is_stmt 1 view .LVU167 + 733 0060 0022 movs r2, #0 + 734 0062 3946 mov r1, r7 + 735 0064 2046 mov r0, r4 + 736 .LVL42: + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 737 .loc 1 828 7 is_stmt 0 view .LVU168 + 738 0066 FFF7FEFF bl QSPI_Config + 739 .LVL43: + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 740 .loc 1 830 7 is_stmt 1 view .LVU169 + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 741 .loc 1 830 14 is_stmt 0 view .LVU170 + ARM GAS /tmp/ccNpZKQO.s page 62 + + + 742 006a 7B6A ldr r3, [r7, #36] + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 743 .loc 1 830 10 view .LVU171 + 744 006c 1BB1 cbz r3, .L39 + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 745 .loc 1 847 9 is_stmt 1 view .LVU172 + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 746 .loc 1 847 22 is_stmt 0 view .LVU173 + 747 006e 0123 movs r3, #1 + 748 0070 84F84130 strb r3, [r4, #65] + 749 0074 DFE7 b .L33 + 750 .L39: + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 751 .loc 1 834 9 is_stmt 1 view .LVU174 + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 752 .loc 1 834 18 is_stmt 0 view .LVU175 + 753 0076 0096 str r6, [sp] + 754 0078 2B46 mov r3, r5 + 755 007a 0122 movs r2, #1 + 756 007c 0221 movs r1, #2 + 757 007e 2046 mov r0, r4 + 758 0080 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 759 .LVL44: + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 760 .loc 1 836 9 is_stmt 1 view .LVU176 + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 761 .loc 1 836 12 is_stmt 0 view .LVU177 + 762 0084 8046 mov r8, r0 + 763 0086 0028 cmp r0, #0 + 764 0088 D5D1 bne .L33 + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 765 .loc 1 838 11 is_stmt 1 view .LVU178 + 766 008a 2368 ldr r3, [r4] + 767 008c 0222 movs r2, #2 + 768 008e DA60 str r2, [r3, #12] + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 769 .loc 1 841 11 view .LVU179 + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 770 .loc 1 841 24 is_stmt 0 view .LVU180 + 771 0090 0123 movs r3, #1 + 772 0092 84F84130 strb r3, [r4, #65] + 773 0096 CEE7 b .L33 + 774 .LVL45: + 775 .L35: + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 776 .loc 1 813 3 view .LVU181 + 777 0098 4FF00208 mov r8, #2 + 778 009c CEE7 b .L32 + 779 .cfi_endproc + 780 .LFE146: + 782 .section .text.HAL_QSPI_Command_IT,"ax",%progbits + 783 .align 1 + 784 .global HAL_QSPI_Command_IT + 785 .syntax unified + 786 .thumb + 787 .thumb_func + 788 .fpu fpv5-d16 + ARM GAS /tmp/ccNpZKQO.s page 63 + + + 790 HAL_QSPI_Command_IT: + 791 .LVL46: + 792 .LFB147: + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 793 .loc 1 871 1 is_stmt 1 view -0 + 794 .cfi_startproc + 795 @ args = 0, pretend = 0, frame = 0 + 796 @ frame_needed = 0, uses_anonymous_args = 0 + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 797 .loc 1 871 1 is_stmt 0 view .LVU183 + 798 0000 70B5 push {r4, r5, r6, lr} + 799 .LCFI10: + 800 .cfi_def_cfa_offset 16 + 801 .cfi_offset 4, -16 + 802 .cfi_offset 5, -12 + 803 .cfi_offset 6, -8 + 804 .cfi_offset 14, -4 + 805 0002 82B0 sub sp, sp, #8 + 806 .LCFI11: + 807 .cfi_def_cfa_offset 24 + 808 0004 0446 mov r4, r0 + 809 0006 0D46 mov r5, r1 + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 810 .loc 1 872 3 is_stmt 1 view .LVU184 + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 811 .loc 1 873 3 view .LVU185 + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 812 .loc 1 873 24 is_stmt 0 view .LVU186 + 813 0008 FFF7FEFF bl HAL_GetTick + 814 .LVL47: + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 815 .loc 1 876 3 is_stmt 1 view .LVU187 + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 816 .loc 1 877 3 view .LVU188 + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 817 .loc 1 879 5 view .LVU189 + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 818 .loc 1 882 3 view .LVU190 + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 819 .loc 1 883 3 view .LVU191 + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 820 .loc 1 885 5 view .LVU192 + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 821 .loc 1 888 3 view .LVU193 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 822 .loc 1 889 3 view .LVU194 + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 823 .loc 1 891 5 view .LVU195 + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 824 .loc 1 894 3 view .LVU196 + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 825 .loc 1 895 3 view .LVU197 + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 826 .loc 1 897 3 view .LVU198 + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 827 .loc 1 898 3 view .LVU199 + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 64 + + + 828 .loc 1 899 3 view .LVU200 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 829 .loc 1 902 3 view .LVU201 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 830 .loc 1 902 3 view .LVU202 + 831 000c 94F84020 ldrb r2, [r4, #64] @ zero_extendqisi2 + 832 0010 D2B2 uxtb r2, r2 + 833 0012 012A cmp r2, #1 + 834 0014 3BD0 beq .L46 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 835 .loc 1 902 3 discriminator 2 view .LVU203 + 836 0016 0123 movs r3, #1 + 837 0018 84F84030 strb r3, [r4, #64] + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 838 .loc 1 902 3 discriminator 2 view .LVU204 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 839 .loc 1 904 3 discriminator 2 view .LVU205 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 840 .loc 1 904 11 is_stmt 0 discriminator 2 view .LVU206 + 841 001c 94F84120 ldrb r2, [r4, #65] @ zero_extendqisi2 + 842 0020 D2B2 uxtb r2, r2 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 843 .loc 1 904 5 discriminator 2 view .LVU207 + 844 0022 9A42 cmp r2, r3 + 845 0024 06D0 beq .L48 + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 846 .loc 1 952 5 is_stmt 1 view .LVU208 + 847 .LVL48: + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 848 .loc 1 955 5 view .LVU209 + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 849 .loc 1 955 5 view .LVU210 + 850 0026 0023 movs r3, #0 + 851 0028 84F84030 strb r3, [r4, #64] + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 852 .loc 1 952 12 is_stmt 0 view .LVU211 + 853 002c 0226 movs r6, #2 + 854 .LVL49: + 855 .L41: + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 856 .loc 1 960 1 view .LVU212 + 857 002e 3046 mov r0, r6 + 858 0030 02B0 add sp, sp, #8 + 859 .LCFI12: + 860 .cfi_remember_state + 861 .cfi_def_cfa_offset 16 + 862 @ sp needed + 863 0032 70BD pop {r4, r5, r6, pc} + 864 .LVL50: + 865 .L48: + 866 .LCFI13: + 867 .cfi_restore_state + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 868 .loc 1 906 5 is_stmt 1 view .LVU213 + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 869 .loc 1 906 22 is_stmt 0 view .LVU214 + 870 0034 0022 movs r2, #0 + ARM GAS /tmp/ccNpZKQO.s page 65 + + + 871 0036 6264 str r2, [r4, #68] + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 872 .loc 1 909 5 is_stmt 1 view .LVU215 + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 873 .loc 1 909 18 is_stmt 0 view .LVU216 + 874 0038 0223 movs r3, #2 + 875 003a 84F84130 strb r3, [r4, #65] + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 876 .loc 1 912 5 is_stmt 1 view .LVU217 + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 877 .loc 1 912 14 is_stmt 0 view .LVU218 + 878 003e A36C ldr r3, [r4, #72] + 879 0040 0093 str r3, [sp] + 880 0042 0346 mov r3, r0 + 881 0044 2021 movs r1, #32 + 882 0046 2046 mov r0, r4 + 883 .LVL51: + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 884 .loc 1 912 14 view .LVU219 + 885 0048 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 886 .LVL52: + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 887 .loc 1 914 5 is_stmt 1 view .LVU220 + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 888 .loc 1 914 8 is_stmt 0 view .LVU221 + 889 004c 0646 mov r6, r0 + 890 004e D0B9 cbnz r0, .L43 + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 891 .loc 1 916 7 is_stmt 1 view .LVU222 + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 892 .loc 1 916 14 is_stmt 0 view .LVU223 + 893 0050 6B6A ldr r3, [r5, #36] + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 894 .loc 1 916 10 view .LVU224 + 895 0052 13B9 cbnz r3, .L44 + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 896 .loc 1 919 9 is_stmt 1 view .LVU225 + 897 0054 2368 ldr r3, [r4] + 898 0056 0322 movs r2, #3 + 899 0058 DA60 str r2, [r3, #12] + 900 .L44: + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 901 .loc 1 923 7 view .LVU226 + 902 005a 0022 movs r2, #0 + 903 005c 2946 mov r1, r5 + 904 005e 2046 mov r0, r4 + 905 .LVL53: + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 906 .loc 1 923 7 is_stmt 0 view .LVU227 + 907 0060 FFF7FEFF bl QSPI_Config + 908 .LVL54: + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 909 .loc 1 925 7 is_stmt 1 view .LVU228 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 910 .loc 1 925 14 is_stmt 0 view .LVU229 + 911 0064 6B6A ldr r3, [r5, #36] + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 66 + + + 912 .loc 1 925 10 view .LVU230 + 913 0066 3BB9 cbnz r3, .L45 + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 914 .loc 1 930 9 is_stmt 1 view .LVU231 + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 915 .loc 1 930 9 view .LVU232 + 916 0068 84F84030 strb r3, [r4, #64] + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 917 .loc 1 930 9 view .LVU233 + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 918 .loc 1 933 9 view .LVU234 + 919 006c 2268 ldr r2, [r4] + 920 006e 1368 ldr r3, [r2] + 921 0070 43F44033 orr r3, r3, #196608 + 922 0074 1360 str r3, [r2] + 923 0076 DAE7 b .L41 + 924 .L45: + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 925 .loc 1 938 9 view .LVU235 + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 926 .loc 1 938 22 is_stmt 0 view .LVU236 + 927 0078 0123 movs r3, #1 + 928 007a 84F84130 strb r3, [r4, #65] + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 929 .loc 1 941 9 is_stmt 1 view .LVU237 + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 930 .loc 1 941 9 view .LVU238 + 931 007e 0023 movs r3, #0 + 932 0080 84F84030 strb r3, [r4, #64] + 933 0084 D3E7 b .L41 + 934 .LVL55: + 935 .L43: + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 936 .loc 1 947 7 discriminator 1 view .LVU239 + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 937 .loc 1 947 7 discriminator 1 view .LVU240 + 938 0086 0023 movs r3, #0 + 939 0088 84F84030 strb r3, [r4, #64] + 940 008c CFE7 b .L41 + 941 .LVL56: + 942 .L46: + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 943 .loc 1 902 3 is_stmt 0 view .LVU241 + 944 008e 0226 movs r6, #2 + 945 0090 CDE7 b .L41 + 946 .cfi_endproc + 947 .LFE147: + 949 .section .text.HAL_QSPI_Transmit,"ax",%progbits + 950 .align 1 + 951 .global HAL_QSPI_Transmit + 952 .syntax unified + 953 .thumb + 954 .thumb_func + 955 .fpu fpv5-d16 + 957 HAL_QSPI_Transmit: + 958 .LVL57: + 959 .LFB148: + ARM GAS /tmp/ccNpZKQO.s page 67 + + + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 960 .loc 1 972 1 is_stmt 1 view -0 + 961 .cfi_startproc + 962 @ args = 0, pretend = 0, frame = 0 + 963 @ frame_needed = 0, uses_anonymous_args = 0 + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 964 .loc 1 972 1 is_stmt 0 view .LVU243 + 965 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 966 .LCFI14: + 967 .cfi_def_cfa_offset 28 + 968 .cfi_offset 4, -28 + 969 .cfi_offset 5, -24 + 970 .cfi_offset 6, -20 + 971 .cfi_offset 7, -16 + 972 .cfi_offset 8, -12 + 973 .cfi_offset 9, -8 + 974 .cfi_offset 14, -4 + 975 0004 83B0 sub sp, sp, #12 + 976 .LCFI15: + 977 .cfi_def_cfa_offset 40 + 978 0006 0446 mov r4, r0 + 979 0008 8946 mov r9, r1 + 980 000a 1746 mov r7, r2 + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 981 .loc 1 973 3 is_stmt 1 view .LVU244 + 982 .LVL58: + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; + 983 .loc 1 974 3 view .LVU245 + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; + 984 .loc 1 974 24 is_stmt 0 view .LVU246 + 985 000c FFF7FEFF bl HAL_GetTick + 986 .LVL59: + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 987 .loc 1 975 3 is_stmt 1 view .LVU247 + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 988 .loc 1 975 35 is_stmt 0 view .LVU248 + 989 0010 D4F80080 ldr r8, [r4] + 990 .LVL60: + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 991 .loc 1 978 3 is_stmt 1 view .LVU249 + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 992 .loc 1 978 3 view .LVU250 + 993 0014 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 994 0018 DBB2 uxtb r3, r3 + 995 001a 012B cmp r3, #1 + 996 001c 57D0 beq .L57 + 997 001e 0646 mov r6, r0 + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 998 .loc 1 978 3 discriminator 2 view .LVU251 + 999 0020 0123 movs r3, #1 + 1000 0022 84F84030 strb r3, [r4, #64] + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1001 .loc 1 978 3 discriminator 2 view .LVU252 + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1002 .loc 1 980 3 discriminator 2 view .LVU253 + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1003 .loc 1 980 11 is_stmt 0 discriminator 2 view .LVU254 + ARM GAS /tmp/ccNpZKQO.s page 68 + + + 1004 0026 94F84150 ldrb r5, [r4, #65] @ zero_extendqisi2 + 1005 002a EDB2 uxtb r5, r5 + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1006 .loc 1 980 5 discriminator 2 view .LVU255 + 1007 002c 9D42 cmp r5, r3 + 1008 002e 07D0 beq .L60 +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1009 .loc 1 1036 12 view .LVU256 + 1010 0030 0225 movs r5, #2 + 1011 .LVL61: + 1012 .L51: +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1013 .loc 1 1040 3 is_stmt 1 view .LVU257 +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1014 .loc 1 1040 3 view .LVU258 + 1015 0032 0023 movs r3, #0 + 1016 0034 84F84030 strb r3, [r4, #64] +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1017 .loc 1 1040 3 view .LVU259 +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1018 .loc 1 1042 3 view .LVU260 + 1019 .LVL62: + 1020 .L50: +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1021 .loc 1 1043 1 is_stmt 0 view .LVU261 + 1022 0038 2846 mov r0, r5 + 1023 003a 03B0 add sp, sp, #12 + 1024 .LCFI16: + 1025 .cfi_remember_state + 1026 .cfi_def_cfa_offset 28 + 1027 @ sp needed + 1028 003c BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 1029 .LVL63: + 1030 .L60: + 1031 .LCFI17: + 1032 .cfi_restore_state + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1033 .loc 1 982 5 is_stmt 1 view .LVU262 + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1034 .loc 1 982 22 is_stmt 0 view .LVU263 + 1035 0040 0023 movs r3, #0 + 1036 0042 6364 str r3, [r4, #68] + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1037 .loc 1 984 5 is_stmt 1 view .LVU264 + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1038 .loc 1 984 7 is_stmt 0 view .LVU265 + 1039 0044 B9F1000F cmp r9, #0 + 1040 0048 3CD0 beq .L52 + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1041 .loc 1 987 7 is_stmt 1 view .LVU266 + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1042 .loc 1 987 20 is_stmt 0 view .LVU267 + 1043 004a 1223 movs r3, #18 + 1044 004c 84F84130 strb r3, [r4, #65] + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1045 .loc 1 990 7 is_stmt 1 view .LVU268 + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + ARM GAS /tmp/ccNpZKQO.s page 69 + + + 1046 .loc 1 990 28 is_stmt 0 view .LVU269 + 1047 0050 D8F81030 ldr r3, [r8, #16] + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1048 .loc 1 990 59 view .LVU270 + 1049 0054 0133 adds r3, r3, #1 + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1050 .loc 1 990 26 view .LVU271 + 1051 0056 E362 str r3, [r4, #44] + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1052 .loc 1 991 7 is_stmt 1 view .LVU272 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1053 .loc 1 991 27 is_stmt 0 view .LVU273 + 1054 0058 D8F81030 ldr r3, [r8, #16] + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1055 .loc 1 991 58 view .LVU274 + 1056 005c 0133 adds r3, r3, #1 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1057 .loc 1 991 25 view .LVU275 + 1058 005e A362 str r3, [r4, #40] + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1059 .loc 1 992 7 is_stmt 1 view .LVU276 + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1060 .loc 1 992 25 is_stmt 0 view .LVU277 + 1061 0060 C4F82490 str r9, [r4, #36] + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1062 .loc 1 995 7 is_stmt 1 view .LVU278 + 1063 0064 D8F81430 ldr r3, [r8, #20] + 1064 0068 23F04063 bic r3, r3, #201326592 + 1065 006c C8F81430 str r3, [r8, #20] + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1066 .loc 1 997 7 view .LVU279 + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 1067 .loc 1 973 21 is_stmt 0 view .LVU280 + 1068 0070 0025 movs r5, #0 + 1069 .LVL64: + 1070 .L53: + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1071 .loc 1 997 12 is_stmt 1 view .LVU281 + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1072 .loc 1 997 18 is_stmt 0 view .LVU282 + 1073 0072 E36A ldr r3, [r4, #44] + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1074 .loc 1 997 12 view .LVU283 + 1075 0074 9BB1 cbz r3, .L54 +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1076 .loc 1 1000 9 is_stmt 1 view .LVU284 +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1077 .loc 1 1000 18 is_stmt 0 view .LVU285 + 1078 0076 0097 str r7, [sp] + 1079 0078 3346 mov r3, r6 + 1080 007a 0122 movs r2, #1 + 1081 007c 0421 movs r1, #4 + 1082 007e 2046 mov r0, r4 + 1083 0080 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 1084 .LVL65: +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1085 .loc 1 1002 9 is_stmt 1 view .LVU286 + ARM GAS /tmp/ccNpZKQO.s page 70 + + +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1086 .loc 1 1002 12 is_stmt 0 view .LVU287 + 1087 0084 0546 mov r5, r0 + 1088 0086 50B9 cbnz r0, .L54 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 1089 .loc 1 1007 9 is_stmt 1 view .LVU288 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 1090 .loc 1 1007 45 is_stmt 0 view .LVU289 + 1091 0088 636A ldr r3, [r4, #36] +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 1092 .loc 1 1007 39 view .LVU290 + 1093 008a 1B78 ldrb r3, [r3] @ zero_extendqisi2 +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 1094 .loc 1 1007 37 view .LVU291 + 1095 008c 88F82030 strb r3, [r8, #32] +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 1096 .loc 1 1008 9 is_stmt 1 view .LVU292 +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 1097 .loc 1 1008 14 is_stmt 0 view .LVU293 + 1098 0090 616A ldr r1, [r4, #36] +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 1099 .loc 1 1008 26 view .LVU294 + 1100 0092 0131 adds r1, r1, #1 + 1101 0094 6162 str r1, [r4, #36] +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1102 .loc 1 1009 9 is_stmt 1 view .LVU295 +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1103 .loc 1 1009 14 is_stmt 0 view .LVU296 + 1104 0096 E16A ldr r1, [r4, #44] +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1105 .loc 1 1009 27 view .LVU297 + 1106 0098 0139 subs r1, r1, #1 + 1107 009a E162 str r1, [r4, #44] + 1108 009c E9E7 b .L53 + 1109 .LVL66: + 1110 .L54: +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1111 .loc 1 1012 7 is_stmt 1 view .LVU298 +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1112 .loc 1 1012 10 is_stmt 0 view .LVU299 + 1113 009e 1DB1 cbz r5, .L61 + 1114 .LVL67: + 1115 .L56: +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1116 .loc 1 1026 7 is_stmt 1 view .LVU300 +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1117 .loc 1 1026 20 is_stmt 0 view .LVU301 + 1118 00a0 0123 movs r3, #1 + 1119 00a2 84F84130 strb r3, [r4, #65] + 1120 00a6 C4E7 b .L51 + 1121 .L61: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1122 .loc 1 1015 9 is_stmt 1 view .LVU302 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1123 .loc 1 1015 18 is_stmt 0 view .LVU303 + 1124 00a8 0097 str r7, [sp] + 1125 00aa 3346 mov r3, r6 + ARM GAS /tmp/ccNpZKQO.s page 71 + + + 1126 00ac 0122 movs r2, #1 + 1127 00ae 0221 movs r1, #2 + 1128 00b0 2046 mov r0, r4 + 1129 00b2 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 1130 .LVL68: +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1131 .loc 1 1017 9 is_stmt 1 view .LVU304 +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1132 .loc 1 1017 12 is_stmt 0 view .LVU305 + 1133 00b6 0546 mov r5, r0 + 1134 00b8 0028 cmp r0, #0 + 1135 00ba F1D1 bne .L56 +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1136 .loc 1 1020 11 is_stmt 1 view .LVU306 + 1137 00bc 2368 ldr r3, [r4] + 1138 00be 0222 movs r2, #2 + 1139 00c0 DA60 str r2, [r3, #12] + 1140 00c2 EDE7 b .L56 + 1141 .LVL69: + 1142 .L52: +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1143 .loc 1 1030 7 view .LVU307 +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1144 .loc 1 1030 24 is_stmt 0 view .LVU308 + 1145 00c4 636C ldr r3, [r4, #68] + 1146 00c6 43F00803 orr r3, r3, #8 + 1147 00ca 6364 str r3, [r4, #68] +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1148 .loc 1 1031 7 is_stmt 1 view .LVU309 + 1149 .LVL70: +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1150 .loc 1 1031 7 is_stmt 0 view .LVU310 + 1151 00cc B1E7 b .L51 + 1152 .LVL71: + 1153 .L57: + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1154 .loc 1 978 3 view .LVU311 + 1155 00ce 0225 movs r5, #2 + 1156 00d0 B2E7 b .L50 + 1157 .cfi_endproc + 1158 .LFE148: + 1160 .section .text.HAL_QSPI_Receive,"ax",%progbits + 1161 .align 1 + 1162 .global HAL_QSPI_Receive + 1163 .syntax unified + 1164 .thumb + 1165 .thumb_func + 1166 .fpu fpv5-d16 + 1168 HAL_QSPI_Receive: + 1169 .LVL72: + 1170 .LFB149: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1171 .loc 1 1055 1 is_stmt 1 view -0 + 1172 .cfi_startproc + 1173 @ args = 0, pretend = 0, frame = 0 + 1174 @ frame_needed = 0, uses_anonymous_args = 0 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccNpZKQO.s page 72 + + + 1175 .loc 1 1055 1 is_stmt 0 view .LVU313 + 1176 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 1177 .LCFI18: + 1178 .cfi_def_cfa_offset 28 + 1179 .cfi_offset 4, -28 + 1180 .cfi_offset 5, -24 + 1181 .cfi_offset 6, -20 + 1182 .cfi_offset 7, -16 + 1183 .cfi_offset 8, -12 + 1184 .cfi_offset 9, -8 + 1185 .cfi_offset 14, -4 + 1186 0004 83B0 sub sp, sp, #12 + 1187 .LCFI19: + 1188 .cfi_def_cfa_offset 40 + 1189 0006 0446 mov r4, r0 + 1190 0008 8946 mov r9, r1 + 1191 000a 1746 mov r7, r2 +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 1192 .loc 1 1056 3 is_stmt 1 view .LVU314 + 1193 .LVL73: +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 1194 .loc 1 1057 3 view .LVU315 +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 1195 .loc 1 1057 24 is_stmt 0 view .LVU316 + 1196 000c FFF7FEFF bl HAL_GetTick + 1197 .LVL74: +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; + 1198 .loc 1 1058 3 is_stmt 1 view .LVU317 +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; + 1199 .loc 1 1058 23 is_stmt 0 view .LVU318 + 1200 0010 D4F80080 ldr r8, [r4] +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg = &hqspi->Instance->DR; + 1201 .loc 1 1058 12 view .LVU319 + 1202 0014 D8F81820 ldr r2, [r8, #24] + 1203 .LVL75: +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1204 .loc 1 1059 3 is_stmt 1 view .LVU320 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1205 .loc 1 1062 3 view .LVU321 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1206 .loc 1 1062 3 view .LVU322 + 1207 0018 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 1208 001c DBB2 uxtb r3, r3 + 1209 001e 012B cmp r3, #1 + 1210 0020 5BD0 beq .L70 + 1211 0022 0646 mov r6, r0 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1212 .loc 1 1062 3 discriminator 2 view .LVU323 + 1213 0024 0123 movs r3, #1 + 1214 0026 84F84030 strb r3, [r4, #64] +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1215 .loc 1 1062 3 discriminator 2 view .LVU324 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1216 .loc 1 1064 3 discriminator 2 view .LVU325 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1217 .loc 1 1064 11 is_stmt 0 discriminator 2 view .LVU326 + 1218 002a 94F84150 ldrb r5, [r4, #65] @ zero_extendqisi2 + ARM GAS /tmp/ccNpZKQO.s page 73 + + + 1219 002e EDB2 uxtb r5, r5 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1220 .loc 1 1064 5 discriminator 2 view .LVU327 + 1221 0030 9D42 cmp r5, r3 + 1222 0032 07D0 beq .L73 +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1223 .loc 1 1123 12 view .LVU328 + 1224 0034 0225 movs r5, #2 + 1225 .LVL76: + 1226 .L64: +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1227 .loc 1 1127 3 is_stmt 1 view .LVU329 +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1228 .loc 1 1127 3 view .LVU330 + 1229 0036 0023 movs r3, #0 + 1230 0038 84F84030 strb r3, [r4, #64] +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1231 .loc 1 1127 3 view .LVU331 +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1232 .loc 1 1129 3 view .LVU332 + 1233 .LVL77: + 1234 .L63: +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1235 .loc 1 1130 1 is_stmt 0 view .LVU333 + 1236 003c 2846 mov r0, r5 + 1237 003e 03B0 add sp, sp, #12 + 1238 .LCFI20: + 1239 .cfi_remember_state + 1240 .cfi_def_cfa_offset 28 + 1241 @ sp needed + 1242 0040 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 1243 .LVL78: + 1244 .L73: + 1245 .LCFI21: + 1246 .cfi_restore_state +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1247 .loc 1 1066 5 is_stmt 1 view .LVU334 +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1248 .loc 1 1066 22 is_stmt 0 view .LVU335 + 1249 0044 0023 movs r3, #0 + 1250 0046 6364 str r3, [r4, #68] +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1251 .loc 1 1068 5 is_stmt 1 view .LVU336 +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1252 .loc 1 1068 7 is_stmt 0 view .LVU337 + 1253 0048 B9F1000F cmp r9, #0 + 1254 004c 40D0 beq .L65 +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1255 .loc 1 1071 7 is_stmt 1 view .LVU338 +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1256 .loc 1 1071 20 is_stmt 0 view .LVU339 + 1257 004e 2223 movs r3, #34 + 1258 0050 84F84130 strb r3, [r4, #65] +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1259 .loc 1 1074 7 is_stmt 1 view .LVU340 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1260 .loc 1 1074 28 is_stmt 0 view .LVU341 + ARM GAS /tmp/ccNpZKQO.s page 74 + + + 1261 0054 D8F81030 ldr r3, [r8, #16] +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1262 .loc 1 1074 59 view .LVU342 + 1263 0058 0133 adds r3, r3, #1 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1264 .loc 1 1074 26 view .LVU343 + 1265 005a A363 str r3, [r4, #56] +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1266 .loc 1 1075 7 is_stmt 1 view .LVU344 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1267 .loc 1 1075 27 is_stmt 0 view .LVU345 + 1268 005c D8F81030 ldr r3, [r8, #16] +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1269 .loc 1 1075 58 view .LVU346 + 1270 0060 0133 adds r3, r3, #1 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1271 .loc 1 1075 25 view .LVU347 + 1272 0062 6363 str r3, [r4, #52] +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1273 .loc 1 1076 7 is_stmt 1 view .LVU348 +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1274 .loc 1 1076 25 is_stmt 0 view .LVU349 + 1275 0064 C4F83090 str r9, [r4, #48] +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1276 .loc 1 1079 7 is_stmt 1 view .LVU350 + 1277 0068 D8F81430 ldr r3, [r8, #20] + 1278 006c 23F04063 bic r3, r3, #201326592 + 1279 0070 43F08063 orr r3, r3, #67108864 + 1280 0074 C8F81430 str r3, [r8, #20] +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1281 .loc 1 1082 7 view .LVU351 + 1282 0078 2368 ldr r3, [r4] + 1283 007a 9A61 str r2, [r3, #24] +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1284 .loc 1 1084 7 view .LVU352 +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 1285 .loc 1 1056 21 is_stmt 0 view .LVU353 + 1286 007c 0025 movs r5, #0 + 1287 .LVL79: + 1288 .L66: +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1289 .loc 1 1084 12 is_stmt 1 view .LVU354 +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1290 .loc 1 1084 18 is_stmt 0 view .LVU355 + 1291 007e A36B ldr r3, [r4, #56] +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1292 .loc 1 1084 12 view .LVU356 + 1293 0080 9BB1 cbz r3, .L67 +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1294 .loc 1 1087 9 is_stmt 1 view .LVU357 +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1295 .loc 1 1087 18 is_stmt 0 view .LVU358 + 1296 0082 0097 str r7, [sp] + 1297 0084 3346 mov r3, r6 + 1298 0086 0122 movs r2, #1 + 1299 0088 0621 movs r1, #6 + 1300 008a 2046 mov r0, r4 + ARM GAS /tmp/ccNpZKQO.s page 75 + + + 1301 008c FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 1302 .LVL80: +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1303 .loc 1 1089 9 is_stmt 1 view .LVU359 +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1304 .loc 1 1089 13 is_stmt 0 view .LVU360 + 1305 0090 0546 mov r5, r0 + 1306 0092 50B9 cbnz r0, .L67 +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 1307 .loc 1 1094 9 is_stmt 1 view .LVU361 +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 1308 .loc 1 1094 15 is_stmt 0 view .LVU362 + 1309 0094 236B ldr r3, [r4, #48] +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 1310 .loc 1 1094 30 view .LVU363 + 1311 0096 98F82020 ldrb r2, [r8, #32] @ zero_extendqisi2 +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 1312 .loc 1 1094 28 view .LVU364 + 1313 009a 1A70 strb r2, [r3] +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 1314 .loc 1 1095 9 is_stmt 1 view .LVU365 +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 1315 .loc 1 1095 14 is_stmt 0 view .LVU366 + 1316 009c 216B ldr r1, [r4, #48] +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 1317 .loc 1 1095 26 view .LVU367 + 1318 009e 0131 adds r1, r1, #1 + 1319 00a0 2163 str r1, [r4, #48] +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1320 .loc 1 1096 9 is_stmt 1 view .LVU368 +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1321 .loc 1 1096 14 is_stmt 0 view .LVU369 + 1322 00a2 A16B ldr r1, [r4, #56] +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1323 .loc 1 1096 27 view .LVU370 + 1324 00a4 0139 subs r1, r1, #1 + 1325 00a6 A163 str r1, [r4, #56] + 1326 00a8 E9E7 b .L66 + 1327 .LVL81: + 1328 .L67: +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1329 .loc 1 1099 7 is_stmt 1 view .LVU371 +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1330 .loc 1 1099 10 is_stmt 0 view .LVU372 + 1331 00aa 1DB1 cbz r5, .L74 + 1332 .LVL82: + 1333 .L69: +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1334 .loc 1 1113 7 is_stmt 1 view .LVU373 +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1335 .loc 1 1113 20 is_stmt 0 view .LVU374 + 1336 00ac 0123 movs r3, #1 + 1337 00ae 84F84130 strb r3, [r4, #65] + 1338 00b2 C0E7 b .L64 + 1339 .L74: +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1340 .loc 1 1102 9 is_stmt 1 view .LVU375 + ARM GAS /tmp/ccNpZKQO.s page 76 + + +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1341 .loc 1 1102 18 is_stmt 0 view .LVU376 + 1342 00b4 0097 str r7, [sp] + 1343 00b6 3346 mov r3, r6 + 1344 00b8 0122 movs r2, #1 + 1345 00ba 0221 movs r1, #2 + 1346 00bc 2046 mov r0, r4 + 1347 00be FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 1348 .LVL83: +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1349 .loc 1 1104 9 is_stmt 1 view .LVU377 +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1350 .loc 1 1104 13 is_stmt 0 view .LVU378 + 1351 00c2 0546 mov r5, r0 + 1352 00c4 0028 cmp r0, #0 + 1353 00c6 F1D1 bne .L69 +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1354 .loc 1 1107 11 is_stmt 1 view .LVU379 + 1355 00c8 2368 ldr r3, [r4] + 1356 00ca 0222 movs r2, #2 + 1357 00cc DA60 str r2, [r3, #12] + 1358 00ce EDE7 b .L69 + 1359 .LVL84: + 1360 .L65: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1361 .loc 1 1117 7 view .LVU380 +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1362 .loc 1 1117 24 is_stmt 0 view .LVU381 + 1363 00d0 636C ldr r3, [r4, #68] + 1364 00d2 43F00803 orr r3, r3, #8 + 1365 00d6 6364 str r3, [r4, #68] +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1366 .loc 1 1118 7 is_stmt 1 view .LVU382 + 1367 .LVL85: +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1368 .loc 1 1118 7 is_stmt 0 view .LVU383 + 1369 00d8 ADE7 b .L64 + 1370 .LVL86: + 1371 .L70: +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1372 .loc 1 1062 3 view .LVU384 + 1373 00da 0225 movs r5, #2 + 1374 00dc AEE7 b .L63 + 1375 .cfi_endproc + 1376 .LFE149: + 1378 .section .text.HAL_QSPI_Transmit_IT,"ax",%progbits + 1379 .align 1 + 1380 .global HAL_QSPI_Transmit_IT + 1381 .syntax unified + 1382 .thumb + 1383 .thumb_func + 1384 .fpu fpv5-d16 + 1386 HAL_QSPI_Transmit_IT: + 1387 .LVL87: + 1388 .LFB150: +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1389 .loc 1 1140 1 is_stmt 1 view -0 + ARM GAS /tmp/ccNpZKQO.s page 77 + + + 1390 .cfi_startproc + 1391 @ args = 0, pretend = 0, frame = 0 + 1392 @ frame_needed = 0, uses_anonymous_args = 0 + 1393 @ link register save eliminated. +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1394 .loc 1 1140 1 is_stmt 0 view .LVU386 + 1395 0000 0346 mov r3, r0 +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1396 .loc 1 1141 3 is_stmt 1 view .LVU387 + 1397 .LVL88: +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1398 .loc 1 1144 3 view .LVU388 +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1399 .loc 1 1144 3 view .LVU389 + 1400 0002 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 1401 0006 D2B2 uxtb r2, r2 + 1402 0008 012A cmp r2, #1 + 1403 000a 32D0 beq .L79 +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1404 .loc 1 1144 3 discriminator 2 view .LVU390 + 1405 000c 0122 movs r2, #1 + 1406 000e 80F84020 strb r2, [r0, #64] +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1407 .loc 1 1144 3 discriminator 2 view .LVU391 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1408 .loc 1 1146 3 discriminator 2 view .LVU392 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1409 .loc 1 1146 11 is_stmt 0 discriminator 2 view .LVU393 + 1410 0012 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 1411 .LVL89: +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1412 .loc 1 1146 11 discriminator 2 view .LVU394 + 1413 0016 C0B2 uxtb r0, r0 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1414 .loc 1 1146 5 discriminator 2 view .LVU395 + 1415 0018 9042 cmp r0, r2 + 1416 001a 04D0 beq .L80 +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1417 .loc 1 1183 5 is_stmt 1 view .LVU396 + 1418 .LVL90: +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1419 .loc 1 1186 5 view .LVU397 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1420 .loc 1 1186 5 view .LVU398 + 1421 001c 0022 movs r2, #0 + 1422 001e 83F84020 strb r2, [r3, #64] +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1423 .loc 1 1183 12 is_stmt 0 view .LVU399 + 1424 0022 0220 movs r0, #2 + 1425 0024 7047 bx lr + 1426 .LVL91: + 1427 .L80: +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1428 .loc 1 1148 5 is_stmt 1 view .LVU400 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1429 .loc 1 1148 22 is_stmt 0 view .LVU401 + 1430 0026 0022 movs r2, #0 + ARM GAS /tmp/ccNpZKQO.s page 78 + + + 1431 0028 5A64 str r2, [r3, #68] +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1432 .loc 1 1150 5 is_stmt 1 view .LVU402 +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1433 .loc 1 1150 7 is_stmt 0 view .LVU403 + 1434 002a D1B1 cbz r1, .L78 +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1435 .loc 1 1153 7 is_stmt 1 view .LVU404 +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1436 .loc 1 1153 20 is_stmt 0 view .LVU405 + 1437 002c 1222 movs r2, #18 + 1438 002e 83F84120 strb r2, [r3, #65] +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1439 .loc 1 1156 7 is_stmt 1 view .LVU406 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1440 .loc 1 1156 28 is_stmt 0 view .LVU407 + 1441 0032 1A68 ldr r2, [r3] + 1442 0034 1069 ldr r0, [r2, #16] +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1443 .loc 1 1156 59 view .LVU408 + 1444 0036 0130 adds r0, r0, #1 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1445 .loc 1 1156 26 view .LVU409 + 1446 0038 D862 str r0, [r3, #44] +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1447 .loc 1 1157 7 is_stmt 1 view .LVU410 +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1448 .loc 1 1157 27 is_stmt 0 view .LVU411 + 1449 003a 1069 ldr r0, [r2, #16] +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1450 .loc 1 1157 58 view .LVU412 + 1451 003c 0130 adds r0, r0, #1 +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1452 .loc 1 1157 25 view .LVU413 + 1453 003e 9862 str r0, [r3, #40] +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1454 .loc 1 1158 7 is_stmt 1 view .LVU414 +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1455 .loc 1 1158 25 is_stmt 0 view .LVU415 + 1456 0040 5962 str r1, [r3, #36] +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1457 .loc 1 1161 7 is_stmt 1 view .LVU416 + 1458 0042 0321 movs r1, #3 + 1459 .LVL92: +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1460 .loc 1 1161 7 is_stmt 0 view .LVU417 + 1461 0044 D160 str r1, [r2, #12] + 1462 .LVL93: +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1463 .loc 1 1164 7 is_stmt 1 view .LVU418 + 1464 0046 1968 ldr r1, [r3] + 1465 0048 4A69 ldr r2, [r1, #20] + 1466 004a 22F04062 bic r2, r2, #201326592 + 1467 004e 4A61 str r2, [r1, #20] +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1468 .loc 1 1167 7 view .LVU419 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 79 + + + 1469 .loc 1 1167 7 view .LVU420 + 1470 0050 0020 movs r0, #0 + 1471 0052 83F84000 strb r0, [r3, #64] +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1472 .loc 1 1167 7 view .LVU421 +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1473 .loc 1 1170 7 view .LVU422 + 1474 0056 1A68 ldr r2, [r3] + 1475 0058 1368 ldr r3, [r2] + 1476 .LVL94: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1477 .loc 1 1170 7 is_stmt 0 view .LVU423 + 1478 005a 43F4E023 orr r3, r3, #458752 + 1479 005e 1360 str r3, [r2] + 1480 0060 7047 bx lr + 1481 .LVL95: + 1482 .L78: +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1483 .loc 1 1174 7 is_stmt 1 view .LVU424 +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1484 .loc 1 1174 24 is_stmt 0 view .LVU425 + 1485 0062 5A6C ldr r2, [r3, #68] + 1486 0064 42F00802 orr r2, r2, #8 + 1487 0068 5A64 str r2, [r3, #68] +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1488 .loc 1 1175 7 is_stmt 1 view .LVU426 + 1489 .LVL96: +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1490 .loc 1 1178 7 view .LVU427 +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1491 .loc 1 1178 7 view .LVU428 + 1492 006a 0022 movs r2, #0 + 1493 006c 83F84020 strb r2, [r3, #64] + 1494 0070 7047 bx lr + 1495 .LVL97: + 1496 .L79: +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1497 .loc 1 1144 3 is_stmt 0 view .LVU429 + 1498 0072 0220 movs r0, #2 + 1499 .LVL98: +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1500 .loc 1 1190 1 view .LVU430 + 1501 0074 7047 bx lr + 1502 .cfi_endproc + 1503 .LFE150: + 1505 .section .text.HAL_QSPI_Receive_IT,"ax",%progbits + 1506 .align 1 + 1507 .global HAL_QSPI_Receive_IT + 1508 .syntax unified + 1509 .thumb + 1510 .thumb_func + 1511 .fpu fpv5-d16 + 1513 HAL_QSPI_Receive_IT: + 1514 .LVL99: + 1515 .LFB151: +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1516 .loc 1 1200 1 is_stmt 1 view -0 + ARM GAS /tmp/ccNpZKQO.s page 80 + + + 1517 .cfi_startproc + 1518 @ args = 0, pretend = 0, frame = 0 + 1519 @ frame_needed = 0, uses_anonymous_args = 0 + 1520 @ link register save eliminated. +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1521 .loc 1 1200 1 is_stmt 0 view .LVU432 + 1522 0000 30B4 push {r4, r5} + 1523 .LCFI22: + 1524 .cfi_def_cfa_offset 8 + 1525 .cfi_offset 4, -8 + 1526 .cfi_offset 5, -4 +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 1527 .loc 1 1201 3 is_stmt 1 view .LVU433 + 1528 .LVL100: +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1529 .loc 1 1202 3 view .LVU434 +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1530 .loc 1 1202 23 is_stmt 0 view .LVU435 + 1531 0002 0468 ldr r4, [r0] +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1532 .loc 1 1202 12 view .LVU436 + 1533 0004 A569 ldr r5, [r4, #24] + 1534 .LVL101: +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1535 .loc 1 1205 3 is_stmt 1 view .LVU437 +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1536 .loc 1 1205 3 view .LVU438 + 1537 0006 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 1538 000a D2B2 uxtb r2, r2 + 1539 000c 012A cmp r2, #1 + 1540 000e 37D0 beq .L85 + 1541 0010 0346 mov r3, r0 +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1542 .loc 1 1205 3 discriminator 2 view .LVU439 + 1543 0012 0122 movs r2, #1 + 1544 0014 80F84020 strb r2, [r0, #64] +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1545 .loc 1 1205 3 discriminator 2 view .LVU440 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1546 .loc 1 1207 3 discriminator 2 view .LVU441 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1547 .loc 1 1207 11 is_stmt 0 discriminator 2 view .LVU442 + 1548 0018 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 1549 .LVL102: +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1550 .loc 1 1207 11 discriminator 2 view .LVU443 + 1551 001c C0B2 uxtb r0, r0 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1552 .loc 1 1207 5 discriminator 2 view .LVU444 + 1553 001e 9042 cmp r0, r2 + 1554 0020 05D0 beq .L87 +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1555 .loc 1 1247 5 is_stmt 1 view .LVU445 + 1556 .LVL103: +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1557 .loc 1 1250 5 view .LVU446 +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 81 + + + 1558 .loc 1 1250 5 view .LVU447 + 1559 0022 0022 movs r2, #0 + 1560 0024 83F84020 strb r2, [r3, #64] +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1561 .loc 1 1247 12 is_stmt 0 view .LVU448 + 1562 0028 0220 movs r0, #2 + 1563 .LVL104: + 1564 .L82: +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1565 .loc 1 1254 1 view .LVU449 + 1566 002a 30BC pop {r4, r5} + 1567 .LCFI23: + 1568 .cfi_remember_state + 1569 .cfi_restore 5 + 1570 .cfi_restore 4 + 1571 .cfi_def_cfa_offset 0 + 1572 .LVL105: +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1573 .loc 1 1254 1 view .LVU450 + 1574 002c 7047 bx lr + 1575 .LVL106: + 1576 .L87: + 1577 .LCFI24: + 1578 .cfi_restore_state +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1579 .loc 1 1209 5 is_stmt 1 view .LVU451 +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1580 .loc 1 1209 22 is_stmt 0 view .LVU452 + 1581 002e 0022 movs r2, #0 + 1582 0030 5A64 str r2, [r3, #68] +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1583 .loc 1 1211 5 is_stmt 1 view .LVU453 +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1584 .loc 1 1211 7 is_stmt 0 view .LVU454 + 1585 0032 E9B1 cbz r1, .L84 +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1586 .loc 1 1214 7 is_stmt 1 view .LVU455 +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1587 .loc 1 1214 20 is_stmt 0 view .LVU456 + 1588 0034 2222 movs r2, #34 + 1589 0036 83F84120 strb r2, [r3, #65] +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1590 .loc 1 1217 7 is_stmt 1 view .LVU457 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1591 .loc 1 1217 28 is_stmt 0 view .LVU458 + 1592 003a 2269 ldr r2, [r4, #16] +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1593 .loc 1 1217 59 view .LVU459 + 1594 003c 0132 adds r2, r2, #1 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + 1595 .loc 1 1217 26 view .LVU460 + 1596 003e 9A63 str r2, [r3, #56] +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1597 .loc 1 1218 7 is_stmt 1 view .LVU461 +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1598 .loc 1 1218 27 is_stmt 0 view .LVU462 + 1599 0040 2269 ldr r2, [r4, #16] + ARM GAS /tmp/ccNpZKQO.s page 82 + + +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1600 .loc 1 1218 58 view .LVU463 + 1601 0042 0132 adds r2, r2, #1 +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 1602 .loc 1 1218 25 view .LVU464 + 1603 0044 5A63 str r2, [r3, #52] +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1604 .loc 1 1219 7 is_stmt 1 view .LVU465 +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1605 .loc 1 1219 25 is_stmt 0 view .LVU466 + 1606 0046 1963 str r1, [r3, #48] +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1607 .loc 1 1222 7 is_stmt 1 view .LVU467 + 1608 0048 0322 movs r2, #3 + 1609 004a E260 str r2, [r4, #12] +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1610 .loc 1 1225 7 view .LVU468 + 1611 004c 1968 ldr r1, [r3] + 1612 .LVL107: +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1613 .loc 1 1225 7 is_stmt 0 view .LVU469 + 1614 004e 4A69 ldr r2, [r1, #20] + 1615 0050 22F04062 bic r2, r2, #201326592 + 1616 0054 42F08062 orr r2, r2, #67108864 + 1617 0058 4A61 str r2, [r1, #20] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1618 .loc 1 1228 7 is_stmt 1 view .LVU470 + 1619 005a 1A68 ldr r2, [r3] + 1620 005c 9561 str r5, [r2, #24] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1621 .loc 1 1231 7 view .LVU471 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1622 .loc 1 1231 7 view .LVU472 + 1623 005e 0020 movs r0, #0 + 1624 0060 83F84000 strb r0, [r3, #64] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1625 .loc 1 1231 7 view .LVU473 +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1626 .loc 1 1234 7 view .LVU474 + 1627 0064 1A68 ldr r2, [r3] + 1628 0066 1368 ldr r3, [r2] + 1629 .LVL108: +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1630 .loc 1 1234 7 is_stmt 0 view .LVU475 + 1631 0068 43F4E023 orr r3, r3, #458752 + 1632 006c 1360 str r3, [r2] + 1633 006e DCE7 b .L82 + 1634 .LVL109: + 1635 .L84: +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1636 .loc 1 1238 7 is_stmt 1 view .LVU476 +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1637 .loc 1 1238 24 is_stmt 0 view .LVU477 + 1638 0070 5A6C ldr r2, [r3, #68] + 1639 0072 42F00802 orr r2, r2, #8 + 1640 0076 5A64 str r2, [r3, #68] +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 83 + + + 1641 .loc 1 1239 7 is_stmt 1 view .LVU478 + 1642 .LVL110: +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1643 .loc 1 1242 7 view .LVU479 +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1644 .loc 1 1242 7 view .LVU480 + 1645 0078 0022 movs r2, #0 + 1646 007a 83F84020 strb r2, [r3, #64] + 1647 007e D4E7 b .L82 + 1648 .LVL111: + 1649 .L85: +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1650 .loc 1 1205 3 is_stmt 0 view .LVU481 + 1651 0080 0220 movs r0, #2 + 1652 .LVL112: +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1653 .loc 1 1205 3 view .LVU482 + 1654 0082 D2E7 b .L82 + 1655 .cfi_endproc + 1656 .LFE151: + 1658 .section .text.HAL_QSPI_Transmit_DMA,"ax",%progbits + 1659 .align 1 + 1660 .global HAL_QSPI_Transmit_DMA + 1661 .syntax unified + 1662 .thumb + 1663 .thumb_func + 1664 .fpu fpv5-d16 + 1666 HAL_QSPI_Transmit_DMA: + 1667 .LVL113: + 1668 .LFB152: +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1669 .loc 1 1264 1 is_stmt 1 view -0 + 1670 .cfi_startproc + 1671 @ args = 0, pretend = 0, frame = 0 + 1672 @ frame_needed = 0, uses_anonymous_args = 0 +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1673 .loc 1 1264 1 is_stmt 0 view .LVU484 + 1674 0000 70B5 push {r4, r5, r6, lr} + 1675 .LCFI25: + 1676 .cfi_def_cfa_offset 16 + 1677 .cfi_offset 4, -16 + 1678 .cfi_offset 5, -12 + 1679 .cfi_offset 6, -8 + 1680 .cfi_offset 14, -4 + 1681 0002 82B0 sub sp, sp, #8 + 1682 .LCFI26: + 1683 .cfi_def_cfa_offset 24 + 1684 0004 0446 mov r4, r0 +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1685 .loc 1 1265 3 is_stmt 1 view .LVU485 + 1686 .LVL114: +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1687 .loc 1 1266 3 view .LVU486 +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1688 .loc 1 1266 25 is_stmt 0 view .LVU487 + 1689 0006 0068 ldr r0, [r0] + 1690 .LVL115: + ARM GAS /tmp/ccNpZKQO.s page 84 + + +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1691 .loc 1 1266 25 view .LVU488 + 1692 0008 0269 ldr r2, [r0, #16] + 1693 .LVL116: +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1694 .loc 1 1269 3 is_stmt 1 view .LVU489 +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1695 .loc 1 1269 3 view .LVU490 + 1696 000a 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 1697 000e DBB2 uxtb r3, r3 + 1698 0010 012B cmp r3, #1 + 1699 0012 00F08680 beq .L97 + 1700 0016 0132 adds r2, r2, #1 + 1701 .LVL117: +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1702 .loc 1 1269 3 discriminator 2 view .LVU491 + 1703 0018 0123 movs r3, #1 + 1704 001a 84F84030 strb r3, [r4, #64] +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1705 .loc 1 1269 3 discriminator 2 view .LVU492 +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1706 .loc 1 1271 3 discriminator 2 view .LVU493 +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1707 .loc 1 1271 11 is_stmt 0 discriminator 2 view .LVU494 + 1708 001e 94F84150 ldrb r5, [r4, #65] @ zero_extendqisi2 + 1709 0022 EDB2 uxtb r5, r5 +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1710 .loc 1 1271 5 discriminator 2 view .LVU495 + 1711 0024 9D42 cmp r5, r3 + 1712 0026 06D0 beq .L99 +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1713 .loc 1 1359 5 is_stmt 1 view .LVU496 + 1714 .LVL118: +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1715 .loc 1 1362 5 view .LVU497 +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1716 .loc 1 1362 5 view .LVU498 + 1717 0028 0023 movs r3, #0 + 1718 002a 84F84030 strb r3, [r4, #64] +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1719 .loc 1 1359 12 is_stmt 0 view .LVU499 + 1720 002e 0225 movs r5, #2 + 1721 .LVL119: + 1722 .L89: +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1723 .loc 1 1366 1 view .LVU500 + 1724 0030 2846 mov r0, r5 + 1725 0032 02B0 add sp, sp, #8 + 1726 .LCFI27: + 1727 .cfi_remember_state + 1728 .cfi_def_cfa_offset 16 + 1729 @ sp needed + 1730 0034 70BD pop {r4, r5, r6, pc} + 1731 .LVL120: + 1732 .L99: + 1733 .LCFI28: + 1734 .cfi_restore_state + ARM GAS /tmp/ccNpZKQO.s page 85 + + +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1735 .loc 1 1274 5 is_stmt 1 view .LVU501 +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1736 .loc 1 1274 22 is_stmt 0 view .LVU502 + 1737 0036 0023 movs r3, #0 + 1738 0038 6364 str r3, [r4, #68] +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1739 .loc 1 1276 5 is_stmt 1 view .LVU503 +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1740 .loc 1 1276 7 is_stmt 0 view .LVU504 + 1741 003a 0029 cmp r1, #0 + 1742 003c 69D0 beq .L91 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1743 .loc 1 1279 7 is_stmt 1 view .LVU505 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1744 .loc 1 1279 26 is_stmt 0 view .LVU506 + 1745 003e E262 str r2, [r4, #44] +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1746 .loc 1 1282 9 is_stmt 1 view .LVU507 +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1747 .loc 1 1282 22 is_stmt 0 view .LVU508 + 1748 0040 1223 movs r3, #18 + 1749 0042 84F84130 strb r3, [r4, #65] +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1750 .loc 1 1285 9 is_stmt 1 view .LVU509 + 1751 0046 0323 movs r3, #3 + 1752 0048 C360 str r3, [r0, #12] +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1753 .loc 1 1288 9 view .LVU510 +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1754 .loc 1 1288 34 is_stmt 0 view .LVU511 + 1755 004a E36A ldr r3, [r4, #44] +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr = pData; + 1756 .loc 1 1288 27 view .LVU512 + 1757 004c A362 str r3, [r4, #40] +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1758 .loc 1 1289 9 is_stmt 1 view .LVU513 +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1759 .loc 1 1289 27 is_stmt 0 view .LVU514 + 1760 004e 6162 str r1, [r4, #36] +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1761 .loc 1 1292 9 is_stmt 1 view .LVU515 + 1762 0050 2268 ldr r2, [r4] + 1763 .LVL121: +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1764 .loc 1 1292 9 is_stmt 0 view .LVU516 + 1765 0052 5369 ldr r3, [r2, #20] + 1766 0054 23F04063 bic r3, r3, #201326592 + 1767 0058 5361 str r3, [r2, #20] +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1768 .loc 1 1295 9 is_stmt 1 view .LVU517 +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1769 .loc 1 1295 14 is_stmt 0 view .LVU518 + 1770 005a E36B ldr r3, [r4, #60] +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1771 .loc 1 1295 40 view .LVU519 + 1772 005c 324A ldr r2, .L102 + ARM GAS /tmp/ccNpZKQO.s page 86 + + + 1773 005e 5A64 str r2, [r3, #68] +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1774 .loc 1 1298 9 is_stmt 1 view .LVU520 +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1775 .loc 1 1298 14 is_stmt 0 view .LVU521 + 1776 0060 E36B ldr r3, [r4, #60] +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1777 .loc 1 1298 41 view .LVU522 + 1778 0062 324A ldr r2, .L102+4 + 1779 0064 5A65 str r2, [r3, #84] +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1780 .loc 1 1301 9 is_stmt 1 view .LVU523 +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1781 .loc 1 1301 14 is_stmt 0 view .LVU524 + 1782 0066 E36B ldr r3, [r4, #60] +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1783 .loc 1 1301 41 view .LVU525 + 1784 0068 0022 movs r2, #0 + 1785 006a 9A65 str r2, [r3, #88] +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1786 .loc 1 1304 9 is_stmt 1 view .LVU526 + 1787 006c E36B ldr r3, [r4, #60] + 1788 006e 1A68 ldr r2, [r3] + 1789 0070 1069 ldr r0, [r2, #16] + 1790 0072 2F4B ldr r3, .L102+8 + 1791 0074 0340 ands r3, r3, r0 + 1792 0076 1361 str r3, [r2, #16] +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1793 .loc 1 1307 9 view .LVU527 +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1794 .loc 1 1307 18 is_stmt 0 view .LVU528 + 1795 0078 E26B ldr r2, [r4, #60] +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1796 .loc 1 1307 31 view .LVU529 + 1797 007a D369 ldr r3, [r2, #28] +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1798 .loc 1 1307 12 view .LVU530 + 1799 007c 03BB cbnz r3, .L92 +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1800 .loc 1 1309 11 is_stmt 1 view .LVU531 + 1801 007e 1268 ldr r2, [r2] + 1802 0080 1069 ldr r0, [r2, #16] + 1803 0082 A3F54173 sub r3, r3, #772 + 1804 0086 0340 ands r3, r3, r0 + 1805 0088 43F00203 orr r3, r3, #2 + 1806 008c 1361 str r3, [r2, #16] +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1807 .loc 1 1265 21 is_stmt 0 view .LVU532 + 1808 008e 0026 movs r6, #0 + 1809 .LVL122: + 1810 .L93: +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1811 .loc 1 1327 9 is_stmt 1 view .LVU533 +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1812 .loc 1 1327 78 is_stmt 0 view .LVU534 + 1813 0090 2268 ldr r2, [r4] +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 87 + + + 1814 .loc 1 1327 13 view .LVU535 + 1815 0092 A36A ldr r3, [r4, #40] + 1816 0094 0120 movs r0, #1 + 1817 0096 0090 str r0, [sp] + 1818 0098 2032 adds r2, r2, #32 + 1819 009a E06B ldr r0, [r4, #60] + 1820 009c FFF7FEFF bl HAL_MDMA_Start_IT + 1821 .LVL123: +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1822 .loc 1 1327 12 view .LVU536 + 1823 00a0 60BB cbnz r0, .L96 +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1824 .loc 1 1330 11 is_stmt 1 view .LVU537 +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1825 .loc 1 1330 11 view .LVU538 + 1826 00a2 0023 movs r3, #0 + 1827 00a4 84F84030 strb r3, [r4, #64] +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1828 .loc 1 1330 11 view .LVU539 +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1829 .loc 1 1333 11 view .LVU540 + 1830 00a8 2268 ldr r2, [r4] + 1831 00aa 1368 ldr r3, [r2] + 1832 00ac 43F48033 orr r3, r3, #65536 + 1833 00b0 1360 str r3, [r2] +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1834 .loc 1 1336 11 view .LVU541 + 1835 00b2 2268 ldr r2, [r4] + 1836 00b4 1368 ldr r3, [r2] + 1837 00b6 43F00403 orr r3, r3, #4 + 1838 00ba 1360 str r3, [r2] + 1839 00bc 3546 mov r5, r6 + 1840 00be B7E7 b .L89 + 1841 .LVL124: + 1842 .L92: +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1843 .loc 1 1311 14 view .LVU542 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1844 .loc 1 1311 17 is_stmt 0 view .LVU543 + 1845 00c0 102B cmp r3, #16 + 1846 00c2 07D0 beq .L100 +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1847 .loc 1 1315 14 is_stmt 1 view .LVU544 +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1848 .loc 1 1315 17 is_stmt 0 view .LVU545 + 1849 00c4 202B cmp r3, #32 + 1850 00c6 0FD0 beq .L101 +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1851 .loc 1 1322 11 is_stmt 1 view .LVU546 +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1852 .loc 1 1322 28 is_stmt 0 view .LVU547 + 1853 00c8 636C ldr r3, [r4, #68] + 1854 00ca 43F00403 orr r3, r3, #4 + 1855 00ce 6364 str r3, [r4, #68] +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1856 .loc 1 1323 11 is_stmt 1 view .LVU548 + 1857 .LVL125: + ARM GAS /tmp/ccNpZKQO.s page 88 + + +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1858 .loc 1 1323 18 is_stmt 0 view .LVU549 + 1859 00d0 2E46 mov r6, r5 + 1860 00d2 DDE7 b .L93 + 1861 .LVL126: + 1862 .L100: +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1863 .loc 1 1313 11 is_stmt 1 view .LVU550 + 1864 00d4 1268 ldr r2, [r2] + 1865 00d6 1069 ldr r0, [r2, #16] + 1866 00d8 A3F54573 sub r3, r3, #788 + 1867 00dc 0340 ands r3, r3, r0 + 1868 00de 43F48173 orr r3, r3, #258 + 1869 00e2 1361 str r3, [r2, #16] +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1870 .loc 1 1265 21 is_stmt 0 view .LVU551 + 1871 00e4 0026 movs r6, #0 + 1872 00e6 D3E7 b .L93 + 1873 .L101: +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1874 .loc 1 1317 11 is_stmt 1 view .LVU552 + 1875 00e8 1068 ldr r0, [r2] + 1876 00ea 0369 ldr r3, [r0, #16] + 1877 00ec 114A ldr r2, .L102+12 + 1878 00ee 1A40 ands r2, r2, r3 + 1879 00f0 40F20223 movw r3, #514 + 1880 00f4 1343 orrs r3, r3, r2 + 1881 00f6 0361 str r3, [r0, #16] +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1882 .loc 1 1265 21 is_stmt 0 view .LVU553 + 1883 00f8 0026 movs r6, #0 + 1884 00fa C9E7 b .L93 + 1885 .LVL127: + 1886 .L96: +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + 1887 .loc 1 1340 11 is_stmt 1 view .LVU554 +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 1888 .loc 1 1341 11 view .LVU555 +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 1889 .loc 1 1341 28 is_stmt 0 view .LVU556 + 1890 00fc 636C ldr r3, [r4, #68] + 1891 00fe 43F00403 orr r3, r3, #4 + 1892 0102 6364 str r3, [r4, #68] +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1893 .loc 1 1342 11 is_stmt 1 view .LVU557 +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1894 .loc 1 1342 24 is_stmt 0 view .LVU558 + 1895 0104 0123 movs r3, #1 + 1896 0106 84F84130 strb r3, [r4, #65] +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1897 .loc 1 1345 11 is_stmt 1 view .LVU559 +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1898 .loc 1 1345 11 view .LVU560 + 1899 010a 0023 movs r3, #0 + 1900 010c 84F84030 strb r3, [r4, #64] + 1901 0110 8EE7 b .L89 + 1902 .LVL128: + ARM GAS /tmp/ccNpZKQO.s page 89 + + + 1903 .L91: +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1904 .loc 1 1350 7 discriminator 1 view .LVU561 +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 1905 .loc 1 1350 24 is_stmt 0 discriminator 1 view .LVU562 + 1906 0112 636C ldr r3, [r4, #68] + 1907 0114 43F00803 orr r3, r3, #8 + 1908 0118 6364 str r3, [r4, #68] +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1909 .loc 1 1351 7 is_stmt 1 discriminator 1 view .LVU563 + 1910 .LVL129: +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1911 .loc 1 1354 7 discriminator 1 view .LVU564 +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1912 .loc 1 1354 7 discriminator 1 view .LVU565 + 1913 011a 0023 movs r3, #0 + 1914 011c 84F84030 strb r3, [r4, #64] + 1915 0120 86E7 b .L89 + 1916 .LVL130: + 1917 .L97: +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1918 .loc 1 1269 3 is_stmt 0 view .LVU566 + 1919 0122 0225 movs r5, #2 + 1920 0124 84E7 b .L89 + 1921 .L103: + 1922 0126 00BF .align 2 + 1923 .L102: + 1924 0128 00000000 .word QSPI_DMATxCplt + 1925 012c 00000000 .word QSPI_DMAError + 1926 0130 F3F3FFFF .word -3085 + 1927 0134 FCFCFFFF .word -772 + 1928 .cfi_endproc + 1929 .LFE152: + 1931 .section .text.HAL_QSPI_Receive_DMA,"ax",%progbits + 1932 .align 1 + 1933 .global HAL_QSPI_Receive_DMA + 1934 .syntax unified + 1935 .thumb + 1936 .thumb_func + 1937 .fpu fpv5-d16 + 1939 HAL_QSPI_Receive_DMA: + 1940 .LVL131: + 1941 .LFB153: +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1942 .loc 1 1376 1 is_stmt 1 view -0 + 1943 .cfi_startproc + 1944 @ args = 0, pretend = 0, frame = 0 + 1945 @ frame_needed = 0, uses_anonymous_args = 0 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 1946 .loc 1 1376 1 is_stmt 0 view .LVU568 + 1947 0000 70B5 push {r4, r5, r6, lr} + 1948 .LCFI29: + 1949 .cfi_def_cfa_offset 16 + 1950 .cfi_offset 4, -16 + 1951 .cfi_offset 5, -12 + 1952 .cfi_offset 6, -8 + 1953 .cfi_offset 14, -4 + ARM GAS /tmp/ccNpZKQO.s page 90 + + + 1954 0002 82B0 sub sp, sp, #8 + 1955 .LCFI30: + 1956 .cfi_def_cfa_offset 24 + 1957 0004 0446 mov r4, r0 +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 1958 .loc 1 1377 3 is_stmt 1 view .LVU569 + 1959 .LVL132: +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1960 .loc 1 1378 3 view .LVU570 +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1961 .loc 1 1378 23 is_stmt 0 view .LVU571 + 1962 0006 0068 ldr r0, [r0] + 1963 .LVL133: +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + 1964 .loc 1 1378 12 view .LVU572 + 1965 0008 8269 ldr r2, [r0, #24] + 1966 .LVL134: +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1967 .loc 1 1379 3 is_stmt 1 view .LVU573 +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1968 .loc 1 1379 25 is_stmt 0 view .LVU574 + 1969 000a 0669 ldr r6, [r0, #16] + 1970 .LVL135: +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1971 .loc 1 1382 3 is_stmt 1 view .LVU575 +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1972 .loc 1 1382 3 view .LVU576 + 1973 000c 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 1974 0010 DBB2 uxtb r3, r3 + 1975 0012 012B cmp r3, #1 + 1976 0014 00F08C80 beq .L113 + 1977 0018 0136 adds r6, r6, #1 + 1978 .LVL136: +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1979 .loc 1 1382 3 discriminator 2 view .LVU577 + 1980 001a 0123 movs r3, #1 + 1981 001c 84F84030 strb r3, [r4, #64] +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1982 .loc 1 1382 3 discriminator 2 view .LVU578 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1983 .loc 1 1384 3 discriminator 2 view .LVU579 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1984 .loc 1 1384 11 is_stmt 0 discriminator 2 view .LVU580 + 1985 0020 94F84150 ldrb r5, [r4, #65] @ zero_extendqisi2 + 1986 0024 EDB2 uxtb r5, r5 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 1987 .loc 1 1384 5 discriminator 2 view .LVU581 + 1988 0026 9D42 cmp r5, r3 + 1989 0028 06D0 beq .L115 +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1990 .loc 1 1473 5 is_stmt 1 view .LVU582 + 1991 .LVL137: +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1992 .loc 1 1476 5 view .LVU583 +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 1993 .loc 1 1476 5 view .LVU584 + 1994 002a 0023 movs r3, #0 + ARM GAS /tmp/ccNpZKQO.s page 91 + + + 1995 002c 84F84030 strb r3, [r4, #64] +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 1996 .loc 1 1473 12 is_stmt 0 view .LVU585 + 1997 0030 0225 movs r5, #2 + 1998 .LVL138: + 1999 .L105: +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2000 .loc 1 1480 1 view .LVU586 + 2001 0032 2846 mov r0, r5 + 2002 0034 02B0 add sp, sp, #8 + 2003 .LCFI31: + 2004 .cfi_remember_state + 2005 .cfi_def_cfa_offset 16 + 2006 @ sp needed + 2007 0036 70BD pop {r4, r5, r6, pc} + 2008 .LVL139: + 2009 .L115: + 2010 .LCFI32: + 2011 .cfi_restore_state +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2012 .loc 1 1387 5 is_stmt 1 view .LVU587 +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2013 .loc 1 1387 22 is_stmt 0 view .LVU588 + 2014 0038 0023 movs r3, #0 + 2015 003a 6364 str r3, [r4, #68] +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2016 .loc 1 1389 5 is_stmt 1 view .LVU589 +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2017 .loc 1 1389 7 is_stmt 0 view .LVU590 + 2018 003c 0029 cmp r1, #0 + 2019 003e 6FD0 beq .L107 +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ + 2020 .loc 1 1392 7 is_stmt 1 view .LVU591 +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Update state */ + 2021 .loc 1 1392 26 is_stmt 0 view .LVU592 + 2022 0040 A663 str r6, [r4, #56] +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2023 .loc 1 1394 9 is_stmt 1 view .LVU593 +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2024 .loc 1 1394 22 is_stmt 0 view .LVU594 + 2025 0042 2223 movs r3, #34 + 2026 0044 84F84130 strb r3, [r4, #65] +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2027 .loc 1 1397 9 is_stmt 1 view .LVU595 + 2028 0048 0323 movs r3, #3 + 2029 004a C360 str r3, [r0, #12] +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 2030 .loc 1 1400 9 view .LVU596 +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 2031 .loc 1 1400 34 is_stmt 0 view .LVU597 + 2032 004c A36B ldr r3, [r4, #56] +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr = pData; + 2033 .loc 1 1400 27 view .LVU598 + 2034 004e 6363 str r3, [r4, #52] +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2035 .loc 1 1401 9 is_stmt 1 view .LVU599 +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 92 + + + 2036 .loc 1 1401 27 is_stmt 0 view .LVU600 + 2037 0050 2163 str r1, [r4, #48] +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2038 .loc 1 1404 9 is_stmt 1 view .LVU601 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2039 .loc 1 1404 14 is_stmt 0 view .LVU602 + 2040 0052 E36B ldr r3, [r4, #60] +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2041 .loc 1 1404 40 view .LVU603 + 2042 0054 3748 ldr r0, .L118 + 2043 0056 5864 str r0, [r3, #68] +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2044 .loc 1 1407 9 is_stmt 1 view .LVU604 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2045 .loc 1 1407 14 is_stmt 0 view .LVU605 + 2046 0058 E36B ldr r3, [r4, #60] +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2047 .loc 1 1407 41 view .LVU606 + 2048 005a 3748 ldr r0, .L118+4 + 2049 005c 5865 str r0, [r3, #84] +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2050 .loc 1 1410 9 is_stmt 1 view .LVU607 +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2051 .loc 1 1410 14 is_stmt 0 view .LVU608 + 2052 005e E36B ldr r3, [r4, #60] +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2053 .loc 1 1410 41 view .LVU609 + 2054 0060 0020 movs r0, #0 + 2055 0062 9865 str r0, [r3, #88] +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2056 .loc 1 1413 7 is_stmt 1 view .LVU610 + 2057 0064 E36B ldr r3, [r4, #60] + 2058 0066 1868 ldr r0, [r3] + 2059 0068 0669 ldr r6, [r0, #16] + 2060 .LVL140: +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2061 .loc 1 1413 7 is_stmt 0 view .LVU611 + 2062 006a 344B ldr r3, .L118+8 + 2063 006c 3340 ands r3, r3, r6 + 2064 006e 0361 str r3, [r0, #16] +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2065 .loc 1 1416 7 is_stmt 1 view .LVU612 +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2066 .loc 1 1416 16 is_stmt 0 view .LVU613 + 2067 0070 E06B ldr r0, [r4, #60] +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2068 .loc 1 1416 29 view .LVU614 + 2069 0072 036A ldr r3, [r0, #32] +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2070 .loc 1 1416 10 view .LVU615 + 2071 0074 5BBB cbnz r3, .L108 +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2072 .loc 1 1418 9 is_stmt 1 view .LVU616 + 2073 0076 0068 ldr r0, [r0] + 2074 0078 0669 ldr r6, [r0, #16] + 2075 007a A3F60D43 subw r3, r3, #3085 + 2076 007e 3340 ands r3, r3, r6 + ARM GAS /tmp/ccNpZKQO.s page 93 + + + 2077 0080 43F00803 orr r3, r3, #8 + 2078 0084 0361 str r3, [r0, #16] +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 2079 .loc 1 1377 21 is_stmt 0 view .LVU617 + 2080 0086 0026 movs r6, #0 + 2081 .LVL141: + 2082 .L109: +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2083 .loc 1 1435 11 is_stmt 1 view .LVU618 + 2084 0088 2068 ldr r0, [r4] + 2085 008a 4369 ldr r3, [r0, #20] + 2086 008c 23F04063 bic r3, r3, #201326592 + 2087 0090 43F08063 orr r3, r3, #67108864 + 2088 0094 4361 str r3, [r0, #20] +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2089 .loc 1 1438 11 view .LVU619 + 2090 0096 2368 ldr r3, [r4] + 2091 0098 9A61 str r2, [r3, #24] +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2092 .loc 1 1441 9 view .LVU620 +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2093 .loc 1 1441 61 is_stmt 0 view .LVU621 + 2094 009a 2068 ldr r0, [r4] +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2095 .loc 1 1441 13 view .LVU622 + 2096 009c 636B ldr r3, [r4, #52] + 2097 009e 0122 movs r2, #1 + 2098 .LVL142: +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2099 .loc 1 1441 13 view .LVU623 + 2100 00a0 0092 str r2, [sp] + 2101 00a2 0A46 mov r2, r1 + 2102 00a4 00F12001 add r1, r0, #32 + 2103 .LVL143: +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2104 .loc 1 1441 13 view .LVU624 + 2105 00a8 E06B ldr r0, [r4, #60] + 2106 00aa FFF7FEFF bl HAL_MDMA_Start_IT + 2107 .LVL144: +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2108 .loc 1 1441 12 view .LVU625 + 2109 00ae 60BB cbnz r0, .L112 +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2110 .loc 1 1444 11 is_stmt 1 view .LVU626 +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2111 .loc 1 1444 11 view .LVU627 + 2112 00b0 0023 movs r3, #0 + 2113 00b2 84F84030 strb r3, [r4, #64] +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2114 .loc 1 1444 11 view .LVU628 +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2115 .loc 1 1447 11 view .LVU629 + 2116 00b6 2268 ldr r2, [r4] + 2117 00b8 1368 ldr r3, [r2] + 2118 00ba 43F48033 orr r3, r3, #65536 + 2119 00be 1360 str r3, [r2] +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + ARM GAS /tmp/ccNpZKQO.s page 94 + + + 2120 .loc 1 1450 11 view .LVU630 + 2121 00c0 2268 ldr r2, [r4] + 2122 00c2 1368 ldr r3, [r2] + 2123 00c4 43F00403 orr r3, r3, #4 + 2124 00c8 1360 str r3, [r2] + 2125 00ca 3546 mov r5, r6 + 2126 00cc B1E7 b .L105 + 2127 .LVL145: + 2128 .L108: +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2129 .loc 1 1420 12 view .LVU631 +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2130 .loc 1 1420 15 is_stmt 0 view .LVU632 + 2131 00ce 402B cmp r3, #64 + 2132 00d0 07D0 beq .L116 +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2133 .loc 1 1424 12 is_stmt 1 view .LVU633 +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2134 .loc 1 1424 15 is_stmt 0 view .LVU634 + 2135 00d2 802B cmp r3, #128 + 2136 00d4 0FD0 beq .L117 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 2137 .loc 1 1431 9 is_stmt 1 view .LVU635 +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 2138 .loc 1 1431 26 is_stmt 0 view .LVU636 + 2139 00d6 636C ldr r3, [r4, #68] + 2140 00d8 43F00403 orr r3, r3, #4 + 2141 00dc 6364 str r3, [r4, #68] +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2142 .loc 1 1432 9 is_stmt 1 view .LVU637 + 2143 .LVL146: +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2144 .loc 1 1432 16 is_stmt 0 view .LVU638 + 2145 00de 2E46 mov r6, r5 + 2146 00e0 D2E7 b .L109 + 2147 .LVL147: + 2148 .L116: +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2149 .loc 1 1422 9 is_stmt 1 view .LVU639 + 2150 00e2 0068 ldr r0, [r0] + 2151 00e4 0669 ldr r6, [r0, #16] + 2152 00e6 A3F64D43 subw r3, r3, #3149 + 2153 00ea 3340 ands r3, r3, r6 + 2154 00ec 43F48163 orr r3, r3, #1032 + 2155 00f0 0361 str r3, [r0, #16] +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 2156 .loc 1 1377 21 is_stmt 0 view .LVU640 + 2157 00f2 0026 movs r6, #0 + 2158 00f4 C8E7 b .L109 + 2159 .L117: +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2160 .loc 1 1426 9 is_stmt 1 view .LVU641 + 2161 00f6 0668 ldr r6, [r0] + 2162 00f8 3369 ldr r3, [r6, #16] + 2163 00fa 1148 ldr r0, .L118+12 + 2164 00fc 1840 ands r0, r0, r3 + 2165 00fe 40F60803 movw r3, #2056 + ARM GAS /tmp/ccNpZKQO.s page 95 + + + 2166 0102 0343 orrs r3, r3, r0 + 2167 0104 3361 str r3, [r6, #16] +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + 2168 .loc 1 1377 21 is_stmt 0 view .LVU642 + 2169 0106 0026 movs r6, #0 + 2170 0108 BEE7 b .L109 + 2171 .LVL148: + 2172 .L112: +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + 2173 .loc 1 1454 11 is_stmt 1 view .LVU643 +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 2174 .loc 1 1455 11 view .LVU644 +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->State = HAL_QSPI_STATE_READY; + 2175 .loc 1 1455 28 is_stmt 0 view .LVU645 + 2176 010a 636C ldr r3, [r4, #68] + 2177 010c 43F00403 orr r3, r3, #4 + 2178 0110 6364 str r3, [r4, #68] +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2179 .loc 1 1456 11 is_stmt 1 view .LVU646 +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2180 .loc 1 1456 24 is_stmt 0 view .LVU647 + 2181 0112 0123 movs r3, #1 + 2182 0114 84F84130 strb r3, [r4, #65] +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2183 .loc 1 1459 11 is_stmt 1 view .LVU648 +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2184 .loc 1 1459 11 view .LVU649 + 2185 0118 0023 movs r3, #0 + 2186 011a 84F84030 strb r3, [r4, #64] + 2187 011e 88E7 b .L105 + 2188 .LVL149: + 2189 .L107: +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 2190 .loc 1 1464 7 discriminator 1 view .LVU650 +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** status = HAL_ERROR; + 2191 .loc 1 1464 24 is_stmt 0 discriminator 1 view .LVU651 + 2192 0120 636C ldr r3, [r4, #68] + 2193 0122 43F00803 orr r3, r3, #8 + 2194 0126 6364 str r3, [r4, #68] +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2195 .loc 1 1465 7 is_stmt 1 discriminator 1 view .LVU652 + 2196 .LVL150: +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2197 .loc 1 1468 7 discriminator 1 view .LVU653 +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2198 .loc 1 1468 7 discriminator 1 view .LVU654 + 2199 0128 0023 movs r3, #0 + 2200 012a 84F84030 strb r3, [r4, #64] + 2201 012e 80E7 b .L105 + 2202 .LVL151: + 2203 .L113: +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2204 .loc 1 1382 3 is_stmt 0 view .LVU655 + 2205 0130 0225 movs r5, #2 + 2206 0132 7EE7 b .L105 + 2207 .L119: + 2208 .align 2 + ARM GAS /tmp/ccNpZKQO.s page 96 + + + 2209 .L118: + 2210 0134 00000000 .word QSPI_DMARxCplt + 2211 0138 00000000 .word QSPI_DMAError + 2212 013c FCFCFFFF .word -772 + 2213 0140 F3F3FFFF .word -3085 + 2214 .cfi_endproc + 2215 .LFE153: + 2217 .section .text.HAL_QSPI_AutoPolling,"ax",%progbits + 2218 .align 1 + 2219 .global HAL_QSPI_AutoPolling + 2220 .syntax unified + 2221 .thumb + 2222 .thumb_func + 2223 .fpu fpv5-d16 + 2225 HAL_QSPI_AutoPolling: + 2226 .LVL152: + 2227 .LFB154: +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 2228 .loc 1 1492 1 is_stmt 1 view -0 + 2229 .cfi_startproc + 2230 @ args = 0, pretend = 0, frame = 0 + 2231 @ frame_needed = 0, uses_anonymous_args = 0 +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 2232 .loc 1 1492 1 is_stmt 0 view .LVU657 + 2233 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2234 .LCFI33: + 2235 .cfi_def_cfa_offset 24 + 2236 .cfi_offset 4, -24 + 2237 .cfi_offset 5, -20 + 2238 .cfi_offset 6, -16 + 2239 .cfi_offset 7, -12 + 2240 .cfi_offset 8, -8 + 2241 .cfi_offset 14, -4 + 2242 0004 82B0 sub sp, sp, #8 + 2243 .LCFI34: + 2244 .cfi_def_cfa_offset 32 + 2245 0006 0446 mov r4, r0 + 2246 0008 8846 mov r8, r1 + 2247 000a 1546 mov r5, r2 + 2248 000c 1F46 mov r7, r3 +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 2249 .loc 1 1493 3 is_stmt 1 view .LVU658 +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2250 .loc 1 1494 3 view .LVU659 +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2251 .loc 1 1494 24 is_stmt 0 view .LVU660 + 2252 000e FFF7FEFF bl HAL_GetTick + 2253 .LVL153: +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 2254 .loc 1 1497 3 is_stmt 1 view .LVU661 +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2255 .loc 1 1498 3 view .LVU662 +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2256 .loc 1 1500 5 view .LVU663 +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 2257 .loc 1 1503 3 view .LVU664 +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 97 + + + 2258 .loc 1 1504 3 view .LVU665 +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2259 .loc 1 1506 5 view .LVU666 +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 2260 .loc 1 1509 3 view .LVU667 +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2261 .loc 1 1510 3 view .LVU668 +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2262 .loc 1 1512 5 view .LVU669 +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 2263 .loc 1 1515 3 view .LVU670 +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2264 .loc 1 1516 3 view .LVU671 +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 2265 .loc 1 1518 3 view .LVU672 +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 2266 .loc 1 1519 3 view .LVU673 +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2267 .loc 1 1520 3 view .LVU674 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); + 2268 .loc 1 1522 3 view .LVU675 +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); + 2269 .loc 1 1523 3 view .LVU676 +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2270 .loc 1 1524 3 view .LVU677 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2271 .loc 1 1527 3 view .LVU678 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2272 .loc 1 1527 3 view .LVU679 + 2273 0012 94F840C0 ldrb ip, [r4, #64] @ zero_extendqisi2 + 2274 0016 5FFA8CFC uxtb ip, ip + 2275 001a BCF1010F cmp ip, #1 + 2276 001e 48D0 beq .L123 + 2277 0020 0646 mov r6, r0 +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2278 .loc 1 1527 3 discriminator 2 view .LVU680 + 2279 0022 0123 movs r3, #1 + 2280 0024 84F84030 strb r3, [r4, #64] +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2281 .loc 1 1527 3 discriminator 2 view .LVU681 +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2282 .loc 1 1529 3 discriminator 2 view .LVU682 +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2283 .loc 1 1529 11 is_stmt 0 discriminator 2 view .LVU683 + 2284 0028 94F841C0 ldrb ip, [r4, #65] @ zero_extendqisi2 + 2285 002c 5FFA8CFC uxtb ip, ip +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2286 .loc 1 1529 5 discriminator 2 view .LVU684 + 2287 0030 9C45 cmp ip, r3 + 2288 0032 06D0 beq .L126 +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2289 .loc 1 1573 12 view .LVU685 + 2290 0034 0220 movs r0, #2 + 2291 .LVL154: + 2292 .L122: +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2293 .loc 1 1577 3 is_stmt 1 view .LVU686 + ARM GAS /tmp/ccNpZKQO.s page 98 + + +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2294 .loc 1 1577 3 view .LVU687 + 2295 0036 0023 movs r3, #0 + 2296 0038 84F84030 strb r3, [r4, #64] +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2297 .loc 1 1577 3 view .LVU688 +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2298 .loc 1 1580 3 view .LVU689 + 2299 .LVL155: + 2300 .L121: +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2301 .loc 1 1581 1 is_stmt 0 view .LVU690 + 2302 003c 02B0 add sp, sp, #8 + 2303 .LCFI35: + 2304 .cfi_remember_state + 2305 .cfi_def_cfa_offset 24 + 2306 @ sp needed + 2307 003e BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2308 .LVL156: + 2309 .L126: + 2310 .LCFI36: + 2311 .cfi_restore_state +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2312 .loc 1 1531 5 is_stmt 1 view .LVU691 +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2313 .loc 1 1531 22 is_stmt 0 view .LVU692 + 2314 0042 0022 movs r2, #0 + 2315 0044 6264 str r2, [r4, #68] +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2316 .loc 1 1534 5 is_stmt 1 view .LVU693 +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2317 .loc 1 1534 18 is_stmt 0 view .LVU694 + 2318 0046 4223 movs r3, #66 + 2319 0048 84F84130 strb r3, [r4, #65] +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2320 .loc 1 1537 5 is_stmt 1 view .LVU695 +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2321 .loc 1 1537 14 is_stmt 0 view .LVU696 + 2322 004c 0097 str r7, [sp] + 2323 004e 0346 mov r3, r0 + 2324 0050 2021 movs r1, #32 + 2325 0052 2046 mov r0, r4 + 2326 .LVL157: +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2327 .loc 1 1537 14 view .LVU697 + 2328 0054 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 2329 .LVL158: +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2330 .loc 1 1539 5 is_stmt 1 view .LVU698 +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2331 .loc 1 1539 8 is_stmt 0 view .LVU699 + 2332 0058 0028 cmp r0, #0 + 2333 005a ECD1 bne .L122 +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2334 .loc 1 1542 7 is_stmt 1 view .LVU700 + 2335 005c 2368 ldr r3, [r4] + 2336 005e 2A68 ldr r2, [r5] + ARM GAS /tmp/ccNpZKQO.s page 99 + + + 2337 0060 9A62 str r2, [r3, #40] +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2338 .loc 1 1545 7 view .LVU701 + 2339 0062 2368 ldr r3, [r4] + 2340 0064 6A68 ldr r2, [r5, #4] + 2341 0066 5A62 str r2, [r3, #36] +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2342 .loc 1 1548 7 view .LVU702 + 2343 0068 2368 ldr r3, [r4] + 2344 006a AA68 ldr r2, [r5, #8] + 2345 006c DA62 str r2, [r3, #44] +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); + 2346 .loc 1 1552 7 view .LVU703 + 2347 006e 2268 ldr r2, [r4] + 2348 0070 1368 ldr r3, [r2] + 2349 0072 23F44003 bic r3, r3, #12582912 + 2350 0076 2969 ldr r1, [r5, #16] + 2351 0078 0B43 orrs r3, r3, r1 + 2352 007a 43F48003 orr r3, r3, #4194304 + 2353 007e 1360 str r3, [r2] +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + 2354 .loc 1 1556 7 view .LVU704 +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + 2355 .loc 1 1556 24 is_stmt 0 view .LVU705 + 2356 0080 EB68 ldr r3, [r5, #12] +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + 2357 .loc 1 1556 19 view .LVU706 + 2358 0082 C8F82830 str r3, [r8, #40] +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2359 .loc 1 1557 7 is_stmt 1 view .LVU707 + 2360 0086 4FF00062 mov r2, #134217728 + 2361 008a 4146 mov r1, r8 + 2362 008c 2046 mov r0, r4 + 2363 .LVL159: +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2364 .loc 1 1557 7 is_stmt 0 view .LVU708 + 2365 008e FFF7FEFF bl QSPI_Config + 2366 .LVL160: +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2367 .loc 1 1560 7 is_stmt 1 view .LVU709 +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2368 .loc 1 1560 16 is_stmt 0 view .LVU710 + 2369 0092 0097 str r7, [sp] + 2370 0094 3346 mov r3, r6 + 2371 0096 0122 movs r2, #1 + 2372 0098 0821 movs r1, #8 + 2373 009a 2046 mov r0, r4 + 2374 009c FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 2375 .LVL161: +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2376 .loc 1 1562 7 is_stmt 1 view .LVU711 +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2377 .loc 1 1562 10 is_stmt 0 view .LVU712 + 2378 00a0 0028 cmp r0, #0 + 2379 00a2 C8D1 bne .L122 +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2380 .loc 1 1564 9 is_stmt 1 view .LVU713 + ARM GAS /tmp/ccNpZKQO.s page 100 + + + 2381 00a4 2368 ldr r3, [r4] + 2382 00a6 0822 movs r2, #8 + 2383 00a8 DA60 str r2, [r3, #12] +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2384 .loc 1 1567 9 view .LVU714 +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2385 .loc 1 1567 22 is_stmt 0 view .LVU715 + 2386 00aa 0123 movs r3, #1 + 2387 00ac 84F84130 strb r3, [r4, #65] + 2388 00b0 C1E7 b .L122 + 2389 .LVL162: + 2390 .L123: +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2391 .loc 1 1527 3 view .LVU716 + 2392 00b2 0220 movs r0, #2 + 2393 .LVL163: +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2394 .loc 1 1527 3 view .LVU717 + 2395 00b4 C2E7 b .L121 + 2396 .cfi_endproc + 2397 .LFE154: + 2399 .section .text.HAL_QSPI_AutoPolling_IT,"ax",%progbits + 2400 .align 1 + 2401 .global HAL_QSPI_AutoPolling_IT + 2402 .syntax unified + 2403 .thumb + 2404 .thumb_func + 2405 .fpu fpv5-d16 + 2407 HAL_QSPI_AutoPolling_IT: + 2408 .LVL164: + 2409 .LFB155: +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 2410 .loc 1 1592 1 is_stmt 1 view -0 + 2411 .cfi_startproc + 2412 @ args = 0, pretend = 0, frame = 0 + 2413 @ frame_needed = 0, uses_anonymous_args = 0 +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 2414 .loc 1 1592 1 is_stmt 0 view .LVU719 + 2415 0000 F0B5 push {r4, r5, r6, r7, lr} + 2416 .LCFI37: + 2417 .cfi_def_cfa_offset 20 + 2418 .cfi_offset 4, -20 + 2419 .cfi_offset 5, -16 + 2420 .cfi_offset 6, -12 + 2421 .cfi_offset 7, -8 + 2422 .cfi_offset 14, -4 + 2423 0002 83B0 sub sp, sp, #12 + 2424 .LCFI38: + 2425 .cfi_def_cfa_offset 32 + 2426 0004 0446 mov r4, r0 + 2427 0006 0E46 mov r6, r1 + 2428 0008 1546 mov r5, r2 +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 2429 .loc 1 1593 3 is_stmt 1 view .LVU720 +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2430 .loc 1 1594 3 view .LVU721 +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 101 + + + 2431 .loc 1 1594 24 is_stmt 0 view .LVU722 + 2432 000a FFF7FEFF bl HAL_GetTick + 2433 .LVL165: +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 2434 .loc 1 1597 3 is_stmt 1 view .LVU723 +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2435 .loc 1 1598 3 view .LVU724 +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2436 .loc 1 1600 5 view .LVU725 +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 2437 .loc 1 1603 3 view .LVU726 +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2438 .loc 1 1604 3 view .LVU727 +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2439 .loc 1 1606 5 view .LVU728 +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 2440 .loc 1 1609 3 view .LVU729 +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2441 .loc 1 1610 3 view .LVU730 +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2442 .loc 1 1612 5 view .LVU731 +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 2443 .loc 1 1615 3 view .LVU732 +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2444 .loc 1 1616 3 view .LVU733 +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 2445 .loc 1 1618 3 view .LVU734 +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 2446 .loc 1 1619 3 view .LVU735 +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2447 .loc 1 1620 3 view .LVU736 +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); + 2448 .loc 1 1622 3 view .LVU737 +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); + 2449 .loc 1 1623 3 view .LVU738 +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); + 2450 .loc 1 1624 3 view .LVU739 +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2451 .loc 1 1625 3 view .LVU740 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2452 .loc 1 1628 3 view .LVU741 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2453 .loc 1 1628 3 view .LVU742 + 2454 000e 94F840C0 ldrb ip, [r4, #64] @ zero_extendqisi2 + 2455 0012 5FFA8CFC uxtb ip, ip + 2456 0016 BCF1010F cmp ip, #1 + 2457 001a 46D0 beq .L131 +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2458 .loc 1 1628 3 discriminator 2 view .LVU743 + 2459 001c 0123 movs r3, #1 + 2460 001e 84F84030 strb r3, [r4, #64] +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2461 .loc 1 1628 3 discriminator 2 view .LVU744 +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2462 .loc 1 1630 3 discriminator 2 view .LVU745 +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2463 .loc 1 1630 11 is_stmt 0 discriminator 2 view .LVU746 + ARM GAS /tmp/ccNpZKQO.s page 102 + + + 2464 0022 94F84120 ldrb r2, [r4, #65] @ zero_extendqisi2 + 2465 0026 D2B2 uxtb r2, r2 +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2466 .loc 1 1630 5 discriminator 2 view .LVU747 + 2467 0028 9A42 cmp r2, r3 + 2468 002a 06D0 beq .L133 +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2469 .loc 1 1677 5 is_stmt 1 view .LVU748 + 2470 .LVL166: +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2471 .loc 1 1680 5 view .LVU749 +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2472 .loc 1 1680 5 view .LVU750 + 2473 002c 0023 movs r3, #0 + 2474 002e 84F84030 strb r3, [r4, #64] +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2475 .loc 1 1677 12 is_stmt 0 view .LVU751 + 2476 0032 0227 movs r7, #2 + 2477 .LVL167: + 2478 .L128: +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2479 .loc 1 1685 1 view .LVU752 + 2480 0034 3846 mov r0, r7 + 2481 0036 03B0 add sp, sp, #12 + 2482 .LCFI39: + 2483 .cfi_remember_state + 2484 .cfi_def_cfa_offset 20 + 2485 @ sp needed + 2486 0038 F0BD pop {r4, r5, r6, r7, pc} + 2487 .LVL168: + 2488 .L133: + 2489 .LCFI40: + 2490 .cfi_restore_state +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2491 .loc 1 1632 5 is_stmt 1 view .LVU753 +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2492 .loc 1 1632 22 is_stmt 0 view .LVU754 + 2493 003a 0022 movs r2, #0 + 2494 003c 6264 str r2, [r4, #68] +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2495 .loc 1 1635 5 is_stmt 1 view .LVU755 +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2496 .loc 1 1635 18 is_stmt 0 view .LVU756 + 2497 003e 4223 movs r3, #66 + 2498 0040 84F84130 strb r3, [r4, #65] +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2499 .loc 1 1638 5 is_stmt 1 view .LVU757 +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2500 .loc 1 1638 14 is_stmt 0 view .LVU758 + 2501 0044 A36C ldr r3, [r4, #72] + 2502 0046 0093 str r3, [sp] + 2503 0048 0346 mov r3, r0 + 2504 004a 2021 movs r1, #32 + 2505 004c 2046 mov r0, r4 + 2506 .LVL169: +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2507 .loc 1 1638 14 view .LVU759 + ARM GAS /tmp/ccNpZKQO.s page 103 + + + 2508 004e FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 2509 .LVL170: +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2510 .loc 1 1640 5 is_stmt 1 view .LVU760 +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2511 .loc 1 1640 8 is_stmt 0 view .LVU761 + 2512 0052 0746 mov r7, r0 + 2513 0054 18B1 cbz r0, .L134 +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2514 .loc 1 1672 7 is_stmt 1 view .LVU762 +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2515 .loc 1 1672 7 view .LVU763 + 2516 0056 0023 movs r3, #0 + 2517 0058 84F84030 strb r3, [r4, #64] + 2518 005c EAE7 b .L128 + 2519 .L134: +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2520 .loc 1 1643 7 view .LVU764 + 2521 005e 2368 ldr r3, [r4] + 2522 0060 2A68 ldr r2, [r5] + 2523 0062 9A62 str r2, [r3, #40] +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2524 .loc 1 1646 7 view .LVU765 + 2525 0064 2368 ldr r3, [r4] + 2526 0066 6A68 ldr r2, [r5, #4] + 2527 0068 5A62 str r2, [r3, #36] +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2528 .loc 1 1649 7 view .LVU766 + 2529 006a 2368 ldr r3, [r4] + 2530 006c AA68 ldr r2, [r5, #8] + 2531 006e DA62 str r2, [r3, #44] +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (cfg->MatchMode | cfg->AutomaticStop)); + 2532 .loc 1 1652 7 view .LVU767 + 2533 0070 2168 ldr r1, [r4] + 2534 0072 0B68 ldr r3, [r1] + 2535 0074 23F44003 bic r3, r3, #12582912 + 2536 0078 2A69 ldr r2, [r5, #16] + 2537 007a 6869 ldr r0, [r5, #20] + 2538 .LVL171: +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** (cfg->MatchMode | cfg->AutomaticStop)); + 2539 .loc 1 1652 7 is_stmt 0 view .LVU768 + 2540 007c 0243 orrs r2, r2, r0 + 2541 007e 1343 orrs r3, r3, r2 + 2542 0080 0B60 str r3, [r1] +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2543 .loc 1 1656 7 is_stmt 1 view .LVU769 + 2544 0082 2368 ldr r3, [r4] + 2545 0084 0922 movs r2, #9 + 2546 0086 DA60 str r2, [r3, #12] +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + 2547 .loc 1 1659 7 view .LVU770 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + 2548 .loc 1 1659 24 is_stmt 0 view .LVU771 + 2549 0088 EB68 ldr r3, [r5, #12] +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + 2550 .loc 1 1659 19 view .LVU772 + 2551 008a B362 str r3, [r6, #40] + ARM GAS /tmp/ccNpZKQO.s page 104 + + +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2552 .loc 1 1660 7 is_stmt 1 view .LVU773 + 2553 008c 4FF00062 mov r2, #134217728 + 2554 0090 3146 mov r1, r6 + 2555 0092 2046 mov r0, r4 + 2556 0094 FFF7FEFF bl QSPI_Config + 2557 .LVL172: +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2558 .loc 1 1663 7 view .LVU774 +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2559 .loc 1 1663 7 view .LVU775 + 2560 0098 0023 movs r3, #0 + 2561 009a 84F84030 strb r3, [r4, #64] +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2562 .loc 1 1663 7 view .LVU776 +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2563 .loc 1 1666 7 view .LVU777 + 2564 009e 2268 ldr r2, [r4] + 2565 00a0 1368 ldr r3, [r2] + 2566 00a2 43F41023 orr r3, r3, #589824 + 2567 00a6 1360 str r3, [r2] + 2568 00a8 C4E7 b .L128 + 2569 .LVL173: + 2570 .L131: +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2571 .loc 1 1628 3 is_stmt 0 view .LVU778 + 2572 00aa 0227 movs r7, #2 + 2573 00ac C2E7 b .L128 + 2574 .cfi_endproc + 2575 .LFE155: + 2577 .section .text.HAL_QSPI_MemoryMapped,"ax",%progbits + 2578 .align 1 + 2579 .global HAL_QSPI_MemoryMapped + 2580 .syntax unified + 2581 .thumb + 2582 .thumb_func + 2583 .fpu fpv5-d16 + 2585 HAL_QSPI_MemoryMapped: + 2586 .LVL174: + 2587 .LFB156: +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 2588 .loc 1 1696 1 is_stmt 1 view -0 + 2589 .cfi_startproc + 2590 @ args = 0, pretend = 0, frame = 0 + 2591 @ frame_needed = 0, uses_anonymous_args = 0 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 2592 .loc 1 1696 1 is_stmt 0 view .LVU780 + 2593 0000 F0B5 push {r4, r5, r6, r7, lr} + 2594 .LCFI41: + 2595 .cfi_def_cfa_offset 20 + 2596 .cfi_offset 4, -20 + 2597 .cfi_offset 5, -16 + 2598 .cfi_offset 6, -12 + 2599 .cfi_offset 7, -8 + 2600 .cfi_offset 14, -4 + 2601 0002 83B0 sub sp, sp, #12 + 2602 .LCFI42: + ARM GAS /tmp/ccNpZKQO.s page 105 + + + 2603 .cfi_def_cfa_offset 32 + 2604 0004 0446 mov r4, r0 + 2605 0006 0E46 mov r6, r1 + 2606 0008 1546 mov r5, r2 +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 2607 .loc 1 1697 3 is_stmt 1 view .LVU781 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2608 .loc 1 1698 3 view .LVU782 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2609 .loc 1 1698 24 is_stmt 0 view .LVU783 + 2610 000a FFF7FEFF bl HAL_GetTick + 2611 .LVL175: +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + 2612 .loc 1 1701 3 is_stmt 1 view .LVU784 +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2613 .loc 1 1702 3 view .LVU785 +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2614 .loc 1 1704 3 view .LVU786 +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AddressMode != QSPI_ADDRESS_NONE) + 2615 .loc 1 1707 3 view .LVU787 +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2616 .loc 1 1708 3 view .LVU788 +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2617 .loc 1 1710 5 view .LVU789 +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + 2618 .loc 1 1713 3 view .LVU790 +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2619 .loc 1 1714 3 view .LVU791 +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2620 .loc 1 1716 5 view .LVU792 +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + 2621 .loc 1 1719 3 view .LVU793 +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2622 .loc 1 1720 3 view .LVU794 +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + 2623 .loc 1 1722 3 view .LVU795 +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + 2624 .loc 1 1723 3 view .LVU796 +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2625 .loc 1 1724 3 view .LVU797 +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2626 .loc 1 1726 3 view .LVU798 +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2627 .loc 1 1729 3 view .LVU799 +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2628 .loc 1 1729 3 view .LVU800 + 2629 000e 94F840C0 ldrb ip, [r4, #64] @ zero_extendqisi2 + 2630 0012 5FFA8CFC uxtb ip, ip + 2631 0016 BCF1010F cmp ip, #1 + 2632 001a 3BD0 beq .L139 +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2633 .loc 1 1729 3 discriminator 2 view .LVU801 + 2634 001c 0123 movs r3, #1 + 2635 001e 84F84030 strb r3, [r4, #64] +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2636 .loc 1 1729 3 discriminator 2 view .LVU802 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 106 + + + 2637 .loc 1 1731 3 discriminator 2 view .LVU803 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2638 .loc 1 1731 11 is_stmt 0 discriminator 2 view .LVU804 + 2639 0022 94F841C0 ldrb ip, [r4, #65] @ zero_extendqisi2 + 2640 0026 5FFA8CFC uxtb ip, ip +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2641 .loc 1 1731 5 discriminator 2 view .LVU805 + 2642 002a 9C45 cmp ip, r3 + 2643 002c 06D0 beq .L142 +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2644 .loc 1 1766 12 view .LVU806 + 2645 002e 0227 movs r7, #2 + 2646 .LVL176: + 2647 .L137: +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2648 .loc 1 1770 3 is_stmt 1 view .LVU807 +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2649 .loc 1 1770 3 view .LVU808 + 2650 0030 0023 movs r3, #0 + 2651 0032 84F84030 strb r3, [r4, #64] +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2652 .loc 1 1770 3 view .LVU809 +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2653 .loc 1 1773 3 view .LVU810 + 2654 .LVL177: + 2655 .L136: +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2656 .loc 1 1774 1 is_stmt 0 view .LVU811 + 2657 0036 3846 mov r0, r7 + 2658 0038 03B0 add sp, sp, #12 + 2659 .LCFI43: + 2660 .cfi_remember_state + 2661 .cfi_def_cfa_offset 20 + 2662 @ sp needed + 2663 003a F0BD pop {r4, r5, r6, r7, pc} + 2664 .LVL178: + 2665 .L142: + 2666 .LCFI44: + 2667 .cfi_restore_state +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2668 .loc 1 1733 5 is_stmt 1 view .LVU812 +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2669 .loc 1 1733 22 is_stmt 0 view .LVU813 + 2670 003c 0022 movs r2, #0 + 2671 003e 6264 str r2, [r4, #68] +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2672 .loc 1 1736 5 is_stmt 1 view .LVU814 +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2673 .loc 1 1736 18 is_stmt 0 view .LVU815 + 2674 0040 8223 movs r3, #130 + 2675 0042 84F84130 strb r3, [r4, #65] +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2676 .loc 1 1739 5 is_stmt 1 view .LVU816 +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2677 .loc 1 1739 14 is_stmt 0 view .LVU817 + 2678 0046 A36C ldr r3, [r4, #72] + 2679 0048 0093 str r3, [sp] + ARM GAS /tmp/ccNpZKQO.s page 107 + + + 2680 004a 0346 mov r3, r0 + 2681 004c 2021 movs r1, #32 + 2682 004e 2046 mov r0, r4 + 2683 .LVL179: +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2684 .loc 1 1739 14 view .LVU818 + 2685 0050 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 2686 .LVL180: +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2687 .loc 1 1741 5 is_stmt 1 view .LVU819 +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2688 .loc 1 1741 8 is_stmt 0 view .LVU820 + 2689 0054 0746 mov r7, r0 + 2690 0056 0028 cmp r0, #0 + 2691 0058 EAD1 bne .L137 +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2692 .loc 1 1744 5 is_stmt 1 view .LVU821 + 2693 005a 2268 ldr r2, [r4] + 2694 005c 1368 ldr r3, [r2] + 2695 005e 23F00803 bic r3, r3, #8 + 2696 0062 6968 ldr r1, [r5, #4] + 2697 0064 0B43 orrs r3, r3, r1 + 2698 0066 1360 str r3, [r2] +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2699 .loc 1 1746 5 view .LVU822 +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2700 .loc 1 1746 12 is_stmt 0 view .LVU823 + 2701 0068 6B68 ldr r3, [r5, #4] +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2702 .loc 1 1746 8 view .LVU824 + 2703 006a 082B cmp r3, #8 + 2704 006c 06D0 beq .L143 + 2705 .L138: +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2706 .loc 1 1761 7 is_stmt 1 view .LVU825 + 2707 006e 4FF04062 mov r2, #201326592 + 2708 0072 3146 mov r1, r6 + 2709 0074 2046 mov r0, r4 + 2710 .LVL181: +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2711 .loc 1 1761 7 is_stmt 0 view .LVU826 + 2712 0076 FFF7FEFF bl QSPI_Config + 2713 .LVL182: + 2714 007a D9E7 b .L137 + 2715 .LVL183: + 2716 .L143: +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2717 .loc 1 1748 9 is_stmt 1 view .LVU827 +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2718 .loc 1 1751 9 view .LVU828 + 2719 007c 2368 ldr r3, [r4] + 2720 007e 2A68 ldr r2, [r5] + 2721 0080 1A63 str r2, [r3, #48] +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2722 .loc 1 1754 9 view .LVU829 + 2723 0082 2368 ldr r3, [r4] + 2724 0084 1022 movs r2, #16 + ARM GAS /tmp/ccNpZKQO.s page 108 + + + 2725 0086 DA60 str r2, [r3, #12] +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2726 .loc 1 1757 9 view .LVU830 + 2727 0088 2268 ldr r2, [r4] + 2728 008a 1368 ldr r3, [r2] + 2729 008c 43F48013 orr r3, r3, #1048576 + 2730 0090 1360 str r3, [r2] + 2731 0092 ECE7 b .L138 + 2732 .LVL184: + 2733 .L139: +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2734 .loc 1 1729 3 is_stmt 0 view .LVU831 + 2735 0094 0227 movs r7, #2 + 2736 0096 CEE7 b .L136 + 2737 .cfi_endproc + 2738 .LFE156: + 2740 .section .text.HAL_QSPI_ErrorCallback,"ax",%progbits + 2741 .align 1 + 2742 .weak HAL_QSPI_ErrorCallback + 2743 .syntax unified + 2744 .thumb + 2745 .thumb_func + 2746 .fpu fpv5-d16 + 2748 HAL_QSPI_ErrorCallback: + 2749 .LVL185: + 2750 .LFB157: +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2751 .loc 1 1782 1 is_stmt 1 view -0 + 2752 .cfi_startproc + 2753 @ args = 0, pretend = 0, frame = 0 + 2754 @ frame_needed = 0, uses_anonymous_args = 0 + 2755 @ link register save eliminated. +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2756 .loc 1 1784 3 view .LVU833 +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2757 .loc 1 1789 1 is_stmt 0 view .LVU834 + 2758 0000 7047 bx lr + 2759 .cfi_endproc + 2760 .LFE157: + 2762 .section .text.QSPI_DMAAbortCplt,"ax",%progbits + 2763 .align 1 + 2764 .syntax unified + 2765 .thumb + 2766 .thumb_func + 2767 .fpu fpv5-d16 + 2769 QSPI_DMAAbortCplt: + 2770 .LVL186: + 2771 .LFB176: +2413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); + 2772 .loc 1 2413 1 is_stmt 1 view -0 + 2773 .cfi_startproc + 2774 @ args = 0, pretend = 0, frame = 0 + 2775 @ frame_needed = 0, uses_anonymous_args = 0 +2413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); + 2776 .loc 1 2413 1 is_stmt 0 view .LVU836 + 2777 0000 08B5 push {r3, lr} + 2778 .LCFI45: + ARM GAS /tmp/ccNpZKQO.s page 109 + + + 2779 .cfi_def_cfa_offset 8 + 2780 .cfi_offset 3, -8 + 2781 .cfi_offset 14, -4 +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2782 .loc 1 2414 3 is_stmt 1 view .LVU837 +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2783 .loc 1 2414 23 is_stmt 0 view .LVU838 + 2784 0002 006C ldr r0, [r0, #64] + 2785 .LVL187: +2416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; + 2786 .loc 1 2416 3 is_stmt 1 view .LVU839 +2416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; + 2787 .loc 1 2416 22 is_stmt 0 view .LVU840 + 2788 0004 0023 movs r3, #0 + 2789 0006 8363 str r3, [r0, #56] +2417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2790 .loc 1 2417 3 is_stmt 1 view .LVU841 +2417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2791 .loc 1 2417 22 is_stmt 0 view .LVU842 + 2792 0008 C362 str r3, [r0, #44] +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2793 .loc 1 2419 3 is_stmt 1 view .LVU843 +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2794 .loc 1 2419 11 is_stmt 0 view .LVU844 + 2795 000a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 2796 000e DBB2 uxtb r3, r3 +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 2797 .loc 1 2419 5 view .LVU845 + 2798 0010 082B cmp r3, #8 + 2799 0012 0DD1 bne .L146 +2423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2800 .loc 1 2423 5 is_stmt 1 view .LVU846 + 2801 0014 0368 ldr r3, [r0] + 2802 0016 0222 movs r2, #2 + 2803 0018 DA60 str r2, [r3, #12] +2426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2804 .loc 1 2426 5 view .LVU847 + 2805 001a 0268 ldr r2, [r0] + 2806 001c 1368 ldr r3, [r2] + 2807 001e 43F40033 orr r3, r3, #131072 + 2808 0022 1360 str r3, [r2] +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 2809 .loc 1 2429 5 view .LVU848 + 2810 0024 0268 ldr r2, [r0] + 2811 0026 1368 ldr r3, [r2] + 2812 0028 43F00203 orr r3, r3, #2 + 2813 002c 1360 str r3, [r2] + 2814 .LVL188: + 2815 .L145: +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2816 .loc 1 2444 1 is_stmt 0 view .LVU849 + 2817 002e 08BD pop {r3, pc} + 2818 .LVL189: + 2819 .L146: +2435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2820 .loc 1 2435 5 is_stmt 1 view .LVU850 +2435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 110 + + + 2821 .loc 1 2435 18 is_stmt 0 view .LVU851 + 2822 0030 0123 movs r3, #1 + 2823 0032 80F84130 strb r3, [r0, #65] +2441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 2824 .loc 1 2441 5 is_stmt 1 view .LVU852 + 2825 0036 FFF7FEFF bl HAL_QSPI_ErrorCallback + 2826 .LVL190: +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2827 .loc 1 2444 1 is_stmt 0 view .LVU853 + 2828 003a F8E7 b .L145 + 2829 .cfi_endproc + 2830 .LFE176: + 2832 .section .text.HAL_QSPI_AbortCpltCallback,"ax",%progbits + 2833 .align 1 + 2834 .weak HAL_QSPI_AbortCpltCallback + 2835 .syntax unified + 2836 .thumb + 2837 .thumb_func + 2838 .fpu fpv5-d16 + 2840 HAL_QSPI_AbortCpltCallback: + 2841 .LVL191: + 2842 .LFB158: +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2843 .loc 1 1797 1 is_stmt 1 view -0 + 2844 .cfi_startproc + 2845 @ args = 0, pretend = 0, frame = 0 + 2846 @ frame_needed = 0, uses_anonymous_args = 0 + 2847 @ link register save eliminated. +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2848 .loc 1 1799 3 view .LVU855 +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2849 .loc 1 1804 1 is_stmt 0 view .LVU856 + 2850 0000 7047 bx lr + 2851 .cfi_endproc + 2852 .LFE158: + 2854 .section .text.HAL_QSPI_CmdCpltCallback,"ax",%progbits + 2855 .align 1 + 2856 .weak HAL_QSPI_CmdCpltCallback + 2857 .syntax unified + 2858 .thumb + 2859 .thumb_func + 2860 .fpu fpv5-d16 + 2862 HAL_QSPI_CmdCpltCallback: + 2863 .LVL192: + 2864 .LFB159: +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2865 .loc 1 1812 1 is_stmt 1 view -0 + 2866 .cfi_startproc + 2867 @ args = 0, pretend = 0, frame = 0 + 2868 @ frame_needed = 0, uses_anonymous_args = 0 + 2869 @ link register save eliminated. +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2870 .loc 1 1814 3 view .LVU858 +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2871 .loc 1 1819 1 is_stmt 0 view .LVU859 + 2872 0000 7047 bx lr + 2873 .cfi_endproc + ARM GAS /tmp/ccNpZKQO.s page 111 + + + 2874 .LFE159: + 2876 .section .text.HAL_QSPI_RxCpltCallback,"ax",%progbits + 2877 .align 1 + 2878 .weak HAL_QSPI_RxCpltCallback + 2879 .syntax unified + 2880 .thumb + 2881 .thumb_func + 2882 .fpu fpv5-d16 + 2884 HAL_QSPI_RxCpltCallback: + 2885 .LVL193: + 2886 .LFB160: +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2887 .loc 1 1827 1 is_stmt 1 view -0 + 2888 .cfi_startproc + 2889 @ args = 0, pretend = 0, frame = 0 + 2890 @ frame_needed = 0, uses_anonymous_args = 0 + 2891 @ link register save eliminated. +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2892 .loc 1 1829 3 view .LVU861 +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2893 .loc 1 1834 1 is_stmt 0 view .LVU862 + 2894 0000 7047 bx lr + 2895 .cfi_endproc + 2896 .LFE160: + 2898 .section .text.HAL_QSPI_TxCpltCallback,"ax",%progbits + 2899 .align 1 + 2900 .weak HAL_QSPI_TxCpltCallback + 2901 .syntax unified + 2902 .thumb + 2903 .thumb_func + 2904 .fpu fpv5-d16 + 2906 HAL_QSPI_TxCpltCallback: + 2907 .LVL194: + 2908 .LFB161: +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2909 .loc 1 1842 1 is_stmt 1 view -0 + 2910 .cfi_startproc + 2911 @ args = 0, pretend = 0, frame = 0 + 2912 @ frame_needed = 0, uses_anonymous_args = 0 + 2913 @ link register save eliminated. +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2914 .loc 1 1844 3 view .LVU864 +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2915 .loc 1 1849 1 is_stmt 0 view .LVU865 + 2916 0000 7047 bx lr + 2917 .cfi_endproc + 2918 .LFE161: + 2920 .section .text.HAL_QSPI_FifoThresholdCallback,"ax",%progbits + 2921 .align 1 + 2922 .weak HAL_QSPI_FifoThresholdCallback + 2923 .syntax unified + 2924 .thumb + 2925 .thumb_func + 2926 .fpu fpv5-d16 + 2928 HAL_QSPI_FifoThresholdCallback: + 2929 .LVL195: + 2930 .LFB162: + ARM GAS /tmp/ccNpZKQO.s page 112 + + +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2931 .loc 1 1858 1 is_stmt 1 view -0 + 2932 .cfi_startproc + 2933 @ args = 0, pretend = 0, frame = 0 + 2934 @ frame_needed = 0, uses_anonymous_args = 0 + 2935 @ link register save eliminated. +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2936 .loc 1 1860 3 view .LVU867 +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2937 .loc 1 1865 1 is_stmt 0 view .LVU868 + 2938 0000 7047 bx lr + 2939 .cfi_endproc + 2940 .LFE162: + 2942 .section .text.HAL_QSPI_StatusMatchCallback,"ax",%progbits + 2943 .align 1 + 2944 .weak HAL_QSPI_StatusMatchCallback + 2945 .syntax unified + 2946 .thumb + 2947 .thumb_func + 2948 .fpu fpv5-d16 + 2950 HAL_QSPI_StatusMatchCallback: + 2951 .LVL196: + 2952 .LFB163: +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2953 .loc 1 1873 1 is_stmt 1 view -0 + 2954 .cfi_startproc + 2955 @ args = 0, pretend = 0, frame = 0 + 2956 @ frame_needed = 0, uses_anonymous_args = 0 + 2957 @ link register save eliminated. +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2958 .loc 1 1875 3 view .LVU870 +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2959 .loc 1 1880 1 is_stmt 0 view .LVU871 + 2960 0000 7047 bx lr + 2961 .cfi_endproc + 2962 .LFE163: + 2964 .section .text.HAL_QSPI_TimeOutCallback,"ax",%progbits + 2965 .align 1 + 2966 .weak HAL_QSPI_TimeOutCallback + 2967 .syntax unified + 2968 .thumb + 2969 .thumb_func + 2970 .fpu fpv5-d16 + 2972 HAL_QSPI_TimeOutCallback: + 2973 .LVL197: + 2974 .LFB164: +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Prevent unused argument(s) compilation warning */ + 2975 .loc 1 1888 1 is_stmt 1 view -0 + 2976 .cfi_startproc + 2977 @ args = 0, pretend = 0, frame = 0 + 2978 @ frame_needed = 0, uses_anonymous_args = 0 + 2979 @ link register save eliminated. +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 2980 .loc 1 1890 3 view .LVU873 +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + 2981 .loc 1 1895 1 is_stmt 0 view .LVU874 + 2982 0000 7047 bx lr + ARM GAS /tmp/ccNpZKQO.s page 113 + + + 2983 .cfi_endproc + 2984 .LFE164: + 2986 .section .text.HAL_QSPI_IRQHandler,"ax",%progbits + 2987 .align 1 + 2988 .global HAL_QSPI_IRQHandler + 2989 .syntax unified + 2990 .thumb + 2991 .thumb_func + 2992 .fpu fpv5-d16 + 2994 HAL_QSPI_IRQHandler: + 2995 .LVL198: + 2996 .LFB145: + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg; + 2997 .loc 1 493 1 is_stmt 1 view -0 + 2998 .cfi_startproc + 2999 @ args = 0, pretend = 0, frame = 0 + 3000 @ frame_needed = 0, uses_anonymous_args = 0 + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** __IO uint32_t *data_reg; + 3001 .loc 1 493 1 is_stmt 0 view .LVU876 + 3002 0000 10B5 push {r4, lr} + 3003 .LCFI46: + 3004 .cfi_def_cfa_offset 8 + 3005 .cfi_offset 4, -8 + 3006 .cfi_offset 14, -4 + 3007 0002 0446 mov r4, r0 + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t flag = READ_REG(hqspi->Instance->SR); + 3008 .loc 1 494 3 is_stmt 1 view .LVU877 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t itsource = READ_REG(hqspi->Instance->CR); + 3009 .loc 1 495 3 view .LVU878 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t itsource = READ_REG(hqspi->Instance->CR); + 3010 .loc 1 495 19 is_stmt 0 view .LVU879 + 3011 0004 0368 ldr r3, [r0] + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t itsource = READ_REG(hqspi->Instance->CR); + 3012 .loc 1 495 12 view .LVU880 + 3013 0006 9A68 ldr r2, [r3, #8] + 3014 .LVL199: + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3015 .loc 1 496 3 is_stmt 1 view .LVU881 + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3016 .loc 1 496 12 is_stmt 0 view .LVU882 + 3017 0008 1968 ldr r1, [r3] + 3018 .LVL200: + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3019 .loc 1 499 3 is_stmt 1 view .LVU883 + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3020 .loc 1 499 5 is_stmt 0 view .LVU884 + 3021 000a 12F0040F tst r2, #4 + 3022 000e 3FD0 beq .L157 + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3023 .loc 1 499 36 discriminator 1 view .LVU885 + 3024 0010 11F4802F tst r1, #262144 + 3025 0014 3CD0 beq .L157 + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3026 .loc 1 501 5 is_stmt 1 view .LVU886 + 3027 .LVL201: + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3028 .loc 1 503 5 view .LVU887 + ARM GAS /tmp/ccNpZKQO.s page 114 + + + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3029 .loc 1 503 13 is_stmt 0 view .LVU888 + 3030 0016 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 3031 .LVL202: + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3032 .loc 1 503 13 view .LVU889 + 3033 001a D2B2 uxtb r2, r2 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3034 .loc 1 503 7 view .LVU890 + 3035 001c 122A cmp r2, #18 + 3036 001e 12D0 beq .L158 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3037 .loc 1 524 10 is_stmt 1 view .LVU891 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3038 .loc 1 524 18 is_stmt 0 view .LVU892 + 3039 0020 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 3040 0024 D2B2 uxtb r2, r2 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3041 .loc 1 524 12 view .LVU893 + 3042 0026 222A cmp r2, #34 + 3043 0028 1FD0 beq .L163 + 3044 .LVL203: + 3045 .L161: + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3046 .loc 1 548 5 is_stmt 1 view .LVU894 + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3047 .loc 1 554 5 view .LVU895 + 3048 002a 2046 mov r0, r4 + 3049 .LVL204: + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3050 .loc 1 554 5 is_stmt 0 view .LVU896 + 3051 002c FFF7FEFF bl HAL_QSPI_FifoThresholdCallback + 3052 .LVL205: + 3053 .L156: + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3054 .loc 1 771 1 view .LVU897 + 3055 0030 10BD pop {r4, pc} + 3056 .LVL206: + 3057 .L182: + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 3058 .loc 1 511 11 is_stmt 1 view .LVU898 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 3059 .loc 1 511 47 is_stmt 0 view .LVU899 + 3060 0032 626A ldr r2, [r4, #36] + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 3061 .loc 1 511 41 view .LVU900 + 3062 0034 1278 ldrb r2, [r2] @ zero_extendqisi2 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pTxBuffPtr++; + 3063 .loc 1 511 39 view .LVU901 + 3064 0036 83F82020 strb r2, [r3, #32] + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 3065 .loc 1 512 11 is_stmt 1 view .LVU902 + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 3066 .loc 1 512 16 is_stmt 0 view .LVU903 + 3067 003a 626A ldr r2, [r4, #36] + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount--; + 3068 .loc 1 512 28 view .LVU904 + ARM GAS /tmp/ccNpZKQO.s page 115 + + + 3069 003c 0132 adds r2, r2, #1 + 3070 003e 6262 str r2, [r4, #36] + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3071 .loc 1 513 11 is_stmt 1 view .LVU905 + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3072 .loc 1 513 16 is_stmt 0 view .LVU906 + 3073 0040 E26A ldr r2, [r4, #44] + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3074 .loc 1 513 29 view .LVU907 + 3075 0042 013A subs r2, r2, #1 + 3076 0044 E262 str r2, [r4, #44] + 3077 .L158: + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3078 .loc 1 506 12 is_stmt 1 view .LVU908 + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3079 .loc 1 506 13 is_stmt 0 view .LVU909 + 3080 0046 2268 ldr r2, [r4] + 3081 0048 9168 ldr r1, [r2, #8] + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3082 .loc 1 506 12 view .LVU910 + 3083 004a 11F0040F tst r1, #4 + 3084 004e ECD0 beq .L161 + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3085 .loc 1 508 9 is_stmt 1 view .LVU911 + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3086 .loc 1 508 18 is_stmt 0 view .LVU912 + 3087 0050 E16A ldr r1, [r4, #44] + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3088 .loc 1 508 12 view .LVU913 + 3089 0052 0029 cmp r1, #0 + 3090 0054 EDD1 bne .L182 + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 3091 .loc 1 519 11 is_stmt 1 view .LVU914 + 3092 0056 1368 ldr r3, [r2] + 3093 .LVL207: + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 3094 .loc 1 519 11 is_stmt 0 view .LVU915 + 3095 0058 23F48023 bic r3, r3, #262144 + 3096 005c 1360 str r3, [r2] + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3097 .loc 1 520 11 is_stmt 1 view .LVU916 + 3098 005e E4E7 b .L161 + 3099 .LVL208: + 3100 .L164: + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 3101 .loc 1 540 11 view .LVU917 + 3102 0060 1368 ldr r3, [r2] + 3103 .LVL209: + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** break; + 3104 .loc 1 540 11 is_stmt 0 view .LVU918 + 3105 0062 23F48023 bic r3, r3, #262144 + 3106 0066 1360 str r3, [r2] + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3107 .loc 1 541 11 is_stmt 1 view .LVU919 + 3108 0068 DFE7 b .L161 + 3109 .LVL210: + 3110 .L163: + ARM GAS /tmp/ccNpZKQO.s page 116 + + + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3111 .loc 1 527 12 view .LVU920 + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3112 .loc 1 527 13 is_stmt 0 view .LVU921 + 3113 006a 2268 ldr r2, [r4] + 3114 006c 9168 ldr r1, [r2, #8] + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3115 .loc 1 527 12 view .LVU922 + 3116 006e 11F0040F tst r1, #4 + 3117 0072 DAD0 beq .L161 + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3118 .loc 1 529 9 is_stmt 1 view .LVU923 + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3119 .loc 1 529 18 is_stmt 0 view .LVU924 + 3120 0074 A16B ldr r1, [r4, #56] + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3121 .loc 1 529 12 view .LVU925 + 3122 0076 0029 cmp r1, #0 + 3123 0078 F2D0 beq .L164 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3124 .loc 1 532 11 is_stmt 1 view .LVU926 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3125 .loc 1 532 17 is_stmt 0 view .LVU927 + 3126 007a 226B ldr r2, [r4, #48] + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3127 .loc 1 532 32 view .LVU928 + 3128 007c 93F82010 ldrb r1, [r3, #32] @ zero_extendqisi2 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3129 .loc 1 532 30 view .LVU929 + 3130 0080 1170 strb r1, [r2] + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 3131 .loc 1 533 11 is_stmt 1 view .LVU930 + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 3132 .loc 1 533 16 is_stmt 0 view .LVU931 + 3133 0082 226B ldr r2, [r4, #48] + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 3134 .loc 1 533 28 view .LVU932 + 3135 0084 0132 adds r2, r2, #1 + 3136 0086 2263 str r2, [r4, #48] + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3137 .loc 1 534 11 is_stmt 1 view .LVU933 + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3138 .loc 1 534 16 is_stmt 0 view .LVU934 + 3139 0088 A26B ldr r2, [r4, #56] + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3140 .loc 1 534 29 view .LVU935 + 3141 008a 013A subs r2, r2, #1 + 3142 008c A263 str r2, [r4, #56] + 3143 008e ECE7 b .L163 + 3144 .LVL211: + 3145 .L157: + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3146 .loc 1 559 8 is_stmt 1 view .LVU936 + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3147 .loc 1 559 10 is_stmt 0 view .LVU937 + 3148 0090 12F0020F tst r2, #2 + 3149 0094 76D0 beq .L167 + ARM GAS /tmp/ccNpZKQO.s page 117 + + + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3150 .loc 1 559 41 discriminator 1 view .LVU938 + 3151 0096 11F4003F tst r1, #131072 + 3152 009a 73D0 beq .L167 + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3153 .loc 1 562 5 is_stmt 1 view .LVU939 + 3154 009c 0222 movs r2, #2 + 3155 .LVL212: + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3156 .loc 1 562 5 is_stmt 0 view .LVU940 + 3157 009e DA60 str r2, [r3, #12] + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3158 .loc 1 565 5 is_stmt 1 view .LVU941 + 3159 00a0 2268 ldr r2, [r4] + 3160 00a2 1368 ldr r3, [r2] + 3161 00a4 23F4E023 bic r3, r3, #458752 + 3162 00a8 1360 str r3, [r2] + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3163 .loc 1 568 5 view .LVU942 + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3164 .loc 1 568 13 is_stmt 0 view .LVU943 + 3165 00aa 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 3166 00ae DBB2 uxtb r3, r3 + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3167 .loc 1 568 7 view .LVU944 + 3168 00b0 122B cmp r3, #18 + 3169 00b2 1DD0 beq .L183 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3170 .loc 1 590 10 is_stmt 1 view .LVU945 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3171 .loc 1 590 18 is_stmt 0 view .LVU946 + 3172 00b4 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 3173 00b8 DBB2 uxtb r3, r3 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3174 .loc 1 590 12 view .LVU947 + 3175 00ba 222B cmp r3, #34 + 3176 00bc 2ED0 beq .L184 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3177 .loc 1 631 10 is_stmt 1 view .LVU948 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3178 .loc 1 631 18 is_stmt 0 view .LVU949 + 3179 00be 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 3180 00c2 DBB2 uxtb r3, r3 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3181 .loc 1 631 12 view .LVU950 + 3182 00c4 022B cmp r3, #2 + 3183 00c6 52D0 beq .L185 + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3184 .loc 1 643 10 is_stmt 1 view .LVU951 + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3185 .loc 1 643 18 is_stmt 0 view .LVU952 + 3186 00c8 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 3187 00cc DBB2 uxtb r3, r3 + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3188 .loc 1 643 12 view .LVU953 + 3189 00ce 082B cmp r3, #8 + 3190 00d0 AED1 bne .L156 + ARM GAS /tmp/ccNpZKQO.s page 118 + + + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3191 .loc 1 646 7 is_stmt 1 view .LVU954 + 3192 00d2 2268 ldr r2, [r4] + 3193 00d4 5369 ldr r3, [r2, #20] + 3194 00d6 23F04063 bic r3, r3, #201326592 + 3195 00da 5361 str r3, [r2, #20] + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3196 .loc 1 649 7 view .LVU955 + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3197 .loc 1 649 20 is_stmt 0 view .LVU956 + 3198 00dc 0123 movs r3, #1 + 3199 00de 84F84130 strb r3, [r4, #65] + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3200 .loc 1 651 7 is_stmt 1 view .LVU957 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3201 .loc 1 651 16 is_stmt 0 view .LVU958 + 3202 00e2 636C ldr r3, [r4, #68] + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3203 .loc 1 651 10 view .LVU959 + 3204 00e4 002B cmp r3, #0 + 3205 00e6 49D1 bne .L175 + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3206 .loc 1 659 9 is_stmt 1 view .LVU960 + 3207 00e8 2046 mov r0, r4 + 3208 .LVL213: + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3209 .loc 1 659 9 is_stmt 0 view .LVU961 + 3210 00ea FFF7FEFF bl HAL_QSPI_AbortCpltCallback + 3211 .LVL214: + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3212 .loc 1 659 9 view .LVU962 + 3213 00ee 9FE7 b .L156 + 3214 .LVL215: + 3215 .L183: + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3216 .loc 1 570 7 is_stmt 1 view .LVU963 + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3217 .loc 1 570 17 is_stmt 0 view .LVU964 + 3218 00f0 2368 ldr r3, [r4] + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3219 .loc 1 570 27 view .LVU965 + 3220 00f2 1A68 ldr r2, [r3] + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3221 .loc 1 570 10 view .LVU966 + 3222 00f4 12F0040F tst r2, #4 + 3223 00f8 09D0 beq .L169 + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3224 .loc 1 573 9 is_stmt 1 view .LVU967 + 3225 00fa 1A68 ldr r2, [r3] + 3226 00fc 22F00402 bic r2, r2, #4 + 3227 0100 1A60 str r2, [r3] + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3228 .loc 1 576 9 view .LVU968 + 3229 0102 E36B ldr r3, [r4, #60] + 3230 0104 1A68 ldr r2, [r3] + 3231 0106 D368 ldr r3, [r2, #12] + 3232 0108 23F00103 bic r3, r3, #1 + ARM GAS /tmp/ccNpZKQO.s page 119 + + + 3233 010c D360 str r3, [r2, #12] + 3234 .L169: + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3235 .loc 1 581 7 view .LVU969 + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3236 .loc 1 581 20 is_stmt 0 view .LVU970 + 3237 010e 0123 movs r3, #1 + 3238 0110 84F84130 strb r3, [r4, #65] + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3239 .loc 1 587 7 is_stmt 1 view .LVU971 + 3240 0114 2046 mov r0, r4 + 3241 .LVL216: + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3242 .loc 1 587 7 is_stmt 0 view .LVU972 + 3243 0116 FFF7FEFF bl HAL_QSPI_TxCpltCallback + 3244 .LVL217: + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3245 .loc 1 587 7 view .LVU973 + 3246 011a 89E7 b .L156 + 3247 .LVL218: + 3248 .L184: + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3249 .loc 1 592 7 is_stmt 1 view .LVU974 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3250 .loc 1 592 17 is_stmt 0 view .LVU975 + 3251 011c 2168 ldr r1, [r4] + 3252 .LVL219: + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3253 .loc 1 592 27 view .LVU976 + 3254 011e 0B68 ldr r3, [r1] + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3255 .loc 1 592 10 view .LVU977 + 3256 0120 13F0040F tst r3, #4 + 3257 0124 10D0 beq .L171 + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3258 .loc 1 595 9 is_stmt 1 view .LVU978 + 3259 0126 0B68 ldr r3, [r1] + 3260 0128 23F00403 bic r3, r3, #4 + 3261 012c 0B60 str r3, [r1] + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3262 .loc 1 598 9 view .LVU979 + 3263 012e E36B ldr r3, [r4, #60] + 3264 0130 1A68 ldr r2, [r3] + 3265 0132 D368 ldr r3, [r2, #12] + 3266 0134 23F00103 bic r3, r3, #1 + 3267 0138 D360 str r3, [r2, #12] + 3268 .L172: + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3269 .loc 1 622 7 view .LVU980 + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3270 .loc 1 622 20 is_stmt 0 view .LVU981 + 3271 013a 0123 movs r3, #1 + 3272 013c 84F84130 strb r3, [r4, #65] + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3273 .loc 1 628 7 is_stmt 1 view .LVU982 + 3274 0140 2046 mov r0, r4 + 3275 .LVL220: + ARM GAS /tmp/ccNpZKQO.s page 120 + + + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3276 .loc 1 628 7 is_stmt 0 view .LVU983 + 3277 0142 FFF7FEFF bl HAL_QSPI_RxCpltCallback + 3278 .LVL221: + 3279 0146 73E7 b .L156 + 3280 .LVL222: + 3281 .L171: + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3282 .loc 1 603 14 is_stmt 1 view .LVU984 + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3283 .loc 1 603 15 is_stmt 0 view .LVU985 + 3284 0148 2368 ldr r3, [r4] + 3285 014a 9B68 ldr r3, [r3, #8] + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3286 .loc 1 603 14 view .LVU986 + 3287 014c 13F47C5F tst r3, #16128 + 3288 0150 F3D0 beq .L172 + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3289 .loc 1 605 11 is_stmt 1 view .LVU987 + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3290 .loc 1 605 20 is_stmt 0 view .LVU988 + 3291 0152 A36B ldr r3, [r4, #56] + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3292 .loc 1 605 14 view .LVU989 + 3293 0154 002B cmp r3, #0 + 3294 0156 F0D0 beq .L172 + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3295 .loc 1 608 13 is_stmt 1 view .LVU990 + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3296 .loc 1 608 19 is_stmt 0 view .LVU991 + 3297 0158 236B ldr r3, [r4, #48] + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3298 .loc 1 608 34 view .LVU992 + 3299 015a 91F82020 ldrb r2, [r1, #32] @ zero_extendqisi2 + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->pRxBuffPtr++; + 3300 .loc 1 608 32 view .LVU993 + 3301 015e 1A70 strb r2, [r3] + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 3302 .loc 1 609 13 is_stmt 1 view .LVU994 + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 3303 .loc 1 609 18 is_stmt 0 view .LVU995 + 3304 0160 236B ldr r3, [r4, #48] + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->RxXferCount--; + 3305 .loc 1 609 30 view .LVU996 + 3306 0162 0133 adds r3, r3, #1 + 3307 0164 2363 str r3, [r4, #48] + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3308 .loc 1 610 13 is_stmt 1 view .LVU997 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3309 .loc 1 610 18 is_stmt 0 view .LVU998 + 3310 0166 A36B ldr r3, [r4, #56] + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3311 .loc 1 610 31 view .LVU999 + 3312 0168 013B subs r3, r3, #1 + 3313 016a A363 str r3, [r4, #56] + 3314 016c ECE7 b .L171 + 3315 .LVL223: + ARM GAS /tmp/ccNpZKQO.s page 121 + + + 3316 .L185: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3317 .loc 1 634 7 is_stmt 1 view .LVU1000 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3318 .loc 1 634 20 is_stmt 0 view .LVU1001 + 3319 016e 0123 movs r3, #1 + 3320 0170 84F84130 strb r3, [r4, #65] + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3321 .loc 1 640 7 is_stmt 1 view .LVU1002 + 3322 0174 2046 mov r0, r4 + 3323 .LVL224: + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3324 .loc 1 640 7 is_stmt 0 view .LVU1003 + 3325 0176 FFF7FEFF bl HAL_QSPI_CmdCpltCallback + 3326 .LVL225: + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3327 .loc 1 640 7 view .LVU1004 + 3328 017a 59E7 b .L156 + 3329 .LVL226: + 3330 .L175: + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3331 .loc 1 670 9 is_stmt 1 view .LVU1005 + 3332 017c 2046 mov r0, r4 + 3333 .LVL227: + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3334 .loc 1 670 9 is_stmt 0 view .LVU1006 + 3335 017e FFF7FEFF bl HAL_QSPI_ErrorCallback + 3336 .LVL228: + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3337 .loc 1 670 9 view .LVU1007 + 3338 0182 55E7 b .L156 + 3339 .LVL229: + 3340 .L167: + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3341 .loc 1 681 8 is_stmt 1 view .LVU1008 + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3342 .loc 1 681 10 is_stmt 0 view .LVU1009 + 3343 0184 12F0080F tst r2, #8 + 3344 0188 14D0 beq .L176 + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3345 .loc 1 681 41 discriminator 1 view .LVU1010 + 3346 018a 11F4002F tst r1, #524288 + 3347 018e 11D0 beq .L176 + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3348 .loc 1 684 5 is_stmt 1 view .LVU1011 + 3349 0190 0822 movs r2, #8 + 3350 .LVL230: + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3351 .loc 1 684 5 is_stmt 0 view .LVU1012 + 3352 0192 DA60 str r2, [r3, #12] + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3353 .loc 1 687 5 is_stmt 1 view .LVU1013 + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3354 .loc 1 687 8 is_stmt 0 view .LVU1014 + 3355 0194 2368 ldr r3, [r4] + 3356 0196 1A68 ldr r2, [r3] + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + ARM GAS /tmp/ccNpZKQO.s page 122 + + + 3357 .loc 1 687 7 view .LVU1015 + 3358 0198 12F4800F tst r2, #4194304 + 3359 019c 06D0 beq .L177 + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3360 .loc 1 690 7 is_stmt 1 view .LVU1016 + 3361 019e 1A68 ldr r2, [r3] + 3362 01a0 22F41022 bic r2, r2, #589824 + 3363 01a4 1A60 str r2, [r3] + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3364 .loc 1 693 7 view .LVU1017 + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3365 .loc 1 693 20 is_stmt 0 view .LVU1018 + 3366 01a6 0123 movs r3, #1 + 3367 01a8 84F84130 strb r3, [r4, #65] + 3368 .L177: + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3369 .loc 1 700 5 is_stmt 1 view .LVU1019 + 3370 01ac 2046 mov r0, r4 + 3371 .LVL231: + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3372 .loc 1 700 5 is_stmt 0 view .LVU1020 + 3373 01ae FFF7FEFF bl HAL_QSPI_StatusMatchCallback + 3374 .LVL232: + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3375 .loc 1 700 5 view .LVU1021 + 3376 01b2 3DE7 b .L156 + 3377 .LVL233: + 3378 .L176: + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3379 .loc 1 705 8 is_stmt 1 view .LVU1022 + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3380 .loc 1 705 10 is_stmt 0 view .LVU1023 + 3381 01b4 12F0010F tst r2, #1 + 3382 01b8 31D0 beq .L178 + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3383 .loc 1 705 41 discriminator 1 view .LVU1024 + 3384 01ba 11F4803F tst r1, #65536 + 3385 01be 2ED0 beq .L178 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3386 .loc 1 708 5 is_stmt 1 view .LVU1025 + 3387 01c0 0122 movs r2, #1 + 3388 .LVL234: + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3389 .loc 1 708 5 is_stmt 0 view .LVU1026 + 3390 01c2 DA60 str r2, [r3, #12] + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3391 .loc 1 711 5 is_stmt 1 view .LVU1027 + 3392 01c4 2268 ldr r2, [r4] + 3393 01c6 1368 ldr r3, [r2] + 3394 01c8 23F47023 bic r3, r3, #983040 + 3395 01cc 1360 str r3, [r2] + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3396 .loc 1 714 5 view .LVU1028 + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3397 .loc 1 714 22 is_stmt 0 view .LVU1029 + 3398 01ce 636C ldr r3, [r4, #68] + 3399 01d0 43F00203 orr r3, r3, #2 + ARM GAS /tmp/ccNpZKQO.s page 123 + + + 3400 01d4 6364 str r3, [r4, #68] + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3401 .loc 1 716 5 is_stmt 1 view .LVU1030 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3402 .loc 1 716 15 is_stmt 0 view .LVU1031 + 3403 01d6 2368 ldr r3, [r4] + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3404 .loc 1 716 25 view .LVU1032 + 3405 01d8 1A68 ldr r2, [r3] + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3406 .loc 1 716 8 view .LVU1033 + 3407 01da 12F0040F tst r2, #4 + 3408 01de 17D0 beq .L179 + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3409 .loc 1 719 7 is_stmt 1 view .LVU1034 + 3410 01e0 1A68 ldr r2, [r3] + 3411 01e2 22F00402 bic r2, r2, #4 + 3412 01e6 1A60 str r2, [r3] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 3413 .loc 1 722 7 view .LVU1035 + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 3414 .loc 1 722 12 is_stmt 0 view .LVU1036 + 3415 01e8 E36B ldr r3, [r4, #60] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 3416 .loc 1 722 39 view .LVU1037 + 3417 01ea 144A ldr r2, .L186 + 3418 01ec 9A65 str r2, [r3, #88] + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3419 .loc 1 723 7 is_stmt 1 view .LVU1038 + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3420 .loc 1 723 11 is_stmt 0 view .LVU1039 + 3421 01ee E06B ldr r0, [r4, #60] + 3422 .LVL235: + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3423 .loc 1 723 11 view .LVU1040 + 3424 01f0 FFF7FEFF bl HAL_MDMA_Abort_IT + 3425 .LVL236: + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3426 .loc 1 723 10 view .LVU1041 + 3427 01f4 0028 cmp r0, #0 + 3428 01f6 3FF41BAF beq .L156 + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3429 .loc 1 726 9 is_stmt 1 view .LVU1042 + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3430 .loc 1 726 26 is_stmt 0 view .LVU1043 + 3431 01fa 636C ldr r3, [r4, #68] + 3432 01fc 43F00403 orr r3, r3, #4 + 3433 0200 6364 str r3, [r4, #68] + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3434 .loc 1 729 9 is_stmt 1 view .LVU1044 + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3435 .loc 1 729 22 is_stmt 0 view .LVU1045 + 3436 0202 0123 movs r3, #1 + 3437 0204 84F84130 strb r3, [r4, #65] + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3438 .loc 1 735 9 is_stmt 1 view .LVU1046 + 3439 0208 2046 mov r0, r4 + ARM GAS /tmp/ccNpZKQO.s page 124 + + + 3440 020a FFF7FEFF bl HAL_QSPI_ErrorCallback + 3441 .LVL237: + 3442 020e 0FE7 b .L156 + 3443 .LVL238: + 3444 .L179: + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3445 .loc 1 742 7 view .LVU1047 + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3446 .loc 1 742 20 is_stmt 0 view .LVU1048 + 3447 0210 0123 movs r3, #1 + 3448 0212 84F84130 strb r3, [r4, #65] + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3449 .loc 1 748 7 is_stmt 1 view .LVU1049 + 3450 0216 2046 mov r0, r4 + 3451 .LVL239: + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3452 .loc 1 748 7 is_stmt 0 view .LVU1050 + 3453 0218 FFF7FEFF bl HAL_QSPI_ErrorCallback + 3454 .LVL240: + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3455 .loc 1 748 7 view .LVU1051 + 3456 021c 08E7 b .L156 + 3457 .LVL241: + 3458 .L178: + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3459 .loc 1 754 8 is_stmt 1 view .LVU1052 + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3460 .loc 1 754 10 is_stmt 0 view .LVU1053 + 3461 021e 12F0100F tst r2, #16 + 3462 0222 3FF405AF beq .L156 + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3463 .loc 1 754 41 discriminator 1 view .LVU1054 + 3464 0226 11F4801F tst r1, #1048576 + 3465 022a 3FF401AF beq .L156 + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3466 .loc 1 757 5 is_stmt 1 view .LVU1055 + 3467 022e 1022 movs r2, #16 + 3468 .LVL242: + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3469 .loc 1 757 5 is_stmt 0 view .LVU1056 + 3470 0230 DA60 str r2, [r3, #12] + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3471 .loc 1 763 5 is_stmt 1 view .LVU1057 + 3472 0232 2046 mov r0, r4 + 3473 .LVL243: + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3474 .loc 1 763 5 is_stmt 0 view .LVU1058 + 3475 0234 FFF7FEFF bl HAL_QSPI_TimeOutCallback + 3476 .LVL244: + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3477 .loc 1 770 3 is_stmt 1 view .LVU1059 + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3478 .loc 1 771 1 is_stmt 0 view .LVU1060 + 3479 0238 FAE6 b .L156 + 3480 .L187: + 3481 023a 00BF .align 2 + 3482 .L186: + ARM GAS /tmp/ccNpZKQO.s page 125 + + + 3483 023c 00000000 .word QSPI_DMAAbortCplt + 3484 .cfi_endproc + 3485 .LFE145: + 3487 .section .text.HAL_QSPI_GetState,"ax",%progbits + 3488 .align 1 + 3489 .global HAL_QSPI_GetState + 3490 .syntax unified + 3491 .thumb + 3492 .thumb_func + 3493 .fpu fpv5-d16 + 3495 HAL_QSPI_GetState: + 3496 .LVL245: + 3497 .LFB165: +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** /* Return QSPI handle state */ + 3498 .loc 1 2130 1 is_stmt 1 view -0 + 3499 .cfi_startproc + 3500 @ args = 0, pretend = 0, frame = 0 + 3501 @ frame_needed = 0, uses_anonymous_args = 0 + 3502 @ link register save eliminated. +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3503 .loc 1 2132 3 view .LVU1062 +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3504 .loc 1 2132 15 is_stmt 0 view .LVU1063 + 3505 0000 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3506 .LVL246: +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3507 .loc 1 2133 1 view .LVU1064 + 3508 0004 7047 bx lr + 3509 .cfi_endproc + 3510 .LFE165: + 3512 .section .text.HAL_QSPI_GetError,"ax",%progbits + 3513 .align 1 + 3514 .global HAL_QSPI_GetError + 3515 .syntax unified + 3516 .thumb + 3517 .thumb_func + 3518 .fpu fpv5-d16 + 3520 HAL_QSPI_GetError: + 3521 .LVL247: + 3522 .LFB166: +2141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return hqspi->ErrorCode; + 3523 .loc 1 2141 1 is_stmt 1 view -0 + 3524 .cfi_startproc + 3525 @ args = 0, pretend = 0, frame = 0 + 3526 @ frame_needed = 0, uses_anonymous_args = 0 + 3527 @ link register save eliminated. +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3528 .loc 1 2142 3 view .LVU1066 +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3529 .loc 1 2142 15 is_stmt 0 view .LVU1067 + 3530 0000 406C ldr r0, [r0, #68] + 3531 .LVL248: +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3532 .loc 1 2143 1 view .LVU1068 + 3533 0002 7047 bx lr + 3534 .cfi_endproc + 3535 .LFE166: + ARM GAS /tmp/ccNpZKQO.s page 126 + + + 3537 .section .text.HAL_QSPI_Abort,"ax",%progbits + 3538 .align 1 + 3539 .global HAL_QSPI_Abort + 3540 .syntax unified + 3541 .thumb + 3542 .thumb_func + 3543 .fpu fpv5-d16 + 3545 HAL_QSPI_Abort: + 3546 .LVL249: + 3547 .LFB167: +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 3548 .loc 1 2151 1 is_stmt 1 view -0 + 3549 .cfi_startproc + 3550 @ args = 0, pretend = 0, frame = 0 + 3551 @ frame_needed = 0, uses_anonymous_args = 0 +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 3552 .loc 1 2151 1 is_stmt 0 view .LVU1070 + 3553 0000 30B5 push {r4, r5, lr} + 3554 .LCFI47: + 3555 .cfi_def_cfa_offset 12 + 3556 .cfi_offset 4, -12 + 3557 .cfi_offset 5, -8 + 3558 .cfi_offset 14, -4 + 3559 0002 83B0 sub sp, sp, #12 + 3560 .LCFI48: + 3561 .cfi_def_cfa_offset 24 + 3562 0004 0446 mov r4, r0 +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 3563 .loc 1 2152 3 is_stmt 1 view .LVU1071 + 3564 .LVL250: +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3565 .loc 1 2153 3 view .LVU1072 +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3566 .loc 1 2153 24 is_stmt 0 view .LVU1073 + 3567 0006 FFF7FEFF bl HAL_GetTick + 3568 .LVL251: +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3569 .loc 1 2153 24 view .LVU1074 + 3570 000a 0546 mov r5, r0 + 3571 .LVL252: +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3572 .loc 1 2156 3 is_stmt 1 view .LVU1075 +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3573 .loc 1 2156 23 is_stmt 0 view .LVU1076 + 3574 000c 94F84120 ldrb r2, [r4, #65] @ zero_extendqisi2 +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3575 .loc 1 2156 6 view .LVU1077 + 3576 0010 12F00200 ands r0, r2, #2 + 3577 .LVL253: +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3578 .loc 1 2156 6 view .LVU1078 + 3579 0014 1ED0 beq .L191 +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3580 .loc 1 2159 5 is_stmt 1 view .LVU1079 +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3581 .loc 1 2159 5 view .LVU1080 + 3582 0016 0023 movs r3, #0 + ARM GAS /tmp/ccNpZKQO.s page 127 + + + 3583 0018 84F84030 strb r3, [r4, #64] +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3584 .loc 1 2159 5 view .LVU1081 +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3585 .loc 1 2161 5 view .LVU1082 +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3586 .loc 1 2161 15 is_stmt 0 view .LVU1083 + 3587 001c 2368 ldr r3, [r4] +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3588 .loc 1 2161 25 view .LVU1084 + 3589 001e 1A68 ldr r2, [r3] +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3590 .loc 1 2161 8 view .LVU1085 + 3591 0020 12F0040F tst r2, #4 + 3592 0024 18D1 bne .L195 + 3593 .LVL254: + 3594 .L192: +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3595 .loc 1 2175 5 is_stmt 1 view .LVU1086 + 3596 0026 2368 ldr r3, [r4] + 3597 0028 1A68 ldr r2, [r3] + 3598 002a 42F00202 orr r2, r2, #2 + 3599 002e 1A60 str r2, [r3] +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3600 .loc 1 2178 5 view .LVU1087 +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3601 .loc 1 2178 14 is_stmt 0 view .LVU1088 + 3602 0030 A36C ldr r3, [r4, #72] + 3603 0032 0093 str r3, [sp] + 3604 0034 2B46 mov r3, r5 + 3605 0036 0122 movs r2, #1 + 3606 0038 0221 movs r1, #2 + 3607 003a 2046 mov r0, r4 + 3608 003c FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 3609 .LVL255: +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3610 .loc 1 2180 5 is_stmt 1 view .LVU1089 +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3611 .loc 1 2180 8 is_stmt 0 view .LVU1090 + 3612 0040 C0B1 cbz r0, .L196 + 3613 .L193: +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3614 .loc 1 2188 5 is_stmt 1 view .LVU1091 +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3615 .loc 1 2188 8 is_stmt 0 view .LVU1092 + 3616 0042 38B9 cbnz r0, .L191 +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3617 .loc 1 2191 7 is_stmt 1 view .LVU1093 + 3618 0044 2268 ldr r2, [r4] + 3619 0046 5369 ldr r3, [r2, #20] + 3620 0048 23F04063 bic r3, r3, #201326592 + 3621 004c 5361 str r3, [r2, #20] +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3622 .loc 1 2194 7 view .LVU1094 +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3623 .loc 1 2194 20 is_stmt 0 view .LVU1095 + 3624 004e 0123 movs r3, #1 + ARM GAS /tmp/ccNpZKQO.s page 128 + + + 3625 0050 84F84130 strb r3, [r4, #65] + 3626 .LVL256: + 3627 .L191: +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3628 .loc 1 2198 3 is_stmt 1 view .LVU1096 +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3629 .loc 1 2199 1 is_stmt 0 view .LVU1097 + 3630 0054 03B0 add sp, sp, #12 + 3631 .LCFI49: + 3632 .cfi_remember_state + 3633 .cfi_def_cfa_offset 12 + 3634 @ sp needed + 3635 0056 30BD pop {r4, r5, pc} + 3636 .LVL257: + 3637 .L195: + 3638 .LCFI50: + 3639 .cfi_restore_state +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3640 .loc 1 2164 7 is_stmt 1 view .LVU1098 + 3641 0058 1A68 ldr r2, [r3] + 3642 005a 22F00402 bic r2, r2, #4 + 3643 005e 1A60 str r2, [r3] +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(status != HAL_OK) + 3644 .loc 1 2167 7 view .LVU1099 +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if(status != HAL_OK) + 3645 .loc 1 2167 16 is_stmt 0 view .LVU1100 + 3646 0060 E06B ldr r0, [r4, #60] + 3647 0062 FFF7FEFF bl HAL_MDMA_Abort + 3648 .LVL258: +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3649 .loc 1 2168 7 is_stmt 1 view .LVU1101 +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3650 .loc 1 2168 9 is_stmt 0 view .LVU1102 + 3651 0066 0028 cmp r0, #0 + 3652 0068 DDD0 beq .L192 +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3653 .loc 1 2170 9 is_stmt 1 view .LVU1103 +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3654 .loc 1 2170 26 is_stmt 0 view .LVU1104 + 3655 006a 636C ldr r3, [r4, #68] + 3656 006c 43F00403 orr r3, r3, #4 + 3657 0070 6364 str r3, [r4, #68] + 3658 0072 D8E7 b .L192 + 3659 .L196: +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3660 .loc 1 2182 7 is_stmt 1 view .LVU1105 + 3661 0074 2368 ldr r3, [r4] + 3662 0076 0222 movs r2, #2 + 3663 0078 DA60 str r2, [r3, #12] +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3664 .loc 1 2185 7 view .LVU1106 +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3665 .loc 1 2185 16 is_stmt 0 view .LVU1107 + 3666 007a A36C ldr r3, [r4, #72] + 3667 007c 0093 str r3, [sp] + 3668 007e 2B46 mov r3, r5 + 3669 0080 0022 movs r2, #0 + ARM GAS /tmp/ccNpZKQO.s page 129 + + + 3670 0082 2021 movs r1, #32 + 3671 0084 2046 mov r0, r4 + 3672 .LVL259: +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3673 .loc 1 2185 16 view .LVU1108 + 3674 0086 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 3675 .LVL260: +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3676 .loc 1 2185 16 view .LVU1109 + 3677 008a DAE7 b .L193 + 3678 .cfi_endproc + 3679 .LFE167: + 3681 .section .text.HAL_QSPI_Abort_IT,"ax",%progbits + 3682 .align 1 + 3683 .global HAL_QSPI_Abort_IT + 3684 .syntax unified + 3685 .thumb + 3686 .thumb_func + 3687 .fpu fpv5-d16 + 3689 HAL_QSPI_Abort_IT: + 3690 .LVL261: + 3691 .LFB168: +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 3692 .loc 1 2207 1 is_stmt 1 view -0 + 3693 .cfi_startproc + 3694 @ args = 0, pretend = 0, frame = 0 + 3695 @ frame_needed = 0, uses_anonymous_args = 0 +2208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3696 .loc 1 2208 3 view .LVU1111 +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3697 .loc 1 2211 3 view .LVU1112 +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3698 .loc 1 2211 23 is_stmt 0 view .LVU1113 + 3699 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3700 .loc 1 2211 6 view .LVU1114 + 3701 0004 13F0020F tst r3, #2 + 3702 0008 32D0 beq .L201 +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 3703 .loc 1 2207 1 view .LVU1115 + 3704 000a 10B5 push {r4, lr} + 3705 .LCFI51: + 3706 .cfi_def_cfa_offset 8 + 3707 .cfi_offset 4, -8 + 3708 .cfi_offset 14, -4 + 3709 000c 0446 mov r4, r0 +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3710 .loc 1 2214 5 is_stmt 1 view .LVU1116 +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3711 .loc 1 2214 5 view .LVU1117 + 3712 000e 0023 movs r3, #0 + 3713 0010 80F84030 strb r3, [r0, #64] +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3714 .loc 1 2214 5 view .LVU1118 +2217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3715 .loc 1 2217 5 view .LVU1119 +2217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 130 + + + 3716 .loc 1 2217 18 is_stmt 0 view .LVU1120 + 3717 0014 0823 movs r3, #8 + 3718 0016 80F84130 strb r3, [r0, #65] +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3719 .loc 1 2220 5 is_stmt 1 view .LVU1121 + 3720 001a 0268 ldr r2, [r0] + 3721 001c 1368 ldr r3, [r2] + 3722 001e 23F4F813 bic r3, r3, #2031616 + 3723 0022 1360 str r3, [r2] +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3724 .loc 1 2222 5 view .LVU1122 +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3725 .loc 1 2222 15 is_stmt 0 view .LVU1123 + 3726 0024 0368 ldr r3, [r0] +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3727 .loc 1 2222 25 view .LVU1124 + 3728 0026 1A68 ldr r2, [r3] +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3729 .loc 1 2222 8 view .LVU1125 + 3730 0028 12F0040F tst r2, #4 + 3731 002c 0DD1 bne .L204 +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3732 .loc 1 2245 7 is_stmt 1 view .LVU1126 + 3733 002e 0222 movs r2, #2 + 3734 0030 DA60 str r2, [r3, #12] +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3735 .loc 1 2248 7 view .LVU1127 + 3736 0032 0268 ldr r2, [r0] + 3737 0034 1368 ldr r3, [r2] + 3738 0036 43F40033 orr r3, r3, #131072 + 3739 003a 1360 str r3, [r2] +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3740 .loc 1 2251 7 view .LVU1128 + 3741 003c 0268 ldr r2, [r0] + 3742 003e 1368 ldr r3, [r2] + 3743 0040 43F00203 orr r3, r3, #2 + 3744 0044 1360 str r3, [r2] + 3745 .LVL262: + 3746 .L198: +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3747 .loc 1 2254 3 view .LVU1129 +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3748 .loc 1 2255 1 is_stmt 0 view .LVU1130 + 3749 0046 0020 movs r0, #0 + 3750 0048 10BD pop {r4, pc} + 3751 .LVL263: + 3752 .L204: +2225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3753 .loc 1 2225 7 is_stmt 1 view .LVU1131 + 3754 004a 1A68 ldr r2, [r3] + 3755 004c 22F00402 bic r2, r2, #4 + 3756 0050 1A60 str r2, [r3] +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 3757 .loc 1 2228 7 view .LVU1132 +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 3758 .loc 1 2228 12 is_stmt 0 view .LVU1133 + 3759 0052 C36B ldr r3, [r0, #60] + ARM GAS /tmp/ccNpZKQO.s page 131 + + +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + 3760 .loc 1 2228 39 view .LVU1134 + 3761 0054 074A ldr r2, .L205 + 3762 0056 9A65 str r2, [r3, #88] +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3763 .loc 1 2229 7 is_stmt 1 view .LVU1135 +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3764 .loc 1 2229 11 is_stmt 0 view .LVU1136 + 3765 0058 C06B ldr r0, [r0, #60] + 3766 .LVL264: +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3767 .loc 1 2229 11 view .LVU1137 + 3768 005a FFF7FEFF bl HAL_MDMA_Abort_IT + 3769 .LVL265: +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3770 .loc 1 2229 10 view .LVU1138 + 3771 005e 0028 cmp r0, #0 + 3772 0060 F1D0 beq .L198 +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3773 .loc 1 2232 9 is_stmt 1 view .LVU1139 +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3774 .loc 1 2232 22 is_stmt 0 view .LVU1140 + 3775 0062 0123 movs r3, #1 + 3776 0064 84F84130 strb r3, [r4, #65] +2238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 3777 .loc 1 2238 9 is_stmt 1 view .LVU1141 + 3778 0068 2046 mov r0, r4 + 3779 006a FFF7FEFF bl HAL_QSPI_AbortCpltCallback + 3780 .LVL266: + 3781 006e EAE7 b .L198 + 3782 .LVL267: + 3783 .L201: + 3784 .LCFI52: + 3785 .cfi_def_cfa_offset 0 + 3786 .cfi_restore 4 + 3787 .cfi_restore 14 +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3788 .loc 1 2254 3 view .LVU1142 +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3789 .loc 1 2255 1 is_stmt 0 view .LVU1143 + 3790 0070 0020 movs r0, #0 + 3791 .LVL268: +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3792 .loc 1 2255 1 view .LVU1144 + 3793 0072 7047 bx lr + 3794 .L206: + 3795 .align 2 + 3796 .L205: + 3797 0074 00000000 .word QSPI_DMAAbortCplt + 3798 .cfi_endproc + 3799 .LFE168: + 3801 .section .text.QSPI_DMAError,"ax",%progbits + 3802 .align 1 + 3803 .syntax unified + 3804 .thumb + 3805 .thumb_func + 3806 .fpu fpv5-d16 + ARM GAS /tmp/ccNpZKQO.s page 132 + + + 3808 QSPI_DMAError: + 3809 .LVL269: + 3810 .LFB175: +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); + 3811 .loc 1 2392 1 is_stmt 1 view -0 + 3812 .cfi_startproc + 3813 @ args = 0, pretend = 0, frame = 0 + 3814 @ frame_needed = 0, uses_anonymous_args = 0 +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); + 3815 .loc 1 2392 1 is_stmt 0 view .LVU1146 + 3816 0000 08B5 push {r3, lr} + 3817 .LCFI53: + 3818 .cfi_def_cfa_offset 8 + 3819 .cfi_offset 3, -8 + 3820 .cfi_offset 14, -4 +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3821 .loc 1 2393 3 is_stmt 1 view .LVU1147 +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3822 .loc 1 2393 23 is_stmt 0 view .LVU1148 + 3823 0002 006C ldr r0, [r0, #64] + 3824 .LVL270: +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; + 3825 .loc 1 2395 3 is_stmt 1 view .LVU1149 +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->TxXferCount = 0U; + 3826 .loc 1 2395 22 is_stmt 0 view .LVU1150 + 3827 0004 0023 movs r3, #0 + 3828 0006 8363 str r3, [r0, #56] +2396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + 3829 .loc 1 2396 3 is_stmt 1 view .LVU1151 +2396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + 3830 .loc 1 2396 22 is_stmt 0 view .LVU1152 + 3831 0008 C362 str r3, [r0, #44] +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3832 .loc 1 2397 3 is_stmt 1 view .LVU1153 +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3833 .loc 1 2397 22 is_stmt 0 view .LVU1154 + 3834 000a 436C ldr r3, [r0, #68] + 3835 000c 43F00403 orr r3, r3, #4 + 3836 0010 4364 str r3, [r0, #68] +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3837 .loc 1 2400 3 is_stmt 1 view .LVU1155 + 3838 0012 0268 ldr r2, [r0] + 3839 0014 1368 ldr r3, [r2] + 3840 0016 23F00403 bic r3, r3, #4 + 3841 001a 1360 str r3, [r2] +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3842 .loc 1 2403 3 view .LVU1156 +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3843 .loc 1 2403 9 is_stmt 0 view .LVU1157 + 3844 001c FFF7FEFF bl HAL_QSPI_Abort_IT + 3845 .LVL271: +2405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3846 .loc 1 2405 1 view .LVU1158 + 3847 0020 08BD pop {r3, pc} + 3848 .cfi_endproc + 3849 .LFE175: + 3851 .section .text.HAL_QSPI_SetTimeout,"ax",%progbits + ARM GAS /tmp/ccNpZKQO.s page 133 + + + 3852 .align 1 + 3853 .global HAL_QSPI_SetTimeout + 3854 .syntax unified + 3855 .thumb + 3856 .thumb_func + 3857 .fpu fpv5-d16 + 3859 HAL_QSPI_SetTimeout: + 3860 .LVL272: + 3861 .LFB169: +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** hqspi->Timeout = Timeout; + 3862 .loc 1 2263 1 is_stmt 1 view -0 + 3863 .cfi_startproc + 3864 @ args = 0, pretend = 0, frame = 0 + 3865 @ frame_needed = 0, uses_anonymous_args = 0 + 3866 @ link register save eliminated. +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3867 .loc 1 2264 3 view .LVU1160 +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3868 .loc 1 2264 18 is_stmt 0 view .LVU1161 + 3869 0000 8164 str r1, [r0, #72] +2265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3870 .loc 1 2265 1 view .LVU1162 + 3871 0002 7047 bx lr + 3872 .cfi_endproc + 3873 .LFE169: + 3875 .section .text.HAL_QSPI_Init,"ax",%progbits + 3876 .align 1 + 3877 .global HAL_QSPI_Init + 3878 .syntax unified + 3879 .thumb + 3880 .thumb_func + 3881 .fpu fpv5-d16 + 3883 HAL_QSPI_Init: + 3884 .LVL273: + 3885 .LFB141: + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 3886 .loc 1 307 1 is_stmt 1 view -0 + 3887 .cfi_startproc + 3888 @ args = 0, pretend = 0, frame = 0 + 3889 @ frame_needed = 0, uses_anonymous_args = 0 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status; + 3890 .loc 1 307 1 is_stmt 0 view .LVU1164 + 3891 0000 70B5 push {r4, r5, r6, lr} + 3892 .LCFI54: + 3893 .cfi_def_cfa_offset 16 + 3894 .cfi_offset 4, -16 + 3895 .cfi_offset 5, -12 + 3896 .cfi_offset 6, -8 + 3897 .cfi_offset 14, -4 + 3898 0002 82B0 sub sp, sp, #8 + 3899 .LCFI55: + 3900 .cfi_def_cfa_offset 24 + 3901 0004 0446 mov r4, r0 + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** uint32_t tickstart = HAL_GetTick(); + 3902 .loc 1 308 3 is_stmt 1 view .LVU1165 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3903 .loc 1 309 3 view .LVU1166 + ARM GAS /tmp/ccNpZKQO.s page 134 + + + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3904 .loc 1 309 24 is_stmt 0 view .LVU1167 + 3905 0006 FFF7FEFF bl HAL_GetTick + 3906 .LVL274: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3907 .loc 1 312 3 is_stmt 1 view .LVU1168 + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3908 .loc 1 312 5 is_stmt 0 view .LVU1169 + 3909 000a 002C cmp r4, #0 + 3910 000c 45D0 beq .L213 + 3911 000e 0646 mov r6, r0 + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); + 3912 .loc 1 318 3 is_stmt 1 view .LVU1170 + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); + 3913 .loc 1 319 3 view .LVU1171 + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); + 3914 .loc 1 320 3 view .LVU1172 + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); + 3915 .loc 1 321 3 view .LVU1173 + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); + 3916 .loc 1 322 3 view .LVU1174 + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); + 3917 .loc 1 323 3 view .LVU1175 + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); + 3918 .loc 1 324 3 view .LVU1176 + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3919 .loc 1 325 3 view .LVU1177 + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3920 .loc 1 327 3 view .LVU1178 + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3921 .loc 1 329 5 view .LVU1179 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3922 .loc 1 332 3 view .LVU1180 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3923 .loc 1 332 11 is_stmt 0 view .LVU1181 + 3924 0010 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3925 .loc 1 332 5 view .LVU1182 + 3926 0014 002B cmp r3, #0 + 3927 0016 37D0 beq .L215 + 3928 .LVL275: + 3929 .L212: + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + 3930 .loc 1 363 3 is_stmt 1 view .LVU1183 + 3931 0018 2568 ldr r5, [r4] + 3932 001a 2A68 ldr r2, [r5] + 3933 001c 22F47062 bic r2, r2, #3840 + 3934 0020 A168 ldr r1, [r4, #8] + 3935 0022 0139 subs r1, r1, #1 + 3936 0024 42EA0122 orr r2, r2, r1, lsl #8 + 3937 0028 2A60 str r2, [r5] + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3938 .loc 1 367 3 view .LVU1184 + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3939 .loc 1 367 12 is_stmt 0 view .LVU1185 + 3940 002a A36C ldr r3, [r4, #72] + 3941 002c 0093 str r3, [sp] + ARM GAS /tmp/ccNpZKQO.s page 135 + + + 3942 002e 3346 mov r3, r6 + 3943 0030 0022 movs r2, #0 + 3944 0032 2021 movs r1, #32 + 3945 0034 2046 mov r0, r4 + 3946 0036 FFF7FEFF bl QSPI_WaitFlagStateUntilTimeout + 3947 .LVL276: + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3948 .loc 1 369 3 is_stmt 1 view .LVU1186 + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 3949 .loc 1 369 5 is_stmt 0 view .LVU1187 + 3950 003a 18BB cbnz r0, .L211 + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + 3951 .loc 1 372 5 is_stmt 1 view .LVU1188 + 3952 003c 2168 ldr r1, [r4] + 3953 003e 0B68 ldr r3, [r1] + 3954 0040 174A ldr r2, .L216 + 3955 0042 1A40 ands r2, r2, r3 + 3956 0044 6568 ldr r5, [r4, #4] + 3957 0046 E368 ldr r3, [r4, #12] + 3958 0048 43EA0563 orr r3, r3, r5, lsl #24 + 3959 004c E569 ldr r5, [r4, #28] + 3960 004e 2B43 orrs r3, r3, r5 + 3961 0050 256A ldr r5, [r4, #32] + 3962 0052 2B43 orrs r3, r3, r5 + 3963 0054 1343 orrs r3, r3, r2 + 3964 0056 0B60 str r3, [r1] + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + 3965 .loc 1 377 5 view .LVU1189 + 3966 0058 2168 ldr r1, [r4] + 3967 005a 4A68 ldr r2, [r1, #4] + 3968 005c 114B ldr r3, .L216+4 + 3969 005e 1340 ands r3, r3, r2 + 3970 0060 2569 ldr r5, [r4, #16] + 3971 0062 6269 ldr r2, [r4, #20] + 3972 0064 42EA0542 orr r2, r2, r5, lsl #16 + 3973 0068 A569 ldr r5, [r4, #24] + 3974 006a 2A43 orrs r2, r2, r5 + 3975 006c 1343 orrs r3, r3, r2 + 3976 006e 4B60 str r3, [r1, #4] + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3977 .loc 1 382 5 view .LVU1190 + 3978 0070 2268 ldr r2, [r4] + 3979 0072 1368 ldr r3, [r2] + 3980 0074 43F00103 orr r3, r3, #1 + 3981 0078 1360 str r3, [r2] + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3982 .loc 1 385 5 view .LVU1191 + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3983 .loc 1 385 22 is_stmt 0 view .LVU1192 + 3984 007a 0023 movs r3, #0 + 3985 007c 6364 str r3, [r4, #68] + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3986 .loc 1 388 5 is_stmt 1 view .LVU1193 + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 3987 .loc 1 388 18 is_stmt 0 view .LVU1194 + 3988 007e 0123 movs r3, #1 + 3989 0080 84F84130 strb r3, [r4, #65] + ARM GAS /tmp/ccNpZKQO.s page 136 + + + 3990 .LVL277: + 3991 .L211: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 3992 .loc 1 393 1 view .LVU1195 + 3993 0084 02B0 add sp, sp, #8 + 3994 .LCFI56: + 3995 .cfi_remember_state + 3996 .cfi_def_cfa_offset 16 + 3997 @ sp needed + 3998 0086 70BD pop {r4, r5, r6, pc} + 3999 .LVL278: + 4000 .L215: + 4001 .LCFI57: + 4002 .cfi_restore_state + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 4003 .loc 1 355 5 is_stmt 1 view .LVU1196 + 4004 0088 2046 mov r0, r4 + 4005 .LVL279: + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** #endif + 4006 .loc 1 355 5 is_stmt 0 view .LVU1197 + 4007 008a FFF7FEFF bl HAL_QSPI_MspInit + 4008 .LVL280: + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4009 .loc 1 359 5 is_stmt 1 view .LVU1198 + 4010 008e 41F28831 movw r1, #5000 + 4011 0092 2046 mov r0, r4 + 4012 0094 FFF7FEFF bl HAL_QSPI_SetTimeout + 4013 .LVL281: + 4014 0098 BEE7 b .L212 + 4015 .LVL282: + 4016 .L213: + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4017 .loc 1 314 12 is_stmt 0 view .LVU1199 + 4018 009a 0120 movs r0, #1 + 4019 .LVL283: + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4020 .loc 1 314 12 view .LVU1200 + 4021 009c F2E7 b .L211 + 4022 .L217: + 4023 009e 00BF .align 2 + 4024 .L216: + 4025 00a0 2FFFFF00 .word 16777007 + 4026 00a4 FEF8E0FF .word -2033410 + 4027 .cfi_endproc + 4028 .LFE141: + 4030 .section .text.HAL_QSPI_SetFifoThreshold,"ax",%progbits + 4031 .align 1 + 4032 .global HAL_QSPI_SetFifoThreshold + 4033 .syntax unified + 4034 .thumb + 4035 .thumb_func + 4036 .fpu fpv5-d16 + 4038 HAL_QSPI_SetFifoThreshold: + 4039 .LVL284: + 4040 .LFB170: +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 4041 .loc 1 2273 1 is_stmt 1 view -0 + ARM GAS /tmp/ccNpZKQO.s page 137 + + + 4042 .cfi_startproc + 4043 @ args = 0, pretend = 0, frame = 0 + 4044 @ frame_needed = 0, uses_anonymous_args = 0 + 4045 @ link register save eliminated. +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 4046 .loc 1 2273 1 is_stmt 0 view .LVU1202 + 4047 0000 0346 mov r3, r0 +2274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4048 .loc 1 2274 3 is_stmt 1 view .LVU1203 + 4049 .LVL285: +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4050 .loc 1 2277 3 view .LVU1204 +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4051 .loc 1 2277 3 view .LVU1205 + 4052 0002 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 4053 0006 D2B2 uxtb r2, r2 + 4054 0008 012A cmp r2, #1 + 4055 000a 17D0 beq .L221 +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4056 .loc 1 2277 3 discriminator 2 view .LVU1206 + 4057 000c 0122 movs r2, #1 + 4058 000e 80F84020 strb r2, [r0, #64] +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4059 .loc 1 2277 3 discriminator 2 view .LVU1207 +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 4060 .loc 1 2279 3 discriminator 2 view .LVU1208 +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 4061 .loc 1 2279 11 is_stmt 0 discriminator 2 view .LVU1209 + 4062 0012 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 4063 0016 D2B2 uxtb r2, r2 +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 4064 .loc 1 2279 5 discriminator 2 view .LVU1210 + 4065 0018 012A cmp r2, #1 + 4066 001a 04D0 beq .L223 +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4067 .loc 1 2290 12 view .LVU1211 + 4068 001c 0220 movs r0, #2 + 4069 .LVL286: + 4070 .L220: +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4071 .loc 1 2294 3 is_stmt 1 view .LVU1212 +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4072 .loc 1 2294 3 view .LVU1213 + 4073 001e 0022 movs r2, #0 + 4074 0020 83F84020 strb r2, [r3, #64] +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4075 .loc 1 2294 3 view .LVU1214 +2297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4076 .loc 1 2297 3 view .LVU1215 +2297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4077 .loc 1 2297 10 is_stmt 0 view .LVU1216 + 4078 0024 7047 bx lr + 4079 .LVL287: + 4080 .L223: +2282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4081 .loc 1 2282 5 is_stmt 1 view .LVU1217 +2282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + ARM GAS /tmp/ccNpZKQO.s page 138 + + + 4082 .loc 1 2282 31 is_stmt 0 view .LVU1218 + 4083 0026 8160 str r1, [r0, #8] +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + 4084 .loc 1 2285 5 is_stmt 1 view .LVU1219 + 4085 0028 0068 ldr r0, [r0] + 4086 .LVL288: +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + 4087 .loc 1 2285 5 is_stmt 0 view .LVU1220 + 4088 002a 0268 ldr r2, [r0] + 4089 002c 22F47062 bic r2, r2, #3840 + 4090 0030 0139 subs r1, r1, #1 + 4091 .LVL289: +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + 4092 .loc 1 2285 5 view .LVU1221 + 4093 0032 42EA0121 orr r1, r2, r1, lsl #8 + 4094 0036 0160 str r1, [r0] + 4095 .LVL290: +2274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4096 .loc 1 2274 21 view .LVU1222 + 4097 0038 0020 movs r0, #0 + 4098 003a F0E7 b .L220 + 4099 .LVL291: + 4100 .L221: +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4101 .loc 1 2277 3 view .LVU1223 + 4102 003c 0220 movs r0, #2 + 4103 .LVL292: +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4104 .loc 1 2298 1 view .LVU1224 + 4105 003e 7047 bx lr + 4106 .cfi_endproc + 4107 .LFE170: + 4109 .section .text.HAL_QSPI_GetFifoThreshold,"ax",%progbits + 4110 .align 1 + 4111 .global HAL_QSPI_GetFifoThreshold + 4112 .syntax unified + 4113 .thumb + 4114 .thumb_func + 4115 .fpu fpv5-d16 + 4117 HAL_QSPI_GetFifoThreshold: + 4118 .LVL293: + 4119 .LFB171: +2305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); + 4120 .loc 1 2305 1 is_stmt 1 view -0 + 4121 .cfi_startproc + 4122 @ args = 0, pretend = 0, frame = 0 + 4123 @ frame_needed = 0, uses_anonymous_args = 0 + 4124 @ link register save eliminated. +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4125 .loc 1 2306 3 view .LVU1226 +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4126 .loc 1 2306 12 is_stmt 0 view .LVU1227 + 4127 0000 0368 ldr r3, [r0] + 4128 0002 1868 ldr r0, [r3] + 4129 .LVL294: +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4130 .loc 1 2306 61 view .LVU1228 + ARM GAS /tmp/ccNpZKQO.s page 139 + + + 4131 0004 C0F30320 ubfx r0, r0, #8, #4 +2307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4132 .loc 1 2307 1 view .LVU1229 + 4133 0008 0130 adds r0, r0, #1 + 4134 000a 7047 bx lr + 4135 .cfi_endproc + 4136 .LFE171: + 4138 .section .text.HAL_QSPI_SetFlashID,"ax",%progbits + 4139 .align 1 + 4140 .global HAL_QSPI_SetFlashID + 4141 .syntax unified + 4142 .thumb + 4143 .thumb_func + 4144 .fpu fpv5-d16 + 4146 HAL_QSPI_SetFlashID: + 4147 .LVL295: + 4148 .LFB172: +2317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 4149 .loc 1 2317 1 is_stmt 1 view -0 + 4150 .cfi_startproc + 4151 @ args = 0, pretend = 0, frame = 0 + 4152 @ frame_needed = 0, uses_anonymous_args = 0 + 4153 @ link register save eliminated. +2317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** HAL_StatusTypeDef status = HAL_OK; + 4154 .loc 1 2317 1 is_stmt 0 view .LVU1231 + 4155 0000 0346 mov r3, r0 +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4156 .loc 1 2318 3 is_stmt 1 view .LVU1232 + 4157 .LVL296: +2321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4158 .loc 1 2321 3 view .LVU1233 +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4159 .loc 1 2324 3 view .LVU1234 +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4160 .loc 1 2324 3 view .LVU1235 + 4161 0002 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 4162 0006 D2B2 uxtb r2, r2 + 4163 0008 012A cmp r2, #1 + 4164 000a 15D0 beq .L228 +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4165 .loc 1 2324 3 discriminator 2 view .LVU1236 + 4166 000c 0122 movs r2, #1 + 4167 000e 80F84020 strb r2, [r0, #64] +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4168 .loc 1 2324 3 discriminator 2 view .LVU1237 +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 4169 .loc 1 2326 3 discriminator 2 view .LVU1238 +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 4170 .loc 1 2326 11 is_stmt 0 discriminator 2 view .LVU1239 + 4171 0012 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 4172 0016 D2B2 uxtb r2, r2 +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** { + 4173 .loc 1 2326 5 discriminator 2 view .LVU1240 + 4174 0018 012A cmp r2, #1 + 4175 001a 04D0 beq .L230 +2336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4176 .loc 1 2336 12 view .LVU1241 + ARM GAS /tmp/ccNpZKQO.s page 140 + + + 4177 001c 0220 movs r0, #2 + 4178 .LVL297: + 4179 .L227: +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4180 .loc 1 2340 3 is_stmt 1 view .LVU1242 +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4181 .loc 1 2340 3 view .LVU1243 + 4182 001e 0022 movs r2, #0 + 4183 0020 83F84020 strb r2, [r3, #64] +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4184 .loc 1 2340 3 view .LVU1244 +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4185 .loc 1 2343 3 view .LVU1245 +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4186 .loc 1 2343 10 is_stmt 0 view .LVU1246 + 4187 0024 7047 bx lr + 4188 .LVL298: + 4189 .L230: +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4190 .loc 1 2329 5 is_stmt 1 view .LVU1247 +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4191 .loc 1 2329 25 is_stmt 0 view .LVU1248 + 4192 0026 C161 str r1, [r0, #28] +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4193 .loc 1 2332 5 is_stmt 1 view .LVU1249 + 4194 0028 0068 ldr r0, [r0] + 4195 .LVL299: +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4196 .loc 1 2332 5 is_stmt 0 view .LVU1250 + 4197 002a 0268 ldr r2, [r0] + 4198 002c 22F08002 bic r2, r2, #128 + 4199 0030 1143 orrs r1, r1, r2 + 4200 .LVL300: +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** } + 4201 .loc 1 2332 5 view .LVU1251 + 4202 0032 0160 str r1, [r0] + 4203 .LVL301: +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4204 .loc 1 2318 21 view .LVU1252 + 4205 0034 0020 movs r0, #0 + 4206 0036 F2E7 b .L227 + 4207 .LVL302: + 4208 .L228: +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4209 .loc 1 2324 3 view .LVU1253 + 4210 0038 0220 movs r0, #2 + 4211 .LVL303: +2344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c **** + 4212 .loc 1 2344 1 view .LVU1254 + 4213 003a 7047 bx lr + 4214 .cfi_endproc + 4215 .LFE172: + 4217 .text + 4218 .Letext0: + 4219 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 4220 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 4221 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + ARM GAS /tmp/ccNpZKQO.s page 141 + + + 4222 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 4223 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 4224 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 4225 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" + 4226 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccNpZKQO.s page 142 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_qspi.c + /tmp/ccNpZKQO.s:17 .text.QSPI_DMARxCplt:0000000000000000 $t + /tmp/ccNpZKQO.s:24 .text.QSPI_DMARxCplt:0000000000000000 QSPI_DMARxCplt + /tmp/ccNpZKQO.s:54 .text.QSPI_DMATxCplt:0000000000000000 $t + /tmp/ccNpZKQO.s:60 .text.QSPI_DMATxCplt:0000000000000000 QSPI_DMATxCplt + /tmp/ccNpZKQO.s:89 .text.QSPI_Config:0000000000000000 $t + /tmp/ccNpZKQO.s:95 .text.QSPI_Config:0000000000000000 QSPI_Config + /tmp/ccNpZKQO.s:432 .text.QSPI_WaitFlagStateUntilTimeout:0000000000000000 $t + /tmp/ccNpZKQO.s:438 .text.QSPI_WaitFlagStateUntilTimeout:0000000000000000 QSPI_WaitFlagStateUntilTimeout + /tmp/ccNpZKQO.s:517 .text.HAL_QSPI_MspInit:0000000000000000 $t + /tmp/ccNpZKQO.s:524 .text.HAL_QSPI_MspInit:0000000000000000 HAL_QSPI_MspInit + /tmp/ccNpZKQO.s:539 .text.HAL_QSPI_MspDeInit:0000000000000000 $t + /tmp/ccNpZKQO.s:546 .text.HAL_QSPI_MspDeInit:0000000000000000 HAL_QSPI_MspDeInit + /tmp/ccNpZKQO.s:561 .text.HAL_QSPI_DeInit:0000000000000000 $t + /tmp/ccNpZKQO.s:568 .text.HAL_QSPI_DeInit:0000000000000000 HAL_QSPI_DeInit + /tmp/ccNpZKQO.s:618 .text.HAL_QSPI_Command:0000000000000000 $t + /tmp/ccNpZKQO.s:625 .text.HAL_QSPI_Command:0000000000000000 HAL_QSPI_Command + /tmp/ccNpZKQO.s:783 .text.HAL_QSPI_Command_IT:0000000000000000 $t + /tmp/ccNpZKQO.s:790 .text.HAL_QSPI_Command_IT:0000000000000000 HAL_QSPI_Command_IT + /tmp/ccNpZKQO.s:950 .text.HAL_QSPI_Transmit:0000000000000000 $t + /tmp/ccNpZKQO.s:957 .text.HAL_QSPI_Transmit:0000000000000000 HAL_QSPI_Transmit + /tmp/ccNpZKQO.s:1161 .text.HAL_QSPI_Receive:0000000000000000 $t + /tmp/ccNpZKQO.s:1168 .text.HAL_QSPI_Receive:0000000000000000 HAL_QSPI_Receive + /tmp/ccNpZKQO.s:1379 .text.HAL_QSPI_Transmit_IT:0000000000000000 $t + /tmp/ccNpZKQO.s:1386 .text.HAL_QSPI_Transmit_IT:0000000000000000 HAL_QSPI_Transmit_IT + /tmp/ccNpZKQO.s:1506 .text.HAL_QSPI_Receive_IT:0000000000000000 $t + /tmp/ccNpZKQO.s:1513 .text.HAL_QSPI_Receive_IT:0000000000000000 HAL_QSPI_Receive_IT + /tmp/ccNpZKQO.s:1659 .text.HAL_QSPI_Transmit_DMA:0000000000000000 $t + /tmp/ccNpZKQO.s:1666 .text.HAL_QSPI_Transmit_DMA:0000000000000000 HAL_QSPI_Transmit_DMA + /tmp/ccNpZKQO.s:1924 .text.HAL_QSPI_Transmit_DMA:0000000000000128 $d + /tmp/ccNpZKQO.s:3808 .text.QSPI_DMAError:0000000000000000 QSPI_DMAError + /tmp/ccNpZKQO.s:1932 .text.HAL_QSPI_Receive_DMA:0000000000000000 $t + /tmp/ccNpZKQO.s:1939 .text.HAL_QSPI_Receive_DMA:0000000000000000 HAL_QSPI_Receive_DMA + /tmp/ccNpZKQO.s:2210 .text.HAL_QSPI_Receive_DMA:0000000000000134 $d + /tmp/ccNpZKQO.s:2218 .text.HAL_QSPI_AutoPolling:0000000000000000 $t + /tmp/ccNpZKQO.s:2225 .text.HAL_QSPI_AutoPolling:0000000000000000 HAL_QSPI_AutoPolling + /tmp/ccNpZKQO.s:2400 .text.HAL_QSPI_AutoPolling_IT:0000000000000000 $t + /tmp/ccNpZKQO.s:2407 .text.HAL_QSPI_AutoPolling_IT:0000000000000000 HAL_QSPI_AutoPolling_IT + /tmp/ccNpZKQO.s:2578 .text.HAL_QSPI_MemoryMapped:0000000000000000 $t + /tmp/ccNpZKQO.s:2585 .text.HAL_QSPI_MemoryMapped:0000000000000000 HAL_QSPI_MemoryMapped + /tmp/ccNpZKQO.s:2741 .text.HAL_QSPI_ErrorCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2748 .text.HAL_QSPI_ErrorCallback:0000000000000000 HAL_QSPI_ErrorCallback + /tmp/ccNpZKQO.s:2763 .text.QSPI_DMAAbortCplt:0000000000000000 $t + /tmp/ccNpZKQO.s:2769 .text.QSPI_DMAAbortCplt:0000000000000000 QSPI_DMAAbortCplt + /tmp/ccNpZKQO.s:2833 .text.HAL_QSPI_AbortCpltCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2840 .text.HAL_QSPI_AbortCpltCallback:0000000000000000 HAL_QSPI_AbortCpltCallback + /tmp/ccNpZKQO.s:2855 .text.HAL_QSPI_CmdCpltCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2862 .text.HAL_QSPI_CmdCpltCallback:0000000000000000 HAL_QSPI_CmdCpltCallback + /tmp/ccNpZKQO.s:2877 .text.HAL_QSPI_RxCpltCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2884 .text.HAL_QSPI_RxCpltCallback:0000000000000000 HAL_QSPI_RxCpltCallback + /tmp/ccNpZKQO.s:2899 .text.HAL_QSPI_TxCpltCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2906 .text.HAL_QSPI_TxCpltCallback:0000000000000000 HAL_QSPI_TxCpltCallback + /tmp/ccNpZKQO.s:2921 .text.HAL_QSPI_FifoThresholdCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2928 .text.HAL_QSPI_FifoThresholdCallback:0000000000000000 HAL_QSPI_FifoThresholdCallback + /tmp/ccNpZKQO.s:2943 .text.HAL_QSPI_StatusMatchCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2950 .text.HAL_QSPI_StatusMatchCallback:0000000000000000 HAL_QSPI_StatusMatchCallback + ARM GAS /tmp/ccNpZKQO.s page 143 + + + /tmp/ccNpZKQO.s:2965 .text.HAL_QSPI_TimeOutCallback:0000000000000000 $t + /tmp/ccNpZKQO.s:2972 .text.HAL_QSPI_TimeOutCallback:0000000000000000 HAL_QSPI_TimeOutCallback + /tmp/ccNpZKQO.s:2987 .text.HAL_QSPI_IRQHandler:0000000000000000 $t + /tmp/ccNpZKQO.s:2994 .text.HAL_QSPI_IRQHandler:0000000000000000 HAL_QSPI_IRQHandler + /tmp/ccNpZKQO.s:3483 .text.HAL_QSPI_IRQHandler:000000000000023c $d + /tmp/ccNpZKQO.s:3488 .text.HAL_QSPI_GetState:0000000000000000 $t + /tmp/ccNpZKQO.s:3495 .text.HAL_QSPI_GetState:0000000000000000 HAL_QSPI_GetState + /tmp/ccNpZKQO.s:3513 .text.HAL_QSPI_GetError:0000000000000000 $t + /tmp/ccNpZKQO.s:3520 .text.HAL_QSPI_GetError:0000000000000000 HAL_QSPI_GetError + /tmp/ccNpZKQO.s:3538 .text.HAL_QSPI_Abort:0000000000000000 $t + /tmp/ccNpZKQO.s:3545 .text.HAL_QSPI_Abort:0000000000000000 HAL_QSPI_Abort + /tmp/ccNpZKQO.s:3682 .text.HAL_QSPI_Abort_IT:0000000000000000 $t + /tmp/ccNpZKQO.s:3689 .text.HAL_QSPI_Abort_IT:0000000000000000 HAL_QSPI_Abort_IT + /tmp/ccNpZKQO.s:3797 .text.HAL_QSPI_Abort_IT:0000000000000074 $d + /tmp/ccNpZKQO.s:3802 .text.QSPI_DMAError:0000000000000000 $t + /tmp/ccNpZKQO.s:3852 .text.HAL_QSPI_SetTimeout:0000000000000000 $t + /tmp/ccNpZKQO.s:3859 .text.HAL_QSPI_SetTimeout:0000000000000000 HAL_QSPI_SetTimeout + /tmp/ccNpZKQO.s:3876 .text.HAL_QSPI_Init:0000000000000000 $t + /tmp/ccNpZKQO.s:3883 .text.HAL_QSPI_Init:0000000000000000 HAL_QSPI_Init + /tmp/ccNpZKQO.s:4025 .text.HAL_QSPI_Init:00000000000000a0 $d + /tmp/ccNpZKQO.s:4031 .text.HAL_QSPI_SetFifoThreshold:0000000000000000 $t + /tmp/ccNpZKQO.s:4038 .text.HAL_QSPI_SetFifoThreshold:0000000000000000 HAL_QSPI_SetFifoThreshold + /tmp/ccNpZKQO.s:4110 .text.HAL_QSPI_GetFifoThreshold:0000000000000000 $t + /tmp/ccNpZKQO.s:4117 .text.HAL_QSPI_GetFifoThreshold:0000000000000000 HAL_QSPI_GetFifoThreshold + /tmp/ccNpZKQO.s:4139 .text.HAL_QSPI_SetFlashID:0000000000000000 $t + /tmp/ccNpZKQO.s:4146 .text.HAL_QSPI_SetFlashID:0000000000000000 HAL_QSPI_SetFlashID + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_MDMA_Start_IT +HAL_MDMA_Abort_IT +HAL_MDMA_Abort diff --git a/build/stm32h7xx_hal_qspi.o b/build/stm32h7xx_hal_qspi.o new file mode 100644 index 0000000..a56eb54 Binary files /dev/null and b/build/stm32h7xx_hal_qspi.o differ diff --git a/build/stm32h7xx_hal_rcc.d b/build/stm32h7xx_hal_rcc.d new file mode 100644 index 0000000..9d297d3 --- /dev/null +++ b/build/stm32h7xx_hal_rcc.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_rcc.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_rcc.lst b/build/stm32h7xx_hal_rcc.lst new file mode 100644 index 0000000..2530977 --- /dev/null +++ b/build/stm32h7xx_hal_rcc.lst @@ -0,0 +1,6112 @@ +ARM GAS /tmp/ccwNdrpc.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_rcc.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_RCC_DeInit,"ax",%progbits + 17 .align 1 + 18 .global HAL_RCC_DeInit + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_RCC_DeInit: + 26 .LFB141: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @file stm32h7xx_hal_rcc.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief RCC HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + Peripheral Control functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** @verbatim + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ============================================================================== + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ##### RCC specific features ##### + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** After reset the device is running from Internal High Speed oscillator + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** internal SRAM, Flash, JTAG and PWR + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** all peripherals mapped on these buses are running at HSI speed. + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) All GPIOs are in analogue mode , except the JTAG pins which + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** are assigned to be used for debug purpose. + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** Once the device started from reset, the user application has to: + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (if the application needs higher frequency/performance) + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) Configure the AHB and APB buses pre-scalers + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used + ARM GAS /tmp/ccwNdrpc.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) Configure the clock kernel source(s) for peripherals which clocks are not + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** and RCC_D3CCIPR registers + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ##### RCC Limitations ##### + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ============================================================================== + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** from/to registers. + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** after the clock enable bit is set on the hardware register + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** after the clock enable bit is set on the hardware register + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** Implemented Workaround: + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** @endverbatim + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ****************************************************************************** + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @attention + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * All rights reserved.

+ 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * This software component is licensed by ST under BSD 3-Clause license, + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * the "License"; You may not use this file except in compliance with the + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * License. You may obtain a copy of the License at: + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * opensource.org/licenses/BSD-3-Clause + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ****************************************************************************** + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #include "stm32h7xx_hal.h" + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @addtogroup STM32H7xx_HAL_Driver + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @defgroup RCC RCC + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief RCC HAL module driver + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + ARM GAS /tmp/ccwNdrpc.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #define MCO2_GPIO_PORT GPIOC + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #define MCO2_PIN GPIO_PIN_9 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @} + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @} + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Exported functions --------------------------------------------------------*/ + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Initialization and Configuration functions + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** @verbatim + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** =============================================================================== + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** =============================================================================== + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, A + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4). + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** the PLL as System clock source. + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) CSI is a low-power RC oscillator which can be used directly as system clock, periphera + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** clock, or PLL input.But even with frequency calibration, is less accurate than an + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** external crystal oscillator or ceramic resonator. + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** clock source. + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI), + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** featuring three different output clocks and able to work either in integer or Fractio + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** and to some peripherals. + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + ARM GAS /tmp/ccwNdrpc.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (HSE used directly or through PLL as System clock source), the System clock + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** is automatically switched to HSI and an interrupt is generated if enabled. + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt) + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** exception vector. + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q) + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** or HSI48 clock (through a configurable pre-scaler) on PA8 pin. + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK, + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin. + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI, + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HSE and PLL. + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System core clock through configurable + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pre-scaler and used to clock the CPU, memory and peripherals mapped + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** and used to clock the peripherals mapped on these buses. You can use + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** with dual clock domain where kernel source clock could be selected through + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers. + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines. + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** @endverbatim + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - HSI ON and used as system clock source + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - HSE, PLL1, PLL2 and PLL3 OFF + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - AHB, APB Bus pre-scaler set to 1. + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - CSS, MCO1 and MCO2 OFF + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - All interrupts disabled + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note This function doesn't modify the configuration of the + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - Peripheral clocks + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * - LSI, LSE and RTC clocks + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval HAL status + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 28 .loc 1 191 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 38B5 push {r3, r4, r5, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 16 + 35 .cfi_offset 3, -16 + 36 .cfi_offset 4, -12 + 37 .cfi_offset 5, -8 + 38 .cfi_offset 14, -4 + ARM GAS /tmp/ccwNdrpc.s page 5 + + + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t tickstart; + 39 .loc 1 192 3 view .LVU1 + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Increasing the CPU frequency */ + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + 40 .loc 1 195 3 view .LVU2 + 41 .loc 1 195 31 is_stmt 0 view .LVU3 + 42 0002 684B ldr r3, .L33 + 43 0004 1B68 ldr r3, [r3] + 44 0006 03F00F03 and r3, r3, #15 + 45 .loc 1 195 5 view .LVU4 + 46 000a 062B cmp r3, #6 + 47 000c 0CD8 bhi .L2 + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + 48 .loc 1 198 5 is_stmt 1 view .LVU5 + 49 000e 654A ldr r2, .L33 + 50 0010 1368 ldr r3, [r2] + 51 0012 23F00F03 bic r3, r3, #15 + 52 0016 43F00703 orr r3, r3, #7 + 53 001a 1360 str r3, [r2] + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + 54 .loc 1 202 5 view .LVU6 + 55 .loc 1 202 8 is_stmt 0 view .LVU7 + 56 001c 1368 ldr r3, [r2] + 57 001e 03F00F03 and r3, r3, #15 + 58 .loc 1 202 7 view .LVU8 + 59 0022 072B cmp r3, #7 + 60 0024 40F0BB80 bne .L16 + 61 .L2: + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick */ + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 62 .loc 1 211 3 is_stmt 1 view .LVU9 + 63 .loc 1 211 15 is_stmt 0 view .LVU10 + 64 0028 FFF7FEFF bl HAL_GetTick + 65 .LVL0: + 66 002c 0446 mov r4, r0 + 67 .LVL1: + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set HSION bit */ + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); + 68 .loc 1 214 3 is_stmt 1 view .LVU11 + 69 002e 5E4A ldr r2, .L33+4 + 70 0030 1368 ldr r3, [r2] + 71 0032 43F00103 orr r3, r3, #1 + 72 0036 1360 str r3, [r2] + ARM GAS /tmp/ccwNdrpc.s page 6 + + + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSI is ready */ + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 73 .loc 1 217 3 view .LVU12 + 74 .LVL2: + 75 .L4: + 76 .loc 1 217 9 view .LVU13 + 77 .loc 1 217 10 is_stmt 0 view .LVU14 + 78 0038 5B4B ldr r3, .L33+4 + 79 003a 1B68 ldr r3, [r3] + 80 .loc 1 217 9 view .LVU15 + 81 003c 13F0040F tst r3, #4 + 82 0040 06D1 bne .L26 + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 83 .loc 1 219 5 is_stmt 1 view .LVU16 + 84 .loc 1 219 10 is_stmt 0 view .LVU17 + 85 0042 FFF7FEFF bl HAL_GetTick + 86 .LVL3: + 87 .loc 1 219 24 view .LVU18 + 88 0046 001B subs r0, r0, r4 + 89 .loc 1 219 8 view .LVU19 + 90 0048 0228 cmp r0, #2 + 91 004a F5D9 bls .L4 + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 92 .loc 1 221 14 view .LVU20 + 93 004c 0324 movs r4, #3 + 94 .LVL4: + 95 .loc 1 221 14 view .LVU21 + 96 004e A7E0 b .L3 + 97 .LVL5: + 98 .L26: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set HSITRIM[6:0] bits to the reset value */ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); + 99 .loc 1 226 3 is_stmt 1 view .LVU22 + 100 0050 554B ldr r3, .L33+4 + 101 0052 5A68 ldr r2, [r3, #4] + 102 0054 42F08042 orr r2, r2, #1073741824 + 103 0058 5A60 str r2, [r3, #4] + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset CFGR register */ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); + 104 .loc 1 229 3 view .LVU23 + 105 005a 0022 movs r2, #0 + 106 005c 1A61 str r2, [r3, #16] + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Update the SystemCoreClock and SystemD2Clock global variables */ + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; + 107 .loc 1 232 3 view .LVU24 + 108 .loc 1 232 19 is_stmt 0 view .LVU25 + 109 005e 534B ldr r3, .L33+8 + 110 0060 534A ldr r2, .L33+12 + 111 0062 1360 str r3, [r2] + ARM GAS /tmp/ccwNdrpc.s page 7 + + + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemD2Clock = HSI_VALUE; + 112 .loc 1 233 3 is_stmt 1 view .LVU26 + 113 .loc 1 233 17 is_stmt 0 view .LVU27 + 114 0064 534A ldr r2, .L33+16 + 115 0066 1360 str r3, [r2] + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Adapt Systick interrupt period */ + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(HAL_InitTick(uwTickPrio) != HAL_OK) + 116 .loc 1 236 3 is_stmt 1 view .LVU28 + 117 .loc 1 236 6 is_stmt 0 view .LVU29 + 118 0068 534B ldr r3, .L33+20 + 119 006a 1868 ldr r0, [r3] + 120 006c FFF7FEFF bl HAL_InitTick + 121 .LVL6: + 122 .loc 1 236 5 view .LVU30 + 123 0070 0446 mov r4, r0 + 124 .LVL7: + 125 .loc 1 236 5 view .LVU31 + 126 0072 08B1 cbz r0, .L27 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 127 .loc 1 238 12 view .LVU32 + 128 0074 0124 movs r4, #1 + 129 0076 93E0 b .L3 + 130 .L27: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick */ + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 131 .loc 1 242 3 is_stmt 1 view .LVU33 + 132 .loc 1 242 15 is_stmt 0 view .LVU34 + 133 0078 FFF7FEFF bl HAL_GetTick + 134 .LVL8: + 135 007c 0546 mov r5, r0 + 136 .LVL9: + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till clock switch is ready */ + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + 137 .loc 1 245 3 is_stmt 1 view .LVU35 + 138 .L6: + 139 .loc 1 245 9 view .LVU36 + 140 .loc 1 245 10 is_stmt 0 view .LVU37 + 141 007e 4A4B ldr r3, .L33+4 + 142 0080 1B69 ldr r3, [r3, #16] + 143 .loc 1 245 9 view .LVU38 + 144 0082 13F0380F tst r3, #56 + 145 0086 08D0 beq .L28 + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 146 .loc 1 247 5 is_stmt 1 view .LVU39 + 147 .loc 1 247 10 is_stmt 0 view .LVU40 + 148 0088 FFF7FEFF bl HAL_GetTick + 149 .LVL10: + 150 .loc 1 247 24 view .LVU41 + 151 008c 401B subs r0, r0, r5 + 152 .loc 1 247 8 view .LVU42 + 153 008e 41F28833 movw r3, #5000 + ARM GAS /tmp/ccwNdrpc.s page 8 + + + 154 0092 9842 cmp r0, r3 + 155 0094 F3D9 bls .L6 + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 156 .loc 1 249 14 view .LVU43 + 157 0096 0324 movs r4, #3 + 158 0098 82E0 b .L3 + 159 .L28: + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick */ + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 160 .loc 1 254 3 is_stmt 1 view .LVU44 + 161 .loc 1 254 15 is_stmt 0 view .LVU45 + 162 009a FFF7FEFF bl HAL_GetTick + 163 .LVL11: + 164 009e 0546 mov r5, r0 + 165 .LVL12: + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | + 166 .loc 1 257 3 is_stmt 1 view .LVU46 + 167 00a0 414A ldr r2, .L33+4 + 168 00a2 1168 ldr r1, [r2] + 169 00a4 454B ldr r3, .L33+24 + 170 00a6 0B40 ands r3, r3, r1 + 171 00a8 1360 str r3, [r2] + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 172 .loc 1 261 3 view .LVU47 + 173 .LVL13: + 174 .L8: + 175 .loc 1 261 9 view .LVU48 + 176 .loc 1 261 10 is_stmt 0 view .LVU49 + 177 00aa 3F4B ldr r3, .L33+4 + 178 00ac 1B68 ldr r3, [r3] + 179 .loc 1 261 9 view .LVU50 + 180 00ae 13F4003F tst r3, #131072 + 181 00b2 07D0 beq .L29 + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 182 .loc 1 263 5 is_stmt 1 view .LVU51 + 183 .loc 1 263 10 is_stmt 0 view .LVU52 + 184 00b4 FFF7FEFF bl HAL_GetTick + 185 .LVL14: + 186 .loc 1 263 24 view .LVU53 + 187 00b8 401B subs r0, r0, r5 + 188 .loc 1 263 8 view .LVU54 + 189 00ba B0F57A7F cmp r0, #1000 + 190 00be F4D9 bls .L8 + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 191 .loc 1 265 14 view .LVU55 + 192 00c0 0324 movs r4, #3 + ARM GAS /tmp/ccwNdrpc.s page 9 + + + 193 00c2 6DE0 b .L3 + 194 .L29: + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick */ + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 195 .loc 1 270 3 is_stmt 1 view .LVU56 + 196 .loc 1 270 15 is_stmt 0 view .LVU57 + 197 00c4 FFF7FEFF bl HAL_GetTick + 198 .LVL15: + 199 00c8 0546 mov r5, r0 + 200 .LVL16: + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Clear PLLON bit */ + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + 201 .loc 1 273 3 is_stmt 1 view .LVU58 + 202 00ca 374A ldr r2, .L33+4 + 203 00cc 1368 ldr r3, [r2] + 204 00ce 23F08073 bic r3, r3, #16777216 + 205 00d2 1360 str r3, [r2] + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + 206 .loc 1 276 3 view .LVU59 + 207 .LVL17: + 208 .L10: + 209 .loc 1 276 9 view .LVU60 + 210 .loc 1 276 10 is_stmt 0 view .LVU61 + 211 00d4 344B ldr r3, .L33+4 + 212 00d6 1B68 ldr r3, [r3] + 213 .loc 1 276 9 view .LVU62 + 214 00d8 13F0007F tst r3, #33554432 + 215 00dc 06D0 beq .L30 + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 216 .loc 1 278 5 is_stmt 1 view .LVU63 + 217 .loc 1 278 10 is_stmt 0 view .LVU64 + 218 00de FFF7FEFF bl HAL_GetTick + 219 .LVL18: + 220 .loc 1 278 24 view .LVU65 + 221 00e2 401B subs r0, r0, r5 + 222 .loc 1 278 8 view .LVU66 + 223 00e4 0228 cmp r0, #2 + 224 00e6 F5D9 bls .L10 + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 225 .loc 1 280 14 view .LVU67 + 226 00e8 0324 movs r4, #3 + 227 00ea 59E0 b .L3 + 228 .L30: + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick */ + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 229 .loc 1 285 3 is_stmt 1 view .LVU68 + ARM GAS /tmp/ccwNdrpc.s page 10 + + + 230 .loc 1 285 15 is_stmt 0 view .LVU69 + 231 00ec FFF7FEFF bl HAL_GetTick + 232 .LVL19: + 233 00f0 0546 mov r5, r0 + 234 .LVL20: + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL2ON bit */ + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + 235 .loc 1 288 3 is_stmt 1 view .LVU70 + 236 00f2 2D4A ldr r2, .L33+4 + 237 00f4 1368 ldr r3, [r2] + 238 00f6 23F08063 bic r3, r3, #67108864 + 239 00fa 1360 str r3, [r2] + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till PLL2 is disabled */ + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + 240 .loc 1 291 3 view .LVU71 + 241 .LVL21: + 242 .L12: + 243 .loc 1 291 9 view .LVU72 + 244 .loc 1 291 10 is_stmt 0 view .LVU73 + 245 00fc 2A4B ldr r3, .L33+4 + 246 00fe 1B68 ldr r3, [r3] + 247 .loc 1 291 9 view .LVU74 + 248 0100 13F0006F tst r3, #134217728 + 249 0104 06D0 beq .L31 + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 250 .loc 1 293 5 is_stmt 1 view .LVU75 + 251 .loc 1 293 10 is_stmt 0 view .LVU76 + 252 0106 FFF7FEFF bl HAL_GetTick + 253 .LVL22: + 254 .loc 1 293 24 view .LVU77 + 255 010a 401B subs r0, r0, r5 + 256 .loc 1 293 8 view .LVU78 + 257 010c 0228 cmp r0, #2 + 258 010e F5D9 bls .L12 + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 259 .loc 1 295 14 view .LVU79 + 260 0110 0324 movs r4, #3 + 261 0112 45E0 b .L3 + 262 .L31: + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick */ + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 263 .loc 1 300 3 is_stmt 1 view .LVU80 + 264 .loc 1 300 15 is_stmt 0 view .LVU81 + 265 0114 FFF7FEFF bl HAL_GetTick + 266 .LVL23: + 267 0118 0546 mov r5, r0 + 268 .LVL24: + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL3 bit */ + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + ARM GAS /tmp/ccwNdrpc.s page 11 + + + 269 .loc 1 303 3 is_stmt 1 view .LVU82 + 270 011a 234A ldr r2, .L33+4 + 271 011c 1368 ldr r3, [r2] + 272 011e 23F08053 bic r3, r3, #268435456 + 273 0122 1360 str r3, [r2] + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till PLL3 is disabled */ + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + 274 .loc 1 306 3 view .LVU83 + 275 .LVL25: + 276 .L14: + 277 .loc 1 306 9 view .LVU84 + 278 .loc 1 306 10 is_stmt 0 view .LVU85 + 279 0124 204B ldr r3, .L33+4 + 280 0126 1B68 ldr r3, [r3] + 281 .loc 1 306 9 view .LVU86 + 282 0128 13F0005F tst r3, #536870912 + 283 012c 06D0 beq .L32 + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 284 .loc 1 308 5 is_stmt 1 view .LVU87 + 285 .loc 1 308 10 is_stmt 0 view .LVU88 + 286 012e FFF7FEFF bl HAL_GetTick + 287 .LVL26: + 288 .loc 1 308 24 view .LVU89 + 289 0132 401B subs r0, r0, r5 + 290 .loc 1 308 8 view .LVU90 + 291 0134 0228 cmp r0, #2 + 292 0136 F5D9 bls .L14 + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 293 .loc 1 310 14 view .LVU91 + 294 0138 0324 movs r4, #3 + 295 013a 31E0 b .L3 + 296 .L32: + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_HPRE) + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset D1CFGR register */ + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->D1CFGR); + 297 .loc 1 316 3 is_stmt 1 view .LVU92 + 298 013c 1A4B ldr r3, .L33+4 + 299 013e 0022 movs r2, #0 + 300 0140 9A61 str r2, [r3, #24] + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset D2CFGR register */ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->D2CFGR); + 301 .loc 1 319 3 view .LVU93 + 302 0142 DA61 str r2, [r3, #28] + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset D3CFGR register */ + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->D3CFGR); + 303 .loc 1 322 3 view .LVU94 + 304 0144 1A62 str r2, [r3, #32] + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset CDCFGR1 register */ + ARM GAS /tmp/ccwNdrpc.s page 12 + + + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->CDCFGR1); + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset CDCFGR2 register */ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->CDCFGR2); + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset SRDCFGR register */ + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->SRDCFGR); + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLLCKSELR register to default value */ + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5; + 305 .loc 1 335 3 view .LVU95 + 306 .loc 1 335 17 is_stmt 0 view .LVU96 + 307 0146 1E49 ldr r1, .L33+28 + 308 0148 9962 str r1, [r3, #40] + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLLCFGR register to default value */ + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** WRITE_REG(RCC->PLLCFGR, 0x01FF0000U); + 309 .loc 1 338 3 is_stmt 1 view .LVU97 + 310 014a 1E49 ldr r1, .L33+32 + 311 014c D962 str r1, [r3, #44] + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL1DIVR register to default value */ + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** WRITE_REG(RCC->PLL1DIVR,0x01010280U); + 312 .loc 1 341 3 view .LVU98 + 313 014e 1E49 ldr r1, .L33+36 + 314 0150 1963 str r1, [r3, #48] + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL1FRACR register */ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->PLL1FRACR); + 315 .loc 1 344 3 view .LVU99 + 316 0152 5A63 str r2, [r3, #52] + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL2DIVR register to default value */ + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** WRITE_REG(RCC->PLL2DIVR,0x01010280U); + 317 .loc 1 347 3 view .LVU100 + 318 0154 9963 str r1, [r3, #56] + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL2FRACR register */ + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->PLL2FRACR); + 319 .loc 1 350 3 view .LVU101 + 320 0156 DA63 str r2, [r3, #60] + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL3DIVR register to default value */ + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** WRITE_REG(RCC->PLL3DIVR,0x01010280U); + 321 .loc 1 353 3 view .LVU102 + 322 0158 1964 str r1, [r3, #64] + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset PLL3FRACR register */ + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->PLL3FRACR); + 323 .loc 1 356 3 view .LVU103 + 324 015a 5A64 str r2, [r3, #68] + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset HSEBYP bit */ + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 325 .loc 1 359 3 view .LVU104 + 326 015c 1968 ldr r1, [r3] + ARM GAS /tmp/ccwNdrpc.s page 13 + + + 327 015e 21F48021 bic r1, r1, #262144 + 328 0162 1960 str r1, [r3] + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable all interrupts */ + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_REG(RCC->CIER); + 329 .loc 1 362 3 view .LVU105 + 330 0164 1A66 str r2, [r3, #96] + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Clear all interrupts flags */ + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** WRITE_REG(RCC->CICR,0xFFFFFFFFU); + 331 .loc 1 365 3 view .LVU106 + 332 0166 4FF0FF32 mov r2, #-1 + 333 016a 9A66 str r2, [r3, #104] + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Reset all RSR flags */ + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SET_BIT(RCC->RSR, RCC_RSR_RMVF); + 334 .loc 1 368 3 view .LVU107 + 335 016c D3F8D020 ldr r2, [r3, #208] + 336 0170 42F48032 orr r2, r2, #65536 + 337 0174 C3F8D020 str r2, [r3, #208] + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + 338 .loc 1 371 3 view .LVU108 + 339 .loc 1 371 31 is_stmt 0 view .LVU109 + 340 0178 0A4B ldr r3, .L33 + 341 017a 1B68 ldr r3, [r3] + 342 .loc 1 371 5 view .LVU110 + 343 017c 13F0080F tst r3, #8 + 344 0180 0ED0 beq .L3 + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + 345 .loc 1 374 5 is_stmt 1 view .LVU111 + 346 0182 084A ldr r2, .L33 + 347 0184 1368 ldr r3, [r2] + 348 0186 23F00F03 bic r3, r3, #15 + 349 018a 43F00703 orr r3, r3, #7 + 350 018e 1360 str r3, [r2] + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + 351 .loc 1 378 5 view .LVU112 + 352 .loc 1 378 8 is_stmt 0 view .LVU113 + 353 0190 1368 ldr r3, [r2] + 354 0192 03F00F03 and r3, r3, #15 + 355 .loc 1 378 7 view .LVU114 + 356 0196 072B cmp r3, #7 + 357 0198 02D0 beq .L3 + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 358 .loc 1 380 14 view .LVU115 + 359 019a 0124 movs r4, #1 + 360 019c 00E0 b .L3 + 361 .LVL27: + 362 .L16: + ARM GAS /tmp/ccwNdrpc.s page 14 + + + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 363 .loc 1 204 14 view .LVU116 + 364 019e 0124 movs r4, #1 + 365 .L3: + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_OK; + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 366 .loc 1 386 1 view .LVU117 + 367 01a0 2046 mov r0, r4 + 368 01a2 38BD pop {r3, r4, r5, pc} + 369 .L34: + 370 .align 2 + 371 .L33: + 372 01a4 00200052 .word 1375739904 + 373 01a8 00440258 .word 1476543488 + 374 01ac 0090D003 .word 64000000 + 375 01b0 00000000 .word SystemCoreClock + 376 01b4 00000000 .word SystemD2Clock + 377 01b8 00000000 .word uwTickPrio + 378 01bc 45EDF6FF .word -594619 + 379 01c0 00020202 .word 33686016 + 380 01c4 0000FF01 .word 33488896 + 381 01c8 80020101 .word 16843392 + 382 .cfi_endproc + 383 .LFE141: + 385 .section .text.HAL_RCC_OscConfig,"ax",%progbits + 386 .align 1 + 387 .weak HAL_RCC_OscConfig + 388 .syntax unified + 389 .thumb + 390 .thumb_func + 391 .fpu fpv5-d16 + 393 HAL_RCC_OscConfig: + 394 .LVL28: + 395 .LFB142: + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * RCC_OscInitTypeDef. + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * supported by this function. User should request a transition to LSE Off + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * supported by this function. User should request a transition to HSE Off + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval HAL status + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 396 .loc 1 403 1 is_stmt 1 view -0 + 397 .cfi_startproc + ARM GAS /tmp/ccwNdrpc.s page 15 + + + 398 @ args = 0, pretend = 0, frame = 0 + 399 @ frame_needed = 0, uses_anonymous_args = 0 + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t tickstart; + 400 .loc 1 404 3 view .LVU119 + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t temp1_pllckcfg, temp2_pllckcfg; + 401 .loc 1 405 3 view .LVU120 + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check Null pointer */ + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(RCC_OscInitStruct == NULL) + 402 .loc 1 408 3 view .LVU121 + 403 .loc 1 408 5 is_stmt 0 view .LVU122 + 404 0000 0028 cmp r0, #0 + 405 0002 00F00483 beq .L107 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t tickstart; + 406 .loc 1 403 1 view .LVU123 + 407 0006 38B5 push {r3, r4, r5, lr} + 408 .LCFI1: + 409 .cfi_def_cfa_offset 16 + 410 .cfi_offset 3, -16 + 411 .cfi_offset 4, -12 + 412 .cfi_offset 5, -8 + 413 .cfi_offset 14, -4 + 414 0008 0446 mov r4, r0 + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 415 .loc 1 414 3 is_stmt 1 view .LVU124 + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 416 .loc 1 416 3 view .LVU125 + 417 .loc 1 416 25 is_stmt 0 view .LVU126 + 418 000a 0368 ldr r3, [r0] + 419 .loc 1 416 5 view .LVU127 + 420 000c 13F0010F tst r3, #1 + 421 0010 25D0 beq .L37 + 422 .LBB2: + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 423 .loc 1 419 5 is_stmt 1 view .LVU128 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 424 .loc 1 421 5 view .LVU129 + 425 .loc 1 421 37 is_stmt 0 view .LVU130 + 426 0012 9D4A ldr r2, .L159 + 427 0014 1369 ldr r3, [r2, #16] + 428 .loc 1 421 20 view .LVU131 + 429 0016 03F03803 and r3, r3, #56 + 430 .LVL29: + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** const uint32_t temp_pllckselr = RCC->PLLCKSELR; + 431 .loc 1 422 5 is_stmt 1 view .LVU132 + 432 .loc 1 422 20 is_stmt 0 view .LVU133 + 433 001a 926A ldr r2, [r2, #40] + 434 .LVL30: + ARM GAS /tmp/ccwNdrpc.s page 16 + + + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not dis + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pll + 435 .loc 1 424 5 is_stmt 1 view .LVU134 + 436 .loc 1 424 7 is_stmt 0 view .LVU135 + 437 001c 102B cmp r3, #16 + 438 001e 15D0 beq .L38 + 439 .loc 1 424 45 discriminator 1 view .LVU136 + 440 0020 182B cmp r3, #24 + 441 0022 0FD0 beq .L139 + 442 .LVL31: + 443 .L39: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 444 .loc 1 434 7 is_stmt 1 view .LVU137 + 445 .loc 1 434 7 view .LVU138 + 446 0024 6368 ldr r3, [r4, #4] + 447 .LVL32: + 448 .loc 1 434 7 is_stmt 0 view .LVU139 + 449 0026 B3F5803F cmp r3, #65536 + 450 002a 3FD0 beq .L140 + 451 .loc 1 434 7 is_stmt 1 discriminator 2 view .LVU140 + 452 002c 002B cmp r3, #0 + 453 002e 54D1 bne .L42 + 454 .loc 1 434 7 discriminator 4 view .LVU141 + 455 0030 954B ldr r3, .L159 + 456 0032 1A68 ldr r2, [r3] + 457 0034 22F48032 bic r2, r2, #65536 + 458 0038 1A60 str r2, [r3] + 459 .loc 1 434 7 discriminator 4 view .LVU142 + 460 003a 1A68 ldr r2, [r3] + 461 003c 22F48022 bic r2, r2, #262144 + 462 0040 1A60 str r2, [r3] + 463 0042 38E0 b .L41 + 464 .LVL33: + 465 .L139: + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 466 .loc 1 424 107 is_stmt 0 discriminator 2 view .LVU143 + 467 0044 02F00302 and r2, r2, #3 + 468 .LVL34: + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 469 .loc 1 424 87 discriminator 2 view .LVU144 + 470 0048 022A cmp r2, #2 + 471 004a EBD1 bne .L39 + 472 .L38: + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 473 .loc 1 426 7 is_stmt 1 view .LVU145 + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 474 .loc 1 426 11 is_stmt 0 view .LVU146 + 475 004c 8E4B ldr r3, .L159 + ARM GAS /tmp/ccwNdrpc.s page 17 + + + 476 .LVL35: + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 477 .loc 1 426 11 view .LVU147 + 478 004e 1B68 ldr r3, [r3] + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 479 .loc 1 426 9 view .LVU148 + 480 0050 13F4003F tst r3, #131072 + 481 0054 03D0 beq .L37 + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 482 .loc 1 426 75 discriminator 1 view .LVU149 + 483 0056 6368 ldr r3, [r4, #4] + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 484 .loc 1 426 54 discriminator 1 view .LVU150 + 485 0058 002B cmp r3, #0 + 486 005a 00F0DA82 beq .L141 + 487 .LVL36: + 488 .L37: + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 489 .loc 1 426 54 discriminator 1 view .LVU151 + 490 .LBE2: + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the HSE State */ + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSE is ready */ + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 491 .loc 1 468 3 is_stmt 1 view .LVU152 + 492 .loc 1 468 25 is_stmt 0 view .LVU153 + 493 005e 2368 ldr r3, [r4] + ARM GAS /tmp/ccwNdrpc.s page 18 + + + 494 .loc 1 468 5 view .LVU154 + 495 0060 13F0020F tst r3, #2 + 496 0064 00F08D80 beq .L49 + 497 .LBB3: + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 498 .loc 1 471 5 is_stmt 1 view .LVU155 + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 499 .loc 1 472 5 view .LVU156 + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* When the HSI is used as system clock it will not be disabled */ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 500 .loc 1 475 5 view .LVU157 + 501 .loc 1 475 37 is_stmt 0 view .LVU158 + 502 0068 874A ldr r2, .L159 + 503 006a 1369 ldr r3, [r2, #16] + 504 .LVL37: + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** const uint32_t temp_pllckselr = RCC->PLLCKSELR; + 505 .loc 1 476 5 is_stmt 1 view .LVU159 + 506 .loc 1 476 20 is_stmt 0 view .LVU160 + 507 006c 926A ldr r2, [r2, #40] + 508 .LVL38: + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pll + 509 .loc 1 477 5 is_stmt 1 view .LVU161 + 510 .loc 1 477 7 is_stmt 0 view .LVU162 + 511 006e 13F03803 ands r3, r3, #56 + 512 .LVL39: + 513 .loc 1 477 7 view .LVU163 + 514 0072 5CD0 beq .L50 + 515 .loc 1 477 45 discriminator 1 view .LVU164 + 516 0074 182B cmp r3, #24 + 517 0076 57D0 beq .L142 + 518 .L51: + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* When HSI is used as system clock it will not be disabled */ + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the HSI State */ + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 519 .loc 1 495 7 is_stmt 1 view .LVU165 + 520 .loc 1 495 28 is_stmt 0 view .LVU166 + 521 0078 E368 ldr r3, [r4, #12] + 522 .LVL40: + 523 .loc 1 495 9 view .LVU167 + ARM GAS /tmp/ccwNdrpc.s page 19 + + + 524 007a 002B cmp r3, #0 + 525 007c 00F0CA80 beq .L55 + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + 526 .loc 1 498 9 is_stmt 1 view .LVU168 + 527 0080 8149 ldr r1, .L159 + 528 0082 0A68 ldr r2, [r1] + 529 .LVL41: + 530 .loc 1 498 9 is_stmt 0 view .LVU169 + 531 0084 22F01902 bic r2, r2, #25 + 532 0088 1343 orrs r3, r3, r2 + 533 008a 0B60 str r3, [r1] + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 534 .loc 1 501 9 is_stmt 1 view .LVU170 + 535 .loc 1 501 21 is_stmt 0 view .LVU171 + 536 008c FFF7FEFF bl HAL_GetTick + 537 .LVL42: + 538 0090 0546 mov r5, r0 + 539 .LVL43: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSI is ready */ + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 540 .loc 1 504 9 is_stmt 1 view .LVU172 + 541 .L56: + 542 .loc 1 504 14 view .LVU173 + 543 .loc 1 504 15 is_stmt 0 view .LVU174 + 544 0092 7D4B ldr r3, .L159 + 545 0094 1B68 ldr r3, [r3] + 546 .loc 1 504 14 view .LVU175 + 547 0096 13F0040F tst r3, #4 + 548 009a 40F09980 bne .L143 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 549 .loc 1 506 11 is_stmt 1 view .LVU176 + 550 .loc 1 506 15 is_stmt 0 view .LVU177 + 551 009e FFF7FEFF bl HAL_GetTick + 552 .LVL44: + 553 .loc 1 506 29 view .LVU178 + 554 00a2 401B subs r0, r0, r5 + 555 .loc 1 506 13 view .LVU179 + 556 00a4 0228 cmp r0, #2 + 557 00a6 F4D9 bls .L56 + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 558 .loc 1 508 20 view .LVU180 + 559 00a8 0320 movs r0, #3 + 560 00aa B9E2 b .L36 + 561 .LVL45: + 562 .L140: + 563 .loc 1 508 20 view .LVU181 + 564 .LBE3: + 565 .LBB4: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 566 .loc 1 434 7 is_stmt 1 discriminator 1 view .LVU182 + ARM GAS /tmp/ccwNdrpc.s page 20 + + + 567 00ac 764A ldr r2, .L159 + 568 00ae 1368 ldr r3, [r2] + 569 00b0 43F48033 orr r3, r3, #65536 + 570 00b4 1360 str r3, [r2] + 571 .L41: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 572 .loc 1 434 7 discriminator 10 view .LVU183 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 573 .loc 1 437 7 discriminator 10 view .LVU184 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 574 .loc 1 437 27 is_stmt 0 discriminator 10 view .LVU185 + 575 00b6 6368 ldr r3, [r4, #4] + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 576 .loc 1 437 9 discriminator 10 view .LVU186 + 577 00b8 33B3 cbz r3, .L44 + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 578 .loc 1 440 9 is_stmt 1 view .LVU187 + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 579 .loc 1 440 21 is_stmt 0 view .LVU188 + 580 00ba FFF7FEFF bl HAL_GetTick + 581 .LVL46: + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 582 .loc 1 440 21 view .LVU189 + 583 00be 0546 mov r5, r0 + 584 .LVL47: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 585 .loc 1 443 9 is_stmt 1 view .LVU190 + 586 .L45: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 587 .loc 1 443 14 view .LVU191 + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 588 .loc 1 443 15 is_stmt 0 view .LVU192 + 589 00c0 714B ldr r3, .L159 + 590 00c2 1B68 ldr r3, [r3] + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 591 .loc 1 443 14 view .LVU193 + 592 00c4 13F4003F tst r3, #131072 + 593 00c8 C9D1 bne .L37 + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 594 .loc 1 445 11 is_stmt 1 view .LVU194 + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 595 .loc 1 445 26 is_stmt 0 view .LVU195 + 596 00ca FFF7FEFF bl HAL_GetTick + 597 .LVL48: + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 598 .loc 1 445 40 view .LVU196 + 599 00ce 401B subs r0, r0, r5 + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 600 .loc 1 445 13 view .LVU197 + 601 00d0 B0F57A7F cmp r0, #1000 + 602 00d4 F4D9 bls .L45 + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 603 .loc 1 447 20 view .LVU198 + 604 00d6 0320 movs r0, #3 + 605 00d8 A2E2 b .L36 + 606 .LVL49: + 607 .L42: + ARM GAS /tmp/ccwNdrpc.s page 21 + + + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 608 .loc 1 434 7 is_stmt 1 discriminator 5 view .LVU199 + 609 00da B3F5A02F cmp r3, #327680 + 610 00de 09D0 beq .L144 + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 611 .loc 1 434 7 discriminator 8 view .LVU200 + 612 00e0 694B ldr r3, .L159 + 613 00e2 1A68 ldr r2, [r3] + 614 00e4 22F48032 bic r2, r2, #65536 + 615 00e8 1A60 str r2, [r3] + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 616 .loc 1 434 7 discriminator 8 view .LVU201 + 617 00ea 1A68 ldr r2, [r3] + 618 00ec 22F48022 bic r2, r2, #262144 + 619 00f0 1A60 str r2, [r3] + 620 00f2 E0E7 b .L41 + 621 .L144: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 622 .loc 1 434 7 discriminator 7 view .LVU202 + 623 00f4 644B ldr r3, .L159 + 624 00f6 1A68 ldr r2, [r3] + 625 00f8 42F48022 orr r2, r2, #262144 + 626 00fc 1A60 str r2, [r3] + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 627 .loc 1 434 7 discriminator 7 view .LVU203 + 628 00fe 1A68 ldr r2, [r3] + 629 0100 42F48032 orr r2, r2, #65536 + 630 0104 1A60 str r2, [r3] + 631 0106 D6E7 b .L41 + 632 .L44: + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 633 .loc 1 454 9 view .LVU204 + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 634 .loc 1 454 21 is_stmt 0 view .LVU205 + 635 0108 FFF7FEFF bl HAL_GetTick + 636 .LVL50: + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 637 .loc 1 454 21 view .LVU206 + 638 010c 0546 mov r5, r0 + 639 .LVL51: + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 640 .loc 1 457 9 is_stmt 1 view .LVU207 + 641 .L47: + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 642 .loc 1 457 14 view .LVU208 + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 643 .loc 1 457 15 is_stmt 0 view .LVU209 + 644 010e 5E4B ldr r3, .L159 + 645 0110 1B68 ldr r3, [r3] + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 646 .loc 1 457 14 view .LVU210 + 647 0112 13F4003F tst r3, #131072 + 648 0116 A2D0 beq .L37 + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 649 .loc 1 459 11 is_stmt 1 view .LVU211 + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 650 .loc 1 459 26 is_stmt 0 view .LVU212 + ARM GAS /tmp/ccwNdrpc.s page 22 + + + 651 0118 FFF7FEFF bl HAL_GetTick + 652 .LVL52: + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 653 .loc 1 459 40 view .LVU213 + 654 011c 401B subs r0, r0, r5 + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 655 .loc 1 459 13 view .LVU214 + 656 011e B0F57A7F cmp r0, #1000 + 657 0122 F4D9 bls .L47 + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 658 .loc 1 461 20 view .LVU215 + 659 0124 0320 movs r0, #3 + 660 0126 7BE2 b .L36 + 661 .LVL53: + 662 .L142: + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 663 .loc 1 461 20 view .LVU216 + 664 .LBE4: + 665 .LBB5: + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 666 .loc 1 477 87 discriminator 2 view .LVU217 + 667 0128 12F0030F tst r2, #3 + 668 012c A4D1 bne .L51 + 669 .L50: + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 670 .loc 1 480 7 is_stmt 1 view .LVU218 + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 671 .loc 1 480 11 is_stmt 0 view .LVU219 + 672 012e 564B ldr r3, .L159 + 673 .LVL54: + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 674 .loc 1 480 11 view .LVU220 + 675 0130 1B68 ldr r3, [r3] + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 676 .loc 1 480 9 view .LVU221 + 677 0132 13F0040F tst r3, #4 + 678 0136 03D0 beq .L52 + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 679 .loc 1 480 75 discriminator 1 view .LVU222 + 680 0138 E368 ldr r3, [r4, #12] + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 681 .loc 1 480 54 discriminator 1 view .LVU223 + 682 013a 002B cmp r3, #0 + 683 013c 00F06B82 beq .L111 + 684 .L52: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 685 .loc 1 488 9 is_stmt 1 view .LVU224 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 686 .loc 1 488 9 view .LVU225 + 687 0140 FFF7FEFF bl HAL_GetREVID + 688 .LVL55: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 689 .loc 1 488 9 is_stmt 0 view .LVU226 + 690 0144 41F20303 movw r3, #4099 + 691 0148 9842 cmp r0, r3 + 692 014a 12D8 bhi .L53 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 23 + + + 693 .loc 1 488 9 is_stmt 1 discriminator 1 view .LVU227 + 694 014c 2269 ldr r2, [r4, #16] + 695 014e 402A cmp r2, #64 + 696 0150 07D0 beq .L145 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 697 .loc 1 488 9 discriminator 4 view .LVU228 + 698 0152 4D49 ldr r1, .L159 + 699 0154 4B68 ldr r3, [r1, #4] + 700 0156 23F47C33 bic r3, r3, #258048 + 701 015a 43EA0233 orr r3, r3, r2, lsl #12 + 702 015e 4B60 str r3, [r1, #4] + 703 0160 0FE0 b .L49 + 704 .L145: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 705 .loc 1 488 9 discriminator 3 view .LVU229 + 706 0162 494A ldr r2, .L159 + 707 0164 5368 ldr r3, [r2, #4] + 708 0166 23F47C33 bic r3, r3, #258048 + 709 016a 43F40033 orr r3, r3, #131072 + 710 016e 5360 str r3, [r2, #4] + 711 0170 07E0 b .L49 + 712 .L53: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 713 .loc 1 488 9 discriminator 2 view .LVU230 + 714 0172 454A ldr r2, .L159 + 715 0174 5368 ldr r3, [r2, #4] + 716 0176 23F0FE43 bic r3, r3, #2130706432 + 717 017a 2169 ldr r1, [r4, #16] + 718 017c 43EA0163 orr r3, r3, r1, lsl #24 + 719 0180 5360 str r3, [r2, #4] + 720 .L49: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 721 .loc 1 488 9 is_stmt 0 discriminator 2 view .LVU231 + 722 .LBE5: + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSI is disabled */ + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 24 + + + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*----------------------------- CSI Configuration --------------------------*/ + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + 723 .loc 1 535 3 is_stmt 1 view .LVU232 + 724 .loc 1 535 25 is_stmt 0 view .LVU233 + 725 0182 2368 ldr r3, [r4] + 726 .loc 1 535 5 view .LVU234 + 727 0184 13F0100F tst r3, #16 + 728 0188 00F08880 beq .L62 + 729 .LBB6: + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); + 730 .loc 1 538 5 is_stmt 1 view .LVU235 + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); + 731 .loc 1 539 5 view .LVU236 + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* When the CSI is used as system clock it will not disabled */ + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 732 .loc 1 542 5 view .LVU237 + 733 .loc 1 542 37 is_stmt 0 view .LVU238 + 734 018c 3E4A ldr r2, .L159 + 735 018e 1369 ldr r3, [r2, #16] + 736 .loc 1 542 20 view .LVU239 + 737 0190 03F03803 and r3, r3, #56 + 738 .LVL56: + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** const uint32_t temp_pllckselr = RCC->PLLCKSELR; + 739 .loc 1 543 5 is_stmt 1 view .LVU240 + 740 .loc 1 543 20 is_stmt 0 view .LVU241 + 741 0194 926A ldr r2, [r2, #40] + 742 .LVL57: + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pll + 743 .loc 1 544 5 is_stmt 1 view .LVU242 + 744 .loc 1 544 7 is_stmt 0 view .LVU243 + 745 0196 082B cmp r3, #8 + 746 0198 54D0 beq .L63 + 747 .loc 1 544 45 discriminator 1 view .LVU244 + 748 019a 182B cmp r3, #24 + 749 019c 4ED0 beq .L146 + 750 .LVL58: + 751 .L64: + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* When CSI is used as system clock it will not disabled */ + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON) + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + ARM GAS /tmp/ccwNdrpc.s page 25 + + + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the CSI State */ + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) + 752 .loc 1 561 7 is_stmt 1 view .LVU245 + 753 .loc 1 561 28 is_stmt 0 view .LVU246 + 754 019e E369 ldr r3, [r4, #28] + 755 .LVL59: + 756 .loc 1 561 9 view .LVU247 + 757 01a0 002B cmp r3, #0 + 758 01a2 00F0B880 beq .L68 + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (CSI). */ + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_CSI_ENABLE(); + 759 .loc 1 564 9 is_stmt 1 view .LVU248 + 760 01a6 384A ldr r2, .L159 + 761 01a8 1368 ldr r3, [r2] + 762 01aa 43F08003 orr r3, r3, #128 + 763 01ae 1360 str r3, [r2] + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 764 .loc 1 567 9 view .LVU249 + 765 .loc 1 567 21 is_stmt 0 view .LVU250 + 766 01b0 FFF7FEFF bl HAL_GetTick + 767 .LVL60: + 768 01b4 0546 mov r5, r0 + 769 .LVL61: + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till CSI is ready */ + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + 770 .loc 1 570 9 is_stmt 1 view .LVU251 + 771 .L69: + 772 .loc 1 570 14 view .LVU252 + 773 .loc 1 570 15 is_stmt 0 view .LVU253 + 774 01b6 344B ldr r3, .L159 + 775 01b8 1B68 ldr r3, [r3] + 776 .loc 1 570 14 view .LVU254 + 777 01ba 13F4807F tst r3, #256 + 778 01be 40F08880 bne .L147 + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) + 779 .loc 1 572 11 is_stmt 1 view .LVU255 + 780 .loc 1 572 15 is_stmt 0 view .LVU256 + 781 01c2 FFF7FEFF bl HAL_GetTick + 782 .LVL62: + 783 .loc 1 572 29 view .LVU257 + 784 01c6 401B subs r0, r0, r5 + 785 .loc 1 572 13 view .LVU258 + 786 01c8 0228 cmp r0, #2 + 787 01ca F4D9 bls .L69 + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 788 .loc 1 574 20 view .LVU259 + 789 01cc 0320 movs r0, #3 + 790 01ce 27E2 b .L36 + 791 .L143: + 792 .loc 1 574 20 view .LVU260 + 793 .LBE6: + ARM GAS /tmp/ccwNdrpc.s page 26 + + + 794 .LBB7: + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 795 .loc 1 513 9 is_stmt 1 view .LVU261 + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 796 .loc 1 513 9 view .LVU262 + 797 01d0 FFF7FEFF bl HAL_GetREVID + 798 .LVL63: + 799 01d4 41F20303 movw r3, #4099 + 800 01d8 9842 cmp r0, r3 + 801 01da 12D8 bhi .L58 + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 802 .loc 1 513 9 discriminator 1 view .LVU263 + 803 01dc 2269 ldr r2, [r4, #16] + 804 01de 402A cmp r2, #64 + 805 01e0 07D0 beq .L148 + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 806 .loc 1 513 9 discriminator 4 view .LVU264 + 807 01e2 2949 ldr r1, .L159 + 808 01e4 4B68 ldr r3, [r1, #4] + 809 01e6 23F47C33 bic r3, r3, #258048 + 810 01ea 43EA0233 orr r3, r3, r2, lsl #12 + 811 01ee 4B60 str r3, [r1, #4] + 812 01f0 C7E7 b .L49 + 813 .L148: + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 814 .loc 1 513 9 discriminator 3 view .LVU265 + 815 01f2 254A ldr r2, .L159 + 816 01f4 5368 ldr r3, [r2, #4] + 817 01f6 23F47C33 bic r3, r3, #258048 + 818 01fa 43F40033 orr r3, r3, #131072 + 819 01fe 5360 str r3, [r2, #4] + 820 0200 BFE7 b .L49 + 821 .L58: + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 822 .loc 1 513 9 discriminator 2 view .LVU266 + 823 0202 214A ldr r2, .L159 + 824 0204 5368 ldr r3, [r2, #4] + 825 0206 23F0FE43 bic r3, r3, #2130706432 + 826 020a 2169 ldr r1, [r4, #16] + 827 020c 43EA0163 orr r3, r3, r1, lsl #24 + 828 0210 5360 str r3, [r2, #4] + 829 0212 B6E7 b .L49 + 830 .LVL64: + 831 .L55: + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 832 .loc 1 518 9 view .LVU267 + 833 0214 1C4A ldr r2, .L159 + 834 .LVL65: + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 835 .loc 1 518 9 is_stmt 0 view .LVU268 + 836 0216 1368 ldr r3, [r2] + 837 0218 23F00103 bic r3, r3, #1 + 838 021c 1360 str r3, [r2] + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 839 .loc 1 521 9 is_stmt 1 view .LVU269 + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 840 .loc 1 521 21 is_stmt 0 view .LVU270 + ARM GAS /tmp/ccwNdrpc.s page 27 + + + 841 021e FFF7FEFF bl HAL_GetTick + 842 .LVL66: + 843 0222 0546 mov r5, r0 + 844 .LVL67: + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 845 .loc 1 524 9 is_stmt 1 view .LVU271 + 846 .L60: + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 847 .loc 1 524 14 view .LVU272 + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 848 .loc 1 524 15 is_stmt 0 view .LVU273 + 849 0224 184B ldr r3, .L159 + 850 0226 1B68 ldr r3, [r3] + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 851 .loc 1 524 14 view .LVU274 + 852 0228 13F0040F tst r3, #4 + 853 022c A9D0 beq .L49 + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 854 .loc 1 526 11 is_stmt 1 view .LVU275 + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 855 .loc 1 526 15 is_stmt 0 view .LVU276 + 856 022e FFF7FEFF bl HAL_GetTick + 857 .LVL68: + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 858 .loc 1 526 29 view .LVU277 + 859 0232 401B subs r0, r0, r5 + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 860 .loc 1 526 13 view .LVU278 + 861 0234 0228 cmp r0, #2 + 862 0236 F5D9 bls .L60 + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 863 .loc 1 528 20 view .LVU279 + 864 0238 0320 movs r0, #3 + 865 023a F1E1 b .L36 + 866 .LVL69: + 867 .L146: + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 868 .loc 1 528 20 view .LVU280 + 869 .LBE7: + 870 .LBB8: + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 871 .loc 1 544 107 discriminator 2 view .LVU281 + 872 023c 02F00302 and r2, r2, #3 + 873 .LVL70: + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 874 .loc 1 544 87 discriminator 2 view .LVU282 + 875 0240 012A cmp r2, #1 + 876 0242 ACD1 bne .L64 + 877 .L63: + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 878 .loc 1 547 7 is_stmt 1 view .LVU283 + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 879 .loc 1 547 11 is_stmt 0 view .LVU284 + 880 0244 104B ldr r3, .L159 + 881 .LVL71: + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 882 .loc 1 547 11 view .LVU285 + ARM GAS /tmp/ccwNdrpc.s page 28 + + + 883 0246 1B68 ldr r3, [r3] + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 884 .loc 1 547 9 view .LVU286 + 885 0248 13F4807F tst r3, #256 + 886 024c 03D0 beq .L65 + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 887 .loc 1 547 75 discriminator 1 view .LVU287 + 888 024e E369 ldr r3, [r4, #28] + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 889 .loc 1 547 54 discriminator 1 view .LVU288 + 890 0250 802B cmp r3, #128 + 891 0252 40F0E281 bne .L114 + 892 .L65: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 893 .loc 1 555 9 is_stmt 1 view .LVU289 + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 894 .loc 1 555 9 view .LVU290 + 895 0256 FFF7FEFF bl HAL_GetREVID + 896 .LVL72: + 897 025a 41F20303 movw r3, #4099 + 898 025e 9842 cmp r0, r3 + 899 0260 14D8 bhi .L66 + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 900 .loc 1 555 9 discriminator 1 view .LVU291 + 901 0262 226A ldr r2, [r4, #32] + 902 0264 202A cmp r2, #32 + 903 0266 07D0 beq .L149 + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 904 .loc 1 555 9 discriminator 4 view .LVU292 + 905 0268 0749 ldr r1, .L159 + 906 026a 4B68 ldr r3, [r1, #4] + 907 026c 23F0F843 bic r3, r3, #2080374784 + 908 0270 43EA8263 orr r3, r3, r2, lsl #26 + 909 0274 4B60 str r3, [r1, #4] + 910 0276 11E0 b .L62 + 911 .L149: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 912 .loc 1 555 9 discriminator 3 view .LVU293 + 913 0278 034A ldr r2, .L159 + 914 027a 5368 ldr r3, [r2, #4] + 915 027c 23F0F843 bic r3, r3, #2080374784 + 916 0280 43F08043 orr r3, r3, #1073741824 + 917 0284 5360 str r3, [r2, #4] + 918 0286 09E0 b .L62 + 919 .L160: + 920 .align 2 + 921 .L159: + 922 0288 00440258 .word 1476543488 + 923 .L66: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 924 .loc 1 555 9 discriminator 2 view .LVU294 + 925 028c 9A4A ldr r2, .L161 + 926 028e D368 ldr r3, [r2, #12] + 927 0290 23F07C53 bic r3, r3, #1056964608 + 928 0294 216A ldr r1, [r4, #32] + 929 0296 43EA0163 orr r3, r3, r1, lsl #24 + 930 029a D360 str r3, [r2, #12] + ARM GAS /tmp/ccwNdrpc.s page 29 + + + 931 .L62: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 932 .loc 1 555 9 is_stmt 0 discriminator 2 view .LVU295 + 933 .LBE8: + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (CSI). */ + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_CSI_DISABLE(); + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till CSI is disabled */ + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 934 .loc 1 601 3 is_stmt 1 view .LVU296 + 935 .loc 1 601 25 is_stmt 0 view .LVU297 + 936 029c 2368 ldr r3, [r4] + 937 .loc 1 601 5 view .LVU298 + 938 029e 13F0080F tst r3, #8 + 939 02a2 60D0 beq .L75 + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + 940 .loc 1 604 5 is_stmt 1 view .LVU299 + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSI State */ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 941 .loc 1 607 5 view .LVU300 + 942 .loc 1 607 26 is_stmt 0 view .LVU301 + 943 02a4 6369 ldr r3, [r4, #20] + 944 .loc 1 607 7 view .LVU302 + 945 02a6 002B cmp r3, #0 + 946 02a8 49D0 beq .L76 + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); + 947 .loc 1 610 7 is_stmt 1 view .LVU303 + 948 02aa 934A ldr r2, .L161 + 949 02ac 536F ldr r3, [r2, #116] + 950 02ae 43F00103 orr r3, r3, #1 + ARM GAS /tmp/ccwNdrpc.s page 30 + + + 951 02b2 5367 str r3, [r2, #116] + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 952 .loc 1 613 7 view .LVU304 + 953 .loc 1 613 19 is_stmt 0 view .LVU305 + 954 02b4 FFF7FEFF bl HAL_GetTick + 955 .LVL73: + 956 02b8 0546 mov r5, r0 + 957 .LVL74: + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till LSI is ready */ + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 958 .loc 1 616 7 is_stmt 1 view .LVU306 + 959 .L77: + 960 .loc 1 616 12 view .LVU307 + 961 .loc 1 616 13 is_stmt 0 view .LVU308 + 962 02ba 8F4B ldr r3, .L161 + 963 02bc 5B6F ldr r3, [r3, #116] + 964 .loc 1 616 12 view .LVU309 + 965 02be 13F0020F tst r3, #2 + 966 02c2 50D1 bne .L75 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 967 .loc 1 618 9 is_stmt 1 view .LVU310 + 968 .loc 1 618 13 is_stmt 0 view .LVU311 + 969 02c4 FFF7FEFF bl HAL_GetTick + 970 .LVL75: + 971 .loc 1 618 27 view .LVU312 + 972 02c8 401B subs r0, r0, r5 + 973 .loc 1 618 11 view .LVU313 + 974 02ca 0228 cmp r0, #2 + 975 02cc F5D9 bls .L77 + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 976 .loc 1 620 18 view .LVU314 + 977 02ce 0320 movs r0, #3 + 978 02d0 A6E1 b .L36 + 979 .L147: + 980 .LBB9: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 981 .loc 1 579 9 is_stmt 1 view .LVU315 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 982 .loc 1 579 9 view .LVU316 + 983 02d2 FFF7FEFF bl HAL_GetREVID + 984 .LVL76: + 985 02d6 41F20303 movw r3, #4099 + 986 02da 9842 cmp r0, r3 + 987 02dc 12D8 bhi .L71 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 988 .loc 1 579 9 discriminator 1 view .LVU317 + 989 02de 226A ldr r2, [r4, #32] + 990 02e0 202A cmp r2, #32 + 991 02e2 07D0 beq .L150 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 992 .loc 1 579 9 discriminator 4 view .LVU318 + 993 02e4 8449 ldr r1, .L161 + ARM GAS /tmp/ccwNdrpc.s page 31 + + + 994 02e6 4B68 ldr r3, [r1, #4] + 995 02e8 23F0F843 bic r3, r3, #2080374784 + 996 02ec 43EA8263 orr r3, r3, r2, lsl #26 + 997 02f0 4B60 str r3, [r1, #4] + 998 02f2 D3E7 b .L62 + 999 .L150: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1000 .loc 1 579 9 discriminator 3 view .LVU319 + 1001 02f4 804A ldr r2, .L161 + 1002 02f6 5368 ldr r3, [r2, #4] + 1003 02f8 23F0F843 bic r3, r3, #2080374784 + 1004 02fc 43F08043 orr r3, r3, #1073741824 + 1005 0300 5360 str r3, [r2, #4] + 1006 0302 CBE7 b .L62 + 1007 .L71: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1008 .loc 1 579 9 discriminator 2 view .LVU320 + 1009 0304 7C4A ldr r2, .L161 + 1010 0306 D368 ldr r3, [r2, #12] + 1011 0308 23F07C53 bic r3, r3, #1056964608 + 1012 030c 216A ldr r1, [r4, #32] + 1013 030e 43EA0163 orr r3, r3, r1, lsl #24 + 1014 0312 D360 str r3, [r2, #12] + 1015 0314 C2E7 b .L62 + 1016 .LVL77: + 1017 .L68: + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1018 .loc 1 584 9 view .LVU321 + 1019 0316 784A ldr r2, .L161 + 1020 0318 1368 ldr r3, [r2] + 1021 031a 23F08003 bic r3, r3, #128 + 1022 031e 1360 str r3, [r2] + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1023 .loc 1 587 9 view .LVU322 + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1024 .loc 1 587 21 is_stmt 0 view .LVU323 + 1025 0320 FFF7FEFF bl HAL_GetTick + 1026 .LVL78: + 1027 0324 0546 mov r5, r0 + 1028 .LVL79: + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1029 .loc 1 590 9 is_stmt 1 view .LVU324 + 1030 .L73: + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1031 .loc 1 590 14 view .LVU325 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1032 .loc 1 590 15 is_stmt 0 view .LVU326 + 1033 0326 744B ldr r3, .L161 + 1034 0328 1B68 ldr r3, [r3] + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1035 .loc 1 590 14 view .LVU327 + 1036 032a 13F4807F tst r3, #256 + 1037 032e B5D0 beq .L62 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1038 .loc 1 592 11 is_stmt 1 view .LVU328 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1039 .loc 1 592 15 is_stmt 0 view .LVU329 + ARM GAS /tmp/ccwNdrpc.s page 32 + + + 1040 0330 FFF7FEFF bl HAL_GetTick + 1041 .LVL80: + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1042 .loc 1 592 29 view .LVU330 + 1043 0334 401B subs r0, r0, r5 + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1044 .loc 1 592 13 view .LVU331 + 1045 0336 0228 cmp r0, #2 + 1046 0338 F5D9 bls .L73 + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1047 .loc 1 594 20 view .LVU332 + 1048 033a 0320 movs r0, #3 + 1049 033c 70E1 b .L36 + 1050 .LVL81: + 1051 .L76: + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1052 .loc 1 594 20 view .LVU333 + 1053 .LBE9: + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); + 1054 .loc 1 627 7 is_stmt 1 view .LVU334 + 1055 033e 6E4A ldr r2, .L161 + 1056 0340 536F ldr r3, [r2, #116] + 1057 0342 23F00103 bic r3, r3, #1 + 1058 0346 5367 str r3, [r2, #116] + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1059 .loc 1 630 7 view .LVU335 + 1060 .loc 1 630 19 is_stmt 0 view .LVU336 + 1061 0348 FFF7FEFF bl HAL_GetTick + 1062 .LVL82: + 1063 034c 0546 mov r5, r0 + 1064 .LVL83: + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till LSI is ready */ + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 1065 .loc 1 633 7 is_stmt 1 view .LVU337 + 1066 .L79: + 1067 .loc 1 633 12 view .LVU338 + 1068 .loc 1 633 13 is_stmt 0 view .LVU339 + 1069 034e 6A4B ldr r3, .L161 + 1070 0350 5B6F ldr r3, [r3, #116] + 1071 .loc 1 633 12 view .LVU340 + 1072 0352 13F0020F tst r3, #2 + 1073 0356 06D0 beq .L75 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 1074 .loc 1 635 9 is_stmt 1 view .LVU341 + 1075 .loc 1 635 13 is_stmt 0 view .LVU342 + 1076 0358 FFF7FEFF bl HAL_GetTick + 1077 .LVL84: + ARM GAS /tmp/ccwNdrpc.s page 33 + + + 1078 .loc 1 635 27 view .LVU343 + 1079 035c 401B subs r0, r0, r5 + 1080 .loc 1 635 11 view .LVU344 + 1081 035e 0228 cmp r0, #2 + 1082 0360 F5D9 bls .L79 + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 1083 .loc 1 637 18 view .LVU345 + 1084 0362 0320 movs r0, #3 + 1085 0364 5CE1 b .L36 + 1086 .LVL85: + 1087 .L75: + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*------------------------------ HSI48 Configuration -------------------------*/ + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 1088 .loc 1 644 3 is_stmt 1 view .LVU346 + 1089 .loc 1 644 25 is_stmt 0 view .LVU347 + 1090 0366 2368 ldr r3, [r4] + 1091 .loc 1 644 5 view .LVU348 + 1092 0368 13F0200F tst r3, #32 + 1093 036c 29D0 beq .L81 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + 1094 .loc 1 647 5 is_stmt 1 view .LVU349 + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the HSI48 State */ + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) + 1095 .loc 1 650 5 view .LVU350 + 1096 .loc 1 650 26 is_stmt 0 view .LVU351 + 1097 036e A369 ldr r3, [r4, #24] + 1098 .loc 1 650 7 view .LVU352 + 1099 0370 9BB1 cbz r3, .L82 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (HSI48). */ + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSI48_ENABLE(); + 1100 .loc 1 653 7 is_stmt 1 view .LVU353 + 1101 0372 614A ldr r2, .L161 + 1102 0374 1368 ldr r3, [r2] + 1103 0376 43F48053 orr r3, r3, #4096 + 1104 037a 1360 str r3, [r2] + 1105 .loc 1 653 31 view .LVU354 + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get time-out */ + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1106 .loc 1 656 7 view .LVU355 + 1107 .loc 1 656 19 is_stmt 0 view .LVU356 + 1108 037c FFF7FEFF bl HAL_GetTick + 1109 .LVL86: + 1110 0380 0546 mov r5, r0 + 1111 .LVL87: + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSI48 is ready */ + ARM GAS /tmp/ccwNdrpc.s page 34 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + 1112 .loc 1 659 7 is_stmt 1 view .LVU357 + 1113 .L83: + 1114 .loc 1 659 12 view .LVU358 + 1115 .loc 1 659 13 is_stmt 0 view .LVU359 + 1116 0382 5D4B ldr r3, .L161 + 1117 0384 1B68 ldr r3, [r3] + 1118 .loc 1 659 12 view .LVU360 + 1119 0386 13F4005F tst r3, #8192 + 1120 038a 1AD1 bne .L81 + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) + 1121 .loc 1 661 9 is_stmt 1 view .LVU361 + 1122 .loc 1 661 13 is_stmt 0 view .LVU362 + 1123 038c FFF7FEFF bl HAL_GetTick + 1124 .LVL88: + 1125 .loc 1 661 27 view .LVU363 + 1126 0390 401B subs r0, r0, r5 + 1127 .loc 1 661 11 view .LVU364 + 1128 0392 0228 cmp r0, #2 + 1129 0394 F5D9 bls .L83 + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 1130 .loc 1 663 18 view .LVU365 + 1131 0396 0320 movs r0, #3 + 1132 0398 42E1 b .L36 + 1133 .LVL89: + 1134 .L82: + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (HSI48). */ + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_HSI48_DISABLE(); + 1135 .loc 1 670 7 is_stmt 1 view .LVU366 + 1136 039a 574A ldr r2, .L161 + 1137 039c 1368 ldr r3, [r2] + 1138 039e 23F48053 bic r3, r3, #4096 + 1139 03a2 1360 str r3, [r2] + 1140 .loc 1 670 32 view .LVU367 + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get time-out */ + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1141 .loc 1 673 7 view .LVU368 + 1142 .loc 1 673 19 is_stmt 0 view .LVU369 + 1143 03a4 FFF7FEFF bl HAL_GetTick + 1144 .LVL90: + 1145 03a8 0546 mov r5, r0 + 1146 .LVL91: + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till HSI48 is ready */ + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + 1147 .loc 1 676 7 is_stmt 1 view .LVU370 + 1148 .L85: + 1149 .loc 1 676 12 view .LVU371 + 1150 .loc 1 676 13 is_stmt 0 view .LVU372 + ARM GAS /tmp/ccwNdrpc.s page 35 + + + 1151 03aa 534B ldr r3, .L161 + 1152 03ac 1B68 ldr r3, [r3] + 1153 .loc 1 676 12 view .LVU373 + 1154 03ae 13F4005F tst r3, #8192 + 1155 03b2 06D0 beq .L81 + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) + 1156 .loc 1 678 9 is_stmt 1 view .LVU374 + 1157 .loc 1 678 13 is_stmt 0 view .LVU375 + 1158 03b4 FFF7FEFF bl HAL_GetTick + 1159 .LVL92: + 1160 .loc 1 678 27 view .LVU376 + 1161 03b8 401B subs r0, r0, r5 + 1162 .loc 1 678 11 view .LVU377 + 1163 03ba 0228 cmp r0, #2 + 1164 03bc F5D9 bls .L85 + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 1165 .loc 1 680 18 view .LVU378 + 1166 03be 0320 movs r0, #3 + 1167 03c0 2EE1 b .L36 + 1168 .LVL93: + 1169 .L81: + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 1170 .loc 1 686 3 is_stmt 1 view .LVU379 + 1171 .loc 1 686 25 is_stmt 0 view .LVU380 + 1172 03c2 2368 ldr r3, [r4] + 1173 .loc 1 686 5 view .LVU381 + 1174 03c4 13F0040F tst r3, #4 + 1175 03c8 21D1 bne .L151 + 1176 .L87: + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable write access to Backup domain */ + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** PWR->CR1 |= PWR_CR1_DBP; + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while((PWR->CR1 & PWR_CR1_DBP) == 0U) + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + ARM GAS /tmp/ccwNdrpc.s page 36 + + + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till LSE is ready */ + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till LSE is disabled */ + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 1177 .loc 1 739 3 is_stmt 1 view .LVU382 + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 1178 .loc 1 740 3 view .LVU383 + 1179 .loc 1 740 30 is_stmt 0 view .LVU384 + 1180 03ca 636A ldr r3, [r4, #36] + 1181 .loc 1 740 6 view .LVU385 + 1182 03cc 002B cmp r3, #0 + 1183 03ce 00F02681 beq .L124 + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) + 1184 .loc 1 743 5 is_stmt 1 view .LVU386 + 1185 .loc 1 743 8 is_stmt 0 view .LVU387 + 1186 03d2 494A ldr r2, .L161 + 1187 03d4 1269 ldr r2, [r2, #16] + 1188 03d6 02F03802 and r2, r2, #56 + 1189 .loc 1 743 7 view .LVU388 + 1190 03da 182A cmp r2, #24 + 1191 03dc 00F0EE80 beq .L99 + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 1192 .loc 1 745 7 is_stmt 1 view .LVU389 + 1193 .loc 1 745 9 is_stmt 0 view .LVU390 + 1194 03e0 022B cmp r3, #2 + 1195 03e2 75D0 beq .L152 + ARM GAS /tmp/ccwNdrpc.s page 37 + + + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable the main PLL. */ + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Configure the main PLL clock source, multiplication and division factors. */ + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN, + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP, + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ, + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR); + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable PLLFRACN . */ + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLLFRACN_DISABLE(); + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Configure PLL PLL1FRACN */ + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Select PLL1 input reference frequency range: VCI */ + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Select PLL1 output frequency range : VCO */ + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable PLL System Clock output. */ + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable PLL1Q Clock output. */ + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable PLL1R Clock output. */ + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable PLL1FRACN . */ + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLLFRACN_ENABLE(); + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + ARM GAS /tmp/ccwNdrpc.s page 38 + + + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Enable the main PLL. */ + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till PLL is ready */ + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Disable the main PLL. */ + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 1196 .loc 1 821 9 is_stmt 1 view .LVU391 + 1197 03e4 444A ldr r2, .L161 + 1198 03e6 1368 ldr r3, [r2] + 1199 03e8 23F08073 bic r3, r3, #16777216 + 1200 03ec 1360 str r3, [r2] + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1201 .loc 1 824 9 view .LVU392 + 1202 .loc 1 824 21 is_stmt 0 view .LVU393 + 1203 03ee FFF7FEFF bl HAL_GetTick + 1204 .LVL94: + 1205 03f2 0446 mov r4, r0 + 1206 .LVL95: + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 1207 .loc 1 827 9 is_stmt 1 view .LVU394 + 1208 .L105: + 1209 .loc 1 827 14 view .LVU395 + 1210 .loc 1 827 15 is_stmt 0 view .LVU396 + 1211 03f4 404B ldr r3, .L161 + 1212 03f6 1B68 ldr r3, [r3] + 1213 .loc 1 827 14 view .LVU397 + 1214 03f8 13F0007F tst r3, #33554432 + 1215 03fc 00F0DC80 beq .L153 + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 1216 .loc 1 829 11 is_stmt 1 view .LVU398 + 1217 .loc 1 829 15 is_stmt 0 view .LVU399 + 1218 0400 FFF7FEFF bl HAL_GetTick + 1219 .LVL96: + 1220 .loc 1 829 29 view .LVU400 + 1221 0404 001B subs r0, r0, r4 + 1222 .loc 1 829 13 view .LVU401 + 1223 0406 0228 cmp r0, #2 + 1224 0408 F4D9 bls .L105 + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + ARM GAS /tmp/ccwNdrpc.s page 39 + + + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; + 1225 .loc 1 831 20 view .LVU402 + 1226 040a 0320 movs r0, #3 + 1227 040c 08E1 b .L36 + 1228 .LVL97: + 1229 .L151: + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1230 .loc 1 689 5 is_stmt 1 view .LVU403 + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1231 .loc 1 692 5 view .LVU404 + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1232 .loc 1 692 14 is_stmt 0 view .LVU405 + 1233 040e 3B4A ldr r2, .L161+4 + 1234 0410 1368 ldr r3, [r2] + 1235 0412 43F48073 orr r3, r3, #256 + 1236 0416 1360 str r3, [r2] + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1237 .loc 1 695 5 is_stmt 1 view .LVU406 + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1238 .loc 1 695 17 is_stmt 0 view .LVU407 + 1239 0418 FFF7FEFF bl HAL_GetTick + 1240 .LVL98: + 1241 041c 0546 mov r5, r0 + 1242 .LVL99: + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1243 .loc 1 697 5 is_stmt 1 view .LVU408 + 1244 .L88: + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1245 .loc 1 697 10 view .LVU409 + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1246 .loc 1 697 15 is_stmt 0 view .LVU410 + 1247 041e 374B ldr r3, .L161+4 + 1248 0420 1B68 ldr r3, [r3] + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1249 .loc 1 697 10 view .LVU411 + 1250 0422 13F4807F tst r3, #256 + 1251 0426 06D1 bne .L154 + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1252 .loc 1 699 7 is_stmt 1 view .LVU412 + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1253 .loc 1 699 11 is_stmt 0 view .LVU413 + 1254 0428 FFF7FEFF bl HAL_GetTick + 1255 .LVL100: + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1256 .loc 1 699 25 view .LVU414 + 1257 042c 401B subs r0, r0, r5 + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1258 .loc 1 699 9 view .LVU415 + 1259 042e 6428 cmp r0, #100 + 1260 0430 F5D9 bls .L88 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1261 .loc 1 701 16 view .LVU416 + 1262 0432 0320 movs r0, #3 + 1263 0434 F4E0 b .L36 + 1264 .L154: + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1265 .loc 1 706 5 is_stmt 1 view .LVU417 + ARM GAS /tmp/ccwNdrpc.s page 40 + + + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1266 .loc 1 706 5 view .LVU418 + 1267 0436 A368 ldr r3, [r4, #8] + 1268 0438 012B cmp r3, #1 + 1269 043a 0AD0 beq .L155 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1270 .loc 1 706 5 discriminator 2 view .LVU419 + 1271 043c 0BBB cbnz r3, .L92 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1272 .loc 1 706 5 discriminator 4 view .LVU420 + 1273 043e 2E4B ldr r3, .L161 + 1274 0440 1A6F ldr r2, [r3, #112] + 1275 0442 22F00102 bic r2, r2, #1 + 1276 0446 1A67 str r2, [r3, #112] + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1277 .loc 1 706 5 discriminator 4 view .LVU421 + 1278 0448 1A6F ldr r2, [r3, #112] + 1279 044a 22F00402 bic r2, r2, #4 + 1280 044e 1A67 str r2, [r3, #112] + 1281 0450 04E0 b .L91 + 1282 .L155: + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1283 .loc 1 706 5 discriminator 1 view .LVU422 + 1284 0452 294A ldr r2, .L161 + 1285 0454 136F ldr r3, [r2, #112] + 1286 0456 43F00103 orr r3, r3, #1 + 1287 045a 1367 str r3, [r2, #112] + 1288 .L91: + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1289 .loc 1 706 5 discriminator 10 view .LVU423 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1290 .loc 1 708 5 discriminator 10 view .LVU424 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1291 .loc 1 708 26 is_stmt 0 discriminator 10 view .LVU425 + 1292 045c A368 ldr r3, [r4, #8] + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1293 .loc 1 708 7 discriminator 10 view .LVU426 + 1294 045e 33B3 cbz r3, .L94 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1295 .loc 1 711 7 is_stmt 1 view .LVU427 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1296 .loc 1 711 19 is_stmt 0 view .LVU428 + 1297 0460 FFF7FEFF bl HAL_GetTick + 1298 .LVL101: + 1299 0464 0546 mov r5, r0 + 1300 .LVL102: + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1301 .loc 1 714 7 is_stmt 1 view .LVU429 + 1302 .L95: + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1303 .loc 1 714 12 view .LVU430 + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1304 .loc 1 714 13 is_stmt 0 view .LVU431 + 1305 0466 244B ldr r3, .L161 + 1306 0468 1B6F ldr r3, [r3, #112] + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1307 .loc 1 714 12 view .LVU432 + ARM GAS /tmp/ccwNdrpc.s page 41 + + + 1308 046a 13F0020F tst r3, #2 + 1309 046e ACD1 bne .L87 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1310 .loc 1 716 9 is_stmt 1 view .LVU433 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1311 .loc 1 716 13 is_stmt 0 view .LVU434 + 1312 0470 FFF7FEFF bl HAL_GetTick + 1313 .LVL103: + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1314 .loc 1 716 27 view .LVU435 + 1315 0474 401B subs r0, r0, r5 + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1316 .loc 1 716 11 view .LVU436 + 1317 0476 41F28833 movw r3, #5000 + 1318 047a 9842 cmp r0, r3 + 1319 047c F3D9 bls .L95 + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1320 .loc 1 718 18 view .LVU437 + 1321 047e 0320 movs r0, #3 + 1322 0480 CEE0 b .L36 + 1323 .L92: + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1324 .loc 1 706 5 is_stmt 1 discriminator 5 view .LVU438 + 1325 0482 052B cmp r3, #5 + 1326 0484 09D0 beq .L156 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1327 .loc 1 706 5 discriminator 8 view .LVU439 + 1328 0486 1C4B ldr r3, .L161 + 1329 0488 1A6F ldr r2, [r3, #112] + 1330 048a 22F00102 bic r2, r2, #1 + 1331 048e 1A67 str r2, [r3, #112] + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1332 .loc 1 706 5 discriminator 8 view .LVU440 + 1333 0490 1A6F ldr r2, [r3, #112] + 1334 0492 22F00402 bic r2, r2, #4 + 1335 0496 1A67 str r2, [r3, #112] + 1336 0498 E0E7 b .L91 + 1337 .L156: + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1338 .loc 1 706 5 discriminator 7 view .LVU441 + 1339 049a 174B ldr r3, .L161 + 1340 049c 1A6F ldr r2, [r3, #112] + 1341 049e 42F00402 orr r2, r2, #4 + 1342 04a2 1A67 str r2, [r3, #112] + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the LSE State */ + 1343 .loc 1 706 5 discriminator 7 view .LVU442 + 1344 04a4 1A6F ldr r2, [r3, #112] + 1345 04a6 42F00102 orr r2, r2, #1 + 1346 04aa 1A67 str r2, [r3, #112] + 1347 04ac D6E7 b .L91 + 1348 .L94: + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1349 .loc 1 725 7 view .LVU443 + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1350 .loc 1 725 19 is_stmt 0 view .LVU444 + 1351 04ae FFF7FEFF bl HAL_GetTick + 1352 .LVL104: + ARM GAS /tmp/ccwNdrpc.s page 42 + + + 1353 04b2 0546 mov r5, r0 + 1354 .LVL105: + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1355 .loc 1 728 7 is_stmt 1 view .LVU445 + 1356 .L97: + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1357 .loc 1 728 12 view .LVU446 + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1358 .loc 1 728 13 is_stmt 0 view .LVU447 + 1359 04b4 104B ldr r3, .L161 + 1360 04b6 1B6F ldr r3, [r3, #112] + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1361 .loc 1 728 12 view .LVU448 + 1362 04b8 13F0020F tst r3, #2 + 1363 04bc 85D0 beq .L87 + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1364 .loc 1 730 9 is_stmt 1 view .LVU449 + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1365 .loc 1 730 13 is_stmt 0 view .LVU450 + 1366 04be FFF7FEFF bl HAL_GetTick + 1367 .LVL106: + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1368 .loc 1 730 27 view .LVU451 + 1369 04c2 401B subs r0, r0, r5 + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1370 .loc 1 730 11 view .LVU452 + 1371 04c4 41F28833 movw r3, #5000 + 1372 04c8 9842 cmp r0, r3 + 1373 04ca F3D9 bls .L97 + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1374 .loc 1 732 18 view .LVU453 + 1375 04cc 0320 movs r0, #3 + 1376 04ce A7E0 b .L36 + 1377 .LVL107: + 1378 .L152: + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 1379 .loc 1 748 9 is_stmt 1 view .LVU454 + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 1380 .loc 1 749 9 view .LVU455 + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 1381 .loc 1 750 9 view .LVU456 + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + 1382 .loc 1 751 9 view .LVU457 + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + 1383 .loc 1 752 9 view .LVU458 + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + 1384 .loc 1 753 9 view .LVU459 + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1385 .loc 1 754 9 view .LVU460 + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1386 .loc 1 757 9 view .LVU461 + 1387 04d0 094A ldr r2, .L161 + 1388 04d2 1368 ldr r3, [r2] + 1389 04d4 23F08073 bic r3, r3, #16777216 + 1390 04d8 1360 str r3, [r2] + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1391 .loc 1 760 9 view .LVU462 + ARM GAS /tmp/ccwNdrpc.s page 43 + + + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1392 .loc 1 760 21 is_stmt 0 view .LVU463 + 1393 04da FFF7FEFF bl HAL_GetTick + 1394 .LVL108: + 1395 04de 0546 mov r5, r0 + 1396 .LVL109: + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1397 .loc 1 763 9 is_stmt 1 view .LVU464 + 1398 .L101: + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1399 .loc 1 763 14 view .LVU465 + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1400 .loc 1 763 15 is_stmt 0 view .LVU466 + 1401 04e0 054B ldr r3, .L161 + 1402 04e2 1B68 ldr r3, [r3] + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1403 .loc 1 763 14 view .LVU467 + 1404 04e4 13F0007F tst r3, #33554432 + 1405 04e8 0AD0 beq .L157 + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1406 .loc 1 765 11 is_stmt 1 view .LVU468 + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1407 .loc 1 765 15 is_stmt 0 view .LVU469 + 1408 04ea FFF7FEFF bl HAL_GetTick + 1409 .LVL110: + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1410 .loc 1 765 29 view .LVU470 + 1411 04ee 401B subs r0, r0, r5 + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1412 .loc 1 765 13 view .LVU471 + 1413 04f0 0228 cmp r0, #2 + 1414 04f2 F5D9 bls .L101 + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1415 .loc 1 767 20 view .LVU472 + 1416 04f4 0320 movs r0, #3 + 1417 04f6 93E0 b .L36 + 1418 .L162: + 1419 .align 2 + 1420 .L161: + 1421 04f8 00440258 .word 1476543488 + 1422 04fc 00480258 .word 1476544512 + 1423 .L157: + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 1424 .loc 1 772 9 is_stmt 1 view .LVU473 + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 1425 .loc 1 772 9 view .LVU474 + 1426 0500 4F4B ldr r3, .L163 + 1427 0502 996A ldr r1, [r3, #40] + 1428 0504 4F4A ldr r2, .L163+4 + 1429 0506 0A40 ands r2, r2, r1 + 1430 0508 A16A ldr r1, [r4, #40] + 1431 050a E06A ldr r0, [r4, #44] + 1432 050c 41EA0011 orr r1, r1, r0, lsl #4 + 1433 0510 0A43 orrs r2, r2, r1 + 1434 0512 9A62 str r2, [r3, #40] + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 1435 .loc 1 772 9 view .LVU475 + ARM GAS /tmp/ccwNdrpc.s page 44 + + + 1436 0514 226B ldr r2, [r4, #48] + 1437 0516 013A subs r2, r2, #1 + 1438 0518 C2F30802 ubfx r2, r2, #0, #9 + 1439 051c 616B ldr r1, [r4, #52] + 1440 051e 0139 subs r1, r1, #1 + 1441 0520 4902 lsls r1, r1, #9 + 1442 0522 89B2 uxth r1, r1 + 1443 0524 0A43 orrs r2, r2, r1 + 1444 0526 A16B ldr r1, [r4, #56] + 1445 0528 0139 subs r1, r1, #1 + 1446 052a 0904 lsls r1, r1, #16 + 1447 052c 01F4FE01 and r1, r1, #8323072 + 1448 0530 0A43 orrs r2, r2, r1 + 1449 0532 E16B ldr r1, [r4, #60] + 1450 0534 0139 subs r1, r1, #1 + 1451 0536 0906 lsls r1, r1, #24 + 1452 0538 01F0FE41 and r1, r1, #2130706432 + 1453 053c 0A43 orrs r2, r2, r1 + 1454 053e 1A63 str r2, [r3, #48] + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 1455 .loc 1 772 9 view .LVU476 + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1456 .loc 1 780 10 view .LVU477 + 1457 0540 DA6A ldr r2, [r3, #44] + 1458 0542 22F00102 bic r2, r2, #1 + 1459 0546 DA62 str r2, [r3, #44] + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1460 .loc 1 783 10 view .LVU478 + 1461 0548 596B ldr r1, [r3, #52] + 1462 054a 3F4A ldr r2, .L163+8 + 1463 054c 0A40 ands r2, r2, r1 + 1464 054e A16C ldr r1, [r4, #72] + 1465 0550 42EAC102 orr r2, r2, r1, lsl #3 + 1466 0554 5A63 str r2, [r3, #52] + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1467 .loc 1 786 9 view .LVU479 + 1468 0556 DA6A ldr r2, [r3, #44] + 1469 0558 22F00C02 bic r2, r2, #12 + 1470 055c 216C ldr r1, [r4, #64] + 1471 055e 0A43 orrs r2, r2, r1 + 1472 0560 DA62 str r2, [r3, #44] + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1473 .loc 1 789 9 view .LVU480 + 1474 0562 DA6A ldr r2, [r3, #44] + 1475 0564 22F00202 bic r2, r2, #2 + 1476 0568 616C ldr r1, [r4, #68] + 1477 056a 0A43 orrs r2, r2, r1 + 1478 056c DA62 str r2, [r3, #44] + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1479 .loc 1 792 10 view .LVU481 + 1480 056e DA6A ldr r2, [r3, #44] + 1481 0570 42F48032 orr r2, r2, #65536 + 1482 0574 DA62 str r2, [r3, #44] + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1483 .loc 1 795 10 view .LVU482 + 1484 0576 DA6A ldr r2, [r3, #44] + 1485 0578 42F40032 orr r2, r2, #131072 + ARM GAS /tmp/ccwNdrpc.s page 45 + + + 1486 057c DA62 str r2, [r3, #44] + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1487 .loc 1 798 10 view .LVU483 + 1488 057e DA6A ldr r2, [r3, #44] + 1489 0580 42F48022 orr r2, r2, #262144 + 1490 0584 DA62 str r2, [r3, #44] + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1491 .loc 1 801 10 view .LVU484 + 1492 0586 DA6A ldr r2, [r3, #44] + 1493 0588 42F00102 orr r2, r2, #1 + 1494 058c DA62 str r2, [r3, #44] + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1495 .loc 1 804 9 view .LVU485 + 1496 058e 1A68 ldr r2, [r3] + 1497 0590 42F08072 orr r2, r2, #16777216 + 1498 0594 1A60 str r2, [r3] + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1499 .loc 1 807 9 view .LVU486 + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1500 .loc 1 807 21 is_stmt 0 view .LVU487 + 1501 0596 FFF7FEFF bl HAL_GetTick + 1502 .LVL111: + 1503 059a 0446 mov r4, r0 + 1504 .LVL112: + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1505 .loc 1 810 9 is_stmt 1 view .LVU488 + 1506 .L103: + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1507 .loc 1 810 14 view .LVU489 + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1508 .loc 1 810 15 is_stmt 0 view .LVU490 + 1509 059c 284B ldr r3, .L163 + 1510 059e 1B68 ldr r3, [r3] + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1511 .loc 1 810 14 view .LVU491 + 1512 05a0 13F0007F tst r3, #33554432 + 1513 05a4 06D1 bne .L158 + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1514 .loc 1 812 11 is_stmt 1 view .LVU492 + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1515 .loc 1 812 15 is_stmt 0 view .LVU493 + 1516 05a6 FFF7FEFF bl HAL_GetTick + 1517 .LVL113: + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1518 .loc 1 812 29 view .LVU494 + 1519 05aa 001B subs r0, r0, r4 + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1520 .loc 1 812 13 view .LVU495 + 1521 05ac 0228 cmp r0, #2 + 1522 05ae F5D9 bls .L103 + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1523 .loc 1 814 20 view .LVU496 + 1524 05b0 0320 movs r0, #3 + 1525 05b2 35E0 b .L36 + 1526 .L158: + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 46 + + + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** temp1_pllckcfg = RCC->PLLCKSELR; + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** temp2_pllckcfg = RCC->PLL1DIVR; + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInit + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct- + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct- + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct- + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_OK; + 1527 .loc 1 853 10 view .LVU497 + 1528 05b4 0020 movs r0, #0 + 1529 05b6 33E0 b .L36 + 1530 .L153: + 1531 .loc 1 853 10 view .LVU498 + 1532 05b8 0020 movs r0, #0 + 1533 05ba 31E0 b .L36 + 1534 .LVL114: + 1535 .L99: + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** temp2_pllckcfg = RCC->PLL1DIVR; + 1536 .loc 1 839 7 is_stmt 1 view .LVU499 + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** temp2_pllckcfg = RCC->PLL1DIVR; + 1537 .loc 1 839 22 is_stmt 0 view .LVU500 + 1538 05bc 204A ldr r2, .L163 + 1539 05be 916A ldr r1, [r2, #40] + 1540 .LVL115: + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 1541 .loc 1 840 7 is_stmt 1 view .LVU501 + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 1542 .loc 1 840 22 is_stmt 0 view .LVU502 + 1543 05c0 106B ldr r0, [r2, #48] + 1544 .LVL116: + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1545 .loc 1 841 7 is_stmt 1 view .LVU503 + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1546 .loc 1 841 9 is_stmt 0 view .LVU504 + 1547 05c2 012B cmp r3, #1 + 1548 05c4 2DD0 beq .L128 + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInit + 1549 .loc 1 842 4 discriminator 1 view .LVU505 + 1550 05c6 01F00303 and r3, r1, #3 + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInit + 1551 .loc 1 842 76 discriminator 1 view .LVU506 + 1552 05ca A26A ldr r2, [r4, #40] + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1553 .loc 1 841 61 discriminator 1 view .LVU507 + 1554 05cc 9342 cmp r3, r2 + ARM GAS /tmp/ccwNdrpc.s page 47 + + + 1555 05ce 2AD1 bne .L129 + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + 1556 .loc 1 843 58 view .LVU508 + 1557 05d0 C1F30511 ubfx r1, r1, #4, #6 + 1558 .LVL117: + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + 1559 .loc 1 843 111 view .LVU509 + 1560 05d4 E36A ldr r3, [r4, #44] + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInit + 1561 .loc 1 842 88 view .LVU510 + 1562 05d6 9942 cmp r1, r3 + 1563 05d8 27D1 bne .L130 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct- + 1564 .loc 1 844 11 view .LVU511 + 1565 05da C0F30802 ubfx r2, r0, #0, #9 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct- + 1566 .loc 1 844 79 view .LVU512 + 1567 05de 236B ldr r3, [r4, #48] + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct- + 1568 .loc 1 844 85 view .LVU513 + 1569 05e0 013B subs r3, r3, #1 + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + 1570 .loc 1 843 118 view .LVU514 + 1571 05e2 9A42 cmp r2, r3 + 1572 05e4 23D1 bne .L131 + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct- + 1573 .loc 1 845 54 view .LVU515 + 1574 05e6 C0F34622 ubfx r2, r0, #9, #7 + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct- + 1575 .loc 1 845 104 view .LVU516 + 1576 05ea 636B ldr r3, [r4, #52] + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct- + 1577 .loc 1 845 110 view .LVU517 + 1578 05ec 013B subs r3, r3, #1 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct- + 1579 .loc 1 844 92 view .LVU518 + 1580 05ee 9A42 cmp r2, r3 + 1581 05f0 1FD1 bne .L132 + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct- + 1582 .loc 1 846 54 view .LVU519 + 1583 05f2 C0F30642 ubfx r2, r0, #16, #7 + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct- + 1584 .loc 1 846 104 view .LVU520 + 1585 05f6 A36B ldr r3, [r4, #56] + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct- + 1586 .loc 1 846 110 view .LVU521 + 1587 05f8 013B subs r3, r3, #1 + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct- + 1588 .loc 1 845 117 view .LVU522 + 1589 05fa 9A42 cmp r2, r3 + 1590 05fc 1BD1 bne .L133 + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1591 .loc 1 847 54 view .LVU523 + 1592 05fe C0F30660 ubfx r0, r0, #24, #7 + 1593 .LVL118: + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1594 .loc 1 847 104 view .LVU524 + ARM GAS /tmp/ccwNdrpc.s page 48 + + + 1595 0602 E36B ldr r3, [r4, #60] + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1596 .loc 1 847 110 view .LVU525 + 1597 0604 013B subs r3, r3, #1 + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct- + 1598 .loc 1 846 117 view .LVU526 + 1599 0606 9842 cmp r0, r3 + 1600 0608 17D1 bne .L134 + 1601 .loc 1 853 10 view .LVU527 + 1602 060a 0020 movs r0, #0 + 1603 060c 08E0 b .L36 + 1604 .LVL119: + 1605 .L107: + 1606 .LCFI2: + 1607 .cfi_def_cfa_offset 0 + 1608 .cfi_restore 3 + 1609 .cfi_restore 4 + 1610 .cfi_restore 5 + 1611 .cfi_restore 14 + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1612 .loc 1 410 12 view .LVU528 + 1613 060e 0120 movs r0, #1 + 1614 .LVL120: + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1615 .loc 1 854 1 view .LVU529 + 1616 0610 7047 bx lr + 1617 .LVL121: + 1618 .L141: + 1619 .LCFI3: + 1620 .cfi_def_cfa_offset 16 + 1621 .cfi_offset 3, -16 + 1622 .cfi_offset 4, -12 + 1623 .cfi_offset 5, -8 + 1624 .cfi_offset 14, -4 + 1625 .LBB10: + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1626 .loc 1 428 16 view .LVU530 + 1627 0612 0120 movs r0, #1 + 1628 .LVL122: + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1629 .loc 1 428 16 view .LVU531 + 1630 0614 04E0 b .L36 + 1631 .LVL123: + 1632 .L111: + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1633 .loc 1 428 16 view .LVU532 + 1634 .LBE10: + 1635 .LBB11: + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1636 .loc 1 482 16 view .LVU533 + 1637 0616 0120 movs r0, #1 + 1638 0618 02E0 b .L36 + 1639 .LVL124: + 1640 .L114: + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1641 .loc 1 482 16 view .LVU534 + 1642 .LBE11: + ARM GAS /tmp/ccwNdrpc.s page 49 + + + 1643 .LBB12: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1644 .loc 1 549 16 view .LVU535 + 1645 061a 0120 movs r0, #1 + 1646 061c 00E0 b .L36 + 1647 .L124: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1648 .loc 1 549 16 view .LVU536 + 1649 .LBE12: + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1650 .loc 1 853 10 view .LVU537 + 1651 061e 0020 movs r0, #0 + 1652 .LVL125: + 1653 .L36: + 1654 .loc 1 854 1 view .LVU538 + 1655 0620 38BD pop {r3, r4, r5, pc} + 1656 .LVL126: + 1657 .L128: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1658 .loc 1 849 16 view .LVU539 + 1659 0622 0120 movs r0, #1 + 1660 .LVL127: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1661 .loc 1 849 16 view .LVU540 + 1662 0624 FCE7 b .L36 + 1663 .LVL128: + 1664 .L129: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1665 .loc 1 849 16 view .LVU541 + 1666 0626 0120 movs r0, #1 + 1667 .LVL129: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1668 .loc 1 849 16 view .LVU542 + 1669 0628 FAE7 b .L36 + 1670 .LVL130: + 1671 .L130: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1672 .loc 1 849 16 view .LVU543 + 1673 062a 0120 movs r0, #1 + 1674 .LVL131: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1675 .loc 1 849 16 view .LVU544 + 1676 062c F8E7 b .L36 + 1677 .LVL132: + 1678 .L131: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1679 .loc 1 849 16 view .LVU545 + 1680 062e 0120 movs r0, #1 + 1681 .LVL133: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1682 .loc 1 849 16 view .LVU546 + 1683 0630 F6E7 b .L36 + 1684 .LVL134: + 1685 .L132: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1686 .loc 1 849 16 view .LVU547 + 1687 0632 0120 movs r0, #1 + ARM GAS /tmp/ccwNdrpc.s page 50 + + + 1688 .LVL135: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1689 .loc 1 849 16 view .LVU548 + 1690 0634 F4E7 b .L36 + 1691 .LVL136: + 1692 .L133: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1693 .loc 1 849 16 view .LVU549 + 1694 0636 0120 movs r0, #1 + 1695 .LVL137: + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1696 .loc 1 849 16 view .LVU550 + 1697 0638 F2E7 b .L36 + 1698 .L134: + 1699 063a 0120 movs r0, #1 + 1700 063c F0E7 b .L36 + 1701 .L164: + 1702 063e 00BF .align 2 + 1703 .L163: + 1704 0640 00440258 .word 1476543488 + 1705 0644 0CFCFFFF .word -1012 + 1706 0648 0700FFFF .word -65529 + 1707 .cfi_endproc + 1708 .LFE142: + 1710 .section .text.HAL_RCC_MCOConfig,"ax",%progbits + 1711 .align 1 + 1712 .global HAL_RCC_MCOConfig + 1713 .syntax unified + 1714 .thumb + 1715 .thumb_func + 1716 .fpu fpv5-d16 + 1718 HAL_RCC_MCOConfig: + 1719 .LVL138: + 1720 .LFB144: + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param FLatency: FLASH Latency, this parameter depend on device selected + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * and updated by HAL_InitTick() function called within this function + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The HSI is used (enabled by hardware) as system clock source after + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * clock source is ready (clock stable after start-up delay or PLL locked). + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * occur when the clock source will be ready. + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * You can use HAL_RCC_GetClockConfig() function to know which clock is + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * currently used as system clock source. + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Depending on the device voltage range, the software has to set correctly + ARM GAS /tmp/ccwNdrpc.s page 51 + + + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed freq + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * (for more details refer to section above "Initialization/de-initialization functions") + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_StatusTypeDef halstatus; + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t tickstart; + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t common_system_clock; + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check Null pointer */ + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(RCC_ClkInitStruct == NULL) + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** (HCLK) and the supply voltage of the device. */ + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Increasing the CPU frequency */ + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(FLatency > __HAL_FLASH_GET_LATENCY()) + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Increasing the BUS frequency divider */ + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined (RCC_D1CFGR_D1PPRE) + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 52 + + + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined (RCC_D2CFGR_D2PPRE1) + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D2CFGR_D2PPRE2) + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- D3PCLK1 Configuration ---------------------------*/ + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D3CFGR_D3PPRE) + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + ARM GAS /tmp/ccwNdrpc.s page 53 + + + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined (RCC_D1CFGR_HPRE) + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set the new HCLK clock divider */ + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set the new HCLK clock divider */ +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration -------------------------*/ +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_D1CPRE) +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the HSE ready flag */ +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the PLL ready flag */ +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* CSI is selected as System Clock Source */ +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the PLL ready flag */ +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + ARM GAS /tmp/ccwNdrpc.s page 54 + + +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the HSI ready flag */ +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get Start Tick*/ +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** tickstart = HAL_GetTick(); +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_P +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_TIMEOUT; +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Decreasing the BUS frequency divider */ +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_HPRE) +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set the new HCLK clock divider */ +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set the new HCLK clock divider */ +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(FLatency < __HAL_FLASH_GET_LATENCY()) +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return HAL_ERROR; +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ + ARM GAS /tmp/ccwNdrpc.s page 55 + + +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_D1PPRE) +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D2CFGR_D2PPRE1) +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined (RCC_D2CFGR_D2PPRE2) +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D3CFGR_D3PPRE) + ARM GAS /tmp/ccwNdrpc.s page 56 + + +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_D1CPRE) +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1 +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_HPRE) +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_ +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RC +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemCoreClock = SystemD2Clock; +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemCoreClock = common_system_clock; +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /* DUAL_CORE && CORE_CM4 */ +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** halstatus = HAL_InitTick (uwTickPrio); +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return halstatus; +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @} +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** @defgroup RCC_Group2 Peripheral Control functions +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief RCC clocks control functions +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** @verbatim +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** =============================================================================== +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** ##### Peripheral Control functions ##### +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** =============================================================================== +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** [..] +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** frequencies. +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** @endverbatim +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @{ +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ + ARM GAS /tmp/ccwNdrpc.s page 57 + + +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note PA8/PC9 should be configured in alternate function mode. +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_MCOx: specifies the output direction for the clock source. +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * This parameter can be one of the following values: +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_MCOSource: specifies the clock source to output. +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * This parameter can be one of the following values: +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_MCODiv: specifies the MCOx pre-scaler. +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * This parameter can be one of the following values: +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1721 .loc 1 1247 1 is_stmt 1 view -0 + 1722 .cfi_startproc + 1723 @ args = 0, pretend = 0, frame = 32 + 1724 @ frame_needed = 0, uses_anonymous_args = 0 + 1725 .loc 1 1247 1 is_stmt 0 view .LVU552 + 1726 0000 70B5 push {r4, r5, r6, lr} + 1727 .LCFI4: + 1728 .cfi_def_cfa_offset 16 + 1729 .cfi_offset 4, -16 + 1730 .cfi_offset 5, -12 + 1731 .cfi_offset 6, -8 + 1732 .cfi_offset 14, -4 + 1733 0002 88B0 sub sp, sp, #32 + 1734 .LCFI5: + 1735 .cfi_def_cfa_offset 48 + 1736 0004 0C46 mov r4, r1 + 1737 0006 1546 mov r5, r2 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitTypeDef GPIO_InitStruct; + 1738 .loc 1 1248 3 is_stmt 1 view .LVU553 +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check the parameters */ +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); + 1739 .loc 1 1250 3 view .LVU554 +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + 1740 .loc 1 1251 3 view .LVU555 +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* RCC_MCO1 */ +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(RCC_MCOx == RCC_MCO1) + 1741 .loc 1 1253 3 view .LVU556 + 1742 .loc 1 1253 5 is_stmt 0 view .LVU557 + 1743 0008 10BB cbnz r0, .L166 + ARM GAS /tmp/ccwNdrpc.s page 58 + + +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + 1744 .loc 1 1255 5 is_stmt 1 view .LVU558 +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* MCO1 Clock Enable */ +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MCO1_CLK_ENABLE(); + 1745 .loc 1 1258 5 view .LVU559 + 1746 .LBB13: + 1747 .loc 1 1258 5 view .LVU560 + 1748 .loc 1 1258 5 view .LVU561 + 1749 000a 234E ldr r6, .L169 + 1750 000c D6F8E030 ldr r3, [r6, #224] + 1751 0010 43F00103 orr r3, r3, #1 + 1752 0014 C6F8E030 str r3, [r6, #224] + 1753 .loc 1 1258 5 view .LVU562 + 1754 0018 D6F8E030 ldr r3, [r6, #224] + 1755 001c 03F00103 and r3, r3, #1 + 1756 0020 0193 str r3, [sp, #4] + 1757 .loc 1 1258 5 view .LVU563 + 1758 0022 019B ldr r3, [sp, #4] + 1759 .LBE13: + 1760 .loc 1 1258 5 view .LVU564 +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO1_PIN; + 1761 .loc 1 1261 5 view .LVU565 + 1762 .loc 1 1261 25 is_stmt 0 view .LVU566 + 1763 0024 4FF48073 mov r3, #256 + 1764 0028 0393 str r3, [sp, #12] +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1765 .loc 1 1262 5 is_stmt 1 view .LVU567 + 1766 .loc 1 1262 26 is_stmt 0 view .LVU568 + 1767 002a 0223 movs r3, #2 + 1768 002c 0493 str r3, [sp, #16] +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1769 .loc 1 1263 5 is_stmt 1 view .LVU569 + 1770 .loc 1 1263 27 is_stmt 0 view .LVU570 + 1771 002e 0323 movs r3, #3 + 1772 0030 0693 str r3, [sp, #24] +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1773 .loc 1 1264 5 is_stmt 1 view .LVU571 + 1774 .loc 1 1264 26 is_stmt 0 view .LVU572 + 1775 0032 0023 movs r3, #0 + 1776 0034 0593 str r3, [sp, #20] +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1777 .loc 1 1265 5 is_stmt 1 view .LVU573 + 1778 .loc 1 1265 31 is_stmt 0 view .LVU574 + 1779 0036 0793 str r3, [sp, #28] +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + 1780 .loc 1 1266 5 is_stmt 1 view .LVU575 + 1781 0038 03A9 add r1, sp, #12 + 1782 .LVL139: + 1783 .loc 1 1266 5 is_stmt 0 view .LVU576 + 1784 003a 1848 ldr r0, .L169+4 + 1785 .LVL140: + 1786 .loc 1 1266 5 view .LVU577 + 1787 003c FFF7FEFF bl HAL_GPIO_Init + ARM GAS /tmp/ccwNdrpc.s page 59 + + + 1788 .LVL141: +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */ +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + 1789 .loc 1 1269 5 is_stmt 1 view .LVU578 + 1790 0040 3369 ldr r3, [r6, #16] + 1791 0042 23F0FE73 bic r3, r3, #33292288 + 1792 0046 2543 orrs r5, r5, r4 + 1793 .LVL142: + 1794 .loc 1 1269 5 is_stmt 0 view .LVU579 + 1795 0048 1D43 orrs r5, r5, r3 + 1796 004a 3561 str r5, [r6, #16] + 1797 .LVL143: + 1798 .L165: +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* MCO2 Clock Enable */ +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MCO2_CLK_ENABLE(); +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Configure the MCO2 pin in alternate function mode */ +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO2_PIN; +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */ +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U))) +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1799 .loc 1 1289 1 view .LVU580 + 1800 004c 08B0 add sp, sp, #32 + 1801 .LCFI6: + 1802 .cfi_remember_state + 1803 .cfi_def_cfa_offset 16 + 1804 @ sp needed + 1805 004e 70BD pop {r4, r5, r6, pc} + 1806 .LVL144: + 1807 .L166: + 1808 .LCFI7: + 1809 .cfi_restore_state +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1810 .loc 1 1273 5 is_stmt 1 view .LVU581 +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1811 .loc 1 1276 5 view .LVU582 + 1812 .LBB14: +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1813 .loc 1 1276 5 view .LVU583 +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1814 .loc 1 1276 5 view .LVU584 + 1815 0050 114E ldr r6, .L169 + 1816 0052 D6F8E030 ldr r3, [r6, #224] + 1817 0056 43F00403 orr r3, r3, #4 + ARM GAS /tmp/ccwNdrpc.s page 60 + + + 1818 005a C6F8E030 str r3, [r6, #224] +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1819 .loc 1 1276 5 view .LVU585 + 1820 005e D6F8E030 ldr r3, [r6, #224] + 1821 0062 03F00403 and r3, r3, #4 + 1822 0066 0293 str r3, [sp, #8] +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1823 .loc 1 1276 5 view .LVU586 + 1824 0068 029B ldr r3, [sp, #8] + 1825 .LBE14: +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1826 .loc 1 1276 5 view .LVU587 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1827 .loc 1 1279 5 view .LVU588 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1828 .loc 1 1279 25 is_stmt 0 view .LVU589 + 1829 006a 4FF40073 mov r3, #512 + 1830 006e 0393 str r3, [sp, #12] +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1831 .loc 1 1280 5 is_stmt 1 view .LVU590 +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1832 .loc 1 1280 26 is_stmt 0 view .LVU591 + 1833 0070 0223 movs r3, #2 + 1834 0072 0493 str r3, [sp, #16] +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1835 .loc 1 1281 5 is_stmt 1 view .LVU592 +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1836 .loc 1 1281 27 is_stmt 0 view .LVU593 + 1837 0074 0323 movs r3, #3 + 1838 0076 0693 str r3, [sp, #24] +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1839 .loc 1 1282 5 is_stmt 1 view .LVU594 +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1840 .loc 1 1282 26 is_stmt 0 view .LVU595 + 1841 0078 0023 movs r3, #0 + 1842 007a 0593 str r3, [sp, #20] +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + 1843 .loc 1 1283 5 is_stmt 1 view .LVU596 +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + 1844 .loc 1 1283 31 is_stmt 0 view .LVU597 + 1845 007c 0793 str r3, [sp, #28] +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1846 .loc 1 1284 5 is_stmt 1 view .LVU598 + 1847 007e 03A9 add r1, sp, #12 + 1848 .LVL145: +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1849 .loc 1 1284 5 is_stmt 0 view .LVU599 + 1850 0080 0748 ldr r0, .L169+8 + 1851 .LVL146: +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 1852 .loc 1 1284 5 view .LVU600 + 1853 0082 FFF7FEFF bl HAL_GPIO_Init + 1854 .LVL147: +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1855 .loc 1 1287 5 is_stmt 1 view .LVU601 + 1856 0086 3369 ldr r3, [r6, #16] + 1857 0088 23F07E43 bic r3, r3, #-33554432 + ARM GAS /tmp/ccwNdrpc.s page 61 + + + 1858 008c 44EAC514 orr r4, r4, r5, lsl #7 + 1859 .LVL148: +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1860 .loc 1 1287 5 is_stmt 0 view .LVU602 + 1861 0090 1C43 orrs r4, r4, r3 + 1862 0092 3461 str r4, [r6, #16] + 1863 .loc 1 1289 1 view .LVU603 + 1864 0094 DAE7 b .L165 + 1865 .L170: + 1866 0096 00BF .align 2 + 1867 .L169: + 1868 0098 00440258 .word 1476543488 + 1869 009c 00000258 .word 1476526080 + 1870 00a0 00080258 .word 1476528128 + 1871 .cfi_endproc + 1872 .LFE144: + 1874 .section .text.HAL_RCC_EnableCSS,"ax",%progbits + 1875 .align 1 + 1876 .global HAL_RCC_EnableCSS + 1877 .syntax unified + 1878 .thumb + 1879 .thumb_func + 1880 .fpu fpv5-d16 + 1882 HAL_RCC_EnableCSS: + 1883 .LFB145: +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Enables the Clock Security System. +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector. +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1884 .loc 1 1301 1 is_stmt 1 view -0 + 1885 .cfi_startproc + 1886 @ args = 0, pretend = 0, frame = 0 + 1887 @ frame_needed = 0, uses_anonymous_args = 0 + 1888 @ link register save eliminated. +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ; + 1889 .loc 1 1302 3 view .LVU605 + 1890 0000 024A ldr r2, .L172 + 1891 0002 1368 ldr r3, [r2] + 1892 0004 43F40023 orr r3, r3, #524288 + 1893 0008 1360 str r3, [r2] +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1894 .loc 1 1303 1 is_stmt 0 view .LVU606 + 1895 000a 7047 bx lr + 1896 .L173: + 1897 .align 2 + 1898 .L172: + 1899 000c 00440258 .word 1476543488 + 1900 .cfi_endproc + 1901 .LFE145: + ARM GAS /tmp/ccwNdrpc.s page 62 + + + 1903 .section .text.HAL_RCC_DisableCSS,"ax",%progbits + 1904 .align 1 + 1905 .global HAL_RCC_DisableCSS + 1906 .syntax unified + 1907 .thumb + 1908 .thumb_func + 1909 .fpu fpv5-d16 + 1911 HAL_RCC_DisableCSS: + 1912 .LFB146: +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Disables the Clock Security System. +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void) +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1913 .loc 1 1310 1 is_stmt 1 view -0 + 1914 .cfi_startproc + 1915 @ args = 0, pretend = 0, frame = 0 + 1916 @ frame_needed = 0, uses_anonymous_args = 0 + 1917 @ link register save eliminated. +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON); + 1918 .loc 1 1311 3 view .LVU608 + 1919 0000 024A ldr r2, .L175 + 1920 0002 1368 ldr r3, [r2] + 1921 0004 23F40023 bic r3, r3, #524288 + 1922 0008 1360 str r3, [r2] +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 1923 .loc 1 1312 1 is_stmt 0 view .LVU609 + 1924 000a 7047 bx lr + 1925 .L176: + 1926 .align 2 + 1927 .L175: + 1928 000c 00440258 .word 1476543488 + 1929 .cfi_endproc + 1930 .LFE146: + 1932 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits + 1933 .align 1 + 1934 .global HAL_RCC_GetSysClockFreq + 1935 .syntax unified + 1936 .thumb + 1937 .thumb_func + 1938 .fpu fpv5-d16 + 1940 HAL_RCC_GetSysClockFreq: + 1941 .LFB147: +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * constant and the selected clock source: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*) +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + ARM GAS /tmp/ccwNdrpc.s page 63 + + +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * 4 MHz) but the real value may vary depending on the variations +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * in voltage and temperature. +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * 64 MHz) but the real value may vary depending on the variations +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * in voltage and temperature. +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * have wrong result. +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * value for HSE crystal. +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note This function can be used by the user application to compute the +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * baud rate for the communication peripherals or configure other parameters. +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval SYSCLK frequency +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 1942 .loc 1 1349 1 is_stmt 1 view -0 + 1943 .cfi_startproc + 1944 @ args = 0, pretend = 0, frame = 0 + 1945 @ frame_needed = 0, uses_anonymous_args = 0 + 1946 @ link register save eliminated. +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + 1947 .loc 1 1350 3 view .LVU611 +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** float_t fracn1, pllvco; + 1948 .loc 1 1351 3 view .LVU612 +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t sysclockfreq; + 1949 .loc 1 1352 3 view .LVU613 +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** switch (RCC->CFGR & RCC_CFGR_SWS) + 1950 .loc 1 1356 3 view .LVU614 + 1951 .loc 1 1356 14 is_stmt 0 view .LVU615 + 1952 0000 744B ldr r3, .L193 + 1953 0002 1B69 ldr r3, [r3, #16] + 1954 .loc 1 1356 21 view .LVU616 + 1955 0004 03F03803 and r3, r3, #56 + 1956 .loc 1 1356 3 view .LVU617 + 1957 0008 102B cmp r3, #16 + 1958 000a 00F0DE80 beq .L185 + 1959 000e 182B cmp r3, #24 + 1960 0010 10D0 beq .L179 + 1961 0012 0BB1 cbz r3, .L191 + 1962 0014 7048 ldr r0, .L193+4 + 1963 0016 7047 bx lr + 1964 .L191: +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + ARM GAS /tmp/ccwNdrpc.s page 64 + + +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + 1965 .loc 1 1360 4 is_stmt 1 view .LVU618 + 1966 .loc 1 1360 8 is_stmt 0 view .LVU619 + 1967 0018 6E4B ldr r3, .L193 + 1968 001a 1B68 ldr r3, [r3] + 1969 .loc 1 1360 7 view .LVU620 + 1970 001c 13F0200F tst r3, #32 + 1971 0020 00F0D580 beq .L187 +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); + 1972 .loc 1 1362 9 is_stmt 1 view .LVU621 + 1973 .loc 1 1362 50 is_stmt 0 view .LVU622 + 1974 0024 6B4B ldr r3, .L193 + 1975 0026 1868 ldr r0, [r3] + 1976 .loc 1 1362 77 view .LVU623 + 1977 0028 C0F3C100 ubfx r0, r0, #3, #2 + 1978 .loc 1 1362 22 view .LVU624 + 1979 002c 6B4B ldr r3, .L193+8 + 1980 002e 23FA00F0 lsr r0, r3, r0 + 1981 .LVL149: + 1982 .loc 1 1362 22 view .LVU625 + 1983 0032 7047 bx lr + 1984 .LVL150: + 1985 .L179: +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + 1986 .loc 1 1349 1 view .LVU626 + 1987 0034 10B4 push {r4} + 1988 .LCFI8: + 1989 .cfi_def_cfa_offset 4 + 1990 .cfi_offset 4, -4 +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = (uint32_t) HSI_VALUE; +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = CSI_VALUE; +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SYSCLK = PLL_VCO / PLLR +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + 1991 .loc 1 1384 5 is_stmt 1 view .LVU627 + 1992 .loc 1 1384 21 is_stmt 0 view .LVU628 + 1993 0036 674A ldr r2, .L193 + 1994 0038 916A ldr r1, [r2, #40] + ARM GAS /tmp/ccwNdrpc.s page 65 + + + 1995 .loc 1 1384 15 view .LVU629 + 1996 003a 01F00301 and r1, r1, #3 + 1997 .LVL151: +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + 1998 .loc 1 1385 5 is_stmt 1 view .LVU630 + 1999 .loc 1 1385 17 is_stmt 0 view .LVU631 + 2000 003e 946A ldr r4, [r2, #40] + 2001 .loc 1 1385 10 view .LVU632 + 2002 0040 C4F30510 ubfx r0, r4, #4, #6 + 2003 .LVL152: +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + 2004 .loc 1 1386 5 is_stmt 1 view .LVU633 + 2005 .loc 1 1386 22 is_stmt 0 view .LVU634 + 2006 0044 D36A ldr r3, [r2, #44] + 2007 .loc 1 1386 15 view .LVU635 + 2008 0046 03F0010C and ip, r3, #1 + 2009 .LVL153: +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 2010 .loc 1 1387 5 is_stmt 1 view .LVU636 + 2011 .loc 1 1387 50 is_stmt 0 view .LVU637 + 2012 004a 536B ldr r3, [r2, #52] + 2013 .loc 1 1387 85 view .LVU638 + 2014 004c C3F3CC03 ubfx r3, r3, #3, #13 + 2015 .loc 1 1387 23 view .LVU639 + 2016 0050 0CFB03F3 mul r3, ip, r3 + 2017 .loc 1 1387 12 view .LVU640 + 2018 0054 07EE903A vmov s15, r3 @ int + 2019 0058 F8EE677A vcvt.f32.u32 s15, s15 + 2020 .LVL154: +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if (pllm != 0U) + 2021 .loc 1 1389 5 is_stmt 1 view .LVU641 + 2022 .loc 1 1389 8 is_stmt 0 view .LVU642 + 2023 005c 14F47C7F tst r4, #1008 + 2024 0060 00F09380 beq .L177 +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** switch (pllsource) + 2025 .loc 1 1391 7 is_stmt 1 view .LVU643 + 2026 0064 0129 cmp r1, #1 + 2027 0066 65D0 beq .L180 + 2028 0068 0229 cmp r1, #2 + 2029 006a 00F09180 beq .L181 + 2030 006e E1B1 cbz r1, .L192 +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + ARM GAS /tmp/ccwNdrpc.s page 66 + + +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** default: +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 2031 .loc 1 1415 9 view .LVU644 + 2032 .loc 1 1415 40 is_stmt 0 view .LVU645 + 2033 0070 07EE100A vmov s14, r0 @ int + 2034 0074 F8EE476A vcvt.f32.u32 s13, s14 + 2035 .loc 1 1415 38 view .LVU646 + 2036 0078 9FED596A vldr.32 s12, .L193+12 + 2037 007c 86EE267A vdiv.f32 s14, s12, s13 + 2038 .loc 1 1415 81 view .LVU647 + 2039 0080 544B ldr r3, .L193 + 2040 0082 1B6B ldr r3, [r3, #48] + 2041 .loc 1 1415 67 view .LVU648 + 2042 0084 C3F30803 ubfx r3, r3, #0, #9 + 2043 .loc 1 1415 58 view .LVU649 + 2044 0088 06EE903A vmov s13, r3 @ int + 2045 008c F8EE666A vcvt.f32.u32 s13, s13 + 2046 .loc 1 1415 120 view .LVU650 + 2047 0090 9FED546A vldr.32 s12, .L193+16 + 2048 0094 67EE867A vmul.f32 s15, s15, s12 + 2049 .LVL155: + 2050 .loc 1 1415 111 view .LVU651 + 2051 0098 76EEA77A vadd.f32 s15, s13, s15 + 2052 .loc 1 1415 138 view .LVU652 + 2053 009c F7EE006A vmov.f32 s13, #1.0e+0 + 2054 00a0 77EEA67A vadd.f32 s15, s15, s13 + 2055 .loc 1 1415 16 view .LVU653 + 2056 00a4 27EE277A vmul.f32 s14, s14, s15 + 2057 .LVL156: +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2058 .loc 1 1416 9 is_stmt 1 view .LVU654 + 2059 00a8 60E0 b .L184 + 2060 .LVL157: + 2061 .L192: +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2062 .loc 1 1395 8 view .LVU655 +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2063 .loc 1 1395 12 is_stmt 0 view .LVU656 + 2064 00aa 1368 ldr r3, [r2] +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2065 .loc 1 1395 11 view .LVU657 + 2066 00ac 13F0200F tst r3, #32 + 2067 00b0 23D0 beq .L183 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 2068 .loc 1 1397 11 is_stmt 1 view .LVU658 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 2069 .loc 1 1397 36 is_stmt 0 view .LVU659 + 2070 00b2 1146 mov r1, r2 + 2071 .LVL158: + ARM GAS /tmp/ccwNdrpc.s page 67 + + +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 2072 .loc 1 1397 36 view .LVU660 + 2073 00b4 1268 ldr r2, [r2] +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 2074 .loc 1 1397 63 view .LVU661 + 2075 00b6 C2F3C102 ubfx r2, r2, #3, #2 +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 2076 .loc 1 1397 19 view .LVU662 + 2077 00ba 484B ldr r3, .L193+8 + 2078 00bc D340 lsrs r3, r3, r2 + 2079 .LVL159: +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2080 .loc 1 1398 11 is_stmt 1 view .LVU663 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2081 .loc 1 1398 22 is_stmt 0 view .LVU664 + 2082 00be 07EE103A vmov s14, r3 @ int + 2083 00c2 F8EE476A vcvt.f32.u32 s13, s14 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2084 .loc 1 1398 42 view .LVU665 + 2085 00c6 07EE100A vmov s14, r0 @ int + 2086 00ca B8EE476A vcvt.f32.u32 s12, s14 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2087 .loc 1 1398 40 view .LVU666 + 2088 00ce 86EE867A vdiv.f32 s14, s13, s12 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2089 .loc 1 1398 83 view .LVU667 + 2090 00d2 0B6B ldr r3, [r1, #48] + 2091 .LVL160: +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2092 .loc 1 1398 69 view .LVU668 + 2093 00d4 C3F30803 ubfx r3, r3, #0, #9 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2094 .loc 1 1398 60 view .LVU669 + 2095 00d8 06EE903A vmov s13, r3 @ int + 2096 00dc F8EE666A vcvt.f32.u32 s13, s13 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2097 .loc 1 1398 122 view .LVU670 + 2098 00e0 9FED406A vldr.32 s12, .L193+16 + 2099 00e4 67EE867A vmul.f32 s15, s15, s12 + 2100 .LVL161: +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2101 .loc 1 1398 113 view .LVU671 + 2102 00e8 76EEA77A vadd.f32 s15, s13, s15 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2103 .loc 1 1398 140 view .LVU672 + 2104 00ec F7EE006A vmov.f32 s13, #1.0e+0 + 2105 00f0 77EEA67A vadd.f32 s15, s15, s13 +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2106 .loc 1 1398 18 view .LVU673 + 2107 00f4 27EE277A vmul.f32 s14, s14, s15 + 2108 .LVL162: +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2109 .loc 1 1398 18 view .LVU674 + 2110 00f8 38E0 b .L184 + 2111 .LVL163: + 2112 .L183: +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 68 + + + 2113 .loc 1 1402 11 is_stmt 1 view .LVU675 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2114 .loc 1 1402 42 is_stmt 0 view .LVU676 + 2115 00fa 07EE100A vmov s14, r0 @ int + 2116 00fe F8EE476A vcvt.f32.u32 s13, s14 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2117 .loc 1 1402 40 view .LVU677 + 2118 0102 9FED396A vldr.32 s12, .L193+20 + 2119 0106 86EE267A vdiv.f32 s14, s12, s13 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2120 .loc 1 1402 83 view .LVU678 + 2121 010a 324B ldr r3, .L193 + 2122 010c 1B6B ldr r3, [r3, #48] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2123 .loc 1 1402 69 view .LVU679 + 2124 010e C3F30803 ubfx r3, r3, #0, #9 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2125 .loc 1 1402 60 view .LVU680 + 2126 0112 06EE903A vmov s13, r3 @ int + 2127 0116 F8EE666A vcvt.f32.u32 s13, s13 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2128 .loc 1 1402 122 view .LVU681 + 2129 011a 9FED326A vldr.32 s12, .L193+16 + 2130 011e 67EE867A vmul.f32 s15, s15, s12 + 2131 .LVL164: +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2132 .loc 1 1402 113 view .LVU682 + 2133 0122 76EEA77A vadd.f32 s15, s13, s15 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2134 .loc 1 1402 140 view .LVU683 + 2135 0126 F7EE006A vmov.f32 s13, #1.0e+0 + 2136 012a 77EEA67A vadd.f32 s15, s15, s13 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2137 .loc 1 1402 18 view .LVU684 + 2138 012e 27EE277A vmul.f32 s14, s14, s15 + 2139 .LVL165: +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2140 .loc 1 1402 18 view .LVU685 + 2141 0132 1BE0 b .L184 + 2142 .LVL166: + 2143 .L180: +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2144 .loc 1 1407 9 is_stmt 1 view .LVU686 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2145 .loc 1 1407 40 is_stmt 0 view .LVU687 + 2146 0134 07EE100A vmov s14, r0 @ int + 2147 0138 F8EE476A vcvt.f32.u32 s13, s14 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2148 .loc 1 1407 38 view .LVU688 + 2149 013c 9FED286A vldr.32 s12, .L193+12 + 2150 0140 86EE267A vdiv.f32 s14, s12, s13 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2151 .loc 1 1407 81 view .LVU689 + 2152 0144 234B ldr r3, .L193 + 2153 0146 1B6B ldr r3, [r3, #48] +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2154 .loc 1 1407 67 view .LVU690 + ARM GAS /tmp/ccwNdrpc.s page 69 + + + 2155 0148 C3F30803 ubfx r3, r3, #0, #9 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2156 .loc 1 1407 58 view .LVU691 + 2157 014c 06EE903A vmov s13, r3 @ int + 2158 0150 F8EE666A vcvt.f32.u32 s13, s13 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2159 .loc 1 1407 120 view .LVU692 + 2160 0154 9FED236A vldr.32 s12, .L193+16 + 2161 0158 67EE867A vmul.f32 s15, s15, s12 + 2162 .LVL167: +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2163 .loc 1 1407 111 view .LVU693 + 2164 015c 76EEA77A vadd.f32 s15, s13, s15 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2165 .loc 1 1407 138 view .LVU694 + 2166 0160 F7EE006A vmov.f32 s13, #1.0e+0 + 2167 0164 77EEA67A vadd.f32 s15, s15, s13 +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2168 .loc 1 1407 16 view .LVU695 + 2169 0168 27EE277A vmul.f32 s14, s14, s15 + 2170 .LVL168: +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2171 .loc 1 1408 9 is_stmt 1 view .LVU696 + 2172 .L184: +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + 2173 .loc 1 1418 7 view .LVU697 + 2174 .loc 1 1418 20 is_stmt 0 view .LVU698 + 2175 016c 194B ldr r3, .L193 + 2176 016e 1B6B ldr r3, [r3, #48] + 2177 .loc 1 1418 50 view .LVU699 + 2178 0170 C3F34623 ubfx r3, r3, #9, #7 + 2179 .loc 1 1418 12 view .LVU700 + 2180 0174 0133 adds r3, r3, #1 + 2181 .LVL169: +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); + 2182 .loc 1 1419 7 is_stmt 1 view .LVU701 + 2183 .loc 1 1419 50 is_stmt 0 view .LVU702 + 2184 0176 07EE903A vmov s15, r3 @ int + 2185 017a F8EE677A vcvt.f32.u32 s15, s15 + 2186 .loc 1 1419 33 view .LVU703 + 2187 017e C7EE276A vdiv.f32 s13, s14, s15 + 2188 .loc 1 1419 20 view .LVU704 + 2189 0182 FCEEE67A vcvt.u32.f32 s15, s13 + 2190 0186 17EE900A vmov r0, s15 @ int + 2191 .LVL170: + 2192 .L177: +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = 0U; +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** default: +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** sysclockfreq = CSI_VALUE; +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + ARM GAS /tmp/ccwNdrpc.s page 70 + + +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return sysclockfreq; +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2193 .loc 1 1433 1 view .LVU705 + 2194 018a 5DF8044B ldr r4, [sp], #4 + 2195 .LCFI9: + 2196 .cfi_remember_state + 2197 .cfi_restore 4 + 2198 .cfi_def_cfa_offset 0 + 2199 .LVL171: + 2200 .loc 1 1433 1 view .LVU706 + 2201 018e 7047 bx lr + 2202 .LVL172: + 2203 .L181: + 2204 .LCFI10: + 2205 .cfi_restore_state +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2206 .loc 1 1411 9 is_stmt 1 view .LVU707 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2207 .loc 1 1411 40 is_stmt 0 view .LVU708 + 2208 0190 07EE100A vmov s14, r0 @ int + 2209 0194 F8EE476A vcvt.f32.u32 s13, s14 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2210 .loc 1 1411 38 view .LVU709 + 2211 0198 9FED146A vldr.32 s12, .L193+24 + 2212 019c 86EE267A vdiv.f32 s14, s12, s13 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2213 .loc 1 1411 81 view .LVU710 + 2214 01a0 0C4B ldr r3, .L193 + 2215 01a2 1B6B ldr r3, [r3, #48] +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2216 .loc 1 1411 67 view .LVU711 + 2217 01a4 C3F30803 ubfx r3, r3, #0, #9 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2218 .loc 1 1411 58 view .LVU712 + 2219 01a8 06EE903A vmov s13, r3 @ int + 2220 01ac F8EE666A vcvt.f32.u32 s13, s13 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2221 .loc 1 1411 120 view .LVU713 + 2222 01b0 9FED0C6A vldr.32 s12, .L193+16 + 2223 01b4 67EE867A vmul.f32 s15, s15, s12 + 2224 .LVL173: +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2225 .loc 1 1411 111 view .LVU714 + 2226 01b8 76EEA77A vadd.f32 s15, s13, s15 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2227 .loc 1 1411 138 view .LVU715 + 2228 01bc F7EE006A vmov.f32 s13, #1.0e+0 + 2229 01c0 77EEA67A vadd.f32 s15, s15, s13 +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2230 .loc 1 1411 16 view .LVU716 + 2231 01c4 27EE277A vmul.f32 s14, s14, s15 + 2232 .LVL174: +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2233 .loc 1 1412 9 is_stmt 1 view .LVU717 + 2234 01c8 D0E7 b .L184 + ARM GAS /tmp/ccwNdrpc.s page 71 + + + 2235 .LVL175: + 2236 .L185: + 2237 .LCFI11: + 2238 .cfi_def_cfa_offset 0 + 2239 .cfi_restore 4 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** break; + 2240 .loc 1 1376 18 is_stmt 0 view .LVU718 + 2241 01ca 0948 ldr r0, .L193+28 + 2242 01cc 7047 bx lr + 2243 .L187: +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2244 .loc 1 1366 22 view .LVU719 + 2245 01ce 0348 ldr r0, .L193+8 + 2246 .LVL176: +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2247 .loc 1 1432 3 is_stmt 1 view .LVU720 + 2248 .loc 1 1433 1 is_stmt 0 view .LVU721 + 2249 01d0 7047 bx lr + 2250 .L194: + 2251 01d2 00BF .align 2 + 2252 .L193: + 2253 01d4 00440258 .word 1476543488 + 2254 01d8 00093D00 .word 4000000 + 2255 01dc 0090D003 .word 64000000 + 2256 01e0 0024744A .word 1249125376 + 2257 01e4 00000039 .word 956301312 + 2258 01e8 0024744C .word 1282679808 + 2259 01ec 0024F44A .word 1257513984 + 2260 01f0 00127A00 .word 8000000 + 2261 .cfi_endproc + 2262 .LFE147: + 2264 .section .text.HAL_RCC_ClockConfig,"ax",%progbits + 2265 .align 1 + 2266 .global HAL_RCC_ClockConfig + 2267 .syntax unified + 2268 .thumb + 2269 .thumb_func + 2270 .fpu fpv5-d16 + 2272 HAL_RCC_ClockConfig: + 2273 .LVL177: + 2274 .LFB143: + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_StatusTypeDef halstatus; + 2275 .loc 1 883 1 is_stmt 1 view -0 + 2276 .cfi_startproc + 2277 @ args = 0, pretend = 0, frame = 0 + 2278 @ frame_needed = 0, uses_anonymous_args = 0 + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t tickstart; + 2279 .loc 1 884 3 view .LVU723 + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t common_system_clock; + 2280 .loc 1 885 3 view .LVU724 + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2281 .loc 1 886 3 view .LVU725 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2282 .loc 1 889 3 view .LVU726 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2283 .loc 1 889 5 is_stmt 0 view .LVU727 + 2284 0000 0028 cmp r0, #0 + ARM GAS /tmp/ccwNdrpc.s page 72 + + + 2285 0002 00F03281 beq .L216 + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_StatusTypeDef halstatus; + 2286 .loc 1 883 1 view .LVU728 + 2287 0006 70B5 push {r4, r5, r6, lr} + 2288 .LCFI12: + 2289 .cfi_def_cfa_offset 16 + 2290 .cfi_offset 4, -16 + 2291 .cfi_offset 5, -12 + 2292 .cfi_offset 6, -8 + 2293 .cfi_offset 14, -4 + 2294 0008 0D46 mov r5, r1 + 2295 000a 0446 mov r4, r0 + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 2296 .loc 1 895 3 is_stmt 1 view .LVU729 + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2297 .loc 1 896 3 view .LVU730 + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2298 .loc 1 903 3 view .LVU731 + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2299 .loc 1 903 17 is_stmt 0 view .LVU732 + 2300 000c 9B4B ldr r3, .L232 + 2301 000e 1B68 ldr r3, [r3] + 2302 0010 03F00F03 and r3, r3, #15 + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2303 .loc 1 903 5 view .LVU733 + 2304 0014 8B42 cmp r3, r1 + 2305 0016 0BD2 bcs .L197 + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2306 .loc 1 906 5 is_stmt 1 view .LVU734 + 2307 0018 984A ldr r2, .L232 + 2308 001a 1368 ldr r3, [r2] + 2309 001c 23F00F03 bic r3, r3, #15 + 2310 0020 0B43 orrs r3, r3, r1 + 2311 0022 1360 str r3, [r2] + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2312 .loc 1 910 5 view .LVU735 + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2313 .loc 1 910 8 is_stmt 0 view .LVU736 + 2314 0024 1368 ldr r3, [r2] + 2315 0026 03F00F03 and r3, r3, #15 + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2316 .loc 1 910 7 view .LVU737 + 2317 002a 8B42 cmp r3, r1 + 2318 002c 40F01F81 bne .L217 + 2319 .L197: + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2320 .loc 1 919 3 is_stmt 1 view .LVU738 + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2321 .loc 1 919 25 is_stmt 0 view .LVU739 + 2322 0030 2368 ldr r3, [r4] + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2323 .loc 1 919 5 view .LVU740 + 2324 0032 13F0040F tst r3, #4 + 2325 0036 0CD0 beq .L198 + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2326 .loc 1 922 5 is_stmt 1 view .LVU741 + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + ARM GAS /tmp/ccwNdrpc.s page 73 + + + 2327 .loc 1 922 26 is_stmt 0 view .LVU742 + 2328 0038 2269 ldr r2, [r4, #16] + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2329 .loc 1 922 50 view .LVU743 + 2330 003a 914B ldr r3, .L232+4 + 2331 003c 9B69 ldr r3, [r3, #24] + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2332 .loc 1 922 59 view .LVU744 + 2333 003e 03F07003 and r3, r3, #112 + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2334 .loc 1 922 7 view .LVU745 + 2335 0042 9A42 cmp r2, r3 + 2336 0044 05D9 bls .L198 + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + 2337 .loc 1 924 7 is_stmt 1 view .LVU746 + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2338 .loc 1 925 7 view .LVU747 + 2339 0046 8E49 ldr r1, .L232+4 + 2340 .LVL178: + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2341 .loc 1 925 7 is_stmt 0 view .LVU748 + 2342 0048 8B69 ldr r3, [r1, #24] + 2343 004a 23F07003 bic r3, r3, #112 + 2344 004e 1A43 orrs r2, r2, r3 + 2345 0050 8A61 str r2, [r1, #24] + 2346 .L198: + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2347 .loc 1 937 3 is_stmt 1 view .LVU749 + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2348 .loc 1 937 25 is_stmt 0 view .LVU750 + 2349 0052 2368 ldr r3, [r4] + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2350 .loc 1 937 5 view .LVU751 + 2351 0054 13F0080F tst r3, #8 + 2352 0058 0CD0 beq .L199 + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2353 .loc 1 940 5 is_stmt 1 view .LVU752 + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2354 .loc 1 940 26 is_stmt 0 view .LVU753 + 2355 005a 6269 ldr r2, [r4, #20] + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2356 .loc 1 940 50 view .LVU754 + 2357 005c 884B ldr r3, .L232+4 + 2358 005e DB69 ldr r3, [r3, #28] + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2359 .loc 1 940 59 view .LVU755 + 2360 0060 03F07003 and r3, r3, #112 + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2361 .loc 1 940 7 view .LVU756 + 2362 0064 9A42 cmp r2, r3 + 2363 0066 05D9 bls .L199 + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + 2364 .loc 1 942 7 is_stmt 1 view .LVU757 + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2365 .loc 1 943 7 view .LVU758 + 2366 0068 8549 ldr r1, .L232+4 + 2367 006a CB69 ldr r3, [r1, #28] + ARM GAS /tmp/ccwNdrpc.s page 74 + + + 2368 006c 23F07003 bic r3, r3, #112 + 2369 0070 1A43 orrs r2, r2, r3 + 2370 0072 CA61 str r2, [r1, #28] + 2371 .L199: + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2372 .loc 1 954 3 view .LVU759 + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2373 .loc 1 954 25 is_stmt 0 view .LVU760 + 2374 0074 2368 ldr r3, [r4] + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2375 .loc 1 954 5 view .LVU761 + 2376 0076 13F0100F tst r3, #16 + 2377 007a 0CD0 beq .L200 + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2378 .loc 1 957 5 is_stmt 1 view .LVU762 + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2379 .loc 1 957 26 is_stmt 0 view .LVU763 + 2380 007c A269 ldr r2, [r4, #24] + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2381 .loc 1 957 50 view .LVU764 + 2382 007e 804B ldr r3, .L232+4 + 2383 0080 DB69 ldr r3, [r3, #28] + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2384 .loc 1 957 59 view .LVU765 + 2385 0082 03F4E063 and r3, r3, #1792 + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2386 .loc 1 957 7 view .LVU766 + 2387 0086 9A42 cmp r2, r3 + 2388 0088 05D9 bls .L200 + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + 2389 .loc 1 959 7 is_stmt 1 view .LVU767 + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2390 .loc 1 960 7 view .LVU768 + 2391 008a 7D49 ldr r1, .L232+4 + 2392 008c CB69 ldr r3, [r1, #28] + 2393 008e 23F4E063 bic r3, r3, #1792 + 2394 0092 1A43 orrs r2, r2, r3 + 2395 0094 CA61 str r2, [r1, #28] + 2396 .L200: + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2397 .loc 1 972 3 view .LVU769 + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2398 .loc 1 972 25 is_stmt 0 view .LVU770 + 2399 0096 2368 ldr r3, [r4] + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2400 .loc 1 972 5 view .LVU771 + 2401 0098 13F0200F tst r3, #32 + 2402 009c 0CD0 beq .L201 + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2403 .loc 1 975 5 is_stmt 1 view .LVU772 + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2404 .loc 1 975 26 is_stmt 0 view .LVU773 + 2405 009e E269 ldr r2, [r4, #28] + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2406 .loc 1 975 50 view .LVU774 + 2407 00a0 774B ldr r3, .L232+4 + 2408 00a2 1B6A ldr r3, [r3, #32] + ARM GAS /tmp/ccwNdrpc.s page 75 + + + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2409 .loc 1 975 59 view .LVU775 + 2410 00a4 03F07003 and r3, r3, #112 + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2411 .loc 1 975 7 view .LVU776 + 2412 00a8 9A42 cmp r2, r3 + 2413 00aa 05D9 bls .L201 + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + 2414 .loc 1 977 7 is_stmt 1 view .LVU777 + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2415 .loc 1 978 7 view .LVU778 + 2416 00ac 7449 ldr r1, .L232+4 + 2417 00ae 0B6A ldr r3, [r1, #32] + 2418 00b0 23F07003 bic r3, r3, #112 + 2419 00b4 1A43 orrs r2, r2, r3 + 2420 00b6 0A62 str r2, [r1, #32] + 2421 .L201: + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2422 .loc 1 990 3 view .LVU779 + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2423 .loc 1 990 25 is_stmt 0 view .LVU780 + 2424 00b8 2368 ldr r3, [r4] + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2425 .loc 1 990 5 view .LVU781 + 2426 00ba 13F0020F tst r3, #2 + 2427 00be 0CD0 beq .L202 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2428 .loc 1 993 5 is_stmt 1 view .LVU782 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2429 .loc 1 993 26 is_stmt 0 view .LVU783 + 2430 00c0 E268 ldr r2, [r4, #12] + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2431 .loc 1 993 49 view .LVU784 + 2432 00c2 6F4B ldr r3, .L232+4 + 2433 00c4 9B69 ldr r3, [r3, #24] + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2434 .loc 1 993 58 view .LVU785 + 2435 00c6 03F00F03 and r3, r3, #15 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2436 .loc 1 993 7 view .LVU786 + 2437 00ca 9A42 cmp r2, r3 + 2438 00cc 05D9 bls .L202 + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 2439 .loc 1 996 7 is_stmt 1 view .LVU787 + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2440 .loc 1 997 7 view .LVU788 + 2441 00ce 6C49 ldr r1, .L232+4 + 2442 00d0 8B69 ldr r3, [r1, #24] + 2443 00d2 23F00F03 bic r3, r3, #15 + 2444 00d6 1A43 orrs r2, r2, r3 + 2445 00d8 8A61 str r2, [r1, #24] + 2446 .L202: +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2447 .loc 1 1010 5 view .LVU789 +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2448 .loc 1 1010 27 is_stmt 0 view .LVU790 + 2449 00da 2368 ldr r3, [r4] + ARM GAS /tmp/ccwNdrpc.s page 76 + + +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2450 .loc 1 1010 7 view .LVU791 + 2451 00dc 13F0010F tst r3, #1 + 2452 00e0 41D0 beq .L203 +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 2453 .loc 1 1012 7 is_stmt 1 view .LVU792 +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_D1CPRE) + 2454 .loc 1 1013 7 view .LVU793 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2455 .loc 1 1015 7 view .LVU794 + 2456 00e2 674A ldr r2, .L232+4 + 2457 00e4 9369 ldr r3, [r2, #24] + 2458 00e6 23F47063 bic r3, r3, #3840 + 2459 00ea A168 ldr r1, [r4, #8] + 2460 00ec 0B43 orrs r3, r3, r1 + 2461 00ee 9361 str r3, [r2, #24] +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2462 .loc 1 1020 7 view .LVU795 +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2463 .loc 1 1020 27 is_stmt 0 view .LVU796 + 2464 00f0 6368 ldr r3, [r4, #4] +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2465 .loc 1 1020 9 view .LVU797 + 2466 00f2 022B cmp r3, #2 + 2467 00f4 0AD0 beq .L228 +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2468 .loc 1 1029 12 is_stmt 1 view .LVU798 +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2469 .loc 1 1029 14 is_stmt 0 view .LVU799 + 2470 00f6 032B cmp r3, #3 + 2471 00f8 27D0 beq .L229 +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2472 .loc 1 1038 12 is_stmt 1 view .LVU800 +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2473 .loc 1 1038 14 is_stmt 0 view .LVU801 + 2474 00fa 012B cmp r3, #1 + 2475 00fc 2CD0 beq .L230 +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2476 .loc 1 1050 9 is_stmt 1 view .LVU802 +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2477 .loc 1 1050 12 is_stmt 0 view .LVU803 + 2478 00fe 604A ldr r2, .L232+4 + 2479 0100 1268 ldr r2, [r2] +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2480 .loc 1 1050 11 view .LVU804 + 2481 0102 12F0040F tst r2, #4 + 2482 0106 06D1 bne .L205 +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2483 .loc 1 1052 18 view .LVU805 + 2484 0108 0120 movs r0, #1 + 2485 .LVL179: +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2486 .loc 1 1052 18 view .LVU806 + 2487 010a ADE0 b .L196 + 2488 .LVL180: + 2489 .L228: +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + ARM GAS /tmp/ccwNdrpc.s page 77 + + + 2490 .loc 1 1023 9 is_stmt 1 view .LVU807 +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2491 .loc 1 1023 12 is_stmt 0 view .LVU808 + 2492 010c 1268 ldr r2, [r2] +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2493 .loc 1 1023 11 view .LVU809 + 2494 010e 12F4003F tst r2, #131072 + 2495 0112 00F0AE80 beq .L231 + 2496 .L205: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2497 .loc 1 1055 7 is_stmt 1 view .LVU810 + 2498 0116 5A49 ldr r1, .L232+4 + 2499 0118 0A69 ldr r2, [r1, #16] + 2500 011a 22F00702 bic r2, r2, #7 + 2501 011e 1343 orrs r3, r3, r2 + 2502 0120 0B61 str r3, [r1, #16] +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2503 .loc 1 1058 7 view .LVU811 +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2504 .loc 1 1058 19 is_stmt 0 view .LVU812 + 2505 0122 FFF7FEFF bl HAL_GetTick + 2506 .LVL181: +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2507 .loc 1 1058 19 view .LVU813 + 2508 0126 0646 mov r6, r0 + 2509 .LVL182: +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2510 .loc 1 1060 9 is_stmt 1 view .LVU814 + 2511 .L208: +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2512 .loc 1 1060 15 view .LVU815 +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2513 .loc 1 1060 16 is_stmt 0 view .LVU816 + 2514 0128 554B ldr r3, .L232+4 + 2515 012a 1B69 ldr r3, [r3, #16] + 2516 012c 03F03803 and r3, r3, #56 +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2517 .loc 1 1060 68 view .LVU817 + 2518 0130 6268 ldr r2, [r4, #4] +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2519 .loc 1 1060 15 view .LVU818 + 2520 0132 B3EBC20F cmp r3, r2, lsl #3 + 2521 0136 16D0 beq .L203 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2522 .loc 1 1062 11 is_stmt 1 view .LVU819 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2523 .loc 1 1062 15 is_stmt 0 view .LVU820 + 2524 0138 FFF7FEFF bl HAL_GetTick + 2525 .LVL183: +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2526 .loc 1 1062 29 view .LVU821 + 2527 013c 801B subs r0, r0, r6 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2528 .loc 1 1062 13 view .LVU822 + 2529 013e 41F28833 movw r3, #5000 + 2530 0142 9842 cmp r0, r3 + 2531 0144 F0D9 bls .L208 + ARM GAS /tmp/ccwNdrpc.s page 78 + + +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2532 .loc 1 1064 20 view .LVU823 + 2533 0146 0320 movs r0, #3 + 2534 0148 8EE0 b .L196 + 2535 .LVL184: + 2536 .L229: +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2537 .loc 1 1032 9 is_stmt 1 view .LVU824 +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2538 .loc 1 1032 12 is_stmt 0 view .LVU825 + 2539 014a 4D4A ldr r2, .L232+4 + 2540 014c 1268 ldr r2, [r2] +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2541 .loc 1 1032 11 view .LVU826 + 2542 014e 12F0007F tst r2, #33554432 + 2543 0152 E0D1 bne .L205 +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2544 .loc 1 1034 18 view .LVU827 + 2545 0154 0120 movs r0, #1 + 2546 .LVL185: +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2547 .loc 1 1034 18 view .LVU828 + 2548 0156 87E0 b .L196 + 2549 .LVL186: + 2550 .L230: +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2551 .loc 1 1041 9 is_stmt 1 view .LVU829 +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2552 .loc 1 1041 12 is_stmt 0 view .LVU830 + 2553 0158 494A ldr r2, .L232+4 + 2554 015a 1268 ldr r2, [r2] +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2555 .loc 1 1041 11 view .LVU831 + 2556 015c 12F4807F tst r2, #256 + 2557 0160 D9D1 bne .L205 +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2558 .loc 1 1043 18 view .LVU832 + 2559 0162 0120 movs r0, #1 + 2560 .LVL187: +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2561 .loc 1 1043 18 view .LVU833 + 2562 0164 80E0 b .L196 + 2563 .L203: +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2564 .loc 1 1072 3 is_stmt 1 view .LVU834 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2565 .loc 1 1072 25 is_stmt 0 view .LVU835 + 2566 0166 2368 ldr r3, [r4] +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2567 .loc 1 1072 5 view .LVU836 + 2568 0168 13F0020F tst r3, #2 + 2569 016c 0CD0 beq .L210 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2570 .loc 1 1075 5 is_stmt 1 view .LVU837 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2571 .loc 1 1075 26 is_stmt 0 view .LVU838 + 2572 016e E268 ldr r2, [r4, #12] + ARM GAS /tmp/ccwNdrpc.s page 79 + + +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2573 .loc 1 1075 49 view .LVU839 + 2574 0170 434B ldr r3, .L232+4 + 2575 0172 9B69 ldr r3, [r3, #24] +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2576 .loc 1 1075 58 view .LVU840 + 2577 0174 03F00F03 and r3, r3, #15 +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2578 .loc 1 1075 7 view .LVU841 + 2579 0178 9A42 cmp r2, r3 + 2580 017a 05D2 bcs .L210 +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 2581 .loc 1 1078 7 is_stmt 1 view .LVU842 +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2582 .loc 1 1079 7 view .LVU843 + 2583 017c 4049 ldr r1, .L232+4 + 2584 017e 8B69 ldr r3, [r1, #24] + 2585 0180 23F00F03 bic r3, r3, #15 + 2586 0184 1A43 orrs r2, r2, r3 + 2587 0186 8A61 str r2, [r1, #24] + 2588 .L210: +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2589 .loc 1 1092 3 view .LVU844 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2590 .loc 1 1092 17 is_stmt 0 view .LVU845 + 2591 0188 3C4B ldr r3, .L232 + 2592 018a 1B68 ldr r3, [r3] + 2593 018c 03F00F03 and r3, r3, #15 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2594 .loc 1 1092 5 view .LVU846 + 2595 0190 AB42 cmp r3, r5 + 2596 0192 0AD9 bls .L211 +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2597 .loc 1 1095 5 is_stmt 1 view .LVU847 + 2598 0194 394A ldr r2, .L232 + 2599 0196 1368 ldr r3, [r2] + 2600 0198 23F00F03 bic r3, r3, #15 + 2601 019c 2B43 orrs r3, r3, r5 + 2602 019e 1360 str r3, [r2] +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2603 .loc 1 1099 5 view .LVU848 +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2604 .loc 1 1099 8 is_stmt 0 view .LVU849 + 2605 01a0 1368 ldr r3, [r2] + 2606 01a2 03F00F03 and r3, r3, #15 +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2607 .loc 1 1099 7 view .LVU850 + 2608 01a6 AB42 cmp r3, r5 + 2609 01a8 65D1 bne .L223 + 2610 .L211: +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2611 .loc 1 1106 2 is_stmt 1 view .LVU851 +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2612 .loc 1 1106 24 is_stmt 0 view .LVU852 + 2613 01aa 2368 ldr r3, [r4] +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2614 .loc 1 1106 4 view .LVU853 + ARM GAS /tmp/ccwNdrpc.s page 80 + + + 2615 01ac 13F0040F tst r3, #4 + 2616 01b0 0CD0 beq .L212 +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2617 .loc 1 1109 4 is_stmt 1 view .LVU854 +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2618 .loc 1 1109 25 is_stmt 0 view .LVU855 + 2619 01b2 2269 ldr r2, [r4, #16] +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2620 .loc 1 1109 49 view .LVU856 + 2621 01b4 324B ldr r3, .L232+4 + 2622 01b6 9B69 ldr r3, [r3, #24] +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2623 .loc 1 1109 58 view .LVU857 + 2624 01b8 03F07003 and r3, r3, #112 +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2625 .loc 1 1109 6 view .LVU858 + 2626 01bc 9A42 cmp r2, r3 + 2627 01be 05D2 bcs .L212 +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + 2628 .loc 1 1111 6 is_stmt 1 view .LVU859 +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2629 .loc 1 1112 6 view .LVU860 + 2630 01c0 2F49 ldr r1, .L232+4 + 2631 01c2 8B69 ldr r3, [r1, #24] + 2632 01c4 23F07003 bic r3, r3, #112 + 2633 01c8 1A43 orrs r2, r2, r3 + 2634 01ca 8A61 str r2, [r1, #24] + 2635 .L212: +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2636 .loc 1 1124 2 view .LVU861 +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2637 .loc 1 1124 24 is_stmt 0 view .LVU862 + 2638 01cc 2368 ldr r3, [r4] +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2639 .loc 1 1124 4 view .LVU863 + 2640 01ce 13F0080F tst r3, #8 + 2641 01d2 0CD0 beq .L213 +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2642 .loc 1 1127 4 is_stmt 1 view .LVU864 +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2643 .loc 1 1127 25 is_stmt 0 view .LVU865 + 2644 01d4 6269 ldr r2, [r4, #20] +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2645 .loc 1 1127 49 view .LVU866 + 2646 01d6 2A4B ldr r3, .L232+4 + 2647 01d8 DB69 ldr r3, [r3, #28] +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2648 .loc 1 1127 58 view .LVU867 + 2649 01da 03F07003 and r3, r3, #112 +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2650 .loc 1 1127 6 view .LVU868 + 2651 01de 9A42 cmp r2, r3 + 2652 01e0 05D2 bcs .L213 +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + 2653 .loc 1 1129 6 is_stmt 1 view .LVU869 +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2654 .loc 1 1130 6 view .LVU870 + ARM GAS /tmp/ccwNdrpc.s page 81 + + + 2655 01e2 2749 ldr r1, .L232+4 + 2656 01e4 CB69 ldr r3, [r1, #28] + 2657 01e6 23F07003 bic r3, r3, #112 + 2658 01ea 1A43 orrs r2, r2, r3 + 2659 01ec CA61 str r2, [r1, #28] + 2660 .L213: +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2661 .loc 1 1142 2 view .LVU871 +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2662 .loc 1 1142 24 is_stmt 0 view .LVU872 + 2663 01ee 2368 ldr r3, [r4] +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2664 .loc 1 1142 4 view .LVU873 + 2665 01f0 13F0100F tst r3, #16 + 2666 01f4 0CD0 beq .L214 +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2667 .loc 1 1145 4 is_stmt 1 view .LVU874 +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2668 .loc 1 1145 25 is_stmt 0 view .LVU875 + 2669 01f6 A269 ldr r2, [r4, #24] +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2670 .loc 1 1145 49 view .LVU876 + 2671 01f8 214B ldr r3, .L232+4 + 2672 01fa DB69 ldr r3, [r3, #28] +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2673 .loc 1 1145 58 view .LVU877 + 2674 01fc 03F4E063 and r3, r3, #1792 +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2675 .loc 1 1145 6 view .LVU878 + 2676 0200 9A42 cmp r2, r3 + 2677 0202 05D2 bcs .L214 +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + 2678 .loc 1 1147 6 is_stmt 1 view .LVU879 +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2679 .loc 1 1148 6 view .LVU880 + 2680 0204 1E49 ldr r1, .L232+4 + 2681 0206 CB69 ldr r3, [r1, #28] + 2682 0208 23F4E063 bic r3, r3, #1792 + 2683 020c 1A43 orrs r2, r2, r3 + 2684 020e CA61 str r2, [r1, #28] + 2685 .L214: +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2686 .loc 1 1160 2 view .LVU881 +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2687 .loc 1 1160 24 is_stmt 0 view .LVU882 + 2688 0210 2368 ldr r3, [r4] +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2689 .loc 1 1160 4 view .LVU883 + 2690 0212 13F0200F tst r3, #32 + 2691 0216 0CD0 beq .L215 +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2692 .loc 1 1163 4 is_stmt 1 view .LVU884 +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2693 .loc 1 1163 25 is_stmt 0 view .LVU885 + 2694 0218 E269 ldr r2, [r4, #28] +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2695 .loc 1 1163 49 view .LVU886 + ARM GAS /tmp/ccwNdrpc.s page 82 + + + 2696 021a 194B ldr r3, .L232+4 + 2697 021c 1B6A ldr r3, [r3, #32] +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2698 .loc 1 1163 58 view .LVU887 + 2699 021e 03F07003 and r3, r3, #112 +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2700 .loc 1 1163 6 view .LVU888 + 2701 0222 9A42 cmp r2, r3 + 2702 0224 05D2 bcs .L215 +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + 2703 .loc 1 1165 6 is_stmt 1 view .LVU889 +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2704 .loc 1 1166 6 view .LVU890 + 2705 0226 1649 ldr r1, .L232+4 + 2706 0228 0B6A ldr r3, [r1, #32] + 2707 022a 23F07003 bic r3, r3, #112 + 2708 022e 1A43 orrs r2, r2, r3 + 2709 0230 0A62 str r2, [r1, #32] + 2710 .L215: +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2711 .loc 1 1179 3 view .LVU891 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2712 .loc 1 1179 25 is_stmt 0 view .LVU892 + 2713 0232 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 2714 .LVL188: +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2715 .loc 1 1179 77 view .LVU893 + 2716 0236 1249 ldr r1, .L232+4 + 2717 0238 8B69 ldr r3, [r1, #24] +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2718 .loc 1 1179 106 view .LVU894 + 2719 023a C3F30323 ubfx r3, r3, #8, #4 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2720 .loc 1 1179 72 view .LVU895 + 2721 023e 114A ldr r2, .L232+8 + 2722 0240 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2723 .loc 1 1179 133 view .LVU896 + 2724 0242 03F01F03 and r3, r3, #31 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2725 .loc 1 1179 23 view .LVU897 + 2726 0246 D840 lsrs r0, r0, r3 + 2727 .LVL189: +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2728 .loc 1 1185 3 is_stmt 1 view .LVU898 +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2729 .loc 1 1185 66 is_stmt 0 view .LVU899 + 2730 0248 8B69 ldr r3, [r1, #24] +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2731 .loc 1 1185 93 view .LVU900 + 2732 024a 03F00F03 and r3, r3, #15 +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2733 .loc 1 1185 61 view .LVU901 + 2734 024e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2735 .loc 1 1185 118 view .LVU902 + 2736 0250 03F01F03 and r3, r3, #31 + ARM GAS /tmp/ccwNdrpc.s page 83 + + +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2737 .loc 1 1185 40 view .LVU903 + 2738 0254 20FA03F3 lsr r3, r0, r3 +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else + 2739 .loc 1 1185 17 view .LVU904 + 2740 0258 0B4A ldr r2, .L232+12 + 2741 025a 1360 str r3, [r2] +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 2742 .loc 1 1193 3 is_stmt 1 view .LVU905 +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 2743 .loc 1 1193 19 is_stmt 0 view .LVU906 + 2744 025c 0B4B ldr r3, .L232+16 + 2745 025e 1860 str r0, [r3] +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2746 .loc 1 1197 3 is_stmt 1 view .LVU907 +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2747 .loc 1 1197 15 is_stmt 0 view .LVU908 + 2748 0260 0B4B ldr r3, .L232+20 + 2749 0262 1868 ldr r0, [r3] + 2750 .LVL190: +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2751 .loc 1 1197 15 view .LVU909 + 2752 0264 FFF7FEFF bl HAL_InitTick + 2753 .LVL191: +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2754 .loc 1 1199 3 is_stmt 1 view .LVU910 + 2755 .L196: +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2756 .loc 1 1200 1 is_stmt 0 view .LVU911 + 2757 0268 70BD pop {r4, r5, r6, pc} + 2758 .LVL192: + 2759 .L216: + 2760 .LCFI13: + 2761 .cfi_def_cfa_offset 0 + 2762 .cfi_restore 4 + 2763 .cfi_restore 5 + 2764 .cfi_restore 6 + 2765 .cfi_restore 14 + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2766 .loc 1 891 12 view .LVU912 + 2767 026a 0120 movs r0, #1 + 2768 .LVL193: +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 2769 .loc 1 1200 1 view .LVU913 + 2770 026c 7047 bx lr + 2771 .LVL194: + 2772 .L217: + 2773 .LCFI14: + 2774 .cfi_def_cfa_offset 16 + 2775 .cfi_offset 4, -16 + 2776 .cfi_offset 5, -12 + 2777 .cfi_offset 6, -8 + 2778 .cfi_offset 14, -4 + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2779 .loc 1 912 14 view .LVU914 + 2780 026e 0120 movs r0, #1 + 2781 .LVL195: + ARM GAS /tmp/ccwNdrpc.s page 84 + + + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2782 .loc 1 912 14 view .LVU915 + 2783 0270 FAE7 b .L196 + 2784 .LVL196: + 2785 .L231: +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2786 .loc 1 1025 18 view .LVU916 + 2787 0272 0120 movs r0, #1 + 2788 .LVL197: +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2789 .loc 1 1025 18 view .LVU917 + 2790 0274 F8E7 b .L196 + 2791 .L223: +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2792 .loc 1 1101 14 view .LVU918 + 2793 0276 0120 movs r0, #1 + 2794 0278 F6E7 b .L196 + 2795 .L233: + 2796 027a 00BF .align 2 + 2797 .L232: + 2798 027c 00200052 .word 1375739904 + 2799 0280 00440258 .word 1476543488 + 2800 0284 00000000 .word D1CorePrescTable + 2801 0288 00000000 .word SystemD2Clock + 2802 028c 00000000 .word SystemCoreClock + 2803 0290 00000000 .word uwTickPrio + 2804 .cfi_endproc + 2805 .LFE143: + 2807 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits + 2808 .align 1 + 2809 .global HAL_RCC_GetHCLKFreq + 2810 .syntax unified + 2811 .thumb + 2812 .thumb_func + 2813 .fpu fpv5-d16 + 2815 HAL_RCC_GetHCLKFreq: + 2816 .LFB148: +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Returns the HCLK frequency +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * and updated within this function +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval HCLK frequency +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2817 .loc 1 1446 1 is_stmt 1 view -0 + 2818 .cfi_startproc + 2819 @ args = 0, pretend = 0, frame = 0 + 2820 @ frame_needed = 0, uses_anonymous_args = 0 + 2821 0000 08B5 push {r3, lr} + 2822 .LCFI15: + 2823 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccwNdrpc.s page 85 + + + 2824 .cfi_offset 3, -8 + 2825 .cfi_offset 14, -4 +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t common_system_clock; + 2826 .loc 1 1447 1 view .LVU920 +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_D1CPRE) +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1 + 2827 .loc 1 1450 3 view .LVU921 + 2828 .loc 1 1450 25 is_stmt 0 view .LVU922 + 2829 0002 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 2830 .LVL198: + 2831 .loc 1 1450 76 view .LVU923 + 2832 0006 0B4A ldr r2, .L236 + 2833 0008 9369 ldr r3, [r2, #24] + 2834 .loc 1 1450 105 view .LVU924 + 2835 000a C3F30323 ubfx r3, r3, #8, #4 + 2836 .loc 1 1450 71 view .LVU925 + 2837 000e 0A49 ldr r1, .L236+4 + 2838 0010 CB5C ldrb r3, [r1, r3] @ zero_extendqisi2 + 2839 .loc 1 1450 131 view .LVU926 + 2840 0012 03F01F03 and r3, r3, #31 + 2841 .loc 1 1450 23 view .LVU927 + 2842 0016 20FA03F3 lsr r3, r0, r3 + 2843 .LVL199: +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_ +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_HPRE) +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_ + 2844 .loc 1 1456 3 is_stmt 1 view .LVU928 + 2845 .loc 1 1456 66 is_stmt 0 view .LVU929 + 2846 001a 9269 ldr r2, [r2, #24] + 2847 .loc 1 1456 93 view .LVU930 + 2848 001c 02F00F02 and r2, r2, #15 + 2849 .loc 1 1456 61 view .LVU931 + 2850 0020 885C ldrb r0, [r1, r2] @ zero_extendqisi2 + 2851 .loc 1 1456 118 view .LVU932 + 2852 0022 00F01F00 and r0, r0, #31 + 2853 .loc 1 1456 40 view .LVU933 + 2854 0026 23FA00F0 lsr r0, r3, r0 + 2855 .loc 1 1456 17 view .LVU934 + 2856 002a 044A ldr r2, .L236+8 + 2857 002c 1060 str r0, [r2] +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RC +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemCoreClock = SystemD2Clock; +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** SystemCoreClock = common_system_clock; + 2858 .loc 1 1464 3 is_stmt 1 view .LVU935 + 2859 .loc 1 1464 19 is_stmt 0 view .LVU936 + 2860 002e 044A ldr r2, .L236+12 + 2861 0030 1360 str r3, [r2] +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /* DUAL_CORE && CORE_CM4 */ + ARM GAS /tmp/ccwNdrpc.s page 86 + + +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return SystemD2Clock; + 2862 .loc 1 1467 3 is_stmt 1 view .LVU937 +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2863 .loc 1 1468 1 is_stmt 0 view .LVU938 + 2864 0032 08BD pop {r3, pc} + 2865 .LVL200: + 2866 .L237: + 2867 .loc 1 1468 1 view .LVU939 + 2868 .align 2 + 2869 .L236: + 2870 0034 00440258 .word 1476543488 + 2871 0038 00000000 .word D1CorePrescTable + 2872 003c 00000000 .word SystemD2Clock + 2873 0040 00000000 .word SystemCoreClock + 2874 .cfi_endproc + 2875 .LFE148: + 2877 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits + 2878 .align 1 + 2879 .global HAL_RCC_GetPCLK1Freq + 2880 .syntax unified + 2881 .thumb + 2882 .thumb_func + 2883 .fpu fpv5-d16 + 2885 HAL_RCC_GetPCLK1Freq: + 2886 .LFB149: +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval PCLK1 frequency +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2887 .loc 1 1478 1 is_stmt 1 view -0 + 2888 .cfi_startproc + 2889 @ args = 0, pretend = 0, frame = 0 + 2890 @ frame_needed = 0, uses_anonymous_args = 0 + 2891 0000 08B5 push {r3, lr} + 2892 .LCFI16: + 2893 .cfi_def_cfa_offset 8 + 2894 .cfi_offset 3, -8 + 2895 .cfi_offset 14, -4 +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined (RCC_D2CFGR_D2PPRE1) +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CF + 2896 .loc 1 1481 3 view .LVU941 + 2897 .loc 1 1481 11 is_stmt 0 view .LVU942 + 2898 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2899 .LVL201: + 2900 .loc 1 1481 59 view .LVU943 + 2901 0006 054B ldr r3, .L240 + 2902 0008 DB69 ldr r3, [r3, #28] + 2903 .loc 1 1481 89 view .LVU944 + 2904 000a C3F30213 ubfx r3, r3, #4, #3 + ARM GAS /tmp/ccwNdrpc.s page 87 + + + 2905 .loc 1 1481 54 view .LVU945 + 2906 000e 044A ldr r2, .L240+4 + 2907 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 2908 .loc 1 1481 117 view .LVU946 + 2909 0012 03F01F03 and r3, r3, #31 +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CD +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2910 .loc 1 1486 1 view .LVU947 + 2911 0016 D840 lsrs r0, r0, r3 + 2912 0018 08BD pop {r3, pc} + 2913 .L241: + 2914 001a 00BF .align 2 + 2915 .L240: + 2916 001c 00440258 .word 1476543488 + 2917 0020 00000000 .word D1CorePrescTable + 2918 .cfi_endproc + 2919 .LFE149: + 2921 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits + 2922 .align 1 + 2923 .global HAL_RCC_GetPCLK2Freq + 2924 .syntax unified + 2925 .thumb + 2926 .thumb_func + 2927 .fpu fpv5-d16 + 2929 HAL_RCC_GetPCLK2Freq: + 2930 .LFB150: +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval PCLK1 frequency +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2931 .loc 1 1496 1 is_stmt 1 view -0 + 2932 .cfi_startproc + 2933 @ args = 0, pretend = 0, frame = 0 + 2934 @ frame_needed = 0, uses_anonymous_args = 0 + 2935 0000 08B5 push {r3, lr} + 2936 .LCFI17: + 2937 .cfi_def_cfa_offset 8 + 2938 .cfi_offset 3, -8 + 2939 .cfi_offset 14, -4 +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D2CFGR_D2PPRE2) +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CF + 2940 .loc 1 1499 3 view .LVU949 + 2941 .loc 1 1499 11 is_stmt 0 view .LVU950 + 2942 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2943 .LVL202: + 2944 .loc 1 1499 59 view .LVU951 + 2945 0006 054B ldr r3, .L244 + ARM GAS /tmp/ccwNdrpc.s page 88 + + + 2946 0008 DB69 ldr r3, [r3, #28] + 2947 .loc 1 1499 89 view .LVU952 + 2948 000a C3F30223 ubfx r3, r3, #8, #3 + 2949 .loc 1 1499 54 view .LVU953 + 2950 000e 044A ldr r2, .L244+4 + 2951 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 2952 .loc 1 1499 117 view .LVU954 + 2953 0012 03F01F03 and r3, r3, #31 +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CD +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 2954 .loc 1 1503 1 view .LVU955 + 2955 0016 D840 lsrs r0, r0, r3 + 2956 0018 08BD pop {r3, pc} + 2957 .L245: + 2958 001a 00BF .align 2 + 2959 .L244: + 2960 001c 00440258 .word 1476543488 + 2961 0020 00000000 .word D1CorePrescTable + 2962 .cfi_endproc + 2963 .LFE150: + 2965 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits + 2966 .align 1 + 2967 .global HAL_RCC_GetOscConfig + 2968 .syntax unified + 2969 .thumb + 2970 .thumb_func + 2971 .fpu fpv5-d16 + 2973 HAL_RCC_GetOscConfig: + 2974 .LVL203: + 2975 .LFB151: +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * RCC configuration registers. +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * will be configured. +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 2976 .loc 1 1513 1 is_stmt 1 view -0 + 2977 .cfi_startproc + 2978 @ args = 0, pretend = 0, frame = 0 + 2979 @ frame_needed = 0, uses_anonymous_args = 0 + 2980 .loc 1 1513 1 is_stmt 0 view .LVU957 + 2981 0000 10B5 push {r4, lr} + 2982 .LCFI18: + 2983 .cfi_def_cfa_offset 8 + 2984 .cfi_offset 4, -8 + 2985 .cfi_offset 14, -4 + 2986 0002 0446 mov r4, r0 +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLA + 2987 .loc 1 1515 3 is_stmt 1 view .LVU958 + 2988 .loc 1 1515 37 is_stmt 0 view .LVU959 + ARM GAS /tmp/ccwNdrpc.s page 89 + + + 2989 0004 3F23 movs r3, #63 + 2990 0006 0360 str r3, [r0] +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLAT +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_CR_HSEEXT) +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + 2991 .loc 1 1537 3 is_stmt 1 view .LVU960 + 2992 .loc 1 1537 10 is_stmt 0 view .LVU961 + 2993 0008 514B ldr r3, .L268 + 2994 000a 1B68 ldr r3, [r3] + 2995 .loc 1 1537 5 view .LVU962 + 2996 000c 13F4802F tst r3, #262144 + 2997 0010 6CD0 beq .L247 +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + 2998 .loc 1 1539 5 is_stmt 1 view .LVU963 + 2999 .loc 1 1539 33 is_stmt 0 view .LVU964 + 3000 0012 4FF4A023 mov r3, #327680 + 3001 0016 4360 str r3, [r0, #4] + 3002 .L248: +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /* RCC_CR_HSEEXT */ +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the CSI configuration -----------------------------------------------*/ +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION) + 3003 .loc 1 1552 3 is_stmt 1 view .LVU965 + 3004 .loc 1 1552 10 is_stmt 0 view .LVU966 + 3005 0018 4D4B ldr r3, .L268 + 3006 001a 1B68 ldr r3, [r3] + 3007 .loc 1 1552 5 view .LVU967 + 3008 001c 13F0800F tst r3, #128 + ARM GAS /tmp/ccwNdrpc.s page 90 + + + 3009 0020 70D0 beq .L250 +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->CSIState = RCC_CSI_ON; + 3010 .loc 1 1554 5 is_stmt 1 view .LVU968 + 3011 .loc 1 1554 33 is_stmt 0 view .LVU969 + 3012 0022 8023 movs r3, #128 + 3013 0024 E361 str r3, [r4, #28] + 3014 .L251: +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->CSIState = RCC_CSI_OFF; +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_VER_X) +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(HAL_GetREVID() <= REV_ID_Y) + 3015 .loc 1 1562 3 is_stmt 1 view .LVU970 + 3016 .loc 1 1562 6 is_stmt 0 view .LVU971 + 3017 0026 FFF7FEFF bl HAL_GetREVID + 3018 .LVL204: + 3019 .loc 1 1562 5 view .LVU972 + 3020 002a 41F20303 movw r3, #4099 + 3021 002e 9842 cmp r0, r3 + 3022 0030 6BD8 bhi .L252 +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRI + 3023 .loc 1 1564 5 is_stmt 1 view .LVU973 + 3024 .loc 1 1564 57 is_stmt 0 view .LVU974 + 3025 0032 474B ldr r3, .L268 + 3026 0034 5B68 ldr r3, [r3, #4] + 3027 .loc 1 1564 46 view .LVU975 + 3028 0036 C3F38463 ubfx r3, r3, #26, #5 + 3029 .loc 1 1564 44 view .LVU976 + 3030 003a 2362 str r3, [r4, #32] + 3031 .L253: +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /*RCC_VER_X*/ +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + 3032 .loc 1 1575 3 is_stmt 1 view .LVU977 + 3033 .loc 1 1575 10 is_stmt 0 view .LVU978 + 3034 003c 444B ldr r3, .L268 + 3035 003e 1B68 ldr r3, [r3] + 3036 .loc 1 1575 5 view .LVU979 + 3037 0040 13F0010F tst r3, #1 + 3038 0044 67D0 beq .L254 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; + 3039 .loc 1 1577 5 is_stmt 1 view .LVU980 + 3040 .loc 1 1577 33 is_stmt 0 view .LVU981 + ARM GAS /tmp/ccwNdrpc.s page 91 + + + 3041 0046 0123 movs r3, #1 + 3042 0048 E360 str r3, [r4, #12] + 3043 .L255: +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_VER_X) +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(HAL_GetREVID() <= REV_ID_Y) + 3044 .loc 1 1585 3 is_stmt 1 view .LVU982 + 3045 .loc 1 1585 6 is_stmt 0 view .LVU983 + 3046 004a FFF7FEFF bl HAL_GetREVID + 3047 .LVL205: + 3048 .loc 1 1585 5 view .LVU984 + 3049 004e 41F20303 movw r3, #4099 + 3050 0052 9842 cmp r0, r3 + 3051 0054 62D8 bhi .L256 +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRI + 3052 .loc 1 1587 5 is_stmt 1 view .LVU985 + 3053 .loc 1 1587 57 is_stmt 0 view .LVU986 + 3054 0056 3E4B ldr r3, .L268 + 3055 0058 5B68 ldr r3, [r3, #4] + 3056 .loc 1 1587 46 view .LVU987 + 3057 005a C3F30533 ubfx r3, r3, #12, #6 + 3058 .loc 1 1587 44 view .LVU988 + 3059 005e 2361 str r3, [r4, #16] + 3060 .L257: +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /*RCC_VER_X*/ +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_BDCR_LSEEXT) +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 92 + + +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + 3061 .loc 1 1616 3 is_stmt 1 view .LVU989 + 3062 .loc 1 1616 10 is_stmt 0 view .LVU990 + 3063 0060 3B4B ldr r3, .L268 + 3064 0062 1B6F ldr r3, [r3, #112] + 3065 .loc 1 1616 5 view .LVU991 + 3066 0064 13F0040F tst r3, #4 + 3067 0068 5ED0 beq .L258 +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + 3068 .loc 1 1618 5 is_stmt 1 view .LVU992 + 3069 .loc 1 1618 33 is_stmt 0 view .LVU993 + 3070 006a 0523 movs r3, #5 + 3071 006c A360 str r3, [r4, #8] + 3072 .L259: +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif /* RCC_BDCR_LSEEXT */ +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + 3073 .loc 1 1631 3 is_stmt 1 view .LVU994 + 3074 .loc 1 1631 10 is_stmt 0 view .LVU995 + 3075 006e 384B ldr r3, .L268 + 3076 0070 5B6F ldr r3, [r3, #116] + 3077 .loc 1 1631 5 view .LVU996 + 3078 0072 13F0010F tst r3, #1 + 3079 0076 62D0 beq .L261 +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; + 3080 .loc 1 1633 5 is_stmt 1 view .LVU997 + 3081 .loc 1 1633 33 is_stmt 0 view .LVU998 + 3082 0078 0123 movs r3, #1 + 3083 007a 6361 str r3, [r4, #20] + 3084 .L262: +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the HSI48 configuration ---------------------------------------------*/ +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + 3085 .loc 1 1641 3 is_stmt 1 view .LVU999 + 3086 .loc 1 1641 10 is_stmt 0 view .LVU1000 + 3087 007c 344B ldr r3, .L268 + 3088 007e 1B68 ldr r3, [r3] + 3089 .loc 1 1641 5 view .LVU1001 + 3090 0080 13F4805F tst r3, #4096 + ARM GAS /tmp/ccwNdrpc.s page 93 + + + 3091 0084 5ED0 beq .L263 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + 3092 .loc 1 1643 5 is_stmt 1 view .LVU1002 + 3093 .loc 1 1643 35 is_stmt 0 view .LVU1003 + 3094 0086 0123 movs r3, #1 + 3095 0088 A361 str r3, [r4, #24] + 3096 .L264: +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + 3097 .loc 1 1651 3 is_stmt 1 view .LVU1004 + 3098 .loc 1 1651 10 is_stmt 0 view .LVU1005 + 3099 008a 314B ldr r3, .L268 + 3100 008c 1B68 ldr r3, [r3] + 3101 .loc 1 1651 5 view .LVU1006 + 3102 008e 13F0807F tst r3, #16777216 + 3103 0092 5AD0 beq .L265 +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + 3104 .loc 1 1653 5 is_stmt 1 view .LVU1007 + 3105 .loc 1 1653 37 is_stmt 0 view .LVU1008 + 3106 0094 0223 movs r3, #2 + 3107 0096 6362 str r3, [r4, #36] + 3108 .L266: +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** else +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + 3109 .loc 1 1659 3 is_stmt 1 view .LVU1009 + 3110 .loc 1 1659 52 is_stmt 0 view .LVU1010 + 3111 0098 2D4B ldr r3, .L268 + 3112 009a 9A6A ldr r2, [r3, #40] + 3113 .loc 1 1659 38 view .LVU1011 + 3114 009c 02F00302 and r2, r2, #3 + 3115 .loc 1 1659 36 view .LVU1012 + 3116 00a0 A262 str r2, [r4, #40] +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_D + 3117 .loc 1 1660 3 is_stmt 1 view .LVU1013 + 3118 .loc 1 1660 48 is_stmt 0 view .LVU1014 + 3119 00a2 9A6A ldr r2, [r3, #40] + 3120 .loc 1 1660 33 view .LVU1015 + 3121 00a4 C2F30512 ubfx r2, r2, #4, #6 + 3122 .loc 1 1660 31 view .LVU1016 + 3123 00a8 E262 str r2, [r4, #44] +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos + 3124 .loc 1 1661 3 is_stmt 1 view .LVU1017 + 3125 .loc 1 1661 48 is_stmt 0 view .LVU1018 + 3126 00aa 1A6B ldr r2, [r3, #48] + 3127 .loc 1 1661 33 view .LVU1019 + ARM GAS /tmp/ccwNdrpc.s page 94 + + + 3128 00ac C2F30802 ubfx r2, r2, #0, #9 + 3129 .loc 1 1661 101 view .LVU1020 + 3130 00b0 0132 adds r2, r2, #1 + 3131 .loc 1 1661 31 view .LVU1021 + 3132 00b2 2263 str r2, [r4, #48] +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos + 3133 .loc 1 1662 3 is_stmt 1 view .LVU1022 + 3134 .loc 1 1662 48 is_stmt 0 view .LVU1023 + 3135 00b4 1A6B ldr r2, [r3, #48] + 3136 .loc 1 1662 33 view .LVU1024 + 3137 00b6 C2F30662 ubfx r2, r2, #24, #7 + 3138 .loc 1 1662 101 view .LVU1025 + 3139 00ba 0132 adds r2, r2, #1 + 3140 .loc 1 1662 31 view .LVU1026 + 3141 00bc E263 str r2, [r4, #60] +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos + 3142 .loc 1 1663 3 is_stmt 1 view .LVU1027 + 3143 .loc 1 1663 48 is_stmt 0 view .LVU1028 + 3144 00be 1A6B ldr r2, [r3, #48] + 3145 .loc 1 1663 33 view .LVU1029 + 3146 00c0 C2F34622 ubfx r2, r2, #9, #7 + 3147 .loc 1 1663 101 view .LVU1030 + 3148 00c4 0132 adds r2, r2, #1 + 3149 .loc 1 1663 31 view .LVU1031 + 3150 00c6 6263 str r2, [r4, #52] +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos + 3151 .loc 1 1664 3 is_stmt 1 view .LVU1032 + 3152 .loc 1 1664 48 is_stmt 0 view .LVU1033 + 3153 00c8 1A6B ldr r2, [r3, #48] + 3154 .loc 1 1664 33 view .LVU1034 + 3155 00ca C2F30642 ubfx r2, r2, #16, #7 + 3156 .loc 1 1664 101 view .LVU1035 + 3157 00ce 0132 adds r2, r2, #1 + 3158 .loc 1 1664 31 view .LVU1036 + 3159 00d0 A263 str r2, [r4, #56] +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE)); + 3160 .loc 1 1665 3 is_stmt 1 view .LVU1037 + 3161 .loc 1 1665 50 is_stmt 0 view .LVU1038 + 3162 00d2 DA6A ldr r2, [r3, #44] + 3163 .loc 1 1665 35 view .LVU1039 + 3164 00d4 02F00C02 and r2, r2, #12 + 3165 .loc 1 1665 33 view .LVU1040 + 3166 00d8 2264 str r2, [r4, #64] +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLC + 3167 .loc 1 1666 3 is_stmt 1 view .LVU1041 + 3168 .loc 1 1666 53 is_stmt 0 view .LVU1042 + 3169 00da DA6A ldr r2, [r3, #44] + 3170 .loc 1 1666 38 view .LVU1043 + 3171 00dc C2F34002 ubfx r2, r2, #1, #1 + 3172 .loc 1 1666 36 view .LVU1044 + 3173 00e0 6264 str r2, [r4, #68] +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1 + 3174 .loc 1 1667 3 is_stmt 1 view .LVU1045 + 3175 .loc 1 1667 53 is_stmt 0 view .LVU1046 + 3176 00e2 5B6B ldr r3, [r3, #52] + 3177 .loc 1 1667 37 view .LVU1047 + 3178 00e4 C3F3CC03 ubfx r3, r3, #3, #13 + ARM GAS /tmp/ccwNdrpc.s page 95 + + + 3179 .loc 1 1667 35 view .LVU1048 + 3180 00e8 A364 str r3, [r4, #72] +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3181 .loc 1 1668 1 view .LVU1049 + 3182 00ea 10BD pop {r4, pc} + 3183 .LVL206: + 3184 .L247: +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3185 .loc 1 1541 8 is_stmt 1 view .LVU1050 +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3186 .loc 1 1541 15 is_stmt 0 view .LVU1051 + 3187 00ec 184B ldr r3, .L268 + 3188 00ee 1B68 ldr r3, [r3] +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3189 .loc 1 1541 10 view .LVU1052 + 3190 00f0 13F4803F tst r3, #65536 + 3191 00f4 03D0 beq .L249 +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3192 .loc 1 1543 5 is_stmt 1 view .LVU1053 +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3193 .loc 1 1543 33 is_stmt 0 view .LVU1054 + 3194 00f6 4FF48033 mov r3, #65536 + 3195 00fa 4360 str r3, [r0, #4] + 3196 00fc 8CE7 b .L248 + 3197 .L249: +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3198 .loc 1 1547 5 is_stmt 1 view .LVU1055 +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3199 .loc 1 1547 33 is_stmt 0 view .LVU1056 + 3200 00fe 0023 movs r3, #0 + 3201 0100 4360 str r3, [r0, #4] + 3202 0102 89E7 b .L248 + 3203 .L250: +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3204 .loc 1 1558 5 is_stmt 1 view .LVU1057 +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3205 .loc 1 1558 33 is_stmt 0 view .LVU1058 + 3206 0104 0023 movs r3, #0 + 3207 0106 E361 str r3, [r4, #28] + 3208 0108 8DE7 b .L251 + 3209 .LVL207: + 3210 .L252: +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3211 .loc 1 1568 5 is_stmt 1 view .LVU1059 +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3212 .loc 1 1568 57 is_stmt 0 view .LVU1060 + 3213 010a 114B ldr r3, .L268 + 3214 010c DB68 ldr r3, [r3, #12] +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3215 .loc 1 1568 46 view .LVU1061 + 3216 010e C3F30563 ubfx r3, r3, #24, #6 +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3217 .loc 1 1568 44 view .LVU1062 + 3218 0112 2362 str r3, [r4, #32] + 3219 0114 92E7 b .L253 + 3220 .L254: +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + ARM GAS /tmp/ccwNdrpc.s page 96 + + + 3221 .loc 1 1581 5 is_stmt 1 view .LVU1063 +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3222 .loc 1 1581 33 is_stmt 0 view .LVU1064 + 3223 0116 0023 movs r3, #0 + 3224 0118 E360 str r3, [r4, #12] + 3225 011a 96E7 b .L255 + 3226 .L256: +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3227 .loc 1 1591 5 is_stmt 1 view .LVU1065 +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3228 .loc 1 1591 57 is_stmt 0 view .LVU1066 + 3229 011c 0C4B ldr r3, .L268 + 3230 011e 5B68 ldr r3, [r3, #4] +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3231 .loc 1 1591 46 view .LVU1067 + 3232 0120 C3F30663 ubfx r3, r3, #24, #7 +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3233 .loc 1 1591 44 view .LVU1068 + 3234 0124 2361 str r3, [r4, #16] + 3235 0126 9BE7 b .L257 + 3236 .L258: +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3237 .loc 1 1620 8 is_stmt 1 view .LVU1069 +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3238 .loc 1 1620 15 is_stmt 0 view .LVU1070 + 3239 0128 094B ldr r3, .L268 + 3240 012a 1B6F ldr r3, [r3, #112] +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3241 .loc 1 1620 10 view .LVU1071 + 3242 012c 13F0010F tst r3, #1 + 3243 0130 02D0 beq .L260 +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3244 .loc 1 1622 5 is_stmt 1 view .LVU1072 +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3245 .loc 1 1622 33 is_stmt 0 view .LVU1073 + 3246 0132 0123 movs r3, #1 + 3247 0134 A360 str r3, [r4, #8] + 3248 0136 9AE7 b .L259 + 3249 .L260: +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3250 .loc 1 1626 5 is_stmt 1 view .LVU1074 +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3251 .loc 1 1626 33 is_stmt 0 view .LVU1075 + 3252 0138 0023 movs r3, #0 + 3253 013a A360 str r3, [r4, #8] + 3254 013c 97E7 b .L259 + 3255 .L261: +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3256 .loc 1 1637 5 is_stmt 1 view .LVU1076 +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3257 .loc 1 1637 33 is_stmt 0 view .LVU1077 + 3258 013e 0023 movs r3, #0 + 3259 0140 6361 str r3, [r4, #20] + 3260 0142 9BE7 b .L262 + 3261 .L263: +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3262 .loc 1 1647 5 is_stmt 1 view .LVU1078 + ARM GAS /tmp/ccwNdrpc.s page 97 + + +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3263 .loc 1 1647 35 is_stmt 0 view .LVU1079 + 3264 0144 0023 movs r3, #0 + 3265 0146 A361 str r3, [r4, #24] + 3266 0148 9FE7 b .L264 + 3267 .L265: +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3268 .loc 1 1657 5 is_stmt 1 view .LVU1080 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3269 .loc 1 1657 37 is_stmt 0 view .LVU1081 + 3270 014a 0123 movs r3, #1 + 3271 014c 6362 str r3, [r4, #36] + 3272 014e A3E7 b .L266 + 3273 .L269: + 3274 .align 2 + 3275 .L268: + 3276 0150 00440258 .word 1476543488 + 3277 .cfi_endproc + 3278 .LFE151: + 3280 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits + 3281 .align 1 + 3282 .global HAL_RCC_GetClockConfig + 3283 .syntax unified + 3284 .thumb + 3285 .thumb_func + 3286 .fpu fpv5-d16 + 3288 HAL_RCC_GetClockConfig: + 3289 .LVL208: + 3290 .LFB152: +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief Configures the RCC_ClkInitStruct according to the internal +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * RCC configuration registers. +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * will be configured. +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @param pFLatency: Pointer on the Flash Latency. +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3291 .loc 1 1679 1 is_stmt 1 view -0 + 3292 .cfi_startproc + 3293 @ args = 0, pretend = 0, frame = 0 + 3294 @ frame_needed = 0, uses_anonymous_args = 0 + 3295 @ link register save eliminated. +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 + 3296 .loc 1 1681 3 view .LVU1083 + 3297 .loc 1 1681 32 is_stmt 0 view .LVU1084 + 3298 0000 3F23 movs r3, #63 + 3299 0002 0360 str r3, [r0] +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 3300 .loc 1 1685 3 is_stmt 1 view .LVU1085 + 3301 .loc 1 1685 51 is_stmt 0 view .LVU1086 + ARM GAS /tmp/ccwNdrpc.s page 98 + + + 3302 0004 114B ldr r3, .L271 + 3303 0006 1A69 ldr r2, [r3, #16] + 3304 .loc 1 1685 37 view .LVU1087 + 3305 0008 02F00702 and r2, r2, #7 + 3306 .loc 1 1685 35 view .LVU1088 + 3307 000c 4260 str r2, [r0, #4] +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #if defined(RCC_D1CFGR_D1CPRE) +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the SYSCLK configuration ----------------------------------------------*/ +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); + 3308 .loc 1 1689 3 is_stmt 1 view .LVU1089 + 3309 .loc 1 1689 52 is_stmt 0 view .LVU1090 + 3310 000e 9A69 ldr r2, [r3, #24] + 3311 .loc 1 1689 38 view .LVU1091 + 3312 0010 02F47062 and r2, r2, #3840 + 3313 .loc 1 1689 36 view .LVU1092 + 3314 0014 8260 str r2, [r0, #8] +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the D1HCLK configuration ----------------------------------------------*/ +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); + 3315 .loc 1 1692 3 is_stmt 1 view .LVU1093 + 3316 .loc 1 1692 52 is_stmt 0 view .LVU1094 + 3317 0016 9A69 ldr r2, [r3, #24] + 3318 .loc 1 1692 38 view .LVU1095 + 3319 0018 02F00F02 and r2, r2, #15 + 3320 .loc 1 1692 36 view .LVU1096 + 3321 001c C260 str r2, [r0, #12] +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB3 configuration ----------------------------------------------*/ +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); + 3322 .loc 1 1695 3 is_stmt 1 view .LVU1097 + 3323 .loc 1 1695 53 is_stmt 0 view .LVU1098 + 3324 001e 9A69 ldr r2, [r3, #24] + 3325 .loc 1 1695 39 view .LVU1099 + 3326 0020 02F07002 and r2, r2, #112 + 3327 .loc 1 1695 37 view .LVU1100 + 3328 0024 0261 str r2, [r0, #16] +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); + 3329 .loc 1 1698 3 is_stmt 1 view .LVU1101 + 3330 .loc 1 1698 53 is_stmt 0 view .LVU1102 + 3331 0026 DA69 ldr r2, [r3, #28] + 3332 .loc 1 1698 39 view .LVU1103 + 3333 0028 02F07002 and r2, r2, #112 + 3334 .loc 1 1698 37 view .LVU1104 + 3335 002c 4261 str r2, [r0, #20] +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); + 3336 .loc 1 1701 3 is_stmt 1 view .LVU1105 + 3337 .loc 1 1701 53 is_stmt 0 view .LVU1106 + 3338 002e DA69 ldr r2, [r3, #28] + 3339 .loc 1 1701 39 view .LVU1107 + 3340 0030 02F4E062 and r2, r2, #1792 + 3341 .loc 1 1701 37 view .LVU1108 + 3342 0034 8261 str r2, [r0, #24] + ARM GAS /tmp/ccwNdrpc.s page 99 + + +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB4 configuration ----------------------------------------------*/ +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); + 3343 .loc 1 1704 3 is_stmt 1 view .LVU1109 + 3344 .loc 1 1704 53 is_stmt 0 view .LVU1110 + 3345 0036 1B6A ldr r3, [r3, #32] + 3346 .loc 1 1704 39 view .LVU1111 + 3347 0038 03F07003 and r3, r3, #112 + 3348 .loc 1 1704 37 view .LVU1112 + 3349 003c C361 str r3, [r0, #28] +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #else +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the SYSCLK configuration ----------------------------------------------*/ +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE); +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the D1HCLK configuration ----------------------------------------------*/ +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE); +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB3 configuration ----------------------------------------------*/ +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE); +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1); +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2); +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the APB4 configuration ----------------------------------------------*/ +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** #endif +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 3350 .loc 1 1726 3 is_stmt 1 view .LVU1113 + 3351 .loc 1 1726 32 is_stmt 0 view .LVU1114 + 3352 003e 044B ldr r3, .L271+4 + 3353 0040 1B68 ldr r3, [r3] + 3354 .loc 1 1726 16 view .LVU1115 + 3355 0042 03F00F03 and r3, r3, #15 + 3356 .loc 1 1726 14 view .LVU1116 + 3357 0046 0B60 str r3, [r1] +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3358 .loc 1 1727 1 view .LVU1117 + 3359 0048 7047 bx lr + 3360 .L272: + 3361 004a 00BF .align 2 + 3362 .L271: + 3363 004c 00440258 .word 1476543488 + 3364 0050 00200052 .word 1375739904 + 3365 .cfi_endproc + 3366 .LFE152: + 3368 .section .text.HAL_RCC_CSSCallback,"ax",%progbits + 3369 .align 1 + 3370 .weak HAL_RCC_CSSCallback + 3371 .syntax unified + 3372 .thumb + 3373 .thumb_func + 3374 .fpu fpv5-d16 + ARM GAS /tmp/ccwNdrpc.s page 100 + + + 3376 HAL_RCC_CSSCallback: + 3377 .LFB154: +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval None +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check RCC CSSF flag */ +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** if(__HAL_RCC_GET_IT(RCC_IT_CSS)) +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** HAL_RCC_CCSCallback(); +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /** +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** * @retval none +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** __weak void HAL_RCC_CCSCallback(void) +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3378 .loc 1 1752 1 is_stmt 1 view -0 + 3379 .cfi_startproc + 3380 @ args = 0, pretend = 0, frame = 0 + 3381 @ frame_needed = 0, uses_anonymous_args = 0 + 3382 @ link register save eliminated. +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** the HAL_RCC_CCSCallback could be implemented in the user file +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** */ +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3383 .loc 1 1756 1 view .LVU1119 + 3384 0000 7047 bx lr + 3385 .cfi_endproc + 3386 .LFE154: + 3388 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits + 3389 .align 1 + 3390 .global HAL_RCC_NMI_IRQHandler + 3391 .syntax unified + 3392 .thumb + 3393 .thumb_func + 3394 .fpu fpv5-d16 + 3396 HAL_RCC_NMI_IRQHandler: + 3397 .LFB153: +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** /* Check RCC CSSF flag */ + 3398 .loc 1 1735 1 view -0 + 3399 .cfi_startproc + 3400 @ args = 0, pretend = 0, frame = 0 + 3401 @ frame_needed = 0, uses_anonymous_args = 0 + 3402 0000 08B5 push {r3, lr} + 3403 .LCFI19: + 3404 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccwNdrpc.s page 101 + + + 3405 .cfi_offset 3, -8 + 3406 .cfi_offset 14, -4 +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3407 .loc 1 1737 3 view .LVU1121 +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3408 .loc 1 1737 6 is_stmt 0 view .LVU1122 + 3409 0002 064B ldr r3, .L278 + 3410 0004 5B6E ldr r3, [r3, #100] +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** { + 3411 .loc 1 1737 5 view .LVU1123 + 3412 0006 13F4806F tst r3, #1024 + 3413 000a 00D1 bne .L277 + 3414 .L274: +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 3415 .loc 1 1745 1 view .LVU1124 + 3416 000c 08BD pop {r3, pc} + 3417 .L277: +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 3418 .loc 1 1740 5 is_stmt 1 view .LVU1125 + 3419 000e FFF7FEFF bl HAL_RCC_CSSCallback + 3420 .LVL209: +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** } + 3421 .loc 1 1743 5 view .LVU1126 + 3422 0012 024B ldr r3, .L278 + 3423 0014 4FF48062 mov r2, #1024 + 3424 0018 9A66 str r2, [r3, #104] +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c **** + 3425 .loc 1 1745 1 is_stmt 0 view .LVU1127 + 3426 001a F7E7 b .L274 + 3427 .L279: + 3428 .align 2 + 3429 .L278: + 3430 001c 00440258 .word 1476543488 + 3431 .cfi_endproc + 3432 .LFE153: + 3434 .text + 3435 .Letext0: + 3436 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 3437 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 3438 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + 3439 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 3440 .file 6 "/usr/arm-none-eabi/include/math.h" + 3441 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 3442 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" + 3443 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + 3444 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccwNdrpc.s page 102 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_rcc.c + /tmp/ccwNdrpc.s:17 .text.HAL_RCC_DeInit:0000000000000000 $t + /tmp/ccwNdrpc.s:25 .text.HAL_RCC_DeInit:0000000000000000 HAL_RCC_DeInit + /tmp/ccwNdrpc.s:372 .text.HAL_RCC_DeInit:00000000000001a4 $d + /tmp/ccwNdrpc.s:386 .text.HAL_RCC_OscConfig:0000000000000000 $t + /tmp/ccwNdrpc.s:393 .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig + /tmp/ccwNdrpc.s:922 .text.HAL_RCC_OscConfig:0000000000000288 $d + /tmp/ccwNdrpc.s:925 .text.HAL_RCC_OscConfig:000000000000028c $t + /tmp/ccwNdrpc.s:1421 .text.HAL_RCC_OscConfig:00000000000004f8 $d + /tmp/ccwNdrpc.s:1426 .text.HAL_RCC_OscConfig:0000000000000500 $t + /tmp/ccwNdrpc.s:1704 .text.HAL_RCC_OscConfig:0000000000000640 $d + /tmp/ccwNdrpc.s:1711 .text.HAL_RCC_MCOConfig:0000000000000000 $t + /tmp/ccwNdrpc.s:1718 .text.HAL_RCC_MCOConfig:0000000000000000 HAL_RCC_MCOConfig + /tmp/ccwNdrpc.s:1868 .text.HAL_RCC_MCOConfig:0000000000000098 $d + /tmp/ccwNdrpc.s:1875 .text.HAL_RCC_EnableCSS:0000000000000000 $t + /tmp/ccwNdrpc.s:1882 .text.HAL_RCC_EnableCSS:0000000000000000 HAL_RCC_EnableCSS + /tmp/ccwNdrpc.s:1899 .text.HAL_RCC_EnableCSS:000000000000000c $d + /tmp/ccwNdrpc.s:1904 .text.HAL_RCC_DisableCSS:0000000000000000 $t + /tmp/ccwNdrpc.s:1911 .text.HAL_RCC_DisableCSS:0000000000000000 HAL_RCC_DisableCSS + /tmp/ccwNdrpc.s:1928 .text.HAL_RCC_DisableCSS:000000000000000c $d + /tmp/ccwNdrpc.s:1933 .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t + /tmp/ccwNdrpc.s:1940 .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq + /tmp/ccwNdrpc.s:2253 .text.HAL_RCC_GetSysClockFreq:00000000000001d4 $d + /tmp/ccwNdrpc.s:2265 .text.HAL_RCC_ClockConfig:0000000000000000 $t + /tmp/ccwNdrpc.s:2272 .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig + /tmp/ccwNdrpc.s:2798 .text.HAL_RCC_ClockConfig:000000000000027c $d + /tmp/ccwNdrpc.s:2808 .text.HAL_RCC_GetHCLKFreq:0000000000000000 $t + /tmp/ccwNdrpc.s:2815 .text.HAL_RCC_GetHCLKFreq:0000000000000000 HAL_RCC_GetHCLKFreq + /tmp/ccwNdrpc.s:2870 .text.HAL_RCC_GetHCLKFreq:0000000000000034 $d + /tmp/ccwNdrpc.s:2878 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t + /tmp/ccwNdrpc.s:2885 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq + /tmp/ccwNdrpc.s:2916 .text.HAL_RCC_GetPCLK1Freq:000000000000001c $d + /tmp/ccwNdrpc.s:2922 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t + /tmp/ccwNdrpc.s:2929 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq + /tmp/ccwNdrpc.s:2960 .text.HAL_RCC_GetPCLK2Freq:000000000000001c $d + /tmp/ccwNdrpc.s:2966 .text.HAL_RCC_GetOscConfig:0000000000000000 $t + /tmp/ccwNdrpc.s:2973 .text.HAL_RCC_GetOscConfig:0000000000000000 HAL_RCC_GetOscConfig + /tmp/ccwNdrpc.s:3276 .text.HAL_RCC_GetOscConfig:0000000000000150 $d + /tmp/ccwNdrpc.s:3281 .text.HAL_RCC_GetClockConfig:0000000000000000 $t + /tmp/ccwNdrpc.s:3288 .text.HAL_RCC_GetClockConfig:0000000000000000 HAL_RCC_GetClockConfig + /tmp/ccwNdrpc.s:3363 .text.HAL_RCC_GetClockConfig:000000000000004c $d + /tmp/ccwNdrpc.s:3369 .text.HAL_RCC_CSSCallback:0000000000000000 $t + /tmp/ccwNdrpc.s:3376 .text.HAL_RCC_CSSCallback:0000000000000000 HAL_RCC_CSSCallback + /tmp/ccwNdrpc.s:3389 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 $t + /tmp/ccwNdrpc.s:3396 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 HAL_RCC_NMI_IRQHandler + /tmp/ccwNdrpc.s:3430 .text.HAL_RCC_NMI_IRQHandler:000000000000001c $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_InitTick +SystemCoreClock +SystemD2Clock +uwTickPrio +HAL_GetREVID +HAL_GPIO_Init +D1CorePrescTable + ARM GAS /tmp/ccwNdrpc.s page 103 + + diff --git a/build/stm32h7xx_hal_rcc.o b/build/stm32h7xx_hal_rcc.o new file mode 100644 index 0000000..b17c776 Binary files /dev/null and b/build/stm32h7xx_hal_rcc.o differ diff --git a/build/stm32h7xx_hal_rcc_ex.d b/build/stm32h7xx_hal_rcc_ex.d new file mode 100644 index 0000000..17c84d4 --- /dev/null +++ b/build/stm32h7xx_hal_rcc_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_rcc_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_rcc_ex.lst b/build/stm32h7xx_hal_rcc_ex.lst new file mode 100644 index 0000000..62eb650 --- /dev/null +++ b/build/stm32h7xx_hal_rcc_ex.lst @@ -0,0 +1,11712 @@ +ARM GAS /tmp/ccSY6g1k.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_rcc_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.RCCEx_PLL2_Config,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 RCCEx_PLL2_Config: + 25 .LVL0: + 26 .LFB165: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @file stm32h7xx_hal_rcc_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Extended RCC HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * functionalities RCC extension peripheral: + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ****************************************************************************** + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @attention + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** *

© COPYRIGHT(c) 2017 STMicroelectronics. + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * All rights reserved.

+ 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * the "License"; You may not use this file except in compliance with the + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * License. You may obtain a copy of the License at: + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * opensource.org/licenses/BSD-3-Clause + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ****************************************************************************** + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #include "stm32h7xx_hal.h" + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx + ARM GAS /tmp/ccSY6g1k.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief RCC HAL module driver + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Private defines -----------------------------------------------------------*/ + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_defines RCCEx Private Defines + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #define DIVIDER_P_UPDATE 0U + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #define DIVIDER_Q_UPDATE 1U + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #define DIVIDER_R_UPDATE 2U + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @} + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Private macros ------------------------------------------------------------*/ + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @} + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Exported functions --------------------------------------------------------*/ + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** @verbatim + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** =============================================================================== + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions ##### + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** =============================================================================== + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** [..] + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequencies. + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** [..] + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** the backup registers) and RCC_BDCR register are set to their reset values. + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** @endverbatim + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ + ARM GAS /tmp/ccSY6g1k.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Initializes the RCC extended peripherals clocks according to the specified + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef. + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * contains the configuration information for the Extended Peripherals + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWP + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * SAI4A*, SAI4B*, SPI6, RTC). + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * the RTC clock source; in this case the Backup domain will be reset in + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * order to modify the RTC Clock source, as consequence RTC registers (including + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * the backup registers) are set to their reset values. + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * (*) : Available on some STM32H7 lines only. + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval HAL status + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tmpreg; + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SPDIFRX configuration -------------------------------*/ + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->SpdifrxClockSelection) + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable PLL1Q Clock output generated form System PLL . */ + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIFRX clock source configuration done later after clock selection check */ + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIFRX clock source configuration done later after clock selection check */ + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIFRX clock source configuration done later after clock selection check */ + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPDIFRXCLKSOURCE_HSI: + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Internal OSC clock is used as source of SPDIFRX clock*/ + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIFRX clock source configuration done later after clock selection check */ + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SPDIFRX clock*/ + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SAI1 configuration -------------------------------*/ + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Sai1ClockSelection) + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SAI Clock output generated form System PLL . */ + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PIN: + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SAI1 clock*/ + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_CLKP: + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SAI1 clock*/ + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SAI2/3 configuration -------------------------------*/ + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Sai23ClockSelection) + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SAI Clock output generated form System PLL . */ + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2/3 clock source configuration done later after clock selection check */ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2/3 clock source configuration done later after clock selection check */ + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2/3 clock source configuration done later after clock selection check */ + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_PIN: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SAI2/3 clock*/ + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2/3 clock source configuration done later after clock selection check */ + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_CLKP: + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2/3 clock source configuration done later after clock selection check */ + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SAI2/3 clock*/ + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); + ARM GAS /tmp/ccSY6g1k.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI3 */ + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2ASEL) + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SAI2A configuration -------------------------------*/ + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Sai2AClockSelection) + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SAI2A Clock output generated form System PLL . */ + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2A clock source configuration done later after clock selection check */ + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2A clock source configuration done later after clock selection check */ + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2A clock source configuration done later after clock selection check */ + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_PIN: + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SAI2A clock*/ + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2A clock source configuration done later after clock selection check */ + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_CLKP: + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2A clock source configuration done later after clock selection check */ + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_SPDIF: + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIF clock is used as source of SAI2A clock */ + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2A clock source configuration done later after clock selection check */ + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + ARM GAS /tmp/ccSY6g1k.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SAI2A clock*/ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI2A*/ + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2BSEL) + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SAI2B configuration -------------------------------*/ + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Sai2BClockSelection) + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SAI Clock output generated form System PLL . */ + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2B clock source configuration done later after clock selection check */ + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2B clock source configuration done later after clock selection check */ + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2B clock source configuration done later after clock selection check */ + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_PIN: + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SAI2B clock*/ + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2B clock source configuration done later after clock selection check */ + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_CLKP: + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2B clock source configuration done later after clock selection check */ + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_SPDIF: + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIF clock is used as source of SAI2B clock */ + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2B clock source configuration done later after clock selection check */ + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SAI2B clock*/ + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI2B*/ + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI4) + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SAI4A configuration -------------------------------*/ + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Sai4AClockSelection) + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SAI Clock output generated form System PLL . */ + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2 clock source configuration done later after clock selection check */ + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4ACLKSOURCE_PIN: + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SAI2 clock*/ + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2 clock source configuration done later after clock selection check */ + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4ACLKSOURCE_CLKP: + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_VER_3_0) + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4ACLKSOURCE_SPDIF: + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIF clock is used as source of SAI4A clock */ + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI4A clock source configuration done later after clock selection check */ + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* RCC_VER_3_0 */ + ARM GAS /tmp/ccSY6g1k.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SAI4A clock*/ + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SAI4B configuration -------------------------------*/ + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Sai4BClockSelection) + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SAI Clock output generated form System PLL . */ + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2 clock source configuration done later after clock selection check */ + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4BCLKSOURCE_PIN: + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SAI2 clock*/ + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI2 clock source configuration done later after clock selection check */ + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4BCLKSOURCE_CLKP: + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI1 clock source configuration done later after clock selection check */ + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_VER_3_0) + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI4BCLKSOURCE_SPDIF: + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPDIF clock is used as source of SAI4B clock */ + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SAI4B clock source configuration done later after clock selection check */ + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* RCC_VER_3_0 */ + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SAI4B clock*/ + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI4*/ + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(QUADSPI) + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- QSPI configuration -------------------------------*/ + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->QspiClockSelection) + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable QSPI Clock output generated form System PLL . */ + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* QSPI clock source configuration done later after clock selection check */ + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* QSPI clock source configuration done later after clock selection check */ + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_QSPICLKSOURCE_CLKP: + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* QSPI clock source configuration done later after clock selection check */ + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_QSPICLKSOURCE_D1HCLK: + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of QSPI clock*/ + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*QUADSPI*/ + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(OCTOSPI1) || defined(OCTOSPI2) + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- OCTOSPI configuration -------------------------------*/ + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->OspiClockSelection) + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable OSPI Clock output generated form System PLL . */ + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* OSPI clock source configuration done later after clock selection check */ + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* OSPI clock source configuration done later after clock selection check */ + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_OSPICLKSOURCE_CLKP: + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* OSPI clock source configuration done later after clock selection check */ + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_OSPICLKSOURCE_HCLK: + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HCLK clock selected as OSPI kernel peripheral clock */ + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of OSPI clock*/ + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*OCTOSPI*/ + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SPI1/2/3 configuration -------------------------------*/ + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Spi123ClockSelection) + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SPI Clock output generated form System PLL . */ + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI1/2/3 clock source configuration done later after clock selection check */ + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI1/2/3 clock source configuration done later after clock selection check */ + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI1/2/3 clock source configuration done later after clock selection check */ + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PIN: + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External clock is used as source of SPI1/2/3 clock*/ + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI1/2/3 clock source configuration done later after clock selection check */ + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_CLKP: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI1/2/3 clock source configuration done later after clock selection check */ + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SPI1/2/3 clock*/ + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SPI4/5 configuration -------------------------------*/ + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Spi45ClockSelection) + ARM GAS /tmp/ccSY6g1k.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for SPI4/5 */ + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_HSI: + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI oscillator clock is used as source of SPI4/5 clock*/ + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_CSI: + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CSI oscillator clock is used as source of SPI4/5 clock */ + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_HSE: + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSE, oscillator is used as source of SPI4/5 clock */ + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SPI4/5 clock*/ + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- SPI6 configuration -------------------------------*/ + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Spi6ClockSelection) + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_HSI: + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI oscillator clock is used as source of SPI6 clock*/ + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_CSI: + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CSI oscillator clock is used as source of SPI6 clock */ + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_HSE: + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSE, oscillator is used as source of SPI6 clock */ + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_SPI6CLKSOURCE_PIN) + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PIN: + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* 2S_CKIN is used as source of SPI6 clock */ + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SPI6 clock*/ + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DSI) + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- DSI configuration -------------------------------*/ + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->DsiClockSelection) + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ + ARM GAS /tmp/ccSY6g1k.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* DSI clock source configuration done later after clock selection check */ + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_DSICLKSOURCE_PHY: + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* PHY is used as clock source for DSI*/ + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* DSI clock source configuration done later after clock selection check */ + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of DSI clock*/ + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*DSI*/ + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(FDCAN1) || defined(FDCAN2) + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- FDCAN configuration -------------------------------*/ + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->FdcanClockSelection) + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable FDCAN Clock output generated form System PLL . */ + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* FDCAN clock source configuration done later after clock selection check */ + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* FDCAN clock source configuration done later after clock selection check */ + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FDCANCLKSOURCE_HSE: + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSE is used as clock source for FDCAN*/ + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* FDCAN clock source configuration done later after clock selection check */ + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of FDCAN clock*/ + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*FDCAN1 || FDCAN2*/ + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- FMC configuration -------------------------------*/ + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->FmcClockSelection) + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable FMC Clock output generated form System PLL . */ + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* FMC clock source configuration done later after clock selection check */ + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* FMC clock source configuration done later after clock selection check */ + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FMCCLKSOURCE_CLKP: + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* FMC clock source configuration done later after clock selection check */ + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_FMCCLKSOURCE_HCLK: + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of FMC clock*/ + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + ARM GAS /tmp/ccSY6g1k.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- RTC configuration -------------------------------*/ + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* check for RTC Parameters used to output RTCCLK */ + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP); + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** while((PWR->CR1 & PWR_CR1_DBP) == 0U) + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_TIMEOUT; + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified */ + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */ + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC->BDCR = tmpreg; + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait fo + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_TIMEOUT; + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + ARM GAS /tmp/ccSY6g1k.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*-------------------------- USART1/6 configuration --------------------------*/ + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Usart16ClockSelection) + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART16CLKSOURCE_HSI: + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI oscillator clock is used as source of USART1/6 clock */ + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART16CLKSOURCE_CSI: + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CSI oscillator clock is used as source of USART1/6 clock */ + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART16CLKSOURCE_LSE: + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LSE, oscillator is used as source of USART1/6 clock */ + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + ARM GAS /tmp/ccSY6g1k.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of USART1/6 clock */ +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART2345 +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Usart234578ClockSelection) +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART234578CLKSOURCE_HSI: +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART234578CLKSOURCE_CSI: +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USART234578CLKSOURCE_LSE: +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of USART2/3/4/5/7/8 clock */ +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*-------------------------- LPUART1 Configuration -------------------------*/ +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Lpuart1ClockSelection) +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPUART1CLKSOURCE_HSI: +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI oscillator clock is used as source of LPUART1 clock */ +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPUART1CLKSOURCE_CSI: +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CSI oscillator clock is used as source of LPUART1 clock */ +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPUART1CLKSOURCE_LSE: +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LSE, oscillator is used as source of LPUART1 clock */ +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of LPUART1 clock */ +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- LPTIM1 configuration -------------------------------*/ + ARM GAS /tmp/ccSY6g1k.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Lptim1ClockSelection) +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM1 clock source configuration done later after clock selection check */ +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM1 clock source configuration done later after clock selection check */ +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM1 clock source configuration done later after clock selection check */ +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM1CLKSOURCE_LSE: +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External low speed OSC clock is used as source of LPTIM1 clock*/ +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM1 clock source configuration done later after clock selection check */ +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM1CLKSOURCE_LSI: +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM1 clock source configuration done later after clock selection check */ +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM1CLKSOURCE_CLKP: +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM1 clock source configuration done later after clock selection check */ +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of LPTIM1 clock*/ +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- LPTIM2 configuration -------------------------------*/ +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Lptim2ClockSelection) +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM2 clock source configuration done later after clock selection check */ +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM2 clock source configuration done later after clock selection check */ +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM2 clock source configuration done later after clock selection check */ +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM2CLKSOURCE_LSE: +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External low speed OSC clock is used as source of LPTIM2 clock*/ +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM2 clock source configuration done later after clock selection check */ +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM2CLKSOURCE_LSI: +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM2 clock source configuration done later after clock selection check */ +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM2CLKSOURCE_CLKP: +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM2 clock source configuration done later after clock selection check */ +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of LPTIM2 clock*/ +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- LPTIM345 configuration -------------------------------*/ +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->Lptim345ClockSelection) +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 * +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM3/4/5 clock source configuration done later after clock selection check */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM3/4/5 clock source configuration done later after clock selection check */ +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM3/4/5 clock source configuration done later after clock selection check */ +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM345CLKSOURCE_LSE: +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM3/4/5 clock source configuration done later after clock selection check */ +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM345CLKSOURCE_LSI: +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM3/4/5 clock source configuration done later after clock selection check */ +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_LPTIM345CLKSOURCE_CLKP: +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPTIM3/4/5 clock source configuration done later after clock selection check */ +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of LPTIM3/4/5 clock */ +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(I2C5) +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 ) +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = HAL_ERROR; +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 ) +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = HAL_ERROR; +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* I2C5 */ +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ I2C4 Configuration ------------------------*/ +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = HAL_ERROR; +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*---------------------------- ADC configuration -------------------------------*/ +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->AdcClockSelection) +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* ADC clock source configuration done later after clock selection check */ +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + ARM GAS /tmp/ccSY6g1k.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* ADC clock source configuration done later after clock selection check */ +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_ADCCLKSOURCE_CLKP: +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* ADC clock source configuration done later after clock selection check */ +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of ADC clock*/ +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ USB Configuration -------------------------*/ +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->UsbClockSelection) +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable USB Clock output generated form System USB . */ +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USB clock source configuration done later after clock selection check */ +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USB clock source configuration done later after clock selection check */ +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_USBCLKSOURCE_HSI48: +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI48 oscillator is used as source of USB clock */ +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USB clock source configuration done later after clock selection check */ +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) + ARM GAS /tmp/ccSY6g1k.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of USB clock*/ +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------------- SDMMC Configuration ------------------------------------* +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->SdmmcClockSelection) +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable SDMMC Clock output generated form System PLL . */ +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SDMMC clock source configuration done later after clock selection check */ +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SDMMC clock source configuration done later after clock selection check */ +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of SDMMC clock*/ +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(LTDC) +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*-------------------------------------- LTDC Configuration -----------------------------------*/ +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status=HAL_ERROR; +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* LTDC */ +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ RNG Configuration -------------------------*/ +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch(PeriphClkInit->RngClockSelection) +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable RNG Clock output generated form System RNG . */ +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RNG clock source configuration done later after clock selection check */ +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RNG clock source configuration done later after clock selection check */ +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RNG clock source configuration done later after clock selection check */ +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_RNGCLKSOURCE_HSI48: +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* HSI48 oscillator is used as source of RNG clock */ +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RNG clock source configuration done later after clock selection check */ +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ret = HAL_ERROR; +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ret == HAL_OK) +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the source of RNG clock*/ +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* set overall return value */ +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** status = ret; +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ SWPMI1 Configuration ------------------------*/ +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure the SWPMI1 interface clock source */ + ARM GAS /tmp/ccSY6g1k.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(HRTIM1) +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ HRTIM1 clock Configuration ----------------*/ +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure the HRTIM1 clock source */ +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*HRTIM1*/ +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ DFSDM1 Configuration ------------------------*/ +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure the DFSDM1 interface clock source */ +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DFSDM2_BASE) +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------ DFSDM2 Configuration ------------------------*/ +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure the DFSDM2 interface clock source */ +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DFSDM2 */ +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------------ TIM configuration --------------------------------------*/ +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure Timer Prescaler */ +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /*------------------------------------ CKPER configuration -------------------------------------- +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure the CKPER clock source */ +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (status == HAL_OK) +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_OK; +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_ERROR; +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * returns the configuration information for the Extended Peripherals clocks : +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SA +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * SAI4A*, SAI4B*, SPI6, RTC, TIM). +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * (*) : Available on some STM32H7 lines only. +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PE +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PE +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CKPER; +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(I2C5) +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2ASEL) +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* RCC_CDCCIP1R_SAI2ASEL */ +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2BSEL) +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* RCC_CDCCIP1R_SAI2BSEL */ +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI3 */ +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI4) +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI4 */ +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DFSDM2_BASE) +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DFSDM2 */ +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(QUADSPI) +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(OCTOSPI1) || defined(OCTOSPI2) +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* OCTOSPI1 || OCTOSPI2 */ +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(HRTIM1) +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; + ARM GAS /tmp/ccSY6g1k.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(LTDC) +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* LTDC */ +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DSI) +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DSI */ +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the PLL3 Clock configuration -----------------------------------------------*/ +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIV +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3 +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFG +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the PLL2 Clock configuration -----------------------------------------------*/ +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIV +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2 +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFG +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USART1 configuration --------------------------------------------*/ +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE(); +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source --------------------------------------------*/ +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(I2C5) +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the I2C1/2/3 clock source -------------------------------------------*/ +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM1 clock source ---------------------------------------------*/ +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM2 clock source ---------------------------------------------*/ +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI1 clock source -----------------------------------------------*/ +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI2/3 clock source ---------------------------------------------*/ +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI3*/ +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2ASEL_0) +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI2A clock source ---------------------------------------------*/ +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI2A*/ +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2BSEL_0) +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI2B clock source ---------------------------------------------*/ + ARM GAS /tmp/ccSY6g1k.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI2B*/ +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI4) +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI4A clock source ----------------------------------------------*/ +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI4B clock source ----------------------------------------------*/ +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI4*/ +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the RTC clock source ------------------------------------------------*/ +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USB clock source ------------------------------------------------*/ +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SDMMC clock source ----------------------------------------------*/ +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the RNG clock source ------------------------------------------------*/ +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(HRTIM1) +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the HRTIM1 clock source ---------------------------------------------*/ +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the ADC clock source ------------------------------------------------*/ +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SWPMI1 clock source ---------------------------------------------*/ +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the DFSDM1 clock source ---------------------------------------------*/ +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DFSDM2_BASE) +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the DFSDM2 clock source ---------------------------------------------*/ +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DFSDM2 */ +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPDIFRX clock source --------------------------------------------*/ +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI1/2/3 clock source -------------------------------------------*/ +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE(); +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI4/5 clock source ---------------------------------------------*/ +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI6 clock source -----------------------------------------------*/ +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FDCAN clock source ----------------------------------------------*/ +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the CEC clock source ------------------------------------------------*/ +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FMC clock source ------------------------------------------------*/ +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(QUADSPI) +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the QSPI clock source -----------------------------------------------*/ +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(OCTOSPI1) || defined(OCTOSPI2) +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the OSPI clock source -----------------------------------------------*/ +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* OCTOSPI1 || OCTOSPI2 */ +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DSI) +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the DSI clock source ------------------------------------------------*/ +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*DSI*/ + ARM GAS /tmp/ccSY6g1k.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the CKPER clock source ----------------------------------------------*/ +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the TIM Prescaler configuration -------------------------------------*/ +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Return the peripheral clock frequency for a given peripheral(SAI..) +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Return 0 if peripheral clock identifier not managed by this API +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param PeriphClk: Peripheral clock identifier +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval Frequency in KHz +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * (*) : Available on some STM32H7 lines only. +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_ClocksTypeDef pll1_clocks; +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_ClocksTypeDef pll2_clocks; +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_ClocksTypeDef pll3_clocks; +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* This variable is used to store the SAI clock frequency (value in Hz) */ +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t frequency; +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* This variable is used to store the SAI and CKP clock source */ +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t saiclocksource; +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t ckpclocksource; +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t srcclk; +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (PeriphClk == RCC_PERIPHCLK_SAI1) +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** saiclocksource= __HAL_RCC_GET_SAI1_SOURCE(); +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (saiclocksource) +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + ARM GAS /tmp/ccSY6g1k.s page 33 + + +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; + ARM GAS /tmp/ccSY6g1k.s page 34 + + +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SAI23) +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** saiclocksource= __HAL_RCC_GET_SAI23_SOURCE(); +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (saiclocksource) +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case 0: /* PLL1 is the clock source for SAI2/3 */ +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else + ARM GAS /tmp/ccSY6g1k.s page 35 + + +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI3 */ +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2ASEL) +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SAI2A) +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE(); +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (saiclocksource) +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case 0: /* PLL1 is the clock source for SAI2A */ +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 36 + + +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_CDCCIP1R_SAI2BSEL_0) +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SAI2B) +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE(); +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (saiclocksource) +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case 0: /* PLL1 is the clock source for SAI2B */ +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 37 + + +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ +2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif + ARM GAS /tmp/ccSY6g1k.s page 38 + + +2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI4) +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SAI4A) +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE(); +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (saiclocksource) +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case 0: /* PLL1 is the clock source for SAI4A */ +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */ +2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */ +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/ +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 39 + + +2141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock sourc +2146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SAI4B) +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE(); +2163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (saiclocksource) +2165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case 0: /* PLL1 is the clock source for SAI4B */ +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */ +2173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +2176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */ +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/ +2187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +2192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + ARM GAS /tmp/ccSY6g1k.s page 40 + + +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +2200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +2212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock sourc +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +2221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI4*/ +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SPI123) +2233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get SPI1/2/3 clock source */ +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** srcclk= __HAL_RCC_GET_SPI123_SOURCE(); +2236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (srcclk) +2238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */ +2240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +2242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */ +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */ +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + ARM GAS /tmp/ccSY6g1k.s page 41 + + +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */ +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +2265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +2268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +2271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +2274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +2280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_ADC) +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get ADC clock source */ +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** srcclk= __HAL_RCC_GET_ADC_SOURCE(); +2307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (srcclk) +2309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_ADCCLKSOURCE_PLL2: +2311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 42 + + +2312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_ADCCLKSOURCE_PLL3: +2317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_R_Frequency; +2320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_ADCCLKSOURCE_CLKP: +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(ckpclocksource== RCC_CLKPSOURCE_HSI) +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSI */ +2331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(ckpclocksource== RCC_CLKPSOURCE_CSI) +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is CSI */ +2337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +2338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (ckpclocksource== RCC_CLKPSOURCE_HSE) +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER Source is HSE */ +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +2344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* In Case the CKPER is disabled*/ +2349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SDMMC) +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get SDMMC clock source */ +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** srcclk= __HAL_RCC_GET_SDMMC_SOURCE(); +2366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (srcclk) +2368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 43 + + +2369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); +2372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_R_Frequency; +2379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if (PeriphClk == RCC_PERIPHCLK_SPI6) +2390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get SPI6 clock source */ +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** srcclk= __HAL_RCC_GET_SPI6_SOURCE(); +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (srcclk) +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HAL_RCCEx_GetD3PCLK1Freq(); +2399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ +2402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_Q_Frequency; +2405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ +2408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +2410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_Q_Frequency; +2411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +2416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = CSI_VALUE; +2421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ +2424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; + ARM GAS /tmp/ccSY6g1k.s page 44 + + +2426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_SPI6CLKSOURCE_PIN) +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +2432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* RCC_SPI6CLKSOURCE_PIN */ +2435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default : +2436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = 0; +2445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return frequency; +2448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Returns the D1PCLK1 frequency +2453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Each time D1PCLK1 changes, this function must be called to update the +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorr +2455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval D1PCLK1 frequency +2456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_D1CFGR_D1PPRE) +2460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR +2462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCF +2465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Returns the D3PCLK1 frequency +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Each time D3PCLK1 changes, this function must be called to update the +2471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorr +2472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval D3PCLK1 frequency +2473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) +2475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_D3CFGR_D3PPRE) +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR +2479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ +2481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRD +2482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif + ARM GAS /tmp/ccSY6g1k.s page 45 + + +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequenc +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The PLL2 clock frequencies computed by this function is not the real +2487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * frequency in the chip. It is calculated based on the predefined +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * constant and the selected clock source: +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/div +2490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This function can be used by the user application to compute the +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * baud-rate for the communication peripherals or configure other parameters. +2492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Each time PLL2CLK changes, this function must be called to update the +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * right PLL2CLK value. Otherwise, any configuration based on this function will be incorr +2495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param PLL2_Clocks structure. +2496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll2m, pll2fracen, hsivalue; +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** float_t fracn2, pll2vco; +2502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N +2504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2xCLK = PLL2_VCO / PLL2x +2505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); +2510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (pll2m != 0U) +2512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (pllsource) +2514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +2517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ +2522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ +2526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PL +2531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PL +2535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PL +2539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 46 + + +2540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR +2544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_P_Frequency = 0U; +2548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = 0U; +2549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = 0U; +2550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequenc +2555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The PLL3 clock frequencies computed by this function is not the real +2556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * frequency in the chip. It is calculated based on the predefined +2557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * constant and the selected clock source: +2558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/div +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This function can be used by the user application to compute the +2560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * baud-rate for the communication peripherals or configure other parameters. +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Each time PLL3CLK changes, this function must be called to update the +2563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * right PLL3CLK value. Otherwise, any configuration based on this function will be incorr +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param PLL3_Clocks structure. +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll3m, pll3fracen, hsivalue; +2570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** float_t fracn3, pll3vco; +2571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3xCLK = PLL3_VCO / PLLxR +2574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (pll3m != 0U) +2581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (pllsource) +2583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_P +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_ +2594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + ARM GAS /tmp/ccSY6g1k.s page 47 + + +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PL +2598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PL +2602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PL +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_P_Frequency = 0U; +2615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = 0U; +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = 0U; +2617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequenc +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The PLL1 clock frequencies computed by this function is not the real +2624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * frequency in the chip. It is calculated based on the predefined +2625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * constant and the selected clock source: +2626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/div +2627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This function can be used by the user application to compute the +2628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * baud-rate for the communication peripherals or configure other parameters. +2629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Each time PLL1CLK changes, this function must be called to update the +2631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * right PLL1CLK value. Otherwise, any configuration based on this function will be incorr +2632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param PLL1_Clocks structure. +2633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) +2636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll1m, pll1fracen, hsivalue; +2638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** float_t fracn1, pll1vco; +2639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); +2641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4); +2642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); +2644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (pll1m != 0U) +2646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** switch (pllsource) +2648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +2651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 48 + + +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ +2660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL +2668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** default: +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL +2672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; +2673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR +2678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_P_Frequency = 0U; +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = 0U; +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = 0U; +2684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Returns the main System frequency +2690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Each time System clock changes, this function must be called to update the +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * right core clock value. Otherwise, any configuration based on this function will be inc +2692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency +2693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * and updated within this function +2694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval HCLK frequency +2695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetD1SysClockFreq(void) +2697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t common_system_clock; +2699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_D1CFGR_D1CPRE) +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1 +2702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_ +2704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif +2705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Update the SystemD2Clock global variable */ +2707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_D1CFGR_HPRE) +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_ +2709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RC + ARM GAS /tmp/ccSY6g1k.s page 49 + + +2711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif +2712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) +2714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SystemCoreClock = SystemD2Clock; +2715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SystemCoreClock = common_system_clock; +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DUAL_CORE && CORE_CM4 */ +2718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return common_system_clock; +2720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @} +2723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions +2726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions +2727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ +2728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Enables the LSE Clock Security System. +2731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled +2732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC +2733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * clock with HAL_RCCEx_PeriphCLKConfig(). +2734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS(void) +2737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +2739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Disables the LSE Clock Security System. +2743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note LSE Clock Security System can only be disabled after a LSE failure detection. +2744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSECSS(void) +2747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Disable LSE CSS IT if any */ +2750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +2751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSECSS_IT(void) +2759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable LSE CSS */ +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +2762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable LSE CSS IT */ +2764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable IT on EXTI Line 18 */ +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + ARM GAS /tmp/ccSY6g1k.s page 50 + + +2768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +2769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +2771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DUAL_CORE && CORE_CM4 */ +2772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +2773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock +2777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param WakeUpClk: Wakeup clock +2778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +2779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection +2780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection +2781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This function shall not be called after the Clock Security System on HSE has been +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * enabled. +2783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +2786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); +2788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Configure the oscillator Kernel clock source for wakeup from Stop +2794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param WakeUpClk: Kernel Wakeup clock +2795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +2796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection +2797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection +2798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +2801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +2805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DUAL_CORE) +2808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Enable COREx boot independently of CMx_B option byte value +2810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param RCC_BootCx: Boot Core to be enabled +2811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +2812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_BOOT_C1: CM7 core selection +2813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_BOOT_C2: CM4 core selection +2814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This bit can be set by software but is cleared by hardware after a system reset or STAN +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx) +2819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_BOOT_CORE(RCC_BootCx)); +2821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->GCR, RCC_BootCx) ; +2822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*DUAL_CORE*/ + ARM GAS /tmp/ccSY6g1k.s page 51 + + +2825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DUAL_CORE) +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out +2829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param RCC_WWDGx: WWDGx to be configured +2830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +2831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_WWDG1: WWDG1 generates system reset +2832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_WWDG2: WWDG2 generates system reset +2833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This bit can be set by software but is cleared by hardware during a system reset +2834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +2838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); +2840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->GCR, RCC_WWDGx) ; +2841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else +2844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_GCR_WW1RSC) +2845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out +2847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param RCC_WWDGx: WWDGx to be configured +2848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +2849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg RCC_WWDG1: WWDG1 generates system reset +2850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note This bit can be set by software but is cleared by hardware during a system reset +2851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +2855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); +2857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->GCR, RCC_WWDGx) ; +2858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif +2860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*DUAL_CORE*/ +2861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @} +2864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions +2867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Extended Clock Recovery System Control functions +2868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +2869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** @verbatim +2870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** =============================================================================== +2871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** ##### Extended Clock Recovery System Control functions ##### +2872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** =============================================================================== +2873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** [..] +2874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as +2875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) In System clock config, HSI48 needs to be enabled +2877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) Enable CRS clock in IP MSP init which will use CRS functions +2879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) Call CRS functions as follows: +2881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (##) Prepare synchronization configuration necessary for HSI48 calibration + ARM GAS /tmp/ccSY6g1k.s page 52 + + +2882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) Default values can be set for frequency Error Measurement (reload and error lim +2883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** and also HSI48 oscillator smooth trimming. +2884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** directly reload value with target and synchronization frequencies values +2886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (##) Call function HAL_RCCEx_CRSConfig which +2887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) Resets CRS registers to their default values. +2888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) Configures CRS registers with synchronization configuration +2889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) Enables automatic calibration and frequency error counter feature +2890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the +2891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** periodic USB SOF will not be generated by the host. No SYNC signal will therefore be +2892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs +2894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** should be used as SYNC signal. +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (##) A polling function is provided to wait for complete synchronization +2897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) Call function HAL_RCCEx_CRSWaitSynchronization() +2898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) According to CRS status, user can decide to adjust again the calibration or con +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** application if synchronization is OK +2900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) User can retrieve information related to synchronization in calling function +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_CRSGetSynchronizationInfo() +2903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) Regarding synchronization status and synchronization information, user can try a new cali +2905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. +2906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** Note: When the SYNC event is detected during the down-counting phase (before reaching th +2907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** it means that the actual frequency is lower than the target (and so, that the TRIM value +2908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** incremented), while when it is detected during the up-counting phase it means that the a +2909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** is higher (and that the TRIM value should be decremented). +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interr +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** through CRS Handler (CRS_IRQn/CRS_IRQHandler) +2913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (++) Call function HAL_RCCEx_CRSConfig() +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (++) Enable CRS_IRQn (thanks to NVIC functions) +2915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) +2916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (++) Implement CRS status management in the following user callbacks called from +2917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_IRQHandler(): +2918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_SyncOkCallback() +2919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_SyncWarnCallback() +2920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (+++) HAL_RCCEx_CRS_ErrorCallback() +2922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGene +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick h +2925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** @endverbatim +2927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ +2928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Start automatic synchronization for polling mode +2932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param pInit Pointer on RCC_CRSInitTypeDef structure +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t value; +2938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 53 + + +2939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameters */ +2940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); +2941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); +2945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CONFIGURATION */ +2948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Before configuration, reset CRS registers to their default values*/ +2950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_FORCE_RESET(); +2951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET(); +2952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */ +2954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the SYNCSRC[1:0] bits according to Source value */ +2955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the SYNCSPOL bit according to Polarity value */ +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2)) +2957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Use Rev.Y value of USB2 */ +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity); +2960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +2962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** value = (pInit->Prescaler | pInit->Source | pInit->Polarity); +2964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the RELOAD[15:0] bits according to ReloadValue value */ +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** value |= pInit->ReloadValue; +2967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ +2968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value); +2970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Adjust HSI48 oscillator smooth trimming */ +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ +2973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); +2974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* START AUTOMATIC SYNCHRONIZATION*/ +2976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable Automatic trimming & Frequency error counter */ +2978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +2979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Generate the software synchronization event +2983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +2986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_SWSYNC); +2988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +2989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +2990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +2991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Return synchronization info +2992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure +2993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +2994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +2995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) + ARM GAS /tmp/ccSY6g1k.s page 54 + + +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +2997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameter */ +2998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(pSynchroInfo != (void *)NULL); +2999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the reload value */ +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +3002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get HSI48 oscillator smooth trimming */ +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Po +3005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Frequency error capture */ +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Po +3008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Frequency error direction */ +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +3011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Wait for CRS Synchronization status. +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param Timeout Duration of the time-out +3016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +3017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * frequency. +3018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +3019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval Combination of Synchronization status +3020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be a combination of the following values: +3021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TIMEOUT +3022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCOK +3023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCWARN +3024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCERR +3025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCMISS +3026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TRIMOVF +3027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +3029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t crsstatus = RCC_CRS_NONE; +3031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; +3032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get time-out */ +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait for CRS flag or time-out detection */ +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** do +3038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(Timeout != HAL_MAX_DELAY) +3040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crsstatus = RCC_CRS_TIMEOUT; +3044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS SYNCOK flag */ +3047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) +3048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CRS SYNC event OK */ +3050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCOK; +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS SYNC event OK bit */ + ARM GAS /tmp/ccSY6g1k.s page 55 + + +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); +3054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS SYNCWARN flag */ +3057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CRS SYNC warning */ +3060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCWARN; +3061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS SYNCWARN bit */ +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); +3064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS TRIM overflow flag */ +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) +3068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CRS SYNC Error */ +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_TRIMOVF; +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS Error bit */ +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); +3074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS Error flag */ +3077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) +3078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CRS SYNC Error */ +3080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCERR; +3081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS Error bit */ +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); +3084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS SYNC Missed flag */ +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) +3088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* CRS SYNC Missed */ +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crsstatus |= RCC_CRS_SYNCMISS; +3091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS SYNC Missed bit */ +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); +3094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS Expected SYNC flag */ +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) +3098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* frequency error counter reached a zero value */ +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); +3101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } while(RCC_CRS_NONE == crsstatus); +3103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return crsstatus; +3105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Handle the Clock Recovery System interrupt request. +3109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None + ARM GAS /tmp/ccSY6g1k.s page 56 + + +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_CRS_IRQHandler(void) +3112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE; +3114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get current IT flags and IT sources values */ +3115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t itflags = READ_REG(CRS->ISR); +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR); +3117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS SYNCOK flag */ +3119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) +3120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS SYNC event OK flag */ +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +3123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* user callback */ +3125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_SyncOkCallback(); +3126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS SYNCWARN flag */ +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) +3129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS SYNCWARN flag */ +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +3132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* user callback */ +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_SyncWarnCallback(); +3135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS Expected SYNC flag */ +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) +3138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* frequency error counter reached a zero value */ +3140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +3141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* user callback */ +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_ExpectedSyncCallback(); +3144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check CRS Error flags */ +3146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +3147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) +3149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) +3151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crserror |= RCC_CRS_SYNCERR; +3153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) +3155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crserror |= RCC_CRS_SYNCMISS; +3157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) +3159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** crserror |= RCC_CRS_TRIMOVF; +3161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear CRS Error flags */ +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +3165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* user error callback */ + ARM GAS /tmp/ccSY6g1k.s page 57 + + +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_CRS_ErrorCallback(crserror); +3168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. +3174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval none +3175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncOkCallback(void) +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +3179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file +3180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. +3185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval none +3186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +3188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +3190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file +3191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval none +3197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +3199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +3201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file +3202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief RCCEx Clock Recovery System Error interrupt callback. +3207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param Error Combination of Error status. +3208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * This parameter can be a combination of the following values: +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCERR +3210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_SYNCMISS +3211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @arg @ref RCC_CRS_TRIMOVF +3212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval none +3213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +3215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Prevent unused argument(s) compilation warning */ +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** UNUSED(Error); +3218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +3220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file +3221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 58 + + +3224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @} +3227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @} +3231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_functions RCCEx Private Functions +3234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @{ +3235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it +3238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that +3239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * contains the configuration parameters as well as VCI, VCO clock ranges. +3240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param Divider divider parameter to be updated +3241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note PLL2 is temporary disabled to apply new parameters +3242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +3243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval HAL status +3244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 28 .loc 1 3246 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 +3247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 32 .loc 1 3248 3 view .LVU1 +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 33 .loc 1 3249 3 view .LVU2 +3250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); + 34 .loc 1 3250 3 view .LVU3 +3251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); + 35 .loc 1 3251 3 view .LVU4 +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); + 36 .loc 1 3252 3 view .LVU5 +3253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); + 37 .loc 1 3253 3 view .LVU6 +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q)); + 38 .loc 1 3254 3 view .LVU7 +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); + 39 .loc 1 3255 3 view .LVU8 +3256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); + 40 .loc 1 3256 3 view .LVU9 +3257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); + 41 .loc 1 3257 3 view .LVU10 +3258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check that PLL2 OSC clock source is already set */ +3260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + 42 .loc 1 3260 3 view .LVU11 + 43 .loc 1 3260 6 is_stmt 0 view .LVU12 + 44 0000 404B ldr r3, .L20 + 45 0002 9B6A ldr r3, [r3, #40] + 46 0004 03F00303 and r3, r3, #3 + 47 .loc 1 3260 5 view .LVU13 + ARM GAS /tmp/ccSY6g1k.s page 59 + + + 48 0008 032B cmp r3, #3 + 49 000a 79D0 beq .L10 +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 50 .loc 1 3246 1 view .LVU14 + 51 000c 70B5 push {r4, r5, r6, lr} + 52 .LCFI0: + 53 .cfi_def_cfa_offset 16 + 54 .cfi_offset 4, -16 + 55 .cfi_offset 5, -12 + 56 .cfi_offset 6, -8 + 57 .cfi_offset 14, -4 + 58 000e 0546 mov r5, r0 + 59 0010 0E46 mov r6, r1 +3261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_ERROR; +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +3267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Disable PLL2. */ +3269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2_DISABLE(); + 60 .loc 1 3269 5 is_stmt 1 view .LVU15 + 61 0012 3C4A ldr r2, .L20 + 62 0014 1368 ldr r3, [r2] + 63 0016 23F08063 bic r3, r3, #67108864 + 64 001a 1360 str r3, [r2] +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +3272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 65 .loc 1 3272 5 view .LVU16 + 66 .loc 1 3272 17 is_stmt 0 view .LVU17 + 67 001c FFF7FEFF bl HAL_GetTick + 68 .LVL1: + 69 .loc 1 3272 17 view .LVU18 + 70 0020 0446 mov r4, r0 + 71 .LVL2: +3273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait till PLL is disabled */ +3275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + 72 .loc 1 3275 5 is_stmt 1 view .LVU19 + 73 .L3: + 74 .loc 1 3275 10 view .LVU20 + 75 .loc 1 3275 11 is_stmt 0 view .LVU21 + 76 0022 384B ldr r3, .L20 + 77 0024 1B68 ldr r3, [r3] + 78 .loc 1 3275 10 view .LVU22 + 79 0026 13F0006F tst r3, #134217728 + 80 002a 06D0 beq .L17 +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) + 81 .loc 1 3277 7 is_stmt 1 view .LVU23 + 82 .loc 1 3277 12 is_stmt 0 view .LVU24 + 83 002c FFF7FEFF bl HAL_GetTick + 84 .LVL3: + 85 .loc 1 3277 26 view .LVU25 + 86 0030 031B subs r3, r0, r4 + ARM GAS /tmp/ccSY6g1k.s page 60 + + + 87 .loc 1 3277 9 view .LVU26 + 88 0032 022B cmp r3, #2 + 89 0034 F5D9 bls .L3 +3278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 90 .loc 1 3279 16 view .LVU27 + 91 0036 0320 movs r0, #3 + 92 .L2: +3280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure PLL2 multiplication and division factors. */ +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, +3285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2N, +3286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2P, +3287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2Q, +3288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2R); +3289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Select PLL2 input reference frequency range: VCI */ +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; +3292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Select PLL2 output frequency range : VCO */ +3294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; +3295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Disable PLL2FRACN . */ +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2FRACN_DISABLE(); +3298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ +3300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); +3301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable PLL2FRACN . */ +3303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2FRACN_ENABLE(); +3304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable the PLL2 clock output */ +3306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(Divider == DIVIDER_P_UPDATE) +3307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); +3309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(Divider == DIVIDER_Q_UPDATE) +3311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); +3313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +3315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); +3317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable PLL2. */ +3320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL2_ENABLE(); +3321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +3323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +3324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait till PLL2 is ready */ +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) +3327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) + ARM GAS /tmp/ccSY6g1k.s page 61 + + +3329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +3331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return status; +3338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 93 .loc 1 3338 1 view .LVU28 + 94 0038 70BD pop {r4, r5, r6, pc} + 95 .LVL4: + 96 .L17: +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2N, + 97 .loc 1 3284 5 is_stmt 1 view .LVU29 +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2N, + 98 .loc 1 3284 5 view .LVU30 + 99 003a 324B ldr r3, .L20 + 100 003c 9A6A ldr r2, [r3, #40] + 101 003e 22F47C32 bic r2, r2, #258048 + 102 0042 2968 ldr r1, [r5] + 103 0044 42EA0132 orr r2, r2, r1, lsl #12 + 104 0048 9A62 str r2, [r3, #40] +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2N, + 105 .loc 1 3284 5 view .LVU31 + 106 004a 6A68 ldr r2, [r5, #4] + 107 004c 013A subs r2, r2, #1 + 108 004e C2F30802 ubfx r2, r2, #0, #9 + 109 0052 A968 ldr r1, [r5, #8] + 110 0054 0139 subs r1, r1, #1 + 111 0056 4902 lsls r1, r1, #9 + 112 0058 89B2 uxth r1, r1 + 113 005a 0A43 orrs r2, r2, r1 + 114 005c E968 ldr r1, [r5, #12] + 115 005e 0139 subs r1, r1, #1 + 116 0060 0904 lsls r1, r1, #16 + 117 0062 01F4FE01 and r1, r1, #8323072 + 118 0066 0A43 orrs r2, r2, r1 + 119 0068 2969 ldr r1, [r5, #16] + 120 006a 0139 subs r1, r1, #1 + 121 006c 0906 lsls r1, r1, #24 + 122 006e 01F0FE41 and r1, r1, #2130706432 + 123 0072 0A43 orrs r2, r2, r1 + 124 0074 9A63 str r2, [r3, #56] +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2->PLL2N, + 125 .loc 1 3284 5 view .LVU32 +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 126 .loc 1 3291 5 view .LVU33 + 127 0076 DA6A ldr r2, [r3, #44] + 128 0078 22F0C002 bic r2, r2, #192 + 129 007c 6969 ldr r1, [r5, #20] + 130 007e 0A43 orrs r2, r2, r1 + 131 0080 DA62 str r2, [r3, #44] +3294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 132 .loc 1 3294 5 view .LVU34 + 133 0082 DA6A ldr r2, [r3, #44] + ARM GAS /tmp/ccSY6g1k.s page 62 + + + 134 0084 22F02002 bic r2, r2, #32 + 135 0088 A969 ldr r1, [r5, #24] + 136 008a 0A43 orrs r2, r2, r1 + 137 008c DA62 str r2, [r3, #44] +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 138 .loc 1 3297 5 view .LVU35 + 139 008e DA6A ldr r2, [r3, #44] + 140 0090 22F01002 bic r2, r2, #16 + 141 0094 DA62 str r2, [r3, #44] +3300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 142 .loc 1 3300 5 view .LVU36 + 143 0096 D96B ldr r1, [r3, #60] + 144 0098 1B4A ldr r2, .L20+4 + 145 009a 0A40 ands r2, r2, r1 + 146 009c E969 ldr r1, [r5, #28] + 147 009e 42EAC102 orr r2, r2, r1, lsl #3 + 148 00a2 DA63 str r2, [r3, #60] +3303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 149 .loc 1 3303 5 view .LVU37 + 150 00a4 DA6A ldr r2, [r3, #44] + 151 00a6 42F01002 orr r2, r2, #16 + 152 00aa DA62 str r2, [r3, #44] +3306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 153 .loc 1 3306 5 view .LVU38 +3306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 154 .loc 1 3306 7 is_stmt 0 view .LVU39 + 155 00ac C6B9 cbnz r6, .L5 +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 156 .loc 1 3308 7 is_stmt 1 view .LVU40 + 157 00ae 1A46 mov r2, r3 + 158 00b0 DB6A ldr r3, [r3, #44] + 159 00b2 43F40023 orr r3, r3, #524288 + 160 00b6 D362 str r3, [r2, #44] + 161 .L6: +3320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 162 .loc 1 3320 5 view .LVU41 + 163 00b8 124A ldr r2, .L20 + 164 00ba 1368 ldr r3, [r2] + 165 00bc 43F08063 orr r3, r3, #67108864 + 166 00c0 1360 str r3, [r2] +3323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 167 .loc 1 3323 5 view .LVU42 +3323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 168 .loc 1 3323 17 is_stmt 0 view .LVU43 + 169 00c2 FFF7FEFF bl HAL_GetTick + 170 .LVL5: + 171 00c6 0446 mov r4, r0 + 172 .LVL6: +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 173 .loc 1 3326 5 is_stmt 1 view .LVU44 + 174 .L8: +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 175 .loc 1 3326 10 view .LVU45 +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 176 .loc 1 3326 11 is_stmt 0 view .LVU46 + 177 00c8 0E4B ldr r3, .L20 + 178 00ca 1B68 ldr r3, [r3] + ARM GAS /tmp/ccSY6g1k.s page 63 + + +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 179 .loc 1 3326 10 view .LVU47 + 180 00cc 13F0006F tst r3, #134217728 + 181 00d0 14D1 bne .L18 +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 182 .loc 1 3328 7 is_stmt 1 view .LVU48 +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 183 .loc 1 3328 12 is_stmt 0 view .LVU49 + 184 00d2 FFF7FEFF bl HAL_GetTick + 185 .LVL7: +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 186 .loc 1 3328 26 view .LVU50 + 187 00d6 001B subs r0, r0, r4 +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 188 .loc 1 3328 9 view .LVU51 + 189 00d8 0228 cmp r0, #2 + 190 00da F5D9 bls .L8 +3330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 191 .loc 1 3330 16 view .LVU52 + 192 00dc 0320 movs r0, #3 + 193 00de ABE7 b .L2 + 194 .L5: +3310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 195 .loc 1 3310 10 is_stmt 1 view .LVU53 +3310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 196 .loc 1 3310 12 is_stmt 0 view .LVU54 + 197 00e0 012E cmp r6, #1 + 198 00e2 05D0 beq .L19 +3316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 199 .loc 1 3316 7 is_stmt 1 view .LVU55 + 200 00e4 074A ldr r2, .L20 + 201 00e6 D36A ldr r3, [r2, #44] + 202 00e8 43F40013 orr r3, r3, #2097152 + 203 00ec D362 str r3, [r2, #44] + 204 00ee E3E7 b .L6 + 205 .L19: +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 206 .loc 1 3312 7 view .LVU56 + 207 00f0 044A ldr r2, .L20 + 208 00f2 D36A ldr r3, [r2, #44] + 209 00f4 43F48013 orr r3, r3, #1048576 + 210 00f8 D362 str r3, [r2, #44] + 211 00fa DDE7 b .L6 + 212 .L18: +3337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 213 .loc 1 3337 10 is_stmt 0 view .LVU57 + 214 00fc 0020 movs r0, #0 + 215 00fe 9BE7 b .L2 + 216 .LVL8: + 217 .L10: + 218 .LCFI1: + 219 .cfi_def_cfa_offset 0 + 220 .cfi_restore 4 + 221 .cfi_restore 5 + 222 .cfi_restore 6 + 223 .cfi_restore 14 +3262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 64 + + + 224 .loc 1 3262 12 view .LVU58 + 225 0100 0120 movs r0, #1 + 226 .LVL9: + 227 .loc 1 3338 1 view .LVU59 + 228 0102 7047 bx lr + 229 .L21: + 230 .align 2 + 231 .L20: + 232 0104 00440258 .word 1476543488 + 233 0108 0700FFFF .word -65529 + 234 .cfi_endproc + 235 .LFE165: + 237 .section .text.RCCEx_PLL3_Config,"ax",%progbits + 238 .align 1 + 239 .syntax unified + 240 .thumb + 241 .thumb_func + 242 .fpu fpv5-d16 + 244 RCCEx_PLL3_Config: + 245 .LVL10: + 246 .LFB166: +3339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it +3343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that +3344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * contains the configuration parameters as well as VCI, VCO clock ranges. +3345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @param Divider divider parameter to be updated +3346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @note PLL3 is temporary disabled to apply new parameters +3347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * +3348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval HAL status +3349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +3351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 247 .loc 1 3351 1 is_stmt 1 view -0 + 248 .cfi_startproc + 249 @ args = 0, pretend = 0, frame = 0 + 250 @ frame_needed = 0, uses_anonymous_args = 0 +3352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 251 .loc 1 3352 3 view .LVU61 +3353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 252 .loc 1 3353 3 view .LVU62 +3354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); + 253 .loc 1 3354 3 view .LVU63 +3355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N)); + 254 .loc 1 3355 3 view .LVU64 +3356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P)); + 255 .loc 1 3356 3 view .LVU65 +3357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R)); + 256 .loc 1 3357 3 view .LVU66 +3358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q)); + 257 .loc 1 3358 3 view .LVU67 +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); + 258 .loc 1 3359 3 view .LVU68 +3360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); + 259 .loc 1 3360 3 view .LVU69 +3361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); + ARM GAS /tmp/ccSY6g1k.s page 65 + + + 260 .loc 1 3361 3 view .LVU70 +3362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check that PLL3 OSC clock source is already set */ +3364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + 261 .loc 1 3364 3 view .LVU71 + 262 .loc 1 3364 6 is_stmt 0 view .LVU72 + 263 0000 404B ldr r3, .L41 + 264 0002 9B6A ldr r3, [r3, #40] + 265 0004 03F00303 and r3, r3, #3 + 266 .loc 1 3364 5 view .LVU73 + 267 0008 032B cmp r3, #3 + 268 000a 79D0 beq .L31 +3351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 269 .loc 1 3351 1 view .LVU74 + 270 000c 70B5 push {r4, r5, r6, lr} + 271 .LCFI2: + 272 .cfi_def_cfa_offset 16 + 273 .cfi_offset 4, -16 + 274 .cfi_offset 5, -12 + 275 .cfi_offset 6, -8 + 276 .cfi_offset 14, -4 + 277 000e 0546 mov r5, r0 + 278 0010 0E46 mov r6, r1 +3365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_ERROR; +3367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +3371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Disable PLL3. */ +3373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3_DISABLE(); + 279 .loc 1 3373 5 is_stmt 1 view .LVU75 + 280 0012 3C4A ldr r2, .L41 + 281 0014 1368 ldr r3, [r2] + 282 0016 23F08053 bic r3, r3, #268435456 + 283 001a 1360 str r3, [r2] +3374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +3376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 284 .loc 1 3376 5 view .LVU76 + 285 .loc 1 3376 17 is_stmt 0 view .LVU77 + 286 001c FFF7FEFF bl HAL_GetTick + 287 .LVL11: + 288 .loc 1 3376 17 view .LVU78 + 289 0020 0446 mov r4, r0 + 290 .LVL12: +3377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait till PLL3 is ready */ +3378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + 291 .loc 1 3378 5 is_stmt 1 view .LVU79 + 292 .L24: + 293 .loc 1 3378 10 view .LVU80 + 294 .loc 1 3378 11 is_stmt 0 view .LVU81 + 295 0022 384B ldr r3, .L41 + 296 0024 1B68 ldr r3, [r3] + 297 .loc 1 3378 10 view .LVU82 + 298 0026 13F0005F tst r3, #536870912 + ARM GAS /tmp/ccSY6g1k.s page 66 + + + 299 002a 06D0 beq .L38 +3379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) + 300 .loc 1 3380 7 is_stmt 1 view .LVU83 + 301 .loc 1 3380 12 is_stmt 0 view .LVU84 + 302 002c FFF7FEFF bl HAL_GetTick + 303 .LVL13: + 304 .loc 1 3380 26 view .LVU85 + 305 0030 031B subs r3, r0, r4 + 306 .loc 1 3380 9 view .LVU86 + 307 0032 022B cmp r3, #2 + 308 0034 F5D9 bls .L24 +3381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 309 .loc 1 3382 16 view .LVU87 + 310 0036 0320 movs r0, #3 + 311 .L23: +3383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configure the PLL3 multiplication and division factors. */ +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, +3388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3N, +3389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3P, +3390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3Q, +3391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3R); +3392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Select PLL3 input reference frequency range: VCI */ +3394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; +3395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Select PLL3 output frequency range : VCO */ +3397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; +3398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Disable PLL3FRACN . */ +3400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3FRACN_DISABLE(); +3401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ +3403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); +3404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable PLL3FRACN . */ +3406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3FRACN_ENABLE(); +3407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable the PLL3 clock output */ +3409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(Divider == DIVIDER_P_UPDATE) +3410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); +3412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else if(Divider == DIVIDER_Q_UPDATE) +3414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** else +3418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); +3420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable PLL3. */ + ARM GAS /tmp/ccSY6g1k.s page 67 + + +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_PLL3_ENABLE(); +3424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +3427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Wait till PLL3 is ready */ +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) +3430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) +3432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +3434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** return status; +3441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 312 .loc 1 3441 1 view .LVU88 + 313 0038 70BD pop {r4, r5, r6, pc} + 314 .LVL14: + 315 .L38: +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3N, + 316 .loc 1 3387 5 is_stmt 1 view .LVU89 +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3N, + 317 .loc 1 3387 5 view .LVU90 + 318 003a 324B ldr r3, .L41 + 319 003c 9A6A ldr r2, [r3, #40] + 320 003e 22F07C72 bic r2, r2, #66060288 + 321 0042 2968 ldr r1, [r5] + 322 0044 42EA0152 orr r2, r2, r1, lsl #20 + 323 0048 9A62 str r2, [r3, #40] +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3N, + 324 .loc 1 3387 5 view .LVU91 + 325 004a 6A68 ldr r2, [r5, #4] + 326 004c 013A subs r2, r2, #1 + 327 004e C2F30802 ubfx r2, r2, #0, #9 + 328 0052 A968 ldr r1, [r5, #8] + 329 0054 0139 subs r1, r1, #1 + 330 0056 4902 lsls r1, r1, #9 + 331 0058 89B2 uxth r1, r1 + 332 005a 0A43 orrs r2, r2, r1 + 333 005c E968 ldr r1, [r5, #12] + 334 005e 0139 subs r1, r1, #1 + 335 0060 0904 lsls r1, r1, #16 + 336 0062 01F4FE01 and r1, r1, #8323072 + 337 0066 0A43 orrs r2, r2, r1 + 338 0068 2969 ldr r1, [r5, #16] + 339 006a 0139 subs r1, r1, #1 + 340 006c 0906 lsls r1, r1, #24 + 341 006e 01F0FE41 and r1, r1, #2130706432 + 342 0072 0A43 orrs r2, r2, r1 + 343 0074 1A64 str r2, [r3, #64] +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3->PLL3N, + 344 .loc 1 3387 5 view .LVU92 +3394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 68 + + + 345 .loc 1 3394 5 view .LVU93 + 346 0076 DA6A ldr r2, [r3, #44] + 347 0078 22F44062 bic r2, r2, #3072 + 348 007c 6969 ldr r1, [r5, #20] + 349 007e 0A43 orrs r2, r2, r1 + 350 0080 DA62 str r2, [r3, #44] +3397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 351 .loc 1 3397 5 view .LVU94 + 352 0082 DA6A ldr r2, [r3, #44] + 353 0084 22F40072 bic r2, r2, #512 + 354 0088 A969 ldr r1, [r5, #24] + 355 008a 0A43 orrs r2, r2, r1 + 356 008c DA62 str r2, [r3, #44] +3400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 357 .loc 1 3400 5 view .LVU95 + 358 008e DA6A ldr r2, [r3, #44] + 359 0090 22F48072 bic r2, r2, #256 + 360 0094 DA62 str r2, [r3, #44] +3403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 361 .loc 1 3403 5 view .LVU96 + 362 0096 596C ldr r1, [r3, #68] + 363 0098 1B4A ldr r2, .L41+4 + 364 009a 0A40 ands r2, r2, r1 + 365 009c E969 ldr r1, [r5, #28] + 366 009e 42EAC102 orr r2, r2, r1, lsl #3 + 367 00a2 5A64 str r2, [r3, #68] +3406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 368 .loc 1 3406 5 view .LVU97 + 369 00a4 DA6A ldr r2, [r3, #44] + 370 00a6 42F48072 orr r2, r2, #256 + 371 00aa DA62 str r2, [r3, #44] +3409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 372 .loc 1 3409 5 view .LVU98 +3409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 373 .loc 1 3409 7 is_stmt 0 view .LVU99 + 374 00ac C6B9 cbnz r6, .L26 +3411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 375 .loc 1 3411 7 is_stmt 1 view .LVU100 + 376 00ae 1A46 mov r2, r3 + 377 00b0 DB6A ldr r3, [r3, #44] + 378 00b2 43F48003 orr r3, r3, #4194304 + 379 00b6 D362 str r3, [r2, #44] + 380 .L27: +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 381 .loc 1 3423 5 view .LVU101 + 382 00b8 124A ldr r2, .L41 + 383 00ba 1368 ldr r3, [r2] + 384 00bc 43F08053 orr r3, r3, #268435456 + 385 00c0 1360 str r3, [r2] +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 386 .loc 1 3426 5 view .LVU102 +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 387 .loc 1 3426 17 is_stmt 0 view .LVU103 + 388 00c2 FFF7FEFF bl HAL_GetTick + 389 .LVL15: + 390 00c6 0446 mov r4, r0 + 391 .LVL16: + ARM GAS /tmp/ccSY6g1k.s page 69 + + +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 392 .loc 1 3429 5 is_stmt 1 view .LVU104 + 393 .L29: +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 394 .loc 1 3429 10 view .LVU105 +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 395 .loc 1 3429 11 is_stmt 0 view .LVU106 + 396 00c8 0E4B ldr r3, .L41 + 397 00ca 1B68 ldr r3, [r3] +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 398 .loc 1 3429 10 view .LVU107 + 399 00cc 13F0005F tst r3, #536870912 + 400 00d0 14D1 bne .L39 +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 401 .loc 1 3431 7 is_stmt 1 view .LVU108 +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 402 .loc 1 3431 12 is_stmt 0 view .LVU109 + 403 00d2 FFF7FEFF bl HAL_GetTick + 404 .LVL17: +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 405 .loc 1 3431 26 view .LVU110 + 406 00d6 001B subs r0, r0, r4 +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 407 .loc 1 3431 9 view .LVU111 + 408 00d8 0228 cmp r0, #2 + 409 00da F5D9 bls .L29 +3433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 410 .loc 1 3433 16 view .LVU112 + 411 00dc 0320 movs r0, #3 + 412 00de ABE7 b .L23 + 413 .L26: +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 414 .loc 1 3413 10 is_stmt 1 view .LVU113 +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 415 .loc 1 3413 12 is_stmt 0 view .LVU114 + 416 00e0 012E cmp r6, #1 + 417 00e2 05D0 beq .L40 +3419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 418 .loc 1 3419 7 is_stmt 1 view .LVU115 + 419 00e4 074A ldr r2, .L41 + 420 00e6 D36A ldr r3, [r2, #44] + 421 00e8 43F08073 orr r3, r3, #16777216 + 422 00ec D362 str r3, [r2, #44] + 423 00ee E3E7 b .L27 + 424 .L40: +3415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 425 .loc 1 3415 7 view .LVU116 + 426 00f0 044A ldr r2, .L41 + 427 00f2 D36A ldr r3, [r2, #44] + 428 00f4 43F40003 orr r3, r3, #8388608 + 429 00f8 D362 str r3, [r2, #44] + 430 00fa DDE7 b .L27 + 431 .L39: +3440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 432 .loc 1 3440 10 is_stmt 0 view .LVU117 + 433 00fc 0020 movs r0, #0 + 434 00fe 9BE7 b .L23 + ARM GAS /tmp/ccSY6g1k.s page 70 + + + 435 .LVL18: + 436 .L31: + 437 .LCFI3: + 438 .cfi_def_cfa_offset 0 + 439 .cfi_restore 4 + 440 .cfi_restore 5 + 441 .cfi_restore 6 + 442 .cfi_restore 14 +3366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 443 .loc 1 3366 12 view .LVU118 + 444 0100 0120 movs r0, #1 + 445 .LVL19: + 446 .loc 1 3441 1 view .LVU119 + 447 0102 7047 bx lr + 448 .L42: + 449 .align 2 + 450 .L41: + 451 0104 00440258 .word 1476543488 + 452 0108 0700FFFF .word -65529 + 453 .cfi_endproc + 454 .LFE166: + 456 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits + 457 .align 1 + 458 .global HAL_RCCEx_PeriphCLKConfig + 459 .syntax unified + 460 .thumb + 461 .thumb_func + 462 .fpu fpv5-d16 + 464 HAL_RCCEx_PeriphCLKConfig: + 465 .LVL20: + 466 .LFB141: + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tmpreg; + 467 .loc 1 108 1 is_stmt 1 view -0 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 0 + 470 @ frame_needed = 0, uses_anonymous_args = 0 + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tmpreg; + 471 .loc 1 108 1 is_stmt 0 view .LVU121 + 472 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 473 .LCFI4: + 474 .cfi_def_cfa_offset 24 + 475 .cfi_offset 3, -24 + 476 .cfi_offset 4, -20 + 477 .cfi_offset 5, -16 + 478 .cfi_offset 6, -12 + 479 .cfi_offset 7, -8 + 480 .cfi_offset 14, -4 + 481 0002 0446 mov r4, r0 + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 482 .loc 1 109 3 is_stmt 1 view .LVU122 + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 483 .loc 1 110 3 view .LVU123 + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 484 .loc 1 111 3 view .LVU124 + 485 .LVL21: + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 486 .loc 1 112 3 view .LVU125 + ARM GAS /tmp/ccSY6g1k.s page 71 + + + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 487 .loc 1 116 3 view .LVU126 + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 488 .loc 1 116 21 is_stmt 0 view .LVU127 + 489 0004 0368 ldr r3, [r0] + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 490 .loc 1 116 5 view .LVU128 + 491 0006 13F0006F tst r3, #134217728 + 492 000a 30D0 beq .L170 + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 493 .loc 1 119 5 is_stmt 1 view .LVU129 + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 494 .loc 1 119 25 is_stmt 0 view .LVU130 + 495 000c 436E ldr r3, [r0, #100] + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 496 .loc 1 119 5 view .LVU131 + 497 000e B3F5001F cmp r3, #2097152 + 498 0012 26D0 beq .L45 + 499 0014 0ED8 bhi .L46 + 500 0016 EBB1 cbz r3, .L47 + 501 0018 B3F5801F cmp r3, #1048576 + 502 001c 07D1 bne .L208 + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 503 .loc 1 130 7 is_stmt 1 view .LVU132 + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 504 .loc 1 130 13 is_stmt 0 view .LVU133 + 505 001e 0221 movs r1, #2 + 506 0020 0430 adds r0, r0, #4 + 507 .LVL22: + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 508 .loc 1 130 13 view .LVU134 + 509 0022 FFF7FEFF bl RCCEx_PLL2_Config + 510 .LVL23: + 511 0026 0546 mov r5, r0 + 512 .LVL24: + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 513 .loc 1 133 7 is_stmt 1 view .LVU135 + 514 .L50: + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 515 .loc 1 151 5 view .LVU136 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 516 .loc 1 151 7 is_stmt 0 view .LVU137 + 517 0028 45B1 cbz r5, .L49 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 518 .loc 1 151 7 view .LVU138 + 519 002a 2E46 mov r6, r5 + 520 002c 21E0 b .L44 + 521 .LVL25: + 522 .L208: + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 523 .loc 1 119 5 view .LVU139 + 524 002e 0126 movs r6, #1 + 525 0030 3546 mov r5, r6 + 526 0032 1EE0 b .L44 + 527 .L46: + 528 0034 B3F5401F cmp r3, #3145728 + 529 0038 09D1 bne .L209 + ARM GAS /tmp/ccSY6g1k.s page 72 + + + 530 003a 0025 movs r5, #0 + 531 .LVL26: + 532 .L49: + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 533 .loc 1 154 7 is_stmt 1 view .LVU140 + 534 003c 954A ldr r2, .L235 + 535 003e 136D ldr r3, [r2, #80] + 536 0040 23F44013 bic r3, r3, #3145728 + 537 0044 616E ldr r1, [r4, #100] + 538 0046 0B43 orrs r3, r3, r1 + 539 0048 1365 str r3, [r2, #80] + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 540 .loc 1 112 21 is_stmt 0 view .LVU141 + 541 004a 0026 movs r6, #0 + 542 004c 11E0 b .L44 + 543 .LVL27: + 544 .L209: + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 545 .loc 1 119 5 view .LVU142 + 546 004e 0126 movs r6, #1 + 547 0050 3546 mov r5, r6 + 548 0052 0EE0 b .L44 + 549 .L47: + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 550 .loc 1 123 7 is_stmt 1 view .LVU143 + 551 0054 8F4A ldr r2, .L235 + 552 0056 D36A ldr r3, [r2, #44] + 553 0058 43F40033 orr r3, r3, #131072 + 554 005c D362 str r3, [r2, #44] + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 555 .loc 1 126 7 view .LVU144 + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 556 .loc 1 151 5 view .LVU145 + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 557 .loc 1 111 21 is_stmt 0 view .LVU146 + 558 005e 0025 movs r5, #0 + 559 0060 ECE7 b .L49 + 560 .L45: + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 561 .loc 1 136 7 is_stmt 1 view .LVU147 + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 562 .loc 1 136 13 is_stmt 0 view .LVU148 + 563 0062 0221 movs r1, #2 + 564 0064 2430 adds r0, r0, #36 + 565 .LVL28: + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 566 .loc 1 136 13 view .LVU149 + 567 0066 FFF7FEFF bl RCCEx_PLL3_Config + 568 .LVL29: + 569 006a 0546 mov r5, r0 + 570 .LVL30: + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 571 .loc 1 139 7 is_stmt 1 view .LVU150 + 572 006c DCE7 b .L50 + 573 .LVL31: + 574 .L170: + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 73 + + + 575 .loc 1 112 21 is_stmt 0 view .LVU151 + 576 006e 0026 movs r6, #0 + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 577 .loc 1 111 21 view .LVU152 + 578 0070 3546 mov r5, r6 + 579 .LVL32: + 580 .L44: + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 581 .loc 1 164 3 is_stmt 1 view .LVU153 + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 582 .loc 1 164 21 is_stmt 0 view .LVU154 + 583 0072 2368 ldr r3, [r4] + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 584 .loc 1 164 5 view .LVU155 + 585 0074 13F4807F tst r3, #256 + 586 0078 14D0 beq .L51 + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 587 .loc 1 166 5 is_stmt 1 view .LVU156 + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 588 .loc 1 166 25 is_stmt 0 view .LVU157 + 589 007a 636D ldr r3, [r4, #84] + 590 007c 042B cmp r3, #4 + 591 007e 30D8 bhi .L173 + 592 0080 DFE803F0 tbb [pc, r3] + 593 .L53: + 594 0084 03 .byte (.L56-.L53)/2 + 595 0085 22 .byte (.L55-.L53)/2 + 596 0086 28 .byte (.L54-.L53)/2 + 597 0087 08 .byte (.L52-.L53)/2 + 598 0088 08 .byte (.L52-.L53)/2 + 599 0089 00 .p2align 1 + 600 .L56: + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 601 .loc 1 170 7 is_stmt 1 view .LVU158 + 602 008a 824A ldr r2, .L235 + 603 008c D36A ldr r3, [r2, #44] + 604 008e 43F40033 orr r3, r3, #131072 + 605 0092 D362 str r3, [r2, #44] + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 606 .loc 1 173 7 view .LVU159 + 607 .L52: + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 608 .loc 1 203 5 view .LVU160 + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 609 .loc 1 203 7 is_stmt 0 view .LVU161 + 610 0094 45BB cbnz r5, .L174 + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 611 .loc 1 206 7 is_stmt 1 view .LVU162 + 612 0096 7F4A ldr r2, .L235 + 613 0098 136D ldr r3, [r2, #80] + 614 009a 23F00703 bic r3, r3, #7 + 615 009e 616D ldr r1, [r4, #84] + 616 00a0 0B43 orrs r3, r3, r1 + 617 00a2 1365 str r3, [r2, #80] + 618 .LVL33: + 619 .L51: + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 74 + + + 620 .loc 1 217 3 view .LVU163 + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 621 .loc 1 217 21 is_stmt 0 view .LVU164 + 622 00a4 2368 ldr r3, [r4] + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 623 .loc 1 217 5 view .LVU165 + 624 00a6 13F4007F tst r3, #512 + 625 00aa 2FD0 beq .L57 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 626 .loc 1 219 5 is_stmt 1 view .LVU166 + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 627 .loc 1 219 25 is_stmt 0 view .LVU167 + 628 00ac A36D ldr r3, [r4, #88] + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 629 .loc 1 219 5 view .LVU168 + 630 00ae 802B cmp r3, #128 + 631 00b0 49D0 beq .L58 + 632 00b2 1ED8 bhi .L59 + 633 00b4 002B cmp r3, #0 + 634 00b6 40D0 beq .L60 + 635 00b8 402B cmp r3, #64 + 636 00ba 17D1 bne .L210 + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 637 .loc 1 230 7 is_stmt 1 view .LVU169 + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 638 .loc 1 230 13 is_stmt 0 view .LVU170 + 639 00bc 0021 movs r1, #0 + 640 00be 201D adds r0, r4, #4 + 641 00c0 FFF7FEFF bl RCCEx_PLL2_Config + 642 .LVL34: + 643 00c4 0546 mov r5, r0 + 644 .LVL35: + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 645 .loc 1 233 7 is_stmt 1 view .LVU171 + 646 00c6 19E0 b .L62 + 647 .L55: + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 648 .loc 1 177 7 view .LVU172 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 649 .loc 1 177 13 is_stmt 0 view .LVU173 + 650 00c8 0021 movs r1, #0 + 651 00ca 201D adds r0, r4, #4 + 652 00cc FFF7FEFF bl RCCEx_PLL2_Config + 653 .LVL36: + 654 00d0 0546 mov r5, r0 + 655 .LVL37: + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 656 .loc 1 180 7 is_stmt 1 view .LVU174 + 657 00d2 DFE7 b .L52 + 658 .L54: + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 659 .loc 1 183 7 view .LVU175 + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 660 .loc 1 183 13 is_stmt 0 view .LVU176 + 661 00d4 0021 movs r1, #0 + 662 00d6 04F12400 add r0, r4, #36 + 663 00da FFF7FEFF bl RCCEx_PLL3_Config + ARM GAS /tmp/ccSY6g1k.s page 75 + + + 664 .LVL38: + 665 00de 0546 mov r5, r0 + 666 .LVL39: + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 667 .loc 1 186 7 is_stmt 1 view .LVU177 + 668 00e0 D8E7 b .L52 + 669 .L173: + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 670 .loc 1 166 25 is_stmt 0 view .LVU178 + 671 00e2 0126 movs r6, #1 + 672 .LVL40: + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 673 .loc 1 166 25 view .LVU179 + 674 00e4 3546 mov r5, r6 + 675 .LVL41: + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 676 .loc 1 166 25 view .LVU180 + 677 00e6 DDE7 b .L51 + 678 .LVL42: + 679 .L174: + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 680 .loc 1 166 25 view .LVU181 + 681 00e8 2E46 mov r6, r5 + 682 .LVL43: + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 683 .loc 1 166 25 view .LVU182 + 684 00ea DBE7 b .L51 + 685 .LVL44: + 686 .L210: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 687 .loc 1 219 5 view .LVU183 + 688 00ec 0126 movs r6, #1 + 689 .LVL45: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 690 .loc 1 219 5 view .LVU184 + 691 00ee 3546 mov r5, r6 + 692 .LVL46: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 693 .loc 1 219 5 view .LVU185 + 694 00f0 0CE0 b .L57 + 695 .LVL47: + 696 .L59: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 697 .loc 1 219 5 view .LVU186 + 698 00f2 C02B cmp r3, #192 + 699 00f4 02D0 beq .L62 + 700 00f6 B3F5807F cmp r3, #256 + 701 00fa 1BD1 bne .L211 + 702 .L62: + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 703 .loc 1 256 5 is_stmt 1 view .LVU187 + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 704 .loc 1 256 7 is_stmt 0 view .LVU188 + 705 00fc 55BB cbnz r5, .L175 + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 706 .loc 1 259 7 is_stmt 1 view .LVU189 + 707 00fe 654A ldr r2, .L235 + ARM GAS /tmp/ccSY6g1k.s page 76 + + + 708 0100 136D ldr r3, [r2, #80] + 709 0102 23F4E073 bic r3, r3, #448 + 710 0106 A16D ldr r1, [r4, #88] + 711 0108 0B43 orrs r3, r3, r1 + 712 010a 1365 str r3, [r2, #80] + 713 .LVL48: + 714 .L57: + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 715 .loc 1 391 3 view .LVU190 + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 716 .loc 1 391 21 is_stmt 0 view .LVU191 + 717 010c 2368 ldr r3, [r4] + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 718 .loc 1 391 5 view .LVU192 + 719 010e 13F4806F tst r3, #1024 + 720 0112 45D0 beq .L63 + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 721 .loc 1 393 5 is_stmt 1 view .LVU193 + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 722 .loc 1 393 25 is_stmt 0 view .LVU194 + 723 0114 D4F8A430 ldr r3, [r4, #164] + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 724 .loc 1 393 5 view .LVU195 + 725 0118 B3F5800F cmp r3, #4194304 + 726 011c 38D0 beq .L64 + 727 011e 1ED8 bhi .L65 + 728 0120 83B3 cbz r3, .L66 + 729 0122 B3F5001F cmp r3, #2097152 + 730 0126 17D1 bne .L212 + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 731 .loc 1 404 7 is_stmt 1 view .LVU196 + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 732 .loc 1 404 13 is_stmt 0 view .LVU197 + 733 0128 0021 movs r1, #0 + 734 012a 201D adds r0, r4, #4 + 735 012c FFF7FEFF bl RCCEx_PLL2_Config + 736 .LVL49: + 737 0130 0546 mov r5, r0 + 738 .LVL50: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 739 .loc 1 407 7 is_stmt 1 view .LVU198 + 740 0132 1AE0 b .L68 + 741 .L211: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 742 .loc 1 219 5 is_stmt 0 view .LVU199 + 743 0134 0126 movs r6, #1 + 744 .LVL51: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 745 .loc 1 219 5 view .LVU200 + 746 0136 3546 mov r5, r6 + 747 .LVL52: + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 748 .loc 1 219 5 view .LVU201 + 749 0138 E8E7 b .L57 + 750 .LVL53: + 751 .L60: + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 77 + + + 752 .loc 1 223 7 is_stmt 1 view .LVU202 + 753 013a 564A ldr r2, .L235 + 754 013c D36A ldr r3, [r2, #44] + 755 013e 43F40033 orr r3, r3, #131072 + 756 0142 D362 str r3, [r2, #44] + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 757 .loc 1 226 7 view .LVU203 + 758 0144 DAE7 b .L62 + 759 .L58: + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 760 .loc 1 236 7 view .LVU204 + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 761 .loc 1 236 13 is_stmt 0 view .LVU205 + 762 0146 0021 movs r1, #0 + 763 0148 04F12400 add r0, r4, #36 + 764 014c FFF7FEFF bl RCCEx_PLL3_Config + 765 .LVL54: + 766 0150 0546 mov r5, r0 + 767 .LVL55: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 768 .loc 1 239 7 is_stmt 1 view .LVU206 + 769 0152 D3E7 b .L62 + 770 .L175: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 771 .loc 1 239 7 is_stmt 0 view .LVU207 + 772 0154 2E46 mov r6, r5 + 773 .LVL56: + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 774 .loc 1 239 7 view .LVU208 + 775 0156 D9E7 b .L57 + 776 .LVL57: + 777 .L212: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 778 .loc 1 393 5 view .LVU209 + 779 0158 0126 movs r6, #1 + 780 .LVL58: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 781 .loc 1 393 5 view .LVU210 + 782 015a 3546 mov r5, r6 + 783 .LVL59: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 784 .loc 1 393 5 view .LVU211 + 785 015c 20E0 b .L63 + 786 .LVL60: + 787 .L65: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 788 .loc 1 393 5 view .LVU212 + 789 015e B3F5C00F cmp r3, #6291456 + 790 0162 02D0 beq .L68 + 791 0164 B3F5000F cmp r3, #8388608 + 792 0168 09D1 bne .L213 + 793 .L68: + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 794 .loc 1 437 5 is_stmt 1 view .LVU213 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 795 .loc 1 437 7 is_stmt 0 view .LVU214 + 796 016a C5B9 cbnz r5, .L176 + ARM GAS /tmp/ccSY6g1k.s page 78 + + + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 797 .loc 1 440 7 is_stmt 1 view .LVU215 + 798 016c 494A ldr r2, .L235 + 799 016e 936D ldr r3, [r2, #88] + 800 0170 23F46003 bic r3, r3, #14680064 + 801 0174 D4F8A410 ldr r1, [r4, #164] + 802 0178 0B43 orrs r3, r3, r1 + 803 017a 9365 str r3, [r2, #88] + 804 017c 10E0 b .L63 + 805 .L213: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 806 .loc 1 393 5 is_stmt 0 view .LVU216 + 807 017e 0126 movs r6, #1 + 808 .LVL61: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 809 .loc 1 393 5 view .LVU217 + 810 0180 3546 mov r5, r6 + 811 .LVL62: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 812 .loc 1 393 5 view .LVU218 + 813 0182 0DE0 b .L63 + 814 .LVL63: + 815 .L66: + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 816 .loc 1 397 7 is_stmt 1 view .LVU219 + 817 0184 434A ldr r2, .L235 + 818 0186 D36A ldr r3, [r2, #44] + 819 0188 43F40033 orr r3, r3, #131072 + 820 018c D362 str r3, [r2, #44] + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 821 .loc 1 400 7 view .LVU220 + 822 018e ECE7 b .L68 + 823 .L64: + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 824 .loc 1 410 7 view .LVU221 + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 825 .loc 1 410 13 is_stmt 0 view .LVU222 + 826 0190 0021 movs r1, #0 + 827 0192 04F12400 add r0, r4, #36 + 828 0196 FFF7FEFF bl RCCEx_PLL3_Config + 829 .LVL64: + 830 019a 0546 mov r5, r0 + 831 .LVL65: + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 832 .loc 1 413 7 is_stmt 1 view .LVU223 + 833 019c E5E7 b .L68 + 834 .L176: + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 835 .loc 1 413 7 is_stmt 0 view .LVU224 + 836 019e 2E46 mov r6, r5 + 837 .LVL66: + 838 .L63: + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 839 .loc 1 449 3 is_stmt 1 view .LVU225 + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 840 .loc 1 449 21 is_stmt 0 view .LVU226 + 841 01a0 2368 ldr r3, [r4] + ARM GAS /tmp/ccSY6g1k.s page 79 + + + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 842 .loc 1 449 5 view .LVU227 + 843 01a2 13F4006F tst r3, #2048 + 844 01a6 23D0 beq .L69 + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 845 .loc 1 451 5 is_stmt 1 view .LVU228 + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 846 .loc 1 451 25 is_stmt 0 view .LVU229 + 847 01a8 D4F8A830 ldr r3, [r4, #168] + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 848 .loc 1 451 5 view .LVU230 + 849 01ac B3F1007F cmp r3, #33554432 + 850 01b0 41D0 beq .L70 + 851 01b2 0DD8 bhi .L71 + 852 01b4 002B cmp r3, #0 + 853 01b6 38D0 beq .L72 + 854 01b8 B3F1807F cmp r3, #16777216 + 855 01bc 05D1 bne .L214 + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 856 .loc 1 462 7 is_stmt 1 view .LVU231 + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 857 .loc 1 462 13 is_stmt 0 view .LVU232 + 858 01be 0021 movs r1, #0 + 859 01c0 201D adds r0, r4, #4 + 860 01c2 FFF7FEFF bl RCCEx_PLL2_Config + 861 .LVL67: + 862 01c6 0546 mov r5, r0 + 863 .LVL68: + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 864 .loc 1 465 7 is_stmt 1 view .LVU233 + 865 01c8 08E0 b .L74 + 866 .L214: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 867 .loc 1 451 5 is_stmt 0 view .LVU234 + 868 01ca 0126 movs r6, #1 + 869 .LVL69: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 870 .loc 1 451 5 view .LVU235 + 871 01cc 3546 mov r5, r6 + 872 .LVL70: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 873 .loc 1 451 5 view .LVU236 + 874 01ce 0FE0 b .L69 + 875 .LVL71: + 876 .L71: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 877 .loc 1 451 5 view .LVU237 + 878 01d0 B3F1407F cmp r3, #50331648 + 879 01d4 02D0 beq .L74 + 880 01d6 B3F1806F cmp r3, #67108864 + 881 01da 23D1 bne .L215 + 882 .L74: + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 883 .loc 1 495 5 is_stmt 1 view .LVU238 + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 884 .loc 1 495 7 is_stmt 0 view .LVU239 + 885 01dc 002D cmp r5, #0 + ARM GAS /tmp/ccSY6g1k.s page 80 + + + 886 01de 31D1 bne .L177 + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 887 .loc 1 498 7 is_stmt 1 view .LVU240 + 888 01e0 2C4A ldr r2, .L235 + 889 01e2 936D ldr r3, [r2, #88] + 890 01e4 23F0E063 bic r3, r3, #117440512 + 891 01e8 D4F8A810 ldr r1, [r4, #168] + 892 01ec 0B43 orrs r3, r3, r1 + 893 01ee 9365 str r3, [r2, #88] + 894 .LVL72: + 895 .L69: + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 896 .loc 1 510 3 view .LVU241 + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 897 .loc 1 510 21 is_stmt 0 view .LVU242 + 898 01f0 2368 ldr r3, [r4] + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 899 .loc 1 510 5 view .LVU243 + 900 01f2 13F0007F tst r3, #33554432 + 901 01f6 2ED0 beq .L75 + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 902 .loc 1 512 5 is_stmt 1 view .LVU244 + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 903 .loc 1 512 25 is_stmt 0 view .LVU245 + 904 01f8 A36C ldr r3, [r4, #72] + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 905 .loc 1 512 5 view .LVU246 + 906 01fa 202B cmp r3, #32 + 907 01fc 3FD0 beq .L76 + 908 01fe 26D8 bhi .L77 + 909 0200 33B1 cbz r3, .L78 + 910 0202 102B cmp r3, #16 + 911 0204 20D1 bne .L216 + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 912 .loc 1 516 7 is_stmt 1 view .LVU247 + 913 0206 234A ldr r2, .L235 + 914 0208 D36A ldr r3, [r2, #44] + 915 020a 43F40033 orr r3, r3, #131072 + 916 020e D362 str r3, [r2, #44] + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 917 .loc 1 519 7 view .LVU248 + 918 .L78: + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 919 .loc 1 543 5 view .LVU249 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 920 .loc 1 543 7 is_stmt 0 view .LVU250 + 921 0210 002D cmp r5, #0 + 922 0212 3AD1 bne .L178 + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 923 .loc 1 546 7 is_stmt 1 view .LVU251 + 924 0214 1F4A ldr r2, .L235 + 925 0216 D36C ldr r3, [r2, #76] + 926 0218 23F03003 bic r3, r3, #48 + 927 021c A16C ldr r1, [r4, #72] + 928 021e 0B43 orrs r3, r3, r1 + 929 0220 D364 str r3, [r2, #76] + 930 0222 18E0 b .L75 + ARM GAS /tmp/ccSY6g1k.s page 81 + + + 931 .L215: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 932 .loc 1 451 5 is_stmt 0 view .LVU252 + 933 0224 0126 movs r6, #1 + 934 .LVL73: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 935 .loc 1 451 5 view .LVU253 + 936 0226 3546 mov r5, r6 + 937 .LVL74: + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 938 .loc 1 451 5 view .LVU254 + 939 0228 E2E7 b .L69 + 940 .LVL75: + 941 .L72: + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 942 .loc 1 455 7 is_stmt 1 view .LVU255 + 943 022a 1A4A ldr r2, .L235 + 944 022c D36A ldr r3, [r2, #44] + 945 022e 43F40033 orr r3, r3, #131072 + 946 0232 D362 str r3, [r2, #44] + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 947 .loc 1 458 7 view .LVU256 + 948 0234 D2E7 b .L74 + 949 .L70: + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 950 .loc 1 468 7 view .LVU257 + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 951 .loc 1 468 13 is_stmt 0 view .LVU258 + 952 0236 0021 movs r1, #0 + 953 0238 04F12400 add r0, r4, #36 + 954 023c FFF7FEFF bl RCCEx_PLL3_Config + 955 .LVL76: + 956 0240 0546 mov r5, r0 + 957 .LVL77: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 958 .loc 1 471 7 is_stmt 1 view .LVU259 + 959 0242 CBE7 b .L74 + 960 .L177: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 961 .loc 1 471 7 is_stmt 0 view .LVU260 + 962 0244 2E46 mov r6, r5 + 963 .LVL78: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 964 .loc 1 471 7 view .LVU261 + 965 0246 D3E7 b .L69 + 966 .LVL79: + 967 .L216: + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 968 .loc 1 512 5 view .LVU262 + 969 0248 0126 movs r6, #1 + 970 .LVL80: + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 971 .loc 1 512 5 view .LVU263 + 972 024a 3546 mov r5, r6 + 973 .LVL81: + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 974 .loc 1 512 5 view .LVU264 + ARM GAS /tmp/ccSY6g1k.s page 82 + + + 975 024c 03E0 b .L75 + 976 .LVL82: + 977 .L77: + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 978 .loc 1 512 5 view .LVU265 + 979 024e 302B cmp r3, #48 + 980 0250 DED0 beq .L78 + 981 0252 0126 movs r6, #1 + 982 .LVL83: + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 983 .loc 1 512 5 view .LVU266 + 984 0254 3546 mov r5, r6 + 985 .LVL84: + 986 .L75: + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 987 .loc 1 605 3 is_stmt 1 view .LVU267 + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 988 .loc 1 605 21 is_stmt 0 view .LVU268 + 989 0256 2368 ldr r3, [r4] + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 990 .loc 1 605 5 view .LVU269 + 991 0258 13F4805F tst r3, #4096 + 992 025c 2BD0 beq .L80 + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 993 .loc 1 607 5 is_stmt 1 view .LVU270 + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 994 .loc 1 607 25 is_stmt 0 view .LVU271 + 995 025e E36D ldr r3, [r4, #92] + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 996 .loc 1 607 5 view .LVU272 + 997 0260 B3F5005F cmp r3, #8192 + 998 0264 4CD0 beq .L81 + 999 0266 17D8 bhi .L82 + 1000 0268 002B cmp r3, #0 + 1001 026a 43D0 beq .L83 + 1002 026c B3F5805F cmp r3, #4096 + 1003 0270 0DD1 bne .L217 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1004 .loc 1 617 7 is_stmt 1 view .LVU273 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1005 .loc 1 617 13 is_stmt 0 view .LVU274 + 1006 0272 0021 movs r1, #0 + 1007 0274 201D adds r0, r4, #4 + 1008 0276 FFF7FEFF bl RCCEx_PLL2_Config + 1009 .LVL85: + 1010 027a 0546 mov r5, r0 + 1011 .LVL86: + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1012 .loc 1 620 7 is_stmt 1 view .LVU275 + 1013 027c 12E0 b .L85 + 1014 .L76: + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1015 .loc 1 523 7 view .LVU276 + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1016 .loc 1 523 13 is_stmt 0 view .LVU277 + 1017 027e 0221 movs r1, #2 + 1018 0280 201D adds r0, r4, #4 + ARM GAS /tmp/ccSY6g1k.s page 83 + + + 1019 0282 FFF7FEFF bl RCCEx_PLL2_Config + 1020 .LVL87: + 1021 0286 0546 mov r5, r0 + 1022 .LVL88: + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1023 .loc 1 526 7 is_stmt 1 view .LVU278 + 1024 0288 C2E7 b .L78 + 1025 .L178: + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1026 .loc 1 526 7 is_stmt 0 view .LVU279 + 1027 028a 2E46 mov r6, r5 + 1028 .LVL89: + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1029 .loc 1 526 7 view .LVU280 + 1030 028c E3E7 b .L75 + 1031 .LVL90: + 1032 .L217: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1033 .loc 1 607 5 view .LVU281 + 1034 028e 0126 movs r6, #1 + 1035 .LVL91: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1036 .loc 1 607 5 view .LVU282 + 1037 0290 3546 mov r5, r6 + 1038 .LVL92: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1039 .loc 1 607 5 view .LVU283 + 1040 0292 10E0 b .L80 + 1041 .L236: + 1042 .align 2 + 1043 .L235: + 1044 0294 00440258 .word 1476543488 + 1045 .LVL93: + 1046 .L82: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1047 .loc 1 607 5 view .LVU284 + 1048 0298 B3F5405F cmp r3, #12288 + 1049 029c 02D0 beq .L85 + 1050 029e B3F5804F cmp r3, #16384 + 1051 02a2 24D1 bne .L218 + 1052 .L85: + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1053 .loc 1 643 5 is_stmt 1 view .LVU285 + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1054 .loc 1 643 7 is_stmt 0 view .LVU286 + 1055 02a4 002D cmp r5, #0 + 1056 02a6 32D1 bne .L179 + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1057 .loc 1 646 7 is_stmt 1 view .LVU287 + 1058 02a8 754A ldr r2, .L237 + 1059 02aa 136D ldr r3, [r2, #80] + 1060 02ac 23F4E043 bic r3, r3, #28672 + 1061 02b0 E16D ldr r1, [r4, #92] + 1062 02b2 0B43 orrs r3, r3, r1 + 1063 02b4 1365 str r3, [r2, #80] + 1064 .LVL94: + 1065 .L80: + ARM GAS /tmp/ccSY6g1k.s page 84 + + + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1066 .loc 1 656 3 view .LVU288 + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1067 .loc 1 656 21 is_stmt 0 view .LVU289 + 1068 02b6 2368 ldr r3, [r4] + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1069 .loc 1 656 5 view .LVU290 + 1070 02b8 13F4005F tst r3, #8192 + 1071 02bc 37D0 beq .L86 + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1072 .loc 1 658 5 is_stmt 1 view .LVU291 + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1073 .loc 1 658 25 is_stmt 0 view .LVU292 + 1074 02be 236E ldr r3, [r4, #96] + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1075 .loc 1 658 5 view .LVU293 + 1076 02c0 B3F5003F cmp r3, #131072 + 1077 02c4 51D0 beq .L87 + 1078 02c6 27D8 bhi .L88 + 1079 02c8 3BB1 cbz r3, .L89 + 1080 02ca B3F5803F cmp r3, #65536 + 1081 02ce 20D1 bne .L219 + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1082 .loc 1 666 7 is_stmt 1 view .LVU294 + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1083 .loc 1 666 13 is_stmt 0 view .LVU295 + 1084 02d0 0121 movs r1, #1 + 1085 02d2 201D adds r0, r4, #4 + 1086 02d4 FFF7FEFF bl RCCEx_PLL2_Config + 1087 .LVL95: + 1088 02d8 0546 mov r5, r0 + 1089 .LVL96: + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + 1090 .loc 1 669 7 is_stmt 1 view .LVU296 + 1091 .L89: + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1092 .loc 1 695 5 view .LVU297 + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1093 .loc 1 695 7 is_stmt 0 view .LVU298 + 1094 02da 002D cmp r5, #0 + 1095 02dc 4CD1 bne .L180 + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1096 .loc 1 698 7 is_stmt 1 view .LVU299 + 1097 02de 684A ldr r2, .L237 + 1098 02e0 136D ldr r3, [r2, #80] + 1099 02e2 23F4E023 bic r3, r3, #458752 + 1100 02e6 216E ldr r1, [r4, #96] + 1101 02e8 0B43 orrs r3, r3, r1 + 1102 02ea 1365 str r3, [r2, #80] + 1103 02ec 1FE0 b .L86 + 1104 .L218: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1105 .loc 1 607 5 is_stmt 0 view .LVU300 + 1106 02ee 0126 movs r6, #1 + 1107 .LVL97: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1108 .loc 1 607 5 view .LVU301 + ARM GAS /tmp/ccSY6g1k.s page 85 + + + 1109 02f0 3546 mov r5, r6 + 1110 .LVL98: + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1111 .loc 1 607 5 view .LVU302 + 1112 02f2 E0E7 b .L80 + 1113 .LVL99: + 1114 .L83: + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1115 .loc 1 611 7 is_stmt 1 view .LVU303 + 1116 02f4 624A ldr r2, .L237 + 1117 02f6 D36A ldr r3, [r2, #44] + 1118 02f8 43F40033 orr r3, r3, #131072 + 1119 02fc D362 str r3, [r2, #44] + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1120 .loc 1 614 7 view .LVU304 + 1121 02fe D1E7 b .L85 + 1122 .L81: + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1123 .loc 1 623 7 view .LVU305 + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1124 .loc 1 623 13 is_stmt 0 view .LVU306 + 1125 0300 0021 movs r1, #0 + 1126 0302 04F12400 add r0, r4, #36 + 1127 0306 FFF7FEFF bl RCCEx_PLL3_Config + 1128 .LVL100: + 1129 030a 0546 mov r5, r0 + 1130 .LVL101: + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1131 .loc 1 626 7 is_stmt 1 view .LVU307 + 1132 030c CAE7 b .L85 + 1133 .L179: + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1134 .loc 1 626 7 is_stmt 0 view .LVU308 + 1135 030e 2E46 mov r6, r5 + 1136 .LVL102: + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1137 .loc 1 626 7 view .LVU309 + 1138 0310 D1E7 b .L80 + 1139 .LVL103: + 1140 .L219: + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1141 .loc 1 658 5 view .LVU310 + 1142 0312 0126 movs r6, #1 + 1143 .LVL104: + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1144 .loc 1 658 5 view .LVU311 + 1145 0314 3546 mov r5, r6 + 1146 .LVL105: + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1147 .loc 1 658 5 view .LVU312 + 1148 0316 0AE0 b .L86 + 1149 .LVL106: + 1150 .L88: + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1151 .loc 1 658 5 view .LVU313 + 1152 0318 B3F5802F cmp r3, #262144 + 1153 031c DDD0 beq .L89 + ARM GAS /tmp/ccSY6g1k.s page 86 + + + 1154 031e B3F5A02F cmp r3, #327680 + 1155 0322 DAD0 beq .L89 + 1156 0324 B3F5403F cmp r3, #196608 + 1157 0328 D7D0 beq .L89 + 1158 032a 0126 movs r6, #1 + 1159 .LVL107: + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1160 .loc 1 658 5 view .LVU314 + 1161 032c 3546 mov r5, r6 + 1162 .LVL108: + 1163 .L86: + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1164 .loc 1 708 3 is_stmt 1 view .LVU315 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1165 .loc 1 708 21 is_stmt 0 view .LVU316 + 1166 032e 2368 ldr r3, [r4] + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1167 .loc 1 708 5 view .LVU317 + 1168 0330 13F4804F tst r3, #16384 + 1169 0334 30D0 beq .L91 + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1170 .loc 1 710 5 is_stmt 1 view .LVU318 + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1171 .loc 1 710 25 is_stmt 0 view .LVU319 + 1172 0336 D4F8AC30 ldr r3, [r4, #172] + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1173 .loc 1 710 5 view .LVU320 + 1174 033a B3F1005F cmp r3, #536870912 + 1175 033e 44D0 beq .L92 + 1176 0340 1FD8 bhi .L93 + 1177 0342 3BB1 cbz r3, .L94 + 1178 0344 B3F1805F cmp r3, #268435456 + 1179 0348 18D1 bne .L220 + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1180 .loc 1 718 7 is_stmt 1 view .LVU321 + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1181 .loc 1 718 13 is_stmt 0 view .LVU322 + 1182 034a 0121 movs r1, #1 + 1183 034c 201D adds r0, r4, #4 + 1184 034e FFF7FEFF bl RCCEx_PLL2_Config + 1185 .LVL109: + 1186 0352 0546 mov r5, r0 + 1187 .LVL110: + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + 1188 .loc 1 721 7 is_stmt 1 view .LVU323 + 1189 .L94: + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1190 .loc 1 753 5 view .LVU324 + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1191 .loc 1 753 7 is_stmt 0 view .LVU325 + 1192 0354 002D cmp r5, #0 + 1193 0356 3FD1 bne .L181 + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1194 .loc 1 756 7 is_stmt 1 view .LVU326 + 1195 0358 494A ldr r2, .L237 + 1196 035a 936D ldr r3, [r2, #88] + 1197 035c 23F0E043 bic r3, r3, #1879048192 + ARM GAS /tmp/ccSY6g1k.s page 87 + + + 1198 0360 D4F8AC10 ldr r1, [r4, #172] + 1199 0364 0B43 orrs r3, r3, r1 + 1200 0366 9365 str r3, [r2, #88] + 1201 0368 16E0 b .L91 + 1202 .L87: + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 1203 .loc 1 671 7 view .LVU327 + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI4/5 clock source configuration done later after clock selection check */ + 1204 .loc 1 671 13 is_stmt 0 view .LVU328 + 1205 036a 0121 movs r1, #1 + 1206 036c 04F12400 add r0, r4, #36 + 1207 0370 FFF7FEFF bl RCCEx_PLL3_Config + 1208 .LVL111: + 1209 0374 0546 mov r5, r0 + 1210 .LVL112: + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1211 .loc 1 673 7 is_stmt 1 view .LVU329 + 1212 0376 B0E7 b .L89 + 1213 .L180: + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1214 .loc 1 673 7 is_stmt 0 view .LVU330 + 1215 0378 2E46 mov r6, r5 + 1216 .LVL113: + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1217 .loc 1 673 7 view .LVU331 + 1218 037a D8E7 b .L86 + 1219 .LVL114: + 1220 .L220: + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1221 .loc 1 710 5 view .LVU332 + 1222 037c 0126 movs r6, #1 + 1223 .LVL115: + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1224 .loc 1 710 5 view .LVU333 + 1225 037e 3546 mov r5, r6 + 1226 .LVL116: + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1227 .loc 1 710 5 view .LVU334 + 1228 0380 0AE0 b .L91 + 1229 .LVL117: + 1230 .L93: + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1231 .loc 1 710 5 view .LVU335 + 1232 0382 B3F1804F cmp r3, #1073741824 + 1233 0386 E5D0 beq .L94 + 1234 0388 B3F1A04F cmp r3, #1342177280 + 1235 038c E2D0 beq .L94 + 1236 038e B3F1405F cmp r3, #805306368 + 1237 0392 DFD0 beq .L94 + 1238 0394 0126 movs r6, #1 + 1239 .LVL118: + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1240 .loc 1 710 5 view .LVU336 + 1241 0396 3546 mov r5, r6 + 1242 .LVL119: + 1243 .L91: + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 88 + + + 1244 .loc 1 804 3 is_stmt 1 view .LVU337 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1245 .loc 1 804 21 is_stmt 0 view .LVU338 + 1246 0398 2368 ldr r3, [r4] + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1247 .loc 1 804 5 view .LVU339 + 1248 039a 13F4004F tst r3, #32768 + 1249 039e 09D0 beq .L96 + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1250 .loc 1 806 5 is_stmt 1 view .LVU340 + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1251 .loc 1 806 25 is_stmt 0 view .LVU341 + 1252 03a0 E36E ldr r3, [r4, #108] + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1253 .loc 1 806 5 view .LVU342 + 1254 03a2 B3F1805F cmp r3, #268435456 + 1255 03a6 19D0 beq .L97 + 1256 03a8 B3F1005F cmp r3, #536870912 + 1257 03ac 24D0 beq .L98 + 1258 03ae D3B1 cbz r3, .L99 + 1259 03b0 0126 movs r6, #1 + 1260 .LVL120: + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1261 .loc 1 806 5 view .LVU343 + 1262 03b2 3546 mov r5, r6 + 1263 .LVL121: + 1264 .L96: + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1265 .loc 1 846 3 is_stmt 1 view .LVU344 + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1266 .loc 1 846 21 is_stmt 0 view .LVU345 + 1267 03b4 2368 ldr r3, [r4] + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1268 .loc 1 846 5 view .LVU346 + 1269 03b6 13F0807F tst r3, #16777216 + 1270 03ba 32D0 beq .L100 + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1271 .loc 1 848 5 is_stmt 1 view .LVU347 + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1272 .loc 1 848 25 is_stmt 0 view .LVU348 + 1273 03bc 636C ldr r3, [r4, #68] + 1274 03be 032B cmp r3, #3 + 1275 03c0 59D8 bhi .L183 + 1276 03c2 DFE803F0 tbb [pc, r3] + 1277 .L102: + 1278 03c6 26 .byte (.L101-.L102)/2 + 1279 03c7 21 .byte (.L104-.L102)/2 + 1280 03c8 52 .byte (.L103-.L102)/2 + 1281 03c9 26 .byte (.L101-.L102)/2 + 1282 .p2align 1 + 1283 .L92: + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 1284 .loc 1 723 7 is_stmt 1 view .LVU349 + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* SPI6 clock source configuration done later after clock selection check */ + 1285 .loc 1 723 13 is_stmt 0 view .LVU350 + 1286 03ca 0121 movs r1, #1 + 1287 03cc 04F12400 add r0, r4, #36 + ARM GAS /tmp/ccSY6g1k.s page 89 + + + 1288 03d0 FFF7FEFF bl RCCEx_PLL3_Config + 1289 .LVL122: + 1290 03d4 0546 mov r5, r0 + 1291 .LVL123: + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1292 .loc 1 725 7 is_stmt 1 view .LVU351 + 1293 03d6 BDE7 b .L94 + 1294 .L181: + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1295 .loc 1 725 7 is_stmt 0 view .LVU352 + 1296 03d8 2E46 mov r6, r5 + 1297 .LVL124: + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1298 .loc 1 725 7 view .LVU353 + 1299 03da DDE7 b .L91 + 1300 .LVL125: + 1301 .L97: + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1302 .loc 1 810 7 is_stmt 1 view .LVU354 + 1303 03dc 284A ldr r2, .L237 + 1304 03de D36A ldr r3, [r2, #44] + 1305 03e0 43F40033 orr r3, r3, #131072 + 1306 03e4 D362 str r3, [r2, #44] + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1307 .loc 1 813 7 view .LVU355 + 1308 .L99: + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1309 .loc 1 832 5 view .LVU356 + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1310 .loc 1 832 7 is_stmt 0 view .LVU357 + 1311 03e6 6DB9 cbnz r5, .L182 + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1312 .loc 1 835 7 is_stmt 1 view .LVU358 + 1313 03e8 254A ldr r2, .L237 + 1314 03ea 136D ldr r3, [r2, #80] + 1315 03ec 23F04053 bic r3, r3, #805306368 + 1316 03f0 E16E ldr r1, [r4, #108] + 1317 03f2 0B43 orrs r3, r3, r1 + 1318 03f4 1365 str r3, [r2, #80] + 1319 03f6 DDE7 b .L96 + 1320 .L98: + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1321 .loc 1 817 7 view .LVU359 + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1322 .loc 1 817 13 is_stmt 0 view .LVU360 + 1323 03f8 0121 movs r1, #1 + 1324 03fa 201D adds r0, r4, #4 + 1325 03fc FFF7FEFF bl RCCEx_PLL2_Config + 1326 .LVL126: + 1327 0400 0546 mov r5, r0 + 1328 .LVL127: + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1329 .loc 1 820 7 is_stmt 1 view .LVU361 + 1330 0402 F0E7 b .L99 + 1331 .L182: + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1332 .loc 1 820 7 is_stmt 0 view .LVU362 + ARM GAS /tmp/ccSY6g1k.s page 90 + + + 1333 0404 2E46 mov r6, r5 + 1334 .LVL128: + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1335 .loc 1 820 7 view .LVU363 + 1336 0406 D5E7 b .L96 + 1337 .LVL129: + 1338 .L104: + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1339 .loc 1 852 7 is_stmt 1 view .LVU364 + 1340 0408 1D4A ldr r2, .L237 + 1341 040a D36A ldr r3, [r2, #44] + 1342 040c 43F40033 orr r3, r3, #131072 + 1343 0410 D362 str r3, [r2, #44] + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1344 .loc 1 855 7 view .LVU365 + 1345 .L101: + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1346 .loc 1 879 5 view .LVU366 + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1347 .loc 1 879 7 is_stmt 0 view .LVU367 + 1348 0412 9DBB cbnz r5, .L184 + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1349 .loc 1 882 7 is_stmt 1 view .LVU368 + 1350 0414 1A4A ldr r2, .L237 + 1351 0416 D36C ldr r3, [r2, #76] + 1352 0418 23F00303 bic r3, r3, #3 + 1353 041c 616C ldr r1, [r4, #68] + 1354 041e 0B43 orrs r3, r3, r1 + 1355 0420 D364 str r3, [r2, #76] + 1356 .LVL130: + 1357 .L100: + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1358 .loc 1 892 3 view .LVU369 + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1359 .loc 1 892 21 is_stmt 0 view .LVU370 + 1360 0422 2368 ldr r3, [r4] + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1361 .loc 1 892 5 view .LVU371 + 1362 0424 13F4800F tst r3, #4194304 + 1363 0428 2CD1 bne .L221 + 1364 .LVL131: + 1365 .L105: + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1366 .loc 1 962 3 is_stmt 1 view .LVU372 + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1367 .loc 1 962 21 is_stmt 0 view .LVU373 + 1368 042a 2368 ldr r3, [r4] + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1369 .loc 1 962 5 view .LVU374 + 1370 042c 13F0010F tst r3, #1 + 1371 0430 00F0A380 beq .L115 + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1372 .loc 1 964 5 is_stmt 1 view .LVU375 + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1373 .loc 1 964 25 is_stmt 0 view .LVU376 + 1374 0434 A36F ldr r3, [r4, #120] + 1375 0436 282B cmp r3, #40 + ARM GAS /tmp/ccSY6g1k.s page 91 + + + 1376 0438 00F29D80 bhi .L189 + 1377 043c DFE803F0 tbb [pc, r3] + 1378 .L117: + 1379 0440 8B .byte (.L116-.L117)/2 + 1380 0441 9B .byte (.L189-.L117)/2 + 1381 0442 9B .byte (.L189-.L117)/2 + 1382 0443 9B .byte (.L189-.L117)/2 + 1383 0444 9B .byte (.L189-.L117)/2 + 1384 0445 9B .byte (.L189-.L117)/2 + 1385 0446 9B .byte (.L189-.L117)/2 + 1386 0447 9B .byte (.L189-.L117)/2 + 1387 0448 86 .byte (.L119-.L117)/2 + 1388 0449 9B .byte (.L189-.L117)/2 + 1389 044a 9B .byte (.L189-.L117)/2 + 1390 044b 9B .byte (.L189-.L117)/2 + 1391 044c 9B .byte (.L189-.L117)/2 + 1392 044d 9B .byte (.L189-.L117)/2 + 1393 044e 9B .byte (.L189-.L117)/2 + 1394 044f 9B .byte (.L189-.L117)/2 + 1395 0450 94 .byte (.L118-.L117)/2 + 1396 0451 9B .byte (.L189-.L117)/2 + 1397 0452 9B .byte (.L189-.L117)/2 + 1398 0453 9B .byte (.L189-.L117)/2 + 1399 0454 9B .byte (.L189-.L117)/2 + 1400 0455 9B .byte (.L189-.L117)/2 + 1401 0456 9B .byte (.L189-.L117)/2 + 1402 0457 9B .byte (.L189-.L117)/2 + 1403 0458 8B .byte (.L116-.L117)/2 + 1404 0459 9B .byte (.L189-.L117)/2 + 1405 045a 9B .byte (.L189-.L117)/2 + 1406 045b 9B .byte (.L189-.L117)/2 + 1407 045c 9B .byte (.L189-.L117)/2 + 1408 045d 9B .byte (.L189-.L117)/2 + 1409 045e 9B .byte (.L189-.L117)/2 + 1410 045f 9B .byte (.L189-.L117)/2 + 1411 0460 8B .byte (.L116-.L117)/2 + 1412 0461 9B .byte (.L189-.L117)/2 + 1413 0462 9B .byte (.L189-.L117)/2 + 1414 0463 9B .byte (.L189-.L117)/2 + 1415 0464 9B .byte (.L189-.L117)/2 + 1416 0465 9B .byte (.L189-.L117)/2 + 1417 0466 9B .byte (.L189-.L117)/2 + 1418 0467 9B .byte (.L189-.L117)/2 + 1419 0468 8B .byte (.L116-.L117)/2 + 1420 0469 00 .p2align 1 + 1421 .L103: + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1422 .loc 1 859 7 is_stmt 1 view .LVU377 + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1423 .loc 1 859 13 is_stmt 0 view .LVU378 + 1424 046a 0221 movs r1, #2 + 1425 046c 201D adds r0, r4, #4 + 1426 046e FFF7FEFF bl RCCEx_PLL2_Config + 1427 .LVL132: + 1428 0472 0546 mov r5, r0 + 1429 .LVL133: + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 92 + + + 1430 .loc 1 862 7 is_stmt 1 view .LVU379 + 1431 0474 CDE7 b .L101 + 1432 .L183: + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1433 .loc 1 848 25 is_stmt 0 view .LVU380 + 1434 0476 0126 movs r6, #1 + 1435 .LVL134: + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1436 .loc 1 848 25 view .LVU381 + 1437 0478 3546 mov r5, r6 + 1438 .LVL135: + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1439 .loc 1 848 25 view .LVU382 + 1440 047a D2E7 b .L100 + 1441 .LVL136: + 1442 .L184: + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1443 .loc 1 848 25 view .LVU383 + 1444 047c 2E46 mov r6, r5 + 1445 .LVL137: + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1446 .loc 1 848 25 view .LVU384 + 1447 047e D0E7 b .L100 + 1448 .L238: + 1449 .align 2 + 1450 .L237: + 1451 0480 00440258 .word 1476543488 + 1452 .LVL138: + 1453 .L221: + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1454 .loc 1 895 5 is_stmt 1 view .LVU385 + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1455 .loc 1 898 5 view .LVU386 + 1456 0484 8F4A ldr r2, .L239 + 1457 0486 1368 ldr r3, [r2] + 1458 0488 43F48073 orr r3, r3, #256 + 1459 048c 1360 str r3, [r2] + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1460 .loc 1 901 5 view .LVU387 + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1461 .loc 1 901 17 is_stmt 0 view .LVU388 + 1462 048e FFF7FEFF bl HAL_GetTick + 1463 .LVL139: + 1464 0492 0746 mov r7, r0 + 1465 .LVL140: + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1466 .loc 1 903 5 is_stmt 1 view .LVU389 + 1467 .L106: + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1468 .loc 1 903 10 view .LVU390 + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1469 .loc 1 903 15 is_stmt 0 view .LVU391 + 1470 0494 8B4B ldr r3, .L239 + 1471 0496 1B68 ldr r3, [r3] + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1472 .loc 1 903 10 view .LVU392 + 1473 0498 13F4807F tst r3, #256 + ARM GAS /tmp/ccSY6g1k.s page 93 + + + 1474 049c 05D1 bne .L107 + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1475 .loc 1 905 7 is_stmt 1 view .LVU393 + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1476 .loc 1 905 11 is_stmt 0 view .LVU394 + 1477 049e FFF7FEFF bl HAL_GetTick + 1478 .LVL141: + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1479 .loc 1 905 25 view .LVU395 + 1480 04a2 C01B subs r0, r0, r7 + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1481 .loc 1 905 9 view .LVU396 + 1482 04a4 6428 cmp r0, #100 + 1483 04a6 F5D9 bls .L106 + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 1484 .loc 1 907 13 view .LVU397 + 1485 04a8 0325 movs r5, #3 + 1486 .LVL142: + 1487 .L107: + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1488 .loc 1 912 5 is_stmt 1 view .LVU398 + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1489 .loc 1 912 7 is_stmt 0 view .LVU399 + 1490 04aa 002D cmp r5, #0 + 1491 04ac 4AD1 bne .L186 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1492 .loc 1 915 7 is_stmt 1 view .LVU400 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1493 .loc 1 915 14 is_stmt 0 view .LVU401 + 1494 04ae 864B ldr r3, .L239+4 + 1495 04b0 1B6F ldr r3, [r3, #112] + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1496 .loc 1 915 57 view .LVU402 + 1497 04b2 D4F8B020 ldr r2, [r4, #176] + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1498 .loc 1 915 40 view .LVU403 + 1499 04b6 5340 eors r3, r3, r2 + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1500 .loc 1 915 9 view .LVU404 + 1501 04b8 13F4407F tst r3, #768 + 1502 04bc 0CD0 beq .L109 + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 1503 .loc 1 918 9 is_stmt 1 view .LVU405 + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 1504 .loc 1 918 22 is_stmt 0 view .LVU406 + 1505 04be 824B ldr r3, .L239+4 + 1506 04c0 1A6F ldr r2, [r3, #112] + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 1507 .loc 1 918 16 view .LVU407 + 1508 04c2 22F44072 bic r2, r2, #768 + 1509 .LVL143: + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 1510 .loc 1 920 9 is_stmt 1 view .LVU408 + 1511 04c6 196F ldr r1, [r3, #112] + 1512 04c8 41F48031 orr r1, r1, #65536 + 1513 04cc 1967 str r1, [r3, #112] + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + ARM GAS /tmp/ccSY6g1k.s page 94 + + + 1514 .loc 1 921 9 view .LVU409 + 1515 04ce 196F ldr r1, [r3, #112] + 1516 04d0 21F48031 bic r1, r1, #65536 + 1517 04d4 1967 str r1, [r3, #112] + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1518 .loc 1 923 9 view .LVU410 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1519 .loc 1 923 19 is_stmt 0 view .LVU411 + 1520 04d6 1A67 str r2, [r3, #112] + 1521 .LVL144: + 1522 .L109: + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1523 .loc 1 927 7 is_stmt 1 view .LVU412 + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1524 .loc 1 927 23 is_stmt 0 view .LVU413 + 1525 04d8 D4F8B030 ldr r3, [r4, #176] + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1526 .loc 1 927 9 view .LVU414 + 1527 04dc B3F5807F cmp r3, #256 + 1528 04e0 15D0 beq .L222 + 1529 .LVL145: + 1530 .L110: + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1531 .loc 1 943 7 is_stmt 1 view .LVU415 + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1532 .loc 1 943 9 is_stmt 0 view .LVU416 + 1533 04e2 8DBB cbnz r5, .L188 + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1534 .loc 1 945 9 is_stmt 1 view .LVU417 + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1535 .loc 1 945 9 view .LVU418 + 1536 04e4 D4F8B030 ldr r3, [r4, #176] + 1537 04e8 03F44072 and r2, r3, #768 + 1538 04ec B2F5407F cmp r2, #768 + 1539 04f0 1ED0 beq .L223 + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1540 .loc 1 945 9 is_stmt 0 discriminator 2 view .LVU419 + 1541 04f2 754A ldr r2, .L239+4 + 1542 04f4 1369 ldr r3, [r2, #16] + 1543 04f6 23F47C53 bic r3, r3, #16128 + 1544 04fa 1361 str r3, [r2, #16] + 1545 .L114: + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1546 .loc 1 945 9 is_stmt 1 discriminator 4 view .LVU420 + 1547 04fc 7249 ldr r1, .L239+4 + 1548 04fe 0B6F ldr r3, [r1, #112] + 1549 0500 D4F8B020 ldr r2, [r4, #176] + 1550 0504 C2F30B02 ubfx r2, r2, #0, #12 + 1551 0508 1343 orrs r3, r3, r2 + 1552 050a 0B67 str r3, [r1, #112] + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1553 .loc 1 945 9 discriminator 4 view .LVU421 + 1554 050c 8DE7 b .L105 + 1555 .L222: + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1556 .loc 1 930 9 view .LVU422 + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 95 + + + 1557 .loc 1 930 21 is_stmt 0 view .LVU423 + 1558 050e FFF7FEFF bl HAL_GetTick + 1559 .LVL146: + 1560 0512 0746 mov r7, r0 + 1561 .LVL147: + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1562 .loc 1 933 9 is_stmt 1 view .LVU424 + 1563 .L111: + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1564 .loc 1 933 14 view .LVU425 + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1565 .loc 1 933 15 is_stmt 0 view .LVU426 + 1566 0514 6C4B ldr r3, .L239+4 + 1567 0516 1B6F ldr r3, [r3, #112] + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1568 .loc 1 933 14 view .LVU427 + 1569 0518 13F0020F tst r3, #2 + 1570 051c E1D1 bne .L110 + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1571 .loc 1 935 11 is_stmt 1 view .LVU428 + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1572 .loc 1 935 15 is_stmt 0 view .LVU429 + 1573 051e FFF7FEFF bl HAL_GetTick + 1574 .LVL148: + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1575 .loc 1 935 29 view .LVU430 + 1576 0522 C01B subs r0, r0, r7 + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1577 .loc 1 935 13 view .LVU431 + 1578 0524 41F28833 movw r3, #5000 + 1579 0528 9842 cmp r0, r3 + 1580 052a F3D9 bls .L111 + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 1581 .loc 1 937 17 view .LVU432 + 1582 052c 0325 movs r5, #3 + 1583 .LVL149: + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 1584 .loc 1 937 17 view .LVU433 + 1585 052e D8E7 b .L110 + 1586 .LVL150: + 1587 .L223: + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1588 .loc 1 945 9 discriminator 1 view .LVU434 + 1589 0530 6548 ldr r0, .L239+4 + 1590 0532 0269 ldr r2, [r0, #16] + 1591 0534 22F47C52 bic r2, r2, #16128 + 1592 0538 6449 ldr r1, .L239+8 + 1593 053a 01EA1313 and r3, r1, r3, lsr #4 + 1594 053e 1343 orrs r3, r3, r2 + 1595 0540 0361 str r3, [r0, #16] + 1596 0542 DBE7 b .L114 + 1597 .L186: + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1598 .loc 1 956 14 view .LVU435 + 1599 0544 2E46 mov r6, r5 + 1600 .LVL151: + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 96 + + + 1601 .loc 1 956 14 view .LVU436 + 1602 0546 70E7 b .L105 + 1603 .LVL152: + 1604 .L188: + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1605 .loc 1 950 16 view .LVU437 + 1606 0548 2E46 mov r6, r5 + 1607 .LVL153: + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1608 .loc 1 950 16 view .LVU438 + 1609 054a 6EE7 b .L105 + 1610 .LVL154: + 1611 .L119: + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 1612 .loc 1 971 7 is_stmt 1 view .LVU439 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 1613 .loc 1 971 13 is_stmt 0 view .LVU440 + 1614 054c 0121 movs r1, #1 + 1615 054e 201D adds r0, r4, #4 + 1616 0550 FFF7FEFF bl RCCEx_PLL2_Config + 1617 .LVL155: + 1618 0554 0546 mov r5, r0 + 1619 .LVL156: + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1620 .loc 1 973 7 is_stmt 1 view .LVU441 + 1621 .L116: +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1622 .loc 1 1000 5 view .LVU442 +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1623 .loc 1 1000 7 is_stmt 0 view .LVU443 + 1624 0556 E5B9 cbnz r5, .L190 +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1625 .loc 1 1003 7 is_stmt 1 view .LVU444 + 1626 0558 5B4A ldr r2, .L239+4 + 1627 055a 536D ldr r3, [r2, #84] + 1628 055c 23F03803 bic r3, r3, #56 + 1629 0560 A16F ldr r1, [r4, #120] + 1630 0562 0B43 orrs r3, r3, r1 + 1631 0564 5365 str r3, [r2, #84] + 1632 0566 08E0 b .L115 + 1633 .L118: + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 1634 .loc 1 976 7 view .LVU445 + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART1/6 clock source configuration done later after clock selection check */ + 1635 .loc 1 976 13 is_stmt 0 view .LVU446 + 1636 0568 0121 movs r1, #1 + 1637 056a 04F12400 add r0, r4, #36 + 1638 056e FFF7FEFF bl RCCEx_PLL3_Config + 1639 .LVL157: + 1640 0572 0546 mov r5, r0 + 1641 .LVL158: + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1642 .loc 1 978 7 is_stmt 1 view .LVU447 + 1643 0574 EFE7 b .L116 + 1644 .L189: + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1645 .loc 1 964 25 is_stmt 0 view .LVU448 + ARM GAS /tmp/ccSY6g1k.s page 97 + + + 1646 0576 0126 movs r6, #1 + 1647 .LVL159: + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1648 .loc 1 964 25 view .LVU449 + 1649 0578 3546 mov r5, r6 + 1650 .LVL160: + 1651 .L115: +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1652 .loc 1 1013 3 is_stmt 1 view .LVU450 +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1653 .loc 1 1013 21 is_stmt 0 view .LVU451 + 1654 057a 2368 ldr r3, [r4] +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1655 .loc 1 1013 5 view .LVU452 + 1656 057c 13F0020F tst r3, #2 + 1657 0580 16D0 beq .L120 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1658 .loc 1 1015 5 is_stmt 1 view .LVU453 +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1659 .loc 1 1015 25 is_stmt 0 view .LVU454 + 1660 0582 636F ldr r3, [r4, #116] + 1661 0584 052B cmp r3, #5 + 1662 0586 27D8 bhi .L191 + 1663 0588 DFE803F0 tbb [pc, r3] + 1664 .L122: + 1665 058c 0A .byte (.L121-.L122)/2 + 1666 058d 05 .byte (.L124-.L122)/2 + 1667 058e 1F .byte (.L123-.L122)/2 + 1668 058f 0A .byte (.L121-.L122)/2 + 1669 0590 0A .byte (.L121-.L122)/2 + 1670 0591 0A .byte (.L121-.L122)/2 + 1671 .p2align 1 + 1672 .L190: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1673 .loc 1 1015 25 view .LVU455 + 1674 0592 2E46 mov r6, r5 + 1675 .LVL161: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1676 .loc 1 1015 25 view .LVU456 + 1677 0594 F1E7 b .L115 + 1678 .LVL162: + 1679 .L124: +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + 1680 .loc 1 1022 7 is_stmt 1 view .LVU457 +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + 1681 .loc 1 1022 13 is_stmt 0 view .LVU458 + 1682 0596 0121 movs r1, #1 + 1683 0598 201D adds r0, r4, #4 + 1684 059a FFF7FEFF bl RCCEx_PLL2_Config + 1685 .LVL163: + 1686 059e 0546 mov r5, r0 + 1687 .LVL164: +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1688 .loc 1 1024 7 is_stmt 1 view .LVU459 + 1689 .L121: +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1690 .loc 1 1051 5 view .LVU460 + ARM GAS /tmp/ccSY6g1k.s page 98 + + +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1691 .loc 1 1051 7 is_stmt 0 view .LVU461 + 1692 05a0 EDB9 cbnz r5, .L192 +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1693 .loc 1 1054 7 is_stmt 1 view .LVU462 + 1694 05a2 494A ldr r2, .L239+4 + 1695 05a4 536D ldr r3, [r2, #84] + 1696 05a6 23F00703 bic r3, r3, #7 + 1697 05aa 616F ldr r1, [r4, #116] + 1698 05ac 0B43 orrs r3, r3, r1 + 1699 05ae 5365 str r3, [r2, #84] + 1700 .LVL165: + 1701 .L120: +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1702 .loc 1 1064 3 view .LVU463 +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1703 .loc 1 1064 21 is_stmt 0 view .LVU464 + 1704 05b0 2368 ldr r3, [r4] +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1705 .loc 1 1064 5 view .LVU465 + 1706 05b2 13F0040F tst r3, #4 + 1707 05b6 22D0 beq .L125 +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1708 .loc 1 1066 5 is_stmt 1 view .LVU466 +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1709 .loc 1 1066 25 is_stmt 0 view .LVU467 + 1710 05b8 D4F89030 ldr r3, [r4, #144] + 1711 05bc 052B cmp r3, #5 + 1712 05be 43D8 bhi .L193 + 1713 05c0 DFE803F0 tbb [pc, r3] + 1714 .L127: + 1715 05c4 14 .byte (.L126-.L127)/2 + 1716 05c5 0F .byte (.L129-.L127)/2 + 1717 05c6 3B .byte (.L128-.L127)/2 + 1718 05c7 14 .byte (.L126-.L127)/2 + 1719 05c8 14 .byte (.L126-.L127)/2 + 1720 05c9 14 .byte (.L126-.L127)/2 + 1721 .p2align 1 + 1722 .L123: +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + 1723 .loc 1 1027 7 is_stmt 1 view .LVU468 +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + 1724 .loc 1 1027 13 is_stmt 0 view .LVU469 + 1725 05ca 0121 movs r1, #1 + 1726 05cc 04F12400 add r0, r4, #36 + 1727 05d0 FFF7FEFF bl RCCEx_PLL3_Config + 1728 .LVL166: + 1729 05d4 0546 mov r5, r0 + 1730 .LVL167: +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1731 .loc 1 1029 7 is_stmt 1 view .LVU470 + 1732 05d6 E3E7 b .L121 + 1733 .L191: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1734 .loc 1 1015 25 is_stmt 0 view .LVU471 + 1735 05d8 0126 movs r6, #1 + 1736 .LVL168: + ARM GAS /tmp/ccSY6g1k.s page 99 + + +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1737 .loc 1 1015 25 view .LVU472 + 1738 05da 3546 mov r5, r6 + 1739 .LVL169: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1740 .loc 1 1015 25 view .LVU473 + 1741 05dc E8E7 b .L120 + 1742 .LVL170: + 1743 .L192: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1744 .loc 1 1015 25 view .LVU474 + 1745 05de 2E46 mov r6, r5 + 1746 .LVL171: +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1747 .loc 1 1015 25 view .LVU475 + 1748 05e0 E6E7 b .L120 + 1749 .LVL172: + 1750 .L129: +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ + 1751 .loc 1 1073 7 is_stmt 1 view .LVU476 +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ + 1752 .loc 1 1073 13 is_stmt 0 view .LVU477 + 1753 05e2 0121 movs r1, #1 + 1754 05e4 201D adds r0, r4, #4 + 1755 05e6 FFF7FEFF bl RCCEx_PLL2_Config + 1756 .LVL173: + 1757 05ea 0546 mov r5, r0 + 1758 .LVL174: +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1759 .loc 1 1075 7 is_stmt 1 view .LVU478 + 1760 .L126: +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1761 .loc 1 1102 5 view .LVU479 +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1762 .loc 1 1102 7 is_stmt 0 view .LVU480 + 1763 05ec 7DBB cbnz r5, .L194 +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1764 .loc 1 1105 7 is_stmt 1 view .LVU481 + 1765 05ee 364A ldr r2, .L239+4 + 1766 05f0 936D ldr r3, [r2, #88] + 1767 05f2 23F00703 bic r3, r3, #7 + 1768 05f6 D4F89010 ldr r1, [r4, #144] + 1769 05fa 0B43 orrs r3, r3, r1 + 1770 05fc 9365 str r3, [r2, #88] + 1771 .LVL175: + 1772 .L125: +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1773 .loc 1 1115 3 view .LVU482 +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1774 .loc 1 1115 21 is_stmt 0 view .LVU483 + 1775 05fe 2368 ldr r3, [r4] +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1776 .loc 1 1115 5 view .LVU484 + 1777 0600 13F0200F tst r3, #32 + 1778 0604 33D0 beq .L130 +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1779 .loc 1 1117 5 is_stmt 1 view .LVU485 + ARM GAS /tmp/ccSY6g1k.s page 100 + + +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1780 .loc 1 1117 25 is_stmt 0 view .LVU486 + 1781 0606 D4F88C30 ldr r3, [r4, #140] +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1782 .loc 1 1117 5 view .LVU487 + 1783 060a B3F1005F cmp r3, #536870912 + 1784 060e 4CD0 beq .L131 + 1785 0610 22D8 bhi .L132 + 1786 0612 3BB1 cbz r3, .L133 + 1787 0614 B3F1805F cmp r3, #268435456 + 1788 0618 1BD1 bne .L224 +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1789 .loc 1 1125 7 is_stmt 1 view .LVU488 +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1790 .loc 1 1125 13 is_stmt 0 view .LVU489 + 1791 061a 0021 movs r1, #0 + 1792 061c 201D adds r0, r4, #4 + 1793 061e FFF7FEFF bl RCCEx_PLL2_Config + 1794 .LVL176: + 1795 0622 0546 mov r5, r0 + 1796 .LVL177: +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1797 .loc 1 1128 7 is_stmt 1 view .LVU490 + 1798 .L133: +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1799 .loc 1 1155 5 view .LVU491 +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1800 .loc 1 1155 7 is_stmt 0 view .LVU492 + 1801 0624 002D cmp r5, #0 + 1802 0626 47D1 bne .L195 +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1803 .loc 1 1158 7 is_stmt 1 view .LVU493 + 1804 0628 274A ldr r2, .L239+4 + 1805 062a 536D ldr r3, [r2, #84] + 1806 062c 23F0E043 bic r3, r3, #1879048192 + 1807 0630 D4F88C10 ldr r1, [r4, #140] + 1808 0634 0B43 orrs r3, r3, r1 + 1809 0636 5365 str r3, [r2, #84] + 1810 0638 19E0 b .L130 + 1811 .L128: +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ + 1812 .loc 1 1078 7 view .LVU494 +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* LPUART1 clock source configuration done later after clock selection check */ + 1813 .loc 1 1078 13 is_stmt 0 view .LVU495 + 1814 063a 0121 movs r1, #1 + 1815 063c 04F12400 add r0, r4, #36 + 1816 0640 FFF7FEFF bl RCCEx_PLL3_Config + 1817 .LVL178: + 1818 0644 0546 mov r5, r0 + 1819 .LVL179: +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1820 .loc 1 1080 7 is_stmt 1 view .LVU496 + 1821 0646 D1E7 b .L126 + 1822 .L193: +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1823 .loc 1 1066 25 is_stmt 0 view .LVU497 + 1824 0648 0126 movs r6, #1 + ARM GAS /tmp/ccSY6g1k.s page 101 + + + 1825 .LVL180: +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1826 .loc 1 1066 25 view .LVU498 + 1827 064a 3546 mov r5, r6 + 1828 .LVL181: +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1829 .loc 1 1066 25 view .LVU499 + 1830 064c D7E7 b .L125 + 1831 .LVL182: + 1832 .L194: +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1833 .loc 1 1066 25 view .LVU500 + 1834 064e 2E46 mov r6, r5 + 1835 .LVL183: +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1836 .loc 1 1066 25 view .LVU501 + 1837 0650 D5E7 b .L125 + 1838 .LVL184: + 1839 .L224: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1840 .loc 1 1117 5 view .LVU502 + 1841 0652 0126 movs r6, #1 + 1842 .LVL185: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1843 .loc 1 1117 5 view .LVU503 + 1844 0654 3546 mov r5, r6 + 1845 .LVL186: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1846 .loc 1 1117 5 view .LVU504 + 1847 0656 0AE0 b .L130 + 1848 .LVL187: + 1849 .L132: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1850 .loc 1 1117 5 view .LVU505 + 1851 0658 B3F1804F cmp r3, #1073741824 + 1852 065c E2D0 beq .L133 + 1853 065e B3F1A04F cmp r3, #1342177280 + 1854 0662 DFD0 beq .L133 + 1855 0664 B3F1405F cmp r3, #805306368 + 1856 0668 DCD0 beq .L133 + 1857 066a 0126 movs r6, #1 + 1858 .LVL188: +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1859 .loc 1 1117 5 view .LVU506 + 1860 066c 3546 mov r5, r6 + 1861 .LVL189: + 1862 .L130: +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1863 .loc 1 1168 3 is_stmt 1 view .LVU507 +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1864 .loc 1 1168 21 is_stmt 0 view .LVU508 + 1865 066e 2368 ldr r3, [r4] +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1866 .loc 1 1168 5 view .LVU509 + 1867 0670 13F0400F tst r3, #64 + 1868 0674 37D0 beq .L135 +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 102 + + + 1869 .loc 1 1170 5 is_stmt 1 view .LVU510 +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1870 .loc 1 1170 25 is_stmt 0 view .LVU511 + 1871 0676 D4F89830 ldr r3, [r4, #152] +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1872 .loc 1 1170 5 view .LVU512 + 1873 067a B3F5006F cmp r3, #2048 + 1874 067e 52D0 beq .L136 + 1875 0680 26D8 bhi .L137 + 1876 0682 3BB1 cbz r3, .L138 + 1877 0684 B3F5806F cmp r3, #1024 + 1878 0688 18D1 bne .L225 +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1879 .loc 1 1178 7 is_stmt 1 view .LVU513 +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1880 .loc 1 1178 13 is_stmt 0 view .LVU514 + 1881 068a 0021 movs r1, #0 + 1882 068c 201D adds r0, r4, #4 + 1883 068e FFF7FEFF bl RCCEx_PLL2_Config + 1884 .LVL190: + 1885 0692 0546 mov r5, r0 + 1886 .LVL191: +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1887 .loc 1 1181 7 is_stmt 1 view .LVU515 + 1888 .L138: +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1889 .loc 1 1208 5 view .LVU516 +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1890 .loc 1 1208 7 is_stmt 0 view .LVU517 + 1891 0694 002D cmp r5, #0 + 1892 0696 4DD1 bne .L196 +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1893 .loc 1 1211 7 is_stmt 1 view .LVU518 + 1894 0698 0B4A ldr r2, .L239+4 + 1895 069a 936D ldr r3, [r2, #88] + 1896 069c 23F4E053 bic r3, r3, #7168 + 1897 06a0 D4F89810 ldr r1, [r4, #152] + 1898 06a4 0B43 orrs r3, r3, r1 + 1899 06a6 9365 str r3, [r2, #88] + 1900 06a8 1DE0 b .L135 + 1901 .L131: +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1902 .loc 1 1131 7 view .LVU519 +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1903 .loc 1 1131 13 is_stmt 0 view .LVU520 + 1904 06aa 0221 movs r1, #2 + 1905 06ac 04F12400 add r0, r4, #36 + 1906 06b0 FFF7FEFF bl RCCEx_PLL3_Config + 1907 .LVL192: + 1908 06b4 0546 mov r5, r0 + 1909 .LVL193: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1910 .loc 1 1134 7 is_stmt 1 view .LVU521 + 1911 06b6 B5E7 b .L133 + 1912 .L195: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1913 .loc 1 1134 7 is_stmt 0 view .LVU522 + ARM GAS /tmp/ccSY6g1k.s page 103 + + + 1914 06b8 2E46 mov r6, r5 + 1915 .LVL194: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1916 .loc 1 1134 7 view .LVU523 + 1917 06ba D8E7 b .L130 + 1918 .LVL195: + 1919 .L225: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1920 .loc 1 1170 5 view .LVU524 + 1921 06bc 0126 movs r6, #1 + 1922 .LVL196: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1923 .loc 1 1170 5 view .LVU525 + 1924 06be 3546 mov r5, r6 + 1925 .LVL197: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1926 .loc 1 1170 5 view .LVU526 + 1927 06c0 11E0 b .L135 + 1928 .L240: + 1929 06c2 00BF .align 2 + 1930 .L239: + 1931 06c4 00480258 .word 1476544512 + 1932 06c8 00440258 .word 1476543488 + 1933 06cc CFFFFF00 .word 16777167 + 1934 .LVL198: + 1935 .L137: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1936 .loc 1 1170 5 view .LVU527 + 1937 06d0 B3F5805F cmp r3, #4096 + 1938 06d4 DED0 beq .L138 + 1939 06d6 B3F5A05F cmp r3, #5120 + 1940 06da DBD0 beq .L138 + 1941 06dc B3F5406F cmp r3, #3072 + 1942 06e0 D8D0 beq .L138 + 1943 06e2 0126 movs r6, #1 + 1944 .LVL199: +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1945 .loc 1 1170 5 view .LVU528 + 1946 06e4 3546 mov r5, r6 + 1947 .LVL200: + 1948 .L135: +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1949 .loc 1 1221 3 is_stmt 1 view .LVU529 +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1950 .loc 1 1221 21 is_stmt 0 view .LVU530 + 1951 06e6 2368 ldr r3, [r4] +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1952 .loc 1 1221 5 view .LVU531 + 1953 06e8 13F0800F tst r3, #128 + 1954 06ec 32D0 beq .L140 +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1955 .loc 1 1223 5 is_stmt 1 view .LVU532 +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1956 .loc 1 1223 25 is_stmt 0 view .LVU533 + 1957 06ee D4F89C30 ldr r3, [r4, #156] +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1958 .loc 1 1223 5 view .LVU534 + ARM GAS /tmp/ccSY6g1k.s page 104 + + + 1959 06f2 B3F5804F cmp r3, #16384 + 1960 06f6 00F09D80 beq .L141 + 1961 06fa 20D8 bhi .L142 + 1962 06fc 3BB1 cbz r3, .L143 + 1963 06fe B3F5005F cmp r3, #8192 + 1964 0702 19D1 bne .L226 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1965 .loc 1 1231 7 is_stmt 1 view .LVU535 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1966 .loc 1 1231 13 is_stmt 0 view .LVU536 + 1967 0704 0021 movs r1, #0 + 1968 0706 201D adds r0, r4, #4 + 1969 0708 FFF7FEFF bl RCCEx_PLL2_Config + 1970 .LVL201: + 1971 070c 0546 mov r5, r0 + 1972 .LVL202: +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1973 .loc 1 1234 7 is_stmt 1 view .LVU537 + 1974 .L143: +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1975 .loc 1 1261 5 view .LVU538 +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 1976 .loc 1 1261 7 is_stmt 0 view .LVU539 + 1977 070e 002D cmp r5, #0 + 1978 0710 40F09780 bne .L197 +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 1979 .loc 1 1264 7 is_stmt 1 view .LVU540 + 1980 0714 A34A ldr r2, .L241 + 1981 0716 936D ldr r3, [r2, #88] + 1982 0718 23F46043 bic r3, r3, #57344 + 1983 071c D4F89C10 ldr r1, [r4, #156] + 1984 0720 0B43 orrs r3, r3, r1 + 1985 0722 9365 str r3, [r2, #88] + 1986 0724 16E0 b .L140 + 1987 .L136: +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1988 .loc 1 1184 7 view .LVU541 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1989 .loc 1 1184 13 is_stmt 0 view .LVU542 + 1990 0726 0221 movs r1, #2 + 1991 0728 04F12400 add r0, r4, #36 + 1992 072c FFF7FEFF bl RCCEx_PLL3_Config + 1993 .LVL203: + 1994 0730 0546 mov r5, r0 + 1995 .LVL204: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1996 .loc 1 1187 7 is_stmt 1 view .LVU543 + 1997 0732 AFE7 b .L138 + 1998 .L196: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 1999 .loc 1 1187 7 is_stmt 0 view .LVU544 + 2000 0734 2E46 mov r6, r5 + 2001 .LVL205: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2002 .loc 1 1187 7 view .LVU545 + 2003 0736 D6E7 b .L135 + 2004 .LVL206: + ARM GAS /tmp/ccSY6g1k.s page 105 + + + 2005 .L226: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2006 .loc 1 1223 5 view .LVU546 + 2007 0738 0126 movs r6, #1 + 2008 .LVL207: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2009 .loc 1 1223 5 view .LVU547 + 2010 073a 3546 mov r5, r6 + 2011 .LVL208: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2012 .loc 1 1223 5 view .LVU548 + 2013 073c 0AE0 b .L140 + 2014 .LVL209: + 2015 .L142: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2016 .loc 1 1223 5 view .LVU549 + 2017 073e B3F5004F cmp r3, #32768 + 2018 0742 E4D0 beq .L143 + 2019 0744 B3F5204F cmp r3, #40960 + 2020 0748 E1D0 beq .L143 + 2021 074a B3F5C04F cmp r3, #24576 + 2022 074e DED0 beq .L143 + 2023 0750 0126 movs r6, #1 + 2024 .LVL210: +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2025 .loc 1 1223 5 view .LVU550 + 2026 0752 3546 mov r5, r6 + 2027 .LVL211: + 2028 .L140: +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2029 .loc 1 1292 3 is_stmt 1 view .LVU551 +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2030 .loc 1 1292 21 is_stmt 0 view .LVU552 + 2031 0754 2368 ldr r3, [r4] +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2032 .loc 1 1292 5 view .LVU553 + 2033 0756 13F0080F tst r3, #8 + 2034 075a 0CD0 beq .L145 +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2035 .loc 1 1295 5 is_stmt 1 view .LVU554 +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2036 .loc 1 1297 5 view .LVU555 +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2037 .loc 1 1297 23 is_stmt 0 view .LVU556 + 2038 075c D4F88030 ldr r3, [r4, #128] +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2039 .loc 1 1297 8 view .LVU557 + 2040 0760 B3F5805F cmp r3, #4096 + 2041 0764 6FD0 beq .L227 + 2042 .LVL212: + 2043 .L146: +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2044 .loc 1 1305 7 is_stmt 1 view .LVU558 + 2045 0766 8F4A ldr r2, .L241 + 2046 0768 536D ldr r3, [r2, #84] + 2047 076a 23F44053 bic r3, r3, #12288 + 2048 076e D4F88010 ldr r1, [r4, #128] + ARM GAS /tmp/ccSY6g1k.s page 106 + + + 2049 0772 0B43 orrs r3, r3, r1 + 2050 0774 5365 str r3, [r2, #84] + 2051 .L145: +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2052 .loc 1 1311 3 view .LVU559 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2053 .loc 1 1311 21 is_stmt 0 view .LVU560 + 2054 0776 2368 ldr r3, [r4] +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2055 .loc 1 1311 5 view .LVU561 + 2056 0778 13F0100F tst r3, #16 + 2057 077c 0CD0 beq .L147 +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2058 .loc 1 1314 5 is_stmt 1 view .LVU562 +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2059 .loc 1 1316 5 view .LVU563 +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2060 .loc 1 1316 23 is_stmt 0 view .LVU564 + 2061 077e D4F89430 ldr r3, [r4, #148] +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2062 .loc 1 1316 8 view .LVU565 + 2063 0782 B3F5807F cmp r3, #256 + 2064 0786 67D0 beq .L228 + 2065 .LVL213: + 2066 .L148: +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2067 .loc 1 1324 7 is_stmt 1 view .LVU566 + 2068 0788 864A ldr r2, .L241 + 2069 078a 936D ldr r3, [r2, #88] + 2070 078c 23F44073 bic r3, r3, #768 + 2071 0790 D4F89410 ldr r1, [r4, #148] + 2072 0794 0B43 orrs r3, r3, r1 + 2073 0796 9365 str r3, [r2, #88] + 2074 .L147: +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2075 .loc 1 1329 3 view .LVU567 +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2076 .loc 1 1329 21 is_stmt 0 view .LVU568 + 2077 0798 2368 ldr r3, [r4] +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2078 .loc 1 1329 5 view .LVU569 + 2079 079a 13F4002F tst r3, #524288 + 2080 079e 0BD0 beq .L149 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2081 .loc 1 1331 5 is_stmt 1 view .LVU570 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2082 .loc 1 1331 25 is_stmt 0 view .LVU571 + 2083 07a0 D4F8A030 ldr r3, [r4, #160] +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2084 .loc 1 1331 5 view .LVU572 + 2085 07a4 B3F5803F cmp r3, #65536 + 2086 07a8 6ED0 beq .L150 + 2087 07aa B3F5003F cmp r3, #131072 + 2088 07ae 61D0 beq .L151 + 2089 07b0 002B cmp r3, #0 + 2090 07b2 5AD0 beq .L229 + 2091 07b4 0126 movs r6, #1 + ARM GAS /tmp/ccSY6g1k.s page 107 + + + 2092 .LVL214: +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2093 .loc 1 1331 5 view .LVU573 + 2094 07b6 3546 mov r5, r6 + 2095 .LVL215: + 2096 .L149: +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2097 .loc 1 1370 3 is_stmt 1 view .LVU574 +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2098 .loc 1 1370 21 is_stmt 0 view .LVU575 + 2099 07b8 2368 ldr r3, [r4] +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2100 .loc 1 1370 5 view .LVU576 + 2101 07ba 13F4802F tst r3, #262144 + 2102 07be 0CD0 beq .L152 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2103 .loc 1 1373 5 is_stmt 1 view .LVU577 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2104 .loc 1 1373 25 is_stmt 0 view .LVU578 + 2105 07c0 D4F88430 ldr r3, [r4, #132] +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2106 .loc 1 1373 5 view .LVU579 + 2107 07c4 B3F5001F cmp r3, #2097152 + 2108 07c8 76D0 beq .L153 + 2109 07ca B3F5401F cmp r3, #3145728 + 2110 07ce 69D0 beq .L154 + 2111 07d0 B3F5801F cmp r3, #1048576 + 2112 07d4 61D0 beq .L230 + 2113 07d6 0126 movs r6, #1 + 2114 .LVL216: +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2115 .loc 1 1373 5 view .LVU580 + 2116 07d8 3546 mov r5, r6 + 2117 .LVL217: + 2118 .L152: +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2119 .loc 1 1413 3 is_stmt 1 view .LVU581 +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2120 .loc 1 1413 21 is_stmt 0 view .LVU582 + 2121 07da 2368 ldr r3, [r4] +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2122 .loc 1 1413 5 view .LVU583 + 2123 07dc 13F4803F tst r3, #65536 + 2124 07e0 07D0 beq .L155 +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2125 .loc 1 1416 5 is_stmt 1 view .LVU584 +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2126 .loc 1 1418 5 view .LVU585 +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2127 .loc 1 1418 25 is_stmt 0 view .LVU586 + 2128 07e2 E36C ldr r3, [r4, #76] +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2129 .loc 1 1418 5 view .LVU587 + 2130 07e4 002B cmp r3, #0 + 2131 07e6 70D0 beq .L156 + 2132 07e8 B3F5803F cmp r3, #65536 + 2133 07ec 7BD0 beq .L157 + ARM GAS /tmp/ccSY6g1k.s page 108 + + + 2134 07ee 0126 movs r6, #1 + 2135 .LVL218: +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2136 .loc 1 1418 5 view .LVU588 + 2137 07f0 3546 mov r5, r6 + 2138 .LVL219: + 2139 .L155: +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2140 .loc 1 1453 3 is_stmt 1 view .LVU589 +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2141 .loc 1 1453 21 is_stmt 0 view .LVU590 + 2142 07f2 2368 ldr r3, [r4] +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2143 .loc 1 1453 5 view .LVU591 + 2144 07f4 13F0005F tst r3, #536870912 + 2145 07f8 7DD1 bne .L231 + 2146 .LVL220: + 2147 .L159: +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2148 .loc 1 1463 3 is_stmt 1 view .LVU592 +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2149 .loc 1 1463 21 is_stmt 0 view .LVU593 + 2150 07fa 2368 ldr r3, [r4] +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2151 .loc 1 1463 5 view .LVU594 + 2152 07fc 13F4003F tst r3, #131072 + 2153 0800 00F08680 beq .L160 +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2154 .loc 1 1466 5 is_stmt 1 view .LVU595 +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2155 .loc 1 1466 25 is_stmt 0 view .LVU596 + 2156 0804 E36F ldr r3, [r4, #124] +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2157 .loc 1 1466 5 view .LVU597 + 2158 0806 B3F5807F cmp r3, #256 + 2159 080a 00F0BA80 beq .L161 + 2160 080e 7CD9 bls .L232 + 2161 0810 B3F5007F cmp r3, #512 + 2162 0814 03D0 beq .L163 + 2163 0816 B3F5407F cmp r3, #768 + 2164 081a 40F0B080 bne .L233 + 2165 .L163: +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2166 .loc 1 1494 5 is_stmt 1 view .LVU598 +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2167 .loc 1 1494 7 is_stmt 0 view .LVU599 + 2168 081e 002D cmp r5, #0 + 2169 0820 40F0B580 bne .L206 +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2170 .loc 1 1497 7 is_stmt 1 view .LVU600 + 2171 0824 5F4A ldr r2, .L241 + 2172 0826 536D ldr r3, [r2, #84] + 2173 0828 23F44073 bic r3, r3, #768 + 2174 082c E16F ldr r1, [r4, #124] + 2175 082e 0B43 orrs r3, r3, r1 + 2176 0830 5365 str r3, [r2, #84] + 2177 0832 6DE0 b .L160 + ARM GAS /tmp/ccSY6g1k.s page 109 + + + 2178 .L141: +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2179 .loc 1 1237 7 view .LVU601 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2180 .loc 1 1237 13 is_stmt 0 view .LVU602 + 2181 0834 0221 movs r1, #2 + 2182 0836 04F12400 add r0, r4, #36 + 2183 083a FFF7FEFF bl RCCEx_PLL3_Config + 2184 .LVL221: + 2185 083e 0546 mov r5, r0 + 2186 .LVL222: +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2187 .loc 1 1240 7 is_stmt 1 view .LVU603 + 2188 0840 65E7 b .L143 + 2189 .L197: +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2190 .loc 1 1240 7 is_stmt 0 view .LVU604 + 2191 0842 2E46 mov r6, r5 + 2192 .LVL223: +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2193 .loc 1 1240 7 view .LVU605 + 2194 0844 86E7 b .L140 + 2195 .LVL224: + 2196 .L227: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2197 .loc 1 1299 9 is_stmt 1 view .LVU606 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2198 .loc 1 1299 12 is_stmt 0 view .LVU607 + 2199 0846 0221 movs r1, #2 + 2200 0848 04F12400 add r0, r4, #36 + 2201 084c FFF7FEFF bl RCCEx_PLL3_Config + 2202 .LVL225: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2203 .loc 1 1299 11 view .LVU608 + 2204 0850 0028 cmp r0, #0 + 2205 0852 88D0 beq .L146 +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2206 .loc 1 1301 18 view .LVU609 + 2207 0854 0126 movs r6, #1 + 2208 .LVL226: +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2209 .loc 1 1301 18 view .LVU610 + 2210 0856 86E7 b .L146 + 2211 .LVL227: + 2212 .L228: +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2213 .loc 1 1318 7 is_stmt 1 view .LVU611 +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2214 .loc 1 1318 10 is_stmt 0 view .LVU612 + 2215 0858 0221 movs r1, #2 + 2216 085a 04F12400 add r0, r4, #36 + 2217 085e FFF7FEFF bl RCCEx_PLL3_Config + 2218 .LVL228: +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2219 .loc 1 1318 9 view .LVU613 + 2220 0862 0028 cmp r0, #0 + 2221 0864 90D0 beq .L148 + ARM GAS /tmp/ccSY6g1k.s page 110 + + +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2222 .loc 1 1320 16 view .LVU614 + 2223 0866 0126 movs r6, #1 + 2224 .LVL229: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2225 .loc 1 1320 16 view .LVU615 + 2226 0868 8EE7 b .L148 + 2227 .LVL230: + 2228 .L229: +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2229 .loc 1 1336 7 is_stmt 1 view .LVU616 +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2230 .loc 1 1336 13 is_stmt 0 view .LVU617 + 2231 086a 0021 movs r1, #0 + 2232 086c 201D adds r0, r4, #4 + 2233 086e FFF7FEFF bl RCCEx_PLL2_Config + 2234 .LVL231: + 2235 0872 0546 mov r5, r0 + 2236 .LVL232: +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2237 .loc 1 1339 7 is_stmt 1 view .LVU618 + 2238 .L151: +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2239 .loc 1 1357 5 view .LVU619 +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2240 .loc 1 1357 7 is_stmt 0 view .LVU620 + 2241 0874 7DB9 cbnz r5, .L201 +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2242 .loc 1 1360 7 is_stmt 1 view .LVU621 + 2243 0876 4B4A ldr r2, .L241 + 2244 0878 936D ldr r3, [r2, #88] + 2245 087a 23F44033 bic r3, r3, #196608 + 2246 087e D4F8A010 ldr r1, [r4, #160] + 2247 0882 0B43 orrs r3, r3, r1 + 2248 0884 9365 str r3, [r2, #88] + 2249 0886 97E7 b .L149 + 2250 .L150: +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2251 .loc 1 1342 7 view .LVU622 +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2252 .loc 1 1342 13 is_stmt 0 view .LVU623 + 2253 0888 0221 movs r1, #2 + 2254 088a 04F12400 add r0, r4, #36 + 2255 088e FFF7FEFF bl RCCEx_PLL3_Config + 2256 .LVL233: + 2257 0892 0546 mov r5, r0 + 2258 .LVL234: +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2259 .loc 1 1345 7 is_stmt 1 view .LVU624 + 2260 0894 EEE7 b .L151 + 2261 .L201: +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2262 .loc 1 1345 7 is_stmt 0 view .LVU625 + 2263 0896 2E46 mov r6, r5 + 2264 .LVL235: +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2265 .loc 1 1345 7 view .LVU626 + ARM GAS /tmp/ccSY6g1k.s page 111 + + + 2266 0898 8EE7 b .L149 + 2267 .LVL236: + 2268 .L230: +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2269 .loc 1 1377 7 is_stmt 1 view .LVU627 + 2270 089a 424A ldr r2, .L241 + 2271 089c D36A ldr r3, [r2, #44] + 2272 089e 43F40033 orr r3, r3, #131072 + 2273 08a2 D362 str r3, [r2, #44] +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2274 .loc 1 1380 7 view .LVU628 + 2275 .L154: +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2276 .loc 1 1399 5 view .LVU629 +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2277 .loc 1 1399 7 is_stmt 0 view .LVU630 + 2278 08a4 7DB9 cbnz r5, .L203 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2279 .loc 1 1402 7 is_stmt 1 view .LVU631 + 2280 08a6 3F4A ldr r2, .L241 + 2281 08a8 536D ldr r3, [r2, #84] + 2282 08aa 23F44013 bic r3, r3, #3145728 + 2283 08ae D4F88410 ldr r1, [r4, #132] + 2284 08b2 0B43 orrs r3, r3, r1 + 2285 08b4 5365 str r3, [r2, #84] + 2286 08b6 90E7 b .L152 + 2287 .L153: +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2288 .loc 1 1384 7 view .LVU632 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2289 .loc 1 1384 13 is_stmt 0 view .LVU633 + 2290 08b8 0121 movs r1, #1 + 2291 08ba 04F12400 add r0, r4, #36 + 2292 08be FFF7FEFF bl RCCEx_PLL3_Config + 2293 .LVL237: + 2294 08c2 0546 mov r5, r0 + 2295 .LVL238: +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2296 .loc 1 1387 7 is_stmt 1 view .LVU634 + 2297 08c4 EEE7 b .L154 + 2298 .L203: +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2299 .loc 1 1387 7 is_stmt 0 view .LVU635 + 2300 08c6 2E46 mov r6, r5 + 2301 .LVL239: +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2302 .loc 1 1387 7 view .LVU636 + 2303 08c8 87E7 b .L152 + 2304 .LVL240: + 2305 .L156: +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2306 .loc 1 1422 7 is_stmt 1 view .LVU637 + 2307 08ca 364A ldr r2, .L241 + 2308 08cc D36A ldr r3, [r2, #44] + 2309 08ce 43F40033 orr r3, r3, #131072 + 2310 08d2 D362 str r3, [r2, #44] +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 112 + + + 2311 .loc 1 1425 7 view .LVU638 + 2312 .L158: +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2313 .loc 1 1439 5 view .LVU639 +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2314 .loc 1 1439 7 is_stmt 0 view .LVU640 + 2315 08d4 6DB9 cbnz r5, .L204 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2316 .loc 1 1442 7 is_stmt 1 view .LVU641 + 2317 08d6 334A ldr r2, .L241 + 2318 08d8 D36C ldr r3, [r2, #76] + 2319 08da 23F48033 bic r3, r3, #65536 + 2320 08de E16C ldr r1, [r4, #76] + 2321 08e0 0B43 orrs r3, r3, r1 + 2322 08e2 D364 str r3, [r2, #76] + 2323 08e4 85E7 b .L155 + 2324 .L157: +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2325 .loc 1 1429 7 view .LVU642 +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2326 .loc 1 1429 13 is_stmt 0 view .LVU643 + 2327 08e6 0221 movs r1, #2 + 2328 08e8 201D adds r0, r4, #4 + 2329 08ea FFF7FEFF bl RCCEx_PLL2_Config + 2330 .LVL241: + 2331 08ee 0546 mov r5, r0 + 2332 .LVL242: +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2333 .loc 1 1432 7 is_stmt 1 view .LVU644 + 2334 08f0 F0E7 b .L158 + 2335 .L204: +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2336 .loc 1 1432 7 is_stmt 0 view .LVU645 + 2337 08f2 2E46 mov r6, r5 + 2338 .LVL243: +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2339 .loc 1 1432 7 view .LVU646 + 2340 08f4 7DE7 b .L155 + 2341 .LVL244: + 2342 .L231: +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2343 .loc 1 1455 5 is_stmt 1 view .LVU647 +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2344 .loc 1 1455 8 is_stmt 0 view .LVU648 + 2345 08f6 0221 movs r1, #2 + 2346 08f8 04F12400 add r0, r4, #36 + 2347 08fc FFF7FEFF bl RCCEx_PLL3_Config + 2348 .LVL245: +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2349 .loc 1 1455 7 view .LVU649 + 2350 0900 0028 cmp r0, #0 + 2351 0902 3FF47AAF beq .L159 +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2352 .loc 1 1457 13 view .LVU650 + 2353 0906 0126 movs r6, #1 + 2354 .LVL246: +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 113 + + + 2355 .loc 1 1457 13 view .LVU651 + 2356 0908 77E7 b .L159 + 2357 .LVL247: + 2358 .L232: +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2359 .loc 1 1466 5 view .LVU652 + 2360 090a 002B cmp r3, #0 + 2361 090c 87D0 beq .L163 + 2362 090e 0126 movs r6, #1 + 2363 .LVL248: + 2364 .L160: +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2365 .loc 1 1508 3 is_stmt 1 view .LVU653 +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2366 .loc 1 1508 21 is_stmt 0 view .LVU654 + 2367 0910 2368 ldr r3, [r4] +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2368 .loc 1 1508 5 view .LVU655 + 2369 0912 13F4801F tst r3, #1048576 + 2370 0916 06D0 beq .L164 +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2371 .loc 1 1511 5 is_stmt 1 view .LVU656 +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2372 .loc 1 1514 5 view .LVU657 + 2373 0918 224A ldr r2, .L241 + 2374 091a 136D ldr r3, [r2, #80] + 2375 091c 23F00043 bic r3, r3, #-2147483648 + 2376 0920 216F ldr r1, [r4, #112] + 2377 0922 0B43 orrs r3, r3, r1 + 2378 0924 1365 str r3, [r2, #80] + 2379 .L164: +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2380 .loc 1 1518 3 view .LVU658 +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2381 .loc 1 1518 21 is_stmt 0 view .LVU659 + 2382 0926 2368 ldr r3, [r4] +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2383 .loc 1 1518 5 view .LVU660 + 2384 0928 13F0805F tst r3, #268435456 + 2385 092c 07D0 beq .L165 +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2386 .loc 1 1521 5 is_stmt 1 view .LVU661 +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2387 .loc 1 1524 5 view .LVU662 + 2388 092e 1D4A ldr r2, .L241 + 2389 0930 1369 ldr r3, [r2, #16] + 2390 0932 23F48043 bic r3, r3, #16384 + 2391 0936 D4F8B410 ldr r1, [r4, #180] + 2392 093a 0B43 orrs r3, r3, r1 + 2393 093c 1361 str r3, [r2, #16] + 2394 .L165: +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2395 .loc 1 1528 3 view .LVU663 +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2396 .loc 1 1528 21 is_stmt 0 view .LVU664 + 2397 093e 2368 ldr r3, [r4] +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 114 + + + 2398 .loc 1 1528 5 view .LVU665 + 2399 0940 13F4001F tst r3, #2097152 + 2400 0944 06D0 beq .L166 +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2401 .loc 1 1531 5 is_stmt 1 view .LVU666 +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2402 .loc 1 1534 5 view .LVU667 + 2403 0946 174A ldr r2, .L241 + 2404 0948 136D ldr r3, [r2, #80] + 2405 094a 23F08073 bic r3, r3, #16777216 + 2406 094e A16E ldr r1, [r4, #104] + 2407 0950 0B43 orrs r3, r3, r1 + 2408 0952 1365 str r3, [r2, #80] + 2409 .L166: +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2410 .loc 1 1550 3 view .LVU668 +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2411 .loc 1 1550 21 is_stmt 0 view .LVU669 + 2412 0954 2368 ldr r3, [r4] +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2413 .loc 1 1550 5 view .LVU670 + 2414 0956 13F0804F tst r3, #1073741824 + 2415 095a 09D0 beq .L167 +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2416 .loc 1 1553 5 is_stmt 1 view .LVU671 +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2417 .loc 1 1556 5 view .LVU672 +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2418 .loc 1 1556 5 view .LVU673 + 2419 095c 114B ldr r3, .L241 + 2420 095e 1A69 ldr r2, [r3, #16] + 2421 0960 22F40042 bic r2, r2, #32768 + 2422 0964 1A61 str r2, [r3, #16] +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2423 .loc 1 1556 5 view .LVU674 + 2424 0966 1A69 ldr r2, [r3, #16] + 2425 0968 D4F8B810 ldr r1, [r4, #184] + 2426 096c 0A43 orrs r2, r2, r1 + 2427 096e 1A61 str r2, [r3, #16] + 2428 .L167: +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2429 .loc 1 1556 5 discriminator 1 view .LVU675 +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2430 .loc 1 1560 3 discriminator 1 view .LVU676 +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2431 .loc 1 1560 21 is_stmt 0 discriminator 1 view .LVU677 + 2432 0970 2368 ldr r3, [r4] +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2433 .loc 1 1560 5 discriminator 1 view .LVU678 + 2434 0972 002B cmp r3, #0 + 2435 0974 0DDB blt .L234 + 2436 .L168: +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2437 .loc 1 1569 3 is_stmt 1 view .LVU679 +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2438 .loc 1 1569 6 is_stmt 0 view .LVU680 + 2439 0976 06B1 cbz r6, .L169 + ARM GAS /tmp/ccSY6g1k.s page 115 + + +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2440 .loc 1 1573 10 view .LVU681 + 2441 0978 0126 movs r6, #1 + 2442 .LVL249: + 2443 .L169: +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2444 .loc 1 1574 1 view .LVU682 + 2445 097a 3046 mov r0, r6 + 2446 097c F8BD pop {r3, r4, r5, r6, r7, pc} + 2447 .LVL250: + 2448 .L233: +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2449 .loc 1 1466 5 view .LVU683 + 2450 097e 0126 movs r6, #1 + 2451 .LVL251: +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2452 .loc 1 1466 5 view .LVU684 + 2453 0980 C6E7 b .L160 + 2454 .LVL252: + 2455 .L161: +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2456 .loc 1 1470 7 is_stmt 1 view .LVU685 + 2457 0982 084A ldr r2, .L241 + 2458 0984 D36A ldr r3, [r2, #44] + 2459 0986 43F40033 orr r3, r3, #131072 + 2460 098a D362 str r3, [r2, #44] +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2461 .loc 1 1473 7 view .LVU686 + 2462 098c 47E7 b .L163 + 2463 .L206: +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2464 .loc 1 1473 7 is_stmt 0 view .LVU687 + 2465 098e 2E46 mov r6, r5 + 2466 .LVL253: +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2467 .loc 1 1473 7 view .LVU688 + 2468 0990 BEE7 b .L160 + 2469 .LVL254: + 2470 .L234: +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2471 .loc 1 1563 5 is_stmt 1 view .LVU689 +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2472 .loc 1 1566 5 view .LVU690 + 2473 0992 044A ldr r2, .L241 + 2474 0994 D36C ldr r3, [r2, #76] + 2475 0996 23F04053 bic r3, r3, #805306368 + 2476 099a 216D ldr r1, [r4, #80] + 2477 099c 0B43 orrs r3, r3, r1 + 2478 099e D364 str r3, [r2, #76] + 2479 09a0 E9E7 b .L168 + 2480 .L242: + 2481 09a2 00BF .align 2 + 2482 .L241: + 2483 09a4 00440258 .word 1476543488 + 2484 .cfi_endproc + 2485 .LFE141: + 2487 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits + ARM GAS /tmp/ccSY6g1k.s page 116 + + + 2488 .align 1 + 2489 .global HAL_RCCEx_GetPeriphCLKConfig + 2490 .syntax unified + 2491 .thumb + 2492 .thumb_func + 2493 .fpu fpv5-d16 + 2495 HAL_RCCEx_GetPeriphCLKConfig: + 2496 .LVL255: + 2497 .LFB142: +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ + 2498 .loc 1 1588 1 view -0 + 2499 .cfi_startproc + 2500 @ args = 0, pretend = 0, frame = 0 + 2501 @ frame_needed = 0, uses_anonymous_args = 0 + 2502 @ link register save eliminated. +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + 2503 .loc 1 1590 3 view .LVU692 +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + 2504 .loc 1 1590 39 is_stmt 0 view .LVU693 + 2505 0000 704B ldr r3, .L246 + 2506 0002 0360 str r3, [r0] +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ + 2507 .loc 1 1602 1 is_stmt 1 view .LVU694 +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ + 2508 .loc 1 1602 37 is_stmt 0 view .LVU695 + 2509 0004 0833 adds r3, r3, #8 + 2510 0006 0360 str r3, [r0] +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI3 */ + 2511 .loc 1 1611 3 is_stmt 1 view .LVU696 +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI3 */ + 2512 .loc 1 1611 39 is_stmt 0 view .LVU697 + 2513 0008 03F50073 add r3, r3, #512 + 2514 000c 0360 str r3, [r0] +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; + 2515 .loc 1 1614 3 is_stmt 1 view .LVU698 +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; + 2516 .loc 1 1614 39 is_stmt 0 view .LVU699 + 2517 000e 03F58063 add r3, r3, #1024 + 2518 0012 0360 str r3, [r0] +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI4 */ + 2519 .loc 1 1615 3 is_stmt 1 view .LVU700 +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* SAI4 */ + 2520 .loc 1 1615 39 is_stmt 0 view .LVU701 + 2521 0014 6FF05853 mvn r3, #905969664 + 2522 0018 0360 str r3, [r0] +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ + 2523 .loc 1 1621 3 is_stmt 1 view .LVU702 +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ + 2524 .loc 1 1621 39 is_stmt 0 view .LVU703 + 2525 001a 6FF05053 mvn r3, #872415232 + 2526 001e 0360 str r3, [r0] +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ + 2527 .loc 1 1627 3 is_stmt 1 view .LVU704 +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ + 2528 .loc 1 1627 39 is_stmt 0 view .LVU705 + 2529 0020 6FF01053 mvn r3, #603979776 + 2530 0024 0360 str r3, [r0] + ARM GAS /tmp/ccSY6g1k.s page 117 + + +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* LTDC */ + 2531 .loc 1 1630 3 is_stmt 1 view .LVU706 +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* LTDC */ + 2532 .loc 1 1630 39 is_stmt 0 view .LVU707 + 2533 0026 6FF08063 mvn r3, #67108864 + 2534 002a 0360 str r3, [r0] +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ + 2535 .loc 1 1637 3 is_stmt 1 view .LVU708 +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ + 2536 .loc 1 1637 46 is_stmt 0 view .LVU709 + 2537 002c 664B ldr r3, .L246+4 + 2538 002e 9A6A ldr r2, [r3, #40] +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ + 2539 .loc 1 1637 31 view .LVU710 + 2540 0030 C2F30552 ubfx r2, r2, #20, #6 +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ + 2541 .loc 1 1637 29 view .LVU711 + 2542 0034 4262 str r2, [r0, #36] +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ + 2543 .loc 1 1638 3 is_stmt 1 view .LVU712 +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ + 2544 .loc 1 1638 46 is_stmt 0 view .LVU713 + 2545 0036 1A6C ldr r2, [r3, #64] +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ + 2546 .loc 1 1638 31 view .LVU714 + 2547 0038 C2F30802 ubfx r2, r2, #0, #9 +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ + 2548 .loc 1 1638 99 view .LVU715 + 2549 003c 0132 adds r2, r2, #1 +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ + 2550 .loc 1 1638 29 view .LVU716 + 2551 003e 8262 str r2, [r0, #40] +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ + 2552 .loc 1 1639 3 is_stmt 1 view .LVU717 +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ + 2553 .loc 1 1639 46 is_stmt 0 view .LVU718 + 2554 0040 1A6C ldr r2, [r3, #64] +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ + 2555 .loc 1 1639 31 view .LVU719 + 2556 0042 C2F30662 ubfx r2, r2, #24, #7 +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ + 2557 .loc 1 1639 99 view .LVU720 + 2558 0046 0132 adds r2, r2, #1 +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ + 2559 .loc 1 1639 29 view .LVU721 + 2560 0048 4263 str r2, [r0, #52] +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ + 2561 .loc 1 1640 3 is_stmt 1 view .LVU722 +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ + 2562 .loc 1 1640 46 is_stmt 0 view .LVU723 + 2563 004a 1A6C ldr r2, [r3, #64] +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ + 2564 .loc 1 1640 31 view .LVU724 + 2565 004c C2F34622 ubfx r2, r2, #9, #7 +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ + 2566 .loc 1 1640 99 view .LVU725 + 2567 0050 0132 adds r2, r2, #1 + ARM GAS /tmp/ccSY6g1k.s page 118 + + +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ + 2568 .loc 1 1640 29 view .LVU726 + 2569 0052 C262 str r2, [r0, #44] +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3 + 2570 .loc 1 1641 3 is_stmt 1 view .LVU727 +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3 + 2571 .loc 1 1641 46 is_stmt 0 view .LVU728 + 2572 0054 1A6C ldr r2, [r3, #64] +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3 + 2573 .loc 1 1641 31 view .LVU729 + 2574 0056 C2F30642 ubfx r2, r2, #16, #7 +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3 + 2575 .loc 1 1641 99 view .LVU730 + 2576 005a 0132 adds r2, r2, #1 +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3 + 2577 .loc 1 1641 29 view .LVU731 + 2578 005c 0263 str r2, [r0, #48] +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFG + 2579 .loc 1 1642 3 is_stmt 1 view .LVU732 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFG + 2580 .loc 1 1642 48 is_stmt 0 view .LVU733 + 2581 005e DA6A ldr r2, [r3, #44] +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFG + 2582 .loc 1 1642 33 view .LVU734 + 2583 0060 C2F38122 ubfx r2, r2, #10, #2 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFG + 2584 .loc 1 1642 31 view .LVU735 + 2585 0064 8263 str r2, [r0, #56] +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2586 .loc 1 1643 3 is_stmt 1 view .LVU736 +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2587 .loc 1 1643 51 is_stmt 0 view .LVU737 + 2588 0066 DA6A ldr r2, [r3, #44] +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2589 .loc 1 1643 36 view .LVU738 + 2590 0068 C2F34022 ubfx r2, r2, #9, #1 +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2591 .loc 1 1643 34 view .LVU739 + 2592 006c C263 str r2, [r0, #60] +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ + 2593 .loc 1 1646 3 is_stmt 1 view .LVU740 +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ + 2594 .loc 1 1646 46 is_stmt 0 view .LVU741 + 2595 006e 9A6A ldr r2, [r3, #40] +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ + 2596 .loc 1 1646 31 view .LVU742 + 2597 0070 C2F30532 ubfx r2, r2, #12, #6 +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ + 2598 .loc 1 1646 29 view .LVU743 + 2599 0074 4260 str r2, [r0, #4] +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ + 2600 .loc 1 1647 3 is_stmt 1 view .LVU744 +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ + 2601 .loc 1 1647 46 is_stmt 0 view .LVU745 + 2602 0076 9A6B ldr r2, [r3, #56] +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ + 2603 .loc 1 1647 31 view .LVU746 + ARM GAS /tmp/ccSY6g1k.s page 119 + + + 2604 0078 C2F30802 ubfx r2, r2, #0, #9 +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ + 2605 .loc 1 1647 99 view .LVU747 + 2606 007c 0132 adds r2, r2, #1 +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ + 2607 .loc 1 1647 29 view .LVU748 + 2608 007e 8260 str r2, [r0, #8] +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ + 2609 .loc 1 1648 3 is_stmt 1 view .LVU749 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ + 2610 .loc 1 1648 46 is_stmt 0 view .LVU750 + 2611 0080 9A6B ldr r2, [r3, #56] +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ + 2612 .loc 1 1648 31 view .LVU751 + 2613 0082 C2F30662 ubfx r2, r2, #24, #7 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ + 2614 .loc 1 1648 99 view .LVU752 + 2615 0086 0132 adds r2, r2, #1 +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ + 2616 .loc 1 1648 29 view .LVU753 + 2617 0088 4261 str r2, [r0, #20] +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ + 2618 .loc 1 1649 3 is_stmt 1 view .LVU754 +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ + 2619 .loc 1 1649 46 is_stmt 0 view .LVU755 + 2620 008a 9A6B ldr r2, [r3, #56] +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ + 2621 .loc 1 1649 31 view .LVU756 + 2622 008c C2F34622 ubfx r2, r2, #9, #7 +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ + 2623 .loc 1 1649 99 view .LVU757 + 2624 0090 0132 adds r2, r2, #1 +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ + 2625 .loc 1 1649 29 view .LVU758 + 2626 0092 C260 str r2, [r0, #12] +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2 + 2627 .loc 1 1650 3 is_stmt 1 view .LVU759 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2 + 2628 .loc 1 1650 46 is_stmt 0 view .LVU760 + 2629 0094 9A6B ldr r2, [r3, #56] +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2 + 2630 .loc 1 1650 31 view .LVU761 + 2631 0096 C2F30642 ubfx r2, r2, #16, #7 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2 + 2632 .loc 1 1650 99 view .LVU762 + 2633 009a 0132 adds r2, r2, #1 +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2 + 2634 .loc 1 1650 29 view .LVU763 + 2635 009c 0261 str r2, [r0, #16] +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFG + 2636 .loc 1 1651 3 is_stmt 1 view .LVU764 +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFG + 2637 .loc 1 1651 48 is_stmt 0 view .LVU765 + 2638 009e DA6A ldr r2, [r3, #44] +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFG + 2639 .loc 1 1651 33 view .LVU766 + 2640 00a0 C2F38112 ubfx r2, r2, #6, #2 + ARM GAS /tmp/ccSY6g1k.s page 120 + + +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFG + 2641 .loc 1 1651 31 view .LVU767 + 2642 00a4 8261 str r2, [r0, #24] +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2643 .loc 1 1652 3 is_stmt 1 view .LVU768 +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2644 .loc 1 1652 51 is_stmt 0 view .LVU769 + 2645 00a6 DA6A ldr r2, [r3, #44] +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2646 .loc 1 1652 36 view .LVU770 + 2647 00a8 C2F34012 ubfx r2, r2, #5, #1 +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2648 .loc 1 1652 34 view .LVU771 + 2649 00ac C261 str r2, [r0, #28] +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + 2650 .loc 1 1655 3 is_stmt 1 view .LVU772 +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + 2651 .loc 1 1655 47 is_stmt 0 view .LVU773 + 2652 00ae 5A6D ldr r2, [r3, #84] + 2653 00b0 02F03802 and r2, r2, #56 +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + 2654 .loc 1 1655 45 view .LVU774 + 2655 00b4 8267 str r2, [r0, #120] +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source --------------------------------------------*/ + 2656 .loc 1 1657 3 is_stmt 1 view .LVU775 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source --------------------------------------------*/ + 2657 .loc 1 1657 47 is_stmt 0 view .LVU776 + 2658 00b6 5A6D ldr r2, [r3, #84] + 2659 00b8 02F00702 and r2, r2, #7 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source --------------------------------------------*/ + 2660 .loc 1 1657 45 view .LVU777 + 2661 00bc 4267 str r2, [r0, #116] +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(I2C5) + 2662 .loc 1 1659 3 is_stmt 1 view .LVU778 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(I2C5) + 2663 .loc 1 1659 47 is_stmt 0 view .LVU779 + 2664 00be 9A6D ldr r2, [r3, #88] + 2665 00c0 02F00702 and r2, r2, #7 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(I2C5) + 2666 .loc 1 1659 45 view .LVU780 + 2667 00c4 C0F89020 str r2, [r0, #144] +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ + 2668 .loc 1 1665 3 is_stmt 1 view .LVU781 +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ + 2669 .loc 1 1665 47 is_stmt 0 view .LVU782 + 2670 00c8 5A6D ldr r2, [r3, #84] + 2671 00ca 02F44052 and r2, r2, #12288 +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*I2C5*/ + 2672 .loc 1 1665 45 view .LVU783 + 2673 00ce C0F88020 str r2, [r0, #128] +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM2 clock source ---------------------------------------------*/ + 2674 .loc 1 1668 3 is_stmt 1 view .LVU784 +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM2 clock source ---------------------------------------------*/ + 2675 .loc 1 1668 47 is_stmt 0 view .LVU785 + 2676 00d2 5A6D ldr r2, [r3, #84] + 2677 00d4 02F0E042 and r2, r2, #1879048192 +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM2 clock source ---------------------------------------------*/ + ARM GAS /tmp/ccSY6g1k.s page 121 + + + 2678 .loc 1 1668 45 view .LVU786 + 2679 00d8 C0F88C20 str r2, [r0, #140] +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + 2680 .loc 1 1670 3 is_stmt 1 view .LVU787 +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + 2681 .loc 1 1670 47 is_stmt 0 view .LVU788 + 2682 00dc 9A6D ldr r2, [r3, #88] + 2683 00de 02F4E052 and r2, r2, #7168 +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + 2684 .loc 1 1670 45 view .LVU789 + 2685 00e2 C0F89820 str r2, [r0, #152] +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI1 clock source -----------------------------------------------*/ + 2686 .loc 1 1672 3 is_stmt 1 view .LVU790 +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI1 clock source -----------------------------------------------*/ + 2687 .loc 1 1672 47 is_stmt 0 view .LVU791 + 2688 00e6 9A6D ldr r2, [r3, #88] + 2689 00e8 02F46042 and r2, r2, #57344 +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI1 clock source -----------------------------------------------*/ + 2690 .loc 1 1672 45 view .LVU792 + 2691 00ec C0F89C20 str r2, [r0, #156] +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) + 2692 .loc 1 1674 3 is_stmt 1 view .LVU793 +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) + 2693 .loc 1 1674 47 is_stmt 0 view .LVU794 + 2694 00f0 1A6D ldr r2, [r3, #80] + 2695 00f2 02F00702 and r2, r2, #7 +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(SAI3) + 2696 .loc 1 1674 45 view .LVU795 + 2697 00f6 4265 str r2, [r0, #84] +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI3*/ + 2698 .loc 1 1677 3 is_stmt 1 view .LVU796 +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI3*/ + 2699 .loc 1 1677 47 is_stmt 0 view .LVU797 + 2700 00f8 1A6D ldr r2, [r3, #80] + 2701 00fa 02F4E072 and r2, r2, #448 +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI3*/ + 2702 .loc 1 1677 45 view .LVU798 + 2703 00fe 8265 str r2, [r0, #88] +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI4B clock source ----------------------------------------------*/ + 2704 .loc 1 1689 3 is_stmt 1 view .LVU799 +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI4B clock source ----------------------------------------------*/ + 2705 .loc 1 1689 47 is_stmt 0 view .LVU800 + 2706 0100 9A6D ldr r2, [r3, #88] + 2707 0102 02F46002 and r2, r2, #14680064 +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SAI4B clock source ----------------------------------------------*/ + 2708 .loc 1 1689 45 view .LVU801 + 2709 0106 C0F8A420 str r2, [r0, #164] +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI4*/ + 2710 .loc 1 1691 3 is_stmt 1 view .LVU802 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI4*/ + 2711 .loc 1 1691 47 is_stmt 0 view .LVU803 + 2712 010a 9A6D ldr r2, [r3, #88] + 2713 010c 02F0E062 and r2, r2, #117440512 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /*SAI4*/ + 2714 .loc 1 1691 45 view .LVU804 + 2715 0110 C0F8A820 str r2, [r0, #168] +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USB clock source ------------------------------------------------*/ + ARM GAS /tmp/ccSY6g1k.s page 122 + + + 2716 .loc 1 1694 3 is_stmt 1 view .LVU805 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USB clock source ------------------------------------------------*/ + 2717 .loc 1 1694 47 is_stmt 0 view .LVU806 + 2718 0114 1A6F ldr r2, [r3, #112] + 2719 0116 02F44072 and r2, r2, #768 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the USB clock source ------------------------------------------------*/ + 2720 .loc 1 1694 45 view .LVU807 + 2721 011a C0F8B020 str r2, [r0, #176] +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SDMMC clock source ----------------------------------------------*/ + 2722 .loc 1 1696 3 is_stmt 1 view .LVU808 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SDMMC clock source ----------------------------------------------*/ + 2723 .loc 1 1696 47 is_stmt 0 view .LVU809 + 2724 011e 5A6D ldr r2, [r3, #84] + 2725 0120 02F44012 and r2, r2, #3145728 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SDMMC clock source ----------------------------------------------*/ + 2726 .loc 1 1696 45 view .LVU810 + 2727 0124 C0F88420 str r2, [r0, #132] +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the RNG clock source ------------------------------------------------*/ + 2728 .loc 1 1698 3 is_stmt 1 view .LVU811 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the RNG clock source ------------------------------------------------*/ + 2729 .loc 1 1698 47 is_stmt 0 view .LVU812 + 2730 0128 DA6C ldr r2, [r3, #76] + 2731 012a 02F48032 and r2, r2, #65536 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the RNG clock source ------------------------------------------------*/ + 2732 .loc 1 1698 45 view .LVU813 + 2733 012e C264 str r2, [r0, #76] +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(HRTIM1) + 2734 .loc 1 1700 3 is_stmt 1 view .LVU814 +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(HRTIM1) + 2735 .loc 1 1700 47 is_stmt 0 view .LVU815 + 2736 0130 5A6D ldr r2, [r3, #84] + 2737 0132 02F44072 and r2, r2, #768 +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(HRTIM1) + 2738 .loc 1 1700 45 view .LVU816 + 2739 0136 C267 str r2, [r0, #124] +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ + 2740 .loc 1 1703 3 is_stmt 1 view .LVU817 +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ + 2741 .loc 1 1703 47 is_stmt 0 view .LVU818 + 2742 0138 1A69 ldr r2, [r3, #16] + 2743 013a 02F48042 and r2, r2, #16384 +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* HRTIM1 */ + 2744 .loc 1 1703 45 view .LVU819 + 2745 013e C0F8B420 str r2, [r0, #180] +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SWPMI1 clock source ---------------------------------------------*/ + 2746 .loc 1 1706 3 is_stmt 1 view .LVU820 +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SWPMI1 clock source ---------------------------------------------*/ + 2747 .loc 1 1706 47 is_stmt 0 view .LVU821 + 2748 0142 9A6D ldr r2, [r3, #88] + 2749 0144 02F44032 and r2, r2, #196608 +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SWPMI1 clock source ---------------------------------------------*/ + 2750 .loc 1 1706 45 view .LVU822 + 2751 0148 C0F8A020 str r2, [r0, #160] +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the DFSDM1 clock source ---------------------------------------------*/ + 2752 .loc 1 1708 3 is_stmt 1 view .LVU823 +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the DFSDM1 clock source ---------------------------------------------*/ + 2753 .loc 1 1708 47 is_stmt 0 view .LVU824 + ARM GAS /tmp/ccSY6g1k.s page 123 + + + 2754 014c 1A6D ldr r2, [r3, #80] + 2755 014e 02F00042 and r2, r2, #-2147483648 +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the DFSDM1 clock source ---------------------------------------------*/ + 2756 .loc 1 1708 45 view .LVU825 + 2757 0152 0267 str r2, [r0, #112] +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DFSDM2_BASE) + 2758 .loc 1 1710 3 is_stmt 1 view .LVU826 +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DFSDM2_BASE) + 2759 .loc 1 1710 47 is_stmt 0 view .LVU827 + 2760 0154 1A6D ldr r2, [r3, #80] + 2761 0156 02F08072 and r2, r2, #16777216 +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(DFSDM2_BASE) + 2762 .loc 1 1710 45 view .LVU828 + 2763 015a 8266 str r2, [r0, #104] +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI1/2/3 clock source -------------------------------------------*/ + 2764 .loc 1 1716 3 is_stmt 1 view .LVU829 +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI1/2/3 clock source -------------------------------------------*/ + 2765 .loc 1 1716 47 is_stmt 0 view .LVU830 + 2766 015c 1A6D ldr r2, [r3, #80] + 2767 015e 02F44012 and r2, r2, #3145728 +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI1/2/3 clock source -------------------------------------------*/ + 2768 .loc 1 1716 45 view .LVU831 + 2769 0162 4266 str r2, [r0, #100] +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI4/5 clock source ---------------------------------------------*/ + 2770 .loc 1 1718 3 is_stmt 1 view .LVU832 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI4/5 clock source ---------------------------------------------*/ + 2771 .loc 1 1718 47 is_stmt 0 view .LVU833 + 2772 0164 1A6D ldr r2, [r3, #80] + 2773 0166 02F4E042 and r2, r2, #28672 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI4/5 clock source ---------------------------------------------*/ + 2774 .loc 1 1718 45 view .LVU834 + 2775 016a C265 str r2, [r0, #92] +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI6 clock source -----------------------------------------------*/ + 2776 .loc 1 1720 3 is_stmt 1 view .LVU835 +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI6 clock source -----------------------------------------------*/ + 2777 .loc 1 1720 47 is_stmt 0 view .LVU836 + 2778 016c 1A6D ldr r2, [r3, #80] + 2779 016e 02F4E022 and r2, r2, #458752 +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the SPI6 clock source -----------------------------------------------*/ + 2780 .loc 1 1720 45 view .LVU837 + 2781 0172 0266 str r2, [r0, #96] +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FDCAN clock source ----------------------------------------------*/ + 2782 .loc 1 1722 3 is_stmt 1 view .LVU838 +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FDCAN clock source ----------------------------------------------*/ + 2783 .loc 1 1722 47 is_stmt 0 view .LVU839 + 2784 0174 9A6D ldr r2, [r3, #88] + 2785 0176 02F0E042 and r2, r2, #1879048192 +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FDCAN clock source ----------------------------------------------*/ + 2786 .loc 1 1722 45 view .LVU840 + 2787 017a C0F8AC20 str r2, [r0, #172] +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the CEC clock source ------------------------------------------------*/ + 2788 .loc 1 1724 3 is_stmt 1 view .LVU841 +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the CEC clock source ------------------------------------------------*/ + 2789 .loc 1 1724 47 is_stmt 0 view .LVU842 + 2790 017e 1A6D ldr r2, [r3, #80] + 2791 0180 02F04052 and r2, r2, #805306368 +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the CEC clock source ------------------------------------------------*/ + ARM GAS /tmp/ccSY6g1k.s page 124 + + + 2792 .loc 1 1724 45 view .LVU843 + 2793 0184 C266 str r2, [r0, #108] +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FMC clock source ------------------------------------------------*/ + 2794 .loc 1 1726 3 is_stmt 1 view .LVU844 +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FMC clock source ------------------------------------------------*/ + 2795 .loc 1 1726 47 is_stmt 0 view .LVU845 + 2796 0186 5A6D ldr r2, [r3, #84] + 2797 0188 02F44002 and r2, r2, #12582912 +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get the FMC clock source ------------------------------------------------*/ + 2798 .loc 1 1726 45 view .LVU846 + 2799 018c C0F88820 str r2, [r0, #136] +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(QUADSPI) + 2800 .loc 1 1728 3 is_stmt 1 view .LVU847 +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(QUADSPI) + 2801 .loc 1 1728 47 is_stmt 0 view .LVU848 + 2802 0190 DA6C ldr r2, [r3, #76] + 2803 0192 02F00302 and r2, r2, #3 +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(QUADSPI) + 2804 .loc 1 1728 45 view .LVU849 + 2805 0196 4264 str r2, [r0, #68] +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ + 2806 .loc 1 1731 3 is_stmt 1 view .LVU850 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ + 2807 .loc 1 1731 47 is_stmt 0 view .LVU851 + 2808 0198 DA6C ldr r2, [r3, #76] + 2809 019a 02F03002 and r2, r2, #48 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* QUADSPI */ + 2810 .loc 1 1731 45 view .LVU852 + 2811 019e 8264 str r2, [r0, #72] +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2812 .loc 1 1744 3 is_stmt 1 view .LVU853 +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2813 .loc 1 1744 47 is_stmt 0 view .LVU854 + 2814 01a0 DA6C ldr r2, [r3, #76] + 2815 01a2 02F04052 and r2, r2, #805306368 +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2816 .loc 1 1744 45 view .LVU855 + 2817 01a6 0265 str r2, [r0, #80] +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2818 .loc 1 1747 3 is_stmt 1 view .LVU856 +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2819 .loc 1 1747 11 is_stmt 0 view .LVU857 + 2820 01a8 1B69 ldr r3, [r3, #16] +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2821 .loc 1 1747 6 view .LVU858 + 2822 01aa 13F4004F tst r3, #32768 + 2823 01ae 03D1 bne .L244 +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2824 .loc 1 1749 5 is_stmt 1 view .LVU859 +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2825 .loc 1 1749 37 is_stmt 0 view .LVU860 + 2826 01b0 0023 movs r3, #0 + 2827 01b2 C0F8B830 str r3, [r0, #184] + 2828 01b6 7047 bx lr + 2829 .L244: +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2830 .loc 1 1753 5 is_stmt 1 view .LVU861 + ARM GAS /tmp/ccSY6g1k.s page 125 + + +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 2831 .loc 1 1753 37 is_stmt 0 view .LVU862 + 2832 01b8 4FF40043 mov r3, #32768 + 2833 01bc C0F8B830 str r3, [r0, #184] +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2834 .loc 1 1755 1 view .LVU863 + 2835 01c0 7047 bx lr + 2836 .L247: + 2837 01c2 00BF .align 2 + 2838 .L246: + 2839 01c4 F7F1FFC9 .word -905973257 + 2840 01c8 00440258 .word 1476543488 + 2841 .cfi_endproc + 2842 .LFE142: + 2844 .section .text.HAL_RCCEx_GetD1PCLK1Freq,"ax",%progbits + 2845 .align 1 + 2846 .global HAL_RCCEx_GetD1PCLK1Freq + 2847 .syntax unified + 2848 .thumb + 2849 .thumb_func + 2850 .fpu fpv5-d16 + 2852 HAL_RCCEx_GetD1PCLK1Freq: + 2853 .LFB144: +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_D1CFGR_D1PPRE) + 2854 .loc 1 2458 1 is_stmt 1 view -0 + 2855 .cfi_startproc + 2856 @ args = 0, pretend = 0, frame = 0 + 2857 @ frame_needed = 0, uses_anonymous_args = 0 + 2858 0000 08B5 push {r3, lr} + 2859 .LCFI5: + 2860 .cfi_def_cfa_offset 8 + 2861 .cfi_offset 3, -8 + 2862 .cfi_offset 14, -4 +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2863 .loc 1 2461 3 view .LVU865 +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2864 .loc 1 2461 11 is_stmt 0 view .LVU866 + 2865 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2866 .LVL256: +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2867 .loc 1 2461 58 view .LVU867 + 2868 0006 054B ldr r3, .L250 + 2869 0008 9B69 ldr r3, [r3, #24] +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2870 .loc 1 2461 87 view .LVU868 + 2871 000a C3F30213 ubfx r3, r3, #4, #3 +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2872 .loc 1 2461 53 view .LVU869 + 2873 000e 044A ldr r2, .L250+4 + 2874 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2875 .loc 1 2461 113 view .LVU870 + 2876 0012 03F01F03 and r3, r3, #31 +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2877 .loc 1 2466 1 view .LVU871 + 2878 0016 D840 lsrs r0, r0, r3 + 2879 0018 08BD pop {r3, pc} + ARM GAS /tmp/ccSY6g1k.s page 126 + + + 2880 .L251: + 2881 001a 00BF .align 2 + 2882 .L250: + 2883 001c 00440258 .word 1476543488 + 2884 0020 00000000 .word D1CorePrescTable + 2885 .cfi_endproc + 2886 .LFE144: + 2888 .section .text.HAL_RCCEx_GetD3PCLK1Freq,"ax",%progbits + 2889 .align 1 + 2890 .global HAL_RCCEx_GetD3PCLK1Freq + 2891 .syntax unified + 2892 .thumb + 2893 .thumb_func + 2894 .fpu fpv5-d16 + 2896 HAL_RCCEx_GetD3PCLK1Freq: + 2897 .LFB145: +2475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #if defined(RCC_D3CFGR_D3PPRE) + 2898 .loc 1 2475 1 is_stmt 1 view -0 + 2899 .cfi_startproc + 2900 @ args = 0, pretend = 0, frame = 0 + 2901 @ frame_needed = 0, uses_anonymous_args = 0 + 2902 0000 08B5 push {r3, lr} + 2903 .LCFI6: + 2904 .cfi_def_cfa_offset 8 + 2905 .cfi_offset 3, -8 + 2906 .cfi_offset 14, -4 +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2907 .loc 1 2478 3 view .LVU873 +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2908 .loc 1 2478 11 is_stmt 0 view .LVU874 + 2909 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2910 .LVL257: +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2911 .loc 1 2478 58 view .LVU875 + 2912 0006 054B ldr r3, .L254 + 2913 0008 1B6A ldr r3, [r3, #32] +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2914 .loc 1 2478 87 view .LVU876 + 2915 000a C3F30213 ubfx r3, r3, #4, #3 +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2916 .loc 1 2478 53 view .LVU877 + 2917 000e 044A ldr r2, .L254+4 + 2918 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 2919 .loc 1 2478 113 view .LVU878 + 2920 0012 03F01F03 and r3, r3, #31 +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** + 2921 .loc 1 2483 1 view .LVU879 + 2922 0016 D840 lsrs r0, r0, r3 + 2923 0018 08BD pop {r3, pc} + 2924 .L255: + 2925 001a 00BF .align 2 + 2926 .L254: + 2927 001c 00440258 .word 1476543488 + 2928 0020 00000000 .word D1CorePrescTable + 2929 .cfi_endproc + 2930 .LFE145: + ARM GAS /tmp/ccSY6g1k.s page 127 + + + 2932 .section .text.HAL_RCCEx_GetPLL2ClockFreq,"ax",%progbits + 2933 .align 1 + 2934 .global HAL_RCCEx_GetPLL2ClockFreq + 2935 .syntax unified + 2936 .thumb + 2937 .thumb_func + 2938 .fpu fpv5-d16 + 2940 HAL_RCCEx_GetPLL2ClockFreq: + 2941 .LVL258: + 2942 .LFB146: +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll2m, pll2fracen, hsivalue; + 2943 .loc 1 2499 1 is_stmt 1 view -0 + 2944 .cfi_startproc + 2945 @ args = 0, pretend = 0, frame = 0 + 2946 @ frame_needed = 0, uses_anonymous_args = 0 +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll2m, pll2fracen, hsivalue; + 2947 .loc 1 2499 1 is_stmt 0 view .LVU881 + 2948 0000 10B5 push {r4, lr} + 2949 .LCFI7: + 2950 .cfi_def_cfa_offset 8 + 2951 .cfi_offset 4, -8 + 2952 .cfi_offset 14, -4 +2500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** float_t fracn2, pll2vco; + 2953 .loc 1 2500 3 is_stmt 1 view .LVU882 +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2954 .loc 1 2501 3 view .LVU883 +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); + 2955 .loc 1 2506 3 view .LVU884 +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); + 2956 .loc 1 2506 19 is_stmt 0 view .LVU885 + 2957 0002 774A ldr r2, .L266 + 2958 0004 916A ldr r1, [r2, #40] + 2959 .LVL259: +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + 2960 .loc 1 2507 3 is_stmt 1 view .LVU886 +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + 2961 .loc 1 2507 16 is_stmt 0 view .LVU887 + 2962 0006 946A ldr r4, [r2, #40] +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + 2963 .loc 1 2507 9 view .LVU888 + 2964 0008 C4F3053E ubfx lr, r4, #12, #6 + 2965 .LVL260: +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); + 2966 .loc 1 2508 3 is_stmt 1 view .LVU889 +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); + 2967 .loc 1 2508 20 is_stmt 0 view .LVU890 + 2968 000c D36A ldr r3, [r2, #44] +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); + 2969 .loc 1 2508 14 view .LVU891 + 2970 000e C3F3001C ubfx ip, r3, #4, #1 + 2971 .LVL261: +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2972 .loc 1 2509 3 is_stmt 1 view .LVU892 +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2973 .loc 1 2509 48 is_stmt 0 view .LVU893 + 2974 0012 D36B ldr r3, [r2, #60] +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 128 + + + 2975 .loc 1 2509 83 view .LVU894 + 2976 0014 C3F3CC03 ubfx r3, r3, #3, #13 +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 2977 .loc 1 2509 20 view .LVU895 + 2978 0018 0CFB03F3 mul r3, ip, r3 + 2979 .LVL262: +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2980 .loc 1 2511 3 is_stmt 1 view .LVU896 +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2981 .loc 1 2511 6 is_stmt 0 view .LVU897 + 2982 001c 14F47C3F tst r4, #258048 + 2983 0020 00F0D880 beq .L257 + 2984 0024 01F00301 and r1, r1, #3 + 2985 .LVL263: +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2986 .loc 1 2511 6 view .LVU898 + 2987 0028 07EE903A vmov s15, r3 @ int + 2988 002c F8EE677A vcvt.f32.u32 s15, s15 +2513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 2989 .loc 1 2513 5 is_stmt 1 view .LVU899 + 2990 0030 0129 cmp r1, #1 + 2991 0032 65D0 beq .L258 + 2992 0034 0229 cmp r1, #2 + 2993 0036 00F0B080 beq .L259 + 2994 003a E1B1 cbz r1, .L265 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 2995 .loc 1 2538 7 view .LVU900 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 2996 .loc 1 2538 39 is_stmt 0 view .LVU901 + 2997 003c 07EE10EA vmov s14, lr @ int + 2998 0040 B8EE477A vcvt.f32.u32 s14, s14 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 2999 .loc 1 2538 37 view .LVU902 + 3000 0044 9FED676A vldr.32 s12, .L266+4 + 3001 0048 C6EE076A vdiv.f32 s13, s12, s14 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3002 .loc 1 2538 81 view .LVU903 + 3003 004c 644B ldr r3, .L266 + 3004 .LVL264: +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3005 .loc 1 2538 81 view .LVU904 + 3006 004e 9B6B ldr r3, [r3, #56] +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3007 .loc 1 2538 67 view .LVU905 + 3008 0050 C3F30803 ubfx r3, r3, #0, #9 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3009 .loc 1 2538 58 view .LVU906 + 3010 0054 07EE103A vmov s14, r3 @ int + 3011 0058 B8EE477A vcvt.f32.u32 s14, s14 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3012 .loc 1 2538 120 view .LVU907 + 3013 005c 9FED626A vldr.32 s12, .L266+8 + 3014 0060 67EE867A vmul.f32 s15, s15, s12 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3015 .loc 1 2538 111 view .LVU908 + 3016 0064 77EE277A vadd.f32 s15, s14, s15 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 129 + + + 3017 .loc 1 2538 138 view .LVU909 + 3018 0068 B7EE007A vmov.f32 s14, #1.0e+0 + 3019 006c 77EE877A vadd.f32 s15, s15, s14 +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3020 .loc 1 2538 15 view .LVU910 + 3021 0070 66EEA76A vmul.f32 s13, s13, s15 + 3022 .LVL265: +2539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3023 .loc 1 2539 7 is_stmt 1 view .LVU911 + 3024 0074 60E0 b .L262 + 3025 .LVL266: + 3026 .L265: +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3027 .loc 1 2518 7 view .LVU912 +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3028 .loc 1 2518 11 is_stmt 0 view .LVU913 + 3029 0076 1368 ldr r3, [r2] + 3030 .LVL267: +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3031 .loc 1 2518 10 view .LVU914 + 3032 0078 13F0200F tst r3, #32 + 3033 007c 23D0 beq .L261 +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ + 3034 .loc 1 2520 9 is_stmt 1 view .LVU915 +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ + 3035 .loc 1 2520 35 is_stmt 0 view .LVU916 + 3036 007e 1146 mov r1, r2 + 3037 .LVL268: +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ + 3038 .loc 1 2520 35 view .LVU917 + 3039 0080 1268 ldr r2, [r2] +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ + 3040 .loc 1 2520 62 view .LVU918 + 3041 0082 C2F3C102 ubfx r2, r2, #3, #2 +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_ + 3042 .loc 1 2520 18 view .LVU919 + 3043 0086 594B ldr r3, .L266+12 + 3044 0088 D340 lsrs r3, r3, r2 + 3045 .LVL269: +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3046 .loc 1 2521 9 is_stmt 1 view .LVU920 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3047 .loc 1 2521 21 is_stmt 0 view .LVU921 + 3048 008a 07EE103A vmov s14, r3 @ int + 3049 008e B8EE477A vcvt.f32.u32 s14, s14 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3050 .loc 1 2521 41 view .LVU922 + 3051 0092 06EE90EA vmov s13, lr @ int + 3052 0096 B8EE666A vcvt.f32.u32 s12, s13 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3053 .loc 1 2521 39 view .LVU923 + 3054 009a C7EE066A vdiv.f32 s13, s14, s12 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3055 .loc 1 2521 83 view .LVU924 + 3056 009e 8B6B ldr r3, [r1, #56] + 3057 .LVL270: +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 130 + + + 3058 .loc 1 2521 69 view .LVU925 + 3059 00a0 C3F30803 ubfx r3, r3, #0, #9 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3060 .loc 1 2521 60 view .LVU926 + 3061 00a4 07EE103A vmov s14, r3 @ int + 3062 00a8 B8EE477A vcvt.f32.u32 s14, s14 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3063 .loc 1 2521 122 view .LVU927 + 3064 00ac 9FED4E6A vldr.32 s12, .L266+8 + 3065 00b0 67EE867A vmul.f32 s15, s15, s12 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3066 .loc 1 2521 113 view .LVU928 + 3067 00b4 77EE277A vadd.f32 s15, s14, s15 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3068 .loc 1 2521 140 view .LVU929 + 3069 00b8 B7EE007A vmov.f32 s14, #1.0e+0 + 3070 00bc 77EE877A vadd.f32 s15, s15, s14 +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3071 .loc 1 2521 17 view .LVU930 + 3072 00c0 66EEA76A vmul.f32 s13, s13, s15 + 3073 .LVL271: +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3074 .loc 1 2521 17 view .LVU931 + 3075 00c4 38E0 b .L262 + 3076 .LVL272: + 3077 .L261: +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3078 .loc 1 2525 9 is_stmt 1 view .LVU932 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3079 .loc 1 2525 41 is_stmt 0 view .LVU933 + 3080 00c6 07EE10EA vmov s14, lr @ int + 3081 00ca B8EE477A vcvt.f32.u32 s14, s14 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3082 .loc 1 2525 39 view .LVU934 + 3083 00ce 9FED486A vldr.32 s12, .L266+16 + 3084 00d2 C6EE076A vdiv.f32 s13, s12, s14 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3085 .loc 1 2525 83 view .LVU935 + 3086 00d6 424B ldr r3, .L266 + 3087 00d8 9B6B ldr r3, [r3, #56] +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3088 .loc 1 2525 69 view .LVU936 + 3089 00da C3F30803 ubfx r3, r3, #0, #9 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3090 .loc 1 2525 60 view .LVU937 + 3091 00de 07EE103A vmov s14, r3 @ int + 3092 00e2 B8EE477A vcvt.f32.u32 s14, s14 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3093 .loc 1 2525 122 view .LVU938 + 3094 00e6 9FED406A vldr.32 s12, .L266+8 + 3095 00ea 67EE867A vmul.f32 s15, s15, s12 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3096 .loc 1 2525 113 view .LVU939 + 3097 00ee 77EE277A vadd.f32 s15, s14, s15 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3098 .loc 1 2525 140 view .LVU940 + 3099 00f2 B7EE007A vmov.f32 s14, #1.0e+0 + ARM GAS /tmp/ccSY6g1k.s page 131 + + + 3100 00f6 77EE877A vadd.f32 s15, s15, s14 +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3101 .loc 1 2525 17 view .LVU941 + 3102 00fa 66EEA76A vmul.f32 s13, s13, s15 + 3103 .LVL273: +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3104 .loc 1 2525 17 view .LVU942 + 3105 00fe 1BE0 b .L262 + 3106 .LVL274: + 3107 .L258: +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3108 .loc 1 2530 7 is_stmt 1 view .LVU943 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3109 .loc 1 2530 39 is_stmt 0 view .LVU944 + 3110 0100 07EE10EA vmov s14, lr @ int + 3111 0104 B8EE477A vcvt.f32.u32 s14, s14 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3112 .loc 1 2530 37 view .LVU945 + 3113 0108 9FED366A vldr.32 s12, .L266+4 + 3114 010c C6EE076A vdiv.f32 s13, s12, s14 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3115 .loc 1 2530 81 view .LVU946 + 3116 0110 334B ldr r3, .L266 + 3117 .LVL275: +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3118 .loc 1 2530 81 view .LVU947 + 3119 0112 9B6B ldr r3, [r3, #56] +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3120 .loc 1 2530 67 view .LVU948 + 3121 0114 C3F30803 ubfx r3, r3, #0, #9 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3122 .loc 1 2530 58 view .LVU949 + 3123 0118 07EE103A vmov s14, r3 @ int + 3124 011c B8EE477A vcvt.f32.u32 s14, s14 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3125 .loc 1 2530 120 view .LVU950 + 3126 0120 9FED316A vldr.32 s12, .L266+8 + 3127 0124 67EE867A vmul.f32 s15, s15, s12 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3128 .loc 1 2530 111 view .LVU951 + 3129 0128 77EE277A vadd.f32 s15, s14, s15 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3130 .loc 1 2530 138 view .LVU952 + 3131 012c B7EE007A vmov.f32 s14, #1.0e+0 + 3132 0130 77EE877A vadd.f32 s15, s15, s14 +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3133 .loc 1 2530 15 view .LVU953 + 3134 0134 66EEA76A vmul.f32 s13, s13, s15 + 3135 .LVL276: +2531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3136 .loc 1 2531 7 is_stmt 1 view .LVU954 + 3137 .L262: +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3138 .loc 1 2541 5 view .LVU955 +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3139 .loc 1 2541 90 is_stmt 0 view .LVU956 + 3140 0138 294A ldr r2, .L266 + ARM GAS /tmp/ccSY6g1k.s page 132 + + + 3141 013a 936B ldr r3, [r2, #56] +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3142 .loc 1 2541 75 view .LVU957 + 3143 013c C3F34623 ubfx r3, r3, #9, #7 + 3144 0140 07EE103A vmov s14, r3 @ int +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3145 .loc 1 2541 66 view .LVU958 + 3146 0144 B8EE477A vcvt.f32.u32 s14, s14 +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3147 .loc 1 2541 126 view .LVU959 + 3148 0148 B7EE006A vmov.f32 s12, #1.0e+0 + 3149 014c 37EE067A vadd.f32 s14, s14, s12 +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3150 .loc 1 2541 47 view .LVU960 + 3151 0150 C6EE877A vdiv.f32 s15, s13, s14 +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3152 .loc 1 2541 37 view .LVU961 + 3153 0154 FCEEE77A vcvt.u32.f32 s15, s15 +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3154 .loc 1 2541 35 view .LVU962 + 3155 0158 C0ED007A vstr.32 s15, [r0] @ int +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3156 .loc 1 2542 5 is_stmt 1 view .LVU963 +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3157 .loc 1 2542 90 is_stmt 0 view .LVU964 + 3158 015c 936B ldr r3, [r2, #56] +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3159 .loc 1 2542 75 view .LVU965 + 3160 015e C3F30643 ubfx r3, r3, #16, #7 + 3161 0162 07EE103A vmov s14, r3 @ int +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3162 .loc 1 2542 66 view .LVU966 + 3163 0166 B8EE477A vcvt.f32.u32 s14, s14 +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3164 .loc 1 2542 126 view .LVU967 + 3165 016a 37EE067A vadd.f32 s14, s14, s12 +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3166 .loc 1 2542 47 view .LVU968 + 3167 016e C6EE877A vdiv.f32 s15, s13, s14 +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3168 .loc 1 2542 37 view .LVU969 + 3169 0172 FCEEE77A vcvt.u32.f32 s15, s15 +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR + 3170 .loc 1 2542 35 view .LVU970 + 3171 0176 C0ED017A vstr.32 s15, [r0, #4] @ int +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3172 .loc 1 2543 5 is_stmt 1 view .LVU971 +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3173 .loc 1 2543 90 is_stmt 0 view .LVU972 + 3174 017a 936B ldr r3, [r2, #56] +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3175 .loc 1 2543 75 view .LVU973 + 3176 017c C3F30663 ubfx r3, r3, #24, #7 + 3177 0180 07EE903A vmov s15, r3 @ int +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3178 .loc 1 2543 66 view .LVU974 + 3179 0184 F8EE677A vcvt.f32.u32 s15, s15 + ARM GAS /tmp/ccSY6g1k.s page 133 + + +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3180 .loc 1 2543 126 view .LVU975 + 3181 0188 77EE867A vadd.f32 s15, s15, s12 +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3182 .loc 1 2543 47 view .LVU976 + 3183 018c 86EEA77A vdiv.f32 s14, s13, s15 +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3184 .loc 1 2543 37 view .LVU977 + 3185 0190 BCEEC77A vcvt.u32.f32 s14, s14 +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3186 .loc 1 2543 35 view .LVU978 + 3187 0194 80ED027A vstr.32 s14, [r0, #8] @ int + 3188 .LVL277: + 3189 .L256: +2551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3190 .loc 1 2551 1 view .LVU979 + 3191 0198 10BD pop {r4, pc} + 3192 .LVL278: + 3193 .L259: +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3194 .loc 1 2534 7 is_stmt 1 view .LVU980 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3195 .loc 1 2534 39 is_stmt 0 view .LVU981 + 3196 019a 07EE10EA vmov s14, lr @ int + 3197 019e B8EE477A vcvt.f32.u32 s14, s14 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3198 .loc 1 2534 37 view .LVU982 + 3199 01a2 9FED146A vldr.32 s12, .L266+20 + 3200 01a6 C6EE076A vdiv.f32 s13, s12, s14 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3201 .loc 1 2534 81 view .LVU983 + 3202 01aa 0D4B ldr r3, .L266 + 3203 .LVL279: +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3204 .loc 1 2534 81 view .LVU984 + 3205 01ac 9B6B ldr r3, [r3, #56] +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3206 .loc 1 2534 67 view .LVU985 + 3207 01ae C3F30803 ubfx r3, r3, #0, #9 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3208 .loc 1 2534 58 view .LVU986 + 3209 01b2 07EE103A vmov s14, r3 @ int + 3210 01b6 B8EE477A vcvt.f32.u32 s14, s14 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3211 .loc 1 2534 120 view .LVU987 + 3212 01ba 9FED0B6A vldr.32 s12, .L266+8 + 3213 01be 67EE867A vmul.f32 s15, s15, s12 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3214 .loc 1 2534 111 view .LVU988 + 3215 01c2 77EE277A vadd.f32 s15, s14, s15 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3216 .loc 1 2534 138 view .LVU989 + 3217 01c6 B7EE007A vmov.f32 s14, #1.0e+0 + 3218 01ca 77EE877A vadd.f32 s15, s15, s14 +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3219 .loc 1 2534 15 view .LVU990 + 3220 01ce 66EEA76A vmul.f32 s13, s13, s15 + ARM GAS /tmp/ccSY6g1k.s page 134 + + + 3221 .LVL280: +2535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3222 .loc 1 2535 7 is_stmt 1 view .LVU991 + 3223 01d2 B1E7 b .L262 + 3224 .LVL281: + 3225 .L257: +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = 0U; + 3226 .loc 1 2547 5 view .LVU992 +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = 0U; + 3227 .loc 1 2547 35 is_stmt 0 view .LVU993 + 3228 01d4 0023 movs r3, #0 + 3229 .LVL282: +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_Q_Frequency = 0U; + 3230 .loc 1 2547 35 view .LVU994 + 3231 01d6 0360 str r3, [r0] +2548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = 0U; + 3232 .loc 1 2548 5 is_stmt 1 view .LVU995 +2548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_Clocks->PLL2_R_Frequency = 0U; + 3233 .loc 1 2548 35 is_stmt 0 view .LVU996 + 3234 01d8 4360 str r3, [r0, #4] +2549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3235 .loc 1 2549 5 is_stmt 1 view .LVU997 +2549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3236 .loc 1 2549 35 is_stmt 0 view .LVU998 + 3237 01da 8360 str r3, [r0, #8] +2551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3238 .loc 1 2551 1 view .LVU999 + 3239 01dc DCE7 b .L256 + 3240 .L267: + 3241 01de 00BF .align 2 + 3242 .L266: + 3243 01e0 00440258 .word 1476543488 + 3244 01e4 0024744A .word 1249125376 + 3245 01e8 00000039 .word 956301312 + 3246 01ec 0090D003 .word 64000000 + 3247 01f0 0024744C .word 1282679808 + 3248 01f4 0024F44A .word 1257513984 + 3249 .cfi_endproc + 3250 .LFE146: + 3252 .section .text.HAL_RCCEx_GetPLL3ClockFreq,"ax",%progbits + 3253 .align 1 + 3254 .global HAL_RCCEx_GetPLL3ClockFreq + 3255 .syntax unified + 3256 .thumb + 3257 .thumb_func + 3258 .fpu fpv5-d16 + 3260 HAL_RCCEx_GetPLL3ClockFreq: + 3261 .LVL283: + 3262 .LFB147: +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll3m, pll3fracen, hsivalue; + 3263 .loc 1 2568 1 is_stmt 1 view -0 + 3264 .cfi_startproc + 3265 @ args = 0, pretend = 0, frame = 0 + 3266 @ frame_needed = 0, uses_anonymous_args = 0 +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll3m, pll3fracen, hsivalue; + 3267 .loc 1 2568 1 is_stmt 0 view .LVU1001 + 3268 0000 10B5 push {r4, lr} + ARM GAS /tmp/ccSY6g1k.s page 135 + + + 3269 .LCFI8: + 3270 .cfi_def_cfa_offset 8 + 3271 .cfi_offset 4, -8 + 3272 .cfi_offset 14, -4 +2569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** float_t fracn3, pll3vco; + 3273 .loc 1 2569 3 is_stmt 1 view .LVU1002 +2570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3274 .loc 1 2570 3 view .LVU1003 +2575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; + 3275 .loc 1 2575 3 view .LVU1004 +2575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; + 3276 .loc 1 2575 19 is_stmt 0 view .LVU1005 + 3277 0002 774A ldr r2, .L278 + 3278 0004 916A ldr r1, [r2, #40] + 3279 .LVL284: +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + 3280 .loc 1 2576 3 is_stmt 1 view .LVU1006 +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + 3281 .loc 1 2576 16 is_stmt 0 view .LVU1007 + 3282 0006 946A ldr r4, [r2, #40] +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + 3283 .loc 1 2576 9 view .LVU1008 + 3284 0008 C4F3055E ubfx lr, r4, #20, #6 + 3285 .LVL285: +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); + 3286 .loc 1 2577 3 is_stmt 1 view .LVU1009 +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); + 3287 .loc 1 2577 20 is_stmt 0 view .LVU1010 + 3288 000c D36A ldr r3, [r2, #44] +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); + 3289 .loc 1 2577 14 view .LVU1011 + 3290 000e C3F3002C ubfx ip, r3, #8, #1 + 3291 .LVL286: +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3292 .loc 1 2578 3 is_stmt 1 view .LVU1012 +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3293 .loc 1 2578 49 is_stmt 0 view .LVU1013 + 3294 0012 536C ldr r3, [r2, #68] +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3295 .loc 1 2578 84 view .LVU1014 + 3296 0014 C3F3CC03 ubfx r3, r3, #3, #13 +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3297 .loc 1 2578 21 view .LVU1015 + 3298 0018 0CFB03F3 mul r3, ip, r3 + 3299 .LVL287: +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3300 .loc 1 2580 3 is_stmt 1 view .LVU1016 +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3301 .loc 1 2580 6 is_stmt 0 view .LVU1017 + 3302 001c 14F07C7F tst r4, #66060288 + 3303 0020 00F0D880 beq .L269 + 3304 0024 01F00301 and r1, r1, #3 + 3305 .LVL288: +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3306 .loc 1 2580 6 view .LVU1018 + 3307 0028 07EE903A vmov s15, r3 @ int + 3308 002c F8EE677A vcvt.f32.u32 s15, s15 + ARM GAS /tmp/ccSY6g1k.s page 136 + + +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3309 .loc 1 2582 5 is_stmt 1 view .LVU1019 + 3310 0030 0129 cmp r1, #1 + 3311 0032 65D0 beq .L270 + 3312 0034 0229 cmp r1, #2 + 3313 0036 00F0B080 beq .L271 + 3314 003a E1B1 cbz r1, .L277 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3315 .loc 1 2605 7 view .LVU1020 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3316 .loc 1 2605 39 is_stmt 0 view .LVU1021 + 3317 003c 07EE10EA vmov s14, lr @ int + 3318 0040 B8EE477A vcvt.f32.u32 s14, s14 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3319 .loc 1 2605 37 view .LVU1022 + 3320 0044 9FED676A vldr.32 s12, .L278+4 + 3321 0048 C6EE076A vdiv.f32 s13, s12, s14 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3322 .loc 1 2605 81 view .LVU1023 + 3323 004c 644B ldr r3, .L278 + 3324 .LVL289: +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3325 .loc 1 2605 81 view .LVU1024 + 3326 004e 1B6C ldr r3, [r3, #64] +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3327 .loc 1 2605 67 view .LVU1025 + 3328 0050 C3F30803 ubfx r3, r3, #0, #9 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3329 .loc 1 2605 58 view .LVU1026 + 3330 0054 07EE103A vmov s14, r3 @ int + 3331 0058 B8EE477A vcvt.f32.u32 s14, s14 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3332 .loc 1 2605 120 view .LVU1027 + 3333 005c 9FED626A vldr.32 s12, .L278+8 + 3334 0060 67EE867A vmul.f32 s15, s15, s12 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3335 .loc 1 2605 111 view .LVU1028 + 3336 0064 77EE277A vadd.f32 s15, s14, s15 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3337 .loc 1 2605 138 view .LVU1029 + 3338 0068 B7EE007A vmov.f32 s14, #1.0e+0 + 3339 006c 77EE877A vadd.f32 s15, s15, s14 +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3340 .loc 1 2605 15 view .LVU1030 + 3341 0070 66EEA76A vmul.f32 s13, s13, s15 + 3342 .LVL290: +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3343 .loc 1 2606 7 is_stmt 1 view .LVU1031 + 3344 0074 60E0 b .L274 + 3345 .LVL291: + 3346 .L277: +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3347 .loc 1 2586 7 view .LVU1032 +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3348 .loc 1 2586 11 is_stmt 0 view .LVU1033 + 3349 0076 1368 ldr r3, [r2] + 3350 .LVL292: + ARM GAS /tmp/ccSY6g1k.s page 137 + + +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3351 .loc 1 2586 10 view .LVU1034 + 3352 0078 13F0200F tst r3, #32 + 3353 007c 23D0 beq .L273 +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_P + 3354 .loc 1 2588 9 is_stmt 1 view .LVU1035 +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_P + 3355 .loc 1 2588 35 is_stmt 0 view .LVU1036 + 3356 007e 1146 mov r1, r2 + 3357 .LVL293: +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_P + 3358 .loc 1 2588 35 view .LVU1037 + 3359 0080 1268 ldr r2, [r2] +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_P + 3360 .loc 1 2588 62 view .LVU1038 + 3361 0082 C2F3C102 ubfx r2, r2, #3, #2 +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_P + 3362 .loc 1 2588 18 view .LVU1039 + 3363 0086 594B ldr r3, .L278+12 + 3364 0088 D340 lsrs r3, r3, r2 + 3365 .LVL294: +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3366 .loc 1 2589 9 is_stmt 1 view .LVU1040 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3367 .loc 1 2589 20 is_stmt 0 view .LVU1041 + 3368 008a 07EE103A vmov s14, r3 @ int + 3369 008e B8EE477A vcvt.f32.u32 s14, s14 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3370 .loc 1 2589 40 view .LVU1042 + 3371 0092 06EE90EA vmov s13, lr @ int + 3372 0096 B8EE666A vcvt.f32.u32 s12, s13 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3373 .loc 1 2589 38 view .LVU1043 + 3374 009a C7EE066A vdiv.f32 s13, s14, s12 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3375 .loc 1 2589 82 view .LVU1044 + 3376 009e 0B6C ldr r3, [r1, #64] + 3377 .LVL295: +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3378 .loc 1 2589 68 view .LVU1045 + 3379 00a0 C3F30803 ubfx r3, r3, #0, #9 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3380 .loc 1 2589 59 view .LVU1046 + 3381 00a4 07EE103A vmov s14, r3 @ int + 3382 00a8 B8EE477A vcvt.f32.u32 s14, s14 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3383 .loc 1 2589 121 view .LVU1047 + 3384 00ac 9FED4E6A vldr.32 s12, .L278+8 + 3385 00b0 67EE867A vmul.f32 s15, s15, s12 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3386 .loc 1 2589 112 view .LVU1048 + 3387 00b4 77EE277A vadd.f32 s15, s14, s15 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3388 .loc 1 2589 139 view .LVU1049 + 3389 00b8 B7EE007A vmov.f32 s14, #1.0e+0 + 3390 00bc 77EE877A vadd.f32 s15, s15, s14 +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 138 + + + 3391 .loc 1 2589 17 view .LVU1050 + 3392 00c0 66EEA76A vmul.f32 s13, s13, s15 + 3393 .LVL296: +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3394 .loc 1 2589 17 view .LVU1051 + 3395 00c4 38E0 b .L274 + 3396 .LVL297: + 3397 .L273: +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3398 .loc 1 2593 9 is_stmt 1 view .LVU1052 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3399 .loc 1 2593 41 is_stmt 0 view .LVU1053 + 3400 00c6 07EE10EA vmov s14, lr @ int + 3401 00ca B8EE477A vcvt.f32.u32 s14, s14 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3402 .loc 1 2593 39 view .LVU1054 + 3403 00ce 9FED486A vldr.32 s12, .L278+16 + 3404 00d2 C6EE076A vdiv.f32 s13, s12, s14 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3405 .loc 1 2593 83 view .LVU1055 + 3406 00d6 424B ldr r3, .L278 + 3407 00d8 1B6C ldr r3, [r3, #64] +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3408 .loc 1 2593 69 view .LVU1056 + 3409 00da C3F30803 ubfx r3, r3, #0, #9 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3410 .loc 1 2593 60 view .LVU1057 + 3411 00de 07EE103A vmov s14, r3 @ int + 3412 00e2 B8EE477A vcvt.f32.u32 s14, s14 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3413 .loc 1 2593 122 view .LVU1058 + 3414 00e6 9FED406A vldr.32 s12, .L278+8 + 3415 00ea 67EE867A vmul.f32 s15, s15, s12 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3416 .loc 1 2593 113 view .LVU1059 + 3417 00ee 77EE277A vadd.f32 s15, s14, s15 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3418 .loc 1 2593 140 view .LVU1060 + 3419 00f2 B7EE007A vmov.f32 s14, #1.0e+0 + 3420 00f6 77EE877A vadd.f32 s15, s15, s14 +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3421 .loc 1 2593 17 view .LVU1061 + 3422 00fa 66EEA76A vmul.f32 s13, s13, s15 + 3423 .LVL298: +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3424 .loc 1 2593 17 view .LVU1062 + 3425 00fe 1BE0 b .L274 + 3426 .LVL299: + 3427 .L270: +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3428 .loc 1 2597 7 is_stmt 1 view .LVU1063 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3429 .loc 1 2597 39 is_stmt 0 view .LVU1064 + 3430 0100 07EE10EA vmov s14, lr @ int + 3431 0104 B8EE477A vcvt.f32.u32 s14, s14 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3432 .loc 1 2597 37 view .LVU1065 + ARM GAS /tmp/ccSY6g1k.s page 139 + + + 3433 0108 9FED366A vldr.32 s12, .L278+4 + 3434 010c C6EE076A vdiv.f32 s13, s12, s14 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3435 .loc 1 2597 81 view .LVU1066 + 3436 0110 334B ldr r3, .L278 + 3437 .LVL300: +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3438 .loc 1 2597 81 view .LVU1067 + 3439 0112 1B6C ldr r3, [r3, #64] +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3440 .loc 1 2597 67 view .LVU1068 + 3441 0114 C3F30803 ubfx r3, r3, #0, #9 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3442 .loc 1 2597 58 view .LVU1069 + 3443 0118 07EE103A vmov s14, r3 @ int + 3444 011c B8EE477A vcvt.f32.u32 s14, s14 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3445 .loc 1 2597 120 view .LVU1070 + 3446 0120 9FED316A vldr.32 s12, .L278+8 + 3447 0124 67EE867A vmul.f32 s15, s15, s12 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3448 .loc 1 2597 111 view .LVU1071 + 3449 0128 77EE277A vadd.f32 s15, s14, s15 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3450 .loc 1 2597 138 view .LVU1072 + 3451 012c B7EE007A vmov.f32 s14, #1.0e+0 + 3452 0130 77EE877A vadd.f32 s15, s15, s14 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3453 .loc 1 2597 15 view .LVU1073 + 3454 0134 66EEA76A vmul.f32 s13, s13, s15 + 3455 .LVL301: +2598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3456 .loc 1 2598 7 is_stmt 1 view .LVU1074 + 3457 .L274: +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3458 .loc 1 2608 5 view .LVU1075 +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3459 .loc 1 2608 90 is_stmt 0 view .LVU1076 + 3460 0138 294A ldr r2, .L278 + 3461 013a 136C ldr r3, [r2, #64] +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3462 .loc 1 2608 75 view .LVU1077 + 3463 013c C3F34623 ubfx r3, r3, #9, #7 + 3464 0140 07EE103A vmov s14, r3 @ int +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3465 .loc 1 2608 66 view .LVU1078 + 3466 0144 B8EE477A vcvt.f32.u32 s14, s14 +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3467 .loc 1 2608 126 view .LVU1079 + 3468 0148 B7EE006A vmov.f32 s12, #1.0e+0 + 3469 014c 37EE067A vadd.f32 s14, s14, s12 +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3470 .loc 1 2608 47 view .LVU1080 + 3471 0150 C6EE877A vdiv.f32 s15, s13, s14 +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3472 .loc 1 2608 37 view .LVU1081 + 3473 0154 FCEEE77A vcvt.u32.f32 s15, s15 + ARM GAS /tmp/ccSY6g1k.s page 140 + + +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3474 .loc 1 2608 35 view .LVU1082 + 3475 0158 C0ED007A vstr.32 s15, [r0] @ int +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3476 .loc 1 2609 5 is_stmt 1 view .LVU1083 +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3477 .loc 1 2609 90 is_stmt 0 view .LVU1084 + 3478 015c 136C ldr r3, [r2, #64] +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3479 .loc 1 2609 75 view .LVU1085 + 3480 015e C3F30643 ubfx r3, r3, #16, #7 + 3481 0162 07EE103A vmov s14, r3 @ int +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3482 .loc 1 2609 66 view .LVU1086 + 3483 0166 B8EE477A vcvt.f32.u32 s14, s14 +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3484 .loc 1 2609 126 view .LVU1087 + 3485 016a 37EE067A vadd.f32 s14, s14, s12 +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3486 .loc 1 2609 47 view .LVU1088 + 3487 016e C6EE877A vdiv.f32 s15, s13, s14 +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3488 .loc 1 2609 37 view .LVU1089 + 3489 0172 FCEEE77A vcvt.u32.f32 s15, s15 +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR + 3490 .loc 1 2609 35 view .LVU1090 + 3491 0176 C0ED017A vstr.32 s15, [r0, #4] @ int +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3492 .loc 1 2610 5 is_stmt 1 view .LVU1091 +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3493 .loc 1 2610 90 is_stmt 0 view .LVU1092 + 3494 017a 136C ldr r3, [r2, #64] +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3495 .loc 1 2610 75 view .LVU1093 + 3496 017c C3F30663 ubfx r3, r3, #24, #7 + 3497 0180 07EE903A vmov s15, r3 @ int +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3498 .loc 1 2610 66 view .LVU1094 + 3499 0184 F8EE677A vcvt.f32.u32 s15, s15 +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3500 .loc 1 2610 126 view .LVU1095 + 3501 0188 77EE867A vadd.f32 s15, s15, s12 +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3502 .loc 1 2610 47 view .LVU1096 + 3503 018c 86EEA77A vdiv.f32 s14, s13, s15 +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3504 .loc 1 2610 37 view .LVU1097 + 3505 0190 BCEEC77A vcvt.u32.f32 s14, s14 +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3506 .loc 1 2610 35 view .LVU1098 + 3507 0194 80ED027A vstr.32 s14, [r0, #8] @ int + 3508 .LVL302: + 3509 .L268: +2619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3510 .loc 1 2619 1 view .LVU1099 + 3511 0198 10BD pop {r4, pc} + 3512 .LVL303: + ARM GAS /tmp/ccSY6g1k.s page 141 + + + 3513 .L271: +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3514 .loc 1 2601 7 is_stmt 1 view .LVU1100 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3515 .loc 1 2601 39 is_stmt 0 view .LVU1101 + 3516 019a 07EE10EA vmov s14, lr @ int + 3517 019e B8EE477A vcvt.f32.u32 s14, s14 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3518 .loc 1 2601 37 view .LVU1102 + 3519 01a2 9FED146A vldr.32 s12, .L278+20 + 3520 01a6 C6EE076A vdiv.f32 s13, s12, s14 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3521 .loc 1 2601 81 view .LVU1103 + 3522 01aa 0D4B ldr r3, .L278 + 3523 .LVL304: +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3524 .loc 1 2601 81 view .LVU1104 + 3525 01ac 1B6C ldr r3, [r3, #64] +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3526 .loc 1 2601 67 view .LVU1105 + 3527 01ae C3F30803 ubfx r3, r3, #0, #9 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3528 .loc 1 2601 58 view .LVU1106 + 3529 01b2 07EE103A vmov s14, r3 @ int + 3530 01b6 B8EE477A vcvt.f32.u32 s14, s14 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3531 .loc 1 2601 120 view .LVU1107 + 3532 01ba 9FED0B6A vldr.32 s12, .L278+8 + 3533 01be 67EE867A vmul.f32 s15, s15, s12 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3534 .loc 1 2601 111 view .LVU1108 + 3535 01c2 77EE277A vadd.f32 s15, s14, s15 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3536 .loc 1 2601 138 view .LVU1109 + 3537 01c6 B7EE007A vmov.f32 s14, #1.0e+0 + 3538 01ca 77EE877A vadd.f32 s15, s15, s14 +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3539 .loc 1 2601 15 view .LVU1110 + 3540 01ce 66EEA76A vmul.f32 s13, s13, s15 + 3541 .LVL305: +2602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3542 .loc 1 2602 7 is_stmt 1 view .LVU1111 + 3543 01d2 B1E7 b .L274 + 3544 .LVL306: + 3545 .L269: +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = 0U; + 3546 .loc 1 2614 5 view .LVU1112 +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = 0U; + 3547 .loc 1 2614 35 is_stmt 0 view .LVU1113 + 3548 01d4 0023 movs r3, #0 + 3549 .LVL307: +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_Q_Frequency = 0U; + 3550 .loc 1 2614 35 view .LVU1114 + 3551 01d6 0360 str r3, [r0] +2615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = 0U; + 3552 .loc 1 2615 5 is_stmt 1 view .LVU1115 +2615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_Clocks->PLL3_R_Frequency = 0U; + ARM GAS /tmp/ccSY6g1k.s page 142 + + + 3553 .loc 1 2615 35 is_stmt 0 view .LVU1116 + 3554 01d8 4360 str r3, [r0, #4] +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3555 .loc 1 2616 5 is_stmt 1 view .LVU1117 +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3556 .loc 1 2616 35 is_stmt 0 view .LVU1118 + 3557 01da 8360 str r3, [r0, #8] +2619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3558 .loc 1 2619 1 view .LVU1119 + 3559 01dc DCE7 b .L268 + 3560 .L279: + 3561 01de 00BF .align 2 + 3562 .L278: + 3563 01e0 00440258 .word 1476543488 + 3564 01e4 0024744A .word 1249125376 + 3565 01e8 00000039 .word 956301312 + 3566 01ec 0090D003 .word 64000000 + 3567 01f0 0024744C .word 1282679808 + 3568 01f4 0024F44A .word 1257513984 + 3569 .cfi_endproc + 3570 .LFE147: + 3572 .section .text.HAL_RCCEx_GetPLL1ClockFreq,"ax",%progbits + 3573 .align 1 + 3574 .global HAL_RCCEx_GetPLL1ClockFreq + 3575 .syntax unified + 3576 .thumb + 3577 .thumb_func + 3578 .fpu fpv5-d16 + 3580 HAL_RCCEx_GetPLL1ClockFreq: + 3581 .LVL308: + 3582 .LFB148: +2636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll1m, pll1fracen, hsivalue; + 3583 .loc 1 2636 1 is_stmt 1 view -0 + 3584 .cfi_startproc + 3585 @ args = 0, pretend = 0, frame = 0 + 3586 @ frame_needed = 0, uses_anonymous_args = 0 +2636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t pllsource, pll1m, pll1fracen, hsivalue; + 3587 .loc 1 2636 1 is_stmt 0 view .LVU1121 + 3588 0000 10B5 push {r4, lr} + 3589 .LCFI9: + 3590 .cfi_def_cfa_offset 8 + 3591 .cfi_offset 4, -8 + 3592 .cfi_offset 14, -4 +2637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** float_t fracn1, pll1vco; + 3593 .loc 1 2637 3 is_stmt 1 view .LVU1122 +2638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3594 .loc 1 2638 3 view .LVU1123 +2640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4); + 3595 .loc 1 2640 3 view .LVU1124 +2640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4); + 3596 .loc 1 2640 19 is_stmt 0 view .LVU1125 + 3597 0002 774A ldr r2, .L290 + 3598 0004 916A ldr r1, [r2, #40] + 3599 .LVL309: +2641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + 3600 .loc 1 2641 3 is_stmt 1 view .LVU1126 +2641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + ARM GAS /tmp/ccSY6g1k.s page 143 + + + 3601 .loc 1 2641 16 is_stmt 0 view .LVU1127 + 3602 0006 946A ldr r4, [r2, #40] +2641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + 3603 .loc 1 2641 9 view .LVU1128 + 3604 0008 C4F3051E ubfx lr, r4, #4, #6 + 3605 .LVL310: +2642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 3606 .loc 1 2642 3 is_stmt 1 view .LVU1129 +2642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 3607 .loc 1 2642 19 is_stmt 0 view .LVU1130 + 3608 000c D36A ldr r3, [r2, #44] +2642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 3609 .loc 1 2642 14 view .LVU1131 + 3610 000e 03F0010C and ip, r3, #1 + 3611 .LVL311: +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3612 .loc 1 2643 3 is_stmt 1 view .LVU1132 +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3613 .loc 1 2643 50 is_stmt 0 view .LVU1133 + 3614 0012 536B ldr r3, [r2, #52] +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3615 .loc 1 2643 85 view .LVU1134 + 3616 0014 C3F3CC03 ubfx r3, r3, #3, #13 +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3617 .loc 1 2643 21 view .LVU1135 + 3618 0018 0CFB03F3 mul r3, ip, r3 + 3619 .LVL312: +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3620 .loc 1 2645 3 is_stmt 1 view .LVU1136 +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3621 .loc 1 2645 6 is_stmt 0 view .LVU1137 + 3622 001c 14F47C7F tst r4, #1008 + 3623 0020 00F0D880 beq .L281 + 3624 0024 01F00301 and r1, r1, #3 + 3625 .LVL313: +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3626 .loc 1 2645 6 view .LVU1138 + 3627 0028 07EE903A vmov s15, r3 @ int + 3628 002c F8EE677A vcvt.f32.u32 s15, s15 +2647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3629 .loc 1 2647 5 is_stmt 1 view .LVU1139 + 3630 0030 0129 cmp r1, #1 + 3631 0032 65D0 beq .L282 + 3632 0034 0229 cmp r1, #2 + 3633 0036 00F0B080 beq .L283 + 3634 003a E1B1 cbz r1, .L289 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3635 .loc 1 2671 7 view .LVU1140 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3636 .loc 1 2671 39 is_stmt 0 view .LVU1141 + 3637 003c 07EE10EA vmov s14, lr @ int + 3638 0040 B8EE477A vcvt.f32.u32 s14, s14 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3639 .loc 1 2671 37 view .LVU1142 + 3640 0044 9FED676A vldr.32 s12, .L290+4 + 3641 0048 C6EE076A vdiv.f32 s13, s12, s14 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 144 + + + 3642 .loc 1 2671 81 view .LVU1143 + 3643 004c 644B ldr r3, .L290 + 3644 .LVL314: +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3645 .loc 1 2671 81 view .LVU1144 + 3646 004e 1B6B ldr r3, [r3, #48] +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3647 .loc 1 2671 67 view .LVU1145 + 3648 0050 C3F30803 ubfx r3, r3, #0, #9 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3649 .loc 1 2671 58 view .LVU1146 + 3650 0054 07EE103A vmov s14, r3 @ int + 3651 0058 B8EE477A vcvt.f32.u32 s14, s14 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3652 .loc 1 2671 120 view .LVU1147 + 3653 005c 9FED626A vldr.32 s12, .L290+8 + 3654 0060 67EE867A vmul.f32 s15, s15, s12 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3655 .loc 1 2671 111 view .LVU1148 + 3656 0064 77EE277A vadd.f32 s15, s14, s15 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3657 .loc 1 2671 138 view .LVU1149 + 3658 0068 B7EE007A vmov.f32 s14, #1.0e+0 + 3659 006c 77EE877A vadd.f32 s15, s15, s14 +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3660 .loc 1 2671 15 view .LVU1150 + 3661 0070 66EEA76A vmul.f32 s13, s13, s15 + 3662 .LVL315: +2672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3663 .loc 1 2672 7 is_stmt 1 view .LVU1151 + 3664 0074 60E0 b .L286 + 3665 .LVL316: + 3666 .L289: +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3667 .loc 1 2652 7 view .LVU1152 +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3668 .loc 1 2652 11 is_stmt 0 view .LVU1153 + 3669 0076 1368 ldr r3, [r2] + 3670 .LVL317: +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3671 .loc 1 2652 10 view .LVU1154 + 3672 0078 13F0200F tst r3, #32 + 3673 007c 23D0 beq .L285 +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P + 3674 .loc 1 2654 9 is_stmt 1 view .LVU1155 +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P + 3675 .loc 1 2654 35 is_stmt 0 view .LVU1156 + 3676 007e 1146 mov r1, r2 + 3677 .LVL318: +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P + 3678 .loc 1 2654 35 view .LVU1157 + 3679 0080 1268 ldr r2, [r2] +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P + 3680 .loc 1 2654 62 view .LVU1158 + 3681 0082 C2F3C102 ubfx r2, r2, #3, #2 +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P + 3682 .loc 1 2654 18 view .LVU1159 + ARM GAS /tmp/ccSY6g1k.s page 145 + + + 3683 0086 594B ldr r3, .L290+12 + 3684 0088 D340 lsrs r3, r3, r2 + 3685 .LVL319: +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3686 .loc 1 2655 9 is_stmt 1 view .LVU1160 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3687 .loc 1 2655 20 is_stmt 0 view .LVU1161 + 3688 008a 07EE103A vmov s14, r3 @ int + 3689 008e B8EE477A vcvt.f32.u32 s14, s14 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3690 .loc 1 2655 40 view .LVU1162 + 3691 0092 06EE90EA vmov s13, lr @ int + 3692 0096 B8EE666A vcvt.f32.u32 s12, s13 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3693 .loc 1 2655 38 view .LVU1163 + 3694 009a C7EE066A vdiv.f32 s13, s14, s12 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3695 .loc 1 2655 82 view .LVU1164 + 3696 009e 0B6B ldr r3, [r1, #48] + 3697 .LVL320: +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3698 .loc 1 2655 68 view .LVU1165 + 3699 00a0 C3F30803 ubfx r3, r3, #0, #9 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3700 .loc 1 2655 59 view .LVU1166 + 3701 00a4 07EE103A vmov s14, r3 @ int + 3702 00a8 B8EE477A vcvt.f32.u32 s14, s14 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3703 .loc 1 2655 121 view .LVU1167 + 3704 00ac 9FED4E6A vldr.32 s12, .L290+8 + 3705 00b0 67EE867A vmul.f32 s15, s15, s12 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3706 .loc 1 2655 112 view .LVU1168 + 3707 00b4 77EE277A vadd.f32 s15, s14, s15 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3708 .loc 1 2655 139 view .LVU1169 + 3709 00b8 B7EE007A vmov.f32 s14, #1.0e+0 + 3710 00bc 77EE877A vadd.f32 s15, s15, s14 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3711 .loc 1 2655 17 view .LVU1170 + 3712 00c0 66EEA76A vmul.f32 s13, s13, s15 + 3713 .LVL321: +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3714 .loc 1 2655 17 view .LVU1171 + 3715 00c4 38E0 b .L286 + 3716 .LVL322: + 3717 .L285: +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3718 .loc 1 2659 9 is_stmt 1 view .LVU1172 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3719 .loc 1 2659 41 is_stmt 0 view .LVU1173 + 3720 00c6 07EE10EA vmov s14, lr @ int + 3721 00ca B8EE477A vcvt.f32.u32 s14, s14 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3722 .loc 1 2659 39 view .LVU1174 + 3723 00ce 9FED486A vldr.32 s12, .L290+16 + 3724 00d2 C6EE076A vdiv.f32 s13, s12, s14 + ARM GAS /tmp/ccSY6g1k.s page 146 + + +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3725 .loc 1 2659 83 view .LVU1175 + 3726 00d6 424B ldr r3, .L290 + 3727 00d8 1B6B ldr r3, [r3, #48] +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3728 .loc 1 2659 69 view .LVU1176 + 3729 00da C3F30803 ubfx r3, r3, #0, #9 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3730 .loc 1 2659 60 view .LVU1177 + 3731 00de 07EE103A vmov s14, r3 @ int + 3732 00e2 B8EE477A vcvt.f32.u32 s14, s14 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3733 .loc 1 2659 122 view .LVU1178 + 3734 00e6 9FED406A vldr.32 s12, .L290+8 + 3735 00ea 67EE867A vmul.f32 s15, s15, s12 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3736 .loc 1 2659 113 view .LVU1179 + 3737 00ee 77EE277A vadd.f32 s15, s14, s15 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3738 .loc 1 2659 140 view .LVU1180 + 3739 00f2 B7EE007A vmov.f32 s14, #1.0e+0 + 3740 00f6 77EE877A vadd.f32 s15, s15, s14 +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3741 .loc 1 2659 17 view .LVU1181 + 3742 00fa 66EEA76A vmul.f32 s13, s13, s15 + 3743 .LVL323: +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3744 .loc 1 2659 17 view .LVU1182 + 3745 00fe 1BE0 b .L286 + 3746 .LVL324: + 3747 .L282: +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3748 .loc 1 2663 7 is_stmt 1 view .LVU1183 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3749 .loc 1 2663 39 is_stmt 0 view .LVU1184 + 3750 0100 07EE10EA vmov s14, lr @ int + 3751 0104 B8EE477A vcvt.f32.u32 s14, s14 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3752 .loc 1 2663 37 view .LVU1185 + 3753 0108 9FED366A vldr.32 s12, .L290+4 + 3754 010c C6EE076A vdiv.f32 s13, s12, s14 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3755 .loc 1 2663 81 view .LVU1186 + 3756 0110 334B ldr r3, .L290 + 3757 .LVL325: +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3758 .loc 1 2663 81 view .LVU1187 + 3759 0112 1B6B ldr r3, [r3, #48] +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3760 .loc 1 2663 67 view .LVU1188 + 3761 0114 C3F30803 ubfx r3, r3, #0, #9 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3762 .loc 1 2663 58 view .LVU1189 + 3763 0118 07EE103A vmov s14, r3 @ int + 3764 011c B8EE477A vcvt.f32.u32 s14, s14 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3765 .loc 1 2663 120 view .LVU1190 + ARM GAS /tmp/ccSY6g1k.s page 147 + + + 3766 0120 9FED316A vldr.32 s12, .L290+8 + 3767 0124 67EE867A vmul.f32 s15, s15, s12 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3768 .loc 1 2663 111 view .LVU1191 + 3769 0128 77EE277A vadd.f32 s15, s14, s15 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3770 .loc 1 2663 138 view .LVU1192 + 3771 012c B7EE007A vmov.f32 s14, #1.0e+0 + 3772 0130 77EE877A vadd.f32 s15, s15, s14 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3773 .loc 1 2663 15 view .LVU1193 + 3774 0134 66EEA76A vmul.f32 s13, s13, s15 + 3775 .LVL326: +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3776 .loc 1 2664 7 is_stmt 1 view .LVU1194 + 3777 .L286: +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3778 .loc 1 2675 5 view .LVU1195 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3779 .loc 1 2675 90 is_stmt 0 view .LVU1196 + 3780 0138 294A ldr r2, .L290 + 3781 013a 136B ldr r3, [r2, #48] +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3782 .loc 1 2675 75 view .LVU1197 + 3783 013c C3F34623 ubfx r3, r3, #9, #7 + 3784 0140 07EE103A vmov s14, r3 @ int +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3785 .loc 1 2675 66 view .LVU1198 + 3786 0144 B8EE477A vcvt.f32.u32 s14, s14 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3787 .loc 1 2675 126 view .LVU1199 + 3788 0148 B7EE006A vmov.f32 s12, #1.0e+0 + 3789 014c 37EE067A vadd.f32 s14, s14, s12 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3790 .loc 1 2675 47 view .LVU1200 + 3791 0150 C6EE877A vdiv.f32 s15, s13, s14 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3792 .loc 1 2675 37 view .LVU1201 + 3793 0154 FCEEE77A vcvt.u32.f32 s15, s15 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3794 .loc 1 2675 35 view .LVU1202 + 3795 0158 C0ED007A vstr.32 s15, [r0] @ int +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3796 .loc 1 2676 5 is_stmt 1 view .LVU1203 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3797 .loc 1 2676 90 is_stmt 0 view .LVU1204 + 3798 015c 136B ldr r3, [r2, #48] +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3799 .loc 1 2676 75 view .LVU1205 + 3800 015e C3F30643 ubfx r3, r3, #16, #7 + 3801 0162 07EE103A vmov s14, r3 @ int +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3802 .loc 1 2676 66 view .LVU1206 + 3803 0166 B8EE477A vcvt.f32.u32 s14, s14 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3804 .loc 1 2676 126 view .LVU1207 + 3805 016a 37EE067A vadd.f32 s14, s14, s12 + ARM GAS /tmp/ccSY6g1k.s page 148 + + +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3806 .loc 1 2676 47 view .LVU1208 + 3807 016e C6EE877A vdiv.f32 s15, s13, s14 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3808 .loc 1 2676 37 view .LVU1209 + 3809 0172 FCEEE77A vcvt.u32.f32 s15, s15 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR + 3810 .loc 1 2676 35 view .LVU1210 + 3811 0176 C0ED017A vstr.32 s15, [r0, #4] @ int +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3812 .loc 1 2677 5 is_stmt 1 view .LVU1211 +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3813 .loc 1 2677 90 is_stmt 0 view .LVU1212 + 3814 017a 136B ldr r3, [r2, #48] +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3815 .loc 1 2677 75 view .LVU1213 + 3816 017c C3F30663 ubfx r3, r3, #24, #7 + 3817 0180 07EE903A vmov s15, r3 @ int +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3818 .loc 1 2677 66 view .LVU1214 + 3819 0184 F8EE677A vcvt.f32.u32 s15, s15 +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3820 .loc 1 2677 126 view .LVU1215 + 3821 0188 77EE867A vadd.f32 s15, s15, s12 +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3822 .loc 1 2677 47 view .LVU1216 + 3823 018c 86EEA77A vdiv.f32 s14, s13, s15 +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3824 .loc 1 2677 37 view .LVU1217 + 3825 0190 BCEEC77A vcvt.u32.f32 s14, s14 +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3826 .loc 1 2677 35 view .LVU1218 + 3827 0194 80ED027A vstr.32 s14, [r0, #8] @ int + 3828 .LVL327: + 3829 .L280: +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3830 .loc 1 2686 1 view .LVU1219 + 3831 0198 10BD pop {r4, pc} + 3832 .LVL328: + 3833 .L283: +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3834 .loc 1 2667 7 is_stmt 1 view .LVU1220 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3835 .loc 1 2667 39 is_stmt 0 view .LVU1221 + 3836 019a 07EE10EA vmov s14, lr @ int + 3837 019e B8EE477A vcvt.f32.u32 s14, s14 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3838 .loc 1 2667 37 view .LVU1222 + 3839 01a2 9FED146A vldr.32 s12, .L290+20 + 3840 01a6 C6EE076A vdiv.f32 s13, s12, s14 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3841 .loc 1 2667 81 view .LVU1223 + 3842 01aa 0D4B ldr r3, .L290 + 3843 .LVL329: +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3844 .loc 1 2667 81 view .LVU1224 + 3845 01ac 1B6B ldr r3, [r3, #48] + ARM GAS /tmp/ccSY6g1k.s page 149 + + +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3846 .loc 1 2667 67 view .LVU1225 + 3847 01ae C3F30803 ubfx r3, r3, #0, #9 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3848 .loc 1 2667 58 view .LVU1226 + 3849 01b2 07EE103A vmov s14, r3 @ int + 3850 01b6 B8EE477A vcvt.f32.u32 s14, s14 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3851 .loc 1 2667 120 view .LVU1227 + 3852 01ba 9FED0B6A vldr.32 s12, .L290+8 + 3853 01be 67EE867A vmul.f32 s15, s15, s12 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3854 .loc 1 2667 111 view .LVU1228 + 3855 01c2 77EE277A vadd.f32 s15, s14, s15 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3856 .loc 1 2667 138 view .LVU1229 + 3857 01c6 B7EE007A vmov.f32 s14, #1.0e+0 + 3858 01ca 77EE877A vadd.f32 s15, s15, s14 +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3859 .loc 1 2667 15 view .LVU1230 + 3860 01ce 66EEA76A vmul.f32 s13, s13, s15 + 3861 .LVL330: +2668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3862 .loc 1 2668 7 is_stmt 1 view .LVU1231 + 3863 01d2 B1E7 b .L286 + 3864 .LVL331: + 3865 .L281: +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = 0U; + 3866 .loc 1 2681 5 view .LVU1232 +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = 0U; + 3867 .loc 1 2681 35 is_stmt 0 view .LVU1233 + 3868 01d4 0023 movs r3, #0 + 3869 .LVL332: +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_Q_Frequency = 0U; + 3870 .loc 1 2681 35 view .LVU1234 + 3871 01d6 0360 str r3, [r0] +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = 0U; + 3872 .loc 1 2682 5 is_stmt 1 view .LVU1235 +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_Clocks->PLL1_R_Frequency = 0U; + 3873 .loc 1 2682 35 is_stmt 0 view .LVU1236 + 3874 01d8 4360 str r3, [r0, #4] +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3875 .loc 1 2683 5 is_stmt 1 view .LVU1237 +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3876 .loc 1 2683 35 is_stmt 0 view .LVU1238 + 3877 01da 8360 str r3, [r0, #8] +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3878 .loc 1 2686 1 view .LVU1239 + 3879 01dc DCE7 b .L280 + 3880 .L291: + 3881 01de 00BF .align 2 + 3882 .L290: + 3883 01e0 00440258 .word 1476543488 + 3884 01e4 0024744A .word 1249125376 + 3885 01e8 00000039 .word 956301312 + 3886 01ec 0090D003 .word 64000000 + 3887 01f0 0024744C .word 1282679808 + ARM GAS /tmp/ccSY6g1k.s page 150 + + + 3888 01f4 0024F44A .word 1257513984 + 3889 .cfi_endproc + 3890 .LFE148: + 3892 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits + 3893 .align 1 + 3894 .global HAL_RCCEx_GetPeriphCLKFreq + 3895 .syntax unified + 3896 .thumb + 3897 .thumb_func + 3898 .fpu fpv5-d16 + 3900 HAL_RCCEx_GetPeriphCLKFreq: + 3901 .LVL333: + 3902 .LFB143: +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_ClocksTypeDef pll1_clocks; + 3903 .loc 1 1777 1 is_stmt 1 view -0 + 3904 .cfi_startproc + 3905 @ args = 0, pretend = 0, frame = 40 + 3906 @ frame_needed = 0, uses_anonymous_args = 0 +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL1_ClocksTypeDef pll1_clocks; + 3907 .loc 1 1777 1 is_stmt 0 view .LVU1241 + 3908 0000 00B5 push {lr} + 3909 .LCFI10: + 3910 .cfi_def_cfa_offset 4 + 3911 .cfi_offset 14, -4 + 3912 0002 8BB0 sub sp, sp, #44 + 3913 .LCFI11: + 3914 .cfi_def_cfa_offset 48 +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL2_ClocksTypeDef pll2_clocks; + 3915 .loc 1 1778 3 is_stmt 1 view .LVU1242 +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** PLL3_ClocksTypeDef pll3_clocks; + 3916 .loc 1 1779 3 view .LVU1243 +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3917 .loc 1 1780 3 view .LVU1244 +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* This variable is used to store the SAI and CKP clock source */ + 3918 .loc 1 1783 3 view .LVU1245 +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t ckpclocksource; + 3919 .loc 1 1785 3 view .LVU1246 +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t srcclk; + 3920 .loc 1 1786 3 view .LVU1247 +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3921 .loc 1 1787 3 view .LVU1248 +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3922 .loc 1 1789 3 view .LVU1249 +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3923 .loc 1 1789 6 is_stmt 0 view .LVU1250 + 3924 0004 B0F5807F cmp r0, #256 + 3925 0008 1BD0 beq .L364 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3926 .loc 1 1862 8 is_stmt 1 view .LVU1251 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3927 .loc 1 1862 11 is_stmt 0 view .LVU1252 + 3928 000a B0F5007F cmp r0, #512 + 3929 000e 46D0 beq .L365 +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3930 .loc 1 2086 8 is_stmt 1 view .LVU1253 +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3931 .loc 1 2086 11 is_stmt 0 view .LVU1254 + ARM GAS /tmp/ccSY6g1k.s page 151 + + + 3932 0010 B0F5806F cmp r0, #1024 + 3933 0014 77D0 beq .L366 +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3934 .loc 1 2159 8 is_stmt 1 view .LVU1255 +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3935 .loc 1 2159 11 is_stmt 0 view .LVU1256 + 3936 0016 B0F5006F cmp r0, #2048 + 3937 001a 00F0AB80 beq .L367 +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3938 .loc 1 2232 8 is_stmt 1 view .LVU1257 +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3939 .loc 1 2232 11 is_stmt 0 view .LVU1258 + 3940 001e B0F5805F cmp r0, #4096 + 3941 0022 00F0DE80 beq .L368 +2303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3942 .loc 1 2303 8 is_stmt 1 view .LVU1259 +2303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3943 .loc 1 2303 11 is_stmt 0 view .LVU1260 + 3944 0026 B0F5002F cmp r0, #524288 + 3945 002a 00F01181 beq .L369 +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3946 .loc 1 2362 8 is_stmt 1 view .LVU1261 +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3947 .loc 1 2362 11 is_stmt 0 view .LVU1262 + 3948 002e B0F5803F cmp r0, #65536 + 3949 0032 00F03981 beq .L370 +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3950 .loc 1 2389 8 is_stmt 1 view .LVU1263 +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3951 .loc 1 2389 11 is_stmt 0 view .LVU1264 + 3952 0036 B0F5804F cmp r0, #16384 + 3953 003a 00F04781 beq .L371 +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3954 .loc 1 2444 17 view .LVU1265 + 3955 003e 0020 movs r0, #0 + 3956 .LVL334: +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3957 .loc 1 2444 17 view .LVU1266 + 3958 0040 71E1 b .L292 + 3959 .LVL335: + 3960 .L364: +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3961 .loc 1 1792 7 is_stmt 1 view .LVU1267 +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3962 .loc 1 1792 23 is_stmt 0 view .LVU1268 + 3963 0042 964B ldr r3, .L393 + 3964 0044 1B6D ldr r3, [r3, #80] +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3965 .loc 1 1792 21 view .LVU1269 + 3966 0046 03F00703 and r3, r3, #7 + 3967 .LVL336: +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 3968 .loc 1 1794 7 is_stmt 1 view .LVU1270 + 3969 004a 042B cmp r3, #4 + 3970 004c 00F26481 bhi .L335 + 3971 0050 DFE803F0 tbb [pc, r3] + 3972 .L296: + ARM GAS /tmp/ccSY6g1k.s page 152 + + + 3973 0054 05 .byte (.L300-.L296)/2 + 3974 0055 0A .byte (.L299-.L296)/2 + 3975 0056 0F .byte (.L298-.L296)/2 + 3976 0057 03 .byte (.L297-.L296)/2 + 3977 0058 14 .byte (.L295-.L296)/2 + 3978 0059 00 .p2align 1 + 3979 .L297: +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3980 .loc 1 1792 21 is_stmt 0 view .LVU1271 + 3981 005a 9148 ldr r0, .L393+4 + 3982 .LVL337: +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 3983 .loc 1 1792 21 view .LVU1272 + 3984 005c 63E1 b .L292 + 3985 .LVL338: + 3986 .L300: +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 3987 .loc 1 1798 11 is_stmt 1 view .LVU1273 + 3988 005e 07A8 add r0, sp, #28 + 3989 .LVL339: +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 3990 .loc 1 1798 11 is_stmt 0 view .LVU1274 + 3991 0060 FFF7FEFF bl HAL_RCCEx_GetPLL1ClockFreq + 3992 .LVL340: +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3993 .loc 1 1799 11 is_stmt 1 view .LVU1275 +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 3994 .loc 1 1799 21 is_stmt 0 view .LVU1276 + 3995 0064 0898 ldr r0, [sp, #32] + 3996 .LVL341: +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 3997 .loc 1 1800 11 is_stmt 1 view .LVU1277 + 3998 0066 5EE1 b .L292 + 3999 .LVL342: + 4000 .L299: +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4001 .loc 1 1804 11 view .LVU1278 + 4002 0068 04A8 add r0, sp, #16 + 4003 .LVL343: +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4004 .loc 1 1804 11 is_stmt 0 view .LVU1279 + 4005 006a FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4006 .LVL344: +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4007 .loc 1 1805 11 is_stmt 1 view .LVU1280 +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4008 .loc 1 1805 21 is_stmt 0 view .LVU1281 + 4009 006e 0498 ldr r0, [sp, #16] + 4010 .LVL345: +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4011 .loc 1 1806 11 is_stmt 1 view .LVU1282 + 4012 0070 59E1 b .L292 + 4013 .LVL346: + 4014 .L298: +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4015 .loc 1 1811 11 view .LVU1283 + 4016 0072 01A8 add r0, sp, #4 + ARM GAS /tmp/ccSY6g1k.s page 153 + + + 4017 .LVL347: +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4018 .loc 1 1811 11 is_stmt 0 view .LVU1284 + 4019 0074 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4020 .LVL348: +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4021 .loc 1 1812 11 is_stmt 1 view .LVU1285 +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4022 .loc 1 1812 21 is_stmt 0 view .LVU1286 + 4023 0078 0198 ldr r0, [sp, #4] + 4024 .LVL349: +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4025 .loc 1 1813 11 is_stmt 1 view .LVU1287 + 4026 007a 54E1 b .L292 + 4027 .LVL350: + 4028 .L295: +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4029 .loc 1 1819 11 view .LVU1288 +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4030 .loc 1 1819 27 is_stmt 0 view .LVU1289 + 4031 007c 874B ldr r3, .L393 + 4032 .LVL351: +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4033 .loc 1 1819 27 view .LVU1290 + 4034 007e DB6C ldr r3, [r3, #76] + 4035 .LVL352: +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4036 .loc 1 1821 11 is_stmt 1 view .LVU1291 +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4037 .loc 1 1821 13 is_stmt 0 view .LVU1292 + 4038 0080 13F04053 ands r3, r3, #805306368 + 4039 .LVL353: +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4040 .loc 1 1821 13 view .LVU1293 + 4041 0084 00F04A81 beq .L336 +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4042 .loc 1 1827 16 is_stmt 1 view .LVU1294 +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4043 .loc 1 1827 18 is_stmt 0 view .LVU1295 + 4044 0088 B3F1805F cmp r3, #268435456 + 4045 008c 00F04881 beq .L337 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4046 .loc 1 1833 16 is_stmt 1 view .LVU1296 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4047 .loc 1 1833 19 is_stmt 0 view .LVU1297 + 4048 0090 B3F1005F cmp r3, #536870912 + 4049 0094 01D0 beq .L372 +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4050 .loc 1 1842 23 view .LVU1298 + 4051 0096 0020 movs r0, #0 + 4052 .LVL354: +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4053 .loc 1 1842 23 view .LVU1299 + 4054 0098 45E1 b .L292 + 4055 .LVL355: + 4056 .L372: +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 154 + + + 4057 .loc 1 1836 23 view .LVU1300 + 4058 009a 8248 ldr r0, .L393+8 + 4059 .LVL356: +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4060 .loc 1 1836 23 view .LVU1301 + 4061 009c 43E1 b .L292 + 4062 .LVL357: + 4063 .L365: +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4064 .loc 1 1865 7 is_stmt 1 view .LVU1302 +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4065 .loc 1 1865 23 is_stmt 0 view .LVU1303 + 4066 009e 7F4B ldr r3, .L393 + 4067 00a0 1B6D ldr r3, [r3, #80] +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4068 .loc 1 1865 21 view .LVU1304 + 4069 00a2 03F4E073 and r3, r3, #448 + 4070 .LVL358: +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4071 .loc 1 1867 7 is_stmt 1 view .LVU1305 + 4072 00a6 802B cmp r3, #128 + 4073 00a8 26D0 beq .L302 + 4074 00aa 14D9 bls .L373 + 4075 00ac C02B cmp r3, #192 + 4076 00ae 00F03981 beq .L339 + 4077 00b2 B3F5807F cmp r3, #256 + 4078 00b6 18D1 bne .L374 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4079 .loc 1 1892 11 view .LVU1306 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4080 .loc 1 1892 27 is_stmt 0 view .LVU1307 + 4081 00b8 784B ldr r3, .L393 + 4082 .LVL359: +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4083 .loc 1 1892 27 view .LVU1308 + 4084 00ba DB6C ldr r3, [r3, #76] + 4085 .LVL360: +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4086 .loc 1 1894 11 is_stmt 1 view .LVU1309 +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4087 .loc 1 1894 13 is_stmt 0 view .LVU1310 + 4088 00bc 13F04053 ands r3, r3, #805306368 + 4089 .LVL361: +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4090 .loc 1 1894 13 view .LVU1311 + 4091 00c0 00F03481 beq .L340 +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4092 .loc 1 1900 16 is_stmt 1 view .LVU1312 +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4093 .loc 1 1900 18 is_stmt 0 view .LVU1313 + 4094 00c4 B3F1805F cmp r3, #268435456 + 4095 00c8 00F03281 beq .L341 +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4096 .loc 1 1906 16 is_stmt 1 view .LVU1314 +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4097 .loc 1 1906 19 is_stmt 0 view .LVU1315 + 4098 00cc B3F1005F cmp r3, #536870912 + ARM GAS /tmp/ccSY6g1k.s page 155 + + + 4099 00d0 17D0 beq .L375 +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4100 .loc 1 1915 23 view .LVU1316 + 4101 00d2 0020 movs r0, #0 + 4102 .LVL362: +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4103 .loc 1 1915 23 view .LVU1317 + 4104 00d4 27E1 b .L292 + 4105 .LVL363: + 4106 .L373: +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4107 .loc 1 1867 7 view .LVU1318 + 4108 00d6 53B1 cbz r3, .L304 + 4109 00d8 402B cmp r3, #64 + 4110 00da 04D1 bne .L376 +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4111 .loc 1 1877 11 is_stmt 1 view .LVU1319 + 4112 00dc 04A8 add r0, sp, #16 + 4113 .LVL364: +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4114 .loc 1 1877 11 is_stmt 0 view .LVU1320 + 4115 00de FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4116 .LVL365: +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4117 .loc 1 1878 11 is_stmt 1 view .LVU1321 +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4118 .loc 1 1878 21 is_stmt 0 view .LVU1322 + 4119 00e2 0498 ldr r0, [sp, #16] + 4120 .LVL366: +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4121 .loc 1 1879 11 is_stmt 1 view .LVU1323 + 4122 00e4 1FE1 b .L292 + 4123 .LVL367: + 4124 .L376: +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4125 .loc 1 1928 21 is_stmt 0 view .LVU1324 + 4126 00e6 0020 movs r0, #0 + 4127 .LVL368: +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4128 .loc 1 1928 21 view .LVU1325 + 4129 00e8 1DE1 b .L292 + 4130 .LVL369: + 4131 .L374: +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4132 .loc 1 1928 21 view .LVU1326 + 4133 00ea 0020 movs r0, #0 + 4134 .LVL370: +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4135 .loc 1 1928 21 view .LVU1327 + 4136 00ec 1BE1 b .L292 + 4137 .LVL371: + 4138 .L304: +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4139 .loc 1 1871 11 is_stmt 1 view .LVU1328 + 4140 00ee 07A8 add r0, sp, #28 + 4141 .LVL372: +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + ARM GAS /tmp/ccSY6g1k.s page 156 + + + 4142 .loc 1 1871 11 is_stmt 0 view .LVU1329 + 4143 00f0 FFF7FEFF bl HAL_RCCEx_GetPLL1ClockFreq + 4144 .LVL373: +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4145 .loc 1 1872 11 is_stmt 1 view .LVU1330 +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4146 .loc 1 1872 21 is_stmt 0 view .LVU1331 + 4147 00f4 0898 ldr r0, [sp, #32] + 4148 .LVL374: +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4149 .loc 1 1873 11 is_stmt 1 view .LVU1332 + 4150 00f6 16E1 b .L292 + 4151 .LVL375: + 4152 .L302: +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4153 .loc 1 1884 11 view .LVU1333 + 4154 00f8 01A8 add r0, sp, #4 + 4155 .LVL376: +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4156 .loc 1 1884 11 is_stmt 0 view .LVU1334 + 4157 00fa FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4158 .LVL377: +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4159 .loc 1 1885 11 is_stmt 1 view .LVU1335 +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4160 .loc 1 1885 21 is_stmt 0 view .LVU1336 + 4161 00fe 0198 ldr r0, [sp, #4] + 4162 .LVL378: +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4163 .loc 1 1886 11 is_stmt 1 view .LVU1337 + 4164 0100 11E1 b .L292 + 4165 .LVL379: + 4166 .L375: +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4167 .loc 1 1909 23 is_stmt 0 view .LVU1338 + 4168 0102 6848 ldr r0, .L393+8 + 4169 .LVL380: +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4170 .loc 1 1909 23 view .LVU1339 + 4171 0104 0FE1 b .L292 + 4172 .LVL381: + 4173 .L366: +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4174 .loc 1 2089 7 is_stmt 1 view .LVU1340 +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4175 .loc 1 2089 23 is_stmt 0 view .LVU1341 + 4176 0106 654B ldr r3, .L393 + 4177 0108 9B6D ldr r3, [r3, #88] +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4178 .loc 1 2089 21 view .LVU1342 + 4179 010a 03F46003 and r3, r3, #14680064 + 4180 .LVL382: +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4181 .loc 1 2091 7 is_stmt 1 view .LVU1343 + 4182 010e B3F5800F cmp r3, #4194304 + 4183 0112 28D0 beq .L308 + 4184 0114 15D9 bls .L377 + ARM GAS /tmp/ccSY6g1k.s page 157 + + + 4185 0116 B3F5C00F cmp r3, #6291456 + 4186 011a 00F00B81 beq .L343 + 4187 011e B3F5000F cmp r3, #8388608 + 4188 0122 19D1 bne .L378 +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4189 .loc 1 2116 11 view .LVU1344 +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4190 .loc 1 2116 27 is_stmt 0 view .LVU1345 + 4191 0124 5D4B ldr r3, .L393 + 4192 .LVL383: +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4193 .loc 1 2116 27 view .LVU1346 + 4194 0126 DB6C ldr r3, [r3, #76] + 4195 .LVL384: +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4196 .loc 1 2118 11 is_stmt 1 view .LVU1347 +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4197 .loc 1 2118 13 is_stmt 0 view .LVU1348 + 4198 0128 13F04053 ands r3, r3, #805306368 + 4199 .LVL385: +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4200 .loc 1 2118 13 view .LVU1349 + 4201 012c 00F00481 beq .L344 +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4202 .loc 1 2124 16 is_stmt 1 view .LVU1350 +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4203 .loc 1 2124 18 is_stmt 0 view .LVU1351 + 4204 0130 B3F1805F cmp r3, #268435456 + 4205 0134 00F00281 beq .L345 +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4206 .loc 1 2130 16 is_stmt 1 view .LVU1352 +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4207 .loc 1 2130 19 is_stmt 0 view .LVU1353 + 4208 0138 B3F1005F cmp r3, #536870912 + 4209 013c 18D0 beq .L379 +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4210 .loc 1 2139 23 view .LVU1354 + 4211 013e 0020 movs r0, #0 + 4212 .LVL386: +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4213 .loc 1 2139 23 view .LVU1355 + 4214 0140 F1E0 b .L292 + 4215 .LVL387: + 4216 .L377: +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4217 .loc 1 2091 7 view .LVU1356 + 4218 0142 5BB1 cbz r3, .L310 + 4219 0144 B3F5001F cmp r3, #2097152 + 4220 0148 04D1 bne .L380 +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4221 .loc 1 2101 11 is_stmt 1 view .LVU1357 + 4222 014a 04A8 add r0, sp, #16 + 4223 .LVL388: +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4224 .loc 1 2101 11 is_stmt 0 view .LVU1358 + 4225 014c FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4226 .LVL389: + ARM GAS /tmp/ccSY6g1k.s page 158 + + +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4227 .loc 1 2102 11 is_stmt 1 view .LVU1359 +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4228 .loc 1 2102 21 is_stmt 0 view .LVU1360 + 4229 0150 0498 ldr r0, [sp, #16] + 4230 .LVL390: +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4231 .loc 1 2103 11 is_stmt 1 view .LVU1361 + 4232 0152 E8E0 b .L292 + 4233 .LVL391: + 4234 .L380: +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4235 .loc 1 2153 21 is_stmt 0 view .LVU1362 + 4236 0154 0020 movs r0, #0 + 4237 .LVL392: +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4238 .loc 1 2153 21 view .LVU1363 + 4239 0156 E6E0 b .L292 + 4240 .LVL393: + 4241 .L378: +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4242 .loc 1 2153 21 view .LVU1364 + 4243 0158 0020 movs r0, #0 + 4244 .LVL394: +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4245 .loc 1 2153 21 view .LVU1365 + 4246 015a E4E0 b .L292 + 4247 .LVL395: + 4248 .L310: +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4249 .loc 1 2095 11 is_stmt 1 view .LVU1366 + 4250 015c 07A8 add r0, sp, #28 + 4251 .LVL396: +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4252 .loc 1 2095 11 is_stmt 0 view .LVU1367 + 4253 015e FFF7FEFF bl HAL_RCCEx_GetPLL1ClockFreq + 4254 .LVL397: +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4255 .loc 1 2096 11 is_stmt 1 view .LVU1368 +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4256 .loc 1 2096 21 is_stmt 0 view .LVU1369 + 4257 0162 0898 ldr r0, [sp, #32] + 4258 .LVL398: +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4259 .loc 1 2097 11 is_stmt 1 view .LVU1370 + 4260 0164 DFE0 b .L292 + 4261 .LVL399: + 4262 .L308: +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4263 .loc 1 2108 11 view .LVU1371 + 4264 0166 01A8 add r0, sp, #4 + 4265 .LVL400: +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4266 .loc 1 2108 11 is_stmt 0 view .LVU1372 + 4267 0168 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4268 .LVL401: +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccSY6g1k.s page 159 + + + 4269 .loc 1 2109 11 is_stmt 1 view .LVU1373 +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4270 .loc 1 2109 21 is_stmt 0 view .LVU1374 + 4271 016c 0198 ldr r0, [sp, #4] + 4272 .LVL402: +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4273 .loc 1 2110 11 is_stmt 1 view .LVU1375 + 4274 016e DAE0 b .L292 + 4275 .LVL403: + 4276 .L379: +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4277 .loc 1 2133 23 is_stmt 0 view .LVU1376 + 4278 0170 4C48 ldr r0, .L393+8 + 4279 .LVL404: +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4280 .loc 1 2133 23 view .LVU1377 + 4281 0172 D8E0 b .L292 + 4282 .LVL405: + 4283 .L367: +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4284 .loc 1 2162 7 is_stmt 1 view .LVU1378 +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4285 .loc 1 2162 23 is_stmt 0 view .LVU1379 + 4286 0174 494B ldr r3, .L393 + 4287 0176 9B6D ldr r3, [r3, #88] +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4288 .loc 1 2162 21 view .LVU1380 + 4289 0178 03F0E063 and r3, r3, #117440512 + 4290 .LVL406: +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4291 .loc 1 2164 7 is_stmt 1 view .LVU1381 + 4292 017c B3F1007F cmp r3, #33554432 + 4293 0180 28D0 beq .L314 + 4294 0182 15D9 bls .L381 + 4295 0184 B3F1407F cmp r3, #50331648 + 4296 0188 00F0DA80 beq .L347 + 4297 018c B3F1806F cmp r3, #67108864 + 4298 0190 19D1 bne .L382 +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4299 .loc 1 2189 11 view .LVU1382 +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4300 .loc 1 2189 27 is_stmt 0 view .LVU1383 + 4301 0192 424B ldr r3, .L393 + 4302 .LVL407: +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4303 .loc 1 2189 27 view .LVU1384 + 4304 0194 DB6C ldr r3, [r3, #76] + 4305 .LVL408: +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4306 .loc 1 2191 11 is_stmt 1 view .LVU1385 +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4307 .loc 1 2191 13 is_stmt 0 view .LVU1386 + 4308 0196 13F04053 ands r3, r3, #805306368 + 4309 .LVL409: +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4310 .loc 1 2191 13 view .LVU1387 + 4311 019a 00F0D380 beq .L348 + ARM GAS /tmp/ccSY6g1k.s page 160 + + +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4312 .loc 1 2197 16 is_stmt 1 view .LVU1388 +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4313 .loc 1 2197 18 is_stmt 0 view .LVU1389 + 4314 019e B3F1805F cmp r3, #268435456 + 4315 01a2 00F0D180 beq .L349 +2203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4316 .loc 1 2203 16 is_stmt 1 view .LVU1390 +2203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4317 .loc 1 2203 19 is_stmt 0 view .LVU1391 + 4318 01a6 B3F1005F cmp r3, #536870912 + 4319 01aa 18D0 beq .L383 +2212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4320 .loc 1 2212 23 view .LVU1392 + 4321 01ac 0020 movs r0, #0 + 4322 .LVL410: +2212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4323 .loc 1 2212 23 view .LVU1393 + 4324 01ae BAE0 b .L292 + 4325 .LVL411: + 4326 .L381: +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4327 .loc 1 2164 7 view .LVU1394 + 4328 01b0 5BB1 cbz r3, .L316 + 4329 01b2 B3F1807F cmp r3, #16777216 + 4330 01b6 04D1 bne .L384 +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4331 .loc 1 2174 11 is_stmt 1 view .LVU1395 + 4332 01b8 04A8 add r0, sp, #16 + 4333 .LVL412: +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4334 .loc 1 2174 11 is_stmt 0 view .LVU1396 + 4335 01ba FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4336 .LVL413: +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4337 .loc 1 2175 11 is_stmt 1 view .LVU1397 +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4338 .loc 1 2175 21 is_stmt 0 view .LVU1398 + 4339 01be 0498 ldr r0, [sp, #16] + 4340 .LVL414: +2176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4341 .loc 1 2176 11 is_stmt 1 view .LVU1399 + 4342 01c0 B1E0 b .L292 + 4343 .LVL415: + 4344 .L384: +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4345 .loc 1 2226 21 is_stmt 0 view .LVU1400 + 4346 01c2 0020 movs r0, #0 + 4347 .LVL416: +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4348 .loc 1 2226 21 view .LVU1401 + 4349 01c4 AFE0 b .L292 + 4350 .LVL417: + 4351 .L382: +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4352 .loc 1 2226 21 view .LVU1402 + 4353 01c6 0020 movs r0, #0 + ARM GAS /tmp/ccSY6g1k.s page 161 + + + 4354 .LVL418: +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4355 .loc 1 2226 21 view .LVU1403 + 4356 01c8 ADE0 b .L292 + 4357 .LVL419: + 4358 .L316: +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4359 .loc 1 2168 11 is_stmt 1 view .LVU1404 + 4360 01ca 07A8 add r0, sp, #28 + 4361 .LVL420: +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4362 .loc 1 2168 11 is_stmt 0 view .LVU1405 + 4363 01cc FFF7FEFF bl HAL_RCCEx_GetPLL1ClockFreq + 4364 .LVL421: +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4365 .loc 1 2169 11 is_stmt 1 view .LVU1406 +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4366 .loc 1 2169 21 is_stmt 0 view .LVU1407 + 4367 01d0 0898 ldr r0, [sp, #32] + 4368 .LVL422: +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4369 .loc 1 2170 11 is_stmt 1 view .LVU1408 + 4370 01d2 A8E0 b .L292 + 4371 .LVL423: + 4372 .L314: +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4373 .loc 1 2181 11 view .LVU1409 + 4374 01d4 01A8 add r0, sp, #4 + 4375 .LVL424: +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4376 .loc 1 2181 11 is_stmt 0 view .LVU1410 + 4377 01d6 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4378 .LVL425: +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4379 .loc 1 2182 11 is_stmt 1 view .LVU1411 +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4380 .loc 1 2182 21 is_stmt 0 view .LVU1412 + 4381 01da 0198 ldr r0, [sp, #4] + 4382 .LVL426: +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4383 .loc 1 2183 11 is_stmt 1 view .LVU1413 + 4384 01dc A3E0 b .L292 + 4385 .LVL427: + 4386 .L383: +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4387 .loc 1 2206 23 is_stmt 0 view .LVU1414 + 4388 01de 3148 ldr r0, .L393+8 + 4389 .LVL428: +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4390 .loc 1 2206 23 view .LVU1415 + 4391 01e0 A1E0 b .L292 + 4392 .LVL429: + 4393 .L368: +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4394 .loc 1 2235 7 is_stmt 1 view .LVU1416 +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4395 .loc 1 2235 15 is_stmt 0 view .LVU1417 + ARM GAS /tmp/ccSY6g1k.s page 162 + + + 4396 01e2 2E4B ldr r3, .L393 + 4397 01e4 1B6D ldr r3, [r3, #80] +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4398 .loc 1 2235 13 view .LVU1418 + 4399 01e6 03F4E043 and r3, r3, #28672 + 4400 .LVL430: +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4401 .loc 1 2237 7 is_stmt 1 view .LVU1419 + 4402 01ea B3F5005F cmp r3, #8192 + 4403 01ee 28D0 beq .L320 + 4404 01f0 15D9 bls .L385 + 4405 01f2 B3F5405F cmp r3, #12288 + 4406 01f6 00F0A980 beq .L351 + 4407 01fa B3F5804F cmp r3, #16384 + 4408 01fe 19D1 bne .L386 +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4409 .loc 1 2262 11 view .LVU1420 +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4410 .loc 1 2262 27 is_stmt 0 view .LVU1421 + 4411 0200 264B ldr r3, .L393 + 4412 .LVL431: +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4413 .loc 1 2262 27 view .LVU1422 + 4414 0202 DB6C ldr r3, [r3, #76] + 4415 .LVL432: +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4416 .loc 1 2264 11 is_stmt 1 view .LVU1423 +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4417 .loc 1 2264 13 is_stmt 0 view .LVU1424 + 4418 0204 13F04053 ands r3, r3, #805306368 + 4419 .LVL433: +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4420 .loc 1 2264 13 view .LVU1425 + 4421 0208 00F0A280 beq .L352 +2270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4422 .loc 1 2270 16 is_stmt 1 view .LVU1426 +2270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4423 .loc 1 2270 18 is_stmt 0 view .LVU1427 + 4424 020c B3F1805F cmp r3, #268435456 + 4425 0210 00F0A080 beq .L353 +2276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4426 .loc 1 2276 16 is_stmt 1 view .LVU1428 +2276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4427 .loc 1 2276 19 is_stmt 0 view .LVU1429 + 4428 0214 B3F1005F cmp r3, #536870912 + 4429 0218 18D0 beq .L387 +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4430 .loc 1 2285 23 view .LVU1430 + 4431 021a 0020 movs r0, #0 + 4432 .LVL434: +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4433 .loc 1 2285 23 view .LVU1431 + 4434 021c 83E0 b .L292 + 4435 .LVL435: + 4436 .L385: +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4437 .loc 1 2237 7 view .LVU1432 + ARM GAS /tmp/ccSY6g1k.s page 163 + + + 4438 021e 5BB1 cbz r3, .L322 + 4439 0220 B3F5805F cmp r3, #4096 + 4440 0224 04D1 bne .L388 +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4441 .loc 1 2247 11 is_stmt 1 view .LVU1433 + 4442 0226 04A8 add r0, sp, #16 + 4443 .LVL436: +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4444 .loc 1 2247 11 is_stmt 0 view .LVU1434 + 4445 0228 FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4446 .LVL437: +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4447 .loc 1 2248 11 is_stmt 1 view .LVU1435 +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4448 .loc 1 2248 21 is_stmt 0 view .LVU1436 + 4449 022c 0498 ldr r0, [sp, #16] + 4450 .LVL438: +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4451 .loc 1 2249 11 is_stmt 1 view .LVU1437 + 4452 022e 7AE0 b .L292 + 4453 .LVL439: + 4454 .L388: +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4455 .loc 1 2298 21 is_stmt 0 view .LVU1438 + 4456 0230 0020 movs r0, #0 + 4457 .LVL440: +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4458 .loc 1 2298 21 view .LVU1439 + 4459 0232 78E0 b .L292 + 4460 .LVL441: + 4461 .L386: +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4462 .loc 1 2298 21 view .LVU1440 + 4463 0234 0020 movs r0, #0 + 4464 .LVL442: +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4465 .loc 1 2298 21 view .LVU1441 + 4466 0236 76E0 b .L292 + 4467 .LVL443: + 4468 .L322: +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4469 .loc 1 2241 11 is_stmt 1 view .LVU1442 + 4470 0238 07A8 add r0, sp, #28 + 4471 .LVL444: +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4472 .loc 1 2241 11 is_stmt 0 view .LVU1443 + 4473 023a FFF7FEFF bl HAL_RCCEx_GetPLL1ClockFreq + 4474 .LVL445: +2242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4475 .loc 1 2242 11 is_stmt 1 view .LVU1444 +2242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4476 .loc 1 2242 21 is_stmt 0 view .LVU1445 + 4477 023e 0898 ldr r0, [sp, #32] + 4478 .LVL446: +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4479 .loc 1 2243 11 is_stmt 1 view .LVU1446 + 4480 0240 71E0 b .L292 + ARM GAS /tmp/ccSY6g1k.s page 164 + + + 4481 .LVL447: + 4482 .L320: +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4483 .loc 1 2254 11 view .LVU1447 + 4484 0242 01A8 add r0, sp, #4 + 4485 .LVL448: +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_P_Frequency; + 4486 .loc 1 2254 11 is_stmt 0 view .LVU1448 + 4487 0244 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4488 .LVL449: +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4489 .loc 1 2255 11 is_stmt 1 view .LVU1449 +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4490 .loc 1 2255 21 is_stmt 0 view .LVU1450 + 4491 0248 0198 ldr r0, [sp, #4] + 4492 .LVL450: +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4493 .loc 1 2256 11 is_stmt 1 view .LVU1451 + 4494 024a 6CE0 b .L292 + 4495 .LVL451: + 4496 .L387: +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4497 .loc 1 2279 23 is_stmt 0 view .LVU1452 + 4498 024c 1548 ldr r0, .L393+8 + 4499 .LVL452: +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4500 .loc 1 2279 23 view .LVU1453 + 4501 024e 6AE0 b .L292 + 4502 .LVL453: + 4503 .L369: +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4504 .loc 1 2306 7 is_stmt 1 view .LVU1454 +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4505 .loc 1 2306 15 is_stmt 0 view .LVU1455 + 4506 0250 124B ldr r3, .L393 + 4507 0252 9B6D ldr r3, [r3, #88] +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4508 .loc 1 2306 13 view .LVU1456 + 4509 0254 03F44033 and r3, r3, #196608 + 4510 .LVL454: +2308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4511 .loc 1 2308 7 is_stmt 1 view .LVU1457 + 4512 0258 B3F5803F cmp r3, #65536 + 4513 025c 0AD0 beq .L326 + 4514 025e B3F5003F cmp r3, #131072 + 4515 0262 0CD0 beq .L327 + 4516 0264 0BB1 cbz r3, .L389 + 4517 0266 0020 movs r0, #0 + 4518 .LVL455: +2308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4519 .loc 1 2308 7 is_stmt 0 view .LVU1458 + 4520 0268 5DE0 b .L292 + 4521 .LVL456: + 4522 .L389: +2312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4523 .loc 1 2312 11 is_stmt 1 view .LVU1459 + 4524 026a 04A8 add r0, sp, #16 + ARM GAS /tmp/ccSY6g1k.s page 165 + + + 4525 .LVL457: +2312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_P_Frequency; + 4526 .loc 1 2312 11 is_stmt 0 view .LVU1460 + 4527 026c FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4528 .LVL458: +2313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4529 .loc 1 2313 11 is_stmt 1 view .LVU1461 +2313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4530 .loc 1 2313 21 is_stmt 0 view .LVU1462 + 4531 0270 0498 ldr r0, [sp, #16] + 4532 .LVL459: +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4533 .loc 1 2314 11 is_stmt 1 view .LVU1463 + 4534 0272 58E0 b .L292 + 4535 .LVL460: + 4536 .L326: +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_R_Frequency; + 4537 .loc 1 2318 11 view .LVU1464 + 4538 0274 01A8 add r0, sp, #4 + 4539 .LVL461: +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_R_Frequency; + 4540 .loc 1 2318 11 is_stmt 0 view .LVU1465 + 4541 0276 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4542 .LVL462: +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4543 .loc 1 2319 11 is_stmt 1 view .LVU1466 +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4544 .loc 1 2319 21 is_stmt 0 view .LVU1467 + 4545 027a 0398 ldr r0, [sp, #12] + 4546 .LVL463: +2320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4547 .loc 1 2320 11 is_stmt 1 view .LVU1468 + 4548 027c 53E0 b .L292 + 4549 .LVL464: + 4550 .L327: +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4551 .loc 1 2326 11 view .LVU1469 +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4552 .loc 1 2326 27 is_stmt 0 view .LVU1470 + 4553 027e 074B ldr r3, .L393 + 4554 .LVL465: +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4555 .loc 1 2326 27 view .LVU1471 + 4556 0280 DB6C ldr r3, [r3, #76] + 4557 .LVL466: +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4558 .loc 1 2328 11 is_stmt 1 view .LVU1472 +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4559 .loc 1 2328 13 is_stmt 0 view .LVU1473 + 4560 0282 13F04053 ands r3, r3, #805306368 + 4561 .LVL467: +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4562 .loc 1 2328 13 view .LVU1474 + 4563 0286 67D0 beq .L356 +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4564 .loc 1 2334 16 is_stmt 1 view .LVU1475 +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 166 + + + 4565 .loc 1 2334 18 is_stmt 0 view .LVU1476 + 4566 0288 B3F1805F cmp r3, #268435456 + 4567 028c 66D0 beq .L357 +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4568 .loc 1 2340 16 is_stmt 1 view .LVU1477 +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4569 .loc 1 2340 19 is_stmt 0 view .LVU1478 + 4570 028e B3F1005F cmp r3, #536870912 + 4571 0292 01D0 beq .L390 +2349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4572 .loc 1 2349 23 view .LVU1479 + 4573 0294 0020 movs r0, #0 + 4574 .LVL468: +2349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4575 .loc 1 2349 23 view .LVU1480 + 4576 0296 46E0 b .L292 + 4577 .LVL469: + 4578 .L390: +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4579 .loc 1 2343 23 view .LVU1481 + 4580 0298 0248 ldr r0, .L393+8 + 4581 .LVL470: +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4582 .loc 1 2343 23 view .LVU1482 + 4583 029a 44E0 b .L292 + 4584 .L394: + 4585 .align 2 + 4586 .L393: + 4587 029c 00440258 .word 1476543488 + 4588 02a0 0080BB00 .word 12288000 + 4589 02a4 00127A00 .word 8000000 + 4590 .LVL471: + 4591 .L370: +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4592 .loc 1 2365 7 is_stmt 1 view .LVU1483 +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4593 .loc 1 2365 15 is_stmt 0 view .LVU1484 + 4594 02a8 304B ldr r3, .L395 + 4595 02aa DB6C ldr r3, [r3, #76] + 4596 .LVL472: +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4597 .loc 1 2367 7 is_stmt 1 view .LVU1485 + 4598 02ac 13F48033 ands r3, r3, #65536 + 4599 .LVL473: +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4600 .loc 1 2367 7 is_stmt 0 view .LVU1486 + 4601 02b0 02D0 beq .L329 + 4602 02b2 33B9 cbnz r3, .L330 + 4603 02b4 0020 movs r0, #0 + 4604 .LVL474: +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4605 .loc 1 2367 7 view .LVU1487 + 4606 02b6 36E0 b .L292 + 4607 .LVL475: + 4608 .L329: +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4609 .loc 1 2371 11 is_stmt 1 view .LVU1488 + ARM GAS /tmp/ccSY6g1k.s page 167 + + + 4610 02b8 07A8 add r0, sp, #28 + 4611 .LVL476: +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll1_clocks.PLL1_Q_Frequency; + 4612 .loc 1 2371 11 is_stmt 0 view .LVU1489 + 4613 02ba FFF7FEFF bl HAL_RCCEx_GetPLL1ClockFreq + 4614 .LVL477: +2372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4615 .loc 1 2372 11 is_stmt 1 view .LVU1490 +2372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4616 .loc 1 2372 21 is_stmt 0 view .LVU1491 + 4617 02be 0898 ldr r0, [sp, #32] + 4618 .LVL478: +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4619 .loc 1 2373 11 is_stmt 1 view .LVU1492 + 4620 02c0 31E0 b .L292 + 4621 .LVL479: + 4622 .L330: +2377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_R_Frequency; + 4623 .loc 1 2377 11 view .LVU1493 + 4624 02c2 04A8 add r0, sp, #16 + 4625 .LVL480: +2377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_R_Frequency; + 4626 .loc 1 2377 11 is_stmt 0 view .LVU1494 + 4627 02c4 FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4628 .LVL481: +2378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4629 .loc 1 2378 11 is_stmt 1 view .LVU1495 +2378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4630 .loc 1 2378 21 is_stmt 0 view .LVU1496 + 4631 02c8 0698 ldr r0, [sp, #24] + 4632 .LVL482: +2379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4633 .loc 1 2379 11 is_stmt 1 view .LVU1497 + 4634 02ca 2CE0 b .L292 + 4635 .LVL483: + 4636 .L371: +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4637 .loc 1 2392 7 view .LVU1498 +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4638 .loc 1 2392 15 is_stmt 0 view .LVU1499 + 4639 02cc 274B ldr r3, .L395 + 4640 02ce 9B6D ldr r3, [r3, #88] +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4641 .loc 1 2392 13 view .LVU1500 + 4642 02d0 03F0E043 and r3, r3, #1879048192 + 4643 .LVL484: +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4644 .loc 1 2394 7 is_stmt 1 view .LVU1501 + 4645 02d4 B3F1405F cmp r3, #805306368 + 4646 02d8 42D0 beq .L360 + 4647 02da 10D8 bhi .L331 + 4648 02dc B3F1805F cmp r3, #268435456 + 4649 02e0 15D0 beq .L332 + 4650 02e2 B3F1005F cmp r3, #536870912 + 4651 02e6 04D1 bne .L391 +2409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_Q_Frequency; + 4652 .loc 1 2409 11 view .LVU1502 + ARM GAS /tmp/ccSY6g1k.s page 168 + + + 4653 02e8 01A8 add r0, sp, #4 + 4654 .LVL485: +2409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll3_clocks.PLL3_Q_Frequency; + 4655 .loc 1 2409 11 is_stmt 0 view .LVU1503 + 4656 02ea FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 4657 .LVL486: +2410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4658 .loc 1 2410 11 is_stmt 1 view .LVU1504 +2410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4659 .loc 1 2410 21 is_stmt 0 view .LVU1505 + 4660 02ee 0298 ldr r0, [sp, #8] + 4661 .LVL487: +2411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4662 .loc 1 2411 11 is_stmt 1 view .LVU1506 + 4663 02f0 19E0 b .L292 + 4664 .LVL488: + 4665 .L391: +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4666 .loc 1 2394 7 is_stmt 0 view .LVU1507 + 4667 02f2 13B9 cbnz r3, .L392 +2398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4668 .loc 1 2398 11 is_stmt 1 view .LVU1508 +2398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4669 .loc 1 2398 23 is_stmt 0 view .LVU1509 + 4670 02f4 FFF7FEFF bl HAL_RCCEx_GetD3PCLK1Freq + 4671 .LVL489: +2399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4672 .loc 1 2399 11 is_stmt 1 view .LVU1510 + 4673 02f8 15E0 b .L292 + 4674 .LVL490: + 4675 .L392: +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4676 .loc 1 2437 21 is_stmt 0 view .LVU1511 + 4677 02fa 0020 movs r0, #0 + 4678 .LVL491: +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4679 .loc 1 2437 21 view .LVU1512 + 4680 02fc 13E0 b .L292 + 4681 .LVL492: + 4682 .L331: +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4683 .loc 1 2394 7 view .LVU1513 + 4684 02fe B3F1804F cmp r3, #1073741824 + 4685 0302 2FD0 beq .L361 + 4686 0304 B3F1A04F cmp r3, #1342177280 + 4687 0308 2ED1 bne .L362 +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4688 .loc 1 2425 21 view .LVU1514 + 4689 030a 1948 ldr r0, .L395+4 + 4690 .LVL493: +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4691 .loc 1 2425 21 view .LVU1515 + 4692 030c 0BE0 b .L292 + 4693 .LVL494: + 4694 .L332: +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_Q_Frequency; + 4695 .loc 1 2403 11 is_stmt 1 view .LVU1516 + ARM GAS /tmp/ccSY6g1k.s page 169 + + + 4696 030e 04A8 add r0, sp, #16 + 4697 .LVL495: +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** frequency = pll2_clocks.PLL2_Q_Frequency; + 4698 .loc 1 2403 11 is_stmt 0 view .LVU1517 + 4699 0310 FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 4700 .LVL496: +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4701 .loc 1 2404 11 is_stmt 1 view .LVU1518 +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4702 .loc 1 2404 21 is_stmt 0 view .LVU1519 + 4703 0314 0598 ldr r0, [sp, #20] + 4704 .LVL497: +2405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4705 .loc 1 2405 11 is_stmt 1 view .LVU1520 + 4706 0316 06E0 b .L292 + 4707 .LVL498: + 4708 .L335: +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4709 .loc 1 1855 21 is_stmt 0 view .LVU1521 + 4710 0318 0020 movs r0, #0 + 4711 .LVL499: +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4712 .loc 1 1855 21 view .LVU1522 + 4713 031a 04E0 b .L292 + 4714 .LVL500: + 4715 .L336: +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4716 .loc 1 1824 23 view .LVU1523 + 4717 031c 1548 ldr r0, .L395+8 + 4718 .LVL501: +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4719 .loc 1 1824 23 view .LVU1524 + 4720 031e 02E0 b .L292 + 4721 .LVL502: + 4722 .L337: +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4723 .loc 1 1830 23 view .LVU1525 + 4724 0320 1548 ldr r0, .L395+12 + 4725 .LVL503: +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4726 .loc 1 1830 23 view .LVU1526 + 4727 0322 00E0 b .L292 + 4728 .LVL504: + 4729 .L339: +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4730 .loc 1 1867 7 view .LVU1527 + 4731 0324 1548 ldr r0, .L395+16 + 4732 .LVL505: + 4733 .L292: +2448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4734 .loc 1 2448 1 view .LVU1528 + 4735 0326 0BB0 add sp, sp, #44 + 4736 .LCFI12: + 4737 .cfi_remember_state + 4738 .cfi_def_cfa_offset 4 + 4739 @ sp needed + 4740 0328 5DF804FB ldr pc, [sp], #4 + ARM GAS /tmp/ccSY6g1k.s page 170 + + + 4741 .LVL506: + 4742 .L340: + 4743 .LCFI13: + 4744 .cfi_restore_state +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4745 .loc 1 1897 23 view .LVU1529 + 4746 032c 1148 ldr r0, .L395+8 + 4747 .LVL507: +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4748 .loc 1 1897 23 view .LVU1530 + 4749 032e FAE7 b .L292 + 4750 .LVL508: + 4751 .L341: +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4752 .loc 1 1903 23 view .LVU1531 + 4753 0330 1148 ldr r0, .L395+12 + 4754 .LVL509: +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4755 .loc 1 1903 23 view .LVU1532 + 4756 0332 F8E7 b .L292 + 4757 .LVL510: + 4758 .L343: +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4759 .loc 1 2091 7 view .LVU1533 + 4760 0334 1148 ldr r0, .L395+16 + 4761 .LVL511: +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4762 .loc 1 2091 7 view .LVU1534 + 4763 0336 F6E7 b .L292 + 4764 .LVL512: + 4765 .L344: +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4766 .loc 1 2121 23 view .LVU1535 + 4767 0338 0E48 ldr r0, .L395+8 + 4768 .LVL513: +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4769 .loc 1 2121 23 view .LVU1536 + 4770 033a F4E7 b .L292 + 4771 .LVL514: + 4772 .L345: +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4773 .loc 1 2127 23 view .LVU1537 + 4774 033c 0E48 ldr r0, .L395+12 + 4775 .LVL515: +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4776 .loc 1 2127 23 view .LVU1538 + 4777 033e F2E7 b .L292 + 4778 .LVL516: + 4779 .L347: +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4780 .loc 1 2164 7 view .LVU1539 + 4781 0340 0E48 ldr r0, .L395+16 + 4782 .LVL517: +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4783 .loc 1 2164 7 view .LVU1540 + 4784 0342 F0E7 b .L292 + 4785 .LVL518: + ARM GAS /tmp/ccSY6g1k.s page 171 + + + 4786 .L348: +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4787 .loc 1 2194 23 view .LVU1541 + 4788 0344 0B48 ldr r0, .L395+8 + 4789 .LVL519: +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4790 .loc 1 2194 23 view .LVU1542 + 4791 0346 EEE7 b .L292 + 4792 .LVL520: + 4793 .L349: +2200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4794 .loc 1 2200 23 view .LVU1543 + 4795 0348 0B48 ldr r0, .L395+12 + 4796 .LVL521: +2200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4797 .loc 1 2200 23 view .LVU1544 + 4798 034a ECE7 b .L292 + 4799 .LVL522: + 4800 .L351: +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4801 .loc 1 2237 7 view .LVU1545 + 4802 034c 0B48 ldr r0, .L395+16 + 4803 .LVL523: +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4804 .loc 1 2237 7 view .LVU1546 + 4805 034e EAE7 b .L292 + 4806 .LVL524: + 4807 .L352: +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4808 .loc 1 2267 23 view .LVU1547 + 4809 0350 0848 ldr r0, .L395+8 + 4810 .LVL525: +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4811 .loc 1 2267 23 view .LVU1548 + 4812 0352 E8E7 b .L292 + 4813 .LVL526: + 4814 .L353: +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4815 .loc 1 2273 23 view .LVU1549 + 4816 0354 0848 ldr r0, .L395+12 + 4817 .LVL527: +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4818 .loc 1 2273 23 view .LVU1550 + 4819 0356 E6E7 b .L292 + 4820 .LVL528: + 4821 .L356: +2331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4822 .loc 1 2331 23 view .LVU1551 + 4823 0358 0648 ldr r0, .L395+8 + 4824 .LVL529: +2331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4825 .loc 1 2331 23 view .LVU1552 + 4826 035a E4E7 b .L292 + 4827 .LVL530: + 4828 .L357: +2337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4829 .loc 1 2337 23 view .LVU1553 + ARM GAS /tmp/ccSY6g1k.s page 172 + + + 4830 035c 0648 ldr r0, .L395+12 + 4831 .LVL531: +2337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4832 .loc 1 2337 23 view .LVU1554 + 4833 035e E2E7 b .L292 + 4834 .LVL532: + 4835 .L360: +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4836 .loc 1 2394 7 view .LVU1555 + 4837 0360 0448 ldr r0, .L395+8 + 4838 .LVL533: +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 4839 .loc 1 2394 7 view .LVU1556 + 4840 0362 E0E7 b .L292 + 4841 .LVL534: + 4842 .L361: +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4843 .loc 1 2420 21 view .LVU1557 + 4844 0364 0448 ldr r0, .L395+12 + 4845 .LVL535: +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4846 .loc 1 2420 21 view .LVU1558 + 4847 0366 DEE7 b .L292 + 4848 .LVL536: + 4849 .L362: +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** break; + 4850 .loc 1 2437 21 view .LVU1559 + 4851 0368 0020 movs r0, #0 + 4852 .LVL537: +2447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4853 .loc 1 2447 3 is_stmt 1 view .LVU1560 +2447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4854 .loc 1 2447 10 is_stmt 0 view .LVU1561 + 4855 036a DCE7 b .L292 + 4856 .L396: + 4857 .align 2 + 4858 .L395: + 4859 036c 00440258 .word 1476543488 + 4860 0370 00127A00 .word 8000000 + 4861 0374 0090D003 .word 64000000 + 4862 0378 00093D00 .word 4000000 + 4863 037c 0080BB00 .word 12288000 + 4864 .cfi_endproc + 4865 .LFE143: + 4867 .section .text.HAL_RCCEx_GetD1SysClockFreq,"ax",%progbits + 4868 .align 1 + 4869 .global HAL_RCCEx_GetD1SysClockFreq + 4870 .syntax unified + 4871 .thumb + 4872 .thumb_func + 4873 .fpu fpv5-d16 + 4875 HAL_RCCEx_GetD1SysClockFreq: + 4876 .LFB149: +2697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t common_system_clock; + 4877 .loc 1 2697 1 is_stmt 1 view -0 + 4878 .cfi_startproc + 4879 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccSY6g1k.s page 173 + + + 4880 @ frame_needed = 0, uses_anonymous_args = 0 + 4881 0000 08B5 push {r3, lr} + 4882 .LCFI14: + 4883 .cfi_def_cfa_offset 8 + 4884 .cfi_offset 3, -8 + 4885 .cfi_offset 14, -4 +2698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4886 .loc 1 2698 1 view .LVU1563 +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4887 .loc 1 2701 3 view .LVU1564 +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4888 .loc 1 2701 25 is_stmt 0 view .LVU1565 + 4889 0002 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 4890 .LVL538: +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4891 .loc 1 2701 76 view .LVU1566 + 4892 0006 0B49 ldr r1, .L399 + 4893 0008 8B69 ldr r3, [r1, #24] +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4894 .loc 1 2701 105 view .LVU1567 + 4895 000a C3F30323 ubfx r3, r3, #8, #4 +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4896 .loc 1 2701 71 view .LVU1568 + 4897 000e 0A4A ldr r2, .L399+4 + 4898 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4899 .loc 1 2701 131 view .LVU1569 + 4900 0012 03F01F03 and r3, r3, #31 +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4901 .loc 1 2701 23 view .LVU1570 + 4902 0016 D840 lsrs r0, r0, r3 + 4903 .LVL539: +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4904 .loc 1 2708 3 is_stmt 1 view .LVU1571 +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4905 .loc 1 2708 66 is_stmt 0 view .LVU1572 + 4906 0018 8B69 ldr r3, [r1, #24] +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4907 .loc 1 2708 93 view .LVU1573 + 4908 001a 03F00F03 and r3, r3, #15 +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4909 .loc 1 2708 61 view .LVU1574 + 4910 001e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4911 .loc 1 2708 118 view .LVU1575 + 4912 0020 03F01F03 and r3, r3, #31 +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4913 .loc 1 2708 40 view .LVU1576 + 4914 0024 20FA03F3 lsr r3, r0, r3 +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #else + 4915 .loc 1 2708 17 view .LVU1577 + 4916 0028 044A ldr r2, .L399+8 + 4917 002a 1360 str r3, [r2] +2716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 4918 .loc 1 2716 3 is_stmt 1 view .LVU1578 +2716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 4919 .loc 1 2716 19 is_stmt 0 view .LVU1579 + ARM GAS /tmp/ccSY6g1k.s page 174 + + + 4920 002c 044B ldr r3, .L399+12 + 4921 002e 1860 str r0, [r3] +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4922 .loc 1 2719 3 is_stmt 1 view .LVU1580 +2720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** + 4923 .loc 1 2720 1 is_stmt 0 view .LVU1581 + 4924 0030 08BD pop {r3, pc} + 4925 .L400: + 4926 0032 00BF .align 2 + 4927 .L399: + 4928 0034 00440258 .word 1476543488 + 4929 0038 00000000 .word D1CorePrescTable + 4930 003c 00000000 .word SystemD2Clock + 4931 0040 00000000 .word SystemCoreClock + 4932 .cfi_endproc + 4933 .LFE149: + 4935 .section .text.HAL_RCCEx_EnableLSECSS,"ax",%progbits + 4936 .align 1 + 4937 .global HAL_RCCEx_EnableLSECSS + 4938 .syntax unified + 4939 .thumb + 4940 .thumb_func + 4941 .fpu fpv5-d16 + 4943 HAL_RCCEx_EnableLSECSS: + 4944 .LFB150: +2737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + 4945 .loc 1 2737 1 is_stmt 1 view -0 + 4946 .cfi_startproc + 4947 @ args = 0, pretend = 0, frame = 0 + 4948 @ frame_needed = 0, uses_anonymous_args = 0 + 4949 @ link register save eliminated. +2738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4950 .loc 1 2738 3 view .LVU1583 + 4951 0000 024A ldr r2, .L402 + 4952 0002 136F ldr r3, [r2, #112] + 4953 0004 43F02003 orr r3, r3, #32 + 4954 0008 1367 str r3, [r2, #112] +2739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4955 .loc 1 2739 1 is_stmt 0 view .LVU1584 + 4956 000a 7047 bx lr + 4957 .L403: + 4958 .align 2 + 4959 .L402: + 4960 000c 00440258 .word 1476543488 + 4961 .cfi_endproc + 4962 .LFE150: + 4964 .section .text.HAL_RCCEx_DisableLSECSS,"ax",%progbits + 4965 .align 1 + 4966 .global HAL_RCCEx_DisableLSECSS + 4967 .syntax unified + 4968 .thumb + 4969 .thumb_func + 4970 .fpu fpv5-d16 + 4972 HAL_RCCEx_DisableLSECSS: + 4973 .LFB151: +2747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + 4974 .loc 1 2747 1 is_stmt 1 view -0 + ARM GAS /tmp/ccSY6g1k.s page 175 + + + 4975 .cfi_startproc + 4976 @ args = 0, pretend = 0, frame = 0 + 4977 @ frame_needed = 0, uses_anonymous_args = 0 + 4978 @ link register save eliminated. +2748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Disable LSE CSS IT if any */ + 4979 .loc 1 2748 3 view .LVU1586 + 4980 0000 044B ldr r3, .L405 + 4981 0002 1A6F ldr r2, [r3, #112] + 4982 0004 22F02002 bic r2, r2, #32 + 4983 0008 1A67 str r2, [r3, #112] +2750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 4984 .loc 1 2750 3 view .LVU1587 + 4985 000a 1A6E ldr r2, [r3, #96] + 4986 000c 22F40072 bic r2, r2, #512 + 4987 0010 1A66 str r2, [r3, #96] +2751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 4988 .loc 1 2751 1 is_stmt 0 view .LVU1588 + 4989 0012 7047 bx lr + 4990 .L406: + 4991 .align 2 + 4992 .L405: + 4993 0014 00440258 .word 1476543488 + 4994 .cfi_endproc + 4995 .LFE151: + 4997 .section .text.HAL_RCCEx_EnableLSECSS_IT,"ax",%progbits + 4998 .align 1 + 4999 .global HAL_RCCEx_EnableLSECSS_IT + 5000 .syntax unified + 5001 .thumb + 5002 .thumb_func + 5003 .fpu fpv5-d16 + 5005 HAL_RCCEx_EnableLSECSS_IT: + 5006 .LFB152: +2759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Enable LSE CSS */ + 5007 .loc 1 2759 1 is_stmt 1 view -0 + 5008 .cfi_startproc + 5009 @ args = 0, pretend = 0, frame = 0 + 5010 @ frame_needed = 0, uses_anonymous_args = 0 + 5011 @ link register save eliminated. +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5012 .loc 1 2761 3 view .LVU1590 + 5013 0000 0A4B ldr r3, .L408 + 5014 0002 1A6F ldr r2, [r3, #112] + 5015 0004 42F02002 orr r2, r2, #32 + 5016 0008 1A67 str r2, [r3, #112] +2764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5017 .loc 1 2764 3 view .LVU1591 + 5018 000a 1A6E ldr r2, [r3, #96] + 5019 000c 42F40072 orr r2, r2, #512 + 5020 0010 1A66 str r2, [r3, #96] +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif /* DUAL_CORE && CORE_CM4 */ + 5021 .loc 1 2770 3 view .LVU1592 + 5022 0012 4FF0B043 mov r3, #1476395008 + 5023 0016 D3F88020 ldr r2, [r3, #128] + 5024 001a 42F48022 orr r2, r2, #262144 + 5025 001e C3F88020 str r2, [r3, #128] +2772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 176 + + + 5026 .loc 1 2772 3 view .LVU1593 + 5027 0022 1A68 ldr r2, [r3] + 5028 0024 42F48022 orr r2, r2, #262144 + 5029 0028 1A60 str r2, [r3] +2773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5030 .loc 1 2773 1 is_stmt 0 view .LVU1594 + 5031 002a 7047 bx lr + 5032 .L409: + 5033 .align 2 + 5034 .L408: + 5035 002c 00440258 .word 1476543488 + 5036 .cfi_endproc + 5037 .LFE152: + 5039 .section .text.HAL_RCCEx_WakeUpStopCLKConfig,"ax",%progbits + 5040 .align 1 + 5041 .global HAL_RCCEx_WakeUpStopCLKConfig + 5042 .syntax unified + 5043 .thumb + 5044 .thumb_func + 5045 .fpu fpv5-d16 + 5047 HAL_RCCEx_WakeUpStopCLKConfig: + 5048 .LVL540: + 5049 .LFB153: +2786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + 5050 .loc 1 2786 1 is_stmt 1 view -0 + 5051 .cfi_startproc + 5052 @ args = 0, pretend = 0, frame = 0 + 5053 @ frame_needed = 0, uses_anonymous_args = 0 + 5054 @ link register save eliminated. +2787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5055 .loc 1 2787 3 view .LVU1596 +2789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5056 .loc 1 2789 3 view .LVU1597 + 5057 0000 034A ldr r2, .L411 + 5058 0002 1369 ldr r3, [r2, #16] + 5059 0004 23F04003 bic r3, r3, #64 + 5060 0008 0343 orrs r3, r3, r0 + 5061 000a 1361 str r3, [r2, #16] +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5062 .loc 1 2790 1 is_stmt 0 view .LVU1598 + 5063 000c 7047 bx lr + 5064 .L412: + 5065 000e 00BF .align 2 + 5066 .L411: + 5067 0010 00440258 .word 1476543488 + 5068 .cfi_endproc + 5069 .LFE153: + 5071 .section .text.HAL_RCCEx_KerWakeUpStopCLKConfig,"ax",%progbits + 5072 .align 1 + 5073 .global HAL_RCCEx_KerWakeUpStopCLKConfig + 5074 .syntax unified + 5075 .thumb + 5076 .thumb_func + 5077 .fpu fpv5-d16 + 5079 HAL_RCCEx_KerWakeUpStopCLKConfig: + 5080 .LVL541: + 5081 .LFB154: + ARM GAS /tmp/ccSY6g1k.s page 177 + + +2801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + 5082 .loc 1 2801 1 is_stmt 1 view -0 + 5083 .cfi_startproc + 5084 @ args = 0, pretend = 0, frame = 0 + 5085 @ frame_needed = 0, uses_anonymous_args = 0 + 5086 @ link register save eliminated. +2802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5087 .loc 1 2802 3 view .LVU1600 +2804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5088 .loc 1 2804 3 view .LVU1601 + 5089 0000 034A ldr r2, .L414 + 5090 0002 1369 ldr r3, [r2, #16] + 5091 0004 23F08003 bic r3, r3, #128 + 5092 0008 0343 orrs r3, r3, r0 + 5093 000a 1361 str r3, [r2, #16] +2805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5094 .loc 1 2805 1 is_stmt 0 view .LVU1602 + 5095 000c 7047 bx lr + 5096 .L415: + 5097 000e 00BF .align 2 + 5098 .L414: + 5099 0010 00440258 .word 1476543488 + 5100 .cfi_endproc + 5101 .LFE154: + 5103 .section .text.HAL_RCCEx_WWDGxSysResetConfig,"ax",%progbits + 5104 .align 1 + 5105 .global HAL_RCCEx_WWDGxSysResetConfig + 5106 .syntax unified + 5107 .thumb + 5108 .thumb_func + 5109 .fpu fpv5-d16 + 5111 HAL_RCCEx_WWDGxSysResetConfig: + 5112 .LVL542: + 5113 .LFB155: +2855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + 5114 .loc 1 2855 1 is_stmt 1 view -0 + 5115 .cfi_startproc + 5116 @ args = 0, pretend = 0, frame = 0 + 5117 @ frame_needed = 0, uses_anonymous_args = 0 + 5118 @ link register save eliminated. +2856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(RCC->GCR, RCC_WWDGx) ; + 5119 .loc 1 2856 3 view .LVU1604 +2857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5120 .loc 1 2857 3 view .LVU1605 + 5121 0000 034A ldr r2, .L417 + 5122 0002 D2F8A030 ldr r3, [r2, #160] + 5123 0006 0343 orrs r3, r3, r0 + 5124 0008 C2F8A030 str r3, [r2, #160] +2858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** #endif + 5125 .loc 1 2858 1 is_stmt 0 view .LVU1606 + 5126 000c 7047 bx lr + 5127 .L418: + 5128 000e 00BF .align 2 + 5129 .L417: + 5130 0010 00440258 .word 1476543488 + 5131 .cfi_endproc + 5132 .LFE155: + ARM GAS /tmp/ccSY6g1k.s page 178 + + + 5134 .section .text.HAL_RCCEx_CRSConfig,"ax",%progbits + 5135 .align 1 + 5136 .global HAL_RCCEx_CRSConfig + 5137 .syntax unified + 5138 .thumb + 5139 .thumb_func + 5140 .fpu fpv5-d16 + 5142 HAL_RCCEx_CRSConfig: + 5143 .LVL543: + 5144 .LFB156: +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t value; + 5145 .loc 1 2936 1 is_stmt 1 view -0 + 5146 .cfi_startproc + 5147 @ args = 0, pretend = 0, frame = 0 + 5148 @ frame_needed = 0, uses_anonymous_args = 0 +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t value; + 5149 .loc 1 2936 1 is_stmt 0 view .LVU1608 + 5150 0000 10B5 push {r4, lr} + 5151 .LCFI15: + 5152 .cfi_def_cfa_offset 8 + 5153 .cfi_offset 4, -8 + 5154 .cfi_offset 14, -4 + 5155 0002 0446 mov r4, r0 +2937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5156 .loc 1 2937 3 is_stmt 1 view .LVU1609 +2940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + 5157 .loc 1 2940 3 view .LVU1610 +2941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + 5158 .loc 1 2941 3 view .LVU1611 +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + 5159 .loc 1 2942 3 view .LVU1612 +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + 5160 .loc 1 2943 3 view .LVU1613 +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + 5161 .loc 1 2944 3 view .LVU1614 +2945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5162 .loc 1 2945 3 view .LVU1615 +2950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CRS_RELEASE_RESET(); + 5163 .loc 1 2950 3 view .LVU1616 + 5164 0004 194B ldr r3, .L424 + 5165 0006 D3F89420 ldr r2, [r3, #148] + 5166 000a 42F00202 orr r2, r2, #2 + 5167 000e C3F89420 str r2, [r3, #148] +2951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5168 .loc 1 2951 3 view .LVU1617 + 5169 0012 D3F89420 ldr r2, [r3, #148] + 5170 0016 22F00202 bic r2, r2, #2 + 5171 001a C3F89420 str r2, [r3, #148] +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5172 .loc 1 2956 3 view .LVU1618 +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5173 .loc 1 2956 8 is_stmt 0 view .LVU1619 + 5174 001e FFF7FEFF bl HAL_GetREVID + 5175 .LVL544: +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5176 .loc 1 2956 6 view .LVU1620 + 5177 0022 41F20303 movw r3, #4099 + ARM GAS /tmp/ccSY6g1k.s page 179 + + + 5178 0026 9842 cmp r0, r3 + 5179 0028 03D8 bhi .L420 +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5180 .loc 1 2956 45 discriminator 1 view .LVU1621 + 5181 002a 6368 ldr r3, [r4, #4] +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5182 .loc 1 2956 36 discriminator 1 view .LVU1622 + 5183 002c B3F1405F cmp r3, #805306368 + 5184 0030 17D0 beq .L423 + 5185 .L420: +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5186 .loc 1 2963 5 is_stmt 1 view .LVU1623 +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5187 .loc 1 2963 19 is_stmt 0 view .LVU1624 + 5188 0032 2268 ldr r2, [r4] +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5189 .loc 1 2963 38 view .LVU1625 + 5190 0034 6368 ldr r3, [r4, #4] +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5191 .loc 1 2963 31 view .LVU1626 + 5192 0036 1A43 orrs r2, r2, r3 +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5193 .loc 1 2963 54 view .LVU1627 + 5194 0038 A368 ldr r3, [r4, #8] +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5195 .loc 1 2963 11 view .LVU1628 + 5196 003a 1A43 orrs r2, r2, r3 + 5197 .LVL545: + 5198 .L421: +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + 5199 .loc 1 2966 3 is_stmt 1 view .LVU1629 +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + 5200 .loc 1 2966 17 is_stmt 0 view .LVU1630 + 5201 003c E368 ldr r3, [r4, #12] +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + 5202 .loc 1 2966 9 view .LVU1631 + 5203 003e 1343 orrs r3, r3, r2 + 5204 .LVL546: +2968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value); + 5205 .loc 1 2968 3 is_stmt 1 view .LVU1632 +2968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value); + 5206 .loc 1 2968 18 is_stmt 0 view .LVU1633 + 5207 0040 2269 ldr r2, [r4, #16] +2968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** WRITE_REG(CRS->CFGR, value); + 5208 .loc 1 2968 9 view .LVU1634 + 5209 0042 43EA0242 orr r2, r3, r2, lsl #16 + 5210 .LVL547: +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5211 .loc 1 2969 3 is_stmt 1 view .LVU1635 + 5212 0046 0A4B ldr r3, .L424+4 + 5213 0048 5A60 str r2, [r3, #4] +2973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5214 .loc 1 2973 3 view .LVU1636 + 5215 004a 1A68 ldr r2, [r3] + 5216 .LVL548: +2973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5217 .loc 1 2973 3 is_stmt 0 view .LVU1637 + ARM GAS /tmp/ccSY6g1k.s page 180 + + + 5218 004c 22F47C52 bic r2, r2, #16128 + 5219 0050 6169 ldr r1, [r4, #20] + 5220 0052 42EA0122 orr r2, r2, r1, lsl #8 + 5221 0056 1A60 str r2, [r3] + 5222 .LVL549: +2978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5223 .loc 1 2978 3 is_stmt 1 view .LVU1638 + 5224 0058 1A68 ldr r2, [r3] + 5225 005a 42F06002 orr r2, r2, #96 + 5226 005e 1A60 str r2, [r3] +2979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5227 .loc 1 2979 1 is_stmt 0 view .LVU1639 + 5228 0060 10BD pop {r4, pc} + 5229 .LVL550: + 5230 .L423: +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5231 .loc 1 2959 5 is_stmt 1 view .LVU1640 +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5232 .loc 1 2959 19 is_stmt 0 view .LVU1641 + 5233 0062 2268 ldr r2, [r4] +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5234 .loc 1 2959 64 view .LVU1642 + 5235 0064 A368 ldr r3, [r4, #8] +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5236 .loc 1 2959 11 view .LVU1643 + 5237 0066 1A43 orrs r2, r2, r3 + 5238 .LVL551: +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5239 .loc 1 2959 11 view .LVU1644 + 5240 0068 E8E7 b .L421 + 5241 .L425: + 5242 006a 00BF .align 2 + 5243 .L424: + 5244 006c 00440258 .word 1476543488 + 5245 0070 00840040 .word 1073775616 + 5246 .cfi_endproc + 5247 .LFE156: + 5249 .section .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate,"ax",%progbits + 5250 .align 1 + 5251 .global HAL_RCCEx_CRSSoftwareSynchronizationGenerate + 5252 .syntax unified + 5253 .thumb + 5254 .thumb_func + 5255 .fpu fpv5-d16 + 5257 HAL_RCCEx_CRSSoftwareSynchronizationGenerate: + 5258 .LFB157: +2986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** SET_BIT(CRS->CR, CRS_CR_SWSYNC); + 5259 .loc 1 2986 1 is_stmt 1 view -0 + 5260 .cfi_startproc + 5261 @ args = 0, pretend = 0, frame = 0 + 5262 @ frame_needed = 0, uses_anonymous_args = 0 + 5263 @ link register save eliminated. +2987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5264 .loc 1 2987 3 view .LVU1646 + 5265 0000 024A ldr r2, .L427 + 5266 0002 1368 ldr r3, [r2] + 5267 0004 43F08003 orr r3, r3, #128 + ARM GAS /tmp/ccSY6g1k.s page 181 + + + 5268 0008 1360 str r3, [r2] +2988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5269 .loc 1 2988 1 is_stmt 0 view .LVU1647 + 5270 000a 7047 bx lr + 5271 .L428: + 5272 .align 2 + 5273 .L427: + 5274 000c 00840040 .word 1073775616 + 5275 .cfi_endproc + 5276 .LFE157: + 5278 .section .text.HAL_RCCEx_CRSGetSynchronizationInfo,"ax",%progbits + 5279 .align 1 + 5280 .global HAL_RCCEx_CRSGetSynchronizationInfo + 5281 .syntax unified + 5282 .thumb + 5283 .thumb_func + 5284 .fpu fpv5-d16 + 5286 HAL_RCCEx_CRSGetSynchronizationInfo: + 5287 .LVL552: + 5288 .LFB158: +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check the parameter */ + 5289 .loc 1 2996 1 is_stmt 1 view -0 + 5290 .cfi_startproc + 5291 @ args = 0, pretend = 0, frame = 0 + 5292 @ frame_needed = 0, uses_anonymous_args = 0 + 5293 @ link register save eliminated. +2998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5294 .loc 1 2998 3 view .LVU1649 +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5295 .loc 1 3001 3 view .LVU1650 +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5296 .loc 1 3001 42 is_stmt 0 view .LVU1651 + 5297 0000 074B ldr r3, .L430 + 5298 0002 5A68 ldr r2, [r3, #4] +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5299 .loc 1 3001 31 view .LVU1652 + 5300 0004 92B2 uxth r2, r2 +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5301 .loc 1 3001 29 view .LVU1653 + 5302 0006 0260 str r2, [r0] +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5303 .loc 1 3004 3 is_stmt 1 view .LVU1654 +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5304 .loc 1 3004 52 is_stmt 0 view .LVU1655 + 5305 0008 1A68 ldr r2, [r3] +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5306 .loc 1 3004 41 view .LVU1656 + 5307 000a C2F30522 ubfx r2, r2, #8, #6 +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5308 .loc 1 3004 39 view .LVU1657 + 5309 000e 4260 str r2, [r0, #4] +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5310 .loc 1 3007 3 is_stmt 1 view .LVU1658 +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5311 .loc 1 3007 47 is_stmt 0 view .LVU1659 + 5312 0010 9A68 ldr r2, [r3, #8] +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 182 + + + 5313 .loc 1 3007 36 view .LVU1660 + 5314 0012 120C lsrs r2, r2, #16 +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5315 .loc 1 3007 34 view .LVU1661 + 5316 0014 8260 str r2, [r0, #8] +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5317 .loc 1 3010 3 is_stmt 1 view .LVU1662 +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5318 .loc 1 3010 49 is_stmt 0 view .LVU1663 + 5319 0016 9B68 ldr r3, [r3, #8] +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5320 .loc 1 3010 38 view .LVU1664 + 5321 0018 03F40043 and r3, r3, #32768 +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5322 .loc 1 3010 36 view .LVU1665 + 5323 001c C360 str r3, [r0, #12] +3011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5324 .loc 1 3011 1 view .LVU1666 + 5325 001e 7047 bx lr + 5326 .L431: + 5327 .align 2 + 5328 .L430: + 5329 0020 00840040 .word 1073775616 + 5330 .cfi_endproc + 5331 .LFE158: + 5333 .section .text.HAL_RCCEx_CRSWaitSynchronization,"ax",%progbits + 5334 .align 1 + 5335 .global HAL_RCCEx_CRSWaitSynchronization + 5336 .syntax unified + 5337 .thumb + 5338 .thumb_func + 5339 .fpu fpv5-d16 + 5341 HAL_RCCEx_CRSWaitSynchronization: + 5342 .LVL553: + 5343 .LFB159: +3029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t crsstatus = RCC_CRS_NONE; + 5344 .loc 1 3029 1 is_stmt 1 view -0 + 5345 .cfi_startproc + 5346 @ args = 0, pretend = 0, frame = 0 + 5347 @ frame_needed = 0, uses_anonymous_args = 0 +3029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t crsstatus = RCC_CRS_NONE; + 5348 .loc 1 3029 1 is_stmt 0 view .LVU1668 + 5349 0000 70B5 push {r4, r5, r6, lr} + 5350 .LCFI16: + 5351 .cfi_def_cfa_offset 16 + 5352 .cfi_offset 4, -16 + 5353 .cfi_offset 5, -12 + 5354 .cfi_offset 6, -8 + 5355 .cfi_offset 14, -4 + 5356 0002 0546 mov r5, r0 +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 5357 .loc 1 3030 3 is_stmt 1 view .LVU1669 + 5358 .LVL554: +3031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5359 .loc 1 3031 3 view .LVU1670 +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5360 .loc 1 3034 3 view .LVU1671 + ARM GAS /tmp/ccSY6g1k.s page 183 + + +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5361 .loc 1 3034 15 is_stmt 0 view .LVU1672 + 5362 0004 FFF7FEFF bl HAL_GetTick + 5363 .LVL555: +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5364 .loc 1 3034 15 view .LVU1673 + 5365 0008 0646 mov r6, r0 + 5366 .LVL556: +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t tickstart; + 5367 .loc 1 3030 12 view .LVU1674 + 5368 000a 0024 movs r4, #0 + 5369 000c 0EE0 b .L440 + 5370 .LVL557: + 5371 .L445: +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5372 .loc 1 3041 7 is_stmt 1 view .LVU1675 +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5373 .loc 1 3041 12 is_stmt 0 view .LVU1676 + 5374 000e FFF7FEFF bl HAL_GetTick + 5375 .LVL558: +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5376 .loc 1 3041 26 view .LVU1677 + 5377 0012 801B subs r0, r0, r6 +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5378 .loc 1 3041 9 view .LVU1678 + 5379 0014 A842 cmp r0, r5 + 5380 0016 02D8 bhi .L441 +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5381 .loc 1 3041 50 discriminator 1 view .LVU1679 + 5382 0018 5DB9 cbnz r5, .L433 +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5383 .loc 1 3043 19 view .LVU1680 + 5384 001a 0124 movs r4, #1 + 5385 .LVL559: +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5386 .loc 1 3043 19 view .LVU1681 + 5387 001c 09E0 b .L433 + 5388 .LVL560: + 5389 .L441: +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5390 .loc 1 3043 19 view .LVU1682 + 5391 001e 0124 movs r4, #1 + 5392 .LVL561: +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5393 .loc 1 3043 19 view .LVU1683 + 5394 0020 07E0 b .L433 + 5395 .LVL562: + 5396 .L446: +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5397 .loc 1 3100 7 is_stmt 1 discriminator 2 view .LVU1684 +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5398 .loc 1 3100 7 discriminator 2 view .LVU1685 +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5399 .loc 1 3100 7 discriminator 2 view .LVU1686 + 5400 0022 214B ldr r3, .L447 + 5401 0024 0822 movs r2, #8 + 5402 0026 DA60 str r2, [r3, #12] + ARM GAS /tmp/ccSY6g1k.s page 184 + + + 5403 .L439: +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5404 .loc 1 3100 7 discriminator 4 view .LVU1687 +3102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5405 .loc 1 3102 10 discriminator 4 view .LVU1688 +3102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5406 .loc 1 3102 3 is_stmt 0 discriminator 4 view .LVU1689 + 5407 0028 002C cmp r4, #0 + 5408 002a 3AD1 bne .L444 + 5409 .LVL563: + 5410 .L440: +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5411 .loc 1 3037 3 is_stmt 1 view .LVU1690 +3039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5412 .loc 1 3039 5 view .LVU1691 +3039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5413 .loc 1 3039 7 is_stmt 0 view .LVU1692 + 5414 002c B5F1FF3F cmp r5, #-1 + 5415 0030 EDD1 bne .L445 + 5416 .LVL564: + 5417 .L433: +3047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5418 .loc 1 3047 5 is_stmt 1 view .LVU1693 +3047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5419 .loc 1 3047 8 is_stmt 0 view .LVU1694 + 5420 0032 1D4B ldr r3, .L447 + 5421 0034 9B68 ldr r3, [r3, #8] +3047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5422 .loc 1 3047 7 view .LVU1695 + 5423 0036 13F0010F tst r3, #1 + 5424 003a 04D0 beq .L434 +3050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5425 .loc 1 3050 7 is_stmt 1 view .LVU1696 +3050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5426 .loc 1 3050 17 is_stmt 0 view .LVU1697 + 5427 003c 44F00204 orr r4, r4, #2 + 5428 .LVL565: +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5429 .loc 1 3053 7 is_stmt 1 view .LVU1698 +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5430 .loc 1 3053 7 view .LVU1699 +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5431 .loc 1 3053 7 view .LVU1700 + 5432 0040 194B ldr r3, .L447 + 5433 0042 0122 movs r2, #1 + 5434 0044 DA60 str r2, [r3, #12] + 5435 .L434: +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5436 .loc 1 3053 7 discriminator 4 view .LVU1701 +3057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5437 .loc 1 3057 5 discriminator 4 view .LVU1702 +3057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5438 .loc 1 3057 8 is_stmt 0 discriminator 4 view .LVU1703 + 5439 0046 184B ldr r3, .L447 + 5440 0048 9B68 ldr r3, [r3, #8] +3057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5441 .loc 1 3057 7 discriminator 4 view .LVU1704 + ARM GAS /tmp/ccSY6g1k.s page 185 + + + 5442 004a 13F0020F tst r3, #2 + 5443 004e 04D0 beq .L435 +3060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5444 .loc 1 3060 7 is_stmt 1 view .LVU1705 +3060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5445 .loc 1 3060 17 is_stmt 0 view .LVU1706 + 5446 0050 44F00404 orr r4, r4, #4 + 5447 .LVL566: +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5448 .loc 1 3063 7 is_stmt 1 view .LVU1707 +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5449 .loc 1 3063 7 view .LVU1708 +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5450 .loc 1 3063 7 view .LVU1709 + 5451 0054 144B ldr r3, .L447 + 5452 0056 0222 movs r2, #2 + 5453 0058 DA60 str r2, [r3, #12] + 5454 .L435: +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5455 .loc 1 3063 7 discriminator 4 view .LVU1710 +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5456 .loc 1 3067 5 discriminator 4 view .LVU1711 +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5457 .loc 1 3067 8 is_stmt 0 discriminator 4 view .LVU1712 + 5458 005a 134B ldr r3, .L447 + 5459 005c 9B68 ldr r3, [r3, #8] +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5460 .loc 1 3067 7 discriminator 4 view .LVU1713 + 5461 005e 13F4806F tst r3, #1024 + 5462 0062 04D0 beq .L436 +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5463 .loc 1 3070 7 is_stmt 1 view .LVU1714 +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5464 .loc 1 3070 17 is_stmt 0 view .LVU1715 + 5465 0064 44F02004 orr r4, r4, #32 + 5466 .LVL567: +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5467 .loc 1 3073 7 is_stmt 1 view .LVU1716 +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5468 .loc 1 3073 7 view .LVU1717 +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5469 .loc 1 3073 7 view .LVU1718 + 5470 0068 0F4B ldr r3, .L447 + 5471 006a 0422 movs r2, #4 + 5472 006c DA60 str r2, [r3, #12] + 5473 .L436: +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5474 .loc 1 3073 7 discriminator 4 view .LVU1719 +3077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5475 .loc 1 3077 5 discriminator 4 view .LVU1720 +3077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5476 .loc 1 3077 8 is_stmt 0 discriminator 4 view .LVU1721 + 5477 006e 0E4B ldr r3, .L447 + 5478 0070 9B68 ldr r3, [r3, #8] +3077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5479 .loc 1 3077 7 discriminator 4 view .LVU1722 + 5480 0072 13F4807F tst r3, #256 + ARM GAS /tmp/ccSY6g1k.s page 186 + + + 5481 0076 04D0 beq .L437 +3080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5482 .loc 1 3080 7 is_stmt 1 view .LVU1723 +3080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5483 .loc 1 3080 17 is_stmt 0 view .LVU1724 + 5484 0078 44F00804 orr r4, r4, #8 + 5485 .LVL568: +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5486 .loc 1 3083 7 is_stmt 1 view .LVU1725 +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5487 .loc 1 3083 7 view .LVU1726 +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5488 .loc 1 3083 7 view .LVU1727 + 5489 007c 0A4B ldr r3, .L447 + 5490 007e 0422 movs r2, #4 + 5491 0080 DA60 str r2, [r3, #12] + 5492 .L437: +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5493 .loc 1 3083 7 discriminator 4 view .LVU1728 +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5494 .loc 1 3087 5 discriminator 4 view .LVU1729 +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5495 .loc 1 3087 8 is_stmt 0 discriminator 4 view .LVU1730 + 5496 0082 094B ldr r3, .L447 + 5497 0084 9B68 ldr r3, [r3, #8] +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5498 .loc 1 3087 7 discriminator 4 view .LVU1731 + 5499 0086 13F4007F tst r3, #512 + 5500 008a 04D0 beq .L438 +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5501 .loc 1 3090 7 is_stmt 1 view .LVU1732 +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5502 .loc 1 3090 17 is_stmt 0 view .LVU1733 + 5503 008c 44F01004 orr r4, r4, #16 + 5504 .LVL569: +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5505 .loc 1 3093 7 is_stmt 1 view .LVU1734 +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5506 .loc 1 3093 7 view .LVU1735 +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5507 .loc 1 3093 7 view .LVU1736 + 5508 0090 054B ldr r3, .L447 + 5509 0092 0422 movs r2, #4 + 5510 0094 DA60 str r2, [r3, #12] + 5511 .L438: +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5512 .loc 1 3093 7 discriminator 4 view .LVU1737 +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5513 .loc 1 3097 5 discriminator 4 view .LVU1738 +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5514 .loc 1 3097 8 is_stmt 0 discriminator 4 view .LVU1739 + 5515 0096 044B ldr r3, .L447 + 5516 0098 9B68 ldr r3, [r3, #8] +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5517 .loc 1 3097 7 discriminator 4 view .LVU1740 + 5518 009a 13F0080F tst r3, #8 + 5519 009e C3D0 beq .L439 + ARM GAS /tmp/ccSY6g1k.s page 187 + + +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5520 .loc 1 3097 7 discriminator 4 view .LVU1741 + 5521 00a0 BFE7 b .L446 + 5522 .L444: +3104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5523 .loc 1 3104 3 is_stmt 1 view .LVU1742 +3105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5524 .loc 1 3105 1 is_stmt 0 view .LVU1743 + 5525 00a2 2046 mov r0, r4 + 5526 00a4 70BD pop {r4, r5, r6, pc} + 5527 .LVL570: + 5528 .L448: +3105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5529 .loc 1 3105 1 view .LVU1744 + 5530 00a6 00BF .align 2 + 5531 .L447: + 5532 00a8 00840040 .word 1073775616 + 5533 .cfi_endproc + 5534 .LFE159: + 5536 .section .text.HAL_RCCEx_CRS_SyncOkCallback,"ax",%progbits + 5537 .align 1 + 5538 .weak HAL_RCCEx_CRS_SyncOkCallback + 5539 .syntax unified + 5540 .thumb + 5541 .thumb_func + 5542 .fpu fpv5-d16 + 5544 HAL_RCCEx_CRS_SyncOkCallback: + 5545 .LFB161: +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 5546 .loc 1 3177 1 is_stmt 1 view -0 + 5547 .cfi_startproc + 5548 @ args = 0, pretend = 0, frame = 0 + 5549 @ frame_needed = 0, uses_anonymous_args = 0 + 5550 @ link register save eliminated. +3181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5551 .loc 1 3181 1 view .LVU1746 + 5552 0000 7047 bx lr + 5553 .cfi_endproc + 5554 .LFE161: + 5556 .section .text.HAL_RCCEx_CRS_SyncWarnCallback,"ax",%progbits + 5557 .align 1 + 5558 .weak HAL_RCCEx_CRS_SyncWarnCallback + 5559 .syntax unified + 5560 .thumb + 5561 .thumb_func + 5562 .fpu fpv5-d16 + 5564 HAL_RCCEx_CRS_SyncWarnCallback: + 5565 .LFB162: +3188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 5566 .loc 1 3188 1 view -0 + 5567 .cfi_startproc + 5568 @ args = 0, pretend = 0, frame = 0 + 5569 @ frame_needed = 0, uses_anonymous_args = 0 + 5570 @ link register save eliminated. +3192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5571 .loc 1 3192 1 view .LVU1748 + 5572 0000 7047 bx lr + ARM GAS /tmp/ccSY6g1k.s page 188 + + + 5573 .cfi_endproc + 5574 .LFE162: + 5576 .section .text.HAL_RCCEx_CRS_ExpectedSyncCallback,"ax",%progbits + 5577 .align 1 + 5578 .weak HAL_RCCEx_CRS_ExpectedSyncCallback + 5579 .syntax unified + 5580 .thumb + 5581 .thumb_func + 5582 .fpu fpv5-d16 + 5584 HAL_RCCEx_CRS_ExpectedSyncCallback: + 5585 .LFB163: +3199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 5586 .loc 1 3199 1 view -0 + 5587 .cfi_startproc + 5588 @ args = 0, pretend = 0, frame = 0 + 5589 @ frame_needed = 0, uses_anonymous_args = 0 + 5590 @ link register save eliminated. +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5591 .loc 1 3203 1 view .LVU1750 + 5592 0000 7047 bx lr + 5593 .cfi_endproc + 5594 .LFE163: + 5596 .section .text.HAL_RCCEx_CRS_ErrorCallback,"ax",%progbits + 5597 .align 1 + 5598 .weak HAL_RCCEx_CRS_ErrorCallback + 5599 .syntax unified + 5600 .thumb + 5601 .thumb_func + 5602 .fpu fpv5-d16 + 5604 HAL_RCCEx_CRS_ErrorCallback: + 5605 .LVL571: + 5606 .LFB164: +3215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 5607 .loc 1 3215 1 view -0 + 5608 .cfi_startproc + 5609 @ args = 0, pretend = 0, frame = 0 + 5610 @ frame_needed = 0, uses_anonymous_args = 0 + 5611 @ link register save eliminated. +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5612 .loc 1 3217 3 view .LVU1752 +3222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5613 .loc 1 3222 1 is_stmt 0 view .LVU1753 + 5614 0000 7047 bx lr + 5615 .cfi_endproc + 5616 .LFE164: + 5618 .section .text.HAL_RCCEx_CRS_IRQHandler,"ax",%progbits + 5619 .align 1 + 5620 .global HAL_RCCEx_CRS_IRQHandler + 5621 .syntax unified + 5622 .thumb + 5623 .thumb_func + 5624 .fpu fpv5-d16 + 5626 HAL_RCCEx_CRS_IRQHandler: + 5627 .LFB160: +3112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t crserror = RCC_CRS_NONE; + 5628 .loc 1 3112 1 is_stmt 1 view -0 + 5629 .cfi_startproc + ARM GAS /tmp/ccSY6g1k.s page 189 + + + 5630 @ args = 0, pretend = 0, frame = 0 + 5631 @ frame_needed = 0, uses_anonymous_args = 0 + 5632 0000 08B5 push {r3, lr} + 5633 .LCFI17: + 5634 .cfi_def_cfa_offset 8 + 5635 .cfi_offset 3, -8 + 5636 .cfi_offset 14, -4 +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Get current IT flags and IT sources values */ + 5637 .loc 1 3113 3 view .LVU1755 + 5638 .LVL572: +3115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR); + 5639 .loc 1 3115 3 view .LVU1756 +3115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** uint32_t itsources = READ_REG(CRS->CR); + 5640 .loc 1 3115 12 is_stmt 0 view .LVU1757 + 5641 0002 204A ldr r2, .L466 + 5642 0004 9368 ldr r3, [r2, #8] + 5643 .LVL573: +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5644 .loc 1 3116 3 is_stmt 1 view .LVU1758 +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5645 .loc 1 3116 12 is_stmt 0 view .LVU1759 + 5646 0006 1268 ldr r2, [r2] + 5647 .LVL574: +3119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5648 .loc 1 3119 3 is_stmt 1 view .LVU1760 +3119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5649 .loc 1 3119 5 is_stmt 0 view .LVU1761 + 5650 0008 13F0010F tst r3, #1 + 5651 000c 02D0 beq .L454 +3119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5652 .loc 1 3119 46 discriminator 1 view .LVU1762 + 5653 000e 12F0010F tst r2, #1 + 5654 0012 25D1 bne .L463 + 5655 .L454: +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5656 .loc 1 3128 8 is_stmt 1 view .LVU1763 +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5657 .loc 1 3128 10 is_stmt 0 view .LVU1764 + 5658 0014 13F0020F tst r3, #2 + 5659 0018 02D0 beq .L456 +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5660 .loc 1 3128 53 discriminator 1 view .LVU1765 + 5661 001a 12F0020F tst r2, #2 + 5662 001e 25D1 bne .L464 + 5663 .L456: +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5664 .loc 1 3137 8 is_stmt 1 view .LVU1766 +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5665 .loc 1 3137 10 is_stmt 0 view .LVU1767 + 5666 0020 13F0080F tst r3, #8 + 5667 0024 02D0 beq .L457 +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5668 .loc 1 3137 50 discriminator 1 view .LVU1768 + 5669 0026 12F0080F tst r2, #8 + 5670 002a 25D1 bne .L465 + 5671 .L457: +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccSY6g1k.s page 190 + + + 5672 .loc 1 3148 5 is_stmt 1 view .LVU1769 +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5673 .loc 1 3148 7 is_stmt 0 view .LVU1770 + 5674 002c 13F0040F tst r3, #4 + 5675 0030 1BD0 beq .L453 +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5676 .loc 1 3148 45 discriminator 1 view .LVU1771 + 5677 0032 12F0040F tst r2, #4 + 5678 0036 18D0 beq .L453 +3150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5679 .loc 1 3150 7 is_stmt 1 view .LVU1772 +3150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5680 .loc 1 3150 9 is_stmt 0 view .LVU1773 + 5681 0038 13F48070 ands r0, r3, #256 + 5682 003c 00D0 beq .L458 +3152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5683 .loc 1 3152 18 view .LVU1774 + 5684 003e 0820 movs r0, #8 + 5685 .L458: + 5686 .LVL575: +3154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5687 .loc 1 3154 7 is_stmt 1 view .LVU1775 +3154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5688 .loc 1 3154 9 is_stmt 0 view .LVU1776 + 5689 0040 13F4007F tst r3, #512 + 5690 0044 01D0 beq .L459 +3156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5691 .loc 1 3156 9 is_stmt 1 view .LVU1777 +3156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5692 .loc 1 3156 18 is_stmt 0 view .LVU1778 + 5693 0046 40F01000 orr r0, r0, #16 + 5694 .LVL576: + 5695 .L459: +3158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5696 .loc 1 3158 7 is_stmt 1 view .LVU1779 +3158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5697 .loc 1 3158 9 is_stmt 0 view .LVU1780 + 5698 004a 13F4806F tst r3, #1024 + 5699 004e 01D0 beq .L460 +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5700 .loc 1 3160 9 is_stmt 1 view .LVU1781 +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5701 .loc 1 3160 18 is_stmt 0 view .LVU1782 + 5702 0050 40F02000 orr r0, r0, #32 + 5703 .LVL577: + 5704 .L460: +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5705 .loc 1 3164 7 is_stmt 1 view .LVU1783 + 5706 0054 0B4B ldr r3, .L466 + 5707 .LVL578: +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5708 .loc 1 3164 7 is_stmt 0 view .LVU1784 + 5709 0056 0422 movs r2, #4 + 5710 .LVL579: +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5711 .loc 1 3164 7 view .LVU1785 + 5712 0058 DA60 str r2, [r3, #12] + ARM GAS /tmp/ccSY6g1k.s page 191 + + +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5713 .loc 1 3167 7 is_stmt 1 view .LVU1786 + 5714 005a FFF7FEFF bl HAL_RCCEx_CRS_ErrorCallback + 5715 .LVL580: +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5716 .loc 1 3170 1 is_stmt 0 view .LVU1787 + 5717 005e 04E0 b .L453 + 5718 .LVL581: + 5719 .L463: +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5720 .loc 1 3122 5 is_stmt 1 view .LVU1788 + 5721 0060 084B ldr r3, .L466 + 5722 .LVL582: +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5723 .loc 1 3122 5 is_stmt 0 view .LVU1789 + 5724 0062 0122 movs r2, #1 + 5725 .LVL583: +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5726 .loc 1 3122 5 view .LVU1790 + 5727 0064 DA60 str r2, [r3, #12] +3125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5728 .loc 1 3125 5 is_stmt 1 view .LVU1791 + 5729 0066 FFF7FEFF bl HAL_RCCEx_CRS_SyncOkCallback + 5730 .LVL584: + 5731 .L453: +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5732 .loc 1 3170 1 is_stmt 0 view .LVU1792 + 5733 006a 08BD pop {r3, pc} + 5734 .LVL585: + 5735 .L464: +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5736 .loc 1 3131 5 is_stmt 1 view .LVU1793 + 5737 006c 054B ldr r3, .L466 + 5738 .LVL586: +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5739 .loc 1 3131 5 is_stmt 0 view .LVU1794 + 5740 006e 0222 movs r2, #2 + 5741 .LVL587: +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5742 .loc 1 3131 5 view .LVU1795 + 5743 0070 DA60 str r2, [r3, #12] +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5744 .loc 1 3134 5 is_stmt 1 view .LVU1796 + 5745 0072 FFF7FEFF bl HAL_RCCEx_CRS_SyncWarnCallback + 5746 .LVL588: + 5747 0076 F8E7 b .L453 + 5748 .LVL589: + 5749 .L465: +3140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5750 .loc 1 3140 5 view .LVU1797 + 5751 0078 024B ldr r3, .L466 + 5752 .LVL590: +3140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5753 .loc 1 3140 5 is_stmt 0 view .LVU1798 + 5754 007a 0822 movs r2, #8 + 5755 .LVL591: +3140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccSY6g1k.s page 192 + + + 5756 .loc 1 3140 5 view .LVU1799 + 5757 007c DA60 str r2, [r3, #12] +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + 5758 .loc 1 3143 5 is_stmt 1 view .LVU1800 + 5759 007e FFF7FEFF bl HAL_RCCEx_CRS_ExpectedSyncCallback + 5760 .LVL592: + 5761 0082 F2E7 b .L453 + 5762 .L467: + 5763 .align 2 + 5764 .L466: + 5765 0084 00840040 .word 1073775616 + 5766 .cfi_endproc + 5767 .LFE160: + 5769 .section .text.HAL_RCCEx_LSECSS_Callback,"ax",%progbits + 5770 .align 1 + 5771 .weak HAL_RCCEx_LSECSS_Callback + 5772 .syntax unified + 5773 .thumb + 5774 .thumb_func + 5775 .fpu fpv5-d16 + 5777 HAL_RCCEx_LSECSS_Callback: + 5778 .LFB168: +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief Handle the RCC LSE Clock Security System interrupt request. +3445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval None +3446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** void HAL_RCCEx_LSECSS_IRQHandler(void) +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check RCC LSE CSSF flag */ +3450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) +3451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Clear RCC LSE CSS pending bit */ +3454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); +3455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* RCC LSE Clock Security System interrupt user callback */ +3457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** HAL_RCCEx_LSECSS_Callback(); +3458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } +3461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** +3462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /** +3463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @brief RCCEx LSE Clock Security System interrupt callback. +3464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** * @retval none +3465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** __weak void HAL_RCCEx_LSECSS_Callback(void) +3467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5779 .loc 1 3467 1 view -0 + 5780 .cfi_startproc + 5781 @ args = 0, pretend = 0, frame = 0 + 5782 @ frame_needed = 0, uses_anonymous_args = 0 + 5783 @ link register save eliminated. +3468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +3469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file +3470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** */ +3471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccSY6g1k.s page 193 + + + 5784 .loc 1 3471 1 view .LVU1802 + 5785 0000 7047 bx lr + 5786 .cfi_endproc + 5787 .LFE168: + 5789 .section .text.HAL_RCCEx_LSECSS_IRQHandler,"ax",%progbits + 5790 .align 1 + 5791 .global HAL_RCCEx_LSECSS_IRQHandler + 5792 .syntax unified + 5793 .thumb + 5794 .thumb_func + 5795 .fpu fpv5-d16 + 5797 HAL_RCCEx_LSECSS_IRQHandler: + 5798 .LFB167: +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** /* Check RCC LSE CSSF flag */ + 5799 .loc 1 3448 1 view -0 + 5800 .cfi_startproc + 5801 @ args = 0, pretend = 0, frame = 0 + 5802 @ frame_needed = 0, uses_anonymous_args = 0 + 5803 0000 08B5 push {r3, lr} + 5804 .LCFI18: + 5805 .cfi_def_cfa_offset 8 + 5806 .cfi_offset 3, -8 + 5807 .cfi_offset 14, -4 +3450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5808 .loc 1 3450 3 view .LVU1804 +3450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5809 .loc 1 3450 6 is_stmt 0 view .LVU1805 + 5810 0002 064B ldr r3, .L473 + 5811 0004 5B6E ldr r3, [r3, #100] +3450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** { + 5812 .loc 1 3450 5 view .LVU1806 + 5813 0006 13F4007F tst r3, #512 + 5814 000a 00D1 bne .L472 + 5815 .L469: +3460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5816 .loc 1 3460 1 view .LVU1807 + 5817 000c 08BD pop {r3, pc} + 5818 .L472: +3454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5819 .loc 1 3454 5 is_stmt 1 view .LVU1808 + 5820 000e 034B ldr r3, .L473 + 5821 0010 4FF40072 mov r2, #512 + 5822 0014 9A66 str r2, [r3, #104] +3457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5823 .loc 1 3457 5 view .LVU1809 + 5824 0016 FFF7FEFF bl HAL_RCCEx_LSECSS_Callback + 5825 .LVL593: +3460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c **** + 5826 .loc 1 3460 1 is_stmt 0 view .LVU1810 + 5827 001a F7E7 b .L469 + 5828 .L474: + 5829 .align 2 + 5830 .L473: + 5831 001c 00440258 .word 1476543488 + 5832 .cfi_endproc + 5833 .LFE167: + 5835 .text + ARM GAS /tmp/ccSY6g1k.s page 194 + + + 5836 .Letext0: + 5837 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 5838 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 5839 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + 5840 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 5841 .file 6 "/usr/arm-none-eabi/include/math.h" + 5842 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 5843 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h" + 5844 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 5845 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" + ARM GAS /tmp/ccSY6g1k.s page 195 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_rcc_ex.c + /tmp/ccSY6g1k.s:17 .text.RCCEx_PLL2_Config:0000000000000000 $t + /tmp/ccSY6g1k.s:24 .text.RCCEx_PLL2_Config:0000000000000000 RCCEx_PLL2_Config + /tmp/ccSY6g1k.s:232 .text.RCCEx_PLL2_Config:0000000000000104 $d + /tmp/ccSY6g1k.s:238 .text.RCCEx_PLL3_Config:0000000000000000 $t + /tmp/ccSY6g1k.s:244 .text.RCCEx_PLL3_Config:0000000000000000 RCCEx_PLL3_Config + /tmp/ccSY6g1k.s:451 .text.RCCEx_PLL3_Config:0000000000000104 $d + /tmp/ccSY6g1k.s:457 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 $t + /tmp/ccSY6g1k.s:464 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 HAL_RCCEx_PeriphCLKConfig + /tmp/ccSY6g1k.s:594 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000084 $d + /tmp/ccSY6g1k.s:1044 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000294 $d + /tmp/ccSY6g1k.s:1048 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000298 $t + /tmp/ccSY6g1k.s:1278 .text.HAL_RCCEx_PeriphCLKConfig:00000000000003c6 $d + /tmp/ccSY6g1k.s:1282 .text.HAL_RCCEx_PeriphCLKConfig:00000000000003ca $t + /tmp/ccSY6g1k.s:1379 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000440 $d + /tmp/ccSY6g1k.s:1451 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000480 $d + /tmp/ccSY6g1k.s:1456 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000484 $t + /tmp/ccSY6g1k.s:1665 .text.HAL_RCCEx_PeriphCLKConfig:000000000000058c $d + /tmp/ccSY6g1k.s:1671 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000592 $t + /tmp/ccSY6g1k.s:1715 .text.HAL_RCCEx_PeriphCLKConfig:00000000000005c4 $d + /tmp/ccSY6g1k.s:1721 .text.HAL_RCCEx_PeriphCLKConfig:00000000000005ca $t + /tmp/ccSY6g1k.s:1931 .text.HAL_RCCEx_PeriphCLKConfig:00000000000006c4 $d + /tmp/ccSY6g1k.s:1937 .text.HAL_RCCEx_PeriphCLKConfig:00000000000006d0 $t + /tmp/ccSY6g1k.s:2483 .text.HAL_RCCEx_PeriphCLKConfig:00000000000009a4 $d + /tmp/ccSY6g1k.s:2488 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 $t + /tmp/ccSY6g1k.s:2495 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 HAL_RCCEx_GetPeriphCLKConfig + /tmp/ccSY6g1k.s:2839 .text.HAL_RCCEx_GetPeriphCLKConfig:00000000000001c4 $d + /tmp/ccSY6g1k.s:2845 .text.HAL_RCCEx_GetD1PCLK1Freq:0000000000000000 $t + /tmp/ccSY6g1k.s:2852 .text.HAL_RCCEx_GetD1PCLK1Freq:0000000000000000 HAL_RCCEx_GetD1PCLK1Freq + /tmp/ccSY6g1k.s:2883 .text.HAL_RCCEx_GetD1PCLK1Freq:000000000000001c $d + /tmp/ccSY6g1k.s:2889 .text.HAL_RCCEx_GetD3PCLK1Freq:0000000000000000 $t + /tmp/ccSY6g1k.s:2896 .text.HAL_RCCEx_GetD3PCLK1Freq:0000000000000000 HAL_RCCEx_GetD3PCLK1Freq + /tmp/ccSY6g1k.s:2927 .text.HAL_RCCEx_GetD3PCLK1Freq:000000000000001c $d + /tmp/ccSY6g1k.s:2933 .text.HAL_RCCEx_GetPLL2ClockFreq:0000000000000000 $t + /tmp/ccSY6g1k.s:2940 .text.HAL_RCCEx_GetPLL2ClockFreq:0000000000000000 HAL_RCCEx_GetPLL2ClockFreq + /tmp/ccSY6g1k.s:3243 .text.HAL_RCCEx_GetPLL2ClockFreq:00000000000001e0 $d + /tmp/ccSY6g1k.s:3253 .text.HAL_RCCEx_GetPLL3ClockFreq:0000000000000000 $t + /tmp/ccSY6g1k.s:3260 .text.HAL_RCCEx_GetPLL3ClockFreq:0000000000000000 HAL_RCCEx_GetPLL3ClockFreq + /tmp/ccSY6g1k.s:3563 .text.HAL_RCCEx_GetPLL3ClockFreq:00000000000001e0 $d + /tmp/ccSY6g1k.s:3573 .text.HAL_RCCEx_GetPLL1ClockFreq:0000000000000000 $t + /tmp/ccSY6g1k.s:3580 .text.HAL_RCCEx_GetPLL1ClockFreq:0000000000000000 HAL_RCCEx_GetPLL1ClockFreq + /tmp/ccSY6g1k.s:3883 .text.HAL_RCCEx_GetPLL1ClockFreq:00000000000001e0 $d + /tmp/ccSY6g1k.s:3893 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 $t + /tmp/ccSY6g1k.s:3900 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 HAL_RCCEx_GetPeriphCLKFreq + /tmp/ccSY6g1k.s:3973 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000054 $d + /tmp/ccSY6g1k.s:4587 .text.HAL_RCCEx_GetPeriphCLKFreq:000000000000029c $d + /tmp/ccSY6g1k.s:4594 .text.HAL_RCCEx_GetPeriphCLKFreq:00000000000002a8 $t + /tmp/ccSY6g1k.s:4859 .text.HAL_RCCEx_GetPeriphCLKFreq:000000000000036c $d + /tmp/ccSY6g1k.s:4868 .text.HAL_RCCEx_GetD1SysClockFreq:0000000000000000 $t + /tmp/ccSY6g1k.s:4875 .text.HAL_RCCEx_GetD1SysClockFreq:0000000000000000 HAL_RCCEx_GetD1SysClockFreq + /tmp/ccSY6g1k.s:4928 .text.HAL_RCCEx_GetD1SysClockFreq:0000000000000034 $d + /tmp/ccSY6g1k.s:4936 .text.HAL_RCCEx_EnableLSECSS:0000000000000000 $t + /tmp/ccSY6g1k.s:4943 .text.HAL_RCCEx_EnableLSECSS:0000000000000000 HAL_RCCEx_EnableLSECSS + /tmp/ccSY6g1k.s:4960 .text.HAL_RCCEx_EnableLSECSS:000000000000000c $d + /tmp/ccSY6g1k.s:4965 .text.HAL_RCCEx_DisableLSECSS:0000000000000000 $t + /tmp/ccSY6g1k.s:4972 .text.HAL_RCCEx_DisableLSECSS:0000000000000000 HAL_RCCEx_DisableLSECSS + ARM GAS /tmp/ccSY6g1k.s page 196 + + + /tmp/ccSY6g1k.s:4993 .text.HAL_RCCEx_DisableLSECSS:0000000000000014 $d + /tmp/ccSY6g1k.s:4998 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000000 $t + /tmp/ccSY6g1k.s:5005 .text.HAL_RCCEx_EnableLSECSS_IT:0000000000000000 HAL_RCCEx_EnableLSECSS_IT + /tmp/ccSY6g1k.s:5035 .text.HAL_RCCEx_EnableLSECSS_IT:000000000000002c $d + /tmp/ccSY6g1k.s:5040 .text.HAL_RCCEx_WakeUpStopCLKConfig:0000000000000000 $t + /tmp/ccSY6g1k.s:5047 .text.HAL_RCCEx_WakeUpStopCLKConfig:0000000000000000 HAL_RCCEx_WakeUpStopCLKConfig + /tmp/ccSY6g1k.s:5067 .text.HAL_RCCEx_WakeUpStopCLKConfig:0000000000000010 $d + /tmp/ccSY6g1k.s:5072 .text.HAL_RCCEx_KerWakeUpStopCLKConfig:0000000000000000 $t + /tmp/ccSY6g1k.s:5079 .text.HAL_RCCEx_KerWakeUpStopCLKConfig:0000000000000000 HAL_RCCEx_KerWakeUpStopCLKConfig + /tmp/ccSY6g1k.s:5099 .text.HAL_RCCEx_KerWakeUpStopCLKConfig:0000000000000010 $d + /tmp/ccSY6g1k.s:5104 .text.HAL_RCCEx_WWDGxSysResetConfig:0000000000000000 $t + /tmp/ccSY6g1k.s:5111 .text.HAL_RCCEx_WWDGxSysResetConfig:0000000000000000 HAL_RCCEx_WWDGxSysResetConfig + /tmp/ccSY6g1k.s:5130 .text.HAL_RCCEx_WWDGxSysResetConfig:0000000000000010 $d + /tmp/ccSY6g1k.s:5135 .text.HAL_RCCEx_CRSConfig:0000000000000000 $t + /tmp/ccSY6g1k.s:5142 .text.HAL_RCCEx_CRSConfig:0000000000000000 HAL_RCCEx_CRSConfig + /tmp/ccSY6g1k.s:5244 .text.HAL_RCCEx_CRSConfig:000000000000006c $d + /tmp/ccSY6g1k.s:5250 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000000000000 $t + /tmp/ccSY6g1k.s:5257 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:0000000000000000 HAL_RCCEx_CRSSoftwareSynchronizationGenerate + /tmp/ccSY6g1k.s:5274 .text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate:000000000000000c $d + /tmp/ccSY6g1k.s:5279 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000000 $t + /tmp/ccSY6g1k.s:5286 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000000 HAL_RCCEx_CRSGetSynchronizationInfo + /tmp/ccSY6g1k.s:5329 .text.HAL_RCCEx_CRSGetSynchronizationInfo:0000000000000020 $d + /tmp/ccSY6g1k.s:5334 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000000 $t + /tmp/ccSY6g1k.s:5341 .text.HAL_RCCEx_CRSWaitSynchronization:0000000000000000 HAL_RCCEx_CRSWaitSynchronization + /tmp/ccSY6g1k.s:5532 .text.HAL_RCCEx_CRSWaitSynchronization:00000000000000a8 $d + /tmp/ccSY6g1k.s:5537 .text.HAL_RCCEx_CRS_SyncOkCallback:0000000000000000 $t + /tmp/ccSY6g1k.s:5544 .text.HAL_RCCEx_CRS_SyncOkCallback:0000000000000000 HAL_RCCEx_CRS_SyncOkCallback + /tmp/ccSY6g1k.s:5557 .text.HAL_RCCEx_CRS_SyncWarnCallback:0000000000000000 $t + /tmp/ccSY6g1k.s:5564 .text.HAL_RCCEx_CRS_SyncWarnCallback:0000000000000000 HAL_RCCEx_CRS_SyncWarnCallback + /tmp/ccSY6g1k.s:5577 .text.HAL_RCCEx_CRS_ExpectedSyncCallback:0000000000000000 $t + /tmp/ccSY6g1k.s:5584 .text.HAL_RCCEx_CRS_ExpectedSyncCallback:0000000000000000 HAL_RCCEx_CRS_ExpectedSyncCallback + /tmp/ccSY6g1k.s:5597 .text.HAL_RCCEx_CRS_ErrorCallback:0000000000000000 $t + /tmp/ccSY6g1k.s:5604 .text.HAL_RCCEx_CRS_ErrorCallback:0000000000000000 HAL_RCCEx_CRS_ErrorCallback + /tmp/ccSY6g1k.s:5619 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000000 $t + /tmp/ccSY6g1k.s:5626 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000000 HAL_RCCEx_CRS_IRQHandler + /tmp/ccSY6g1k.s:5765 .text.HAL_RCCEx_CRS_IRQHandler:0000000000000084 $d + /tmp/ccSY6g1k.s:5770 .text.HAL_RCCEx_LSECSS_Callback:0000000000000000 $t + /tmp/ccSY6g1k.s:5777 .text.HAL_RCCEx_LSECSS_Callback:0000000000000000 HAL_RCCEx_LSECSS_Callback + /tmp/ccSY6g1k.s:5790 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000000 $t + /tmp/ccSY6g1k.s:5797 .text.HAL_RCCEx_LSECSS_IRQHandler:0000000000000000 HAL_RCCEx_LSECSS_IRQHandler + /tmp/ccSY6g1k.s:5831 .text.HAL_RCCEx_LSECSS_IRQHandler:000000000000001c $d + /tmp/ccSY6g1k.s:599 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000089 $d + /tmp/ccSY6g1k.s:599 .text.HAL_RCCEx_PeriphCLKConfig:000000000000008a $t + /tmp/ccSY6g1k.s:1420 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000469 $d + /tmp/ccSY6g1k.s:1420 .text.HAL_RCCEx_PeriphCLKConfig:000000000000046a $t + /tmp/ccSY6g1k.s:3978 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000059 $d + /tmp/ccSY6g1k.s:3978 .text.HAL_RCCEx_GetPeriphCLKFreq:000000000000005a $t + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_RCC_GetHCLKFreq +D1CorePrescTable +HAL_RCC_GetSysClockFreq +SystemD2Clock +SystemCoreClock +HAL_GetREVID diff --git a/build/stm32h7xx_hal_rcc_ex.o b/build/stm32h7xx_hal_rcc_ex.o new file mode 100644 index 0000000..27ff6d8 Binary files /dev/null and b/build/stm32h7xx_hal_rcc_ex.o differ diff --git a/build/stm32h7xx_hal_tim.d b/build/stm32h7xx_hal_tim.d new file mode 100644 index 0000000..1d2ba95 --- /dev/null +++ b/build/stm32h7xx_hal_tim.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_tim.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_tim.lst b/build/stm32h7xx_hal_tim.lst new file mode 100644 index 0000000..988398f --- /dev/null +++ b/build/stm32h7xx_hal_tim.lst @@ -0,0 +1,26 @@ +ARM GAS /tmp/ccUVphj6.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_tim.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .Letext0: + ARM GAS /tmp/ccUVphj6.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_tim.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_tim.o b/build/stm32h7xx_hal_tim.o new file mode 100644 index 0000000..5f801e3 Binary files /dev/null and b/build/stm32h7xx_hal_tim.o differ diff --git a/build/stm32h7xx_hal_tim_ex.d b/build/stm32h7xx_hal_tim_ex.d new file mode 100644 index 0000000..43090d5 --- /dev/null +++ b/build/stm32h7xx_hal_tim_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_tim_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_tim_ex.lst b/build/stm32h7xx_hal_tim_ex.lst new file mode 100644 index 0000000..1388bf9 --- /dev/null +++ b/build/stm32h7xx_hal_tim_ex.lst @@ -0,0 +1,26 @@ +ARM GAS /tmp/cca4BPwk.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_tim_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .Letext0: + ARM GAS /tmp/cca4BPwk.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_tim_ex.c + +NO UNDEFINED SYMBOLS diff --git a/build/stm32h7xx_hal_tim_ex.o b/build/stm32h7xx_hal_tim_ex.o new file mode 100644 index 0000000..216f878 Binary files /dev/null and b/build/stm32h7xx_hal_tim_ex.o differ diff --git a/build/stm32h7xx_hal_uart.d b/build/stm32h7xx_hal_uart.d new file mode 100644 index 0000000..90661c0 --- /dev/null +++ b/build/stm32h7xx_hal_uart.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_uart.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_uart.lst b/build/stm32h7xx_hal_uart.lst new file mode 100644 index 0000000..8c696a9 --- /dev/null +++ b/build/stm32h7xx_hal_uart.lst @@ -0,0 +1,14952 @@ +ARM GAS /tmp/ccizsdzp.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_uart.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.UART_EndTxTransfer,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 UART_EndTxTransfer: + 25 .LVL0: + 26 .LFB187: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @file stm32h7xx_hal_uart.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + IO operation functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + Peripheral Control functions + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @verbatim + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ##### How to use this driver ##### + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The UART HAL driver can be used as follows: + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Enable the USARTx interface clock. + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) UART pins configuration: + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Enable the clock for the UART GPIOs. + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Configure these UART pins as alternate function pull-up. + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and HAL_UART_Receive_IT() APIs): + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Configure the USARTx interrupt priority. + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Enable the NVIC USART IRQ handle. + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) UART interrupts handling: + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** -@@- The specific UART interrupts (Transmission complete interrupt, + ARM GAS /tmp/ccizsdzp.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** inside the transmit and receive processes. + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and HAL_UART_Receive_DMA() APIs): + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Declare a DMA handle structure for the Tx/Rx channel. + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Enable the DMAx interface clock. + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Configure the DMA Tx/Rx channel. + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in the huart handle AdvancedInit structure. + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) For the UART asynchronous mode, initialize the UART registers by calling + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_Init() API. + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) For the UART Half duplex mode, initialize the UART registers by calling + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_HalfDuplex_Init() API. + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** by calling the HAL_LIN_Init() API. + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) For the UART Multiprocessor mode, initialize the UART registers + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** by calling the HAL_MultiProcessor_Init() API. + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** by calling the HAL_RS485Ex_Init() API. + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Ini + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** calling the customized HAL_UART_MspInit() API. + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ##### Callback registration ##### + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ================================== + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** allows the user to configure dynamically the driver callbacks. + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) TxHalfCpltCallback : Tx Half Complete Callback. + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) TxCpltCallback : Tx Complete Callback. + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) RxHalfCpltCallback : Rx Half Complete Callback. + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) RxCpltCallback : Rx Complete Callback. + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) ErrorCallback : Error Callback. + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) AbortCpltCallback : Abort Complete Callback. + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) WakeupCallback : Wakeup Callback. + ARM GAS /tmp/ccizsdzp.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) RxFifoFullCallback : Rx Fifo Full Callback. + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) MspInitCallback : UART MspInit. + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) MspDeInitCallback : UART MspDeInit. + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and a pointer to the user callback function. + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** weak (surcharged) function. + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and the Callback ID. + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This function allows to reset following callbacks: + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) TxHalfCpltCallback : Tx Half Complete Callback. + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) TxCpltCallback : Tx Complete Callback. + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) RxHalfCpltCallback : Rx Half Complete Callback. + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) RxCpltCallback : Rx Complete Callback. + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) ErrorCallback : Error Callback. + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) AbortCpltCallback : Abort Complete Callback. + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) WakeupCallback : Wakeup Callback. + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) RxFifoFullCallback : Rx Fifo Full Callback. + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) MspInitCallback : UART MspInit. + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) MspDeInitCallback : UART MspDeInit. + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** all callbacks are set to the corresponding weak (surcharged) functions: + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Exception done for MspInit and MspDeInit functions that are respectively + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Exception done MspInit/MspDeInit that can be registered/unregistered + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MspInit/DeInit callbacks can be used during the Init/DeInit. + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** In that case first register the MspInit/MspDeInit user callbacks + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** or @ref HAL_UART_Init() function. + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** not defined, the callback registration feature is not available + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and weak (surcharged) callbacks are used. + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @endverbatim + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ****************************************************************************** + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @attention + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *

© Copyright (c) 2017 STMicroelectronics. + ARM GAS /tmp/ccizsdzp.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * All rights reserved.

+ 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This software component is licensed by ST under BSD 3-Clause license, + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the "License"; You may not use this file except in compliance with the + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * License. You may obtain a copy of the License at: + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * opensource.org/licenses/BSD-3-Clause + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ****************************************************************************** + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Includes ------------------------------------------------------------------*/ + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #include "stm32h7xx_hal.h" + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @addtogroup STM32H7xx_HAL_Driver + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART UART + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief HAL UART module driver + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #ifdef HAL_UART_MODULE_ENABLED + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Private typedef -----------------------------------------------------------*/ + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Private define ------------------------------------------------------------*/ + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Private_Constants UART Private Constants + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** USART_CR1_FIFOEN )) /*!< UART or USART C + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Private macros ------------------------------------------------------------*/ + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Private variables ---------------------------------------------------------*/ + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Private function prototypes -----------------------------------------------*/ + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @addtogroup UART_Private_Functions + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart); + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart); + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); + ARM GAS /tmp/ccizsdzp.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma); + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Exported functions --------------------------------------------------------*/ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions UART Exported Functions + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialization and Configuration functions + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @verbatim + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ##### Initialization and Configuration functions ##### + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in asynchronous mode. + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) For the asynchronous mode the parameters below can be configured: + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Baud Rate + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Word Length + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Stop Bit + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in the data register is transmitted but is changed by the parity bit. + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Hardware flow control + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Receiver/transmitter modes + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) Over Sampling Method + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) One-Bit Sampling Method + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) For the asynchronous mode, the following advanced features can be configured as well: + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) TX and/or RX pin level inversion + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) data logical level inversion + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) RX and TX pins swap + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) RX overrun detection disabling + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) DMA disabling on RX error + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) MSB first on communication line + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (++) auto Baud rate detection + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] + ARM GAS /tmp/ccizsdzp.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and UART multiprocessor mode configuration procedures (details for the procedures + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** are available in reference manual). + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @endverbatim + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit, + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** 8-bit or 9-bit), the possible UART formats are listed in the + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** following table. + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Table 1. UART frame format. + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +-----------------------------------------------------------------------+ + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | M1 bit | M0 bit | PCE bit | UART frame | + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | | + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | | + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | | + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** |---------|---------|-----------|---------------------------------------| + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +-----------------------------------------------------------------------+ + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialize the UART mode according to the specified + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and initialize the associated handle. + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart == NULL) + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the parameters */ + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the parameters */ + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + ARM GAS /tmp/ccizsdzp.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware */ + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback(huart); + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* In asynchronous mode, the following bits must be kept cleared: + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialize the half-duplex mode according to the specified + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart == NULL) + ARM GAS /tmp/ccizsdzp.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check UART instance */ + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware */ + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback(huart); + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* In half-duplex mode, the following bits must be kept cleared: + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - SCEN and IREN bits in the USART_CR3 register.*/ + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialize the LIN mode according to the specified + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param BreakDetectLength Specifies the LIN break detection length. + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This parameter can be one of the following values: + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart == NULL) + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the LIN UART instance */ + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the Break detection length parameter */ + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* LIN mode limited to 16-bit oversampling only */ + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* LIN mode limited to 8-bit data length */ + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->Init.WordLength != UART_WORDLENGTH_8B) + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware */ + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback(huart); + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* In LIN mode, the following bits must be kept cleared: + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - SCEN and IREN bits in the USART_CR3 register.*/ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the USART LIN Break detection length. */ + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialize the multiprocessor mode according to the specified + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and initialize the associated handle. + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Address UART node address (4-, 6-, 7- or 8-bit long). + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param WakeUpMethod Specifies the UART wakeup method. + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This parameter can be one of the following values: + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note If the user resorts to idle line detection wake up, the Address parameter + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * is useless and ignored by the initialization function. + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note If the user resorts to address mark wake up, the address length detection + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * is configured by default to 4 bits only. For the UART to be able to + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * manage 6-, 7- or 8-bit long addresses detection, the API + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * HAL_MultiProcessorEx_AddressLength_Set() must be called after + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * HAL_MultiProcessor_Init(). + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t Wake + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart == NULL) + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the wake up method parameter */ + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware */ + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback(huart); + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* In multiprocessor mode, the following bits must be kept cleared: + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* If address mark wake up method is chosen, set the USART address node */ + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS) + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the wake up method by setting the WAKE bit in the CR1 register */ + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DeInitialize the UART peripheral. + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart == NULL) + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the parameters */ + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR1 = 0x0U; + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->MspDeInitCallback == NULL) + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspDeInitCallback = HAL_UART_MspDeInit; + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DeInit the low level hardware */ + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspDeInitCallback(huart); + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DeInit the low level hardware */ + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_MspDeInit(huart); + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialize the UART MSP. + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + ARM GAS /tmp/ccizsdzp.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_MspInit can be implemented in the user file + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DeInitialize the UART MSP. + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_MspDeInit can be implemented in the user file + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Register a User UART Callback + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * To be used instead of the weak predefined callback + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart uart handle + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param CallbackID ID of the callback to be registered + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This parameter can be one of the following values: + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pCallback pointer to the Callback function + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef C + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pUART_CallbackTypeDef pCallback) + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef status = HAL_OK; + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (pCallback == NULL) + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (CallbackID) + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_TX_HALFCOMPLETE_CB_ID : + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxHalfCpltCallback = pCallback; + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_TX_COMPLETE_CB_ID : + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxCpltCallback = pCallback; + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_RX_HALFCOMPLETE_CB_ID : + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxHalfCpltCallback = pCallback; + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_RX_COMPLETE_CB_ID : + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback = pCallback; + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ERROR_CB_ID : + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback = pCallback; + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ABORT_COMPLETE_CB_ID : + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortCpltCallback = pCallback; + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortTransmitCpltCallback = pCallback; + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortReceiveCpltCallback = pCallback; + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_WAKEUP_CB_ID : + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->WakeupCallback = pCallback; + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_RX_FIFO_FULL_CB_ID : + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxFifoFullCallback = pCallback; + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_TX_FIFO_EMPTY_CB_ID : + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxFifoEmptyCallback = pCallback; + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = pCallback; + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspDeInitCallback = pCallback; + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default : + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** status = HAL_ERROR; + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else if (huart->gState == HAL_UART_STATE_RESET) + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (CallbackID) + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = pCallback; + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspDeInitCallback = pCallback; + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default : + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** status = HAL_ERROR; + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** status = HAL_ERROR; + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return status; + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Unregister an UART Callback + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * UART callaback is redirected to the weak predefined callback + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart uart handle + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param CallbackID ID of the callback to be unregistered + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This parameter can be one of the following values: + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + ARM GAS /tmp/ccizsdzp.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef status = HAL_OK; + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_UART_STATE_READY == huart->gState) + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (CallbackID) + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_TX_HALFCOMPLETE_CB_ID : + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHa + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_TX_COMPLETE_CB_ID : + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpl + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_RX_HALFCOMPLETE_CB_ID : + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHal + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_RX_COMPLETE_CB_ID : + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpl + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ERROR_CB_ID : + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak Error + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ABORT_COMPLETE_CB_ID : + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak Abort + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak Abort + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak Abort + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_WAKEUP_CB_ID : + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak Wakeu + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_RX_FIFO_FULL_CB_ID : + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFif + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_TX_FIFO_EMPTY_CB_ID : + ARM GAS /tmp/ccizsdzp.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFif + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspIn + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDe + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default : + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** status = HAL_ERROR; + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else if (HAL_UART_STATE_RESET == huart->gState) + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (CallbackID) + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->MspDeInitCallback = HAL_UART_MspDeInit; + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default : + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** status = HAL_ERROR; + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** status = HAL_ERROR; + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return status; + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group2 IO operation functions + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART Transmit/Receive functions + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * + ARM GAS /tmp/ccizsdzp.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @verbatim + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ##### IO operation functions ##### + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This subsection provides a set of functions allowing to manage the UART asynchronous + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and Half duplex data transfers. + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) There are two mode of transfer: + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) Blocking mode: The communication is performed in polling mode. + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The HAL status of all data processing is returned by the same function + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** after finishing transfer. + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) Non-Blocking mode: The communication is performed using Interrupts + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** or DMA, These API's return the HAL status. + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The end of the data processing will be indicated through the + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** using DMA mode. + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** will be executed respectively at the end of the transmit or Receive process + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** The HAL_UART_ErrorCallback()user callback will be executed when a communication error is + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Blocking mode API's are : + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Transmit() + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Receive() + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Non-Blocking mode API's with Interrupt are : + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Transmit_IT() + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Receive_IT() + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_IRQHandler() + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Non-Blocking mode API's with DMA are : + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Transmit_DMA() + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Receive_DMA() + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_DMAPause() + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_DMAResume() + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_DMAStop() + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_TxHalfCpltCallback() + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_TxCpltCallback() + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_RxHalfCpltCallback() + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_RxCpltCallback() + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_ErrorCallback() + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) Non-Blocking mode transfers could be aborted using Abort API's : + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Abort() + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortTransmit() + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortReceive() + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_Abort_IT() + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortTransmit_IT() + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortReceive_IT() + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Call + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortCpltCallback() + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortTransmitCpltCallback() + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_AbortReceiveCpltCallback() + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + ARM GAS /tmp/ccizsdzp.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Errors are handled as follows : +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but er +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Inte +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Received character is then retrieved and stored in Rx buffer, Error code is set to allow +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** If user wants to abort it, Abort services should be called by user. +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) Error is considered as Blocking : Transfer could not be completed properly and is aborte +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() use +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** -@- In the Half duplex communication, it is forbidden to run the transmit +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @endverbatim +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Send an amount of data in blocking mode. +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the sent data is handled as a set of u16. In this case, Size must indicate the number +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * of u16 provided through pData. +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When FIFO mode is enabled, writing a data in the TDR register adds one +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * data to the TXFIFO. Write operations to the TDR register are performed +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * when TXFNF flag is set. From hardware perspective, TXFNF flag and +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * TXE are mapped on the same bit-field. +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be sent. +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Timeout Timeout duration. +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint3 +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint8_t *pdata8bits; +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *pdata16bits; +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init tickstart for timeout managment*/ +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tickstart = HAL_GetTick(); +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits = NULL; +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits = pData; +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = NULL; +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** while (huart->TxXferCount > 0U) +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (pdata8bits == NULL) +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* At end of Tx process, restore huart->gState to Ready */ +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Receive an amount of data in blocking mode. +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the received data is handled as a set of u16. In this case, Size must indicate the numb +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * of u16 available through pData. +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * is not empty. Read operations from the RDR register are performed when +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * RXFNE flag is set. From hardware perspective, RXFNE flag and + ARM GAS /tmp/ccizsdzp.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * RXNE are mapped on the same bit-field. +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Timeout Timeout duration. +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32 +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint8_t *pdata8bits; +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *pdata16bits; +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhMask; +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init tickstart for timeout managment*/ +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tickstart = HAL_GetTick(); +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = Size; +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Computation of UART mask to apply to RDR register */ +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_MASK_COMPUTATION(huart); +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits = NULL; +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits = pData; +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = NULL; +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* as long as data have to be received */ +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** while (huart->RxXferCount > 0U) +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; + ARM GAS /tmp/ccizsdzp.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (pdata8bits == NULL) +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Send an amount of data in interrupt mode. +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the sent data is handled as a set of u16. In this case, Size must indicate the number +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * of u16 provided through pData. +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be sent. +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr = pData; +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Configure Tx interrupt processing */ +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) + ARM GAS /tmp/ccizsdzp.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the Tx ISR function pointer according to the data word length */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = UART_TxISR_16BIT_FIFOEN; +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = UART_TxISR_8BIT_FIFOEN; +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the TX FIFO threshold interrupt */ +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the Tx ISR function pointer according to the data word length */ +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = UART_TxISR_16BIT; +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = UART_TxISR_8BIT; +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the Transmit Data Register Empty interrupt */ +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Receive an amount of data in interrupt mode. +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the received data is handled as a set of u16. In this case, Size must indicate the numb +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * of u16 available through pData. +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr = pData; +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = Size; +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Computation of UART mask to apply to RDR register */ +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_MASK_COMPUTATION(huart); +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Configure Rx interrupt processing*/ +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the Rx ISR function pointer according to the data word length */ +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = UART_RxISR_16BIT_FIFOEN; +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = UART_RxISR_8BIT_FIFOEN; +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the Rx ISR function pointer according to the data word length */ +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = UART_RxISR_16BIT; +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = UART_RxISR_8BIT; +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 25 + + +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Send an amount of data in DMA mode. +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the sent data is handled as a set of u16. In this case, Size must indicate the number +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * of u16 provided through pData. +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be sent. +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr = pData; +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA transfer complete callback */ +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Half transfer complete callback */ +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the DMA error callback */ +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferErrorCallback = UART_DMAError; +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the DMA abort callback */ +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART transmit DMA channel */ +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance-> +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; + ARM GAS /tmp/ccizsdzp.s page 26 + + +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState to ready */ +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the TC flag in the ICR register */ +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the DMA transfer for transmit request by setting the DMAT bit +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in the UART CR3 register */ +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Receive an amount of data in DMA mode. +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When the UART parity is enabled (PCE = 1), the received data contain +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the parity bit (MSB position). +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the received data is handled as a set of u16. In this case, Size must indicate the numb +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * of u16 available through pData. +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr = pData; +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) + ARM GAS /tmp/ccizsdzp.s page 27 + + +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA transfer complete callback */ +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Half transfer complete callback */ +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the DMA error callback */ +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferErrorCallback = UART_DMAError; +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the DMA abort callback */ +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the DMA channel */ +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuff +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState to ready */ +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Parity Error Interrupt */ +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the DMA transfer for the receiver request by setting the DMAR bit +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in the UART CR3 register */ +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Pause the DMA Transfer. +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 28 + + +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Tx request */ +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Rx request */ +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Resume the DMA Transfer. +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART DMA Tx request */ +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Overrun flag before resuming the Rx transfer */ +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART DMA Rx request */ +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + ARM GAS /tmp/ccizsdzp.s page 29 + + +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Stop the DMA Transfer. +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the stream and the corresponding call back is executed. */ +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Stop UART DMA Tx request if ongoing */ +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Tx channel */ +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndTxTransfer(huart); +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Stop UART DMA Rx request if ongoing */ +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Rx channel */ +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; + ARM GAS /tmp/ccizsdzp.s page 30 + + +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndRxTransfer(huart); +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Abort ongoing transfers (blocking mode). +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This procedure performs following operations : +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable UART Interrupts (Tx and Rx) +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Set handle State to READY +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interr +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFN +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ARM GAS /tmp/ccizsdzp.s page 31 + + +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Tx and Rx transfer counters */ +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Flush the whole TX FIFO (if needed) */ +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Discard the received data */ +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Abort ongoing Transmit transfer (blocking mode). +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This procedure performs following operations : +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable UART Interrupts (Tx) +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Set handle State to READY +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status + ARM GAS /tmp/ccizsdzp.s page 32 + + +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TCIE, TXEIE and TXFTIE interrupts */ +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Tx transfer counter */ +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Flush the whole TX FIFO (if needed) */ +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Abort ongoing Receive transfer (blocking mode). +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This procedure performs following operations : +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable UART Interrupts (Rx) +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Set handle State to READY +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere + ARM GAS /tmp/ccizsdzp.s page 33 + + +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set error code to DMA */ +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Rx transfer counter */ +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Discard the received data */ +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Abort ongoing transfers (Interrupt mode). +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This procedure performs following operations : +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable UART Interrupts (Tx and Rx) +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Set handle State to READY + ARM GAS /tmp/ccizsdzp.s page 34 + + +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - At abort completion, call user abort complete callback +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t abortcplt = 1U; +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable interrupts */ +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USA +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks sh +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** before any call to DMA Abort functions */ +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DMA Tx Handle is valid */ +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Otherwise, set it to NULL */ +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DMA Rx Handle is valid */ +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Otherwise, set it to NULL */ +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable DMA Tx at UART level */ +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART Tx DMA Abort callback has already been initialised : +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort DMA TX */ + ARM GAS /tmp/ccizsdzp.s page 35 + + +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** abortcplt = 0U; +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART Rx DMA Abort callback has already been initialised : +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort DMA RX */ +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** abortcplt = 1U; +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** abortcplt = 0U; +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if no DMA abort complete callback execution is required => call user Abort Complete callback * +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (abortcplt == 1U) +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Tx and Rx transfer counters */ +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear ISR function pointers */ +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset errorCode */ +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Flush the whole TX FIFO (if needed) */ +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 36 + + +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Discard the received data */ +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort complete callback */ +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortCpltCallback(huart); +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort complete callback */ +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Abort ongoing Transmit transfer (Interrupt mode). +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This procedure performs following operations : +1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable UART Interrupts (Tx) +1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Set handle State to READY +2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - At abort completion, call user abort complete callback +2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable interrupts */ +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); +2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback : +2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; +2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort DMA TX */ +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) +2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + ARM GAS /tmp/ccizsdzp.s page 37 + + +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback(huart->hdmatx); +2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Tx transfer counter */ +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear TxISR function pointers */ +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; +2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort Transmit Complete Callback */ +2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortTransmitCpltCallback(huart); +2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort Transmit Complete Callback */ +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Tx transfer counter */ +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear TxISR function pointers */ +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; +2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Flush the whole TX FIFO (if needed) */ +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) +2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); +2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort Transmit Complete Callback */ +2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortTransmitCpltCallback(huart); +2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort Transmit Complete Callback */ +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Abort ongoing Receive transfer (Interrupt mode). +2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. + ARM GAS /tmp/ccizsdzp.s page 38 + + +2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt +2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * This procedure performs following operations : +2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable UART Interrupts (Rx) +2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - Set handle State to READY +2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - At abort completion, call user abort complete callback +2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback : +2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; +2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort DMA RX */ +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback(huart->hdmarx); +2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Rx transfer counter */ +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RxISR function pointer */ +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr = NULL; +2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_F +2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Discard the received data */ +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort Receive Complete Callback */ +2140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortReceiveCpltCallback(huart); + ARM GAS /tmp/ccizsdzp.s page 39 + + +2141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort Receive Complete Callback */ +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +2144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset Rx transfer counter */ +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +2151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RxISR function pointer */ +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr = NULL; +2154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF +2157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort Receive Complete Callback */ +2164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortReceiveCpltCallback(huart); +2165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort Receive Complete Callback */ +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +2168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Handle UART interrupt request. +2176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr3its = READ_REG(huart->Instance->CR3); +2184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t errorflags; +2186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t errorcode; +2187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* If no error occurs */ +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (errorflags == 0U) +2191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART in mode Receiver ---------------------------------------------------*/ +2193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr3its & USART_CR3_RXFTIE) != 0U))) +2196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxISR != NULL) + ARM GAS /tmp/ccizsdzp.s page 40 + + +2198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR(huart); +2200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* If some errors occur */ +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((errorflags != 0U) +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) +2208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) +2209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART parity error interrupt occurred -------------------------------------*/ +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) +2212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); +2214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_PE; +2216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART frame error interrupt occurred --------------------------------------*/ +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) +2220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); +2222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_FE; +2224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART noise error interrupt occurred --------------------------------------*/ +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) +2228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); +2230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_NE; +2232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART Over-Run interrupt occurred -----------------------------------------*/ +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_ORE) != 0U) +2236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || +2237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) +2238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); +2240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_ORE; +2242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART Receiver Timeout interrupt occurred ---------------------------------*/ +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) +2246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); +2248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_RTO; +2250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call UART Error Call back function if need be ----------------------------*/ +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->ErrorCode != HAL_UART_ERROR_NONE) +2254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 41 + + +2255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART in mode Receiver --------------------------------------------------*/ +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) +2257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr3its & USART_CR3_RXFTIE) != 0U))) +2259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxISR != NULL) +2261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR(huart); +2263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* If Error is to be considered as blocking : +2267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - Receiver Timeout error in Reception +2268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - Overrun error in Reception +2269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** - any error occurs in DMA mode reception +2270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** errorcode = huart->ErrorCode; +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || +2273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) +2274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Blocking error : transfer is aborted +2276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Set the UART state ready to be able to start again the process, +2277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ +2278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndRxTransfer(huart); +2279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +2282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +2284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort the UART DMA Rx channel */ +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +2287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the UART DMA Abort callback : +2289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; +2291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Abort DMA RX */ +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +2294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback(huart->hdmarx); +2297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call user error callback */ +2302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered error callback*/ +2304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback(huart); +2305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak error callback*/ +2307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 42 + + +2312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call user error callback */ +2315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered error callback*/ +2317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback(huart); +2318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak error callback*/ +2320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Non Blocking error : transfer could go on. +2327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** Error is notified to user through user error callback */ +2328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered error callback*/ +2330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback(huart); +2331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak error callback*/ +2333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +2336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } /* End if some error occurs */ +2341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) +2344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); +2346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART Rx state is not reset as a reception process might be ongoing. +2348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** If UART handle state fields need to be reset to READY, this could be done in Wakeup callback +2349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Wakeup Callback */ +2352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->WakeupCallback(huart); +2353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Wakeup Callback */ +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UARTEx_WakeupCallback(huart); +2356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART in mode Transmitter ------------------------------------------------*/ +2361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr3its & USART_CR3_TXFTIE) != 0U))) +2364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->TxISR != NULL) +2366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR(huart); +2368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 43 + + +2369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART in mode Transmitter (transmission end) -----------------------------*/ +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) +2374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndTransmit_IT(huart); +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART TX Fifo Empty occurred ----------------------------------------------*/ +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) +2381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Tx Fifo Empty Callback */ +2384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxFifoEmptyCallback(huart); +2385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Tx Fifo Empty Callback */ +2387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UARTEx_TxFifoEmptyCallback(huart); +2388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* UART RX Fifo Full occurred ----------------------------------------------*/ +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) +2394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Rx Fifo Full Callback */ +2397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxFifoFullCallback(huart); +2398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +2399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Rx Fifo Full Callback */ +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UARTEx_RxFifoFullCallback(huart); +2401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +2403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Tx Transfer completed callback. +2408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +2412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_TxCpltCallback can be implemented in the user file. +2418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Tx Half Transfer completed callback. +2423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + ARM GAS /tmp/ccizsdzp.s page 44 + + +2426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE: This function should not be modified, when the callback is needed, +2432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_TxHalfCpltCallback can be implemented in the user file. +2433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Rx Transfer completed callback. +2438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +2442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_RxCpltCallback can be implemented in the user file. +2448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Rx Half Transfer completed callback. +2453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE: This function should not be modified, when the callback is needed, +2462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_RxHalfCpltCallback can be implemented in the user file. +2463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART error callback. +2468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +2472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_ErrorCallback can be implemented in the user file. +2478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART Abort Complete callback. + ARM GAS /tmp/ccizsdzp.s page 45 + + +2483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +2487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_AbortCpltCallback can be implemented in the user file. +2493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART Abort Complete callback. +2498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +2502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. +2508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART Abort Receive Complete callback. +2513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +2517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UNUSED(huart); +2520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. +2523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} +2528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions +2531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART control functions +2532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * +2533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @verbatim +2534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== +2535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ##### Peripheral Control functions ##### +2536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** =============================================================================== +2537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] +2538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This subsection provides a set of functions allowing to control the UART. +2539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on th + ARM GAS /tmp/ccizsdzp.s page 46 + + +2540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature +2541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature +2542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode +2543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode +2544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode +2545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) UART_SetConfig() API configures the UART peripheral +2546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features +2547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization +2548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter +2549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver +2550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) HAL_LIN_SendBreak() API transmits the break characters +2551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @endverbatim +2552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ +2553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Update on the fly the receiver timeout value in RTOR register. +2557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the configuration information for the specified UART module. +2559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout +2560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * value must be less or equal to 0x0FFFFFFFF. +2561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(IS_LPUART_INSTANCE(huart->Instance))) +2566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +2569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Enable the UART receiver timeout feature. +2574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the configuration information for the specified UART module. +2576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(IS_LPUART_INSTANCE(huart->Instance))) +2581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +2583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Process Locked */ +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Set the USART RTOEN bit */ +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); +2591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Process Unlocked */ +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 47 + + +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +2598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +2602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +2607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Disable the UART receiver timeout feature. +2612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the configuration information for the specified UART module. +2614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +2617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(IS_LPUART_INSTANCE(huart->Instance))) +2619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +2621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Process Locked */ +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the USART RTOEN bit */ +2628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); +2629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Process Unlocked */ +2633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +2636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_BUSY; +2640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_ERROR; +2645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Enable UART in mute mode (does not mean UART enters mute mode; +2650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). +2651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ + ARM GAS /tmp/ccizsdzp.s page 48 + + +2654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable USART mute mode by setting the MME bit in the CR1 register */ +2661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_MME); +2662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); +2666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Disable UART mute mode (does not mean the UART actually exits mute mode +2670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * as it may not have been in mute mode at this very moment). +2671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable USART mute mode by clearing the MME bit in the CR1 register */ +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); +2682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Enter UART mute mode (means UART actually enters mute mode). +2690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. +2691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +2693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +2695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +2697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Enable the UART transmitter and disable the UART receiver. +2701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +2705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear TE and RE bits */ +2710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ARM GAS /tmp/ccizsdzp.s page 49 + + +2711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ +2713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TE); +2714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +2720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Enable the UART receiver and disable the UART transmitter. +2724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status. +2726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +2728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear TE and RE bits */ +2733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); +2734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ +2736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_RE); +2737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +2743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Transmit break characters. +2748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +2752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the parameters */ +2754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); +2755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); +2757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Send break characters */ +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); +2762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; + ARM GAS /tmp/ccizsdzp.s page 50 + + +2768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} +2772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions +2775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief UART Peripheral State functions +2776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * +2777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @verbatim +2778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ============================================================================== +2779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ##### Peripheral State and Error functions ##### +2780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ============================================================================== +2781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** [..] +2782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** This subsection provides functions allowing to : +2783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) Return the UART handle state. +2784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (+) Return the UART handle error code +2785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** @endverbatim +2787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ +2788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Return the UART handle state. +2792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the configuration information for the specified UART. +2794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL state +2795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +2797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t temp1; +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t temp2; +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** temp1 = huart->gState; +2801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** temp2 = huart->RxState; +2802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return (HAL_UART_StateTypeDef)(temp1 | temp2); +2804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Return the UART handle error code. +2808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the configuration information for the specified UART. +2810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval UART Error Code +2811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +2813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return huart->ErrorCode; +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} +2818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @} +2822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** @defgroup UART_Private_Functions UART Private Functions + ARM GAS /tmp/ccizsdzp.s page 51 + + +2825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @{ +2826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Initialize the callbacks to their default values. +2830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval none +2832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +2835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init the UART Callback settings */ +2837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltC +2838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallb +2839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltC +2840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallb +2841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallba +2842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCa +2843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransm +2844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiv +2845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallb +2846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullC +2847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmpty +2848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +2853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Configure the UART peripheral. +2854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +2855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +2856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +2857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +2858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tmpreg; +2860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t brrtemp; +2861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_ClockSourceTypeDef clocksource; +2862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t usartdiv; +2863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef ret = HAL_OK; +2864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t lpuart_ker_ck_pres; +2865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** PLL2_ClocksTypeDef pll2_clocks; +2866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** PLL3_ClocksTypeDef pll3_clocks; +2867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t pclk; +2868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the parameters */ +2870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); +2871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +2872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_INSTANCE_LOWPOWER(huart)) +2873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); +2875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); +2879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); +2880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 52 + + +2882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_PARITY(huart->Init.Parity)); +2883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_MODE(huart->Init.Mode)); +2884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +2886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); +2887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*-------------------------- USART CR1 Configuration -----------------------*/ +2889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure +2890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the UART Word Length, Parity, Mode and oversampling: +2891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * set the M bits according to huart->Init.WordLength value +2892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * set PCE and PS bits according to huart->Init.Parity value +2893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * set TE and RE bits according to huart->Init.Mode value +2894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * set OVER8 bit according to huart->Init.OverSampling value */ +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O +2896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; +2897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); +2898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*-------------------------- USART CR2 Configuration -----------------------*/ +2900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Configure the UART Stop Bits: Set STOP[13:12] bits according +2901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * to huart->Init.StopBits value */ +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); +2903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*-------------------------- USART CR3 Configuration -----------------------*/ +2905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Configure +2906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - UART HardWare Flow Control: set CTSE and RTSE bits according +2907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * to huart->Init.HwFlowCtl value +2908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - one-bit sampling method versus three samples' majority rule according +2909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * to huart->Init.OneBitSampling (not applicable to LPUART) */ +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg = (uint32_t)huart->Init.HwFlowCtl; +2911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(UART_INSTANCE_LOWPOWER(huart))) +2913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= huart->Init.OneBitSampling; +2915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); +2917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*-------------------------- USART PRESC Configuration -----------------------*/ +2919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Configure +2920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); +2922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*-------------------------- USART BRR Configuration -----------------------*/ +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_GETCLOCKSOURCE(huart, clocksource); +2925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check LPUART instance */ +2927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_INSTANCE_LOWPOWER(huart)) +2928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Retrieve frequency clock */ +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (clocksource) +2931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D3PCLK1: +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = HAL_RCCEx_GetD3PCLK1Freq(); +2934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +2935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL2: +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +2937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll2_clocks.PLL2_Q_Frequency; +2938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + ARM GAS /tmp/ccizsdzp.s page 53 + + +2939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL3: +2940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +2941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll3_clocks.PLL3_Q_Frequency; +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +2943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +2945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); +2947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) HSI_VALUE; +2951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +2953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_CSI: +2954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) CSI_VALUE; +2955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +2956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +2957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) LSE_VALUE; +2958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +2959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default: +2960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = 0U; +2961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +2962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +2963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* If proper clock source reported */ +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (pclk != 0U) +2967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Compute clock after Prescaler */ +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); +2970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +2971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || +2973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) +2974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +2976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check computed UsartDiv value is in allocated range +2980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.Clo +2982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) +2983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->BRR = usartdiv; +2985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +2987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +2989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * +2991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } /* if (pclk != 0) */ +2992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +2993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check UART Over Sampling to set Baud Rate Register */ +2994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) +2995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 54 + + +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (clocksource) +2997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +2998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D2PCLK1: +2999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK1Freq(); +3000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D2PCLK2: +3002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK2Freq(); +3003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL2: +3005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +3006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll2_clocks.PLL2_Q_Frequency; +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL3: +3009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll3_clocks.PLL3_Q_Frequency; +3011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +3014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); +3016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) HSI_VALUE; +3020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_CSI: +3023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) CSI_VALUE; +3024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +3026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) LSE_VALUE; +3027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default: +3029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = 0U; +3030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +3031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* USARTDIV must be greater than or equal to 0d16 */ +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (pclk != 0U) +3036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescal +3038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) +3039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** brrtemp = (uint16_t)(usartdiv & 0xFFF0U); +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; +3043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +3047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** switch (clocksource) + ARM GAS /tmp/ccizsdzp.s page 55 + + +3053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D2PCLK1: +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK1Freq(); +3056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D2PCLK2: +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK2Freq(); +3059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL2: +3061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); +3062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll2_clocks.PLL2_Q_Frequency; +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL3: +3065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll3_clocks.PLL3_Q_Frequency; +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) +3070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); +3072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) HSI_VALUE; +3076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_CSI: +3079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) CSI_VALUE; +3080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +3082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = (uint32_t) LSE_VALUE; +3083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** default: +3085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = 0U; +3086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +3087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; +3088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (pclk != 0U) +3091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* USARTDIV must be greater than or equal to 0d16 */ +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPresca +3094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) +3095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->BRR = usartdiv; +3097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ret = HAL_ERROR; +3101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Initialize the number of data to process during RX/TX ISR execution */ +3106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->NbTxDataToProcess = 1; +3107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->NbRxDataToProcess = 1; +3108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear ISR function pointers */ + ARM GAS /tmp/ccizsdzp.s page 56 + + +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +3111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; +3112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return ret; +3114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Configure the UART peripheral advanced features. +3118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check whether the set of advanced features to configure is properly set */ +3124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); +3125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure TX pin active level inversion */ +3127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) +3128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); +3130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); +3131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure RX pin active level inversion */ +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) +3135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); +3138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure data inversion */ +3141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) +3142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); +3144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); +3145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure RX/TX pins swap */ +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) +3149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); +3151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); +3152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure RX overrun detection disabling */ +3155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) +3156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); +3158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); +3159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure DMA disabling on reception error */ +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) +3163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); +3165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); +3166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 57 + + +3167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure auto Baud rate detection scheme */ +3169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) +3170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); +3172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); +3173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); +3174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* set auto Baudrate detection parameters if detection is enabled */ +3175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) +3176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); +3178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); +3179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* if required, configure MSB first on communication line */ +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) +3184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); +3186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); +3187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Check the UART Idle State. +3192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +3194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; +3198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Initialize the UART ErrorCode */ +3200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Init tickstart for timeout managment*/ +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tickstart = HAL_GetTick(); +3204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check if the Transmitter is enabled */ +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) +3207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Wait until TEACK flag is set */ +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALU +3210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Timeout occurred */ +3212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +3213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check if the Receiver is enabled */ +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) +3218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Wait until REACK flag is set */ +3220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALU +3221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Timeout occurred */ +3223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; + ARM GAS /tmp/ccizsdzp.s page 58 + + +3224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Initialize the UART State */ +3228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +3234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Handle UART Communication Timeout. +3238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Flag Specifies the UART flag to check +3240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Status Flag status (SET or RESET) +3241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Tickstart Tick start value +3242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param Timeout Timeout duration +3243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval HAL status +3244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus +3246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t Tickstart, uint32_t Timeout) +3247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Wait until flag is set */ +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) +3250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check for the Timeout */ +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (Timeout != HAL_MAX_DELAY) +3253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +3255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for t +3257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEI +3258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +3266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) +3269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) +3271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear Receiver Timeout flag*/ +3273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); +3274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TX +3277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + ARM GAS /tmp/ccizsdzp.s page 59 + + +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_RTO; +3282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Process Unlocked */ +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_TIMEOUT; +3287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return HAL_OK; +3292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit compl +3297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +3301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 28 .loc 1 3301 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +3302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TXEIE, TCIE, TXFT interrupts */ +3303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + 33 .loc 1 3303 3 view .LVU1 + 34 0000 0268 ldr r2, [r0] + 35 0002 1368 ldr r3, [r2] + 36 0004 23F0C003 bic r3, r3, #192 + 37 0008 1360 str r3, [r2] +3304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + 38 .loc 1 3304 3 view .LVU2 + 39 000a 0268 ldr r2, [r0] + 40 000c 9368 ldr r3, [r2, #8] + 41 000e 23F40003 bic r3, r3, #8388608 + 42 0012 9360 str r3, [r2, #8] +3305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* At end of Tx process, restore huart->gState to Ready */ +3307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; + 43 .loc 1 3307 3 view .LVU3 + 44 .loc 1 3307 17 is_stmt 0 view .LVU4 + 45 0014 2023 movs r3, #32 + 46 0016 C0F88030 str r3, [r0, #128] +3308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 47 .loc 1 3308 1 view .LVU5 + 48 001a 7047 bx lr + 49 .cfi_endproc + 50 .LFE187: + 52 .section .text.UART_EndRxTransfer,"ax",%progbits + 53 .align 1 + 54 .syntax unified + 55 .thumb + 56 .thumb_func + 57 .fpu fpv5-d16 + ARM GAS /tmp/ccizsdzp.s page 60 + + + 59 UART_EndRxTransfer: + 60 .LVL1: + 61 .LFB188: +3309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception comp +3313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +3317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 62 .loc 1 3317 1 is_stmt 1 view -0 + 63 .cfi_startproc + 64 @ args = 0, pretend = 0, frame = 0 + 65 @ frame_needed = 0, uses_anonymous_args = 0 + 66 @ link register save eliminated. +3318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +3319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 67 .loc 1 3319 3 view .LVU7 + 68 0000 0268 ldr r2, [r0] + 69 0002 1368 ldr r3, [r2] + 70 0004 23F49073 bic r3, r3, #288 + 71 0008 1360 str r3, [r2] +3320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 72 .loc 1 3320 3 view .LVU8 + 73 000a 0268 ldr r2, [r0] + 74 000c 9168 ldr r1, [r2, #8] + 75 000e 044B ldr r3, .L3 + 76 0010 0B40 ands r3, r3, r1 + 77 0012 9360 str r3, [r2, #8] +3321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +3323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 78 .loc 1 3323 3 view .LVU9 + 79 .loc 1 3323 18 is_stmt 0 view .LVU10 + 80 0014 2023 movs r3, #32 + 81 0016 C0F88430 str r3, [r0, #132] +3324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset RxIsr function pointer */ +3326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; + 82 .loc 1 3326 3 is_stmt 1 view .LVU11 + 83 .loc 1 3326 16 is_stmt 0 view .LVU12 + 84 001a 0023 movs r3, #0 + 85 001c C366 str r3, [r0, #108] +3327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 86 .loc 1 3327 1 view .LVU13 + 87 001e 7047 bx lr + 88 .L4: + 89 .align 2 + 90 .L3: + 91 0020 FEFFFFEF .word -268435458 + 92 .cfi_endproc + 93 .LFE188: + 95 .section .text.UART_TxISR_8BIT,"ax",%progbits + 96 .align 1 + 97 .syntax unified + ARM GAS /tmp/ccizsdzp.s page 61 + + + 98 .thumb + 99 .thumb_func + 100 .fpu fpv5-d16 + 102 UART_TxISR_8BIT: + 103 .LVL2: + 104 .LFB199: +3328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART transmit process complete callback. +3332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +3336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DMA Normal mode */ +3340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (hdma->Init.Mode != DMA_CIRCULAR) +3341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +3343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the DMA transfer for transmit request by resetting the DMAT bit +3345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in the UART CR3 register */ +3346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +3347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DMA Circular mode */ +3352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Tx complete callback*/ +3356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxCpltCallback(huart); +3357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Tx complete callback*/ +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_TxCpltCallback(huart); +3360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART transmit process half complete callback. +3366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +3370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Tx Half complete callback*/ +3375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxHalfCpltCallback(huart); +3376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Tx Half complete callback*/ +3378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_TxHalfCpltCallback(huart); + ARM GAS /tmp/ccizsdzp.s page 62 + + +3379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART receive process complete callback. +3384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +3388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* DMA Normal mode */ +3392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (hdma->Init.Mode != DMA_CIRCULAR) +3393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +3395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +3397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +3398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the DMA transfer for the receiver request by resetting the DMAR bit +3401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** in the UART CR3 register */ +3402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +3403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +3405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +3410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback(huart); +3411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +3414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART receive process half complete callback. +3419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Rx Half complete callback*/ +3428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxHalfCpltCallback(huart); +3429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Rx Half complete callback*/ +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_RxHalfCpltCallback(huart); +3432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + ARM GAS /tmp/ccizsdzp.s page 63 + + +3436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART communication error callback. +3437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma) +3441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; +3445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; +3446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Stop UART DMA Tx request if ongoing */ +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && +3449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) +3450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndTxTransfer(huart); +3453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Stop UART DMA Rx request if ongoing */ +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && +3457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) +3458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +3460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndRxTransfer(huart); +3461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_DMA; +3464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered error callback*/ +3467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback(huart); +3468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak error callback*/ +3470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +3471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART communication abort callback, when initiated by HAL services on Error +3476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * (To be called at end of DMA Abort procedure following error occurrence). +3477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +3481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +3484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +3485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered error callback*/ +3488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCallback(huart); +3489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak error callback*/ +3491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +3492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccizsdzp.s page 64 + + +3493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART Tx communication abort callback, when initiated by user +3497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * (To be called at end of DMA Tx Abort procedure following user abort request). +3498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * Abort still ongoing for Rx DMA Handle. +3500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +3504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +3508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check if an Abort process is still ongoing */ +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx != NULL) +3511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmarx->XferAbortCallback != NULL) +3513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +3515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba +3519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +3520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +3521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset errorCode */ +3523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +3526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +3527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Flush the whole TX FIFO (if needed) */ +3529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) +3530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); +3532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +3535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call user Abort complete callback */ +3539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort complete callback */ +3541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortCpltCallback(huart); +3542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort complete callback */ +3544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +3545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + ARM GAS /tmp/ccizsdzp.s page 65 + + +3550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART Rx communication abort callback, when initiated by user +3551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * (To be called at end of DMA Rx Abort procedure following user abort request). +3552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * Abort still ongoing for Tx DMA Handle. +3554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +3562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check if an Abort process is still ongoing */ +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx != NULL) +3565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->hdmatx->XferAbortCallback != NULL) +3567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; +3569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba +3573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +3574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +3575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Reset errorCode */ +3577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +3580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +3581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Discard the received data */ +3583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +3584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +3586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call user Abort complete callback */ +3590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort complete callback */ +3592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortCpltCallback(huart); +3593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort complete callback */ +3595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +3596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART Tx communication abort callback, when initiated by user by a call to +3602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) +3603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * (This callback is executed at end of DMA Tx Abort procedure following user abort reques +3604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * and leads to user Tx Abort Complete callback execution). +3605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None + ARM GAS /tmp/ccizsdzp.s page 66 + + +3607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +3609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; +3613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Flush the whole TX FIFO (if needed) */ +3615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->FifoMode == UART_FIFOMODE_ENABLE) +3616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); +3618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +3621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call user Abort complete callback */ +3624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort Transmit Complete Callback */ +3626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortTransmitCpltCallback(huart); +3627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort Transmit Complete Callback */ +3629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +3630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief DMA UART Rx communication abort callback, when initiated by user by a call to +3635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) +3636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * (This callback is executed at end of DMA Rx Abort procedure following user abort reques +3637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * and leads to user Rx Abort Complete callback execution). +3638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param hdma DMA handle. +3639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +3642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +3644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; +3646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +3648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +3649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Discard the received data */ +3651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +3652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call user Abort complete callback */ +3657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call registered Abort Receive Complete Callback */ +3659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->AbortReceiveCpltCallback(huart); +3660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Call legacy weak Abort Receive Complete Callback */ +3662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +3663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccizsdzp.s page 67 + + +3664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief TX interrrupt handler for 7 or 8 bits data word length . +3668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +3669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +3670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +3674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 105 .loc 1 3674 1 is_stmt 1 view -0 + 106 .cfi_startproc + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 @ link register save eliminated. +3675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +3676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 110 .loc 1 3676 3 view .LVU15 + 111 .loc 1 3676 12 is_stmt 0 view .LVU16 + 112 0000 D0F88030 ldr r3, [r0, #128] + 113 .loc 1 3676 6 view .LVU17 + 114 0004 212B cmp r3, #33 + 115 0006 00D0 beq .L8 + 116 .L5: +3677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->TxXferCount == 0U) +3679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Transmit Data Register Empty Interrupt */ +3681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +3682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); +3689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; +3691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 117 .loc 1 3693 1 view .LVU18 + 118 0008 7047 bx lr + 119 .L8: +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 120 .loc 1 3678 5 is_stmt 1 view .LVU19 +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 121 .loc 1 3678 14 is_stmt 0 view .LVU20 + 122 000a B0F85630 ldrh r3, [r0, #86] + 123 000e 9BB2 uxth r3, r3 +3678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 124 .loc 1 3678 8 view .LVU21 + 125 0010 53B9 cbnz r3, .L7 +3681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 126 .loc 1 3681 7 is_stmt 1 view .LVU22 + 127 0012 0268 ldr r2, [r0] + ARM GAS /tmp/ccizsdzp.s page 68 + + + 128 0014 1368 ldr r3, [r2] + 129 0016 23F08003 bic r3, r3, #128 + 130 001a 1360 str r3, [r2] +3684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 131 .loc 1 3684 7 view .LVU23 + 132 001c 0268 ldr r2, [r0] + 133 001e 1368 ldr r3, [r2] + 134 0020 43F04003 orr r3, r3, #64 + 135 0024 1360 str r3, [r2] + 136 0026 7047 bx lr + 137 .L7: +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 138 .loc 1 3688 7 view .LVU24 +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 139 .loc 1 3688 46 is_stmt 0 view .LVU25 + 140 0028 036D ldr r3, [r0, #80] +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 141 .loc 1 3688 40 view .LVU26 + 142 002a 1A78 ldrb r2, [r3] @ zero_extendqisi2 +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 143 .loc 1 3688 12 view .LVU27 + 144 002c 0368 ldr r3, [r0] +3688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 145 .loc 1 3688 28 view .LVU28 + 146 002e 9A62 str r2, [r3, #40] +3689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 147 .loc 1 3689 7 is_stmt 1 view .LVU29 +3689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 148 .loc 1 3689 12 is_stmt 0 view .LVU30 + 149 0030 036D ldr r3, [r0, #80] +3689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 150 .loc 1 3689 24 view .LVU31 + 151 0032 0133 adds r3, r3, #1 + 152 0034 0365 str r3, [r0, #80] +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 153 .loc 1 3690 7 is_stmt 1 view .LVU32 +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 154 .loc 1 3690 12 is_stmt 0 view .LVU33 + 155 0036 B0F85630 ldrh r3, [r0, #86] + 156 003a 9BB2 uxth r3, r3 +3690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 157 .loc 1 3690 25 view .LVU34 + 158 003c 013B subs r3, r3, #1 + 159 003e 9BB2 uxth r3, r3 + 160 0040 A0F85630 strh r3, [r0, #86] @ movhi + 161 .loc 1 3693 1 view .LVU35 + 162 0044 E0E7 b .L5 + 163 .cfi_endproc + 164 .LFE199: + 166 .section .text.UART_TxISR_16BIT,"ax",%progbits + 167 .align 1 + 168 .syntax unified + 169 .thumb + 170 .thumb_func + 171 .fpu fpv5-d16 + 173 UART_TxISR_16BIT: + 174 .LVL3: + ARM GAS /tmp/ccizsdzp.s page 69 + + + 175 .LFB200: +3694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief TX interrrupt handler for 9 bits data word length. +3697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +3698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +3699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +3703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 176 .loc 1 3703 1 is_stmt 1 view -0 + 177 .cfi_startproc + 178 @ args = 0, pretend = 0, frame = 0 + 179 @ frame_needed = 0, uses_anonymous_args = 0 + 180 @ link register save eliminated. +3704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *tmp; + 181 .loc 1 3704 3 view .LVU37 +3705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +3707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 182 .loc 1 3707 3 view .LVU38 + 183 .loc 1 3707 12 is_stmt 0 view .LVU39 + 184 0000 D0F88030 ldr r3, [r0, #128] + 185 .loc 1 3707 6 view .LVU40 + 186 0004 212B cmp r3, #33 + 187 0006 00D0 beq .L12 + 188 .L9: +3708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->TxXferCount == 0U) +3710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Transmit Data Register Empty Interrupt */ +3712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); +3713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pTxBuffPtr; +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); +3721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; +3722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; +3723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 189 .loc 1 3725 1 view .LVU41 + 190 0008 7047 bx lr + 191 .L12: +3709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 192 .loc 1 3709 5 is_stmt 1 view .LVU42 +3709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 193 .loc 1 3709 14 is_stmt 0 view .LVU43 + 194 000a B0F85630 ldrh r3, [r0, #86] + 195 000e 9BB2 uxth r3, r3 +3709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 196 .loc 1 3709 8 view .LVU44 + ARM GAS /tmp/ccizsdzp.s page 70 + + + 197 0010 53B9 cbnz r3, .L11 +3712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 198 .loc 1 3712 7 is_stmt 1 view .LVU45 + 199 0012 0268 ldr r2, [r0] + 200 0014 1368 ldr r3, [r2] + 201 0016 23F08003 bic r3, r3, #128 + 202 001a 1360 str r3, [r2] +3715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 203 .loc 1 3715 7 view .LVU46 + 204 001c 0268 ldr r2, [r0] + 205 001e 1368 ldr r3, [r2] + 206 0020 43F04003 orr r3, r3, #64 + 207 0024 1360 str r3, [r2] + 208 0026 7047 bx lr + 209 .L11: +3719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + 210 .loc 1 3719 7 view .LVU47 +3719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + 211 .loc 1 3719 11 is_stmt 0 view .LVU48 + 212 0028 036D ldr r3, [r0, #80] + 213 .LVL4: +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 214 .loc 1 3720 7 is_stmt 1 view .LVU49 +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 215 .loc 1 3720 43 is_stmt 0 view .LVU50 + 216 002a 1B88 ldrh r3, [r3] + 217 .LVL5: +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 218 .loc 1 3720 12 view .LVU51 + 219 002c 0268 ldr r2, [r0] +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 220 .loc 1 3720 50 view .LVU52 + 221 002e C3F30803 ubfx r3, r3, #0, #9 +3720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 222 .loc 1 3720 28 view .LVU53 + 223 0032 9362 str r3, [r2, #40] + 224 .LVL6: +3721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 225 .loc 1 3721 7 is_stmt 1 view .LVU54 +3721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 226 .loc 1 3721 25 is_stmt 0 view .LVU55 + 227 0034 036D ldr r3, [r0, #80] + 228 0036 0233 adds r3, r3, #2 + 229 0038 0365 str r3, [r0, #80] +3722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 230 .loc 1 3722 7 is_stmt 1 view .LVU56 +3722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 231 .loc 1 3722 12 is_stmt 0 view .LVU57 + 232 003a B0F85630 ldrh r3, [r0, #86] + 233 003e 9BB2 uxth r3, r3 +3722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 234 .loc 1 3722 25 view .LVU58 + 235 0040 013B subs r3, r3, #1 + 236 0042 9BB2 uxth r3, r3 + 237 0044 A0F85630 strh r3, [r0, #86] @ movhi + 238 .loc 1 3725 1 view .LVU59 + 239 0048 DEE7 b .L9 + ARM GAS /tmp/ccizsdzp.s page 71 + + + 240 .cfi_endproc + 241 .LFE200: + 243 .section .text.UART_TxISR_8BIT_FIFOEN,"ax",%progbits + 244 .align 1 + 245 .syntax unified + 246 .thumb + 247 .thumb_func + 248 .fpu fpv5-d16 + 250 UART_TxISR_8BIT_FIFOEN: + 251 .LVL7: + 252 .LFB201: +3726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. +3729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +3730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +3731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +3735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 253 .loc 1 3735 1 is_stmt 1 view -0 + 254 .cfi_startproc + 255 @ args = 0, pretend = 0, frame = 0 + 256 @ frame_needed = 0, uses_anonymous_args = 0 + 257 @ link register save eliminated. +3736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t nb_tx_data; + 258 .loc 1 3736 3 view .LVU61 +3737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +3739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 259 .loc 1 3739 3 view .LVU62 + 260 .loc 1 3739 12 is_stmt 0 view .LVU63 + 261 0000 D0F88030 ldr r3, [r0, #128] + 262 .loc 1 3739 6 view .LVU64 + 263 0004 212B cmp r3, #33 + 264 0006 00D0 beq .L19 + 265 .L13: +3740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) +3742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->TxXferCount == 0U) +3744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the TX FIFO threshold interrupt */ +3746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); +3747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; /* force exit loop */ +3752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) +3754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; +3757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; +3758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 72 + + +3759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Nothing to do */ +3762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 266 .loc 1 3765 1 view .LVU65 + 267 0008 7047 bx lr + 268 .L19: +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 269 .loc 1 3741 5 is_stmt 1 view .LVU66 +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 270 .loc 1 3741 21 is_stmt 0 view .LVU67 + 271 000a B0F86A30 ldrh r3, [r0, #106] + 272 .LVL8: +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 273 .loc 1 3741 5 view .LVU68 + 274 000e 0CE0 b .L15 + 275 .L20: +3746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 276 .loc 1 3746 9 is_stmt 1 view .LVU69 + 277 0010 0268 ldr r2, [r0] + 278 0012 9368 ldr r3, [r2, #8] + 279 .LVL9: +3746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 280 .loc 1 3746 9 is_stmt 0 view .LVU70 + 281 0014 23F40003 bic r3, r3, #8388608 + 282 0018 9360 str r3, [r2, #8] +3749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 283 .loc 1 3749 9 is_stmt 1 view .LVU71 + 284 001a 0268 ldr r2, [r0] + 285 001c 1368 ldr r3, [r2] + 286 001e 43F04003 orr r3, r3, #64 + 287 0022 1360 str r3, [r2] +3751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 288 .loc 1 3751 9 view .LVU72 + 289 0024 7047 bx lr + 290 .LVL10: + 291 .L17: +3762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 292 .loc 1 3762 7 discriminator 2 view .LVU73 +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 293 .loc 1 3741 68 discriminator 2 view .LVU74 +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 294 .loc 1 3741 78 is_stmt 0 discriminator 2 view .LVU75 + 295 0026 013B subs r3, r3, #1 + 296 .LVL11: +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 297 .loc 1 3741 78 discriminator 2 view .LVU76 + 298 0028 9BB2 uxth r3, r3 + 299 .LVL12: + 300 .L15: +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 301 .loc 1 3741 50 is_stmt 1 discriminator 1 view .LVU77 +3741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 302 .loc 1 3741 5 is_stmt 0 discriminator 1 view .LVU78 + ARM GAS /tmp/ccizsdzp.s page 73 + + + 303 002a 002B cmp r3, #0 + 304 002c ECD0 beq .L13 +3743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 305 .loc 1 3743 7 is_stmt 1 view .LVU79 +3743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 306 .loc 1 3743 16 is_stmt 0 view .LVU80 + 307 002e B0F85620 ldrh r2, [r0, #86] + 308 0032 92B2 uxth r2, r2 +3743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 309 .loc 1 3743 10 view .LVU81 + 310 0034 002A cmp r2, #0 + 311 0036 EBD0 beq .L20 +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 312 .loc 1 3753 12 is_stmt 1 view .LVU82 +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 313 .loc 1 3753 16 is_stmt 0 view .LVU83 + 314 0038 0268 ldr r2, [r0] + 315 003a D169 ldr r1, [r2, #28] +3753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 316 .loc 1 3753 15 view .LVU84 + 317 003c 11F0800F tst r1, #128 + 318 0040 F1D0 beq .L17 +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 319 .loc 1 3755 9 is_stmt 1 view .LVU85 +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 320 .loc 1 3755 48 is_stmt 0 view .LVU86 + 321 0042 016D ldr r1, [r0, #80] +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 322 .loc 1 3755 42 view .LVU87 + 323 0044 0978 ldrb r1, [r1] @ zero_extendqisi2 +3755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr++; + 324 .loc 1 3755 30 view .LVU88 + 325 0046 9162 str r1, [r2, #40] +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 326 .loc 1 3756 9 is_stmt 1 view .LVU89 +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 327 .loc 1 3756 14 is_stmt 0 view .LVU90 + 328 0048 026D ldr r2, [r0, #80] +3756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 329 .loc 1 3756 26 view .LVU91 + 330 004a 0132 adds r2, r2, #1 + 331 004c 0265 str r2, [r0, #80] +3757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 332 .loc 1 3757 9 is_stmt 1 view .LVU92 +3757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 333 .loc 1 3757 14 is_stmt 0 view .LVU93 + 334 004e B0F85620 ldrh r2, [r0, #86] + 335 0052 92B2 uxth r2, r2 +3757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 336 .loc 1 3757 27 view .LVU94 + 337 0054 013A subs r2, r2, #1 + 338 0056 92B2 uxth r2, r2 + 339 0058 A0F85620 strh r2, [r0, #86] @ movhi + 340 005c E3E7 b .L17 + 341 .cfi_endproc + 342 .LFE201: + 344 .section .text.UART_TxISR_16BIT_FIFOEN,"ax",%progbits + ARM GAS /tmp/ccizsdzp.s page 74 + + + 345 .align 1 + 346 .syntax unified + 347 .thumb + 348 .thumb_func + 349 .fpu fpv5-d16 + 351 UART_TxISR_16BIT_FIFOEN: + 352 .LVL13: + 353 .LFB202: +3766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. +3769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +3770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +3771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +3775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 354 .loc 1 3775 1 is_stmt 1 view -0 + 355 .cfi_startproc + 356 @ args = 0, pretend = 0, frame = 0 + 357 @ frame_needed = 0, uses_anonymous_args = 0 + 358 @ link register save eliminated. +3776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *tmp; + 359 .loc 1 3776 3 view .LVU96 +3777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t nb_tx_data; + 360 .loc 1 3777 3 view .LVU97 +3778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +3780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 361 .loc 1 3780 3 view .LVU98 + 362 .loc 1 3780 12 is_stmt 0 view .LVU99 + 363 0000 D0F88030 ldr r3, [r0, #128] + 364 .loc 1 3780 6 view .LVU100 + 365 0004 212B cmp r3, #33 + 366 0006 00D0 beq .L27 + 367 .L21: +3781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) +3783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->TxXferCount == 0U) +3785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the TX FIFO threshold interrupt */ +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); +3788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; /* force exit loop */ +3793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) +3795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pTxBuffPtr; +3797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); +3798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; +3800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 75 + + +3801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Nothing to do */ +3804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 368 .loc 1 3807 1 view .LVU101 + 369 0008 7047 bx lr + 370 .L27: +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 371 .loc 1 3782 5 is_stmt 1 view .LVU102 +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 372 .loc 1 3782 21 is_stmt 0 view .LVU103 + 373 000a B0F86A30 ldrh r3, [r0, #106] + 374 .LVL14: +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 375 .loc 1 3782 5 view .LVU104 + 376 000e 0CE0 b .L23 + 377 .L28: +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 378 .loc 1 3787 9 is_stmt 1 view .LVU105 + 379 0010 0268 ldr r2, [r0] + 380 0012 9368 ldr r3, [r2, #8] + 381 .LVL15: +3787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 382 .loc 1 3787 9 is_stmt 0 view .LVU106 + 383 0014 23F40003 bic r3, r3, #8388608 + 384 0018 9360 str r3, [r2, #8] +3790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 385 .loc 1 3790 9 is_stmt 1 view .LVU107 + 386 001a 0268 ldr r2, [r0] + 387 001c 1368 ldr r3, [r2] + 388 001e 43F04003 orr r3, r3, #64 + 389 0022 1360 str r3, [r2] +3792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 390 .loc 1 3792 9 view .LVU108 + 391 0024 7047 bx lr + 392 .LVL16: + 393 .L25: +3804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 394 .loc 1 3804 7 discriminator 2 view .LVU109 +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 395 .loc 1 3782 68 discriminator 2 view .LVU110 +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 396 .loc 1 3782 78 is_stmt 0 discriminator 2 view .LVU111 + 397 0026 013B subs r3, r3, #1 + 398 .LVL17: +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 399 .loc 1 3782 78 discriminator 2 view .LVU112 + 400 0028 9BB2 uxth r3, r3 + 401 .LVL18: + 402 .L23: +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 403 .loc 1 3782 50 is_stmt 1 discriminator 1 view .LVU113 +3782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 404 .loc 1 3782 5 is_stmt 0 discriminator 1 view .LVU114 + ARM GAS /tmp/ccizsdzp.s page 76 + + + 405 002a 002B cmp r3, #0 + 406 002c ECD0 beq .L21 +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 407 .loc 1 3784 7 is_stmt 1 view .LVU115 +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 408 .loc 1 3784 16 is_stmt 0 view .LVU116 + 409 002e B0F85620 ldrh r2, [r0, #86] + 410 0032 92B2 uxth r2, r2 +3784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 411 .loc 1 3784 10 view .LVU117 + 412 0034 002A cmp r2, #0 + 413 0036 EBD0 beq .L28 +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 414 .loc 1 3794 12 is_stmt 1 view .LVU118 +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 415 .loc 1 3794 16 is_stmt 0 view .LVU119 + 416 0038 0268 ldr r2, [r0] + 417 003a D169 ldr r1, [r2, #28] +3794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 418 .loc 1 3794 15 view .LVU120 + 419 003c 11F0800F tst r1, #128 + 420 0040 F1D0 beq .L25 +3796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + 421 .loc 1 3796 9 is_stmt 1 view .LVU121 +3796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + 422 .loc 1 3796 13 is_stmt 0 view .LVU122 + 423 0042 016D ldr r1, [r0, #80] + 424 .LVL19: +3797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 425 .loc 1 3797 9 is_stmt 1 view .LVU123 +3797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 426 .loc 1 3797 45 is_stmt 0 view .LVU124 + 427 0044 0988 ldrh r1, [r1] + 428 .LVL20: +3797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 429 .loc 1 3797 52 view .LVU125 + 430 0046 C1F30801 ubfx r1, r1, #0, #9 +3797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 431 .loc 1 3797 30 view .LVU126 + 432 004a 9162 str r1, [r2, #40] + 433 .LVL21: +3798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 434 .loc 1 3798 9 is_stmt 1 view .LVU127 +3798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount--; + 435 .loc 1 3798 27 is_stmt 0 view .LVU128 + 436 004c 026D ldr r2, [r0, #80] + 437 004e 0232 adds r2, r2, #2 + 438 0050 0265 str r2, [r0, #80] +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 439 .loc 1 3799 9 is_stmt 1 view .LVU129 +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 440 .loc 1 3799 14 is_stmt 0 view .LVU130 + 441 0052 B0F85620 ldrh r2, [r0, #86] + 442 0056 92B2 uxth r2, r2 +3799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 443 .loc 1 3799 27 view .LVU131 + 444 0058 013A subs r2, r2, #1 + ARM GAS /tmp/ccizsdzp.s page 77 + + + 445 005a 92B2 uxth r2, r2 + 446 005c A0F85620 strh r2, [r0, #86] @ movhi + 447 0060 E1E7 b .L25 + 448 .cfi_endproc + 449 .LFE202: + 451 .section .text.HAL_UART_MspInit,"ax",%progbits + 452 .align 1 + 453 .weak HAL_UART_MspInit + 454 .syntax unified + 455 .thumb + 456 .thumb_func + 457 .fpu fpv5-d16 + 459 HAL_UART_MspInit: + 460 .LVL22: + 461 .LFB146: + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 462 .loc 1 660 1 is_stmt 1 view -0 + 463 .cfi_startproc + 464 @ args = 0, pretend = 0, frame = 0 + 465 @ frame_needed = 0, uses_anonymous_args = 0 + 466 @ link register save eliminated. + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 467 .loc 1 662 3 view .LVU133 + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 468 .loc 1 667 1 is_stmt 0 view .LVU134 + 469 0000 7047 bx lr + 470 .cfi_endproc + 471 .LFE146: + 473 .section .text.HAL_UART_MspDeInit,"ax",%progbits + 474 .align 1 + 475 .weak HAL_UART_MspDeInit + 476 .syntax unified + 477 .thumb + 478 .thumb_func + 479 .fpu fpv5-d16 + 481 HAL_UART_MspDeInit: + 482 .LVL23: + 483 .LFB147: + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 484 .loc 1 675 1 is_stmt 1 view -0 + 485 .cfi_startproc + 486 @ args = 0, pretend = 0, frame = 0 + 487 @ frame_needed = 0, uses_anonymous_args = 0 + 488 @ link register save eliminated. + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 489 .loc 1 677 3 view .LVU136 + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 490 .loc 1 682 1 is_stmt 0 view .LVU137 + 491 0000 7047 bx lr + 492 .cfi_endproc + 493 .LFE147: + 495 .section .text.HAL_UART_DeInit,"ax",%progbits + 496 .align 1 + 497 .global HAL_UART_DeInit + 498 .syntax unified + 499 .thumb + 500 .thumb_func + ARM GAS /tmp/ccizsdzp.s page 78 + + + 501 .fpu fpv5-d16 + 503 HAL_UART_DeInit: + 504 .LVL24: + 505 .LFB145: + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 506 .loc 1 615 1 is_stmt 1 view -0 + 507 .cfi_startproc + 508 @ args = 0, pretend = 0, frame = 0 + 509 @ frame_needed = 0, uses_anonymous_args = 0 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 510 .loc 1 617 3 view .LVU139 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 511 .loc 1 617 6 is_stmt 0 view .LVU140 + 512 0000 E0B1 cbz r0, .L33 + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 513 .loc 1 615 1 view .LVU141 + 514 0002 38B5 push {r3, r4, r5, lr} + 515 .LCFI0: + 516 .cfi_def_cfa_offset 16 + 517 .cfi_offset 3, -16 + 518 .cfi_offset 4, -12 + 519 .cfi_offset 5, -8 + 520 .cfi_offset 14, -4 + 521 0004 0546 mov r5, r0 + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 522 .loc 1 623 3 is_stmt 1 view .LVU142 + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 523 .loc 1 625 3 view .LVU143 + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 524 .loc 1 625 17 is_stmt 0 view .LVU144 + 525 0006 2423 movs r3, #36 + 526 0008 C0F88030 str r3, [r0, #128] + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 527 .loc 1 627 3 is_stmt 1 view .LVU145 + 528 000c 0268 ldr r2, [r0] + 529 000e 1368 ldr r3, [r2] + 530 0010 23F00103 bic r3, r3, #1 + 531 0014 1360 str r3, [r2] + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 532 .loc 1 629 3 view .LVU146 + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 533 .loc 1 629 8 is_stmt 0 view .LVU147 + 534 0016 0368 ldr r3, [r0] + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 535 .loc 1 629 24 view .LVU148 + 536 0018 0024 movs r4, #0 + 537 001a 1C60 str r4, [r3] + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 538 .loc 1 630 3 is_stmt 1 view .LVU149 + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 539 .loc 1 630 8 is_stmt 0 view .LVU150 + 540 001c 0368 ldr r3, [r0] + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 541 .loc 1 630 24 view .LVU151 + 542 001e 5C60 str r4, [r3, #4] + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 543 .loc 1 631 3 is_stmt 1 view .LVU152 + ARM GAS /tmp/ccizsdzp.s page 79 + + + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 544 .loc 1 631 8 is_stmt 0 view .LVU153 + 545 0020 0368 ldr r3, [r0] + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 546 .loc 1 631 24 view .LVU154 + 547 0022 9C60 str r4, [r3, #8] + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 548 .loc 1 642 3 is_stmt 1 view .LVU155 + 549 0024 FFF7FEFF bl HAL_UART_MspDeInit + 550 .LVL25: + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 551 .loc 1 645 3 view .LVU156 + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 552 .loc 1 645 20 is_stmt 0 view .LVU157 + 553 0028 C5F88840 str r4, [r5, #136] + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 554 .loc 1 646 3 is_stmt 1 view .LVU158 + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 555 .loc 1 646 17 is_stmt 0 view .LVU159 + 556 002c C5F88040 str r4, [r5, #128] + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 557 .loc 1 647 3 is_stmt 1 view .LVU160 + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 558 .loc 1 647 18 is_stmt 0 view .LVU161 + 559 0030 C5F88440 str r4, [r5, #132] + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 560 .loc 1 649 3 is_stmt 1 view .LVU162 + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 561 .loc 1 649 3 view .LVU163 + 562 0034 85F87C40 strb r4, [r5, #124] + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 563 .loc 1 649 3 view .LVU164 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 564 .loc 1 651 3 view .LVU165 + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 565 .loc 1 651 10 is_stmt 0 view .LVU166 + 566 0038 2046 mov r0, r4 + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 567 .loc 1 652 1 view .LVU167 + 568 003a 38BD pop {r3, r4, r5, pc} + 569 .LVL26: + 570 .L33: + 571 .LCFI1: + 572 .cfi_def_cfa_offset 0 + 573 .cfi_restore 3 + 574 .cfi_restore 4 + 575 .cfi_restore 5 + 576 .cfi_restore 14 + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 577 .loc 1 619 12 view .LVU168 + 578 003c 0120 movs r0, #1 + 579 .LVL27: + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 580 .loc 1 652 1 view .LVU169 + 581 003e 7047 bx lr + 582 .cfi_endproc + 583 .LFE145: + ARM GAS /tmp/ccizsdzp.s page 80 + + + 585 .section .text.HAL_UART_Transmit_IT,"ax",%progbits + 586 .align 1 + 587 .global HAL_UART_Transmit_IT + 588 .syntax unified + 589 .thumb + 590 .thumb_func + 591 .fpu fpv5-d16 + 593 HAL_UART_Transmit_IT: + 594 .LVL28: + 595 .LFB150: +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 596 .loc 1 1208 1 is_stmt 1 view -0 + 597 .cfi_startproc + 598 @ args = 0, pretend = 0, frame = 0 + 599 @ frame_needed = 0, uses_anonymous_args = 0 + 600 @ link register save eliminated. +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 601 .loc 1 1210 3 view .LVU171 +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 602 .loc 1 1210 12 is_stmt 0 view .LVU172 + 603 0000 D0F88030 ldr r3, [r0, #128] +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 604 .loc 1 1210 6 view .LVU173 + 605 0004 202B cmp r3, #32 + 606 0006 45D1 bne .L46 +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 607 .loc 1 1212 5 is_stmt 1 view .LVU174 +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 608 .loc 1 1212 8 is_stmt 0 view .LVU175 + 609 0008 002A cmp r2, #0 + 610 000a 18BF it ne + 611 000c 0029 cmpne r1, #0 + 612 000e 43D0 beq .L47 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 613 .loc 1 1217 5 is_stmt 1 view .LVU176 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 614 .loc 1 1217 5 view .LVU177 + 615 0010 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 616 0014 012B cmp r3, #1 + 617 0016 41D0 beq .L48 +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 618 .loc 1 1217 5 discriminator 2 view .LVU178 + 619 0018 0123 movs r3, #1 + 620 001a 80F87C30 strb r3, [r0, #124] +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 621 .loc 1 1217 5 discriminator 2 view .LVU179 +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; + 622 .loc 1 1219 5 discriminator 2 view .LVU180 +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; + 623 .loc 1 1219 24 is_stmt 0 discriminator 2 view .LVU181 + 624 001e 0165 str r1, [r0, #80] +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; + 625 .loc 1 1220 5 is_stmt 1 discriminator 2 view .LVU182 +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; + 626 .loc 1 1220 24 is_stmt 0 discriminator 2 view .LVU183 + 627 0020 A0F85420 strh r2, [r0, #84] @ movhi +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + ARM GAS /tmp/ccizsdzp.s page 81 + + + 628 .loc 1 1221 5 is_stmt 1 discriminator 2 view .LVU184 +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + 629 .loc 1 1221 24 is_stmt 0 discriminator 2 view .LVU185 + 630 0024 A0F85620 strh r2, [r0, #86] @ movhi +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 631 .loc 1 1222 5 is_stmt 1 discriminator 2 view .LVU186 +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 632 .loc 1 1222 24 is_stmt 0 discriminator 2 view .LVU187 + 633 0028 0023 movs r3, #0 + 634 002a 0367 str r3, [r0, #112] +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 635 .loc 1 1224 5 is_stmt 1 discriminator 2 view .LVU188 +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 636 .loc 1 1224 22 is_stmt 0 discriminator 2 view .LVU189 + 637 002c C0F88830 str r3, [r0, #136] +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 638 .loc 1 1225 5 is_stmt 1 discriminator 2 view .LVU190 +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 639 .loc 1 1225 19 is_stmt 0 discriminator 2 view .LVU191 + 640 0030 2123 movs r3, #33 + 641 0032 C0F88030 str r3, [r0, #128] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 642 .loc 1 1228 5 is_stmt 1 discriminator 2 view .LVU192 +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 643 .loc 1 1228 14 is_stmt 0 discriminator 2 view .LVU193 + 644 0036 436E ldr r3, [r0, #100] +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 645 .loc 1 1228 8 discriminator 2 view .LVU194 + 646 0038 B3F1005F cmp r3, #536870912 + 647 003c 0FD0 beq .L49 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 648 .loc 1 1248 7 is_stmt 1 view .LVU195 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 649 .loc 1 1248 23 is_stmt 0 view .LVU196 + 650 003e 8368 ldr r3, [r0, #8] +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 651 .loc 1 1248 10 view .LVU197 + 652 0040 B3F5805F cmp r3, #4096 + 653 0044 20D0 beq .L50 + 654 .L44: +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 655 .loc 1 1254 9 is_stmt 1 view .LVU198 +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 656 .loc 1 1254 22 is_stmt 0 view .LVU199 + 657 0046 164B ldr r3, .L52 + 658 0048 0367 str r3, [r0, #112] + 659 .L45: +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 660 .loc 1 1257 7 is_stmt 1 view .LVU200 +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 661 .loc 1 1257 7 view .LVU201 + 662 004a 0023 movs r3, #0 + 663 004c 80F87C30 strb r3, [r0, #124] +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 664 .loc 1 1257 7 view .LVU202 +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 665 .loc 1 1260 7 view .LVU203 + ARM GAS /tmp/ccizsdzp.s page 82 + + + 666 0050 0268 ldr r2, [r0] + 667 .LVL29: +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 668 .loc 1 1260 7 is_stmt 0 view .LVU204 + 669 0052 1368 ldr r3, [r2] + 670 0054 43F08003 orr r3, r3, #128 + 671 0058 1360 str r3, [r2] + 672 .LVL30: + 673 .L43: +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 674 .loc 1 1263 5 is_stmt 1 view .LVU205 +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 675 .loc 1 1263 12 is_stmt 0 view .LVU206 + 676 005a 0020 movs r0, #0 + 677 .LVL31: +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 678 .loc 1 1263 12 view .LVU207 + 679 005c 7047 bx lr + 680 .LVL32: + 681 .L49: +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 682 .loc 1 1231 7 is_stmt 1 view .LVU208 +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 683 .loc 1 1231 23 is_stmt 0 view .LVU209 + 684 005e 8368 ldr r3, [r0, #8] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 685 .loc 1 1231 10 view .LVU210 + 686 0060 B3F5805F cmp r3, #4096 + 687 0064 0AD0 beq .L51 + 688 .L41: +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 689 .loc 1 1237 9 is_stmt 1 view .LVU211 +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 690 .loc 1 1237 22 is_stmt 0 view .LVU212 + 691 0066 0F4B ldr r3, .L52+4 + 692 0068 0367 str r3, [r0, #112] + 693 .L42: +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 694 .loc 1 1240 7 is_stmt 1 view .LVU213 +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 695 .loc 1 1240 7 view .LVU214 + 696 006a 0023 movs r3, #0 + 697 006c 80F87C30 strb r3, [r0, #124] +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 698 .loc 1 1240 7 view .LVU215 +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 699 .loc 1 1243 7 view .LVU216 + 700 0070 0268 ldr r2, [r0] + 701 .LVL33: +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 702 .loc 1 1243 7 is_stmt 0 view .LVU217 + 703 0072 9368 ldr r3, [r2, #8] + 704 0074 43F40003 orr r3, r3, #8388608 + 705 0078 9360 str r3, [r2, #8] + 706 .LVL34: +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 707 .loc 1 1243 7 view .LVU218 + ARM GAS /tmp/ccizsdzp.s page 83 + + + 708 007a EEE7 b .L43 + 709 .LVL35: + 710 .L51: +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 711 .loc 1 1231 73 discriminator 1 view .LVU219 + 712 007c 0369 ldr r3, [r0, #16] +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 713 .loc 1 1231 58 discriminator 1 view .LVU220 + 714 007e 002B cmp r3, #0 + 715 0080 F1D1 bne .L41 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 716 .loc 1 1233 9 is_stmt 1 view .LVU221 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 717 .loc 1 1233 22 is_stmt 0 view .LVU222 + 718 0082 094B ldr r3, .L52+8 + 719 0084 0367 str r3, [r0, #112] + 720 0086 F0E7 b .L42 + 721 .L50: +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 722 .loc 1 1248 73 discriminator 1 view .LVU223 + 723 0088 0369 ldr r3, [r0, #16] +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 724 .loc 1 1248 58 discriminator 1 view .LVU224 + 725 008a 002B cmp r3, #0 + 726 008c DBD1 bne .L44 +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 727 .loc 1 1250 9 is_stmt 1 view .LVU225 +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 728 .loc 1 1250 22 is_stmt 0 view .LVU226 + 729 008e 074B ldr r3, .L52+12 + 730 0090 0367 str r3, [r0, #112] + 731 0092 DAE7 b .L45 + 732 .L46: +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 733 .loc 1 1267 12 view .LVU227 + 734 0094 0220 movs r0, #2 + 735 .LVL36: +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 736 .loc 1 1267 12 view .LVU228 + 737 0096 7047 bx lr + 738 .LVL37: + 739 .L47: +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 740 .loc 1 1214 14 view .LVU229 + 741 0098 0120 movs r0, #1 + 742 .LVL38: +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 743 .loc 1 1214 14 view .LVU230 + 744 009a 7047 bx lr + 745 .LVL39: + 746 .L48: +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 747 .loc 1 1217 5 view .LVU231 + 748 009c 0220 movs r0, #2 + 749 .LVL40: +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 750 .loc 1 1269 1 view .LVU232 + ARM GAS /tmp/ccizsdzp.s page 84 + + + 751 009e 7047 bx lr + 752 .L53: + 753 .align 2 + 754 .L52: + 755 00a0 00000000 .word UART_TxISR_8BIT + 756 00a4 00000000 .word UART_TxISR_8BIT_FIFOEN + 757 00a8 00000000 .word UART_TxISR_16BIT_FIFOEN + 758 00ac 00000000 .word UART_TxISR_16BIT + 759 .cfi_endproc + 760 .LFE150: + 762 .section .text.HAL_UART_Receive_IT,"ax",%progbits + 763 .align 1 + 764 .global HAL_UART_Receive_IT + 765 .syntax unified + 766 .thumb + 767 .thumb_func + 768 .fpu fpv5-d16 + 770 HAL_UART_Receive_IT: + 771 .LVL41: + 772 .LFB151: +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 773 .loc 1 1282 1 is_stmt 1 view -0 + 774 .cfi_startproc + 775 @ args = 0, pretend = 0, frame = 0 + 776 @ frame_needed = 0, uses_anonymous_args = 0 + 777 @ link register save eliminated. +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 778 .loc 1 1284 3 view .LVU234 +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 779 .loc 1 1284 12 is_stmt 0 view .LVU235 + 780 0000 D0F88430 ldr r3, [r0, #132] +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 781 .loc 1 1284 6 view .LVU236 + 782 0004 202B cmp r3, #32 + 783 0006 7ED1 bne .L69 +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 784 .loc 1 1286 5 is_stmt 1 view .LVU237 +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 785 .loc 1 1286 8 is_stmt 0 view .LVU238 + 786 0008 002A cmp r2, #0 + 787 000a 18BF it ne + 788 000c 0029 cmpne r1, #0 + 789 000e 7CD0 beq .L70 +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 790 .loc 1 1291 5 is_stmt 1 view .LVU239 +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 791 .loc 1 1291 5 view .LVU240 + 792 0010 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 793 0014 012B cmp r3, #1 + 794 0016 7AD0 beq .L71 +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 795 .loc 1 1291 5 discriminator 2 view .LVU241 + 796 0018 0123 movs r3, #1 + 797 001a 80F87C30 strb r3, [r0, #124] +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 798 .loc 1 1291 5 discriminator 2 view .LVU242 +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; + ARM GAS /tmp/ccizsdzp.s page 85 + + + 799 .loc 1 1293 5 discriminator 2 view .LVU243 +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; + 800 .loc 1 1293 24 is_stmt 0 discriminator 2 view .LVU244 + 801 001e 8165 str r1, [r0, #88] +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = Size; + 802 .loc 1 1294 5 is_stmt 1 discriminator 2 view .LVU245 +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = Size; + 803 .loc 1 1294 24 is_stmt 0 discriminator 2 view .LVU246 + 804 0020 A0F85C20 strh r2, [r0, #92] @ movhi +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; + 805 .loc 1 1295 5 is_stmt 1 discriminator 2 view .LVU247 +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; + 806 .loc 1 1295 24 is_stmt 0 discriminator 2 view .LVU248 + 807 0024 A0F85E20 strh r2, [r0, #94] @ movhi +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 808 .loc 1 1296 5 is_stmt 1 discriminator 2 view .LVU249 +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 809 .loc 1 1296 24 is_stmt 0 discriminator 2 view .LVU250 + 810 0028 0023 movs r3, #0 + 811 002a C366 str r3, [r0, #108] +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 812 .loc 1 1299 5 is_stmt 1 discriminator 2 view .LVU251 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 813 .loc 1 1299 5 discriminator 2 view .LVU252 + 814 002c 8368 ldr r3, [r0, #8] + 815 002e B3F5805F cmp r3, #4096 + 816 0032 06D0 beq .L72 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 817 .loc 1 1299 5 discriminator 2 view .LVU253 + 818 0034 A3B9 cbnz r3, .L59 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 819 .loc 1 1299 5 discriminator 5 view .LVU254 + 820 0036 0369 ldr r3, [r0, #16] + 821 0038 73B9 cbnz r3, .L60 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 822 .loc 1 1299 5 discriminator 7 view .LVU255 + 823 003a FF23 movs r3, #255 + 824 003c A0F86030 strh r3, [r0, #96] @ movhi + 825 0040 14E0 b .L58 + 826 .L72: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 827 .loc 1 1299 5 discriminator 1 view .LVU256 + 828 0042 0369 ldr r3, [r0, #16] + 829 0044 23B9 cbnz r3, .L57 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 830 .loc 1 1299 5 discriminator 3 view .LVU257 + 831 0046 40F2FF13 movw r3, #511 + 832 004a A0F86030 strh r3, [r0, #96] @ movhi + 833 004e 0DE0 b .L58 + 834 .L57: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 835 .loc 1 1299 5 discriminator 4 view .LVU258 + 836 0050 FF23 movs r3, #255 + 837 0052 A0F86030 strh r3, [r0, #96] @ movhi + 838 0056 09E0 b .L58 + 839 .L60: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 86 + + + 840 .loc 1 1299 5 discriminator 8 view .LVU259 + 841 0058 7F23 movs r3, #127 + 842 005a A0F86030 strh r3, [r0, #96] @ movhi + 843 005e 05E0 b .L58 + 844 .L59: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 845 .loc 1 1299 5 discriminator 6 view .LVU260 + 846 0060 B3F1805F cmp r3, #268435456 + 847 0064 21D0 beq .L73 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 848 .loc 1 1299 5 discriminator 10 view .LVU261 + 849 0066 0023 movs r3, #0 + 850 0068 A0F86030 strh r3, [r0, #96] @ movhi + 851 .L58: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 852 .loc 1 1299 5 discriminator 13 view .LVU262 +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 853 .loc 1 1301 5 discriminator 13 view .LVU263 +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 854 .loc 1 1301 22 is_stmt 0 discriminator 13 view .LVU264 + 855 006c 0023 movs r3, #0 + 856 006e C0F88830 str r3, [r0, #136] +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 857 .loc 1 1302 5 is_stmt 1 discriminator 13 view .LVU265 +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 858 .loc 1 1302 20 is_stmt 0 discriminator 13 view .LVU266 + 859 0072 2223 movs r3, #34 + 860 0074 C0F88430 str r3, [r0, #132] +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 861 .loc 1 1305 5 is_stmt 1 discriminator 13 view .LVU267 + 862 0078 0168 ldr r1, [r0] + 863 .LVL42: +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 864 .loc 1 1305 5 is_stmt 0 discriminator 13 view .LVU268 + 865 007a 8B68 ldr r3, [r1, #8] + 866 007c 43F00103 orr r3, r3, #1 + 867 0080 8B60 str r3, [r1, #8] + 868 .LVL43: +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 869 .loc 1 1308 5 is_stmt 1 discriminator 13 view .LVU269 +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 870 .loc 1 1308 15 is_stmt 0 discriminator 13 view .LVU270 + 871 0082 436E ldr r3, [r0, #100] +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 872 .loc 1 1308 8 discriminator 13 view .LVU271 + 873 0084 B3F1005F cmp r3, #536870912 + 874 0088 19D0 beq .L74 + 875 .L63: +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 876 .loc 1 1329 7 is_stmt 1 view .LVU272 +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 877 .loc 1 1329 23 is_stmt 0 view .LVU273 + 878 008a 8368 ldr r3, [r0, #8] +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 879 .loc 1 1329 10 view .LVU274 + 880 008c B3F5805F cmp r3, #4096 + 881 0090 33D0 beq .L75 + ARM GAS /tmp/ccizsdzp.s page 87 + + + 882 .L67: +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 883 .loc 1 1335 9 is_stmt 1 view .LVU275 +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 884 .loc 1 1335 22 is_stmt 0 view .LVU276 + 885 0092 204B ldr r3, .L77 + 886 0094 C366 str r3, [r0, #108] + 887 .L68: +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 888 .loc 1 1338 7 is_stmt 1 view .LVU277 +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 889 .loc 1 1338 7 view .LVU278 + 890 0096 0023 movs r3, #0 + 891 0098 80F87C30 strb r3, [r0, #124] +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 892 .loc 1 1338 7 view .LVU279 +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 893 .loc 1 1341 7 view .LVU280 + 894 009c 0268 ldr r2, [r0] + 895 .LVL44: +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 896 .loc 1 1341 7 is_stmt 0 view .LVU281 + 897 009e 1368 ldr r3, [r2] + 898 00a0 43F49073 orr r3, r3, #288 + 899 00a4 1360 str r3, [r2] + 900 .L66: +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 901 .loc 1 1344 5 is_stmt 1 view .LVU282 +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 902 .loc 1 1344 12 is_stmt 0 view .LVU283 + 903 00a6 0020 movs r0, #0 + 904 .LVL45: +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 905 .loc 1 1344 12 view .LVU284 + 906 00a8 7047 bx lr + 907 .LVL46: + 908 .L73: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 909 .loc 1 1299 5 is_stmt 1 discriminator 9 view .LVU285 + 910 00aa 0369 ldr r3, [r0, #16] + 911 00ac 1BB9 cbnz r3, .L62 +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 912 .loc 1 1299 5 discriminator 11 view .LVU286 + 913 00ae 7F23 movs r3, #127 + 914 00b0 A0F86030 strh r3, [r0, #96] @ movhi + 915 00b4 DAE7 b .L58 + 916 .L62: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 917 .loc 1 1299 5 discriminator 12 view .LVU287 + 918 00b6 3F23 movs r3, #63 + 919 00b8 A0F86030 strh r3, [r0, #96] @ movhi + 920 00bc D6E7 b .L58 + 921 .LVL47: + 922 .L74: +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 923 .loc 1 1308 68 is_stmt 0 discriminator 1 view .LVU288 + 924 00be B0F86830 ldrh r3, [r0, #104] + ARM GAS /tmp/ccizsdzp.s page 88 + + +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 925 .loc 1 1308 51 discriminator 1 view .LVU289 + 926 00c2 9342 cmp r3, r2 + 927 00c4 E1D8 bhi .L63 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 928 .loc 1 1311 7 is_stmt 1 view .LVU290 +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 929 .loc 1 1311 23 is_stmt 0 view .LVU291 + 930 00c6 8368 ldr r3, [r0, #8] +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 931 .loc 1 1311 10 view .LVU292 + 932 00c8 B3F5805F cmp r3, #4096 + 933 00cc 0FD0 beq .L76 + 934 .L64: +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 935 .loc 1 1317 9 is_stmt 1 view .LVU293 +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 936 .loc 1 1317 22 is_stmt 0 view .LVU294 + 937 00ce 124B ldr r3, .L77+4 + 938 00d0 C366 str r3, [r0, #108] + 939 .L65: +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 940 .loc 1 1320 7 is_stmt 1 view .LVU295 +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 941 .loc 1 1320 7 view .LVU296 + 942 00d2 0023 movs r3, #0 + 943 00d4 80F87C30 strb r3, [r0, #124] +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 944 .loc 1 1320 7 view .LVU297 +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 945 .loc 1 1323 7 view .LVU298 + 946 00d8 0268 ldr r2, [r0] + 947 .LVL48: +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 948 .loc 1 1323 7 is_stmt 0 view .LVU299 + 949 00da 1368 ldr r3, [r2] + 950 00dc 43F48073 orr r3, r3, #256 + 951 00e0 1360 str r3, [r2] +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 952 .loc 1 1324 7 is_stmt 1 view .LVU300 + 953 00e2 0268 ldr r2, [r0] + 954 00e4 9368 ldr r3, [r2, #8] + 955 00e6 43F08053 orr r3, r3, #268435456 + 956 00ea 9360 str r3, [r2, #8] + 957 00ec DBE7 b .L66 + 958 .LVL49: + 959 .L76: +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 960 .loc 1 1311 73 is_stmt 0 discriminator 1 view .LVU301 + 961 00ee 0369 ldr r3, [r0, #16] +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 962 .loc 1 1311 58 discriminator 1 view .LVU302 + 963 00f0 002B cmp r3, #0 + 964 00f2 ECD1 bne .L64 +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 965 .loc 1 1313 9 is_stmt 1 view .LVU303 +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 89 + + + 966 .loc 1 1313 22 is_stmt 0 view .LVU304 + 967 00f4 094B ldr r3, .L77+8 + 968 00f6 C366 str r3, [r0, #108] + 969 00f8 EBE7 b .L65 + 970 .L75: +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 971 .loc 1 1329 73 discriminator 1 view .LVU305 + 972 00fa 0369 ldr r3, [r0, #16] +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 973 .loc 1 1329 58 discriminator 1 view .LVU306 + 974 00fc 002B cmp r3, #0 + 975 00fe C8D1 bne .L67 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 976 .loc 1 1331 9 is_stmt 1 view .LVU307 +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 977 .loc 1 1331 22 is_stmt 0 view .LVU308 + 978 0100 074B ldr r3, .L77+12 + 979 0102 C366 str r3, [r0, #108] + 980 0104 C7E7 b .L68 + 981 .LVL50: + 982 .L69: +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 983 .loc 1 1348 12 view .LVU309 + 984 0106 0220 movs r0, #2 + 985 .LVL51: +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 986 .loc 1 1348 12 view .LVU310 + 987 0108 7047 bx lr + 988 .LVL52: + 989 .L70: +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 990 .loc 1 1288 14 view .LVU311 + 991 010a 0120 movs r0, #1 + 992 .LVL53: +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 993 .loc 1 1288 14 view .LVU312 + 994 010c 7047 bx lr + 995 .LVL54: + 996 .L71: +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 997 .loc 1 1291 5 view .LVU313 + 998 010e 0220 movs r0, #2 + 999 .LVL55: +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1000 .loc 1 1350 1 view .LVU314 + 1001 0110 7047 bx lr + 1002 .L78: + 1003 0112 00BF .align 2 + 1004 .L77: + 1005 0114 00000000 .word UART_RxISR_8BIT + 1006 0118 00000000 .word UART_RxISR_8BIT_FIFOEN + 1007 011c 00000000 .word UART_RxISR_16BIT_FIFOEN + 1008 0120 00000000 .word UART_RxISR_16BIT + 1009 .cfi_endproc + 1010 .LFE151: + 1012 .section .text.HAL_UART_Transmit_DMA,"ax",%progbits + 1013 .align 1 + ARM GAS /tmp/ccizsdzp.s page 90 + + + 1014 .global HAL_UART_Transmit_DMA + 1015 .syntax unified + 1016 .thumb + 1017 .thumb_func + 1018 .fpu fpv5-d16 + 1020 HAL_UART_Transmit_DMA: + 1021 .LVL56: + 1022 .LFB152: +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 1023 .loc 1 1363 1 is_stmt 1 view -0 + 1024 .cfi_startproc + 1025 @ args = 0, pretend = 0, frame = 0 + 1026 @ frame_needed = 0, uses_anonymous_args = 0 +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 1027 .loc 1 1363 1 is_stmt 0 view .LVU316 + 1028 0000 1346 mov r3, r2 +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1029 .loc 1 1365 3 is_stmt 1 view .LVU317 +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1030 .loc 1 1365 12 is_stmt 0 view .LVU318 + 1031 0002 D0F88020 ldr r2, [r0, #128] + 1032 .LVL57: +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1033 .loc 1 1365 6 view .LVU319 + 1034 0006 202A cmp r2, #32 + 1035 0008 42D1 bne .L82 +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 1036 .loc 1 1363 1 view .LVU320 + 1037 000a 10B5 push {r4, lr} + 1038 .LCFI2: + 1039 .cfi_def_cfa_offset 8 + 1040 .cfi_offset 4, -8 + 1041 .cfi_offset 14, -4 + 1042 000c 0446 mov r4, r0 +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1043 .loc 1 1367 5 is_stmt 1 view .LVU321 +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1044 .loc 1 1367 8 is_stmt 0 view .LVU322 + 1045 000e 002B cmp r3, #0 + 1046 0010 18BF it ne + 1047 0012 0029 cmpne r1, #0 + 1048 0014 3ED0 beq .L83 +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1049 .loc 1 1372 5 is_stmt 1 view .LVU323 +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1050 .loc 1 1372 5 view .LVU324 + 1051 0016 90F87C20 ldrb r2, [r0, #124] @ zero_extendqisi2 + 1052 001a 012A cmp r2, #1 + 1053 001c 3CD0 beq .L84 +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1054 .loc 1 1372 5 discriminator 2 view .LVU325 + 1055 001e 0122 movs r2, #1 + 1056 0020 80F87C20 strb r2, [r0, #124] +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1057 .loc 1 1372 5 discriminator 2 view .LVU326 +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; + 1058 .loc 1 1374 5 discriminator 2 view .LVU327 + ARM GAS /tmp/ccizsdzp.s page 91 + + +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferSize = Size; + 1059 .loc 1 1374 24 is_stmt 0 discriminator 2 view .LVU328 + 1060 0024 0165 str r1, [r0, #80] +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; + 1061 .loc 1 1375 5 is_stmt 1 discriminator 2 view .LVU329 +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; + 1062 .loc 1 1375 24 is_stmt 0 discriminator 2 view .LVU330 + 1063 0026 A0F85430 strh r3, [r0, #84] @ movhi +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1064 .loc 1 1376 5 is_stmt 1 discriminator 2 view .LVU331 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1065 .loc 1 1376 24 is_stmt 0 discriminator 2 view .LVU332 + 1066 002a A0F85630 strh r3, [r0, #86] @ movhi +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 1067 .loc 1 1378 5 is_stmt 1 discriminator 2 view .LVU333 +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 1068 .loc 1 1378 22 is_stmt 0 discriminator 2 view .LVU334 + 1069 002e 0022 movs r2, #0 + 1070 0030 C0F88820 str r2, [r0, #136] +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1071 .loc 1 1379 5 is_stmt 1 discriminator 2 view .LVU335 +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1072 .loc 1 1379 19 is_stmt 0 discriminator 2 view .LVU336 + 1073 0034 2122 movs r2, #33 + 1074 0036 C0F88020 str r2, [r0, #128] +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1075 .loc 1 1381 5 is_stmt 1 discriminator 2 view .LVU337 +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1076 .loc 1 1381 14 is_stmt 0 discriminator 2 view .LVU338 + 1077 003a 426F ldr r2, [r0, #116] +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1078 .loc 1 1381 8 discriminator 2 view .LVU339 + 1079 003c E2B1 cbz r2, .L81 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1080 .loc 1 1384 7 is_stmt 1 view .LVU340 +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1081 .loc 1 1384 39 is_stmt 0 view .LVU341 + 1082 003e 1749 ldr r1, .L89 + 1083 .LVL58: +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1084 .loc 1 1384 39 view .LVU342 + 1085 0040 D163 str r1, [r2, #60] + 1086 .LVL59: +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1087 .loc 1 1387 7 is_stmt 1 view .LVU343 +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1088 .loc 1 1387 12 is_stmt 0 view .LVU344 + 1089 0042 426F ldr r2, [r0, #116] +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1090 .loc 1 1387 43 view .LVU345 + 1091 0044 1649 ldr r1, .L89+4 + 1092 0046 1164 str r1, [r2, #64] +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1093 .loc 1 1390 7 is_stmt 1 view .LVU346 +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1094 .loc 1 1390 12 is_stmt 0 view .LVU347 + 1095 0048 426F ldr r2, [r0, #116] + ARM GAS /tmp/ccizsdzp.s page 92 + + +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1096 .loc 1 1390 40 view .LVU348 + 1097 004a 1649 ldr r1, .L89+8 + 1098 004c D164 str r1, [r2, #76] +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1099 .loc 1 1393 7 is_stmt 1 view .LVU349 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1100 .loc 1 1393 12 is_stmt 0 view .LVU350 + 1101 004e 426F ldr r2, [r0, #116] +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1102 .loc 1 1393 40 view .LVU351 + 1103 0050 0021 movs r1, #0 + 1104 0052 1165 str r1, [r2, #80] +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1105 .loc 1 1396 7 is_stmt 1 view .LVU352 +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1106 .loc 1 1396 88 is_stmt 0 view .LVU353 + 1107 0054 0268 ldr r2, [r0] +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1108 .loc 1 1396 11 view .LVU354 + 1109 0056 2832 adds r2, r2, #40 + 1110 0058 016D ldr r1, [r0, #80] + 1111 005a 406F ldr r0, [r0, #116] + 1112 .LVL60: +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1113 .loc 1 1396 11 view .LVU355 + 1114 005c FFF7FEFF bl HAL_DMA_Start_IT + 1115 .LVL61: +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1116 .loc 1 1396 10 view .LVU356 + 1117 0060 50B1 cbz r0, .L81 +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1118 .loc 1 1399 9 is_stmt 1 view .LVU357 +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1119 .loc 1 1399 26 is_stmt 0 view .LVU358 + 1120 0062 1023 movs r3, #16 + 1121 0064 C4F88830 str r3, [r4, #136] +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1122 .loc 1 1401 9 is_stmt 1 view .LVU359 +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1123 .loc 1 1401 9 view .LVU360 + 1124 0068 0023 movs r3, #0 + 1125 006a 84F87C30 strb r3, [r4, #124] +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1126 .loc 1 1401 9 view .LVU361 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1127 .loc 1 1404 9 view .LVU362 +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1128 .loc 1 1404 23 is_stmt 0 view .LVU363 + 1129 006e 2023 movs r3, #32 + 1130 0070 C4F88030 str r3, [r4, #128] +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1131 .loc 1 1406 9 is_stmt 1 view .LVU364 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1132 .loc 1 1406 16 is_stmt 0 view .LVU365 + 1133 0074 0120 movs r0, #1 + 1134 0076 0AE0 b .L80 + ARM GAS /tmp/ccizsdzp.s page 93 + + + 1135 .L81: +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1136 .loc 1 1410 5 is_stmt 1 view .LVU366 + 1137 0078 2368 ldr r3, [r4] + 1138 007a 4022 movs r2, #64 + 1139 007c 1A62 str r2, [r3, #32] +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1140 .loc 1 1412 5 view .LVU367 +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1141 .loc 1 1412 5 view .LVU368 + 1142 007e 0020 movs r0, #0 + 1143 0080 84F87C00 strb r0, [r4, #124] +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1144 .loc 1 1412 5 view .LVU369 +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1145 .loc 1 1416 5 view .LVU370 + 1146 0084 2268 ldr r2, [r4] + 1147 0086 9368 ldr r3, [r2, #8] + 1148 0088 43F08003 orr r3, r3, #128 + 1149 008c 9360 str r3, [r2, #8] +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1150 .loc 1 1418 5 view .LVU371 + 1151 .L80: +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1152 .loc 1 1424 1 is_stmt 0 view .LVU372 + 1153 008e 10BD pop {r4, pc} + 1154 .LVL62: + 1155 .L82: + 1156 .LCFI3: + 1157 .cfi_def_cfa_offset 0 + 1158 .cfi_restore 4 + 1159 .cfi_restore 14 +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1160 .loc 1 1422 12 view .LVU373 + 1161 0090 0220 movs r0, #2 + 1162 .LVL63: +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1163 .loc 1 1424 1 view .LVU374 + 1164 0092 7047 bx lr + 1165 .LVL64: + 1166 .L83: + 1167 .LCFI4: + 1168 .cfi_def_cfa_offset 8 + 1169 .cfi_offset 4, -8 + 1170 .cfi_offset 14, -4 +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1171 .loc 1 1369 14 view .LVU375 + 1172 0094 0120 movs r0, #1 + 1173 .LVL65: +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1174 .loc 1 1369 14 view .LVU376 + 1175 0096 FAE7 b .L80 + 1176 .LVL66: + 1177 .L84: +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1178 .loc 1 1372 5 view .LVU377 + 1179 0098 0220 movs r0, #2 + ARM GAS /tmp/ccizsdzp.s page 94 + + + 1180 .LVL67: +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1181 .loc 1 1372 5 view .LVU378 + 1182 009a F8E7 b .L80 + 1183 .L90: + 1184 .align 2 + 1185 .L89: + 1186 009c 00000000 .word UART_DMATransmitCplt + 1187 00a0 00000000 .word UART_DMATxHalfCplt + 1188 00a4 00000000 .word UART_DMAError + 1189 .cfi_endproc + 1190 .LFE152: + 1192 .section .text.HAL_UART_Receive_DMA,"ax",%progbits + 1193 .align 1 + 1194 .global HAL_UART_Receive_DMA + 1195 .syntax unified + 1196 .thumb + 1197 .thumb_func + 1198 .fpu fpv5-d16 + 1200 HAL_UART_Receive_DMA: + 1201 .LVL68: + 1202 .LFB153: +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 1203 .loc 1 1439 1 is_stmt 1 view -0 + 1204 .cfi_startproc + 1205 @ args = 0, pretend = 0, frame = 0 + 1206 @ frame_needed = 0, uses_anonymous_args = 0 +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 1207 .loc 1 1439 1 is_stmt 0 view .LVU380 + 1208 0000 1346 mov r3, r2 +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1209 .loc 1 1441 3 is_stmt 1 view .LVU381 +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1210 .loc 1 1441 12 is_stmt 0 view .LVU382 + 1211 0002 D0F88420 ldr r2, [r0, #132] + 1212 .LVL69: +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1213 .loc 1 1441 6 view .LVU383 + 1214 0006 202A cmp r2, #32 + 1215 0008 47D1 bne .L94 +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 1216 .loc 1 1439 1 view .LVU384 + 1217 000a 10B5 push {r4, lr} + 1218 .LCFI5: + 1219 .cfi_def_cfa_offset 8 + 1220 .cfi_offset 4, -8 + 1221 .cfi_offset 14, -4 + 1222 000c 0446 mov r4, r0 +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1223 .loc 1 1443 5 is_stmt 1 view .LVU385 +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1224 .loc 1 1443 8 is_stmt 0 view .LVU386 + 1225 000e 002B cmp r3, #0 + 1226 0010 18BF it ne + 1227 0012 0029 cmpne r1, #0 + 1228 0014 43D0 beq .L95 +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 95 + + + 1229 .loc 1 1448 5 is_stmt 1 view .LVU387 +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1230 .loc 1 1448 5 view .LVU388 + 1231 0016 90F87C20 ldrb r2, [r0, #124] @ zero_extendqisi2 + 1232 001a 012A cmp r2, #1 + 1233 001c 41D0 beq .L96 +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1234 .loc 1 1448 5 discriminator 2 view .LVU389 + 1235 001e 0122 movs r2, #1 + 1236 0020 80F87C20 strb r2, [r0, #124] +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1237 .loc 1 1448 5 discriminator 2 view .LVU390 +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; + 1238 .loc 1 1450 5 discriminator 2 view .LVU391 +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferSize = Size; + 1239 .loc 1 1450 23 is_stmt 0 discriminator 2 view .LVU392 + 1240 0024 8165 str r1, [r0, #88] +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1241 .loc 1 1451 5 is_stmt 1 discriminator 2 view .LVU393 +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1242 .loc 1 1451 23 is_stmt 0 discriminator 2 view .LVU394 + 1243 0026 A0F85C30 strh r3, [r0, #92] @ movhi +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 1244 .loc 1 1453 5 is_stmt 1 discriminator 2 view .LVU395 +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 1245 .loc 1 1453 22 is_stmt 0 discriminator 2 view .LVU396 + 1246 002a 0022 movs r2, #0 + 1247 002c C0F88820 str r2, [r0, #136] +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1248 .loc 1 1454 5 is_stmt 1 discriminator 2 view .LVU397 +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1249 .loc 1 1454 20 is_stmt 0 discriminator 2 view .LVU398 + 1250 0030 2222 movs r2, #34 + 1251 0032 C0F88420 str r2, [r0, #132] +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1252 .loc 1 1456 5 is_stmt 1 discriminator 2 view .LVU399 +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1253 .loc 1 1456 14 is_stmt 0 discriminator 2 view .LVU400 + 1254 0036 826F ldr r2, [r0, #120] +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1255 .loc 1 1456 8 discriminator 2 view .LVU401 + 1256 0038 E2B1 cbz r2, .L93 +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1257 .loc 1 1459 7 is_stmt 1 view .LVU402 +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1258 .loc 1 1459 39 is_stmt 0 view .LVU403 + 1259 003a 1B49 ldr r1, .L101 + 1260 .LVL70: +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1261 .loc 1 1459 39 view .LVU404 + 1262 003c D163 str r1, [r2, #60] + 1263 .LVL71: +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1264 .loc 1 1462 7 is_stmt 1 view .LVU405 +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1265 .loc 1 1462 12 is_stmt 0 view .LVU406 + 1266 003e 826F ldr r2, [r0, #120] + ARM GAS /tmp/ccizsdzp.s page 96 + + +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1267 .loc 1 1462 43 view .LVU407 + 1268 0040 1A49 ldr r1, .L101+4 + 1269 0042 1164 str r1, [r2, #64] +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1270 .loc 1 1465 7 is_stmt 1 view .LVU408 +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1271 .loc 1 1465 12 is_stmt 0 view .LVU409 + 1272 0044 826F ldr r2, [r0, #120] +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1273 .loc 1 1465 40 view .LVU410 + 1274 0046 1A49 ldr r1, .L101+8 + 1275 0048 D164 str r1, [r2, #76] +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1276 .loc 1 1468 7 is_stmt 1 view .LVU411 +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1277 .loc 1 1468 12 is_stmt 0 view .LVU412 + 1278 004a 826F ldr r2, [r0, #120] +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1279 .loc 1 1468 40 view .LVU413 + 1280 004c 0021 movs r1, #0 + 1281 004e 1165 str r1, [r2, #80] +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1282 .loc 1 1471 7 is_stmt 1 view .LVU414 +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1283 .loc 1 1471 59 is_stmt 0 view .LVU415 + 1284 0050 0168 ldr r1, [r0] +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1285 .loc 1 1471 11 view .LVU416 + 1286 0052 826D ldr r2, [r0, #88] + 1287 0054 2431 adds r1, r1, #36 + 1288 0056 806F ldr r0, [r0, #120] + 1289 .LVL72: +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1290 .loc 1 1471 11 view .LVU417 + 1291 0058 FFF7FEFF bl HAL_DMA_Start_IT + 1292 .LVL73: +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1293 .loc 1 1471 10 view .LVU418 + 1294 005c 50B1 cbz r0, .L93 +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1295 .loc 1 1474 9 is_stmt 1 view .LVU419 +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1296 .loc 1 1474 26 is_stmt 0 view .LVU420 + 1297 005e 1023 movs r3, #16 + 1298 0060 C4F88830 str r3, [r4, #136] +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1299 .loc 1 1476 9 is_stmt 1 view .LVU421 +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1300 .loc 1 1476 9 view .LVU422 + 1301 0064 0023 movs r3, #0 + 1302 0066 84F87C30 strb r3, [r4, #124] +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1303 .loc 1 1476 9 view .LVU423 +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1304 .loc 1 1479 9 view .LVU424 +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 97 + + + 1305 .loc 1 1479 23 is_stmt 0 view .LVU425 + 1306 006a 2023 movs r3, #32 + 1307 006c C4F88030 str r3, [r4, #128] +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1308 .loc 1 1481 9 is_stmt 1 view .LVU426 +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1309 .loc 1 1481 16 is_stmt 0 view .LVU427 + 1310 0070 0120 movs r0, #1 + 1311 0072 11E0 b .L92 + 1312 .L93: +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1313 .loc 1 1484 5 is_stmt 1 view .LVU428 +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1314 .loc 1 1484 5 view .LVU429 + 1315 0074 0020 movs r0, #0 + 1316 0076 84F87C00 strb r0, [r4, #124] +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1317 .loc 1 1484 5 view .LVU430 +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1318 .loc 1 1487 5 view .LVU431 + 1319 007a 2268 ldr r2, [r4] + 1320 007c 1368 ldr r3, [r2] + 1321 007e 43F48073 orr r3, r3, #256 + 1322 0082 1360 str r3, [r2] +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1323 .loc 1 1490 5 view .LVU432 + 1324 0084 2268 ldr r2, [r4] + 1325 0086 9368 ldr r3, [r2, #8] + 1326 0088 43F00103 orr r3, r3, #1 + 1327 008c 9360 str r3, [r2, #8] +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1328 .loc 1 1494 5 view .LVU433 + 1329 008e 2268 ldr r2, [r4] + 1330 0090 9368 ldr r3, [r2, #8] + 1331 0092 43F04003 orr r3, r3, #64 + 1332 0096 9360 str r3, [r2, #8] +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1333 .loc 1 1496 5 view .LVU434 + 1334 .L92: +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1335 .loc 1 1502 1 is_stmt 0 view .LVU435 + 1336 0098 10BD pop {r4, pc} + 1337 .LVL74: + 1338 .L94: + 1339 .LCFI6: + 1340 .cfi_def_cfa_offset 0 + 1341 .cfi_restore 4 + 1342 .cfi_restore 14 +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1343 .loc 1 1500 12 view .LVU436 + 1344 009a 0220 movs r0, #2 + 1345 .LVL75: +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1346 .loc 1 1502 1 view .LVU437 + 1347 009c 7047 bx lr + 1348 .LVL76: + 1349 .L95: + ARM GAS /tmp/ccizsdzp.s page 98 + + + 1350 .LCFI7: + 1351 .cfi_def_cfa_offset 8 + 1352 .cfi_offset 4, -8 + 1353 .cfi_offset 14, -4 +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1354 .loc 1 1445 14 view .LVU438 + 1355 009e 0120 movs r0, #1 + 1356 .LVL77: +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1357 .loc 1 1445 14 view .LVU439 + 1358 00a0 FAE7 b .L92 + 1359 .LVL78: + 1360 .L96: +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1361 .loc 1 1448 5 view .LVU440 + 1362 00a2 0220 movs r0, #2 + 1363 .LVL79: +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1364 .loc 1 1448 5 view .LVU441 + 1365 00a4 F8E7 b .L92 + 1366 .L102: + 1367 00a6 00BF .align 2 + 1368 .L101: + 1369 00a8 00000000 .word UART_DMAReceiveCplt + 1370 00ac 00000000 .word UART_DMARxHalfCplt + 1371 00b0 00000000 .word UART_DMAError + 1372 .cfi_endproc + 1373 .LFE153: + 1375 .section .text.HAL_UART_DMAPause,"ax",%progbits + 1376 .align 1 + 1377 .global HAL_UART_DMAPause + 1378 .syntax unified + 1379 .thumb + 1380 .thumb_func + 1381 .fpu fpv5-d16 + 1383 HAL_UART_DMAPause: + 1384 .LVL80: + 1385 .LFB154: +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; + 1386 .loc 1 1510 1 is_stmt 1 view -0 + 1387 .cfi_startproc + 1388 @ args = 0, pretend = 0, frame = 0 + 1389 @ frame_needed = 0, uses_anonymous_args = 0 + 1390 @ link register save eliminated. +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; + 1391 .loc 1 1510 1 is_stmt 0 view .LVU443 + 1392 0000 10B4 push {r4} + 1393 .LCFI8: + 1394 .cfi_def_cfa_offset 4 + 1395 .cfi_offset 4, -4 +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1396 .loc 1 1511 3 is_stmt 1 view .LVU444 +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1397 .loc 1 1511 31 is_stmt 0 view .LVU445 + 1398 0002 D0F88040 ldr r4, [r0, #128] + 1399 .LVL81: +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 99 + + + 1400 .loc 1 1512 3 is_stmt 1 view .LVU446 +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1401 .loc 1 1512 31 is_stmt 0 view .LVU447 + 1402 0006 D0F88410 ldr r1, [r0, #132] + 1403 .LVL82: +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1404 .loc 1 1514 3 is_stmt 1 view .LVU448 +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1405 .loc 1 1514 3 view .LVU449 + 1406 000a 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 1407 000e 012B cmp r3, #1 + 1408 0010 2BD0 beq .L107 +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1409 .loc 1 1514 3 discriminator 2 view .LVU450 + 1410 0012 0123 movs r3, #1 + 1411 0014 80F87C30 strb r3, [r0, #124] +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1412 .loc 1 1514 3 discriminator 2 view .LVU451 +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1413 .loc 1 1516 3 discriminator 2 view .LVU452 +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1414 .loc 1 1516 8 is_stmt 0 discriminator 2 view .LVU453 + 1415 0018 0368 ldr r3, [r0] + 1416 001a 9A68 ldr r2, [r3, #8] +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1417 .loc 1 1516 6 discriminator 2 view .LVU454 + 1418 001c 12F0800F tst r2, #128 + 1419 0020 01D0 beq .L105 +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1420 .loc 1 1516 62 discriminator 1 view .LVU455 + 1421 0022 212C cmp r4, #33 + 1422 0024 0DD0 beq .L109 + 1423 .L105: +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1424 .loc 1 1522 3 is_stmt 1 view .LVU456 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1425 .loc 1 1522 8 is_stmt 0 view .LVU457 + 1426 0026 0368 ldr r3, [r0] + 1427 0028 9A68 ldr r2, [r3, #8] +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1428 .loc 1 1522 6 view .LVU458 + 1429 002a 12F0400F tst r2, #64 + 1430 002e 01D0 beq .L106 +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1431 .loc 1 1522 62 discriminator 1 view .LVU459 + 1432 0030 2229 cmp r1, #34 + 1433 0032 0BD0 beq .L110 + 1434 .L106: +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1435 .loc 1 1533 3 is_stmt 1 view .LVU460 +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1436 .loc 1 1533 3 view .LVU461 + 1437 0034 0023 movs r3, #0 + 1438 0036 80F87C30 strb r3, [r0, #124] +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1439 .loc 1 1533 3 view .LVU462 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 100 + + + 1440 .loc 1 1535 3 view .LVU463 +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1441 .loc 1 1535 10 is_stmt 0 view .LVU464 + 1442 003a 1846 mov r0, r3 + 1443 .LVL83: + 1444 .L104: +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1445 .loc 1 1536 1 view .LVU465 + 1446 003c 5DF8044B ldr r4, [sp], #4 + 1447 .LCFI9: + 1448 .cfi_remember_state + 1449 .cfi_restore 4 + 1450 .cfi_def_cfa_offset 0 + 1451 .LVL84: +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1452 .loc 1 1536 1 view .LVU466 + 1453 0040 7047 bx lr + 1454 .LVL85: + 1455 .L109: + 1456 .LCFI10: + 1457 .cfi_restore_state +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1458 .loc 1 1520 5 is_stmt 1 view .LVU467 + 1459 0042 9A68 ldr r2, [r3, #8] + 1460 0044 22F08002 bic r2, r2, #128 + 1461 0048 9A60 str r2, [r3, #8] + 1462 004a ECE7 b .L105 + 1463 .L110: +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1464 .loc 1 1526 5 view .LVU468 + 1465 004c 1A68 ldr r2, [r3] + 1466 004e 22F48072 bic r2, r2, #256 + 1467 0052 1A60 str r2, [r3] +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1468 .loc 1 1527 5 view .LVU469 + 1469 0054 0268 ldr r2, [r0] + 1470 0056 9368 ldr r3, [r2, #8] + 1471 0058 23F00103 bic r3, r3, #1 + 1472 005c 9360 str r3, [r2, #8] +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1473 .loc 1 1530 5 view .LVU470 + 1474 005e 0268 ldr r2, [r0] + 1475 0060 9368 ldr r3, [r2, #8] + 1476 0062 23F04003 bic r3, r3, #64 + 1477 0066 9360 str r3, [r2, #8] + 1478 0068 E4E7 b .L106 + 1479 .L107: +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1480 .loc 1 1514 3 is_stmt 0 view .LVU471 + 1481 006a 0220 movs r0, #2 + 1482 .LVL86: +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1483 .loc 1 1514 3 view .LVU472 + 1484 006c E6E7 b .L104 + 1485 .cfi_endproc + 1486 .LFE154: + 1488 .section .text.HAL_UART_DMAResume,"ax",%progbits + ARM GAS /tmp/ccizsdzp.s page 101 + + + 1489 .align 1 + 1490 .global HAL_UART_DMAResume + 1491 .syntax unified + 1492 .thumb + 1493 .thumb_func + 1494 .fpu fpv5-d16 + 1496 HAL_UART_DMAResume: + 1497 .LVL87: + 1498 .LFB155: +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 1499 .loc 1 1544 1 is_stmt 1 view -0 + 1500 .cfi_startproc + 1501 @ args = 0, pretend = 0, frame = 0 + 1502 @ frame_needed = 0, uses_anonymous_args = 0 + 1503 @ link register save eliminated. +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1504 .loc 1 1545 3 view .LVU474 +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1505 .loc 1 1545 3 view .LVU475 + 1506 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 1507 0004 012B cmp r3, #1 + 1508 0006 28D0 beq .L115 +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1509 .loc 1 1545 3 discriminator 2 view .LVU476 + 1510 0008 0123 movs r3, #1 + 1511 000a 80F87C30 strb r3, [r0, #124] +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1512 .loc 1 1545 3 discriminator 2 view .LVU477 +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1513 .loc 1 1547 3 discriminator 2 view .LVU478 +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1514 .loc 1 1547 12 is_stmt 0 discriminator 2 view .LVU479 + 1515 000e D0F88030 ldr r3, [r0, #128] +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1516 .loc 1 1547 6 discriminator 2 view .LVU480 + 1517 0012 212B cmp r3, #33 + 1518 0014 08D0 beq .L116 + 1519 .L113: +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1520 .loc 1 1552 3 is_stmt 1 view .LVU481 +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1521 .loc 1 1552 12 is_stmt 0 view .LVU482 + 1522 0016 D0F88430 ldr r3, [r0, #132] +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1523 .loc 1 1552 6 view .LVU483 + 1524 001a 222B cmp r3, #34 + 1525 001c 0AD0 beq .L117 + 1526 .L114: +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1527 .loc 1 1565 3 is_stmt 1 view .LVU484 +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1528 .loc 1 1565 3 view .LVU485 + 1529 001e 0023 movs r3, #0 + 1530 0020 80F87C30 strb r3, [r0, #124] +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1531 .loc 1 1565 3 view .LVU486 +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 102 + + + 1532 .loc 1 1567 3 view .LVU487 +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1533 .loc 1 1567 10 is_stmt 0 view .LVU488 + 1534 0024 1846 mov r0, r3 + 1535 .LVL88: +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1536 .loc 1 1567 10 view .LVU489 + 1537 0026 7047 bx lr + 1538 .LVL89: + 1539 .L116: +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1540 .loc 1 1550 5 is_stmt 1 view .LVU490 + 1541 0028 0268 ldr r2, [r0] + 1542 002a 9368 ldr r3, [r2, #8] + 1543 002c 43F08003 orr r3, r3, #128 + 1544 0030 9360 str r3, [r2, #8] + 1545 0032 F0E7 b .L113 + 1546 .L117: +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1547 .loc 1 1555 5 view .LVU491 + 1548 0034 0368 ldr r3, [r0] + 1549 0036 0822 movs r2, #8 + 1550 0038 1A62 str r2, [r3, #32] +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1551 .loc 1 1558 5 view .LVU492 + 1552 003a 0268 ldr r2, [r0] + 1553 003c 1368 ldr r3, [r2] + 1554 003e 43F48073 orr r3, r3, #256 + 1555 0042 1360 str r3, [r2] +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1556 .loc 1 1559 5 view .LVU493 + 1557 0044 0268 ldr r2, [r0] + 1558 0046 9368 ldr r3, [r2, #8] + 1559 0048 43F00103 orr r3, r3, #1 + 1560 004c 9360 str r3, [r2, #8] +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1561 .loc 1 1562 5 view .LVU494 + 1562 004e 0268 ldr r2, [r0] + 1563 0050 9368 ldr r3, [r2, #8] + 1564 0052 43F04003 orr r3, r3, #64 + 1565 0056 9360 str r3, [r2, #8] + 1566 0058 E1E7 b .L114 + 1567 .L115: +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1568 .loc 1 1545 3 is_stmt 0 view .LVU495 + 1569 005a 0220 movs r0, #2 + 1570 .LVL90: +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1571 .loc 1 1568 1 view .LVU496 + 1572 005c 7047 bx lr + 1573 .cfi_endproc + 1574 .LFE155: + 1576 .section .text.HAL_UART_DMAStop,"ax",%progbits + 1577 .align 1 + 1578 .global HAL_UART_DMAStop + 1579 .syntax unified + 1580 .thumb + ARM GAS /tmp/ccizsdzp.s page 103 + + + 1581 .thumb_func + 1582 .fpu fpv5-d16 + 1584 HAL_UART_DMAStop: + 1585 .LVL91: + 1586 .LFB156: +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application + 1587 .loc 1 1576 1 is_stmt 1 view -0 + 1588 .cfi_startproc + 1589 @ args = 0, pretend = 0, frame = 0 + 1590 @ frame_needed = 0, uses_anonymous_args = 0 +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application + 1591 .loc 1 1576 1 is_stmt 0 view .LVU498 + 1592 0000 38B5 push {r3, r4, r5, lr} + 1593 .LCFI11: + 1594 .cfi_def_cfa_offset 16 + 1595 .cfi_offset 3, -16 + 1596 .cfi_offset 4, -12 + 1597 .cfi_offset 5, -8 + 1598 .cfi_offset 14, -4 + 1599 0002 0446 mov r4, r0 +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1600 .loc 1 1584 3 is_stmt 1 view .LVU499 +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1601 .loc 1 1584 31 is_stmt 0 view .LVU500 + 1602 0004 D0F88010 ldr r1, [r0, #128] + 1603 .LVL92: +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1604 .loc 1 1585 3 is_stmt 1 view .LVU501 +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1605 .loc 1 1585 31 is_stmt 0 view .LVU502 + 1606 0008 D0F88450 ldr r5, [r0, #132] + 1607 .LVL93: +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1608 .loc 1 1588 3 is_stmt 1 view .LVU503 +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1609 .loc 1 1588 8 is_stmt 0 view .LVU504 + 1610 000c 0368 ldr r3, [r0] + 1611 000e 9A68 ldr r2, [r3, #8] +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1612 .loc 1 1588 6 view .LVU505 + 1613 0010 12F0800F tst r2, #128 + 1614 0014 01D0 beq .L119 +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1615 .loc 1 1588 62 discriminator 1 view .LVU506 + 1616 0016 2129 cmp r1, #33 + 1617 0018 08D0 beq .L126 + 1618 .LVL94: + 1619 .L119: +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1620 .loc 1 1612 3 is_stmt 1 view .LVU507 +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1621 .loc 1 1612 8 is_stmt 0 view .LVU508 + 1622 001a 2368 ldr r3, [r4] + 1623 001c 9A68 ldr r2, [r3, #8] +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1624 .loc 1 1612 6 view .LVU509 + 1625 001e 12F0400F tst r2, #64 + ARM GAS /tmp/ccizsdzp.s page 104 + + + 1626 0022 32D0 beq .L123 +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1627 .loc 1 1612 62 discriminator 1 view .LVU510 + 1628 0024 222D cmp r5, #34 + 1629 0026 18D0 beq .L127 +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1630 .loc 1 1635 10 view .LVU511 + 1631 0028 0020 movs r0, #0 + 1632 002a 2FE0 b .L121 + 1633 .LVL95: + 1634 .L126: +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1635 .loc 1 1591 5 is_stmt 1 view .LVU512 + 1636 002c 9A68 ldr r2, [r3, #8] + 1637 002e 22F08002 bic r2, r2, #128 + 1638 0032 9A60 str r2, [r3, #8] +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1639 .loc 1 1594 5 view .LVU513 +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1640 .loc 1 1594 14 is_stmt 0 view .LVU514 + 1641 0034 406F ldr r0, [r0, #116] + 1642 .LVL96: +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1643 .loc 1 1594 8 view .LVU515 + 1644 0036 10B1 cbz r0, .L120 +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1645 .loc 1 1596 7 is_stmt 1 view .LVU516 +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1646 .loc 1 1596 11 is_stmt 0 view .LVU517 + 1647 0038 FFF7FEFF bl HAL_DMA_Abort + 1648 .LVL97: +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1649 .loc 1 1596 10 view .LVU518 + 1650 003c 18B9 cbnz r0, .L128 + 1651 .L120: +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1652 .loc 1 1608 5 is_stmt 1 view .LVU519 + 1653 003e 2046 mov r0, r4 + 1654 0040 FFF7FEFF bl UART_EndTxTransfer + 1655 .LVL98: + 1656 0044 E9E7 b .L119 + 1657 .L128: +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1658 .loc 1 1598 9 view .LVU520 +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1659 .loc 1 1598 13 is_stmt 0 view .LVU521 + 1660 0046 606F ldr r0, [r4, #116] + 1661 0048 FFF7FEFF bl HAL_DMA_GetError + 1662 .LVL99: +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1663 .loc 1 1598 12 view .LVU522 + 1664 004c 2028 cmp r0, #32 + 1665 004e F6D1 bne .L120 +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1666 .loc 1 1601 11 is_stmt 1 view .LVU523 +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1667 .loc 1 1601 28 is_stmt 0 view .LVU524 + ARM GAS /tmp/ccizsdzp.s page 105 + + + 1668 0050 1023 movs r3, #16 + 1669 0052 C4F88830 str r3, [r4, #136] +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1670 .loc 1 1603 11 is_stmt 1 view .LVU525 +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1671 .loc 1 1603 18 is_stmt 0 view .LVU526 + 1672 0056 0320 movs r0, #3 + 1673 0058 18E0 b .L121 + 1674 .L127: +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1675 .loc 1 1615 5 is_stmt 1 view .LVU527 + 1676 005a 9A68 ldr r2, [r3, #8] + 1677 005c 22F04002 bic r2, r2, #64 + 1678 0060 9A60 str r2, [r3, #8] +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1679 .loc 1 1618 5 view .LVU528 +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1680 .loc 1 1618 14 is_stmt 0 view .LVU529 + 1681 0062 A06F ldr r0, [r4, #120] +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1682 .loc 1 1618 8 view .LVU530 + 1683 0064 10B1 cbz r0, .L122 +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1684 .loc 1 1620 7 is_stmt 1 view .LVU531 +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1685 .loc 1 1620 11 is_stmt 0 view .LVU532 + 1686 0066 FFF7FEFF bl HAL_DMA_Abort + 1687 .LVL100: +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1688 .loc 1 1620 10 view .LVU533 + 1689 006a 20B9 cbnz r0, .L129 + 1690 .L122: +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1691 .loc 1 1632 5 is_stmt 1 view .LVU534 + 1692 006c 2046 mov r0, r4 + 1693 006e FFF7FEFF bl UART_EndRxTransfer + 1694 .LVL101: +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1695 .loc 1 1635 10 is_stmt 0 view .LVU535 + 1696 0072 0020 movs r0, #0 + 1697 0074 0AE0 b .L121 + 1698 .L129: +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1699 .loc 1 1622 9 is_stmt 1 view .LVU536 +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1700 .loc 1 1622 13 is_stmt 0 view .LVU537 + 1701 0076 A06F ldr r0, [r4, #120] + 1702 0078 FFF7FEFF bl HAL_DMA_GetError + 1703 .LVL102: +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1704 .loc 1 1622 12 view .LVU538 + 1705 007c 2028 cmp r0, #32 + 1706 007e F5D1 bne .L122 +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1707 .loc 1 1625 11 is_stmt 1 view .LVU539 +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1708 .loc 1 1625 28 is_stmt 0 view .LVU540 + ARM GAS /tmp/ccizsdzp.s page 106 + + + 1709 0080 1023 movs r3, #16 + 1710 0082 C4F88830 str r3, [r4, #136] +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1711 .loc 1 1627 11 is_stmt 1 view .LVU541 +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1712 .loc 1 1627 18 is_stmt 0 view .LVU542 + 1713 0086 0320 movs r0, #3 + 1714 0088 00E0 b .L121 + 1715 .L123: +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1716 .loc 1 1635 10 view .LVU543 + 1717 008a 0020 movs r0, #0 + 1718 .L121: +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1719 .loc 1 1636 1 view .LVU544 + 1720 008c 38BD pop {r3, r4, r5, pc} +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1721 .loc 1 1636 1 view .LVU545 + 1722 .cfi_endproc + 1723 .LFE156: + 1725 .section .text.HAL_UART_Abort,"ax",%progbits + 1726 .align 1 + 1727 .global HAL_UART_Abort + 1728 .syntax unified + 1729 .thumb + 1730 .thumb_func + 1731 .fpu fpv5-d16 + 1733 HAL_UART_Abort: + 1734 .LVL103: + 1735 .LFB157: +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interr + 1736 .loc 1 1651 1 is_stmt 1 view -0 + 1737 .cfi_startproc + 1738 @ args = 0, pretend = 0, frame = 0 + 1739 @ frame_needed = 0, uses_anonymous_args = 0 +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interr + 1740 .loc 1 1651 1 is_stmt 0 view .LVU547 + 1741 0000 10B5 push {r4, lr} + 1742 .LCFI12: + 1743 .cfi_def_cfa_offset 8 + 1744 .cfi_offset 4, -8 + 1745 .cfi_offset 14, -4 + 1746 0002 0446 mov r4, r0 +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + 1747 .loc 1 1653 3 is_stmt 1 view .LVU548 + 1748 0004 0268 ldr r2, [r0] + 1749 0006 1368 ldr r3, [r2] + 1750 0008 23F4F073 bic r3, r3, #480 + 1751 000c 1360 str r3, [r2] +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1752 .loc 1 1654 3 view .LVU549 + 1753 000e 0268 ldr r2, [r0] + 1754 0010 9168 ldr r1, [r2, #8] + 1755 0012 2C4B ldr r3, .L139 + 1756 0014 0B40 ands r3, r3, r1 + 1757 0016 9360 str r3, [r2, #8] +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 107 + + + 1758 .loc 1 1657 3 view .LVU550 +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1759 .loc 1 1657 7 is_stmt 0 view .LVU551 + 1760 0018 0368 ldr r3, [r0] + 1761 001a 9A68 ldr r2, [r3, #8] +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1762 .loc 1 1657 6 view .LVU552 + 1763 001c 12F0800F tst r2, #128 + 1764 0020 0BD0 beq .L131 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1765 .loc 1 1659 5 is_stmt 1 view .LVU553 + 1766 0022 9A68 ldr r2, [r3, #8] + 1767 0024 22F08002 bic r2, r2, #128 + 1768 0028 9A60 str r2, [r3, #8] +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1769 .loc 1 1662 5 view .LVU554 +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1770 .loc 1 1662 14 is_stmt 0 view .LVU555 + 1771 002a 436F ldr r3, [r0, #116] +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1772 .loc 1 1662 8 view .LVU556 + 1773 002c 2BB1 cbz r3, .L131 +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1774 .loc 1 1666 7 is_stmt 1 view .LVU557 +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1775 .loc 1 1666 40 is_stmt 0 view .LVU558 + 1776 002e 0022 movs r2, #0 + 1777 0030 1A65 str r2, [r3, #80] +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1778 .loc 1 1668 7 is_stmt 1 view .LVU559 +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1779 .loc 1 1668 11 is_stmt 0 view .LVU560 + 1780 0032 406F ldr r0, [r0, #116] + 1781 .LVL104: +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1782 .loc 1 1668 11 view .LVU561 + 1783 0034 FFF7FEFF bl HAL_DMA_Abort + 1784 .LVL105: +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1785 .loc 1 1668 10 view .LVU562 + 1786 0038 50BB cbnz r0, .L136 + 1787 .L131: +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1788 .loc 1 1682 3 is_stmt 1 view .LVU563 +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1789 .loc 1 1682 7 is_stmt 0 view .LVU564 + 1790 003a 2368 ldr r3, [r4] + 1791 003c 9A68 ldr r2, [r3, #8] +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1792 .loc 1 1682 6 view .LVU565 + 1793 003e 12F0400F tst r2, #64 + 1794 0042 0BD0 beq .L133 +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1795 .loc 1 1684 5 is_stmt 1 view .LVU566 + 1796 0044 9A68 ldr r2, [r3, #8] + 1797 0046 22F04002 bic r2, r2, #64 + 1798 004a 9A60 str r2, [r3, #8] + ARM GAS /tmp/ccizsdzp.s page 108 + + +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1799 .loc 1 1687 5 view .LVU567 +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1800 .loc 1 1687 14 is_stmt 0 view .LVU568 + 1801 004c A36F ldr r3, [r4, #120] +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1802 .loc 1 1687 8 view .LVU569 + 1803 004e 2BB1 cbz r3, .L133 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1804 .loc 1 1691 7 is_stmt 1 view .LVU570 +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1805 .loc 1 1691 40 is_stmt 0 view .LVU571 + 1806 0050 0022 movs r2, #0 + 1807 0052 1A65 str r2, [r3, #80] +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1808 .loc 1 1693 7 is_stmt 1 view .LVU572 +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1809 .loc 1 1693 11 is_stmt 0 view .LVU573 + 1810 0054 A06F ldr r0, [r4, #120] + 1811 0056 FFF7FEFF bl HAL_DMA_Abort + 1812 .LVL106: +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1813 .loc 1 1693 10 view .LVU574 + 1814 005a 18BB cbnz r0, .L137 + 1815 .L133: +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 1816 .loc 1 1707 3 is_stmt 1 view .LVU575 +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 1817 .loc 1 1707 22 is_stmt 0 view .LVU576 + 1818 005c 0023 movs r3, #0 + 1819 005e A4F85630 strh r3, [r4, #86] @ movhi +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1820 .loc 1 1708 3 is_stmt 1 view .LVU577 +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1821 .loc 1 1708 22 is_stmt 0 view .LVU578 + 1822 0062 A4F85E30 strh r3, [r4, #94] @ movhi +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1823 .loc 1 1711 3 is_stmt 1 view .LVU579 + 1824 0066 2368 ldr r3, [r4] + 1825 0068 0F22 movs r2, #15 + 1826 006a 1A62 str r2, [r3, #32] +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1827 .loc 1 1714 3 view .LVU580 +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1828 .loc 1 1714 12 is_stmt 0 view .LVU581 + 1829 006c 636E ldr r3, [r4, #100] +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1830 .loc 1 1714 6 view .LVU582 + 1831 006e B3F1005F cmp r3, #536870912 + 1832 0072 21D0 beq .L138 + 1833 .L134: +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1834 .loc 1 1720 3 is_stmt 1 view .LVU583 + 1835 0074 2268 ldr r2, [r4] + 1836 0076 9369 ldr r3, [r2, #24] + 1837 0078 43F00803 orr r3, r3, #8 + 1838 007c 9361 str r3, [r2, #24] + ARM GAS /tmp/ccizsdzp.s page 109 + + +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 1839 .loc 1 1723 3 view .LVU584 +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 1840 .loc 1 1723 18 is_stmt 0 view .LVU585 + 1841 007e 2023 movs r3, #32 + 1842 0080 C4F88030 str r3, [r4, #128] +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1843 .loc 1 1724 3 is_stmt 1 view .LVU586 +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1844 .loc 1 1724 18 is_stmt 0 view .LVU587 + 1845 0084 C4F88430 str r3, [r4, #132] +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1846 .loc 1 1726 3 is_stmt 1 view .LVU588 +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1847 .loc 1 1726 20 is_stmt 0 view .LVU589 + 1848 0088 0020 movs r0, #0 + 1849 008a C4F88800 str r0, [r4, #136] +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1850 .loc 1 1728 3 is_stmt 1 view .LVU590 + 1851 .L132: +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1852 .loc 1 1729 1 is_stmt 0 view .LVU591 + 1853 008e 10BD pop {r4, pc} + 1854 .LVL107: + 1855 .L136: +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1856 .loc 1 1670 9 is_stmt 1 view .LVU592 +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1857 .loc 1 1670 13 is_stmt 0 view .LVU593 + 1858 0090 606F ldr r0, [r4, #116] + 1859 0092 FFF7FEFF bl HAL_DMA_GetError + 1860 .LVL108: +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1861 .loc 1 1670 12 view .LVU594 + 1862 0096 2028 cmp r0, #32 + 1863 0098 CFD1 bne .L131 +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1864 .loc 1 1673 11 is_stmt 1 view .LVU595 +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1865 .loc 1 1673 28 is_stmt 0 view .LVU596 + 1866 009a 1023 movs r3, #16 + 1867 009c C4F88830 str r3, [r4, #136] +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1868 .loc 1 1675 11 is_stmt 1 view .LVU597 +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1869 .loc 1 1675 18 is_stmt 0 view .LVU598 + 1870 00a0 0320 movs r0, #3 + 1871 00a2 F4E7 b .L132 + 1872 .L137: +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1873 .loc 1 1695 9 is_stmt 1 view .LVU599 +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1874 .loc 1 1695 13 is_stmt 0 view .LVU600 + 1875 00a4 A06F ldr r0, [r4, #120] + 1876 00a6 FFF7FEFF bl HAL_DMA_GetError + 1877 .LVL109: +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 110 + + + 1878 .loc 1 1695 12 view .LVU601 + 1879 00aa 2028 cmp r0, #32 + 1880 00ac D6D1 bne .L133 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1881 .loc 1 1698 11 is_stmt 1 view .LVU602 +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1882 .loc 1 1698 28 is_stmt 0 view .LVU603 + 1883 00ae 1023 movs r3, #16 + 1884 00b0 C4F88830 str r3, [r4, #136] +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1885 .loc 1 1700 11 is_stmt 1 view .LVU604 +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1886 .loc 1 1700 18 is_stmt 0 view .LVU605 + 1887 00b4 0320 movs r0, #3 + 1888 00b6 EAE7 b .L132 + 1889 .L138: +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1890 .loc 1 1716 5 is_stmt 1 view .LVU606 + 1891 00b8 2268 ldr r2, [r4] + 1892 00ba 9369 ldr r3, [r2, #24] + 1893 00bc 43F01003 orr r3, r3, #16 + 1894 00c0 9361 str r3, [r2, #24] + 1895 00c2 D7E7 b .L134 + 1896 .L140: + 1897 .align 2 + 1898 .L139: + 1899 00c4 FEFF7FEF .word -276824066 + 1900 .cfi_endproc + 1901 .LFE157: + 1903 .section .text.HAL_UART_AbortTransmit,"ax",%progbits + 1904 .align 1 + 1905 .global HAL_UART_AbortTransmit + 1906 .syntax unified + 1907 .thumb + 1908 .thumb_func + 1909 .fpu fpv5-d16 + 1911 HAL_UART_AbortTransmit: + 1912 .LVL110: + 1913 .LFB158: +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TCIE, TXEIE and TXFTIE interrupts */ + 1914 .loc 1 1744 1 view -0 + 1915 .cfi_startproc + 1916 @ args = 0, pretend = 0, frame = 0 + 1917 @ frame_needed = 0, uses_anonymous_args = 0 +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable TCIE, TXEIE and TXFTIE interrupts */ + 1918 .loc 1 1744 1 is_stmt 0 view .LVU608 + 1919 0000 10B5 push {r4, lr} + 1920 .LCFI13: + 1921 .cfi_def_cfa_offset 8 + 1922 .cfi_offset 4, -8 + 1923 .cfi_offset 14, -4 + 1924 0002 0446 mov r4, r0 +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + 1925 .loc 1 1746 3 is_stmt 1 view .LVU609 + 1926 0004 0268 ldr r2, [r0] + 1927 0006 1368 ldr r3, [r2] + 1928 0008 23F0C003 bic r3, r3, #192 + ARM GAS /tmp/ccizsdzp.s page 111 + + + 1929 000c 1360 str r3, [r2] +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1930 .loc 1 1747 3 view .LVU610 + 1931 000e 0268 ldr r2, [r0] + 1932 0010 9368 ldr r3, [r2, #8] + 1933 0012 23F40003 bic r3, r3, #8388608 + 1934 0016 9360 str r3, [r2, #8] +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1935 .loc 1 1750 3 view .LVU611 +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1936 .loc 1 1750 7 is_stmt 0 view .LVU612 + 1937 0018 0368 ldr r3, [r0] + 1938 001a 9A68 ldr r2, [r3, #8] +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1939 .loc 1 1750 6 view .LVU613 + 1940 001c 12F0800F tst r2, #128 + 1941 0020 0BD0 beq .L142 +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1942 .loc 1 1752 5 is_stmt 1 view .LVU614 + 1943 0022 9A68 ldr r2, [r3, #8] + 1944 0024 22F08002 bic r2, r2, #128 + 1945 0028 9A60 str r2, [r3, #8] +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1946 .loc 1 1755 5 view .LVU615 +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1947 .loc 1 1755 14 is_stmt 0 view .LVU616 + 1948 002a 436F ldr r3, [r0, #116] +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1949 .loc 1 1755 8 view .LVU617 + 1950 002c 2BB1 cbz r3, .L142 +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1951 .loc 1 1759 7 is_stmt 1 view .LVU618 +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1952 .loc 1 1759 40 is_stmt 0 view .LVU619 + 1953 002e 0022 movs r2, #0 + 1954 0030 1A65 str r2, [r3, #80] +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1955 .loc 1 1761 7 is_stmt 1 view .LVU620 +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1956 .loc 1 1761 11 is_stmt 0 view .LVU621 + 1957 0032 406F ldr r0, [r0, #116] + 1958 .LVL111: +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1959 .loc 1 1761 11 view .LVU622 + 1960 0034 FFF7FEFF bl HAL_DMA_Abort + 1961 .LVL112: +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1962 .loc 1 1761 10 view .LVU623 + 1963 0038 58B9 cbnz r0, .L146 + 1964 .L142: +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1965 .loc 1 1775 3 is_stmt 1 view .LVU624 +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1966 .loc 1 1775 22 is_stmt 0 view .LVU625 + 1967 003a 0023 movs r3, #0 + 1968 003c A4F85630 strh r3, [r4, #86] @ movhi +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 112 + + + 1969 .loc 1 1778 3 is_stmt 1 view .LVU626 +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1970 .loc 1 1778 12 is_stmt 0 view .LVU627 + 1971 0040 636E ldr r3, [r4, #100] +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1972 .loc 1 1778 6 view .LVU628 + 1973 0042 B3F1005F cmp r3, #536870912 + 1974 0046 0ED0 beq .L147 + 1975 .L144: +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1976 .loc 1 1784 3 is_stmt 1 view .LVU629 +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1977 .loc 1 1784 17 is_stmt 0 view .LVU630 + 1978 0048 2023 movs r3, #32 + 1979 004a C4F88030 str r3, [r4, #128] +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1980 .loc 1 1786 3 is_stmt 1 view .LVU631 +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 1981 .loc 1 1786 10 is_stmt 0 view .LVU632 + 1982 004e 0020 movs r0, #0 + 1983 .L143: +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1984 .loc 1 1787 1 view .LVU633 + 1985 0050 10BD pop {r4, pc} + 1986 .LVL113: + 1987 .L146: +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1988 .loc 1 1763 9 is_stmt 1 view .LVU634 +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1989 .loc 1 1763 13 is_stmt 0 view .LVU635 + 1990 0052 606F ldr r0, [r4, #116] + 1991 0054 FFF7FEFF bl HAL_DMA_GetError + 1992 .LVL114: +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 1993 .loc 1 1763 12 view .LVU636 + 1994 0058 2028 cmp r0, #32 + 1995 005a EED1 bne .L142 +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1996 .loc 1 1766 11 is_stmt 1 view .LVU637 +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 1997 .loc 1 1766 28 is_stmt 0 view .LVU638 + 1998 005c 1023 movs r3, #16 + 1999 005e C4F88830 str r3, [r4, #136] +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2000 .loc 1 1768 11 is_stmt 1 view .LVU639 +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2001 .loc 1 1768 18 is_stmt 0 view .LVU640 + 2002 0062 0320 movs r0, #3 + 2003 0064 F4E7 b .L143 + 2004 .L147: +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2005 .loc 1 1780 5 is_stmt 1 view .LVU641 + 2006 0066 2268 ldr r2, [r4] + 2007 0068 9369 ldr r3, [r2, #24] + 2008 006a 43F01003 orr r3, r3, #16 + 2009 006e 9361 str r3, [r2, #24] + 2010 0070 EAE7 b .L144 + ARM GAS /tmp/ccizsdzp.s page 113 + + + 2011 .cfi_endproc + 2012 .LFE158: + 2014 .section .text.HAL_UART_AbortReceive,"ax",%progbits + 2015 .align 1 + 2016 .global HAL_UART_AbortReceive + 2017 .syntax unified + 2018 .thumb + 2019 .thumb_func + 2020 .fpu fpv5-d16 + 2022 HAL_UART_AbortReceive: + 2023 .LVL115: + 2024 .LFB159: +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + 2025 .loc 1 1802 1 view -0 + 2026 .cfi_startproc + 2027 @ args = 0, pretend = 0, frame = 0 + 2028 @ frame_needed = 0, uses_anonymous_args = 0 +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + 2029 .loc 1 1802 1 is_stmt 0 view .LVU643 + 2030 0000 10B5 push {r4, lr} + 2031 .LCFI14: + 2032 .cfi_def_cfa_offset 8 + 2033 .cfi_offset 4, -8 + 2034 .cfi_offset 14, -4 + 2035 0002 0446 mov r4, r0 +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + 2036 .loc 1 1804 3 is_stmt 1 view .LVU644 + 2037 0004 0268 ldr r2, [r0] + 2038 0006 1368 ldr r3, [r2] + 2039 0008 23F49073 bic r3, r3, #288 + 2040 000c 1360 str r3, [r2] +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2041 .loc 1 1805 3 view .LVU645 + 2042 000e 0268 ldr r2, [r0] + 2043 0010 9168 ldr r1, [r2, #8] + 2044 0012 164B ldr r3, .L153 + 2045 0014 0B40 ands r3, r3, r1 + 2046 0016 9360 str r3, [r2, #8] +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2047 .loc 1 1808 3 view .LVU646 +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2048 .loc 1 1808 7 is_stmt 0 view .LVU647 + 2049 0018 0368 ldr r3, [r0] + 2050 001a 9A68 ldr r2, [r3, #8] +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2051 .loc 1 1808 6 view .LVU648 + 2052 001c 12F0400F tst r2, #64 + 2053 0020 0BD0 beq .L149 +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2054 .loc 1 1810 5 is_stmt 1 view .LVU649 + 2055 0022 9A68 ldr r2, [r3, #8] + 2056 0024 22F04002 bic r2, r2, #64 + 2057 0028 9A60 str r2, [r3, #8] +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2058 .loc 1 1813 5 view .LVU650 +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2059 .loc 1 1813 14 is_stmt 0 view .LVU651 + ARM GAS /tmp/ccizsdzp.s page 114 + + + 2060 002a 836F ldr r3, [r0, #120] +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2061 .loc 1 1813 8 view .LVU652 + 2062 002c 2BB1 cbz r3, .L149 +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2063 .loc 1 1817 7 is_stmt 1 view .LVU653 +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2064 .loc 1 1817 40 is_stmt 0 view .LVU654 + 2065 002e 0022 movs r2, #0 + 2066 0030 1A65 str r2, [r3, #80] +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2067 .loc 1 1819 7 is_stmt 1 view .LVU655 +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2068 .loc 1 1819 11 is_stmt 0 view .LVU656 + 2069 0032 806F ldr r0, [r0, #120] + 2070 .LVL116: +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2071 .loc 1 1819 11 view .LVU657 + 2072 0034 FFF7FEFF bl HAL_DMA_Abort + 2073 .LVL117: +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2074 .loc 1 1819 10 view .LVU658 + 2075 0038 70B9 cbnz r0, .L152 + 2076 .L149: +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2077 .loc 1 1833 3 is_stmt 1 view .LVU659 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2078 .loc 1 1833 22 is_stmt 0 view .LVU660 + 2079 003a 0020 movs r0, #0 + 2080 003c A4F85E00 strh r0, [r4, #94] @ movhi +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2081 .loc 1 1836 3 is_stmt 1 view .LVU661 + 2082 0040 2368 ldr r3, [r4] + 2083 0042 0F22 movs r2, #15 + 2084 0044 1A62 str r2, [r3, #32] +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2085 .loc 1 1839 3 view .LVU662 + 2086 0046 2268 ldr r2, [r4] + 2087 0048 9369 ldr r3, [r2, #24] + 2088 004a 43F00803 orr r3, r3, #8 + 2089 004e 9361 str r3, [r2, #24] +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2090 .loc 1 1842 3 view .LVU663 +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2091 .loc 1 1842 18 is_stmt 0 view .LVU664 + 2092 0050 2023 movs r3, #32 + 2093 0052 C4F88430 str r3, [r4, #132] +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2094 .loc 1 1844 3 is_stmt 1 view .LVU665 + 2095 .L150: +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2096 .loc 1 1845 1 is_stmt 0 view .LVU666 + 2097 0056 10BD pop {r4, pc} + 2098 .LVL118: + 2099 .L152: +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2100 .loc 1 1821 9 is_stmt 1 view .LVU667 + ARM GAS /tmp/ccizsdzp.s page 115 + + +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2101 .loc 1 1821 13 is_stmt 0 view .LVU668 + 2102 0058 A06F ldr r0, [r4, #120] + 2103 005a FFF7FEFF bl HAL_DMA_GetError + 2104 .LVL119: +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2105 .loc 1 1821 12 view .LVU669 + 2106 005e 2028 cmp r0, #32 + 2107 0060 EBD1 bne .L149 +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2108 .loc 1 1824 11 is_stmt 1 view .LVU670 +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2109 .loc 1 1824 28 is_stmt 0 view .LVU671 + 2110 0062 1023 movs r3, #16 + 2111 0064 C4F88830 str r3, [r4, #136] +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2112 .loc 1 1826 11 is_stmt 1 view .LVU672 +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2113 .loc 1 1826 18 is_stmt 0 view .LVU673 + 2114 0068 0320 movs r0, #3 + 2115 006a F4E7 b .L150 + 2116 .L154: + 2117 .align 2 + 2118 .L153: + 2119 006c FEFFFFEF .word -268435458 + 2120 .cfi_endproc + 2121 .LFE159: + 2123 .section .text.HAL_UART_TxCpltCallback,"ax",%progbits + 2124 .align 1 + 2125 .weak HAL_UART_TxCpltCallback + 2126 .syntax unified + 2127 .thumb + 2128 .thumb_func + 2129 .fpu fpv5-d16 + 2131 HAL_UART_TxCpltCallback: + 2132 .LVL120: + 2133 .LFB164: +2412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2134 .loc 1 2412 1 is_stmt 1 view -0 + 2135 .cfi_startproc + 2136 @ args = 0, pretend = 0, frame = 0 + 2137 @ frame_needed = 0, uses_anonymous_args = 0 + 2138 @ link register save eliminated. +2414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2139 .loc 1 2414 3 view .LVU675 +2419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2140 .loc 1 2419 1 is_stmt 0 view .LVU676 + 2141 0000 7047 bx lr + 2142 .cfi_endproc + 2143 .LFE164: + 2145 .section .text.UART_DMATransmitCplt,"ax",%progbits + 2146 .align 1 + 2147 .syntax unified + 2148 .thumb + 2149 .thumb_func + 2150 .fpu fpv5-d16 + 2152 UART_DMATransmitCplt: + ARM GAS /tmp/ccizsdzp.s page 116 + + + 2153 .LVL121: + 2154 .LFB189: +3336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2155 .loc 1 3336 1 is_stmt 1 view -0 + 2156 .cfi_startproc + 2157 @ args = 0, pretend = 0, frame = 0 + 2158 @ frame_needed = 0, uses_anonymous_args = 0 +3336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2159 .loc 1 3336 1 is_stmt 0 view .LVU678 + 2160 0000 08B5 push {r3, lr} + 2161 .LCFI15: + 2162 .cfi_def_cfa_offset 8 + 2163 .cfi_offset 3, -8 + 2164 .cfi_offset 14, -4 +3337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2165 .loc 1 3337 3 is_stmt 1 view .LVU679 +3337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2166 .loc 1 3337 23 is_stmt 0 view .LVU680 + 2167 0002 836B ldr r3, [r0, #56] + 2168 .LVL122: +3340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2169 .loc 1 3340 3 is_stmt 1 view .LVU681 +3340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2170 .loc 1 3340 17 is_stmt 0 view .LVU682 + 2171 0004 C269 ldr r2, [r0, #28] +3340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2172 .loc 1 3340 6 view .LVU683 + 2173 0006 B2F5807F cmp r2, #256 + 2174 000a 0DD0 beq .L157 +3342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2175 .loc 1 3342 5 is_stmt 1 view .LVU684 +3342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2176 .loc 1 3342 24 is_stmt 0 view .LVU685 + 2177 000c 0022 movs r2, #0 + 2178 000e A3F85620 strh r2, [r3, #86] @ movhi +3346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2179 .loc 1 3346 5 is_stmt 1 view .LVU686 + 2180 0012 1968 ldr r1, [r3] + 2181 0014 8A68 ldr r2, [r1, #8] + 2182 0016 22F08002 bic r2, r2, #128 + 2183 001a 8A60 str r2, [r1, #8] +3349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2184 .loc 1 3349 5 view .LVU687 + 2185 001c 1A68 ldr r2, [r3] + 2186 001e 1368 ldr r3, [r2] + 2187 .LVL123: +3349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2188 .loc 1 3349 5 is_stmt 0 view .LVU688 + 2189 0020 43F04003 orr r3, r3, #64 + 2190 0024 1360 str r3, [r2] + 2191 .LVL124: + 2192 .L156: +3362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2193 .loc 1 3362 1 view .LVU689 + 2194 0026 08BD pop {r3, pc} + 2195 .LVL125: + 2196 .L157: + ARM GAS /tmp/ccizsdzp.s page 117 + + +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2197 .loc 1 3359 5 is_stmt 1 view .LVU690 + 2198 0028 1846 mov r0, r3 + 2199 .LVL126: +3359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2200 .loc 1 3359 5 is_stmt 0 view .LVU691 + 2201 002a FFF7FEFF bl HAL_UART_TxCpltCallback + 2202 .LVL127: +3362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2203 .loc 1 3362 1 view .LVU692 + 2204 002e FAE7 b .L156 + 2205 .cfi_endproc + 2206 .LFE189: + 2208 .section .text.UART_EndTransmit_IT,"ax",%progbits + 2209 .align 1 + 2210 .syntax unified + 2211 .thumb + 2212 .thumb_func + 2213 .fpu fpv5-d16 + 2215 UART_EndTransmit_IT: + 2216 .LVL128: + 2217 .LFB203: +3808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief Wrap up transmission in non-blocking mode. +3811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart pointer to a UART_HandleTypeDef structure that contains +3812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * the configuration information for the specified UART module. +3813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +3816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2218 .loc 1 3816 1 is_stmt 1 view -0 + 2219 .cfi_startproc + 2220 @ args = 0, pretend = 0, frame = 0 + 2221 @ frame_needed = 0, uses_anonymous_args = 0 + 2222 .loc 1 3816 1 is_stmt 0 view .LVU694 + 2223 0000 08B5 push {r3, lr} + 2224 .LCFI16: + 2225 .cfi_def_cfa_offset 8 + 2226 .cfi_offset 3, -8 + 2227 .cfi_offset 14, -4 +3817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Transmit Complete Interrupt */ +3818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 2228 .loc 1 3818 3 is_stmt 1 view .LVU695 + 2229 0002 0168 ldr r1, [r0] + 2230 0004 0A68 ldr r2, [r1] + 2231 0006 22F04002 bic r2, r2, #64 + 2232 000a 0A60 str r2, [r1] +3819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Tx process is ended, restore huart->gState to Ready */ +3821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; + 2233 .loc 1 3821 3 view .LVU696 + 2234 .loc 1 3821 17 is_stmt 0 view .LVU697 + 2235 000c 2022 movs r2, #32 + 2236 000e C0F88020 str r2, [r0, #128] +3822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Cleat TxISR function pointer */ + ARM GAS /tmp/ccizsdzp.s page 118 + + +3824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + 2237 .loc 1 3824 3 is_stmt 1 view .LVU698 + 2238 .loc 1 3824 16 is_stmt 0 view .LVU699 + 2239 0012 0022 movs r2, #0 + 2240 0014 0267 str r2, [r0, #112] +3825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Tx complete callback*/ +3828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxCpltCallback(huart); +3829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Tx complete callback*/ +3831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_TxCpltCallback(huart); + 2241 .loc 1 3831 3 is_stmt 1 view .LVU700 + 2242 0016 FFF7FEFF bl HAL_UART_TxCpltCallback + 2243 .LVL129: +3832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2244 .loc 1 3833 1 is_stmt 0 view .LVU701 + 2245 001a 08BD pop {r3, pc} + 2246 .cfi_endproc + 2247 .LFE203: + 2249 .section .text.HAL_UART_TxHalfCpltCallback,"ax",%progbits + 2250 .align 1 + 2251 .weak HAL_UART_TxHalfCpltCallback + 2252 .syntax unified + 2253 .thumb + 2254 .thumb_func + 2255 .fpu fpv5-d16 + 2257 HAL_UART_TxHalfCpltCallback: + 2258 .LVL130: + 2259 .LFB165: +2427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2260 .loc 1 2427 1 is_stmt 1 view -0 + 2261 .cfi_startproc + 2262 @ args = 0, pretend = 0, frame = 0 + 2263 @ frame_needed = 0, uses_anonymous_args = 0 + 2264 @ link register save eliminated. +2429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2265 .loc 1 2429 3 view .LVU703 +2434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2266 .loc 1 2434 1 is_stmt 0 view .LVU704 + 2267 0000 7047 bx lr + 2268 .cfi_endproc + 2269 .LFE165: + 2271 .section .text.UART_DMATxHalfCplt,"ax",%progbits + 2272 .align 1 + 2273 .syntax unified + 2274 .thumb + 2275 .thumb_func + 2276 .fpu fpv5-d16 + 2278 UART_DMATxHalfCplt: + 2279 .LVL131: + 2280 .LFB190: +3370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2281 .loc 1 3370 1 is_stmt 1 view -0 + 2282 .cfi_startproc + 2283 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccizsdzp.s page 119 + + + 2284 @ frame_needed = 0, uses_anonymous_args = 0 +3370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2285 .loc 1 3370 1 is_stmt 0 view .LVU706 + 2286 0000 08B5 push {r3, lr} + 2287 .LCFI17: + 2288 .cfi_def_cfa_offset 8 + 2289 .cfi_offset 3, -8 + 2290 .cfi_offset 14, -4 +3371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2291 .loc 1 3371 3 is_stmt 1 view .LVU707 + 2292 .LVL132: +3378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2293 .loc 1 3378 3 view .LVU708 + 2294 0002 806B ldr r0, [r0, #56] + 2295 .LVL133: +3378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2296 .loc 1 3378 3 is_stmt 0 view .LVU709 + 2297 0004 FFF7FEFF bl HAL_UART_TxHalfCpltCallback + 2298 .LVL134: +3380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2299 .loc 1 3380 1 view .LVU710 + 2300 0008 08BD pop {r3, pc} + 2301 .cfi_endproc + 2302 .LFE190: + 2304 .section .text.HAL_UART_RxCpltCallback,"ax",%progbits + 2305 .align 1 + 2306 .weak HAL_UART_RxCpltCallback + 2307 .syntax unified + 2308 .thumb + 2309 .thumb_func + 2310 .fpu fpv5-d16 + 2312 HAL_UART_RxCpltCallback: + 2313 .LVL135: + 2314 .LFB166: +2442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2315 .loc 1 2442 1 is_stmt 1 view -0 + 2316 .cfi_startproc + 2317 @ args = 0, pretend = 0, frame = 0 + 2318 @ frame_needed = 0, uses_anonymous_args = 0 + 2319 @ link register save eliminated. +2444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2320 .loc 1 2444 3 view .LVU712 +2449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2321 .loc 1 2449 1 is_stmt 0 view .LVU713 + 2322 0000 7047 bx lr + 2323 .cfi_endproc + 2324 .LFE166: + 2326 .section .text.UART_RxISR_8BIT,"ax",%progbits + 2327 .align 1 + 2328 .syntax unified + 2329 .thumb + 2330 .thumb_func + 2331 .fpu fpv5-d16 + 2333 UART_RxISR_8BIT: + 2334 .LVL136: + 2335 .LFB204: +3834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 120 + + +3835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief RX interrrupt handler for 7 or 8 bits data word length . +3837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +3841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2336 .loc 1 3841 1 is_stmt 1 view -0 + 2337 .cfi_startproc + 2338 @ args = 0, pretend = 0, frame = 0 + 2339 @ frame_needed = 0, uses_anonymous_args = 0 + 2340 .loc 1 3841 1 is_stmt 0 view .LVU715 + 2341 0000 08B5 push {r3, lr} + 2342 .LCFI18: + 2343 .cfi_def_cfa_offset 8 + 2344 .cfi_offset 3, -8 + 2345 .cfi_offset 14, -4 +3842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 2346 .loc 1 3842 3 is_stmt 1 view .LVU716 + 2347 .loc 1 3842 12 is_stmt 0 view .LVU717 + 2348 0002 B0F86030 ldrh r3, [r0, #96] + 2349 .LVL137: +3843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhdata; + 2350 .loc 1 3843 3 is_stmt 1 view .LVU718 +3844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +3846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 2351 .loc 1 3846 3 view .LVU719 + 2352 .loc 1 3846 12 is_stmt 0 view .LVU720 + 2353 0006 D0F88420 ldr r2, [r0, #132] + 2354 .loc 1 3846 6 view .LVU721 + 2355 000a 222A cmp r2, #34 + 2356 000c 05D0 beq .L170 +3847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); +3850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; +3852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxXferCount == 0U) +3854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXNE interrupts */ +3856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +3857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +3859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +3862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RxISR function pointer */ +3865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +3866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +3869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback(huart); +3870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else + ARM GAS /tmp/ccizsdzp.s page 121 + + +3871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +3872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +3873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +3879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 2357 .loc 1 3879 5 is_stmt 1 view .LVU722 + 2358 000e 0268 ldr r2, [r0] + 2359 0010 9369 ldr r3, [r2, #24] + 2360 .LVL138: + 2361 .loc 1 3879 5 is_stmt 0 view .LVU723 + 2362 0012 43F00803 orr r3, r3, #8 + 2363 0016 9361 str r3, [r2, #24] + 2364 .LVL139: + 2365 .L166: +3880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2366 .loc 1 3881 1 view .LVU724 + 2367 0018 08BD pop {r3, pc} + 2368 .LVL140: + 2369 .L170: +3848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 2370 .loc 1 3848 5 is_stmt 1 view .LVU725 +3848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 2371 .loc 1 3848 25 is_stmt 0 view .LVU726 + 2372 001a 0268 ldr r2, [r0] + 2373 001c 516A ldr r1, [r2, #36] + 2374 .LVL141: +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2375 .loc 1 3849 5 is_stmt 1 view .LVU727 +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2376 .loc 1 3849 45 is_stmt 0 view .LVU728 + 2377 001e DBB2 uxtb r3, r3 + 2378 .LVL142: +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2379 .loc 1 3849 11 view .LVU729 + 2380 0020 826D ldr r2, [r0, #88] +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2381 .loc 1 3849 26 view .LVU730 + 2382 0022 0B40 ands r3, r3, r1 +3849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2383 .loc 1 3849 24 view .LVU731 + 2384 0024 1370 strb r3, [r2] + 2385 .LVL143: +3850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2386 .loc 1 3850 5 is_stmt 1 view .LVU732 +3850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2387 .loc 1 3850 10 is_stmt 0 view .LVU733 + 2388 0026 836D ldr r3, [r0, #88] +3850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2389 .loc 1 3850 22 view .LVU734 + 2390 0028 0133 adds r3, r3, #1 + 2391 002a 8365 str r3, [r0, #88] +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 122 + + + 2392 .loc 1 3851 5 is_stmt 1 view .LVU735 +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2393 .loc 1 3851 10 is_stmt 0 view .LVU736 + 2394 002c B0F85E30 ldrh r3, [r0, #94] + 2395 0030 9BB2 uxth r3, r3 +3851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2396 .loc 1 3851 23 view .LVU737 + 2397 0032 013B subs r3, r3, #1 + 2398 0034 9BB2 uxth r3, r3 + 2399 0036 A0F85E30 strh r3, [r0, #94] @ movhi +3853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2400 .loc 1 3853 5 is_stmt 1 view .LVU738 +3853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2401 .loc 1 3853 14 is_stmt 0 view .LVU739 + 2402 003a B0F85E30 ldrh r3, [r0, #94] + 2403 003e 9BB2 uxth r3, r3 +3853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2404 .loc 1 3853 8 view .LVU740 + 2405 0040 002B cmp r3, #0 + 2406 0042 E9D1 bne .L166 +3856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2407 .loc 1 3856 7 is_stmt 1 view .LVU741 + 2408 0044 0268 ldr r2, [r0] + 2409 0046 1368 ldr r3, [r2] + 2410 0048 23F49073 bic r3, r3, #288 + 2411 004c 1360 str r3, [r2] +3859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2412 .loc 1 3859 7 view .LVU742 + 2413 004e 0268 ldr r2, [r0] + 2414 0050 9368 ldr r3, [r2, #8] + 2415 0052 23F00103 bic r3, r3, #1 + 2416 0056 9360 str r3, [r2, #8] +3862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2417 .loc 1 3862 7 view .LVU743 +3862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2418 .loc 1 3862 22 is_stmt 0 view .LVU744 + 2419 0058 2023 movs r3, #32 + 2420 005a C0F88430 str r3, [r0, #132] +3865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2421 .loc 1 3865 7 is_stmt 1 view .LVU745 +3865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2422 .loc 1 3865 20 is_stmt 0 view .LVU746 + 2423 005e 0023 movs r3, #0 + 2424 0060 C366 str r3, [r0, #108] +3872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2425 .loc 1 3872 7 is_stmt 1 view .LVU747 + 2426 0062 FFF7FEFF bl HAL_UART_RxCpltCallback + 2427 .LVL144: +3872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2428 .loc 1 3872 7 is_stmt 0 view .LVU748 + 2429 0066 D7E7 b .L166 + 2430 .cfi_endproc + 2431 .LFE204: + 2433 .section .text.UART_RxISR_16BIT,"ax",%progbits + 2434 .align 1 + 2435 .syntax unified + 2436 .thumb + ARM GAS /tmp/ccizsdzp.s page 123 + + + 2437 .thumb_func + 2438 .fpu fpv5-d16 + 2440 UART_RxISR_16BIT: + 2441 .LVL145: + 2442 .LFB205: +3882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief RX interrrupt handler for 9 bits data word length . +3885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +3886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Receive_IT() +3887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +3891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2443 .loc 1 3891 1 is_stmt 1 view -0 + 2444 .cfi_startproc + 2445 @ args = 0, pretend = 0, frame = 0 + 2446 @ frame_needed = 0, uses_anonymous_args = 0 + 2447 .loc 1 3891 1 is_stmt 0 view .LVU750 + 2448 0000 08B5 push {r3, lr} + 2449 .LCFI19: + 2450 .cfi_def_cfa_offset 8 + 2451 .cfi_offset 3, -8 + 2452 .cfi_offset 14, -4 +3892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *tmp; + 2453 .loc 1 3892 3 is_stmt 1 view .LVU751 +3893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 2454 .loc 1 3893 3 view .LVU752 + 2455 .loc 1 3893 12 is_stmt 0 view .LVU753 + 2456 0002 B0F86020 ldrh r2, [r0, #96] + 2457 .LVL146: +3894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhdata; + 2458 .loc 1 3894 3 is_stmt 1 view .LVU754 +3895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +3897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 2459 .loc 1 3897 3 view .LVU755 + 2460 .loc 1 3897 12 is_stmt 0 view .LVU756 + 2461 0006 D0F88430 ldr r3, [r0, #132] + 2462 .loc 1 3897 6 view .LVU757 + 2463 000a 222B cmp r3, #34 + 2464 000c 05D0 beq .L175 +3898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); +3900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; +3901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); +3902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; +3904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxXferCount == 0U) +3906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +3908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); +3909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +3911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ARM GAS /tmp/ccizsdzp.s page 124 + + +3912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +3914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RxISR function pointer */ +3917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +3918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +3921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback(huart); +3922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +3924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +3925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +3929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +3931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 2465 .loc 1 3931 5 is_stmt 1 view .LVU758 + 2466 000e 0268 ldr r2, [r0] + 2467 .LVL147: + 2468 .loc 1 3931 5 is_stmt 0 view .LVU759 + 2469 0010 9369 ldr r3, [r2, #24] + 2470 0012 43F00803 orr r3, r3, #8 + 2471 0016 9361 str r3, [r2, #24] + 2472 .LVL148: + 2473 .L171: +3932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2474 .loc 1 3933 1 view .LVU760 + 2475 0018 08BD pop {r3, pc} + 2476 .LVL149: + 2477 .L175: +3899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; + 2478 .loc 1 3899 5 is_stmt 1 view .LVU761 +3899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; + 2479 .loc 1 3899 25 is_stmt 0 view .LVU762 + 2480 001a 0368 ldr r3, [r0] + 2481 001c 5B6A ldr r3, [r3, #36] + 2482 .LVL150: +3900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); + 2483 .loc 1 3900 5 is_stmt 1 view .LVU763 +3900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); + 2484 .loc 1 3900 9 is_stmt 0 view .LVU764 + 2485 001e 816D ldr r1, [r0, #88] + 2486 .LVL151: +3901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 2487 .loc 1 3901 5 is_stmt 1 view .LVU765 +3901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 2488 .loc 1 3901 12 is_stmt 0 view .LVU766 + 2489 0020 1340 ands r3, r3, r2 + 2490 .LVL152: +3901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 2491 .loc 1 3901 10 view .LVU767 + 2492 0022 0B80 strh r3, [r1] @ movhi + ARM GAS /tmp/ccizsdzp.s page 125 + + +3902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2493 .loc 1 3902 5 is_stmt 1 view .LVU768 +3902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2494 .loc 1 3902 23 is_stmt 0 view .LVU769 + 2495 0024 836D ldr r3, [r0, #88] + 2496 0026 0233 adds r3, r3, #2 + 2497 0028 8365 str r3, [r0, #88] +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2498 .loc 1 3903 5 is_stmt 1 view .LVU770 +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2499 .loc 1 3903 10 is_stmt 0 view .LVU771 + 2500 002a B0F85E30 ldrh r3, [r0, #94] + 2501 002e 9BB2 uxth r3, r3 +3903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2502 .loc 1 3903 23 view .LVU772 + 2503 0030 013B subs r3, r3, #1 + 2504 0032 9BB2 uxth r3, r3 + 2505 0034 A0F85E30 strh r3, [r0, #94] @ movhi +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2506 .loc 1 3905 5 is_stmt 1 view .LVU773 +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2507 .loc 1 3905 14 is_stmt 0 view .LVU774 + 2508 0038 B0F85E30 ldrh r3, [r0, #94] + 2509 003c 9BB2 uxth r3, r3 +3905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2510 .loc 1 3905 8 view .LVU775 + 2511 003e 002B cmp r3, #0 + 2512 0040 EAD1 bne .L171 +3908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2513 .loc 1 3908 7 is_stmt 1 view .LVU776 + 2514 0042 0268 ldr r2, [r0] + 2515 .LVL153: +3908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2516 .loc 1 3908 7 is_stmt 0 view .LVU777 + 2517 0044 1368 ldr r3, [r2] + 2518 0046 23F49073 bic r3, r3, #288 + 2519 004a 1360 str r3, [r2] +3911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2520 .loc 1 3911 7 is_stmt 1 view .LVU778 + 2521 004c 0268 ldr r2, [r0] + 2522 004e 9368 ldr r3, [r2, #8] + 2523 0050 23F00103 bic r3, r3, #1 + 2524 0054 9360 str r3, [r2, #8] +3914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2525 .loc 1 3914 7 view .LVU779 +3914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2526 .loc 1 3914 22 is_stmt 0 view .LVU780 + 2527 0056 2023 movs r3, #32 + 2528 0058 C0F88430 str r3, [r0, #132] +3917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2529 .loc 1 3917 7 is_stmt 1 view .LVU781 +3917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2530 .loc 1 3917 20 is_stmt 0 view .LVU782 + 2531 005c 0023 movs r3, #0 + 2532 005e C366 str r3, [r0, #108] +3924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2533 .loc 1 3924 7 is_stmt 1 view .LVU783 + ARM GAS /tmp/ccizsdzp.s page 126 + + + 2534 0060 FFF7FEFF bl HAL_UART_RxCpltCallback + 2535 .LVL154: +3924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2536 .loc 1 3924 7 is_stmt 0 view .LVU784 + 2537 0064 D8E7 b .L171 + 2538 .cfi_endproc + 2539 .LFE205: + 2541 .section .text.UART_RxISR_8BIT_FIFOEN,"ax",%progbits + 2542 .align 1 + 2543 .syntax unified + 2544 .thumb + 2545 .thumb_func + 2546 .fpu fpv5-d16 + 2548 UART_RxISR_8BIT_FIFOEN: + 2549 .LVL155: + 2550 .LFB206: +3934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +3936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. +3937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +3938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Receive_IT() +3939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +3940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +3941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +3943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2551 .loc 1 3943 1 is_stmt 1 view -0 + 2552 .cfi_startproc + 2553 @ args = 0, pretend = 0, frame = 0 + 2554 @ frame_needed = 0, uses_anonymous_args = 0 + 2555 .loc 1 3943 1 is_stmt 0 view .LVU786 + 2556 0000 70B5 push {r4, r5, r6, lr} + 2557 .LCFI20: + 2558 .cfi_def_cfa_offset 16 + 2559 .cfi_offset 4, -16 + 2560 .cfi_offset 5, -12 + 2561 .cfi_offset 6, -8 + 2562 .cfi_offset 14, -4 + 2563 0002 0446 mov r4, r0 +3944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 2564 .loc 1 3944 3 is_stmt 1 view .LVU787 + 2565 .loc 1 3944 13 is_stmt 0 view .LVU788 + 2566 0004 B0F86060 ldrh r6, [r0, #96] + 2567 .LVL156: +3945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhdata; + 2568 .loc 1 3945 3 is_stmt 1 view .LVU789 +3946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t nb_rx_data; + 2569 .loc 1 3946 3 view .LVU790 +3947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t rxdatacount; + 2570 .loc 1 3947 3 view .LVU791 +3948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +3950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 2571 .loc 1 3950 3 view .LVU792 + 2572 .loc 1 3950 12 is_stmt 0 view .LVU793 + 2573 0008 D0F88430 ldr r3, [r0, #132] + 2574 .loc 1 3950 6 view .LVU794 + ARM GAS /tmp/ccizsdzp.s page 127 + + + 2575 000c 222B cmp r3, #34 + 2576 000e 05D0 beq .L183 +3951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) +3953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); +3956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; +3957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; +3958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxXferCount == 0U) +3960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ +3962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +3963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO +3965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +3966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +3968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RxISR function pointer */ +3971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +3972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +3975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback(huart); +3976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +3977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +3978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +3979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* When remaining number of bytes to receive is less than the RX FIFO +3984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** threshold, next incoming frames are processed as if FIFO mode was +3985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** disabled (i.e. one interrupt per received frame). +3986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +3987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** rxdatacount = huart->RxXferCount; +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) +3989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +3990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART RXFT interrupt*/ +3991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); +3992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Update the RxISR function pointer */ +3994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = UART_RxISR_8BIT; +3995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +3996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Data Register Not Empty interrupt */ +3997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); +3998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +3999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +4001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +4002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +4003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 2577 .loc 1 4003 5 is_stmt 1 view .LVU795 + 2578 0010 0268 ldr r2, [r0] + ARM GAS /tmp/ccizsdzp.s page 128 + + + 2579 0012 9369 ldr r3, [r2, #24] + 2580 0014 43F00803 orr r3, r3, #8 + 2581 0018 9361 str r3, [r2, #24] + 2582 .LVL157: + 2583 .L176: +4004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2584 .loc 1 4005 1 is_stmt 0 view .LVU796 + 2585 001a 70BD pop {r4, r5, r6, pc} + 2586 .LVL158: + 2587 .L183: +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2588 .loc 1 3952 5 is_stmt 1 view .LVU797 +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2589 .loc 1 3952 21 is_stmt 0 view .LVU798 + 2590 001c B0F86850 ldrh r5, [r0, #104] + 2591 .LVL159: +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2592 .loc 1 3952 5 view .LVU799 + 2593 0020 01E0 b .L178 + 2594 .LVL160: + 2595 .L179: +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2596 .loc 1 3952 68 is_stmt 1 discriminator 2 view .LVU800 +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2597 .loc 1 3952 78 is_stmt 0 discriminator 2 view .LVU801 + 2598 0022 013D subs r5, r5, #1 + 2599 .LVL161: +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2600 .loc 1 3952 78 discriminator 2 view .LVU802 + 2601 0024 ADB2 uxth r5, r5 + 2602 .LVL162: + 2603 .L178: +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2604 .loc 1 3952 50 is_stmt 1 discriminator 1 view .LVU803 +3952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2605 .loc 1 3952 5 is_stmt 0 discriminator 1 view .LVU804 + 2606 0026 3DB3 cbz r5, .L184 +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 2607 .loc 1 3954 7 is_stmt 1 view .LVU805 +3954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 2608 .loc 1 3954 27 is_stmt 0 view .LVU806 + 2609 0028 2368 ldr r3, [r4] + 2610 002a 596A ldr r1, [r3, #36] + 2611 .LVL163: +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2612 .loc 1 3955 7 is_stmt 1 view .LVU807 +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2613 .loc 1 3955 47 is_stmt 0 view .LVU808 + 2614 002c F3B2 uxtb r3, r6 +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2615 .loc 1 3955 13 view .LVU809 + 2616 002e A26D ldr r2, [r4, #88] +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + 2617 .loc 1 3955 28 view .LVU810 + 2618 0030 0B40 ands r3, r3, r1 +3955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr++; + ARM GAS /tmp/ccizsdzp.s page 129 + + + 2619 .loc 1 3955 26 view .LVU811 + 2620 0032 1370 strb r3, [r2] +3956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2621 .loc 1 3956 7 is_stmt 1 view .LVU812 +3956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2622 .loc 1 3956 12 is_stmt 0 view .LVU813 + 2623 0034 A36D ldr r3, [r4, #88] +3956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2624 .loc 1 3956 24 view .LVU814 + 2625 0036 0133 adds r3, r3, #1 + 2626 0038 A365 str r3, [r4, #88] +3957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2627 .loc 1 3957 7 is_stmt 1 view .LVU815 +3957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2628 .loc 1 3957 12 is_stmt 0 view .LVU816 + 2629 003a B4F85E30 ldrh r3, [r4, #94] + 2630 003e 9BB2 uxth r3, r3 +3957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2631 .loc 1 3957 25 view .LVU817 + 2632 0040 013B subs r3, r3, #1 + 2633 0042 9BB2 uxth r3, r3 + 2634 0044 A4F85E30 strh r3, [r4, #94] @ movhi +3959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2635 .loc 1 3959 7 is_stmt 1 view .LVU818 +3959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2636 .loc 1 3959 16 is_stmt 0 view .LVU819 + 2637 0048 B4F85E30 ldrh r3, [r4, #94] + 2638 004c 9BB2 uxth r3, r3 +3959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2639 .loc 1 3959 10 view .LVU820 + 2640 004e 002B cmp r3, #0 + 2641 0050 E7D1 bne .L179 +3962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2642 .loc 1 3962 9 is_stmt 1 view .LVU821 + 2643 0052 2268 ldr r2, [r4] + 2644 0054 1368 ldr r3, [r2] + 2645 0056 23F48073 bic r3, r3, #256 + 2646 005a 1360 str r3, [r2] +3965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2647 .loc 1 3965 9 view .LVU822 + 2648 005c 2268 ldr r2, [r4] + 2649 005e 9168 ldr r1, [r2, #8] + 2650 .LVL164: +3965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2651 .loc 1 3965 9 is_stmt 0 view .LVU823 + 2652 0060 104B ldr r3, .L185 + 2653 0062 0B40 ands r3, r3, r1 + 2654 0064 9360 str r3, [r2, #8] +3968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2655 .loc 1 3968 9 is_stmt 1 view .LVU824 +3968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2656 .loc 1 3968 24 is_stmt 0 view .LVU825 + 2657 0066 2023 movs r3, #32 + 2658 0068 C4F88430 str r3, [r4, #132] +3971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2659 .loc 1 3971 9 is_stmt 1 view .LVU826 +3971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 130 + + + 2660 .loc 1 3971 22 is_stmt 0 view .LVU827 + 2661 006c 0023 movs r3, #0 + 2662 006e E366 str r3, [r4, #108] +3978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2663 .loc 1 3978 9 is_stmt 1 view .LVU828 + 2664 0070 2046 mov r0, r4 + 2665 0072 FFF7FEFF bl HAL_UART_RxCpltCallback + 2666 .LVL165: + 2667 0076 D4E7 b .L179 + 2668 .L184: +3987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 2669 .loc 1 3987 5 view .LVU829 +3987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 2670 .loc 1 3987 17 is_stmt 0 view .LVU830 + 2671 0078 B4F85E30 ldrh r3, [r4, #94] + 2672 007c 9BB2 uxth r3, r3 + 2673 .LVL166: +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2674 .loc 1 3988 5 is_stmt 1 view .LVU831 +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2675 .loc 1 3988 8 is_stmt 0 view .LVU832 + 2676 007e 002B cmp r3, #0 + 2677 0080 CBD0 beq .L176 +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2678 .loc 1 3988 52 discriminator 1 view .LVU833 + 2679 0082 B4F86820 ldrh r2, [r4, #104] +3988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2680 .loc 1 3988 29 discriminator 1 view .LVU834 + 2681 0086 9A42 cmp r2, r3 + 2682 0088 C7D9 bls .L176 +3991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2683 .loc 1 3991 7 is_stmt 1 view .LVU835 + 2684 008a 2268 ldr r2, [r4] + 2685 008c 9368 ldr r3, [r2, #8] + 2686 .LVL167: +3991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2687 .loc 1 3991 7 is_stmt 0 view .LVU836 + 2688 008e 23F08053 bic r3, r3, #268435456 + 2689 0092 9360 str r3, [r2, #8] +3994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2690 .loc 1 3994 7 is_stmt 1 view .LVU837 +3994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2691 .loc 1 3994 20 is_stmt 0 view .LVU838 + 2692 0094 044B ldr r3, .L185+4 + 2693 0096 E366 str r3, [r4, #108] +3997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2694 .loc 1 3997 7 is_stmt 1 view .LVU839 + 2695 0098 2268 ldr r2, [r4] + 2696 009a 1368 ldr r3, [r2] + 2697 009c 43F02003 orr r3, r3, #32 + 2698 00a0 1360 str r3, [r2] + 2699 00a2 BAE7 b .L176 + 2700 .L186: + 2701 .align 2 + 2702 .L185: + 2703 00a4 FEFFFFEF .word -268435458 + 2704 00a8 00000000 .word UART_RxISR_8BIT + ARM GAS /tmp/ccizsdzp.s page 131 + + + 2705 .cfi_endproc + 2706 .LFE206: + 2708 .section .text.UART_RxISR_16BIT_FIFOEN,"ax",%progbits + 2709 .align 1 + 2710 .syntax unified + 2711 .thumb + 2712 .thumb_func + 2713 .fpu fpv5-d16 + 2715 UART_RxISR_16BIT_FIFOEN: + 2716 .LVL168: + 2717 .LFB207: +4006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** +4008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. +4009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @note Function is called under interruption only, once +4010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Receive_IT() +4011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @param huart UART handle. +4012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** * @retval None +4013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +4014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +4015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2718 .loc 1 4015 1 view -0 + 2719 .cfi_startproc + 2720 @ args = 0, pretend = 0, frame = 0 + 2721 @ frame_needed = 0, uses_anonymous_args = 0 + 2722 .loc 1 4015 1 is_stmt 0 view .LVU841 + 2723 0000 70B5 push {r4, r5, r6, lr} + 2724 .LCFI21: + 2725 .cfi_def_cfa_offset 16 + 2726 .cfi_offset 4, -16 + 2727 .cfi_offset 5, -12 + 2728 .cfi_offset 6, -8 + 2729 .cfi_offset 14, -4 + 2730 0002 0446 mov r4, r0 +4016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *tmp; + 2731 .loc 1 4016 3 is_stmt 1 view .LVU842 +4017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 2732 .loc 1 4017 3 view .LVU843 + 2733 .loc 1 4017 13 is_stmt 0 view .LVU844 + 2734 0004 B0F86060 ldrh r6, [r0, #96] + 2735 .LVL169: +4018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhdata; + 2736 .loc 1 4018 3 is_stmt 1 view .LVU845 +4019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t nb_rx_data; + 2737 .loc 1 4019 3 view .LVU846 +4020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t rxdatacount; + 2738 .loc 1 4020 3 view .LVU847 +4021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +4023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 2739 .loc 1 4023 3 view .LVU848 + 2740 .loc 1 4023 12 is_stmt 0 view .LVU849 + 2741 0008 D0F88430 ldr r3, [r0, #132] + 2742 .loc 1 4023 6 view .LVU850 + 2743 000c 222B cmp r3, #34 + 2744 000e 05D0 beq .L194 +4024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 132 + + +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) +4026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +4027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); +4028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; +4031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; +4032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (huart->RxXferCount == 0U) +4034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +4035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ +4036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +4037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO +4039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); +4040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +4042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +4043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RxISR function pointer */ +4045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = NULL; +4046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +4048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +4049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxCpltCallback(huart); +4050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #else +4051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +4052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +4053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +4054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* When remaining number of bytes to receive is less than the RX FIFO +4058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** threshold, next incoming frames are processed as if FIFO mode was +4059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** disabled (i.e. one interrupt per received frame). +4060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** */ +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** rxdatacount = huart->RxXferCount; +4062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) +4063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +4064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable the UART RXFT interrupt*/ +4065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); +4066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Update the RxISR function pointer */ +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxISR = UART_RxISR_16BIT; +4069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** +4070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Enable the UART Data Register Not Empty interrupt */ +4071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); +4072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** else +4075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { +4076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +4077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 2745 .loc 1 4077 5 is_stmt 1 view .LVU851 + 2746 0010 0268 ldr r2, [r0] + 2747 0012 9369 ldr r3, [r2, #24] + 2748 0014 43F00803 orr r3, r3, #8 + ARM GAS /tmp/ccizsdzp.s page 133 + + + 2749 0018 9361 str r3, [r2, #24] + 2750 .LVL170: + 2751 .L187: +4078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } +4079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2752 .loc 1 4079 1 is_stmt 0 view .LVU852 + 2753 001a 70BD pop {r4, r5, r6, pc} + 2754 .LVL171: + 2755 .L194: +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2756 .loc 1 4025 5 is_stmt 1 view .LVU853 +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2757 .loc 1 4025 21 is_stmt 0 view .LVU854 + 2758 001c B0F86850 ldrh r5, [r0, #104] + 2759 .LVL172: +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2760 .loc 1 4025 5 view .LVU855 + 2761 0020 01E0 b .L189 + 2762 .LVL173: + 2763 .L190: +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2764 .loc 1 4025 68 is_stmt 1 discriminator 2 view .LVU856 +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2765 .loc 1 4025 78 is_stmt 0 discriminator 2 view .LVU857 + 2766 0022 013D subs r5, r5, #1 + 2767 .LVL174: +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2768 .loc 1 4025 78 discriminator 2 view .LVU858 + 2769 0024 ADB2 uxth r5, r5 + 2770 .LVL175: + 2771 .L189: +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2772 .loc 1 4025 50 is_stmt 1 discriminator 1 view .LVU859 +4025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2773 .loc 1 4025 5 is_stmt 0 discriminator 1 view .LVU860 + 2774 0026 35B3 cbz r5, .L195 +4027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; + 2775 .loc 1 4027 7 is_stmt 1 view .LVU861 +4027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; + 2776 .loc 1 4027 27 is_stmt 0 view .LVU862 + 2777 0028 2368 ldr r3, [r4] + 2778 002a 5B6A ldr r3, [r3, #36] + 2779 .LVL176: +4028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); + 2780 .loc 1 4028 7 is_stmt 1 view .LVU863 +4028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); + 2781 .loc 1 4028 11 is_stmt 0 view .LVU864 + 2782 002c A26D ldr r2, [r4, #88] + 2783 .LVL177: +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 2784 .loc 1 4029 7 is_stmt 1 view .LVU865 +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 2785 .loc 1 4029 14 is_stmt 0 view .LVU866 + 2786 002e 3340 ands r3, r3, r6 + 2787 .LVL178: +4029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 2788 .loc 1 4029 12 view .LVU867 + ARM GAS /tmp/ccizsdzp.s page 134 + + + 2789 0030 1380 strh r3, [r2] @ movhi +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2790 .loc 1 4030 7 is_stmt 1 view .LVU868 +4030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount--; + 2791 .loc 1 4030 25 is_stmt 0 view .LVU869 + 2792 0032 A36D ldr r3, [r4, #88] + 2793 0034 0233 adds r3, r3, #2 + 2794 0036 A365 str r3, [r4, #88] +4031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2795 .loc 1 4031 7 is_stmt 1 view .LVU870 +4031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2796 .loc 1 4031 12 is_stmt 0 view .LVU871 + 2797 0038 B4F85E30 ldrh r3, [r4, #94] + 2798 003c 9BB2 uxth r3, r3 +4031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2799 .loc 1 4031 25 view .LVU872 + 2800 003e 013B subs r3, r3, #1 + 2801 0040 9BB2 uxth r3, r3 + 2802 0042 A4F85E30 strh r3, [r4, #94] @ movhi +4033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2803 .loc 1 4033 7 is_stmt 1 view .LVU873 +4033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2804 .loc 1 4033 16 is_stmt 0 view .LVU874 + 2805 0046 B4F85E30 ldrh r3, [r4, #94] + 2806 004a 9BB2 uxth r3, r3 +4033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2807 .loc 1 4033 10 view .LVU875 + 2808 004c 002B cmp r3, #0 + 2809 004e E8D1 bne .L190 +4036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2810 .loc 1 4036 9 is_stmt 1 view .LVU876 + 2811 0050 2268 ldr r2, [r4] + 2812 .LVL179: +4036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2813 .loc 1 4036 9 is_stmt 0 view .LVU877 + 2814 0052 1368 ldr r3, [r2] + 2815 0054 23F48073 bic r3, r3, #256 + 2816 0058 1360 str r3, [r2] +4039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2817 .loc 1 4039 9 is_stmt 1 view .LVU878 + 2818 005a 2268 ldr r2, [r4] + 2819 005c 9168 ldr r1, [r2, #8] + 2820 005e 114B ldr r3, .L196 + 2821 0060 0B40 ands r3, r3, r1 + 2822 0062 9360 str r3, [r2, #8] +4042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2823 .loc 1 4042 9 view .LVU879 +4042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2824 .loc 1 4042 24 is_stmt 0 view .LVU880 + 2825 0064 2023 movs r3, #32 + 2826 0066 C4F88430 str r3, [r4, #132] +4045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2827 .loc 1 4045 9 is_stmt 1 view .LVU881 +4045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2828 .loc 1 4045 22 is_stmt 0 view .LVU882 + 2829 006a 0023 movs r3, #0 + 2830 006c E366 str r3, [r4, #108] + ARM GAS /tmp/ccizsdzp.s page 135 + + +4052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2831 .loc 1 4052 9 is_stmt 1 view .LVU883 + 2832 006e 2046 mov r0, r4 + 2833 0070 FFF7FEFF bl HAL_UART_RxCpltCallback + 2834 .LVL180: + 2835 0074 D5E7 b .L190 + 2836 .L195: +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 2837 .loc 1 4061 5 view .LVU884 +4061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 2838 .loc 1 4061 17 is_stmt 0 view .LVU885 + 2839 0076 B4F85E30 ldrh r3, [r4, #94] + 2840 007a 9BB2 uxth r3, r3 + 2841 .LVL181: +4062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2842 .loc 1 4062 5 is_stmt 1 view .LVU886 +4062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2843 .loc 1 4062 8 is_stmt 0 view .LVU887 + 2844 007c 002B cmp r3, #0 + 2845 007e CCD0 beq .L187 +4062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2846 .loc 1 4062 52 discriminator 1 view .LVU888 + 2847 0080 B4F86820 ldrh r2, [r4, #104] +4062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2848 .loc 1 4062 29 discriminator 1 view .LVU889 + 2849 0084 9A42 cmp r2, r3 + 2850 0086 C8D9 bls .L187 +4065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2851 .loc 1 4065 7 is_stmt 1 view .LVU890 + 2852 0088 2268 ldr r2, [r4] + 2853 008a 9368 ldr r3, [r2, #8] + 2854 .LVL182: +4065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2855 .loc 1 4065 7 is_stmt 0 view .LVU891 + 2856 008c 23F08053 bic r3, r3, #268435456 + 2857 0090 9360 str r3, [r2, #8] +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2858 .loc 1 4068 7 is_stmt 1 view .LVU892 +4068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2859 .loc 1 4068 20 is_stmt 0 view .LVU893 + 2860 0092 054B ldr r3, .L196+4 + 2861 0094 E366 str r3, [r4, #108] +4071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2862 .loc 1 4071 7 is_stmt 1 view .LVU894 + 2863 0096 2268 ldr r2, [r4] + 2864 0098 1368 ldr r3, [r2] + 2865 009a 43F02003 orr r3, r3, #32 + 2866 009e 1360 str r3, [r2] + 2867 00a0 BBE7 b .L187 + 2868 .L197: + 2869 00a2 00BF .align 2 + 2870 .L196: + 2871 00a4 FEFFFFEF .word -268435458 + 2872 00a8 00000000 .word UART_RxISR_16BIT + 2873 .cfi_endproc + 2874 .LFE207: + 2876 .section .text.UART_DMAReceiveCplt,"ax",%progbits + ARM GAS /tmp/ccizsdzp.s page 136 + + + 2877 .align 1 + 2878 .syntax unified + 2879 .thumb + 2880 .thumb_func + 2881 .fpu fpv5-d16 + 2883 UART_DMAReceiveCplt: + 2884 .LVL183: + 2885 .LFB191: +3388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2886 .loc 1 3388 1 view -0 + 2887 .cfi_startproc + 2888 @ args = 0, pretend = 0, frame = 0 + 2889 @ frame_needed = 0, uses_anonymous_args = 0 +3388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2890 .loc 1 3388 1 is_stmt 0 view .LVU896 + 2891 0000 08B5 push {r3, lr} + 2892 .LCFI22: + 2893 .cfi_def_cfa_offset 8 + 2894 .cfi_offset 3, -8 + 2895 .cfi_offset 14, -4 + 2896 0002 0346 mov r3, r0 +3389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2897 .loc 1 3389 3 is_stmt 1 view .LVU897 +3389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2898 .loc 1 3389 23 is_stmt 0 view .LVU898 + 2899 0004 806B ldr r0, [r0, #56] + 2900 .LVL184: +3392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2901 .loc 1 3392 3 is_stmt 1 view .LVU899 +3392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2902 .loc 1 3392 17 is_stmt 0 view .LVU900 + 2903 0006 DB69 ldr r3, [r3, #28] + 2904 .LVL185: +3392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 2905 .loc 1 3392 6 view .LVU901 + 2906 0008 B3F5807F cmp r3, #256 + 2907 000c 14D0 beq .L199 +3394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2908 .loc 1 3394 5 is_stmt 1 view .LVU902 +3394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2909 .loc 1 3394 24 is_stmt 0 view .LVU903 + 2910 000e 0023 movs r3, #0 + 2911 0010 A0F85E30 strh r3, [r0, #94] @ movhi +3397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2912 .loc 1 3397 5 is_stmt 1 view .LVU904 + 2913 0014 0268 ldr r2, [r0] + 2914 0016 1368 ldr r3, [r2] + 2915 0018 23F48073 bic r3, r3, #256 + 2916 001c 1360 str r3, [r2] +3398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2917 .loc 1 3398 5 view .LVU905 + 2918 001e 0268 ldr r2, [r0] + 2919 0020 9368 ldr r3, [r2, #8] + 2920 0022 23F00103 bic r3, r3, #1 + 2921 0026 9360 str r3, [r2, #8] +3402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2922 .loc 1 3402 5 view .LVU906 + ARM GAS /tmp/ccizsdzp.s page 137 + + + 2923 0028 0268 ldr r2, [r0] + 2924 002a 9368 ldr r3, [r2, #8] + 2925 002c 23F04003 bic r3, r3, #64 + 2926 0030 9360 str r3, [r2, #8] +3405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2927 .loc 1 3405 5 view .LVU907 +3405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 2928 .loc 1 3405 20 is_stmt 0 view .LVU908 + 2929 0032 2023 movs r3, #32 + 2930 0034 C0F88430 str r3, [r0, #132] + 2931 .L199: +3413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2932 .loc 1 3413 3 is_stmt 1 view .LVU909 + 2933 0038 FFF7FEFF bl HAL_UART_RxCpltCallback + 2934 .LVL186: +3415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2935 .loc 1 3415 1 is_stmt 0 view .LVU910 + 2936 003c 08BD pop {r3, pc} + 2937 .cfi_endproc + 2938 .LFE191: + 2940 .section .text.HAL_UART_RxHalfCpltCallback,"ax",%progbits + 2941 .align 1 + 2942 .weak HAL_UART_RxHalfCpltCallback + 2943 .syntax unified + 2944 .thumb + 2945 .thumb_func + 2946 .fpu fpv5-d16 + 2948 HAL_UART_RxHalfCpltCallback: + 2949 .LVL187: + 2950 .LFB167: +2457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2951 .loc 1 2457 1 is_stmt 1 view -0 + 2952 .cfi_startproc + 2953 @ args = 0, pretend = 0, frame = 0 + 2954 @ frame_needed = 0, uses_anonymous_args = 0 + 2955 @ link register save eliminated. +2459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2956 .loc 1 2459 3 view .LVU912 +2464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2957 .loc 1 2464 1 is_stmt 0 view .LVU913 + 2958 0000 7047 bx lr + 2959 .cfi_endproc + 2960 .LFE167: + 2962 .section .text.UART_DMARxHalfCplt,"ax",%progbits + 2963 .align 1 + 2964 .syntax unified + 2965 .thumb + 2966 .thumb_func + 2967 .fpu fpv5-d16 + 2969 UART_DMARxHalfCplt: + 2970 .LVL188: + 2971 .LFB192: +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2972 .loc 1 3423 1 is_stmt 1 view -0 + 2973 .cfi_startproc + 2974 @ args = 0, pretend = 0, frame = 0 + 2975 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccizsdzp.s page 138 + + +3423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2976 .loc 1 3423 1 is_stmt 0 view .LVU915 + 2977 0000 08B5 push {r3, lr} + 2978 .LCFI23: + 2979 .cfi_def_cfa_offset 8 + 2980 .cfi_offset 3, -8 + 2981 .cfi_offset 14, -4 +3424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2982 .loc 1 3424 3 is_stmt 1 view .LVU916 + 2983 .LVL189: +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2984 .loc 1 3431 3 view .LVU917 + 2985 0002 806B ldr r0, [r0, #56] + 2986 .LVL190: +3431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 2987 .loc 1 3431 3 is_stmt 0 view .LVU918 + 2988 0004 FFF7FEFF bl HAL_UART_RxHalfCpltCallback + 2989 .LVL191: +3433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 2990 .loc 1 3433 1 view .LVU919 + 2991 0008 08BD pop {r3, pc} + 2992 .cfi_endproc + 2993 .LFE192: + 2995 .section .text.HAL_UART_ErrorCallback,"ax",%progbits + 2996 .align 1 + 2997 .weak HAL_UART_ErrorCallback + 2998 .syntax unified + 2999 .thumb + 3000 .thumb_func + 3001 .fpu fpv5-d16 + 3003 HAL_UART_ErrorCallback: + 3004 .LVL192: + 3005 .LFB168: +2472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3006 .loc 1 2472 1 is_stmt 1 view -0 + 3007 .cfi_startproc + 3008 @ args = 0, pretend = 0, frame = 0 + 3009 @ frame_needed = 0, uses_anonymous_args = 0 + 3010 @ link register save eliminated. +2474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3011 .loc 1 2474 3 view .LVU921 +2479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3012 .loc 1 2479 1 is_stmt 0 view .LVU922 + 3013 0000 7047 bx lr + 3014 .cfi_endproc + 3015 .LFE168: + 3017 .section .text.UART_DMAError,"ax",%progbits + 3018 .align 1 + 3019 .syntax unified + 3020 .thumb + 3021 .thumb_func + 3022 .fpu fpv5-d16 + 3024 UART_DMAError: + 3025 .LVL193: + 3026 .LFB193: +3441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3027 .loc 1 3441 1 is_stmt 1 view -0 + ARM GAS /tmp/ccizsdzp.s page 139 + + + 3028 .cfi_startproc + 3029 @ args = 0, pretend = 0, frame = 0 + 3030 @ frame_needed = 0, uses_anonymous_args = 0 +3441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3031 .loc 1 3441 1 is_stmt 0 view .LVU924 + 3032 0000 38B5 push {r3, r4, r5, lr} + 3033 .LCFI24: + 3034 .cfi_def_cfa_offset 16 + 3035 .cfi_offset 3, -16 + 3036 .cfi_offset 4, -12 + 3037 .cfi_offset 5, -8 + 3038 .cfi_offset 14, -4 +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3039 .loc 1 3442 3 is_stmt 1 view .LVU925 +3442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3040 .loc 1 3442 23 is_stmt 0 view .LVU926 + 3041 0002 846B ldr r4, [r0, #56] + 3042 .LVL194: +3444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 3043 .loc 1 3444 3 is_stmt 1 view .LVU927 +3444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 3044 .loc 1 3444 31 is_stmt 0 view .LVU928 + 3045 0004 D4F88020 ldr r2, [r4, #128] + 3046 .LVL195: +3445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3047 .loc 1 3445 3 is_stmt 1 view .LVU929 +3445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3048 .loc 1 3445 31 is_stmt 0 view .LVU930 + 3049 0008 D4F88450 ldr r5, [r4, #132] + 3050 .LVL196: +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3051 .loc 1 3448 3 is_stmt 1 view .LVU931 +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3052 .loc 1 3448 8 is_stmt 0 view .LVU932 + 3053 000c 2368 ldr r3, [r4] + 3054 000e 9B68 ldr r3, [r3, #8] +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3055 .loc 1 3448 6 view .LVU933 + 3056 0010 13F0800F tst r3, #128 + 3057 0014 01D0 beq .L206 +3448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3058 .loc 1 3448 62 discriminator 1 view .LVU934 + 3059 0016 212A cmp r2, #33 + 3060 0018 10D0 beq .L209 + 3061 .LVL197: + 3062 .L206: +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3063 .loc 1 3456 3 is_stmt 1 view .LVU935 +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3064 .loc 1 3456 8 is_stmt 0 view .LVU936 + 3065 001a 2368 ldr r3, [r4] + 3066 001c 9B68 ldr r3, [r3, #8] +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3067 .loc 1 3456 6 view .LVU937 + 3068 001e 13F0400F tst r3, #64 + 3069 0022 01D0 beq .L207 +3456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + ARM GAS /tmp/ccizsdzp.s page 140 + + + 3070 .loc 1 3456 62 discriminator 1 view .LVU938 + 3071 0024 222D cmp r5, #34 + 3072 0026 10D0 beq .L210 + 3073 .L207: +3463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3074 .loc 1 3463 3 is_stmt 1 view .LVU939 +3463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3075 .loc 1 3463 20 is_stmt 0 view .LVU940 + 3076 0028 D4F88830 ldr r3, [r4, #136] + 3077 002c 43F01003 orr r3, r3, #16 + 3078 0030 C4F88830 str r3, [r4, #136] +3470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3079 .loc 1 3470 3 is_stmt 1 view .LVU941 + 3080 0034 2046 mov r0, r4 + 3081 0036 FFF7FEFF bl HAL_UART_ErrorCallback + 3082 .LVL198: +3472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3083 .loc 1 3472 1 is_stmt 0 view .LVU942 + 3084 003a 38BD pop {r3, r4, r5, pc} + 3085 .LVL199: + 3086 .L209: +3451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndTxTransfer(huart); + 3087 .loc 1 3451 5 is_stmt 1 view .LVU943 +3451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndTxTransfer(huart); + 3088 .loc 1 3451 24 is_stmt 0 view .LVU944 + 3089 003c 0023 movs r3, #0 + 3090 003e A4F85630 strh r3, [r4, #86] @ movhi +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3091 .loc 1 3452 5 is_stmt 1 view .LVU945 + 3092 0042 2046 mov r0, r4 + 3093 .LVL200: +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3094 .loc 1 3452 5 is_stmt 0 view .LVU946 + 3095 0044 FFF7FEFF bl UART_EndTxTransfer + 3096 .LVL201: +3452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3097 .loc 1 3452 5 view .LVU947 + 3098 0048 E7E7 b .L206 + 3099 .L210: +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndRxTransfer(huart); + 3100 .loc 1 3459 5 is_stmt 1 view .LVU948 +3459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_EndRxTransfer(huart); + 3101 .loc 1 3459 24 is_stmt 0 view .LVU949 + 3102 004a 0023 movs r3, #0 + 3103 004c A4F85E30 strh r3, [r4, #94] @ movhi +3460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3104 .loc 1 3460 5 is_stmt 1 view .LVU950 + 3105 0050 2046 mov r0, r4 + 3106 0052 FFF7FEFF bl UART_EndRxTransfer + 3107 .LVL202: + 3108 0056 E7E7 b .L207 + 3109 .cfi_endproc + 3110 .LFE193: + 3112 .section .text.HAL_UART_IRQHandler,"ax",%progbits + 3113 .align 1 + 3114 .global HAL_UART_IRQHandler + 3115 .syntax unified + ARM GAS /tmp/ccizsdzp.s page 141 + + + 3116 .thumb + 3117 .thumb_func + 3118 .fpu fpv5-d16 + 3120 HAL_UART_IRQHandler: + 3121 .LVL203: + 3122 .LFB163: +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); + 3123 .loc 1 2180 1 view -0 + 3124 .cfi_startproc + 3125 @ args = 0, pretend = 0, frame = 0 + 3126 @ frame_needed = 0, uses_anonymous_args = 0 +2180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); + 3127 .loc 1 2180 1 is_stmt 0 view .LVU952 + 3128 0000 70B5 push {r4, r5, r6, lr} + 3129 .LCFI25: + 3130 .cfi_def_cfa_offset 16 + 3131 .cfi_offset 4, -16 + 3132 .cfi_offset 5, -12 + 3133 .cfi_offset 6, -8 + 3134 .cfi_offset 14, -4 + 3135 0002 0446 mov r4, r0 +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 3136 .loc 1 2181 3 is_stmt 1 view .LVU953 +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 3137 .loc 1 2181 25 is_stmt 0 view .LVU954 + 3138 0004 0168 ldr r1, [r0] +2181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 3139 .loc 1 2181 12 view .LVU955 + 3140 0006 CB69 ldr r3, [r1, #28] + 3141 .LVL204: +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr3its = READ_REG(huart->Instance->CR3); + 3142 .loc 1 2182 3 is_stmt 1 view .LVU956 +2182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t cr3its = READ_REG(huart->Instance->CR3); + 3143 .loc 1 2182 12 is_stmt 0 view .LVU957 + 3144 0008 0D68 ldr r5, [r1] + 3145 .LVL205: +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3146 .loc 1 2183 3 is_stmt 1 view .LVU958 +2183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3147 .loc 1 2183 12 is_stmt 0 view .LVU959 + 3148 000a 8868 ldr r0, [r1, #8] + 3149 .LVL206: +2185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t errorcode; + 3150 .loc 1 2185 3 is_stmt 1 view .LVU960 +2186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3151 .loc 1 2186 3 view .LVU961 +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (errorflags == 0U) + 3152 .loc 1 2189 3 view .LVU962 +2189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (errorflags == 0U) + 3153 .loc 1 2189 14 is_stmt 0 view .LVU963 + 3154 000c 40F60F02 movw r2, #2063 + 3155 .LVL207: +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3156 .loc 1 2190 3 is_stmt 1 view .LVU964 +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3157 .loc 1 2190 6 is_stmt 0 view .LVU965 + 3158 0010 1A40 ands r2, r3, r2 + ARM GAS /tmp/ccizsdzp.s page 142 + + + 3159 .LVL208: +2190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3160 .loc 1 2190 6 view .LVU966 + 3161 0012 08D1 bne .L212 +2193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 3162 .loc 1 2193 5 is_stmt 1 view .LVU967 +2193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 3163 .loc 1 2193 8 is_stmt 0 view .LVU968 + 3164 0014 13F0200F tst r3, #32 + 3165 0018 05D0 beq .L212 +2194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 3166 .loc 1 2194 9 view .LVU969 + 3167 001a 15F0200F tst r5, #32 + 3168 001e 30D1 bne .L213 +2195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3169 .loc 1 2195 13 view .LVU970 + 3170 0020 10F0805F tst r0, #268435456 + 3171 0024 2DD1 bne .L213 + 3172 .L212: +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + 3173 .loc 1 2206 3 is_stmt 1 view .LVU971 +2206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + 3174 .loc 1 2206 6 is_stmt 0 view .LVU972 + 3175 0026 2AB1 cbz r2, .L216 +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + 3176 .loc 1 2207 21 view .LVU973 + 3177 0028 6D4A ldr r2, .L242 + 3178 .LVL209: +2207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + 3179 .loc 1 2207 7 view .LVU974 + 3180 002a 0240 ands r2, r0, r2 + 3181 002c 2FD1 bne .L217 +2208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3182 .loc 1 2208 12 view .LVU975 + 3183 002e 6D4E ldr r6, .L242+4 + 3184 0030 3542 tst r5, r6 + 3185 0032 2CD1 bne .L217 + 3186 .L216: +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3187 .loc 1 2343 3 is_stmt 1 view .LVU976 +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3188 .loc 1 2343 6 is_stmt 0 view .LVU977 + 3189 0034 13F4801F tst r3, #1048576 + 3190 0038 03D0 beq .L231 +2343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3191 .loc 1 2343 42 discriminator 1 view .LVU978 + 3192 003a 10F4800F tst r0, #4194304 + 3193 003e 40F0B480 bne .L238 + 3194 .L231: +2361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + 3195 .loc 1 2361 3 is_stmt 1 view .LVU979 +2361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + 3196 .loc 1 2361 6 is_stmt 0 view .LVU980 + 3197 0042 13F0800F tst r3, #128 + 3198 0046 07D0 beq .L232 +2362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr3its & USART_CR3_TXFTIE) != 0U))) + 3199 .loc 1 2362 7 view .LVU981 + ARM GAS /tmp/ccizsdzp.s page 143 + + + 3200 0048 15F0800F tst r5, #128 + 3201 004c 40F0B480 bne .L233 +2363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3202 .loc 1 2363 11 view .LVU982 + 3203 0050 10F4000F tst r0, #8388608 + 3204 0054 40F0B080 bne .L233 + 3205 .L232: +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3206 .loc 1 2373 3 is_stmt 1 view .LVU983 +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3207 .loc 1 2373 6 is_stmt 0 view .LVU984 + 3208 0058 13F0400F tst r3, #64 + 3209 005c 03D0 beq .L235 +2373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3210 .loc 1 2373 41 discriminator 1 view .LVU985 + 3211 005e 15F0400F tst r5, #64 + 3212 0062 40F0B080 bne .L239 + 3213 .L235: +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3214 .loc 1 2380 3 is_stmt 1 view .LVU986 +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3215 .loc 1 2380 6 is_stmt 0 view .LVU987 + 3216 0066 13F4000F tst r3, #8388608 + 3217 006a 03D0 beq .L236 +2380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3218 .loc 1 2380 43 discriminator 1 view .LVU988 + 3219 006c 15F0804F tst r5, #1073741824 + 3220 0070 40F0AD80 bne .L240 + 3221 .L236: +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3222 .loc 1 2393 3 is_stmt 1 view .LVU989 +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3223 .loc 1 2393 6 is_stmt 0 view .LVU990 + 3224 0074 13F0807F tst r3, #16777216 + 3225 0078 02D0 beq .L211 +2393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3226 .loc 1 2393 43 discriminator 1 view .LVU991 + 3227 007a 002D cmp r5, #0 + 3228 007c C0F2AB80 blt .L241 + 3229 .LVL210: + 3230 .L211: +2404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3231 .loc 1 2404 1 view .LVU992 + 3232 0080 70BD pop {r4, r5, r6, pc} + 3233 .LVL211: + 3234 .L213: +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3235 .loc 1 2197 7 is_stmt 1 view .LVU993 +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3236 .loc 1 2197 16 is_stmt 0 view .LVU994 + 3237 0082 E36E ldr r3, [r4, #108] + 3238 .LVL212: +2197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3239 .loc 1 2197 10 view .LVU995 + 3240 0084 002B cmp r3, #0 + 3241 0086 FBD0 beq .L211 +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 144 + + + 3242 .loc 1 2199 9 is_stmt 1 view .LVU996 + 3243 0088 2046 mov r0, r4 + 3244 .LVL213: +2199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3245 .loc 1 2199 9 is_stmt 0 view .LVU997 + 3246 008a 9847 blx r3 + 3247 .LVL214: +2201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3248 .loc 1 2201 7 is_stmt 1 view .LVU998 + 3249 008c F8E7 b .L211 + 3250 .LVL215: + 3251 .L217: +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3252 .loc 1 2211 5 view .LVU999 +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3253 .loc 1 2211 8 is_stmt 0 view .LVU1000 + 3254 008e 13F0010F tst r3, #1 + 3255 0092 09D0 beq .L218 +2211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3256 .loc 1 2211 43 discriminator 1 view .LVU1001 + 3257 0094 15F4807F tst r5, #256 + 3258 0098 06D0 beq .L218 +2213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3259 .loc 1 2213 7 is_stmt 1 view .LVU1002 + 3260 009a 0126 movs r6, #1 + 3261 009c 0E62 str r6, [r1, #32] +2215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3262 .loc 1 2215 7 view .LVU1003 +2215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3263 .loc 1 2215 24 is_stmt 0 view .LVU1004 + 3264 009e D4F88810 ldr r1, [r4, #136] + 3265 00a2 3143 orrs r1, r1, r6 + 3266 00a4 C4F88810 str r1, [r4, #136] + 3267 .L218: +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3268 .loc 1 2219 5 is_stmt 1 view .LVU1005 +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3269 .loc 1 2219 8 is_stmt 0 view .LVU1006 + 3270 00a8 13F0020F tst r3, #2 + 3271 00ac 0BD0 beq .L219 +2219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3272 .loc 1 2219 43 discriminator 1 view .LVU1007 + 3273 00ae 10F0010F tst r0, #1 + 3274 00b2 08D0 beq .L219 +2221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3275 .loc 1 2221 7 is_stmt 1 view .LVU1008 + 3276 00b4 2168 ldr r1, [r4] + 3277 00b6 0226 movs r6, #2 + 3278 00b8 0E62 str r6, [r1, #32] +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3279 .loc 1 2223 7 view .LVU1009 +2223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3280 .loc 1 2223 24 is_stmt 0 view .LVU1010 + 3281 00ba D4F88810 ldr r1, [r4, #136] + 3282 00be 41F00401 orr r1, r1, #4 + 3283 00c2 C4F88810 str r1, [r4, #136] + 3284 .L219: + ARM GAS /tmp/ccizsdzp.s page 145 + + +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3285 .loc 1 2227 5 is_stmt 1 view .LVU1011 +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3286 .loc 1 2227 8 is_stmt 0 view .LVU1012 + 3287 00c6 13F0040F tst r3, #4 + 3288 00ca 0BD0 beq .L220 +2227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3289 .loc 1 2227 43 discriminator 1 view .LVU1013 + 3290 00cc 10F0010F tst r0, #1 + 3291 00d0 08D0 beq .L220 +2229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3292 .loc 1 2229 7 is_stmt 1 view .LVU1014 + 3293 00d2 2168 ldr r1, [r4] + 3294 00d4 0426 movs r6, #4 + 3295 00d6 0E62 str r6, [r1, #32] +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3296 .loc 1 2231 7 view .LVU1015 +2231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3297 .loc 1 2231 24 is_stmt 0 view .LVU1016 + 3298 00d8 D4F88810 ldr r1, [r4, #136] + 3299 00dc 41F00201 orr r1, r1, #2 + 3300 00e0 C4F88810 str r1, [r4, #136] + 3301 .L220: +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 3302 .loc 1 2235 5 is_stmt 1 view .LVU1017 +2235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 3303 .loc 1 2235 8 is_stmt 0 view .LVU1018 + 3304 00e4 13F0080F tst r3, #8 + 3305 00e8 0BD0 beq .L221 +2236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + 3306 .loc 1 2236 9 view .LVU1019 + 3307 00ea 15F0200F tst r5, #32 + 3308 00ee 00D1 bne .L222 +2236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + 3309 .loc 1 2236 57 discriminator 1 view .LVU1020 + 3310 00f0 3AB1 cbz r2, .L221 + 3311 .L222: +2239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3312 .loc 1 2239 7 is_stmt 1 view .LVU1021 + 3313 00f2 2268 ldr r2, [r4] + 3314 00f4 0821 movs r1, #8 + 3315 00f6 1162 str r1, [r2, #32] +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3316 .loc 1 2241 7 view .LVU1022 +2241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3317 .loc 1 2241 24 is_stmt 0 view .LVU1023 + 3318 00f8 D4F88820 ldr r2, [r4, #136] + 3319 00fc 0A43 orrs r2, r2, r1 + 3320 00fe C4F88820 str r2, [r4, #136] + 3321 .L221: +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3322 .loc 1 2245 5 is_stmt 1 view .LVU1024 +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3323 .loc 1 2245 8 is_stmt 0 view .LVU1025 + 3324 0102 13F4006F tst r3, #2048 + 3325 0106 0CD0 beq .L223 +2245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 146 + + + 3326 .loc 1 2245 45 discriminator 1 view .LVU1026 + 3327 0108 15F0806F tst r5, #67108864 + 3328 010c 09D0 beq .L223 +2247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3329 .loc 1 2247 7 is_stmt 1 view .LVU1027 + 3330 010e 2268 ldr r2, [r4] + 3331 0110 4FF40061 mov r1, #2048 + 3332 0114 1162 str r1, [r2, #32] +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3333 .loc 1 2249 7 view .LVU1028 +2249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3334 .loc 1 2249 24 is_stmt 0 view .LVU1029 + 3335 0116 D4F88820 ldr r2, [r4, #136] + 3336 011a 42F02002 orr r2, r2, #32 + 3337 011e C4F88820 str r2, [r4, #136] + 3338 .L223: +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3339 .loc 1 2253 5 is_stmt 1 view .LVU1030 +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3340 .loc 1 2253 14 is_stmt 0 view .LVU1031 + 3341 0122 D4F88820 ldr r2, [r4, #136] +2253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3342 .loc 1 2253 8 view .LVU1032 + 3343 0126 002A cmp r2, #0 + 3344 0128 AAD0 beq .L211 +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 3345 .loc 1 2256 7 is_stmt 1 view .LVU1033 +2256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 3346 .loc 1 2256 10 is_stmt 0 view .LVU1034 + 3347 012a 13F0200F tst r3, #32 + 3348 012e 09D0 beq .L225 +2257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 3349 .loc 1 2257 11 view .LVU1035 + 3350 0130 15F0200F tst r5, #32 + 3351 0134 02D1 bne .L226 +2258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3352 .loc 1 2258 15 view .LVU1036 + 3353 0136 10F0805F tst r0, #268435456 + 3354 013a 03D0 beq .L225 + 3355 .L226: +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3356 .loc 1 2260 9 is_stmt 1 view .LVU1037 +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3357 .loc 1 2260 18 is_stmt 0 view .LVU1038 + 3358 013c E36E ldr r3, [r4, #108] + 3359 .LVL216: +2260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3360 .loc 1 2260 12 view .LVU1039 + 3361 013e 0BB1 cbz r3, .L225 +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3362 .loc 1 2262 11 is_stmt 1 view .LVU1040 + 3363 0140 2046 mov r0, r4 + 3364 .LVL217: +2262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3365 .loc 1 2262 11 is_stmt 0 view .LVU1041 + 3366 0142 9847 blx r3 + 3367 .LVL218: + ARM GAS /tmp/ccizsdzp.s page 147 + + + 3368 .L225: +2271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 3369 .loc 1 2271 7 is_stmt 1 view .LVU1042 +2271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 3370 .loc 1 2271 17 is_stmt 0 view .LVU1043 + 3371 0144 D4F88820 ldr r2, [r4, #136] + 3372 .LVL219: +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 3373 .loc 1 2272 7 is_stmt 1 view .LVU1044 +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 3374 .loc 1 2272 12 is_stmt 0 view .LVU1045 + 3375 0148 2368 ldr r3, [r4] + 3376 014a 9B68 ldr r3, [r3, #8] +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 3377 .loc 1 2272 10 view .LVU1046 + 3378 014c 13F0400F tst r3, #64 + 3379 0150 02D1 bne .L227 +2272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 3380 .loc 1 2272 66 discriminator 1 view .LVU1047 + 3381 0152 12F0280F tst r2, #40 + 3382 0156 21D0 beq .L228 + 3383 .L227: +2278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3384 .loc 1 2278 9 is_stmt 1 view .LVU1048 + 3385 0158 2046 mov r0, r4 + 3386 015a FFF7FEFF bl UART_EndRxTransfer + 3387 .LVL220: +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3388 .loc 1 2281 9 view .LVU1049 +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3389 .loc 1 2281 13 is_stmt 0 view .LVU1050 + 3390 015e 2368 ldr r3, [r4] + 3391 0160 9A68 ldr r2, [r3, #8] +2281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3392 .loc 1 2281 12 view .LVU1051 + 3393 0162 12F0400F tst r2, #64 + 3394 0166 15D0 beq .L229 +2283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3395 .loc 1 2283 11 is_stmt 1 view .LVU1052 + 3396 0168 9A68 ldr r2, [r3, #8] + 3397 016a 22F04002 bic r2, r2, #64 + 3398 016e 9A60 str r2, [r3, #8] +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3399 .loc 1 2286 11 view .LVU1053 +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3400 .loc 1 2286 20 is_stmt 0 view .LVU1054 + 3401 0170 A36F ldr r3, [r4, #120] +2286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3402 .loc 1 2286 14 view .LVU1055 + 3403 0172 5BB1 cbz r3, .L230 +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3404 .loc 1 2290 13 is_stmt 1 view .LVU1056 +2290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3405 .loc 1 2290 46 is_stmt 0 view .LVU1057 + 3406 0174 1C4A ldr r2, .L242+8 + 3407 0176 1A65 str r2, [r3, #80] +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 148 + + + 3408 .loc 1 2293 13 is_stmt 1 view .LVU1058 +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3409 .loc 1 2293 17 is_stmt 0 view .LVU1059 + 3410 0178 A06F ldr r0, [r4, #120] + 3411 017a FFF7FEFF bl HAL_DMA_Abort_IT + 3412 .LVL221: +2293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3413 .loc 1 2293 16 view .LVU1060 + 3414 017e 0028 cmp r0, #0 + 3415 0180 3FF47EAF beq .L211 +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3416 .loc 1 2296 15 is_stmt 1 view .LVU1061 +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3417 .loc 1 2296 20 is_stmt 0 view .LVU1062 + 3418 0184 A06F ldr r0, [r4, #120] +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3419 .loc 1 2296 28 view .LVU1063 + 3420 0186 036D ldr r3, [r0, #80] +2296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3421 .loc 1 2296 15 view .LVU1064 + 3422 0188 9847 blx r3 + 3423 .LVL222: + 3424 018a 79E7 b .L211 + 3425 .L230: +2307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3426 .loc 1 2307 13 is_stmt 1 view .LVU1065 + 3427 018c 2046 mov r0, r4 + 3428 018e FFF7FEFF bl HAL_UART_ErrorCallback + 3429 .LVL223: + 3430 0192 75E7 b .L211 + 3431 .L229: +2320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3432 .loc 1 2320 11 view .LVU1066 + 3433 0194 2046 mov r0, r4 + 3434 0196 FFF7FEFF bl HAL_UART_ErrorCallback + 3435 .LVL224: + 3436 019a 71E7 b .L211 + 3437 .LVL225: + 3438 .L228: +2333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3439 .loc 1 2333 9 view .LVU1067 + 3440 019c 2046 mov r0, r4 + 3441 019e FFF7FEFF bl HAL_UART_ErrorCallback + 3442 .LVL226: +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3443 .loc 1 2335 9 view .LVU1068 +2335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3444 .loc 1 2335 26 is_stmt 0 view .LVU1069 + 3445 01a2 0023 movs r3, #0 + 3446 01a4 C4F88830 str r3, [r4, #136] +2338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3447 .loc 1 2338 5 is_stmt 1 view .LVU1070 + 3448 01a8 6AE7 b .L211 + 3449 .LVL227: + 3450 .L238: +2345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3451 .loc 1 2345 5 view .LVU1071 + ARM GAS /tmp/ccizsdzp.s page 149 + + + 3452 01aa 4FF48013 mov r3, #1048576 + 3453 .LVL228: +2345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3454 .loc 1 2345 5 is_stmt 0 view .LVU1072 + 3455 01ae 0B62 str r3, [r1, #32] +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3456 .loc 1 2355 5 is_stmt 1 view .LVU1073 + 3457 01b0 2046 mov r0, r4 + 3458 .LVL229: +2355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3459 .loc 1 2355 5 is_stmt 0 view .LVU1074 + 3460 01b2 FFF7FEFF bl HAL_UARTEx_WakeupCallback + 3461 .LVL230: +2357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3462 .loc 1 2357 5 is_stmt 1 view .LVU1075 + 3463 01b6 63E7 b .L211 + 3464 .LVL231: + 3465 .L233: +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3466 .loc 1 2365 5 view .LVU1076 +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3467 .loc 1 2365 14 is_stmt 0 view .LVU1077 + 3468 01b8 236F ldr r3, [r4, #112] + 3469 .LVL232: +2365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3470 .loc 1 2365 8 view .LVU1078 + 3471 01ba 002B cmp r3, #0 + 3472 01bc 3FF460AF beq .L211 +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3473 .loc 1 2367 7 is_stmt 1 view .LVU1079 + 3474 01c0 2046 mov r0, r4 + 3475 .LVL233: +2367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3476 .loc 1 2367 7 is_stmt 0 view .LVU1080 + 3477 01c2 9847 blx r3 + 3478 .LVL234: +2369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3479 .loc 1 2369 5 is_stmt 1 view .LVU1081 + 3480 01c4 5CE7 b .L211 + 3481 .LVL235: + 3482 .L239: +2375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; + 3483 .loc 1 2375 5 view .LVU1082 + 3484 01c6 2046 mov r0, r4 + 3485 .LVL236: +2375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return; + 3486 .loc 1 2375 5 is_stmt 0 view .LVU1083 + 3487 01c8 FFF7FEFF bl UART_EndTransmit_IT + 3488 .LVL237: +2376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3489 .loc 1 2376 5 is_stmt 1 view .LVU1084 + 3490 01cc 58E7 b .L211 + 3491 .LVL238: + 3492 .L240: +2387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3493 .loc 1 2387 5 view .LVU1085 + 3494 01ce 2046 mov r0, r4 + ARM GAS /tmp/ccizsdzp.s page 150 + + + 3495 .LVL239: +2387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3496 .loc 1 2387 5 is_stmt 0 view .LVU1086 + 3497 01d0 FFF7FEFF bl HAL_UARTEx_TxFifoEmptyCallback + 3498 .LVL240: +2389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3499 .loc 1 2389 5 is_stmt 1 view .LVU1087 + 3500 01d4 54E7 b .L211 + 3501 .LVL241: + 3502 .L241: +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3503 .loc 1 2400 5 view .LVU1088 + 3504 01d6 2046 mov r0, r4 + 3505 .LVL242: +2400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3506 .loc 1 2400 5 is_stmt 0 view .LVU1089 + 3507 01d8 FFF7FEFF bl HAL_UARTEx_RxFifoFullCallback + 3508 .LVL243: +2402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3509 .loc 1 2402 5 is_stmt 1 view .LVU1090 + 3510 01dc 50E7 b .L211 + 3511 .L243: + 3512 01de 00BF .align 2 + 3513 .L242: + 3514 01e0 01000010 .word 268435457 + 3515 01e4 20010004 .word 67109152 + 3516 01e8 00000000 .word UART_DMAAbortOnError + 3517 .cfi_endproc + 3518 .LFE163: + 3520 .section .text.UART_DMAAbortOnError,"ax",%progbits + 3521 .align 1 + 3522 .syntax unified + 3523 .thumb + 3524 .thumb_func + 3525 .fpu fpv5-d16 + 3527 UART_DMAAbortOnError: + 3528 .LVL244: + 3529 .LFB194: +3481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3530 .loc 1 3481 1 view -0 + 3531 .cfi_startproc + 3532 @ args = 0, pretend = 0, frame = 0 + 3533 @ frame_needed = 0, uses_anonymous_args = 0 +3481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3534 .loc 1 3481 1 is_stmt 0 view .LVU1092 + 3535 0000 08B5 push {r3, lr} + 3536 .LCFI26: + 3537 .cfi_def_cfa_offset 8 + 3538 .cfi_offset 3, -8 + 3539 .cfi_offset 14, -4 +3482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3540 .loc 1 3482 3 is_stmt 1 view .LVU1093 +3482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3541 .loc 1 3482 23 is_stmt 0 view .LVU1094 + 3542 0002 806B ldr r0, [r0, #56] + 3543 .LVL245: +3483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; + ARM GAS /tmp/ccizsdzp.s page 151 + + + 3544 .loc 1 3483 3 is_stmt 1 view .LVU1095 +3483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = 0U; + 3545 .loc 1 3483 22 is_stmt 0 view .LVU1096 + 3546 0004 0023 movs r3, #0 + 3547 0006 A0F85E30 strh r3, [r0, #94] @ movhi +3484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3548 .loc 1 3484 3 is_stmt 1 view .LVU1097 +3484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3549 .loc 1 3484 22 is_stmt 0 view .LVU1098 + 3550 000a A0F85630 strh r3, [r0, #86] @ movhi +3491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3551 .loc 1 3491 3 is_stmt 1 view .LVU1099 + 3552 000e FFF7FEFF bl HAL_UART_ErrorCallback + 3553 .LVL246: +3493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3554 .loc 1 3493 1 is_stmt 0 view .LVU1100 + 3555 0012 08BD pop {r3, pc} + 3556 .cfi_endproc + 3557 .LFE194: + 3559 .section .text.HAL_UART_AbortCpltCallback,"ax",%progbits + 3560 .align 1 + 3561 .weak HAL_UART_AbortCpltCallback + 3562 .syntax unified + 3563 .thumb + 3564 .thumb_func + 3565 .fpu fpv5-d16 + 3567 HAL_UART_AbortCpltCallback: + 3568 .LVL247: + 3569 .LFB169: +2487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3570 .loc 1 2487 1 is_stmt 1 view -0 + 3571 .cfi_startproc + 3572 @ args = 0, pretend = 0, frame = 0 + 3573 @ frame_needed = 0, uses_anonymous_args = 0 + 3574 @ link register save eliminated. +2489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3575 .loc 1 2489 3 view .LVU1102 +2494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3576 .loc 1 2494 1 is_stmt 0 view .LVU1103 + 3577 0000 7047 bx lr + 3578 .cfi_endproc + 3579 .LFE169: + 3581 .section .text.HAL_UART_Abort_IT,"ax",%progbits + 3582 .align 1 + 3583 .global HAL_UART_Abort_IT + 3584 .syntax unified + 3585 .thumb + 3586 .thumb_func + 3587 .fpu fpv5-d16 + 3589 HAL_UART_Abort_IT: + 3590 .LVL248: + 3591 .LFB160: +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t abortcplt = 1U; + 3592 .loc 1 1862 1 is_stmt 1 view -0 + 3593 .cfi_startproc + 3594 @ args = 0, pretend = 0, frame = 0 + 3595 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccizsdzp.s page 152 + + +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t abortcplt = 1U; + 3596 .loc 1 1862 1 is_stmt 0 view .LVU1105 + 3597 0000 10B5 push {r4, lr} + 3598 .LCFI27: + 3599 .cfi_def_cfa_offset 8 + 3600 .cfi_offset 4, -8 + 3601 .cfi_offset 14, -4 + 3602 0002 0446 mov r4, r0 +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3603 .loc 1 1863 3 is_stmt 1 view .LVU1106 + 3604 .LVL249: +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + 3605 .loc 1 1866 3 view .LVU1107 + 3606 0004 0268 ldr r2, [r0] + 3607 0006 1368 ldr r3, [r2] + 3608 0008 23F4F073 bic r3, r3, #480 + 3609 000c 1360 str r3, [r2] +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3610 .loc 1 1867 3 view .LVU1108 + 3611 000e 0268 ldr r2, [r0] + 3612 0010 9168 ldr r1, [r2, #8] + 3613 0012 374B ldr r3, .L262 + 3614 0014 0B40 ands r3, r3, r1 + 3615 0016 9360 str r3, [r2, #8] +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3616 .loc 1 1872 3 view .LVU1109 +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3617 .loc 1 1872 12 is_stmt 0 view .LVU1110 + 3618 0018 436F ldr r3, [r0, #116] +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3619 .loc 1 1872 6 view .LVU1111 + 3620 001a 33B1 cbz r3, .L248 +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3621 .loc 1 1876 5 is_stmt 1 view .LVU1112 +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3622 .loc 1 1876 9 is_stmt 0 view .LVU1113 + 3623 001c 0268 ldr r2, [r0] + 3624 001e 9268 ldr r2, [r2, #8] +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3625 .loc 1 1876 8 view .LVU1114 + 3626 0020 12F0800F tst r2, #128 + 3627 0024 1FD0 beq .L249 +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3628 .loc 1 1878 7 is_stmt 1 view .LVU1115 +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3629 .loc 1 1878 40 is_stmt 0 view .LVU1116 + 3630 0026 334A ldr r2, .L262+4 + 3631 0028 1A65 str r2, [r3, #80] + 3632 .L248: +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3633 .loc 1 1886 3 is_stmt 1 view .LVU1117 +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3634 .loc 1 1886 12 is_stmt 0 view .LVU1118 + 3635 002a A36F ldr r3, [r4, #120] +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3636 .loc 1 1886 6 view .LVU1119 + 3637 002c 33B1 cbz r3, .L250 + ARM GAS /tmp/ccizsdzp.s page 153 + + +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3638 .loc 1 1890 5 is_stmt 1 view .LVU1120 +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3639 .loc 1 1890 9 is_stmt 0 view .LVU1121 + 3640 002e 2268 ldr r2, [r4] + 3641 0030 9268 ldr r2, [r2, #8] +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3642 .loc 1 1890 8 view .LVU1122 + 3643 0032 12F0400F tst r2, #64 + 3644 0036 19D0 beq .L251 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3645 .loc 1 1892 7 is_stmt 1 view .LVU1123 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3646 .loc 1 1892 40 is_stmt 0 view .LVU1124 + 3647 0038 2F4A ldr r2, .L262+8 + 3648 003a 1A65 str r2, [r3, #80] + 3649 .L250: +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3650 .loc 1 1901 3 is_stmt 1 view .LVU1125 +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3651 .loc 1 1901 7 is_stmt 0 view .LVU1126 + 3652 003c 2368 ldr r3, [r4] + 3653 003e 9A68 ldr r2, [r3, #8] +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3654 .loc 1 1901 6 view .LVU1127 + 3655 0040 12F0800F tst r2, #128 + 3656 0044 15D0 beq .L257 +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3657 .loc 1 1904 5 is_stmt 1 view .LVU1128 + 3658 0046 9A68 ldr r2, [r3, #8] + 3659 0048 22F08002 bic r2, r2, #128 + 3660 004c 9A60 str r2, [r3, #8] +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3661 .loc 1 1907 5 view .LVU1129 +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3662 .loc 1 1907 14 is_stmt 0 view .LVU1130 + 3663 004e 606F ldr r0, [r4, #116] + 3664 .LVL250: +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3665 .loc 1 1907 8 view .LVU1131 + 3666 0050 0028 cmp r0, #0 + 3667 0052 3ED0 beq .L258 +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3668 .loc 1 1913 7 is_stmt 1 view .LVU1132 +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3669 .loc 1 1913 11 is_stmt 0 view .LVU1133 + 3670 0054 FFF7FEFF bl HAL_DMA_Abort_IT + 3671 .LVL251: +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3672 .loc 1 1913 10 view .LVU1134 + 3673 0058 0028 cmp r0, #0 + 3674 005a 3CD0 beq .L259 +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3675 .loc 1 1915 9 is_stmt 1 view .LVU1135 +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3676 .loc 1 1915 14 is_stmt 0 view .LVU1136 + 3677 005c 636F ldr r3, [r4, #116] + ARM GAS /tmp/ccizsdzp.s page 154 + + +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3678 .loc 1 1915 42 view .LVU1137 + 3679 005e 0022 movs r2, #0 + 3680 0060 1A65 str r2, [r3, #80] +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3681 .loc 1 1863 12 view .LVU1138 + 3682 0062 0121 movs r1, #1 + 3683 0064 06E0 b .L252 + 3684 .LVL252: + 3685 .L249: +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3686 .loc 1 1882 7 is_stmt 1 view .LVU1139 +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3687 .loc 1 1882 40 is_stmt 0 view .LVU1140 + 3688 0066 0022 movs r2, #0 + 3689 0068 1A65 str r2, [r3, #80] + 3690 006a DEE7 b .L248 + 3691 .L251: +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3692 .loc 1 1896 7 is_stmt 1 view .LVU1141 +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3693 .loc 1 1896 40 is_stmt 0 view .LVU1142 + 3694 006c 0022 movs r2, #0 + 3695 006e 1A65 str r2, [r3, #80] + 3696 0070 E4E7 b .L250 + 3697 .L257: +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3698 .loc 1 1863 12 view .LVU1143 + 3699 0072 0121 movs r1, #1 + 3700 .LVL253: + 3701 .L252: +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3702 .loc 1 1925 3 is_stmt 1 view .LVU1144 +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3703 .loc 1 1925 7 is_stmt 0 view .LVU1145 + 3704 0074 2368 ldr r3, [r4] + 3705 0076 9A68 ldr r2, [r3, #8] +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3706 .loc 1 1925 6 view .LVU1146 + 3707 0078 12F0400F tst r2, #64 + 3708 007c 2DD0 beq .L253 +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3709 .loc 1 1927 5 is_stmt 1 view .LVU1147 + 3710 007e 9A68 ldr r2, [r3, #8] + 3711 0080 22F04002 bic r2, r2, #64 + 3712 0084 9A60 str r2, [r3, #8] +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3713 .loc 1 1930 5 view .LVU1148 +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3714 .loc 1 1930 14 is_stmt 0 view .LVU1149 + 3715 0086 A06F ldr r0, [r4, #120] +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3716 .loc 1 1930 8 view .LVU1150 + 3717 0088 38B3 cbz r0, .L253 +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3718 .loc 1 1936 7 is_stmt 1 view .LVU1151 +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 155 + + + 3719 .loc 1 1936 11 is_stmt 0 view .LVU1152 + 3720 008a FFF7FEFF bl HAL_DMA_Abort_IT + 3721 .LVL254: +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3722 .loc 1 1936 10 view .LVU1153 + 3723 008e 30B3 cbz r0, .L254 +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** abortcplt = 1U; + 3724 .loc 1 1938 9 is_stmt 1 view .LVU1154 +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** abortcplt = 1U; + 3725 .loc 1 1938 14 is_stmt 0 view .LVU1155 + 3726 0090 A36F ldr r3, [r4, #120] +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** abortcplt = 1U; + 3727 .loc 1 1938 42 view .LVU1156 + 3728 0092 0022 movs r2, #0 + 3729 0094 1A65 str r2, [r3, #80] +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3730 .loc 1 1939 9 is_stmt 1 view .LVU1157 + 3731 .LVL255: +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3732 .loc 1 1949 3 view .LVU1158 + 3733 .L255: +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3734 .loc 1 1952 5 view .LVU1159 +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3735 .loc 1 1952 24 is_stmt 0 view .LVU1160 + 3736 0096 0023 movs r3, #0 + 3737 0098 A4F85630 strh r3, [r4, #86] @ movhi +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3738 .loc 1 1953 5 is_stmt 1 view .LVU1161 +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3739 .loc 1 1953 24 is_stmt 0 view .LVU1162 + 3740 009c A4F85E30 strh r3, [r4, #94] @ movhi +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + 3741 .loc 1 1956 5 is_stmt 1 view .LVU1163 +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + 3742 .loc 1 1956 18 is_stmt 0 view .LVU1164 + 3743 00a0 E366 str r3, [r4, #108] +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3744 .loc 1 1957 5 is_stmt 1 view .LVU1165 +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3745 .loc 1 1957 18 is_stmt 0 view .LVU1166 + 3746 00a2 2367 str r3, [r4, #112] +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3747 .loc 1 1960 5 is_stmt 1 view .LVU1167 +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3748 .loc 1 1960 22 is_stmt 0 view .LVU1168 + 3749 00a4 C4F88830 str r3, [r4, #136] +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3750 .loc 1 1963 5 is_stmt 1 view .LVU1169 + 3751 00a8 2368 ldr r3, [r4] + 3752 00aa 0F22 movs r2, #15 + 3753 00ac 1A62 str r2, [r3, #32] +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3754 .loc 1 1966 5 view .LVU1170 +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3755 .loc 1 1966 14 is_stmt 0 view .LVU1171 + 3756 00ae 636E ldr r3, [r4, #100] + ARM GAS /tmp/ccizsdzp.s page 156 + + +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3757 .loc 1 1966 8 view .LVU1172 + 3758 00b0 B3F1005F cmp r3, #536870912 + 3759 00b4 15D0 beq .L261 + 3760 .L256: +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3761 .loc 1 1972 5 is_stmt 1 view .LVU1173 + 3762 00b6 2268 ldr r2, [r4] + 3763 00b8 9369 ldr r3, [r2, #24] + 3764 00ba 43F00803 orr r3, r3, #8 + 3765 00be 9361 str r3, [r2, #24] +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3766 .loc 1 1975 5 view .LVU1174 +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3767 .loc 1 1975 20 is_stmt 0 view .LVU1175 + 3768 00c0 2023 movs r3, #32 + 3769 00c2 C4F88030 str r3, [r4, #128] +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3770 .loc 1 1976 5 is_stmt 1 view .LVU1176 +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3771 .loc 1 1976 20 is_stmt 0 view .LVU1177 + 3772 00c6 C4F88430 str r3, [r4, #132] +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3773 .loc 1 1984 5 is_stmt 1 view .LVU1178 + 3774 00ca 2046 mov r0, r4 + 3775 00cc FFF7FEFF bl HAL_UART_AbortCpltCallback + 3776 .LVL256: + 3777 00d0 05E0 b .L254 + 3778 .LVL257: + 3779 .L258: +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3780 .loc 1 1863 12 is_stmt 0 view .LVU1179 + 3781 00d2 0121 movs r1, #1 + 3782 00d4 CEE7 b .L252 + 3783 .L259: +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3784 .loc 1 1919 19 view .LVU1180 + 3785 00d6 0021 movs r1, #0 + 3786 00d8 CCE7 b .L252 + 3787 .LVL258: + 3788 .L253: +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3789 .loc 1 1949 3 is_stmt 1 view .LVU1181 +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3790 .loc 1 1949 6 is_stmt 0 view .LVU1182 + 3791 00da 0029 cmp r1, #0 + 3792 00dc DBD1 bne .L255 + 3793 .LVL259: + 3794 .L254: +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3795 .loc 1 1988 3 is_stmt 1 view .LVU1183 +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3796 .loc 1 1989 1 is_stmt 0 view .LVU1184 + 3797 00de 0020 movs r0, #0 + 3798 00e0 10BD pop {r4, pc} + 3799 .LVL260: + 3800 .L261: + ARM GAS /tmp/ccizsdzp.s page 157 + + +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3801 .loc 1 1968 7 is_stmt 1 view .LVU1185 + 3802 00e2 2268 ldr r2, [r4] + 3803 00e4 9369 ldr r3, [r2, #24] + 3804 00e6 43F01003 orr r3, r3, #16 + 3805 00ea 9361 str r3, [r2, #24] + 3806 00ec E3E7 b .L256 + 3807 .L263: + 3808 00ee 00BF .align 2 + 3809 .L262: + 3810 00f0 FEFF7FEF .word -276824066 + 3811 00f4 00000000 .word UART_DMATxAbortCallback + 3812 00f8 00000000 .word UART_DMARxAbortCallback + 3813 .cfi_endproc + 3814 .LFE160: + 3816 .section .text.UART_DMARxAbortCallback,"ax",%progbits + 3817 .align 1 + 3818 .syntax unified + 3819 .thumb + 3820 .thumb_func + 3821 .fpu fpv5-d16 + 3823 UART_DMARxAbortCallback: + 3824 .LVL261: + 3825 .LFB196: +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3826 .loc 1 3558 1 view -0 + 3827 .cfi_startproc + 3828 @ args = 0, pretend = 0, frame = 0 + 3829 @ frame_needed = 0, uses_anonymous_args = 0 +3558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3830 .loc 1 3558 1 is_stmt 0 view .LVU1187 + 3831 0000 08B5 push {r3, lr} + 3832 .LCFI28: + 3833 .cfi_def_cfa_offset 8 + 3834 .cfi_offset 3, -8 + 3835 .cfi_offset 14, -4 +3559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3836 .loc 1 3559 3 is_stmt 1 view .LVU1188 +3559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3837 .loc 1 3559 23 is_stmt 0 view .LVU1189 + 3838 0002 806B ldr r0, [r0, #56] + 3839 .LVL262: +3561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3840 .loc 1 3561 3 is_stmt 1 view .LVU1190 +3561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3841 .loc 1 3561 8 is_stmt 0 view .LVU1191 + 3842 0004 836F ldr r3, [r0, #120] +3561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3843 .loc 1 3561 36 view .LVU1192 + 3844 0006 0022 movs r2, #0 + 3845 0008 1A65 str r2, [r3, #80] +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3846 .loc 1 3564 3 is_stmt 1 view .LVU1193 +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3847 .loc 1 3564 12 is_stmt 0 view .LVU1194 + 3848 000a 436F ldr r3, [r0, #116] +3564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 158 + + + 3849 .loc 1 3564 6 view .LVU1195 + 3850 000c 0BB1 cbz r3, .L265 +3566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3851 .loc 1 3566 5 is_stmt 1 view .LVU1196 +3566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3852 .loc 1 3566 22 is_stmt 0 view .LVU1197 + 3853 000e 1B6D ldr r3, [r3, #80] +3566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3854 .loc 1 3566 8 view .LVU1198 + 3855 0010 ABB9 cbnz r3, .L264 + 3856 .L265: +3573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3857 .loc 1 3573 3 is_stmt 1 view .LVU1199 +3573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3858 .loc 1 3573 22 is_stmt 0 view .LVU1200 + 3859 0012 0023 movs r3, #0 + 3860 0014 A0F85630 strh r3, [r0, #86] @ movhi +3574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3861 .loc 1 3574 3 is_stmt 1 view .LVU1201 +3574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3862 .loc 1 3574 22 is_stmt 0 view .LVU1202 + 3863 0018 A0F85E30 strh r3, [r0, #94] @ movhi +3577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3864 .loc 1 3577 3 is_stmt 1 view .LVU1203 +3577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3865 .loc 1 3577 20 is_stmt 0 view .LVU1204 + 3866 001c C0F88830 str r3, [r0, #136] +3580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3867 .loc 1 3580 3 is_stmt 1 view .LVU1205 + 3868 0020 0368 ldr r3, [r0] + 3869 0022 0F22 movs r2, #15 + 3870 0024 1A62 str r2, [r3, #32] +3583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3871 .loc 1 3583 3 view .LVU1206 + 3872 0026 0268 ldr r2, [r0] + 3873 0028 9369 ldr r3, [r2, #24] + 3874 002a 43F00803 orr r3, r3, #8 + 3875 002e 9361 str r3, [r2, #24] +3586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3876 .loc 1 3586 3 view .LVU1207 +3586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3877 .loc 1 3586 18 is_stmt 0 view .LVU1208 + 3878 0030 2023 movs r3, #32 + 3879 0032 C0F88030 str r3, [r0, #128] +3587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3880 .loc 1 3587 3 is_stmt 1 view .LVU1209 +3587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3881 .loc 1 3587 18 is_stmt 0 view .LVU1210 + 3882 0036 C0F88430 str r3, [r0, #132] +3595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3883 .loc 1 3595 3 is_stmt 1 view .LVU1211 + 3884 003a FFF7FEFF bl HAL_UART_AbortCpltCallback + 3885 .LVL263: + 3886 .L264: +3597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3887 .loc 1 3597 1 is_stmt 0 view .LVU1212 + 3888 003e 08BD pop {r3, pc} + ARM GAS /tmp/ccizsdzp.s page 159 + + + 3889 .cfi_endproc + 3890 .LFE196: + 3892 .section .text.UART_DMATxAbortCallback,"ax",%progbits + 3893 .align 1 + 3894 .syntax unified + 3895 .thumb + 3896 .thumb_func + 3897 .fpu fpv5-d16 + 3899 UART_DMATxAbortCallback: + 3900 .LVL264: + 3901 .LFB195: +3504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3902 .loc 1 3504 1 is_stmt 1 view -0 + 3903 .cfi_startproc + 3904 @ args = 0, pretend = 0, frame = 0 + 3905 @ frame_needed = 0, uses_anonymous_args = 0 +3504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3906 .loc 1 3504 1 is_stmt 0 view .LVU1214 + 3907 0000 08B5 push {r3, lr} + 3908 .LCFI29: + 3909 .cfi_def_cfa_offset 8 + 3910 .cfi_offset 3, -8 + 3911 .cfi_offset 14, -4 +3505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3912 .loc 1 3505 3 is_stmt 1 view .LVU1215 +3505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3913 .loc 1 3505 23 is_stmt 0 view .LVU1216 + 3914 0002 806B ldr r0, [r0, #56] + 3915 .LVL265: +3507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3916 .loc 1 3507 3 is_stmt 1 view .LVU1217 +3507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3917 .loc 1 3507 8 is_stmt 0 view .LVU1218 + 3918 0004 436F ldr r3, [r0, #116] +3507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3919 .loc 1 3507 36 view .LVU1219 + 3920 0006 0022 movs r2, #0 + 3921 0008 1A65 str r2, [r3, #80] +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3922 .loc 1 3510 3 is_stmt 1 view .LVU1220 +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3923 .loc 1 3510 12 is_stmt 0 view .LVU1221 + 3924 000a 836F ldr r3, [r0, #120] +3510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3925 .loc 1 3510 6 view .LVU1222 + 3926 000c 0BB1 cbz r3, .L269 +3512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3927 .loc 1 3512 5 is_stmt 1 view .LVU1223 +3512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3928 .loc 1 3512 22 is_stmt 0 view .LVU1224 + 3929 000e 1B6D ldr r3, [r3, #80] +3512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3930 .loc 1 3512 8 view .LVU1225 + 3931 0010 A3B9 cbnz r3, .L268 + 3932 .L269: +3519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3933 .loc 1 3519 3 is_stmt 1 view .LVU1226 + ARM GAS /tmp/ccizsdzp.s page 160 + + +3519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3934 .loc 1 3519 22 is_stmt 0 view .LVU1227 + 3935 0012 0023 movs r3, #0 + 3936 0014 A0F85630 strh r3, [r0, #86] @ movhi +3520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3937 .loc 1 3520 3 is_stmt 1 view .LVU1228 +3520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3938 .loc 1 3520 22 is_stmt 0 view .LVU1229 + 3939 0018 A0F85E30 strh r3, [r0, #94] @ movhi +3523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3940 .loc 1 3523 3 is_stmt 1 view .LVU1230 +3523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3941 .loc 1 3523 20 is_stmt 0 view .LVU1231 + 3942 001c C0F88830 str r3, [r0, #136] +3526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3943 .loc 1 3526 3 is_stmt 1 view .LVU1232 + 3944 0020 0368 ldr r3, [r0] + 3945 0022 0F22 movs r2, #15 + 3946 0024 1A62 str r2, [r3, #32] +3529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3947 .loc 1 3529 3 view .LVU1233 +3529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3948 .loc 1 3529 12 is_stmt 0 view .LVU1234 + 3949 0026 436E ldr r3, [r0, #100] +3529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 3950 .loc 1 3529 6 view .LVU1235 + 3951 0028 B3F1005F cmp r3, #536870912 + 3952 002c 07D0 beq .L273 + 3953 .L271: +3535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3954 .loc 1 3535 3 is_stmt 1 view .LVU1236 +3535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3955 .loc 1 3535 18 is_stmt 0 view .LVU1237 + 3956 002e 2023 movs r3, #32 + 3957 0030 C0F88030 str r3, [r0, #128] +3536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3958 .loc 1 3536 3 is_stmt 1 view .LVU1238 +3536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3959 .loc 1 3536 18 is_stmt 0 view .LVU1239 + 3960 0034 C0F88430 str r3, [r0, #132] +3544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3961 .loc 1 3544 3 is_stmt 1 view .LVU1240 + 3962 0038 FFF7FEFF bl HAL_UART_AbortCpltCallback + 3963 .LVL266: + 3964 .L268: +3546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3965 .loc 1 3546 1 is_stmt 0 view .LVU1241 + 3966 003c 08BD pop {r3, pc} + 3967 .LVL267: + 3968 .L273: +3531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 3969 .loc 1 3531 5 is_stmt 1 view .LVU1242 + 3970 003e 0268 ldr r2, [r0] + 3971 0040 9369 ldr r3, [r2, #24] + 3972 0042 43F01003 orr r3, r3, #16 + 3973 0046 9361 str r3, [r2, #24] + 3974 0048 F1E7 b .L271 + ARM GAS /tmp/ccizsdzp.s page 161 + + + 3975 .cfi_endproc + 3976 .LFE195: + 3978 .section .text.HAL_UART_AbortTransmitCpltCallback,"ax",%progbits + 3979 .align 1 + 3980 .weak HAL_UART_AbortTransmitCpltCallback + 3981 .syntax unified + 3982 .thumb + 3983 .thumb_func + 3984 .fpu fpv5-d16 + 3986 HAL_UART_AbortTransmitCpltCallback: + 3987 .LVL268: + 3988 .LFB170: +2502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3989 .loc 1 2502 1 view -0 + 3990 .cfi_startproc + 3991 @ args = 0, pretend = 0, frame = 0 + 3992 @ frame_needed = 0, uses_anonymous_args = 0 + 3993 @ link register save eliminated. +2504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3994 .loc 1 2504 3 view .LVU1244 +2509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 3995 .loc 1 2509 1 is_stmt 0 view .LVU1245 + 3996 0000 7047 bx lr + 3997 .cfi_endproc + 3998 .LFE170: + 4000 .section .text.HAL_UART_AbortTransmit_IT,"ax",%progbits + 4001 .align 1 + 4002 .global HAL_UART_AbortTransmit_IT + 4003 .syntax unified + 4004 .thumb + 4005 .thumb_func + 4006 .fpu fpv5-d16 + 4008 HAL_UART_AbortTransmit_IT: + 4009 .LVL269: + 4010 .LFB161: +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable interrupts */ + 4011 .loc 1 2006 1 is_stmt 1 view -0 + 4012 .cfi_startproc + 4013 @ args = 0, pretend = 0, frame = 0 + 4014 @ frame_needed = 0, uses_anonymous_args = 0 +2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable interrupts */ + 4015 .loc 1 2006 1 is_stmt 0 view .LVU1247 + 4016 0000 10B5 push {r4, lr} + 4017 .LCFI30: + 4018 .cfi_def_cfa_offset 8 + 4019 .cfi_offset 4, -8 + 4020 .cfi_offset 14, -4 + 4021 0002 0446 mov r4, r0 +2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + 4022 .loc 1 2008 3 is_stmt 1 view .LVU1248 + 4023 0004 0268 ldr r2, [r0] + 4024 0006 1368 ldr r3, [r2] + 4025 0008 23F0C003 bic r3, r3, #192 + 4026 000c 1360 str r3, [r2] +2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4027 .loc 1 2009 3 view .LVU1249 + 4028 000e 0268 ldr r2, [r0] + ARM GAS /tmp/ccizsdzp.s page 162 + + + 4029 0010 9368 ldr r3, [r2, #8] + 4030 0012 23F40003 bic r3, r3, #8388608 + 4031 0016 9360 str r3, [r2, #8] +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4032 .loc 1 2012 3 view .LVU1250 +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4033 .loc 1 2012 7 is_stmt 0 view .LVU1251 + 4034 0018 0368 ldr r3, [r0] + 4035 001a 9A68 ldr r2, [r3, #8] +2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4036 .loc 1 2012 6 view .LVU1252 + 4037 001c 12F0800F tst r2, #128 + 4038 0020 19D0 beq .L276 +2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4039 .loc 1 2014 5 is_stmt 1 view .LVU1253 + 4040 0022 9A68 ldr r2, [r3, #8] + 4041 0024 22F08002 bic r2, r2, #128 + 4042 0028 9A60 str r2, [r3, #8] +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4043 .loc 1 2017 5 view .LVU1254 +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4044 .loc 1 2017 14 is_stmt 0 view .LVU1255 + 4045 002a 436F ldr r3, [r0, #116] +2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4046 .loc 1 2017 8 view .LVU1256 + 4047 002c 4BB1 cbz r3, .L277 +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4048 .loc 1 2021 7 is_stmt 1 view .LVU1257 +2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4049 .loc 1 2021 40 is_stmt 0 view .LVU1258 + 4050 002e 144A ldr r2, .L282 + 4051 0030 1A65 str r2, [r3, #80] +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4052 .loc 1 2024 7 is_stmt 1 view .LVU1259 +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4053 .loc 1 2024 11 is_stmt 0 view .LVU1260 + 4054 0032 406F ldr r0, [r0, #116] + 4055 .LVL270: +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4056 .loc 1 2024 11 view .LVU1261 + 4057 0034 FFF7FEFF bl HAL_DMA_Abort_IT + 4058 .LVL271: +2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4059 .loc 1 2024 10 view .LVU1262 + 4060 0038 D8B1 cbz r0, .L278 +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4061 .loc 1 2027 9 is_stmt 1 view .LVU1263 +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4062 .loc 1 2027 14 is_stmt 0 view .LVU1264 + 4063 003a 606F ldr r0, [r4, #116] +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4064 .loc 1 2027 22 view .LVU1265 + 4065 003c 036D ldr r3, [r0, #80] +2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4066 .loc 1 2027 9 view .LVU1266 + 4067 003e 9847 blx r3 + 4068 .LVL272: + ARM GAS /tmp/ccizsdzp.s page 163 + + + 4069 0040 17E0 b .L278 + 4070 .LVL273: + 4071 .L277: +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4072 .loc 1 2033 7 is_stmt 1 view .LVU1267 +2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4073 .loc 1 2033 26 is_stmt 0 view .LVU1268 + 4074 0042 0023 movs r3, #0 + 4075 0044 A0F85630 strh r3, [r0, #86] @ movhi +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4076 .loc 1 2036 7 is_stmt 1 view .LVU1269 +2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4077 .loc 1 2036 20 is_stmt 0 view .LVU1270 + 4078 0048 0367 str r3, [r0, #112] +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4079 .loc 1 2039 7 is_stmt 1 view .LVU1271 +2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4080 .loc 1 2039 21 is_stmt 0 view .LVU1272 + 4081 004a 2023 movs r3, #32 + 4082 004c C0F88030 str r3, [r0, #128] +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4083 .loc 1 2047 7 is_stmt 1 view .LVU1273 + 4084 0050 FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 4085 .LVL274: +2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4086 .loc 1 2047 7 is_stmt 0 view .LVU1274 + 4087 0054 0DE0 b .L278 + 4088 .LVL275: + 4089 .L276: +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4090 .loc 1 2054 5 is_stmt 1 view .LVU1275 +2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4091 .loc 1 2054 24 is_stmt 0 view .LVU1276 + 4092 0056 0022 movs r2, #0 + 4093 0058 A0F85620 strh r2, [r0, #86] @ movhi +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4094 .loc 1 2057 5 is_stmt 1 view .LVU1277 +2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4095 .loc 1 2057 18 is_stmt 0 view .LVU1278 + 4096 005c 0267 str r2, [r0, #112] +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4097 .loc 1 2060 5 is_stmt 1 view .LVU1279 +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4098 .loc 1 2060 14 is_stmt 0 view .LVU1280 + 4099 005e 426E ldr r2, [r0, #100] +2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4100 .loc 1 2060 8 view .LVU1281 + 4101 0060 B2F1005F cmp r2, #536870912 + 4102 0064 07D0 beq .L281 + 4103 .L279: +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4104 .loc 1 2066 5 is_stmt 1 view .LVU1282 +2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4105 .loc 1 2066 19 is_stmt 0 view .LVU1283 + 4106 0066 2023 movs r3, #32 + 4107 0068 C4F88030 str r3, [r4, #128] +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccizsdzp.s page 164 + + + 4108 .loc 1 2074 5 is_stmt 1 view .LVU1284 + 4109 006c 2046 mov r0, r4 + 4110 .LVL276: +2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4111 .loc 1 2074 5 is_stmt 0 view .LVU1285 + 4112 006e FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 4113 .LVL277: + 4114 .L278: +2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4115 .loc 1 2078 3 is_stmt 1 view .LVU1286 +2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4116 .loc 1 2079 1 is_stmt 0 view .LVU1287 + 4117 0072 0020 movs r0, #0 + 4118 0074 10BD pop {r4, pc} + 4119 .LVL278: + 4120 .L281: +2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4121 .loc 1 2062 7 is_stmt 1 view .LVU1288 + 4122 0076 9A69 ldr r2, [r3, #24] + 4123 0078 42F01002 orr r2, r2, #16 + 4124 007c 9A61 str r2, [r3, #24] + 4125 007e F2E7 b .L279 + 4126 .L283: + 4127 .align 2 + 4128 .L282: + 4129 0080 00000000 .word UART_DMATxOnlyAbortCallback + 4130 .cfi_endproc + 4131 .LFE161: + 4133 .section .text.UART_DMATxOnlyAbortCallback,"ax",%progbits + 4134 .align 1 + 4135 .syntax unified + 4136 .thumb + 4137 .thumb_func + 4138 .fpu fpv5-d16 + 4140 UART_DMATxOnlyAbortCallback: + 4141 .LVL279: + 4142 .LFB197: +3609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 4143 .loc 1 3609 1 view -0 + 4144 .cfi_startproc + 4145 @ args = 0, pretend = 0, frame = 0 + 4146 @ frame_needed = 0, uses_anonymous_args = 0 +3609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 4147 .loc 1 3609 1 is_stmt 0 view .LVU1290 + 4148 0000 08B5 push {r3, lr} + 4149 .LCFI31: + 4150 .cfi_def_cfa_offset 8 + 4151 .cfi_offset 3, -8 + 4152 .cfi_offset 14, -4 +3610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4153 .loc 1 3610 3 is_stmt 1 view .LVU1291 +3610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4154 .loc 1 3610 23 is_stmt 0 view .LVU1292 + 4155 0002 806B ldr r0, [r0, #56] + 4156 .LVL280: +3612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4157 .loc 1 3612 3 is_stmt 1 view .LVU1293 + ARM GAS /tmp/ccizsdzp.s page 165 + + +3612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4158 .loc 1 3612 22 is_stmt 0 view .LVU1294 + 4159 0004 0023 movs r3, #0 + 4160 0006 A0F85630 strh r3, [r0, #86] @ movhi +3615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4161 .loc 1 3615 3 is_stmt 1 view .LVU1295 +3615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4162 .loc 1 3615 12 is_stmt 0 view .LVU1296 + 4163 000a 436E ldr r3, [r0, #100] +3615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4164 .loc 1 3615 6 view .LVU1297 + 4165 000c B3F1005F cmp r3, #536870912 + 4166 0010 05D0 beq .L287 + 4167 .L285: +3621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4168 .loc 1 3621 3 is_stmt 1 view .LVU1298 +3621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4169 .loc 1 3621 17 is_stmt 0 view .LVU1299 + 4170 0012 2023 movs r3, #32 + 4171 0014 C0F88030 str r3, [r0, #128] +3629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4172 .loc 1 3629 3 is_stmt 1 view .LVU1300 + 4173 0018 FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 4174 .LVL281: +3631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4175 .loc 1 3631 1 is_stmt 0 view .LVU1301 + 4176 001c 08BD pop {r3, pc} + 4177 .LVL282: + 4178 .L287: +3617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4179 .loc 1 3617 5 is_stmt 1 view .LVU1302 + 4180 001e 0268 ldr r2, [r0] + 4181 0020 9369 ldr r3, [r2, #24] + 4182 0022 43F01003 orr r3, r3, #16 + 4183 0026 9361 str r3, [r2, #24] + 4184 0028 F3E7 b .L285 + 4185 .cfi_endproc + 4186 .LFE197: + 4188 .section .text.HAL_UART_AbortReceiveCpltCallback,"ax",%progbits + 4189 .align 1 + 4190 .weak HAL_UART_AbortReceiveCpltCallback + 4191 .syntax unified + 4192 .thumb + 4193 .thumb_func + 4194 .fpu fpv5-d16 + 4196 HAL_UART_AbortReceiveCpltCallback: + 4197 .LVL283: + 4198 .LFB171: +2517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 4199 .loc 1 2517 1 view -0 + 4200 .cfi_startproc + 4201 @ args = 0, pretend = 0, frame = 0 + 4202 @ frame_needed = 0, uses_anonymous_args = 0 + 4203 @ link register save eliminated. +2519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4204 .loc 1 2519 3 view .LVU1304 +2524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 166 + + + 4205 .loc 1 2524 1 is_stmt 0 view .LVU1305 + 4206 0000 7047 bx lr + 4207 .cfi_endproc + 4208 .LFE171: + 4210 .section .text.HAL_UART_AbortReceive_IT,"ax",%progbits + 4211 .align 1 + 4212 .global HAL_UART_AbortReceive_IT + 4213 .syntax unified + 4214 .thumb + 4215 .thumb_func + 4216 .fpu fpv5-d16 + 4218 HAL_UART_AbortReceive_IT: + 4219 .LVL284: + 4220 .LFB162: +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 4221 .loc 1 2096 1 is_stmt 1 view -0 + 4222 .cfi_startproc + 4223 @ args = 0, pretend = 0, frame = 0 + 4224 @ frame_needed = 0, uses_anonymous_args = 0 +2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 4225 .loc 1 2096 1 is_stmt 0 view .LVU1307 + 4226 0000 10B5 push {r4, lr} + 4227 .LCFI32: + 4228 .cfi_def_cfa_offset 8 + 4229 .cfi_offset 4, -8 + 4230 .cfi_offset 14, -4 + 4231 0002 0446 mov r4, r0 +2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 4232 .loc 1 2098 3 is_stmt 1 view .LVU1308 + 4233 0004 0268 ldr r2, [r0] + 4234 0006 1368 ldr r3, [r2] + 4235 0008 23F49073 bic r3, r3, #288 + 4236 000c 1360 str r3, [r2] +2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4237 .loc 1 2099 3 view .LVU1309 + 4238 000e 0268 ldr r2, [r0] + 4239 0010 9168 ldr r1, [r2, #8] + 4240 0012 1B4B ldr r3, .L294 + 4241 0014 0B40 ands r3, r3, r1 + 4242 0016 9360 str r3, [r2, #8] +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4243 .loc 1 2102 3 view .LVU1310 +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4244 .loc 1 2102 7 is_stmt 0 view .LVU1311 + 4245 0018 0368 ldr r3, [r0] + 4246 001a 9A68 ldr r2, [r3, #8] +2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4247 .loc 1 2102 6 view .LVU1312 + 4248 001c 12F0400F tst r2, #64 + 4249 0020 21D0 beq .L290 +2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4250 .loc 1 2104 5 is_stmt 1 view .LVU1313 + 4251 0022 9A68 ldr r2, [r3, #8] + 4252 0024 22F04002 bic r2, r2, #64 + 4253 0028 9A60 str r2, [r3, #8] +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4254 .loc 1 2107 5 view .LVU1314 + ARM GAS /tmp/ccizsdzp.s page 167 + + +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4255 .loc 1 2107 14 is_stmt 0 view .LVU1315 + 4256 002a 836F ldr r3, [r0, #120] +2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4257 .loc 1 2107 8 view .LVU1316 + 4258 002c 4BB1 cbz r3, .L291 +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4259 .loc 1 2111 7 is_stmt 1 view .LVU1317 +2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4260 .loc 1 2111 40 is_stmt 0 view .LVU1318 + 4261 002e 154A ldr r2, .L294+4 + 4262 0030 1A65 str r2, [r3, #80] +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4263 .loc 1 2114 7 is_stmt 1 view .LVU1319 +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4264 .loc 1 2114 11 is_stmt 0 view .LVU1320 + 4265 0032 806F ldr r0, [r0, #120] + 4266 .LVL285: +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4267 .loc 1 2114 11 view .LVU1321 + 4268 0034 FFF7FEFF bl HAL_DMA_Abort_IT + 4269 .LVL286: +2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4270 .loc 1 2114 10 view .LVU1322 + 4271 0038 00B3 cbz r0, .L292 +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4272 .loc 1 2117 9 is_stmt 1 view .LVU1323 +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4273 .loc 1 2117 14 is_stmt 0 view .LVU1324 + 4274 003a A06F ldr r0, [r4, #120] +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4275 .loc 1 2117 22 view .LVU1325 + 4276 003c 036D ldr r3, [r0, #80] +2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4277 .loc 1 2117 9 view .LVU1326 + 4278 003e 9847 blx r3 + 4279 .LVL287: + 4280 0040 1CE0 b .L292 + 4281 .LVL288: + 4282 .L291: +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4283 .loc 1 2123 7 is_stmt 1 view .LVU1327 +2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4284 .loc 1 2123 26 is_stmt 0 view .LVU1328 + 4285 0042 0023 movs r3, #0 + 4286 0044 A0F85E30 strh r3, [r0, #94] @ movhi +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4287 .loc 1 2126 7 is_stmt 1 view .LVU1329 +2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4288 .loc 1 2126 25 is_stmt 0 view .LVU1330 + 4289 0048 8365 str r3, [r0, #88] +2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4290 .loc 1 2129 7 is_stmt 1 view .LVU1331 + 4291 004a 0368 ldr r3, [r0] + 4292 004c 0F22 movs r2, #15 + 4293 004e 1A62 str r2, [r3, #32] +2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 168 + + + 4294 .loc 1 2132 7 view .LVU1332 + 4295 0050 0268 ldr r2, [r0] + 4296 0052 9369 ldr r3, [r2, #24] + 4297 0054 43F00803 orr r3, r3, #8 + 4298 0058 9361 str r3, [r2, #24] +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4299 .loc 1 2135 7 view .LVU1333 +2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4300 .loc 1 2135 22 is_stmt 0 view .LVU1334 + 4301 005a 2023 movs r3, #32 + 4302 005c C0F88430 str r3, [r0, #132] +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4303 .loc 1 2143 7 is_stmt 1 view .LVU1335 + 4304 0060 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 4305 .LVL289: +2143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4306 .loc 1 2143 7 is_stmt 0 view .LVU1336 + 4307 0064 0AE0 b .L292 + 4308 .LVL290: + 4309 .L290: +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4310 .loc 1 2150 5 is_stmt 1 view .LVU1337 +2150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4311 .loc 1 2150 24 is_stmt 0 view .LVU1338 + 4312 0066 0022 movs r2, #0 + 4313 0068 A0F85E20 strh r2, [r0, #94] @ movhi +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4314 .loc 1 2153 5 is_stmt 1 view .LVU1339 +2153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4315 .loc 1 2153 23 is_stmt 0 view .LVU1340 + 4316 006c 8265 str r2, [r0, #88] +2156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4317 .loc 1 2156 5 is_stmt 1 view .LVU1341 + 4318 006e 0F22 movs r2, #15 + 4319 0070 1A62 str r2, [r3, #32] +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4320 .loc 1 2159 5 view .LVU1342 +2159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4321 .loc 1 2159 20 is_stmt 0 view .LVU1343 + 4322 0072 2023 movs r3, #32 + 4323 0074 C0F88430 str r3, [r0, #132] +2167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4324 .loc 1 2167 5 is_stmt 1 view .LVU1344 + 4325 0078 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 4326 .LVL291: + 4327 .L292: +2171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4328 .loc 1 2171 3 view .LVU1345 +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4329 .loc 1 2172 1 is_stmt 0 view .LVU1346 + 4330 007c 0020 movs r0, #0 + 4331 007e 10BD pop {r4, pc} + 4332 .LVL292: + 4333 .L295: +2172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4334 .loc 1 2172 1 view .LVU1347 + 4335 .align 2 + ARM GAS /tmp/ccizsdzp.s page 169 + + + 4336 .L294: + 4337 0080 FEFFFFEF .word -268435458 + 4338 0084 00000000 .word UART_DMARxOnlyAbortCallback + 4339 .cfi_endproc + 4340 .LFE162: + 4342 .section .text.UART_DMARxOnlyAbortCallback,"ax",%progbits + 4343 .align 1 + 4344 .syntax unified + 4345 .thumb + 4346 .thumb_func + 4347 .fpu fpv5-d16 + 4349 UART_DMARxOnlyAbortCallback: + 4350 .LVL293: + 4351 .LFB198: +3642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4352 .loc 1 3642 1 is_stmt 1 view -0 + 4353 .cfi_startproc + 4354 @ args = 0, pretend = 0, frame = 0 + 4355 @ frame_needed = 0, uses_anonymous_args = 0 +3642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4356 .loc 1 3642 1 is_stmt 0 view .LVU1349 + 4357 0000 08B5 push {r3, lr} + 4358 .LCFI33: + 4359 .cfi_def_cfa_offset 8 + 4360 .cfi_offset 3, -8 + 4361 .cfi_offset 14, -4 +3643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4362 .loc 1 3643 3 is_stmt 1 view .LVU1350 +3643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4363 .loc 1 3643 23 is_stmt 0 view .LVU1351 + 4364 0002 806B ldr r0, [r0, #56] + 4365 .LVL294: +3645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4366 .loc 1 3645 3 is_stmt 1 view .LVU1352 +3645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4367 .loc 1 3645 22 is_stmt 0 view .LVU1353 + 4368 0004 0023 movs r3, #0 + 4369 0006 A0F85E30 strh r3, [r0, #94] @ movhi +3648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4370 .loc 1 3648 3 is_stmt 1 view .LVU1354 + 4371 000a 0368 ldr r3, [r0] + 4372 000c 0F22 movs r2, #15 + 4373 000e 1A62 str r2, [r3, #32] +3651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4374 .loc 1 3651 3 view .LVU1355 + 4375 0010 0268 ldr r2, [r0] + 4376 0012 9369 ldr r3, [r2, #24] + 4377 0014 43F00803 orr r3, r3, #8 + 4378 0018 9361 str r3, [r2, #24] +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4379 .loc 1 3654 3 view .LVU1356 +3654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4380 .loc 1 3654 18 is_stmt 0 view .LVU1357 + 4381 001a 2023 movs r3, #32 + 4382 001c C0F88430 str r3, [r0, #132] +3662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4383 .loc 1 3662 3 is_stmt 1 view .LVU1358 + ARM GAS /tmp/ccizsdzp.s page 170 + + + 4384 0020 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 4385 .LVL295: +3664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4386 .loc 1 3664 1 is_stmt 0 view .LVU1359 + 4387 0024 08BD pop {r3, pc} + 4388 .cfi_endproc + 4389 .LFE198: + 4391 .section .text.HAL_UART_ReceiverTimeout_Config,"ax",%progbits + 4392 .align 1 + 4393 .global HAL_UART_ReceiverTimeout_Config + 4394 .syntax unified + 4395 .thumb + 4396 .thumb_func + 4397 .fpu fpv5-d16 + 4399 HAL_UART_ReceiverTimeout_Config: + 4400 .LVL296: + 4401 .LFB172: +2564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(IS_LPUART_INSTANCE(huart->Instance))) + 4402 .loc 1 2564 1 is_stmt 1 view -0 + 4403 .cfi_startproc + 4404 @ args = 0, pretend = 0, frame = 0 + 4405 @ frame_needed = 0, uses_anonymous_args = 0 + 4406 @ link register save eliminated. +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4407 .loc 1 2565 3 view .LVU1361 +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4408 .loc 1 2565 9 is_stmt 0 view .LVU1362 + 4409 0000 0268 ldr r2, [r0] +2565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4410 .loc 1 2565 6 view .LVU1363 + 4411 0002 044B ldr r3, .L300 + 4412 0004 9A42 cmp r2, r3 + 4413 0006 04D0 beq .L298 +2567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + 4414 .loc 1 2567 5 is_stmt 1 view .LVU1364 +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4415 .loc 1 2568 5 view .LVU1365 + 4416 0008 5369 ldr r3, [r2, #20] + 4417 000a 03F07F43 and r3, r3, #-16777216 + 4418 000e 1943 orrs r1, r1, r3 + 4419 .LVL297: +2568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4420 .loc 1 2568 5 is_stmt 0 view .LVU1366 + 4421 0010 5161 str r1, [r2, #20] + 4422 .L298: +2570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4423 .loc 1 2570 1 view .LVU1367 + 4424 0012 7047 bx lr + 4425 .L301: + 4426 .align 2 + 4427 .L300: + 4428 0014 000C0058 .word 1476398080 + 4429 .cfi_endproc + 4430 .LFE172: + 4432 .section .text.HAL_UART_EnableReceiverTimeout,"ax",%progbits + 4433 .align 1 + 4434 .global HAL_UART_EnableReceiverTimeout + ARM GAS /tmp/ccizsdzp.s page 171 + + + 4435 .syntax unified + 4436 .thumb + 4437 .thumb_func + 4438 .fpu fpv5-d16 + 4440 HAL_UART_EnableReceiverTimeout: + 4441 .LVL298: + 4442 .LFB173: +2579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(IS_LPUART_INSTANCE(huart->Instance))) + 4443 .loc 1 2579 1 is_stmt 1 view -0 + 4444 .cfi_startproc + 4445 @ args = 0, pretend = 0, frame = 0 + 4446 @ frame_needed = 0, uses_anonymous_args = 0 + 4447 @ link register save eliminated. +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4448 .loc 1 2580 3 view .LVU1369 +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4449 .loc 1 2580 9 is_stmt 0 view .LVU1370 + 4450 0000 0368 ldr r3, [r0] +2580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4451 .loc 1 2580 6 view .LVU1371 + 4452 0002 114A ldr r2, .L307 + 4453 0004 9342 cmp r3, r2 + 4454 0006 19D0 beq .L304 +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4455 .loc 1 2582 5 is_stmt 1 view .LVU1372 +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4456 .loc 1 2582 14 is_stmt 0 view .LVU1373 + 4457 0008 D0F88020 ldr r2, [r0, #128] +2582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4458 .loc 1 2582 8 view .LVU1374 + 4459 000c 202A cmp r2, #32 + 4460 000e 17D1 bne .L305 +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4461 .loc 1 2585 7 is_stmt 1 view .LVU1375 +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4462 .loc 1 2585 7 view .LVU1376 + 4463 0010 90F87C20 ldrb r2, [r0, #124] @ zero_extendqisi2 + 4464 0014 012A cmp r2, #1 + 4465 0016 15D0 beq .L306 +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4466 .loc 1 2585 7 discriminator 2 view .LVU1377 + 4467 0018 0122 movs r2, #1 + 4468 001a 80F87C20 strb r2, [r0, #124] +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4469 .loc 1 2585 7 discriminator 2 view .LVU1378 +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4470 .loc 1 2587 7 discriminator 2 view .LVU1379 +2587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4471 .loc 1 2587 21 is_stmt 0 discriminator 2 view .LVU1380 + 4472 001e 2422 movs r2, #36 + 4473 0020 C0F88020 str r2, [r0, #128] +2590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4474 .loc 1 2590 7 is_stmt 1 discriminator 2 view .LVU1381 + 4475 0024 5A68 ldr r2, [r3, #4] + 4476 0026 42F40002 orr r2, r2, #8388608 + 4477 002a 5A60 str r2, [r3, #4] +2592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 172 + + + 4478 .loc 1 2592 7 discriminator 2 view .LVU1382 +2592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4479 .loc 1 2592 21 is_stmt 0 discriminator 2 view .LVU1383 + 4480 002c 2023 movs r3, #32 + 4481 002e C0F88030 str r3, [r0, #128] +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4482 .loc 1 2595 7 is_stmt 1 discriminator 2 view .LVU1384 +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4483 .loc 1 2595 7 discriminator 2 view .LVU1385 + 4484 0032 0023 movs r3, #0 + 4485 0034 80F87C30 strb r3, [r0, #124] +2595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4486 .loc 1 2595 7 discriminator 2 view .LVU1386 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4487 .loc 1 2597 7 discriminator 2 view .LVU1387 +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4488 .loc 1 2597 14 is_stmt 0 discriminator 2 view .LVU1388 + 4489 0038 1846 mov r0, r3 + 4490 .LVL299: +2597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4491 .loc 1 2597 14 discriminator 2 view .LVU1389 + 4492 003a 7047 bx lr + 4493 .LVL300: + 4494 .L304: +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4495 .loc 1 2606 12 view .LVU1390 + 4496 003c 0120 movs r0, #1 + 4497 .LVL301: +2606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4498 .loc 1 2606 12 view .LVU1391 + 4499 003e 7047 bx lr + 4500 .LVL302: + 4501 .L305: +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4502 .loc 1 2601 14 view .LVU1392 + 4503 0040 0220 movs r0, #2 + 4504 .LVL303: +2601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4505 .loc 1 2601 14 view .LVU1393 + 4506 0042 7047 bx lr + 4507 .LVL304: + 4508 .L306: +2585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4509 .loc 1 2585 7 view .LVU1394 + 4510 0044 0220 movs r0, #2 + 4511 .LVL305: +2608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4512 .loc 1 2608 1 view .LVU1395 + 4513 0046 7047 bx lr + 4514 .L308: + 4515 .align 2 + 4516 .L307: + 4517 0048 000C0058 .word 1476398080 + 4518 .cfi_endproc + 4519 .LFE173: + 4521 .section .text.HAL_UART_DisableReceiverTimeout,"ax",%progbits + 4522 .align 1 + ARM GAS /tmp/ccizsdzp.s page 173 + + + 4523 .global HAL_UART_DisableReceiverTimeout + 4524 .syntax unified + 4525 .thumb + 4526 .thumb_func + 4527 .fpu fpv5-d16 + 4529 HAL_UART_DisableReceiverTimeout: + 4530 .LVL306: + 4531 .LFB174: +2617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (!(IS_LPUART_INSTANCE(huart->Instance))) + 4532 .loc 1 2617 1 is_stmt 1 view -0 + 4533 .cfi_startproc + 4534 @ args = 0, pretend = 0, frame = 0 + 4535 @ frame_needed = 0, uses_anonymous_args = 0 + 4536 @ link register save eliminated. +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4537 .loc 1 2618 3 view .LVU1397 +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4538 .loc 1 2618 9 is_stmt 0 view .LVU1398 + 4539 0000 0368 ldr r3, [r0] +2618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4540 .loc 1 2618 6 view .LVU1399 + 4541 0002 114A ldr r2, .L314 + 4542 0004 9342 cmp r3, r2 + 4543 0006 19D0 beq .L311 +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4544 .loc 1 2620 5 is_stmt 1 view .LVU1400 +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4545 .loc 1 2620 14 is_stmt 0 view .LVU1401 + 4546 0008 D0F88020 ldr r2, [r0, #128] +2620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4547 .loc 1 2620 8 view .LVU1402 + 4548 000c 202A cmp r2, #32 + 4549 000e 17D1 bne .L312 +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4550 .loc 1 2623 7 is_stmt 1 view .LVU1403 +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4551 .loc 1 2623 7 view .LVU1404 + 4552 0010 90F87C20 ldrb r2, [r0, #124] @ zero_extendqisi2 + 4553 0014 012A cmp r2, #1 + 4554 0016 15D0 beq .L313 +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4555 .loc 1 2623 7 discriminator 2 view .LVU1405 + 4556 0018 0122 movs r2, #1 + 4557 001a 80F87C20 strb r2, [r0, #124] +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4558 .loc 1 2623 7 discriminator 2 view .LVU1406 +2625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4559 .loc 1 2625 7 discriminator 2 view .LVU1407 +2625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4560 .loc 1 2625 21 is_stmt 0 discriminator 2 view .LVU1408 + 4561 001e 2422 movs r2, #36 + 4562 0020 C0F88020 str r2, [r0, #128] +2628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4563 .loc 1 2628 7 is_stmt 1 discriminator 2 view .LVU1409 + 4564 0024 5A68 ldr r2, [r3, #4] + 4565 0026 22F40002 bic r2, r2, #8388608 + 4566 002a 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccizsdzp.s page 174 + + +2630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4567 .loc 1 2630 7 discriminator 2 view .LVU1410 +2630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4568 .loc 1 2630 21 is_stmt 0 discriminator 2 view .LVU1411 + 4569 002c 2023 movs r3, #32 + 4570 002e C0F88030 str r3, [r0, #128] +2633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4571 .loc 1 2633 7 is_stmt 1 discriminator 2 view .LVU1412 +2633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4572 .loc 1 2633 7 discriminator 2 view .LVU1413 + 4573 0032 0023 movs r3, #0 + 4574 0034 80F87C30 strb r3, [r0, #124] +2633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4575 .loc 1 2633 7 discriminator 2 view .LVU1414 +2635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4576 .loc 1 2635 7 discriminator 2 view .LVU1415 +2635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4577 .loc 1 2635 14 is_stmt 0 discriminator 2 view .LVU1416 + 4578 0038 1846 mov r0, r3 + 4579 .LVL307: +2635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4580 .loc 1 2635 14 discriminator 2 view .LVU1417 + 4581 003a 7047 bx lr + 4582 .LVL308: + 4583 .L311: +2644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4584 .loc 1 2644 12 view .LVU1418 + 4585 003c 0120 movs r0, #1 + 4586 .LVL309: +2644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4587 .loc 1 2644 12 view .LVU1419 + 4588 003e 7047 bx lr + 4589 .LVL310: + 4590 .L312: +2639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4591 .loc 1 2639 14 view .LVU1420 + 4592 0040 0220 movs r0, #2 + 4593 .LVL311: +2639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4594 .loc 1 2639 14 view .LVU1421 + 4595 0042 7047 bx lr + 4596 .LVL312: + 4597 .L313: +2623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4598 .loc 1 2623 7 view .LVU1422 + 4599 0044 0220 movs r0, #2 + 4600 .LVL313: +2646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4601 .loc 1 2646 1 view .LVU1423 + 4602 0046 7047 bx lr + 4603 .L315: + 4604 .align 2 + 4605 .L314: + 4606 0048 000C0058 .word 1476398080 + 4607 .cfi_endproc + 4608 .LFE174: + 4610 .section .text.HAL_MultiProcessor_EnterMuteMode,"ax",%progbits + ARM GAS /tmp/ccizsdzp.s page 175 + + + 4611 .align 1 + 4612 .global HAL_MultiProcessor_EnterMuteMode + 4613 .syntax unified + 4614 .thumb + 4615 .thumb_func + 4616 .fpu fpv5-d16 + 4618 HAL_MultiProcessor_EnterMuteMode: + 4619 .LVL314: + 4620 .LFB177: +2695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); + 4621 .loc 1 2695 1 is_stmt 1 view -0 + 4622 .cfi_startproc + 4623 @ args = 0, pretend = 0, frame = 0 + 4624 @ frame_needed = 0, uses_anonymous_args = 0 + 4625 @ link register save eliminated. +2696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4626 .loc 1 2696 3 view .LVU1425 + 4627 0000 0268 ldr r2, [r0] + 4628 0002 9369 ldr r3, [r2, #24] + 4629 0004 43F00403 orr r3, r3, #4 + 4630 0008 9361 str r3, [r2, #24] +2697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4631 .loc 1 2697 1 is_stmt 0 view .LVU1426 + 4632 000a 7047 bx lr + 4633 .cfi_endproc + 4634 .LFE177: + 4636 .section .text.HAL_HalfDuplex_EnableTransmitter,"ax",%progbits + 4637 .align 1 + 4638 .global HAL_HalfDuplex_EnableTransmitter + 4639 .syntax unified + 4640 .thumb + 4641 .thumb_func + 4642 .fpu fpv5-d16 + 4644 HAL_HalfDuplex_EnableTransmitter: + 4645 .LVL315: + 4646 .LFB178: +2705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 4647 .loc 1 2705 1 is_stmt 1 view -0 + 4648 .cfi_startproc + 4649 @ args = 0, pretend = 0, frame = 0 + 4650 @ frame_needed = 0, uses_anonymous_args = 0 + 4651 @ link register save eliminated. +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4652 .loc 1 2706 3 view .LVU1428 +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4653 .loc 1 2706 3 view .LVU1429 + 4654 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 4655 0004 012B cmp r3, #1 + 4656 0006 17D0 beq .L319 +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4657 .loc 1 2706 3 discriminator 2 view .LVU1430 + 4658 0008 0123 movs r3, #1 + 4659 000a 80F87C30 strb r3, [r0, #124] +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4660 .loc 1 2706 3 discriminator 2 view .LVU1431 +2707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4661 .loc 1 2707 3 discriminator 2 view .LVU1432 + ARM GAS /tmp/ccizsdzp.s page 176 + + +2707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4662 .loc 1 2707 17 is_stmt 0 discriminator 2 view .LVU1433 + 4663 000e 2423 movs r3, #36 + 4664 0010 C0F88030 str r3, [r0, #128] +2710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4665 .loc 1 2710 3 is_stmt 1 discriminator 2 view .LVU1434 + 4666 0014 0268 ldr r2, [r0] + 4667 0016 1368 ldr r3, [r2] + 4668 0018 23F00C03 bic r3, r3, #12 + 4669 001c 1360 str r3, [r2] +2713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4670 .loc 1 2713 3 discriminator 2 view .LVU1435 + 4671 001e 0268 ldr r2, [r0] + 4672 0020 1368 ldr r3, [r2] + 4673 0022 43F00803 orr r3, r3, #8 + 4674 0026 1360 str r3, [r2] +2715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4675 .loc 1 2715 3 discriminator 2 view .LVU1436 +2715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4676 .loc 1 2715 17 is_stmt 0 discriminator 2 view .LVU1437 + 4677 0028 2023 movs r3, #32 + 4678 002a C0F88030 str r3, [r0, #128] +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4679 .loc 1 2717 3 is_stmt 1 discriminator 2 view .LVU1438 +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4680 .loc 1 2717 3 discriminator 2 view .LVU1439 + 4681 002e 0023 movs r3, #0 + 4682 0030 80F87C30 strb r3, [r0, #124] +2717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4683 .loc 1 2717 3 discriminator 2 view .LVU1440 +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4684 .loc 1 2719 3 discriminator 2 view .LVU1441 +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4685 .loc 1 2719 10 is_stmt 0 discriminator 2 view .LVU1442 + 4686 0034 1846 mov r0, r3 + 4687 .LVL316: +2719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4688 .loc 1 2719 10 discriminator 2 view .LVU1443 + 4689 0036 7047 bx lr + 4690 .LVL317: + 4691 .L319: +2706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4692 .loc 1 2706 3 view .LVU1444 + 4693 0038 0220 movs r0, #2 + 4694 .LVL318: +2720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4695 .loc 1 2720 1 view .LVU1445 + 4696 003a 7047 bx lr + 4697 .cfi_endproc + 4698 .LFE178: + 4700 .section .text.HAL_HalfDuplex_EnableReceiver,"ax",%progbits + 4701 .align 1 + 4702 .global HAL_HalfDuplex_EnableReceiver + 4703 .syntax unified + 4704 .thumb + 4705 .thumb_func + 4706 .fpu fpv5-d16 + ARM GAS /tmp/ccizsdzp.s page 177 + + + 4708 HAL_HalfDuplex_EnableReceiver: + 4709 .LVL319: + 4710 .LFB179: +2728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 4711 .loc 1 2728 1 is_stmt 1 view -0 + 4712 .cfi_startproc + 4713 @ args = 0, pretend = 0, frame = 0 + 4714 @ frame_needed = 0, uses_anonymous_args = 0 + 4715 @ link register save eliminated. +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4716 .loc 1 2729 3 view .LVU1447 +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4717 .loc 1 2729 3 view .LVU1448 + 4718 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 4719 0004 012B cmp r3, #1 + 4720 0006 17D0 beq .L322 +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4721 .loc 1 2729 3 discriminator 2 view .LVU1449 + 4722 0008 0123 movs r3, #1 + 4723 000a 80F87C30 strb r3, [r0, #124] +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4724 .loc 1 2729 3 discriminator 2 view .LVU1450 +2730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4725 .loc 1 2730 3 discriminator 2 view .LVU1451 +2730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4726 .loc 1 2730 17 is_stmt 0 discriminator 2 view .LVU1452 + 4727 000e 2423 movs r3, #36 + 4728 0010 C0F88030 str r3, [r0, #128] +2733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4729 .loc 1 2733 3 is_stmt 1 discriminator 2 view .LVU1453 + 4730 0014 0268 ldr r2, [r0] + 4731 0016 1368 ldr r3, [r2] + 4732 0018 23F00C03 bic r3, r3, #12 + 4733 001c 1360 str r3, [r2] +2736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4734 .loc 1 2736 3 discriminator 2 view .LVU1454 + 4735 001e 0268 ldr r2, [r0] + 4736 0020 1368 ldr r3, [r2] + 4737 0022 43F00403 orr r3, r3, #4 + 4738 0026 1360 str r3, [r2] +2738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4739 .loc 1 2738 3 discriminator 2 view .LVU1455 +2738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4740 .loc 1 2738 17 is_stmt 0 discriminator 2 view .LVU1456 + 4741 0028 2023 movs r3, #32 + 4742 002a C0F88030 str r3, [r0, #128] +2740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4743 .loc 1 2740 3 is_stmt 1 discriminator 2 view .LVU1457 +2740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4744 .loc 1 2740 3 discriminator 2 view .LVU1458 + 4745 002e 0023 movs r3, #0 + 4746 0030 80F87C30 strb r3, [r0, #124] +2740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4747 .loc 1 2740 3 discriminator 2 view .LVU1459 +2742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4748 .loc 1 2742 3 discriminator 2 view .LVU1460 +2742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 178 + + + 4749 .loc 1 2742 10 is_stmt 0 discriminator 2 view .LVU1461 + 4750 0034 1846 mov r0, r3 + 4751 .LVL320: +2742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4752 .loc 1 2742 10 discriminator 2 view .LVU1462 + 4753 0036 7047 bx lr + 4754 .LVL321: + 4755 .L322: +2729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 4756 .loc 1 2729 3 view .LVU1463 + 4757 0038 0220 movs r0, #2 + 4758 .LVL322: +2743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4759 .loc 1 2743 1 view .LVU1464 + 4760 003a 7047 bx lr + 4761 .cfi_endproc + 4762 .LFE179: + 4764 .section .text.HAL_LIN_SendBreak,"ax",%progbits + 4765 .align 1 + 4766 .global HAL_LIN_SendBreak + 4767 .syntax unified + 4768 .thumb + 4769 .thumb_func + 4770 .fpu fpv5-d16 + 4772 HAL_LIN_SendBreak: + 4773 .LVL323: + 4774 .LFB180: +2752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the parameters */ + 4775 .loc 1 2752 1 is_stmt 1 view -0 + 4776 .cfi_startproc + 4777 @ args = 0, pretend = 0, frame = 0 + 4778 @ frame_needed = 0, uses_anonymous_args = 0 + 4779 @ link register save eliminated. +2754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4780 .loc 1 2754 3 view .LVU1466 +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4781 .loc 1 2756 3 view .LVU1467 +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4782 .loc 1 2756 3 view .LVU1468 + 4783 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 4784 0004 012B cmp r3, #1 + 4785 0006 12D0 beq .L325 +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4786 .loc 1 2756 3 discriminator 2 view .LVU1469 + 4787 0008 0123 movs r3, #1 + 4788 000a 80F87C30 strb r3, [r0, #124] +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4789 .loc 1 2756 3 discriminator 2 view .LVU1470 +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4790 .loc 1 2758 3 discriminator 2 view .LVU1471 +2758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4791 .loc 1 2758 17 is_stmt 0 discriminator 2 view .LVU1472 + 4792 000e 2423 movs r3, #36 + 4793 0010 C0F88030 str r3, [r0, #128] +2761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4794 .loc 1 2761 3 is_stmt 1 discriminator 2 view .LVU1473 + 4795 0014 0268 ldr r2, [r0] + ARM GAS /tmp/ccizsdzp.s page 179 + + + 4796 0016 9369 ldr r3, [r2, #24] + 4797 0018 43F00203 orr r3, r3, #2 + 4798 001c 9361 str r3, [r2, #24] +2763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4799 .loc 1 2763 3 discriminator 2 view .LVU1474 +2763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4800 .loc 1 2763 17 is_stmt 0 discriminator 2 view .LVU1475 + 4801 001e 2023 movs r3, #32 + 4802 0020 C0F88030 str r3, [r0, #128] +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4803 .loc 1 2765 3 is_stmt 1 discriminator 2 view .LVU1476 +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4804 .loc 1 2765 3 discriminator 2 view .LVU1477 + 4805 0024 0023 movs r3, #0 + 4806 0026 80F87C30 strb r3, [r0, #124] +2765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4807 .loc 1 2765 3 discriminator 2 view .LVU1478 +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4808 .loc 1 2767 3 discriminator 2 view .LVU1479 +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4809 .loc 1 2767 10 is_stmt 0 discriminator 2 view .LVU1480 + 4810 002a 1846 mov r0, r3 + 4811 .LVL324: +2767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4812 .loc 1 2767 10 discriminator 2 view .LVU1481 + 4813 002c 7047 bx lr + 4814 .LVL325: + 4815 .L325: +2756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4816 .loc 1 2756 3 view .LVU1482 + 4817 002e 0220 movs r0, #2 + 4818 .LVL326: +2768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4819 .loc 1 2768 1 view .LVU1483 + 4820 0030 7047 bx lr + 4821 .cfi_endproc + 4822 .LFE180: + 4824 .section .text.HAL_UART_GetState,"ax",%progbits + 4825 .align 1 + 4826 .global HAL_UART_GetState + 4827 .syntax unified + 4828 .thumb + 4829 .thumb_func + 4830 .fpu fpv5-d16 + 4832 HAL_UART_GetState: + 4833 .LVL327: + 4834 .LFB181: +2797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t temp1; + 4835 .loc 1 2797 1 is_stmt 1 view -0 + 4836 .cfi_startproc + 4837 @ args = 0, pretend = 0, frame = 0 + 4838 @ frame_needed = 0, uses_anonymous_args = 0 + 4839 @ link register save eliminated. +2798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t temp2; + 4840 .loc 1 2798 3 view .LVU1485 +2799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** temp1 = huart->gState; + 4841 .loc 1 2799 3 view .LVU1486 + ARM GAS /tmp/ccizsdzp.s page 180 + + +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** temp2 = huart->RxState; + 4842 .loc 1 2800 3 view .LVU1487 +2800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** temp2 = huart->RxState; + 4843 .loc 1 2800 9 is_stmt 0 view .LVU1488 + 4844 0000 D0F88020 ldr r2, [r0, #128] + 4845 .LVL328: +2801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4846 .loc 1 2801 3 is_stmt 1 view .LVU1489 +2801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4847 .loc 1 2801 9 is_stmt 0 view .LVU1490 + 4848 0004 D0F88400 ldr r0, [r0, #132] + 4849 .LVL329: +2803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4850 .loc 1 2803 3 is_stmt 1 view .LVU1491 +2804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4851 .loc 1 2804 1 is_stmt 0 view .LVU1492 + 4852 0008 1043 orrs r0, r0, r2 + 4853 .LVL330: +2804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4854 .loc 1 2804 1 view .LVU1493 + 4855 000a 7047 bx lr + 4856 .cfi_endproc + 4857 .LFE181: + 4859 .section .text.HAL_UART_GetError,"ax",%progbits + 4860 .align 1 + 4861 .global HAL_UART_GetError + 4862 .syntax unified + 4863 .thumb + 4864 .thumb_func + 4865 .fpu fpv5-d16 + 4867 HAL_UART_GetError: + 4868 .LVL331: + 4869 .LFB182: +2813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** return huart->ErrorCode; + 4870 .loc 1 2813 1 is_stmt 1 view -0 + 4871 .cfi_startproc + 4872 @ args = 0, pretend = 0, frame = 0 + 4873 @ frame_needed = 0, uses_anonymous_args = 0 + 4874 @ link register save eliminated. +2814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4875 .loc 1 2814 3 view .LVU1495 +2814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4876 .loc 1 2814 15 is_stmt 0 view .LVU1496 + 4877 0000 D0F88800 ldr r0, [r0, #136] + 4878 .LVL332: +2815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /** + 4879 .loc 1 2815 1 view .LVU1497 + 4880 0004 7047 bx lr + 4881 .cfi_endproc + 4882 .LFE182: + 4884 .global __aeabi_uldivmod + 4885 .section .text.UART_SetConfig,"ax",%progbits + 4886 .align 1 + 4887 .global UART_SetConfig + 4888 .syntax unified + 4889 .thumb + 4890 .thumb_func + ARM GAS /tmp/ccizsdzp.s page 181 + + + 4891 .fpu fpv5-d16 + 4893 UART_SetConfig: + 4894 .LVL333: + 4895 .LFB183: +2858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tmpreg; + 4896 .loc 1 2858 1 is_stmt 1 view -0 + 4897 .cfi_startproc + 4898 @ args = 0, pretend = 0, frame = 24 + 4899 @ frame_needed = 0, uses_anonymous_args = 0 +2858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tmpreg; + 4900 .loc 1 2858 1 is_stmt 0 view .LVU1499 + 4901 0000 70B5 push {r4, r5, r6, lr} + 4902 .LCFI34: + 4903 .cfi_def_cfa_offset 16 + 4904 .cfi_offset 4, -16 + 4905 .cfi_offset 5, -12 + 4906 .cfi_offset 6, -8 + 4907 .cfi_offset 14, -4 + 4908 0002 86B0 sub sp, sp, #24 + 4909 .LCFI35: + 4910 .cfi_def_cfa_offset 40 + 4911 0004 0446 mov r4, r0 +2859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t brrtemp; + 4912 .loc 1 2859 3 is_stmt 1 view .LVU1500 +2860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** UART_ClockSourceTypeDef clocksource; + 4913 .loc 1 2860 3 view .LVU1501 +2861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t usartdiv; + 4914 .loc 1 2861 3 view .LVU1502 +2862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** HAL_StatusTypeDef ret = HAL_OK; + 4915 .loc 1 2862 3 view .LVU1503 +2863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t lpuart_ker_ck_pres; + 4916 .loc 1 2863 3 view .LVU1504 + 4917 .LVL334: +2864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** PLL2_ClocksTypeDef pll2_clocks; + 4918 .loc 1 2864 3 view .LVU1505 +2865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** PLL3_ClocksTypeDef pll3_clocks; + 4919 .loc 1 2865 3 view .LVU1506 +2866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t pclk; + 4920 .loc 1 2866 3 view .LVU1507 +2867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4921 .loc 1 2867 3 view .LVU1508 +2870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + 4922 .loc 1 2870 3 view .LVU1509 +2871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if (UART_INSTANCE_LOWPOWER(huart)) + 4923 .loc 1 2871 3 view .LVU1510 +2872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4924 .loc 1 2872 3 view .LVU1511 +2872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4925 .loc 1 2872 7 is_stmt 0 view .LVU1512 + 4926 0006 0168 ldr r1, [r0] +2878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + 4927 .loc 1 2878 5 is_stmt 1 view .LVU1513 +2879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4928 .loc 1 2879 5 view .LVU1514 +2882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_MODE(huart->Init.Mode)); + 4929 .loc 1 2882 3 view .LVU1515 +2883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + ARM GAS /tmp/ccizsdzp.s page 182 + + + 4930 .loc 1 2883 3 view .LVU1516 +2884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + 4931 .loc 1 2884 3 view .LVU1517 +2885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + 4932 .loc 1 2885 3 view .LVU1518 +2886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4933 .loc 1 2886 3 view .LVU1519 +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4934 .loc 1 2895 3 view .LVU1520 +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4935 .loc 1 2895 33 is_stmt 0 view .LVU1521 + 4936 0008 8368 ldr r3, [r0, #8] +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4937 .loc 1 2895 58 view .LVU1522 + 4938 000a 0269 ldr r2, [r0, #16] +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4939 .loc 1 2895 45 view .LVU1523 + 4940 000c 1343 orrs r3, r3, r2 +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4941 .loc 1 2895 79 view .LVU1524 + 4942 000e 4269 ldr r2, [r0, #20] +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4943 .loc 1 2895 66 view .LVU1525 + 4944 0010 1343 orrs r3, r3, r2 +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4945 .loc 1 2895 98 view .LVU1526 + 4946 0012 C269 ldr r2, [r0, #28] +2895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** tmpreg |= (uint32_t)huart->FifoMode; + 4947 .loc 1 2895 10 view .LVU1527 + 4948 0014 1343 orrs r3, r3, r2 + 4949 .LVL335: +2896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 4950 .loc 1 2896 3 is_stmt 1 view .LVU1528 +2896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 4951 .loc 1 2896 28 is_stmt 0 view .LVU1529 + 4952 0016 426E ldr r2, [r0, #100] +2896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 4953 .loc 1 2896 10 view .LVU1530 + 4954 0018 1343 orrs r3, r3, r2 + 4955 .LVL336: +2897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4956 .loc 1 2897 3 is_stmt 1 view .LVU1531 + 4957 001a 0868 ldr r0, [r1] + 4958 .LVL337: +2897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4959 .loc 1 2897 3 is_stmt 0 view .LVU1532 + 4960 001c 884A ldr r2, .L476 + 4961 001e 0240 ands r2, r2, r0 + 4962 0020 1A43 orrs r2, r2, r3 + 4963 0022 0A60 str r2, [r1] +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4964 .loc 1 2902 3 is_stmt 1 view .LVU1533 + 4965 0024 2268 ldr r2, [r4] + 4966 0026 5368 ldr r3, [r2, #4] + 4967 .LVL338: +2902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4968 .loc 1 2902 3 is_stmt 0 view .LVU1534 + ARM GAS /tmp/ccizsdzp.s page 183 + + + 4969 0028 23F44053 bic r3, r3, #12288 + 4970 002c E168 ldr r1, [r4, #12] + 4971 002e 0B43 orrs r3, r3, r1 + 4972 0030 5360 str r3, [r2, #4] +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4973 .loc 1 2910 3 is_stmt 1 view .LVU1535 +2910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4974 .loc 1 2910 10 is_stmt 0 view .LVU1536 + 4975 0032 A169 ldr r1, [r4, #24] + 4976 .LVL339: +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4977 .loc 1 2912 3 is_stmt 1 view .LVU1537 +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4978 .loc 1 2912 9 is_stmt 0 view .LVU1538 + 4979 0034 2268 ldr r2, [r4] +2912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 4980 .loc 1 2912 6 view .LVU1539 + 4981 0036 834B ldr r3, .L476+4 + 4982 0038 9A42 cmp r2, r3 + 4983 003a 01D0 beq .L329 +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4984 .loc 1 2914 5 is_stmt 1 view .LVU1540 +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4985 .loc 1 2914 26 is_stmt 0 view .LVU1541 + 4986 003c 236A ldr r3, [r4, #32] +2914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 4987 .loc 1 2914 12 view .LVU1542 + 4988 003e 1943 orrs r1, r1, r3 + 4989 .LVL340: + 4990 .L329: +2916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4991 .loc 1 2916 3 is_stmt 1 view .LVU1543 + 4992 0040 9068 ldr r0, [r2, #8] + 4993 0042 814B ldr r3, .L476+8 + 4994 0044 0340 ands r3, r3, r0 + 4995 0046 0B43 orrs r3, r3, r1 + 4996 0048 9360 str r3, [r2, #8] +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 4997 .loc 1 2921 3 view .LVU1544 + 4998 004a 2268 ldr r2, [r4] + 4999 004c D36A ldr r3, [r2, #44] + 5000 004e 23F00F03 bic r3, r3, #15 + 5001 0052 616A ldr r1, [r4, #36] + 5002 .LVL341: +2921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5003 .loc 1 2921 3 is_stmt 0 view .LVU1545 + 5004 0054 0B43 orrs r3, r3, r1 + 5005 0056 D362 str r3, [r2, #44] +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5006 .loc 1 2924 3 is_stmt 1 view .LVU1546 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5007 .loc 1 2924 3 view .LVU1547 + 5008 0058 2268 ldr r2, [r4] + 5009 005a 7C4B ldr r3, .L476+12 + 5010 005c 9A42 cmp r2, r3 + 5011 005e 21D0 beq .L462 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 184 + + + 5012 .loc 1 2924 3 discriminator 2 view .LVU1548 + 5013 0060 7B4B ldr r3, .L476+16 + 5014 0062 9A42 cmp r2, r3 + 5015 0064 00F08C80 beq .L463 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5016 .loc 1 2924 3 discriminator 19 view .LVU1549 + 5017 0068 7A4B ldr r3, .L476+20 + 5018 006a 9A42 cmp r2, r3 + 5019 006c 00F0A280 beq .L464 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5020 .loc 1 2924 3 discriminator 36 view .LVU1550 + 5021 0070 794B ldr r3, .L476+24 + 5022 0072 9A42 cmp r2, r3 + 5023 0074 00F0B580 beq .L465 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5024 .loc 1 2924 3 discriminator 53 view .LVU1551 + 5025 0078 784B ldr r3, .L476+28 + 5026 007a 9A42 cmp r2, r3 + 5027 007c 00F0C880 beq .L466 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5028 .loc 1 2924 3 discriminator 70 view .LVU1552 + 5029 0080 774B ldr r3, .L476+32 + 5030 0082 9A42 cmp r2, r3 + 5031 0084 00F0F480 beq .L467 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5032 .loc 1 2924 3 discriminator 87 view .LVU1553 + 5033 0088 764B ldr r3, .L476+36 + 5034 008a 9A42 cmp r2, r3 + 5035 008c 00F01981 beq .L468 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5036 .loc 1 2924 3 discriminator 104 view .LVU1554 + 5037 0090 754B ldr r3, .L476+40 + 5038 0092 9A42 cmp r2, r3 + 5039 0094 00F02C81 beq .L469 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5040 .loc 1 2924 3 discriminator 121 view .LVU1555 + 5041 0098 6A4B ldr r3, .L476+4 + 5042 009a 9A42 cmp r2, r3 + 5043 009c 00F03F81 beq .L470 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5044 .loc 1 2924 3 is_stmt 0 view .LVU1556 + 5045 00a0 8023 movs r3, #128 + 5046 00a2 33E0 b .L337 + 5047 .L462: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5048 .loc 1 2924 3 is_stmt 1 discriminator 1 view .LVU1557 + 5049 00a4 714B ldr r3, .L476+44 + 5050 00a6 5B6D ldr r3, [r3, #84] + 5051 00a8 03F03803 and r3, r3, #56 + 5052 00ac 282B cmp r3, #40 + 5053 00ae 65D8 bhi .L331 + 5054 00b0 DFE813F0 tbh [pc, r3, lsl #1] + 5055 .L333: + 5056 00b4 2900 .2byte (.L338-.L333)/2 + 5057 00b6 6400 .2byte (.L331-.L333)/2 + 5058 00b8 6400 .2byte (.L331-.L333)/2 + 5059 00ba 6400 .2byte (.L331-.L333)/2 + ARM GAS /tmp/ccizsdzp.s page 185 + + + 5060 00bc 6400 .2byte (.L331-.L333)/2 + 5061 00be 6400 .2byte (.L331-.L333)/2 + 5062 00c0 6400 .2byte (.L331-.L333)/2 + 5063 00c2 6400 .2byte (.L331-.L333)/2 + 5064 00c4 4D01 .2byte (.L431-.L333)/2 + 5065 00c6 6400 .2byte (.L331-.L333)/2 + 5066 00c8 6400 .2byte (.L331-.L333)/2 + 5067 00ca 6400 .2byte (.L331-.L333)/2 + 5068 00cc 6400 .2byte (.L331-.L333)/2 + 5069 00ce 6400 .2byte (.L331-.L333)/2 + 5070 00d0 6400 .2byte (.L331-.L333)/2 + 5071 00d2 6400 .2byte (.L331-.L333)/2 + 5072 00d4 2B00 .2byte (.L336-.L333)/2 + 5073 00d6 6400 .2byte (.L331-.L333)/2 + 5074 00d8 6400 .2byte (.L331-.L333)/2 + 5075 00da 6400 .2byte (.L331-.L333)/2 + 5076 00dc 6400 .2byte (.L331-.L333)/2 + 5077 00de 6400 .2byte (.L331-.L333)/2 + 5078 00e0 6400 .2byte (.L331-.L333)/2 + 5079 00e2 6400 .2byte (.L331-.L333)/2 + 5080 00e4 5E00 .2byte (.L335-.L333)/2 + 5081 00e6 6400 .2byte (.L331-.L333)/2 + 5082 00e8 6400 .2byte (.L331-.L333)/2 + 5083 00ea 6400 .2byte (.L331-.L333)/2 + 5084 00ec 6400 .2byte (.L331-.L333)/2 + 5085 00ee 6400 .2byte (.L331-.L333)/2 + 5086 00f0 6400 .2byte (.L331-.L333)/2 + 5087 00f2 6400 .2byte (.L331-.L333)/2 + 5088 00f4 6000 .2byte (.L334-.L333)/2 + 5089 00f6 6400 .2byte (.L331-.L333)/2 + 5090 00f8 6400 .2byte (.L331-.L333)/2 + 5091 00fa 6400 .2byte (.L331-.L333)/2 + 5092 00fc 6400 .2byte (.L331-.L333)/2 + 5093 00fe 6400 .2byte (.L331-.L333)/2 + 5094 0100 6400 .2byte (.L331-.L333)/2 + 5095 0102 6400 .2byte (.L331-.L333)/2 + 5096 0104 6200 .2byte (.L332-.L333)/2 + 5097 .p2align 1 + 5098 .L338: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5099 .loc 1 2924 3 is_stmt 0 view .LVU1558 + 5100 0106 0123 movs r3, #1 + 5101 0108 00E0 b .L337 + 5102 .L336: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5103 .loc 1 2924 3 is_stmt 1 discriminator 6 view .LVU1559 + 5104 .LVL342: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5105 .loc 1 2924 3 discriminator 6 view .LVU1560 + 5106 010a 0823 movs r3, #8 + 5107 .LVL343: + 5108 .L337: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5109 .loc 1 2924 3 discriminator 154 view .LVU1561 +2927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5110 .loc 1 2927 3 discriminator 154 view .LVU1562 +2927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + ARM GAS /tmp/ccizsdzp.s page 186 + + + 5111 .loc 1 2927 6 is_stmt 0 discriminator 154 view .LVU1563 + 5112 010c 4D49 ldr r1, .L476+4 + 5113 010e 8A42 cmp r2, r1 + 5114 0110 00F02F81 beq .L471 +2994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5115 .loc 1 2994 8 is_stmt 1 view .LVU1564 +2994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5116 .loc 1 2994 23 is_stmt 0 view .LVU1565 + 5117 0114 E069 ldr r0, [r4, #28] +2994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5118 .loc 1 2994 11 view .LVU1566 + 5119 0116 B0F5004F cmp r0, #32768 + 5120 011a 00F0AF81 beq .L472 +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5121 .loc 1 3052 5 is_stmt 1 view .LVU1567 + 5122 011e 202B cmp r3, #32 + 5123 0120 00F20782 bhi .L422 + 5124 0124 202B cmp r3, #32 + 5125 0126 00F25182 bhi .L455 + 5126 012a DFE813F0 tbh [pc, r3, lsl #1] + 5127 .L424: + 5128 012e 1E02 .2byte (.L429-.L424)/2 + 5129 0130 2402 .2byte (.L428-.L424)/2 + 5130 0132 4F02 .2byte (.L455-.L424)/2 + 5131 0134 4F02 .2byte (.L455-.L424)/2 + 5132 0136 2702 .2byte (.L427-.L424)/2 + 5133 0138 4F02 .2byte (.L455-.L424)/2 + 5134 013a 4F02 .2byte (.L455-.L424)/2 + 5135 013c 4F02 .2byte (.L455-.L424)/2 + 5136 013e 2C02 .2byte (.L426-.L424)/2 + 5137 0140 4F02 .2byte (.L455-.L424)/2 + 5138 0142 4F02 .2byte (.L455-.L424)/2 + 5139 0144 4F02 .2byte (.L455-.L424)/2 + 5140 0146 4F02 .2byte (.L455-.L424)/2 + 5141 0148 4F02 .2byte (.L455-.L424)/2 + 5142 014a 4F02 .2byte (.L455-.L424)/2 + 5143 014c 4F02 .2byte (.L455-.L424)/2 + 5144 014e 3102 .2byte (.L425-.L424)/2 + 5145 0150 4F02 .2byte (.L455-.L424)/2 + 5146 0152 4F02 .2byte (.L455-.L424)/2 + 5147 0154 4F02 .2byte (.L455-.L424)/2 + 5148 0156 4F02 .2byte (.L455-.L424)/2 + 5149 0158 4F02 .2byte (.L455-.L424)/2 + 5150 015a 4F02 .2byte (.L455-.L424)/2 + 5151 015c 4F02 .2byte (.L455-.L424)/2 + 5152 015e 4F02 .2byte (.L455-.L424)/2 + 5153 0160 4F02 .2byte (.L455-.L424)/2 + 5154 0162 4F02 .2byte (.L455-.L424)/2 + 5155 0164 4F02 .2byte (.L455-.L424)/2 + 5156 0166 4F02 .2byte (.L455-.L424)/2 + 5157 0168 4F02 .2byte (.L455-.L424)/2 + 5158 016a 4F02 .2byte (.L455-.L424)/2 + 5159 016c 4F02 .2byte (.L455-.L424)/2 + 5160 016e 3D02 .2byte (.L456-.L424)/2 + 5161 .LVL344: + 5162 .p2align 1 + 5163 .L335: + ARM GAS /tmp/ccizsdzp.s page 187 + + +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5164 .loc 1 2924 3 discriminator 7 view .LVU1568 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5165 .loc 1 2924 3 discriminator 7 view .LVU1569 + 5166 0170 1023 movs r3, #16 + 5167 0172 CBE7 b .L337 + 5168 .LVL345: + 5169 .L334: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5170 .loc 1 2924 3 discriminator 8 view .LVU1570 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5171 .loc 1 2924 3 discriminator 8 view .LVU1571 + 5172 0174 2023 movs r3, #32 + 5173 0176 C9E7 b .L337 + 5174 .LVL346: + 5175 .L332: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5176 .loc 1 2924 3 discriminator 9 view .LVU1572 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5177 .loc 1 2924 3 discriminator 9 view .LVU1573 + 5178 0178 4023 movs r3, #64 + 5179 017a C7E7 b .L337 + 5180 .LVL347: + 5181 .L331: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5182 .loc 1 2924 3 discriminator 3 view .LVU1574 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5183 .loc 1 2924 3 discriminator 3 view .LVU1575 + 5184 017c 8023 movs r3, #128 + 5185 017e C5E7 b .L337 + 5186 .LVL348: + 5187 .L463: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5188 .loc 1 2924 3 discriminator 18 view .LVU1576 + 5189 0180 3A4B ldr r3, .L476+44 + 5190 0182 5B6D ldr r3, [r3, #84] + 5191 0184 03F00703 and r3, r3, #7 + 5192 0188 052B cmp r3, #5 + 5193 018a 11D8 bhi .L340 + 5194 018c DFE813F0 tbh [pc, r3, lsl #1] + 5195 .L342: + 5196 0190 0600 .2byte (.L346-.L342)/2 + 5197 0192 E100 .2byte (.L432-.L342)/2 + 5198 0194 0800 .2byte (.L345-.L342)/2 + 5199 0196 0A00 .2byte (.L344-.L342)/2 + 5200 0198 0C00 .2byte (.L343-.L342)/2 + 5201 019a 0E00 .2byte (.L341-.L342)/2 + 5202 .p2align 1 + 5203 .L346: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5204 .loc 1 2924 3 is_stmt 0 view .LVU1577 + 5205 019c 0023 movs r3, #0 + 5206 019e B5E7 b .L337 + 5207 .L345: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5208 .loc 1 2924 3 is_stmt 1 discriminator 23 view .LVU1578 + 5209 .LVL349: + ARM GAS /tmp/ccizsdzp.s page 188 + + +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5210 .loc 1 2924 3 discriminator 23 view .LVU1579 + 5211 01a0 0823 movs r3, #8 + 5212 01a2 B3E7 b .L337 + 5213 .LVL350: + 5214 .L344: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5215 .loc 1 2924 3 discriminator 24 view .LVU1580 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5216 .loc 1 2924 3 discriminator 24 view .LVU1581 + 5217 01a4 1023 movs r3, #16 + 5218 01a6 B1E7 b .L337 + 5219 .LVL351: + 5220 .L343: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5221 .loc 1 2924 3 discriminator 25 view .LVU1582 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5222 .loc 1 2924 3 discriminator 25 view .LVU1583 + 5223 01a8 2023 movs r3, #32 + 5224 01aa AFE7 b .L337 + 5225 .LVL352: + 5226 .L341: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5227 .loc 1 2924 3 discriminator 26 view .LVU1584 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5228 .loc 1 2924 3 discriminator 26 view .LVU1585 + 5229 01ac 4023 movs r3, #64 + 5230 01ae ADE7 b .L337 + 5231 .LVL353: + 5232 .L340: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5233 .loc 1 2924 3 discriminator 20 view .LVU1586 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5234 .loc 1 2924 3 discriminator 20 view .LVU1587 + 5235 01b0 8023 movs r3, #128 + 5236 01b2 ABE7 b .L337 + 5237 .LVL354: + 5238 .L464: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5239 .loc 1 2924 3 discriminator 35 view .LVU1588 + 5240 01b4 2D4B ldr r3, .L476+44 + 5241 01b6 5B6D ldr r3, [r3, #84] + 5242 01b8 03F00703 and r3, r3, #7 + 5243 01bc 052B cmp r3, #5 + 5244 01be 0ED8 bhi .L348 + 5245 01c0 DFE803F0 tbb [pc, r3] + 5246 .L350: + 5247 01c4 03 .byte (.L354-.L350)/2 + 5248 01c5 C9 .byte (.L433-.L350)/2 + 5249 01c6 05 .byte (.L353-.L350)/2 + 5250 01c7 07 .byte (.L352-.L350)/2 + 5251 01c8 09 .byte (.L351-.L350)/2 + 5252 01c9 0B .byte (.L349-.L350)/2 + 5253 .p2align 1 + 5254 .L354: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5255 .loc 1 2924 3 is_stmt 0 view .LVU1589 + ARM GAS /tmp/ccizsdzp.s page 189 + + + 5256 01ca 0023 movs r3, #0 + 5257 01cc 9EE7 b .L337 + 5258 .L353: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5259 .loc 1 2924 3 is_stmt 1 discriminator 40 view .LVU1590 + 5260 .LVL355: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5261 .loc 1 2924 3 discriminator 40 view .LVU1591 + 5262 01ce 0823 movs r3, #8 + 5263 01d0 9CE7 b .L337 + 5264 .LVL356: + 5265 .L352: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5266 .loc 1 2924 3 discriminator 41 view .LVU1592 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5267 .loc 1 2924 3 discriminator 41 view .LVU1593 + 5268 01d2 1023 movs r3, #16 + 5269 01d4 9AE7 b .L337 + 5270 .LVL357: + 5271 .L351: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5272 .loc 1 2924 3 discriminator 42 view .LVU1594 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5273 .loc 1 2924 3 discriminator 42 view .LVU1595 + 5274 01d6 2023 movs r3, #32 + 5275 01d8 98E7 b .L337 + 5276 .LVL358: + 5277 .L349: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5278 .loc 1 2924 3 discriminator 43 view .LVU1596 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5279 .loc 1 2924 3 discriminator 43 view .LVU1597 + 5280 01da 4023 movs r3, #64 + 5281 01dc 96E7 b .L337 + 5282 .LVL359: + 5283 .L348: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5284 .loc 1 2924 3 discriminator 37 view .LVU1598 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5285 .loc 1 2924 3 discriminator 37 view .LVU1599 + 5286 01de 8023 movs r3, #128 + 5287 01e0 94E7 b .L337 + 5288 .LVL360: + 5289 .L465: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5290 .loc 1 2924 3 discriminator 52 view .LVU1600 + 5291 01e2 224B ldr r3, .L476+44 + 5292 01e4 5B6D ldr r3, [r3, #84] + 5293 01e6 03F00703 and r3, r3, #7 + 5294 01ea 052B cmp r3, #5 + 5295 01ec 0ED8 bhi .L356 + 5296 01ee DFE803F0 tbb [pc, r3] + 5297 .L358: + 5298 01f2 03 .byte (.L362-.L358)/2 + 5299 01f3 B4 .byte (.L434-.L358)/2 + 5300 01f4 05 .byte (.L361-.L358)/2 + 5301 01f5 07 .byte (.L360-.L358)/2 + ARM GAS /tmp/ccizsdzp.s page 190 + + + 5302 01f6 09 .byte (.L359-.L358)/2 + 5303 01f7 0B .byte (.L357-.L358)/2 + 5304 .p2align 1 + 5305 .L362: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5306 .loc 1 2924 3 is_stmt 0 view .LVU1601 + 5307 01f8 0023 movs r3, #0 + 5308 01fa 87E7 b .L337 + 5309 .L361: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5310 .loc 1 2924 3 is_stmt 1 discriminator 57 view .LVU1602 + 5311 .LVL361: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5312 .loc 1 2924 3 discriminator 57 view .LVU1603 + 5313 01fc 0823 movs r3, #8 + 5314 01fe 85E7 b .L337 + 5315 .LVL362: + 5316 .L360: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5317 .loc 1 2924 3 discriminator 58 view .LVU1604 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5318 .loc 1 2924 3 discriminator 58 view .LVU1605 + 5319 0200 1023 movs r3, #16 + 5320 0202 83E7 b .L337 + 5321 .LVL363: + 5322 .L359: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5323 .loc 1 2924 3 discriminator 59 view .LVU1606 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5324 .loc 1 2924 3 discriminator 59 view .LVU1607 + 5325 0204 2023 movs r3, #32 + 5326 0206 81E7 b .L337 + 5327 .LVL364: + 5328 .L357: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5329 .loc 1 2924 3 discriminator 60 view .LVU1608 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5330 .loc 1 2924 3 discriminator 60 view .LVU1609 + 5331 0208 4023 movs r3, #64 + 5332 020a 7FE7 b .L337 + 5333 .LVL365: + 5334 .L356: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5335 .loc 1 2924 3 discriminator 54 view .LVU1610 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5336 .loc 1 2924 3 discriminator 54 view .LVU1611 + 5337 020c 8023 movs r3, #128 + 5338 020e 7DE7 b .L337 + 5339 .LVL366: + 5340 .L466: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5341 .loc 1 2924 3 discriminator 69 view .LVU1612 + 5342 0210 164B ldr r3, .L476+44 + 5343 0212 5B6D ldr r3, [r3, #84] + 5344 0214 03F00703 and r3, r3, #7 + 5345 0218 052B cmp r3, #5 + 5346 021a 0ED8 bhi .L364 + ARM GAS /tmp/ccizsdzp.s page 191 + + + 5347 021c DFE803F0 tbb [pc, r3] + 5348 .L366: + 5349 0220 03 .byte (.L370-.L366)/2 + 5350 0221 9F .byte (.L435-.L366)/2 + 5351 0222 05 .byte (.L369-.L366)/2 + 5352 0223 07 .byte (.L368-.L366)/2 + 5353 0224 09 .byte (.L367-.L366)/2 + 5354 0225 0B .byte (.L365-.L366)/2 + 5355 .p2align 1 + 5356 .L370: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5357 .loc 1 2924 3 is_stmt 0 view .LVU1613 + 5358 0226 0023 movs r3, #0 + 5359 0228 70E7 b .L337 + 5360 .L369: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5361 .loc 1 2924 3 is_stmt 1 discriminator 74 view .LVU1614 + 5362 .LVL367: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5363 .loc 1 2924 3 discriminator 74 view .LVU1615 + 5364 022a 0823 movs r3, #8 + 5365 022c 6EE7 b .L337 + 5366 .LVL368: + 5367 .L368: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5368 .loc 1 2924 3 discriminator 75 view .LVU1616 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5369 .loc 1 2924 3 discriminator 75 view .LVU1617 + 5370 022e 1023 movs r3, #16 + 5371 0230 6CE7 b .L337 + 5372 .LVL369: + 5373 .L367: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5374 .loc 1 2924 3 discriminator 76 view .LVU1618 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5375 .loc 1 2924 3 discriminator 76 view .LVU1619 + 5376 0232 2023 movs r3, #32 + 5377 0234 6AE7 b .L337 + 5378 .LVL370: + 5379 .L365: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5380 .loc 1 2924 3 discriminator 77 view .LVU1620 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5381 .loc 1 2924 3 discriminator 77 view .LVU1621 + 5382 0236 4023 movs r3, #64 + 5383 0238 68E7 b .L337 + 5384 .LVL371: + 5385 .L364: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5386 .loc 1 2924 3 discriminator 71 view .LVU1622 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5387 .loc 1 2924 3 discriminator 71 view .LVU1623 + 5388 023a 8023 movs r3, #128 + 5389 023c 66E7 b .L337 + 5390 .L477: + 5391 023e 00BF .align 2 + 5392 .L476: + ARM GAS /tmp/ccizsdzp.s page 192 + + + 5393 0240 F369FFCF .word -805344781 + 5394 0244 000C0058 .word 1476398080 + 5395 0248 FFF4FF11 .word 301987071 + 5396 024c 00100140 .word 1073811456 + 5397 0250 00440040 .word 1073759232 + 5398 0254 00480040 .word 1073760256 + 5399 0258 004C0040 .word 1073761280 + 5400 025c 00500040 .word 1073762304 + 5401 0260 00140140 .word 1073812480 + 5402 0264 00780040 .word 1073772544 + 5403 0268 007C0040 .word 1073773568 + 5404 026c 00440258 .word 1476543488 + 5405 .LVL372: + 5406 .L467: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5407 .loc 1 2924 3 discriminator 86 view .LVU1624 + 5408 0270 7D4B ldr r3, .L478 + 5409 0272 5B6D ldr r3, [r3, #84] + 5410 0274 03F03803 and r3, r3, #56 + 5411 0278 282B cmp r3, #40 + 5412 027a 20D8 bhi .L372 + 5413 027c DFE803F0 tbb [pc, r3] + 5414 .L374: + 5415 0280 15 .byte (.L378-.L374)/2 + 5416 0281 1F .byte (.L372-.L374)/2 + 5417 0282 1F .byte (.L372-.L374)/2 + 5418 0283 1F .byte (.L372-.L374)/2 + 5419 0284 1F .byte (.L372-.L374)/2 + 5420 0285 1F .byte (.L372-.L374)/2 + 5421 0286 1F .byte (.L372-.L374)/2 + 5422 0287 1F .byte (.L372-.L374)/2 + 5423 0288 71 .byte (.L436-.L374)/2 + 5424 0289 1F .byte (.L372-.L374)/2 + 5425 028a 1F .byte (.L372-.L374)/2 + 5426 028b 1F .byte (.L372-.L374)/2 + 5427 028c 1F .byte (.L372-.L374)/2 + 5428 028d 1F .byte (.L372-.L374)/2 + 5429 028e 1F .byte (.L372-.L374)/2 + 5430 028f 1F .byte (.L372-.L374)/2 + 5431 0290 17 .byte (.L377-.L374)/2 + 5432 0291 1F .byte (.L372-.L374)/2 + 5433 0292 1F .byte (.L372-.L374)/2 + 5434 0293 1F .byte (.L372-.L374)/2 + 5435 0294 1F .byte (.L372-.L374)/2 + 5436 0295 1F .byte (.L372-.L374)/2 + 5437 0296 1F .byte (.L372-.L374)/2 + 5438 0297 1F .byte (.L372-.L374)/2 + 5439 0298 19 .byte (.L376-.L374)/2 + 5440 0299 1F .byte (.L372-.L374)/2 + 5441 029a 1F .byte (.L372-.L374)/2 + 5442 029b 1F .byte (.L372-.L374)/2 + 5443 029c 1F .byte (.L372-.L374)/2 + 5444 029d 1F .byte (.L372-.L374)/2 + 5445 029e 1F .byte (.L372-.L374)/2 + 5446 029f 1F .byte (.L372-.L374)/2 + 5447 02a0 1B .byte (.L375-.L374)/2 + 5448 02a1 1F .byte (.L372-.L374)/2 + ARM GAS /tmp/ccizsdzp.s page 193 + + + 5449 02a2 1F .byte (.L372-.L374)/2 + 5450 02a3 1F .byte (.L372-.L374)/2 + 5451 02a4 1F .byte (.L372-.L374)/2 + 5452 02a5 1F .byte (.L372-.L374)/2 + 5453 02a6 1F .byte (.L372-.L374)/2 + 5454 02a7 1F .byte (.L372-.L374)/2 + 5455 02a8 1D .byte (.L373-.L374)/2 + 5456 02a9 00 .p2align 1 + 5457 .L378: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5458 .loc 1 2924 3 is_stmt 0 view .LVU1625 + 5459 02aa 0123 movs r3, #1 + 5460 02ac 2EE7 b .L337 + 5461 .L377: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5462 .loc 1 2924 3 is_stmt 1 discriminator 91 view .LVU1626 + 5463 .LVL373: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5464 .loc 1 2924 3 discriminator 91 view .LVU1627 + 5465 02ae 0823 movs r3, #8 + 5466 02b0 2CE7 b .L337 + 5467 .LVL374: + 5468 .L376: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5469 .loc 1 2924 3 discriminator 92 view .LVU1628 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5470 .loc 1 2924 3 discriminator 92 view .LVU1629 + 5471 02b2 1023 movs r3, #16 + 5472 02b4 2AE7 b .L337 + 5473 .LVL375: + 5474 .L375: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5475 .loc 1 2924 3 discriminator 93 view .LVU1630 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5476 .loc 1 2924 3 discriminator 93 view .LVU1631 + 5477 02b6 2023 movs r3, #32 + 5478 02b8 28E7 b .L337 + 5479 .LVL376: + 5480 .L373: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5481 .loc 1 2924 3 discriminator 94 view .LVU1632 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5482 .loc 1 2924 3 discriminator 94 view .LVU1633 + 5483 02ba 4023 movs r3, #64 + 5484 02bc 26E7 b .L337 + 5485 .LVL377: + 5486 .L372: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5487 .loc 1 2924 3 discriminator 88 view .LVU1634 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5488 .loc 1 2924 3 discriminator 88 view .LVU1635 + 5489 02be 8023 movs r3, #128 + 5490 02c0 24E7 b .L337 + 5491 .LVL378: + 5492 .L468: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5493 .loc 1 2924 3 discriminator 103 view .LVU1636 + ARM GAS /tmp/ccizsdzp.s page 194 + + + 5494 02c2 694B ldr r3, .L478 + 5495 02c4 5B6D ldr r3, [r3, #84] + 5496 02c6 03F00703 and r3, r3, #7 + 5497 02ca 052B cmp r3, #5 + 5498 02cc 0ED8 bhi .L380 + 5499 02ce DFE803F0 tbb [pc, r3] + 5500 .L382: + 5501 02d2 03 .byte (.L386-.L382)/2 + 5502 02d3 4A .byte (.L437-.L382)/2 + 5503 02d4 05 .byte (.L385-.L382)/2 + 5504 02d5 07 .byte (.L384-.L382)/2 + 5505 02d6 09 .byte (.L383-.L382)/2 + 5506 02d7 0B .byte (.L381-.L382)/2 + 5507 .p2align 1 + 5508 .L386: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5509 .loc 1 2924 3 is_stmt 0 view .LVU1637 + 5510 02d8 0023 movs r3, #0 + 5511 02da 17E7 b .L337 + 5512 .L385: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5513 .loc 1 2924 3 is_stmt 1 discriminator 108 view .LVU1638 + 5514 .LVL379: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5515 .loc 1 2924 3 discriminator 108 view .LVU1639 + 5516 02dc 0823 movs r3, #8 + 5517 02de 15E7 b .L337 + 5518 .LVL380: + 5519 .L384: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5520 .loc 1 2924 3 discriminator 109 view .LVU1640 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5521 .loc 1 2924 3 discriminator 109 view .LVU1641 + 5522 02e0 1023 movs r3, #16 + 5523 02e2 13E7 b .L337 + 5524 .LVL381: + 5525 .L383: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5526 .loc 1 2924 3 discriminator 110 view .LVU1642 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5527 .loc 1 2924 3 discriminator 110 view .LVU1643 + 5528 02e4 2023 movs r3, #32 + 5529 02e6 11E7 b .L337 + 5530 .LVL382: + 5531 .L381: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5532 .loc 1 2924 3 discriminator 111 view .LVU1644 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5533 .loc 1 2924 3 discriminator 111 view .LVU1645 + 5534 02e8 4023 movs r3, #64 + 5535 02ea 0FE7 b .L337 + 5536 .LVL383: + 5537 .L380: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5538 .loc 1 2924 3 discriminator 105 view .LVU1646 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5539 .loc 1 2924 3 discriminator 105 view .LVU1647 + ARM GAS /tmp/ccizsdzp.s page 195 + + + 5540 02ec 8023 movs r3, #128 + 5541 02ee 0DE7 b .L337 + 5542 .LVL384: + 5543 .L469: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5544 .loc 1 2924 3 discriminator 120 view .LVU1648 + 5545 02f0 5D4B ldr r3, .L478 + 5546 02f2 5B6D ldr r3, [r3, #84] + 5547 02f4 03F00703 and r3, r3, #7 + 5548 02f8 052B cmp r3, #5 + 5549 02fa 0ED8 bhi .L388 + 5550 02fc DFE803F0 tbb [pc, r3] + 5551 .L390: + 5552 0300 03 .byte (.L394-.L390)/2 + 5553 0301 35 .byte (.L438-.L390)/2 + 5554 0302 05 .byte (.L393-.L390)/2 + 5555 0303 07 .byte (.L392-.L390)/2 + 5556 0304 09 .byte (.L391-.L390)/2 + 5557 0305 0B .byte (.L389-.L390)/2 + 5558 .p2align 1 + 5559 .L394: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5560 .loc 1 2924 3 is_stmt 0 view .LVU1649 + 5561 0306 0023 movs r3, #0 + 5562 0308 00E7 b .L337 + 5563 .L393: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5564 .loc 1 2924 3 is_stmt 1 discriminator 125 view .LVU1650 + 5565 .LVL385: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5566 .loc 1 2924 3 discriminator 125 view .LVU1651 + 5567 030a 0823 movs r3, #8 + 5568 030c FEE6 b .L337 + 5569 .LVL386: + 5570 .L392: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5571 .loc 1 2924 3 discriminator 126 view .LVU1652 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5572 .loc 1 2924 3 discriminator 126 view .LVU1653 + 5573 030e 1023 movs r3, #16 + 5574 0310 FCE6 b .L337 + 5575 .LVL387: + 5576 .L391: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5577 .loc 1 2924 3 discriminator 127 view .LVU1654 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5578 .loc 1 2924 3 discriminator 127 view .LVU1655 + 5579 0312 2023 movs r3, #32 + 5580 0314 FAE6 b .L337 + 5581 .LVL388: + 5582 .L389: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5583 .loc 1 2924 3 discriminator 128 view .LVU1656 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5584 .loc 1 2924 3 discriminator 128 view .LVU1657 + 5585 0316 4023 movs r3, #64 + 5586 0318 F8E6 b .L337 + ARM GAS /tmp/ccizsdzp.s page 196 + + + 5587 .LVL389: + 5588 .L388: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5589 .loc 1 2924 3 discriminator 122 view .LVU1658 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5590 .loc 1 2924 3 discriminator 122 view .LVU1659 + 5591 031a 8023 movs r3, #128 + 5592 031c F6E6 b .L337 + 5593 .LVL390: + 5594 .L470: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5595 .loc 1 2924 3 discriminator 137 view .LVU1660 + 5596 031e 03F50E33 add r3, r3, #145408 + 5597 0322 9B6D ldr r3, [r3, #88] + 5598 0324 03F00703 and r3, r3, #7 + 5599 0328 052B cmp r3, #5 + 5600 032a 0ED8 bhi .L395 + 5601 032c DFE803F0 tbb [pc, r3] + 5602 .L397: + 5603 0330 03 .byte (.L401-.L397)/2 + 5604 0331 1F .byte (.L440-.L397)/2 + 5605 0332 05 .byte (.L400-.L397)/2 + 5606 0333 07 .byte (.L399-.L397)/2 + 5607 0334 09 .byte (.L398-.L397)/2 + 5608 0335 0B .byte (.L396-.L397)/2 + 5609 .p2align 1 + 5610 .L401: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5611 .loc 1 2924 3 is_stmt 0 view .LVU1661 + 5612 0336 0223 movs r3, #2 + 5613 0338 E8E6 b .L337 + 5614 .L400: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5615 .loc 1 2924 3 is_stmt 1 discriminator 142 view .LVU1662 + 5616 .LVL391: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5617 .loc 1 2924 3 discriminator 142 view .LVU1663 + 5618 033a 0823 movs r3, #8 + 5619 033c E6E6 b .L337 + 5620 .LVL392: + 5621 .L399: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5622 .loc 1 2924 3 discriminator 143 view .LVU1664 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5623 .loc 1 2924 3 discriminator 143 view .LVU1665 + 5624 033e 1023 movs r3, #16 + 5625 0340 E4E6 b .L337 + 5626 .LVL393: + 5627 .L398: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5628 .loc 1 2924 3 discriminator 144 view .LVU1666 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5629 .loc 1 2924 3 discriminator 144 view .LVU1667 + 5630 0342 2023 movs r3, #32 + 5631 0344 E2E6 b .L337 + 5632 .LVL394: + 5633 .L396: + ARM GAS /tmp/ccizsdzp.s page 197 + + +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5634 .loc 1 2924 3 discriminator 145 view .LVU1668 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5635 .loc 1 2924 3 discriminator 145 view .LVU1669 + 5636 0346 4023 movs r3, #64 + 5637 0348 E0E6 b .L337 + 5638 .LVL395: + 5639 .L395: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5640 .loc 1 2924 3 discriminator 139 view .LVU1670 +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5641 .loc 1 2924 3 discriminator 139 view .LVU1671 + 5642 034a 8023 movs r3, #128 + 5643 034c DEE6 b .L337 + 5644 .LVL396: + 5645 .L431: +2924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5646 .loc 1 2924 3 is_stmt 0 view .LVU1672 + 5647 034e 0423 movs r3, #4 + 5648 0350 DCE6 b .L337 + 5649 .L432: + 5650 0352 0423 movs r3, #4 + 5651 0354 DAE6 b .L337 + 5652 .L433: + 5653 0356 0423 movs r3, #4 + 5654 0358 D8E6 b .L337 + 5655 .L434: + 5656 035a 0423 movs r3, #4 + 5657 035c D6E6 b .L337 + 5658 .L435: + 5659 035e 0423 movs r3, #4 + 5660 0360 D4E6 b .L337 + 5661 .L436: + 5662 0362 0423 movs r3, #4 + 5663 0364 D2E6 b .L337 + 5664 .L437: + 5665 0366 0423 movs r3, #4 + 5666 0368 D0E6 b .L337 + 5667 .L438: + 5668 036a 0423 movs r3, #4 + 5669 036c CEE6 b .L337 + 5670 .L440: + 5671 036e 0423 movs r3, #4 + 5672 0370 CCE6 b .L337 + 5673 .LVL397: + 5674 .L471: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5675 .loc 1 2930 5 is_stmt 1 view .LVU1673 + 5676 0372 202B cmp r3, #32 + 5677 0374 27D8 bhi .L403 + 5678 0376 022B cmp r3, #2 + 5679 0378 C0F01A81 bcc .L441 + 5680 037c 023B subs r3, r3, #2 + 5681 .LVL398: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5682 .loc 1 2930 5 is_stmt 0 view .LVU1674 + 5683 037e 1E2B cmp r3, #30 + ARM GAS /tmp/ccizsdzp.s page 198 + + + 5684 0380 00F21881 bhi .L442 + 5685 0384 DFE813F0 tbh [pc, r3, lsl #1] + 5686 .L406: + 5687 0388 5000 .2byte (.L410-.L406)/2 + 5688 038a 1601 .2byte (.L442-.L406)/2 + 5689 038c 5600 .2byte (.L409-.L406)/2 + 5690 038e 1601 .2byte (.L442-.L406)/2 + 5691 0390 1601 .2byte (.L442-.L406)/2 + 5692 0392 1601 .2byte (.L442-.L406)/2 + 5693 0394 5B00 .2byte (.L408-.L406)/2 + 5694 0396 1601 .2byte (.L442-.L406)/2 + 5695 0398 1601 .2byte (.L442-.L406)/2 + 5696 039a 1601 .2byte (.L442-.L406)/2 + 5697 039c 1601 .2byte (.L442-.L406)/2 + 5698 039e 1601 .2byte (.L442-.L406)/2 + 5699 03a0 1601 .2byte (.L442-.L406)/2 + 5700 03a2 1601 .2byte (.L442-.L406)/2 + 5701 03a4 6000 .2byte (.L407-.L406)/2 + 5702 03a6 1601 .2byte (.L442-.L406)/2 + 5703 03a8 1601 .2byte (.L442-.L406)/2 + 5704 03aa 1601 .2byte (.L442-.L406)/2 + 5705 03ac 1601 .2byte (.L442-.L406)/2 + 5706 03ae 1601 .2byte (.L442-.L406)/2 + 5707 03b0 1601 .2byte (.L442-.L406)/2 + 5708 03b2 1601 .2byte (.L442-.L406)/2 + 5709 03b4 1601 .2byte (.L442-.L406)/2 + 5710 03b6 1601 .2byte (.L442-.L406)/2 + 5711 03b8 1601 .2byte (.L442-.L406)/2 + 5712 03ba 1601 .2byte (.L442-.L406)/2 + 5713 03bc 1601 .2byte (.L442-.L406)/2 + 5714 03be 1601 .2byte (.L442-.L406)/2 + 5715 03c0 1601 .2byte (.L442-.L406)/2 + 5716 03c2 1601 .2byte (.L442-.L406)/2 + 5717 03c4 6C00 .2byte (.L443-.L406)/2 + 5718 .LVL399: + 5719 .p2align 1 + 5720 .L403: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5721 .loc 1 2930 5 view .LVU1675 + 5722 03c6 402B cmp r3, #64 + 5723 03c8 2CD1 bne .L473 +2957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5724 .loc 1 2957 14 view .LVU1676 + 5725 03ca 4FF40040 mov r0, #32768 + 5726 .LVL400: + 5727 .L405: +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5728 .loc 1 2969 7 is_stmt 1 view .LVU1677 +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5729 .loc 1 2969 62 is_stmt 0 view .LVU1678 + 5730 03ce 626A ldr r2, [r4, #36] +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5731 .loc 1 2969 50 view .LVU1679 + 5732 03d0 264B ldr r3, .L478+4 + 5733 03d2 33F81220 ldrh r2, [r3, r2, lsl #1] +2969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 5734 .loc 1 2969 26 view .LVU1680 + ARM GAS /tmp/ccizsdzp.s page 199 + + + 5735 03d6 B0FBF2F3 udiv r3, r0, r2 + 5736 .LVL401: +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 5737 .loc 1 2972 7 is_stmt 1 view .LVU1681 +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 5738 .loc 1 2972 50 is_stmt 0 view .LVU1682 + 5739 03da 6568 ldr r5, [r4, #4] +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 5740 .loc 1 2972 37 view .LVU1683 + 5741 03dc 05EB4501 add r1, r5, r5, lsl #1 +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 5742 .loc 1 2972 10 view .LVU1684 + 5743 03e0 9942 cmp r1, r3 + 5744 03e2 00F2E980 bhi .L447 +2972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 5745 .loc 1 2972 62 discriminator 1 view .LVU1685 + 5746 03e6 B3EB053F cmp r3, r5, lsl #12 + 5747 03ea 00F2E780 bhi .L448 +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 5748 .loc 1 2981 9 is_stmt 1 view .LVU1686 +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 5749 .loc 1 2981 31 is_stmt 0 view .LVU1687 + 5750 03ee 0026 movs r6, #0 + 5751 03f0 3346 mov r3, r6 + 5752 .LVL402: +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 5753 .loc 1 2981 31 view .LVU1688 + 5754 03f2 3146 mov r1, r6 + 5755 03f4 FFF7FEFF bl __aeabi_uldivmod + 5756 .LVL403: +2981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 5757 .loc 1 2981 31 view .LVU1689 + 5758 03f8 0902 lsls r1, r1, #8 + 5759 03fa 41EA1061 orr r1, r1, r0, lsr #24 + 5760 03fe 0002 lsls r0, r0, #8 + 5761 0400 6B08 lsrs r3, r5, #1 + 5762 0402 C018 adds r0, r0, r3 + 5763 0404 2A46 mov r2, r5 + 5764 0406 3346 mov r3, r6 + 5765 0408 41F10001 adc r1, r1, #0 + 5766 040c FFF7FEFF bl __aeabi_uldivmod + 5767 .LVL404: +2982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5768 .loc 1 2982 9 is_stmt 1 view .LVU1690 +2982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5769 .loc 1 2982 42 is_stmt 0 view .LVU1691 + 5770 0410 A0F54072 sub r2, r0, #768 +2982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5771 .loc 1 2982 12 view .LVU1692 + 5772 0414 164B ldr r3, .L478+8 + 5773 0416 9A42 cmp r2, r3 + 5774 0418 00F2D280 bhi .L449 +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5775 .loc 1 2984 11 is_stmt 1 view .LVU1693 +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5776 .loc 1 2984 16 is_stmt 0 view .LVU1694 + 5777 041c 2368 ldr r3, [r4] + ARM GAS /tmp/ccizsdzp.s page 200 + + +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5778 .loc 1 2984 32 view .LVU1695 + 5779 041e D860 str r0, [r3, #12] + 5780 0420 3046 mov r0, r6 + 5781 .LVL405: +2984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5782 .loc 1 2984 32 view .LVU1696 + 5783 0422 D4E0 b .L404 + 5784 .LVL406: + 5785 .L473: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5786 .loc 1 2930 5 view .LVU1697 + 5787 0424 0120 movs r0, #1 + 5788 0426 D2E0 b .L404 + 5789 .LVL407: + 5790 .L410: +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5791 .loc 1 2933 9 is_stmt 1 view .LVU1698 +2933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5792 .loc 1 2933 16 is_stmt 0 view .LVU1699 + 5793 0428 FFF7FEFF bl HAL_RCCEx_GetD3PCLK1Freq + 5794 .LVL408: +2934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL2: + 5795 .loc 1 2934 9 is_stmt 1 view .LVU1700 + 5796 .L411: +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5797 .loc 1 2966 5 view .LVU1701 +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5798 .loc 1 2966 8 is_stmt 0 view .LVU1702 + 5799 042c 0028 cmp r0, #0 + 5800 042e CED1 bne .L405 +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5801 .loc 1 2966 8 view .LVU1703 + 5802 0430 0020 movs r0, #0 + 5803 .LVL409: +2966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5804 .loc 1 2966 8 view .LVU1704 + 5805 0432 CCE0 b .L404 + 5806 .L409: +2936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll2_clocks.PLL2_Q_Frequency; + 5807 .loc 1 2936 9 is_stmt 1 view .LVU1705 + 5808 0434 03A8 add r0, sp, #12 + 5809 0436 FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 5810 .LVL410: +2937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5811 .loc 1 2937 9 view .LVU1706 +2937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5812 .loc 1 2937 14 is_stmt 0 view .LVU1707 + 5813 043a 0498 ldr r0, [sp, #16] + 5814 .LVL411: +2938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL3: + 5815 .loc 1 2938 9 is_stmt 1 view .LVU1708 + 5816 043c F6E7 b .L411 + 5817 .LVL412: + 5818 .L408: +2940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll3_clocks.PLL3_Q_Frequency; + 5819 .loc 1 2940 9 view .LVU1709 + ARM GAS /tmp/ccizsdzp.s page 201 + + + 5820 043e 6846 mov r0, sp + 5821 0440 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 5822 .LVL413: +2941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5823 .loc 1 2941 9 view .LVU1710 +2941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5824 .loc 1 2941 14 is_stmt 0 view .LVU1711 + 5825 0444 0198 ldr r0, [sp, #4] + 5826 .LVL414: +2942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 5827 .loc 1 2942 9 is_stmt 1 view .LVU1712 + 5828 0446 F1E7 b .L411 + 5829 .LVL415: + 5830 .L407: +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5831 .loc 1 2944 9 view .LVU1713 +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5832 .loc 1 2944 13 is_stmt 0 view .LVU1714 + 5833 0448 074B ldr r3, .L478 + 5834 044a 1B68 ldr r3, [r3] +2944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5835 .loc 1 2944 12 view .LVU1715 + 5836 044c 13F0200F tst r3, #32 + 5837 0450 08D0 beq .L445 +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5838 .loc 1 2946 11 is_stmt 1 view .LVU1716 +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5839 .loc 1 2946 43 is_stmt 0 view .LVU1717 + 5840 0452 054B ldr r3, .L478 + 5841 0454 1B68 ldr r3, [r3] +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5842 .loc 1 2946 71 view .LVU1718 + 5843 0456 C3F3C103 ubfx r3, r3, #3, #2 +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5844 .loc 1 2946 16 view .LVU1719 + 5845 045a 0648 ldr r0, .L478+12 + 5846 045c D840 lsrs r0, r0, r3 + 5847 .LVL416: +2946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5848 .loc 1 2946 16 view .LVU1720 + 5849 045e E5E7 b .L411 + 5850 .LVL417: + 5851 .L443: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5852 .loc 1 2930 5 view .LVU1721 + 5853 0460 0548 ldr r0, .L478+16 + 5854 0462 B4E7 b .L405 + 5855 .L445: +2950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5856 .loc 1 2950 16 view .LVU1722 + 5857 0464 0348 ldr r0, .L478+12 + 5858 0466 B2E7 b .L405 + 5859 .L479: + 5860 .align 2 + 5861 .L478: + 5862 0468 00440258 .word 1476543488 + 5863 046c 00000000 .word .LANCHOR0 + ARM GAS /tmp/ccizsdzp.s page 202 + + + 5864 0470 FFFC0F00 .word 1047807 + 5865 0474 0090D003 .word 64000000 + 5866 0478 00093D00 .word 4000000 + 5867 .LVL418: + 5868 .L472: +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5869 .loc 1 2996 5 is_stmt 1 view .LVU1723 + 5870 047c 202B cmp r3, #32 + 5871 047e 15D8 bhi .L413 + 5872 0480 202B cmp r3, #32 + 5873 0482 00F29F80 bhi .L450 + 5874 0486 DFE803F0 tbb [pc, r3] + 5875 .L415: + 5876 048a 31 .byte (.L420-.L415)/2 + 5877 048b 37 .byte (.L419-.L415)/2 + 5878 048c 9D .byte (.L450-.L415)/2 + 5879 048d 9D .byte (.L450-.L415)/2 + 5880 048e 3A .byte (.L418-.L415)/2 + 5881 048f 9D .byte (.L450-.L415)/2 + 5882 0490 9D .byte (.L450-.L415)/2 + 5883 0491 9D .byte (.L450-.L415)/2 + 5884 0492 3F .byte (.L417-.L415)/2 + 5885 0493 9D .byte (.L450-.L415)/2 + 5886 0494 9D .byte (.L450-.L415)/2 + 5887 0495 9D .byte (.L450-.L415)/2 + 5888 0496 9D .byte (.L450-.L415)/2 + 5889 0497 9D .byte (.L450-.L415)/2 + 5890 0498 9D .byte (.L450-.L415)/2 + 5891 0499 9D .byte (.L450-.L415)/2 + 5892 049a 44 .byte (.L416-.L415)/2 + 5893 049b 9D .byte (.L450-.L415)/2 + 5894 049c 9D .byte (.L450-.L415)/2 + 5895 049d 9D .byte (.L450-.L415)/2 + 5896 049e 9D .byte (.L450-.L415)/2 + 5897 049f 9D .byte (.L450-.L415)/2 + 5898 04a0 9D .byte (.L450-.L415)/2 + 5899 04a1 9D .byte (.L450-.L415)/2 + 5900 04a2 9D .byte (.L450-.L415)/2 + 5901 04a3 9D .byte (.L450-.L415)/2 + 5902 04a4 9D .byte (.L450-.L415)/2 + 5903 04a5 9D .byte (.L450-.L415)/2 + 5904 04a6 9D .byte (.L450-.L415)/2 + 5905 04a7 9D .byte (.L450-.L415)/2 + 5906 04a8 9D .byte (.L450-.L415)/2 + 5907 04a9 9D .byte (.L450-.L415)/2 + 5908 04aa 50 .byte (.L451-.L415)/2 + 5909 04ab 00 .p2align 1 + 5910 .L413: + 5911 04ac 402B cmp r3, #64 + 5912 04ae 1BD1 bne .L474 + 5913 .LVL419: + 5914 .L414: +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 5915 .loc 1 3037 7 view .LVU1724 +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 5916 .loc 1 3037 29 is_stmt 0 view .LVU1725 + 5917 04b0 626A ldr r2, [r4, #36] + ARM GAS /tmp/ccizsdzp.s page 203 + + + 5918 04b2 4D4B ldr r3, .L480 + 5919 04b4 33F81230 ldrh r3, [r3, r2, lsl #1] + 5920 04b8 B0FBF3F0 udiv r0, r0, r3 + 5921 04bc 6268 ldr r2, [r4, #4] + 5922 04be 5308 lsrs r3, r2, #1 + 5923 04c0 03EB4000 add r0, r3, r0, lsl #1 + 5924 04c4 B0FBF2F0 udiv r0, r0, r2 +3037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 5925 .loc 1 3037 18 view .LVU1726 + 5926 04c8 80B2 uxth r0, r0 + 5927 .LVL420: +3038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5928 .loc 1 3038 7 is_stmt 1 view .LVU1727 +3038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5929 .loc 1 3038 38 is_stmt 0 view .LVU1728 + 5930 04ca A0F11002 sub r2, r0, #16 +3038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5931 .loc 1 3038 10 view .LVU1729 + 5932 04ce 4FF6EF73 movw r3, #65519 + 5933 04d2 9A42 cmp r2, r3 + 5934 04d4 78D8 bhi .L454 +3040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 5935 .loc 1 3040 9 is_stmt 1 view .LVU1730 +3040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 5936 .loc 1 3040 17 is_stmt 0 view .LVU1731 + 5937 04d6 20F00F03 bic r3, r0, #15 + 5938 .LVL421: +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 5939 .loc 1 3041 9 is_stmt 1 view .LVU1732 +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 5940 .loc 1 3041 20 is_stmt 0 view .LVU1733 + 5941 04da C0F34200 ubfx r0, r0, #1, #3 + 5942 .LVL422: +3041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 5943 .loc 1 3041 17 view .LVU1734 + 5944 04de 1843 orrs r0, r0, r3 + 5945 .LVL423: +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5946 .loc 1 3042 9 is_stmt 1 view .LVU1735 +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5947 .loc 1 3042 14 is_stmt 0 view .LVU1736 + 5948 04e0 2368 ldr r3, [r4] +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5949 .loc 1 3042 30 view .LVU1737 + 5950 04e2 D860 str r0, [r3, #12] + 5951 04e4 0020 movs r0, #0 + 5952 .LVL424: +3042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 5953 .loc 1 3042 30 view .LVU1738 + 5954 04e6 72E0 b .L404 + 5955 .LVL425: + 5956 .L474: +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5957 .loc 1 2996 5 view .LVU1739 + 5958 04e8 0120 movs r0, #1 + 5959 04ea 70E0 b .L404 + 5960 .L420: + ARM GAS /tmp/ccizsdzp.s page 204 + + +2999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5961 .loc 1 2999 9 is_stmt 1 view .LVU1740 +2999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5962 .loc 1 2999 16 is_stmt 0 view .LVU1741 + 5963 04ec FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 5964 .LVL426: +3000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D2PCLK2: + 5965 .loc 1 3000 9 is_stmt 1 view .LVU1742 + 5966 .L421: +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5967 .loc 1 3035 5 view .LVU1743 +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5968 .loc 1 3035 8 is_stmt 0 view .LVU1744 + 5969 04f0 0028 cmp r0, #0 + 5970 04f2 DDD1 bne .L414 +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5971 .loc 1 3035 8 view .LVU1745 + 5972 04f4 0020 movs r0, #0 + 5973 .LVL427: +3035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 5974 .loc 1 3035 8 view .LVU1746 + 5975 04f6 6AE0 b .L404 + 5976 .LVL428: + 5977 .L419: +3002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5978 .loc 1 3002 9 is_stmt 1 view .LVU1747 +3002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5979 .loc 1 3002 16 is_stmt 0 view .LVU1748 + 5980 04f8 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 5981 .LVL429: +3003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL2: + 5982 .loc 1 3003 9 is_stmt 1 view .LVU1749 + 5983 04fc F8E7 b .L421 + 5984 .LVL430: + 5985 .L418: +3005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll2_clocks.PLL2_Q_Frequency; + 5986 .loc 1 3005 9 view .LVU1750 + 5987 04fe 03A8 add r0, sp, #12 + 5988 0500 FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 5989 .LVL431: +3006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5990 .loc 1 3006 9 view .LVU1751 +3006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 5991 .loc 1 3006 14 is_stmt 0 view .LVU1752 + 5992 0504 0498 ldr r0, [sp, #16] + 5993 .LVL432: +3007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL3: + 5994 .loc 1 3007 9 is_stmt 1 view .LVU1753 + 5995 0506 F3E7 b .L421 + 5996 .LVL433: + 5997 .L417: +3009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll3_clocks.PLL3_Q_Frequency; + 5998 .loc 1 3009 9 view .LVU1754 + 5999 0508 6846 mov r0, sp + 6000 050a FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 6001 .LVL434: +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + ARM GAS /tmp/ccizsdzp.s page 205 + + + 6002 .loc 1 3010 9 view .LVU1755 +3010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6003 .loc 1 3010 14 is_stmt 0 view .LVU1756 + 6004 050e 0198 ldr r0, [sp, #4] + 6005 .LVL435: +3011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 6006 .loc 1 3011 9 is_stmt 1 view .LVU1757 + 6007 0510 EEE7 b .L421 + 6008 .LVL436: + 6009 .L416: +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6010 .loc 1 3013 9 view .LVU1758 +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6011 .loc 1 3013 13 is_stmt 0 view .LVU1759 + 6012 0512 364B ldr r3, .L480+4 + 6013 .LVL437: +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6014 .loc 1 3013 13 view .LVU1760 + 6015 0514 1B68 ldr r3, [r3] +3013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6016 .loc 1 3013 12 view .LVU1761 + 6017 0516 13F0200F tst r3, #32 + 6018 051a 08D0 beq .L452 +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6019 .loc 1 3015 11 is_stmt 1 view .LVU1762 +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6020 .loc 1 3015 43 is_stmt 0 view .LVU1763 + 6021 051c 334B ldr r3, .L480+4 + 6022 051e 1B68 ldr r3, [r3] +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6023 .loc 1 3015 71 view .LVU1764 + 6024 0520 C3F3C103 ubfx r3, r3, #3, #2 +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6025 .loc 1 3015 16 view .LVU1765 + 6026 0524 3248 ldr r0, .L480+8 + 6027 0526 D840 lsrs r0, r0, r3 + 6028 .LVL438: +3015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6029 .loc 1 3015 16 view .LVU1766 + 6030 0528 E2E7 b .L421 + 6031 .LVL439: + 6032 .L451: +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6033 .loc 1 2996 5 view .LVU1767 + 6034 052a 3248 ldr r0, .L480+12 + 6035 052c C0E7 b .L414 + 6036 .LVL440: + 6037 .L452: +3019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6038 .loc 1 3019 16 view .LVU1768 + 6039 052e 3048 ldr r0, .L480+8 + 6040 0530 BEE7 b .L414 + 6041 .LVL441: + 6042 .L422: +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6043 .loc 1 3052 5 view .LVU1769 + 6044 0532 402B cmp r3, #64 + ARM GAS /tmp/ccizsdzp.s page 206 + + + 6045 0534 17D1 bne .L475 +3082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6046 .loc 1 3082 14 view .LVU1770 + 6047 0536 4FF40040 mov r0, #32768 + 6048 .LVL442: + 6049 .L423: +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 6050 .loc 1 3093 7 is_stmt 1 view .LVU1771 +3093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 6051 .loc 1 3093 29 is_stmt 0 view .LVU1772 + 6052 053a 626A ldr r2, [r4, #36] + 6053 053c 2A4B ldr r3, .L480 + 6054 053e 33F81230 ldrh r3, [r3, r2, lsl #1] + 6055 0542 B0FBF3F0 udiv r0, r0, r3 + 6056 0546 6368 ldr r3, [r4, #4] + 6057 0548 00EB5300 add r0, r0, r3, lsr #1 + 6058 054c B0FBF3F0 udiv r0, r0, r3 + 6059 0550 80B2 uxth r0, r0 + 6060 .LVL443: +3094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6061 .loc 1 3094 7 is_stmt 1 view .LVU1773 +3094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6062 .loc 1 3094 38 is_stmt 0 view .LVU1774 + 6063 0552 A0F11002 sub r2, r0, #16 +3094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6064 .loc 1 3094 10 view .LVU1775 + 6065 0556 4FF6EF73 movw r3, #65519 + 6066 055a 9A42 cmp r2, r3 + 6067 055c 41D8 bhi .L460 +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6068 .loc 1 3096 9 is_stmt 1 view .LVU1776 +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6069 .loc 1 3096 14 is_stmt 0 view .LVU1777 + 6070 055e 2368 ldr r3, [r4] +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6071 .loc 1 3096 30 view .LVU1778 + 6072 0560 D860 str r0, [r3, #12] + 6073 0562 0020 movs r0, #0 + 6074 .LVL444: +3096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6075 .loc 1 3096 30 view .LVU1779 + 6076 0564 33E0 b .L404 + 6077 .LVL445: + 6078 .L475: +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6079 .loc 1 3052 5 view .LVU1780 + 6080 0566 0120 movs r0, #1 + 6081 0568 31E0 b .L404 + 6082 .L429: +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6083 .loc 1 3055 9 is_stmt 1 view .LVU1781 +3055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6084 .loc 1 3055 16 is_stmt 0 view .LVU1782 + 6085 056a FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 6086 .LVL446: +3056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_D2PCLK2: + 6087 .loc 1 3056 9 is_stmt 1 view .LVU1783 + ARM GAS /tmp/ccizsdzp.s page 207 + + + 6088 .L430: +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6089 .loc 1 3090 5 view .LVU1784 +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6090 .loc 1 3090 8 is_stmt 0 view .LVU1785 + 6091 056e 0028 cmp r0, #0 + 6092 0570 E3D1 bne .L423 +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6093 .loc 1 3090 8 view .LVU1786 + 6094 0572 0020 movs r0, #0 + 6095 .LVL447: +3090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6096 .loc 1 3090 8 view .LVU1787 + 6097 0574 2BE0 b .L404 + 6098 .LVL448: + 6099 .L428: +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6100 .loc 1 3058 9 is_stmt 1 view .LVU1788 +3058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6101 .loc 1 3058 16 is_stmt 0 view .LVU1789 + 6102 0576 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 6103 .LVL449: +3059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL2: + 6104 .loc 1 3059 9 is_stmt 1 view .LVU1790 + 6105 057a F8E7 b .L430 + 6106 .LVL450: + 6107 .L427: +3061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll2_clocks.PLL2_Q_Frequency; + 6108 .loc 1 3061 9 view .LVU1791 + 6109 057c 03A8 add r0, sp, #12 + 6110 057e FFF7FEFF bl HAL_RCCEx_GetPLL2ClockFreq + 6111 .LVL451: +3062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6112 .loc 1 3062 9 view .LVU1792 +3062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6113 .loc 1 3062 14 is_stmt 0 view .LVU1793 + 6114 0582 0498 ldr r0, [sp, #16] + 6115 .LVL452: +3063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_PLL3: + 6116 .loc 1 3063 9 is_stmt 1 view .LVU1794 + 6117 0584 F3E7 b .L430 + 6118 .LVL453: + 6119 .L426: +3065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pclk = pll3_clocks.PLL3_Q_Frequency; + 6120 .loc 1 3065 9 view .LVU1795 + 6121 0586 6846 mov r0, sp + 6122 0588 FFF7FEFF bl HAL_RCCEx_GetPLL3ClockFreq + 6123 .LVL454: +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6124 .loc 1 3066 9 view .LVU1796 +3066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** break; + 6125 .loc 1 3066 14 is_stmt 0 view .LVU1797 + 6126 058c 0198 ldr r0, [sp, #4] + 6127 .LVL455: +3067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 6128 .loc 1 3067 9 is_stmt 1 view .LVU1798 + 6129 058e EEE7 b .L430 + ARM GAS /tmp/ccizsdzp.s page 208 + + + 6130 .LVL456: + 6131 .L425: +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6132 .loc 1 3069 9 view .LVU1799 +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6133 .loc 1 3069 13 is_stmt 0 view .LVU1800 + 6134 0590 164B ldr r3, .L480+4 + 6135 .LVL457: +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6136 .loc 1 3069 13 view .LVU1801 + 6137 0592 1B68 ldr r3, [r3] +3069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6138 .loc 1 3069 12 view .LVU1802 + 6139 0594 13F0200F tst r3, #32 + 6140 0598 08D0 beq .L458 +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6141 .loc 1 3071 11 is_stmt 1 view .LVU1803 +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6142 .loc 1 3071 43 is_stmt 0 view .LVU1804 + 6143 059a 144B ldr r3, .L480+4 + 6144 059c 1B68 ldr r3, [r3] +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6145 .loc 1 3071 71 view .LVU1805 + 6146 059e C3F3C103 ubfx r3, r3, #3, #2 +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6147 .loc 1 3071 16 view .LVU1806 + 6148 05a2 1348 ldr r0, .L480+8 + 6149 05a4 D840 lsrs r0, r0, r3 + 6150 .LVL458: +3071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6151 .loc 1 3071 16 view .LVU1807 + 6152 05a6 E2E7 b .L430 + 6153 .LVL459: + 6154 .L456: +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6155 .loc 1 3052 5 view .LVU1808 + 6156 05a8 1248 ldr r0, .L480+12 + 6157 05aa C6E7 b .L423 + 6158 .LVL460: + 6159 .L458: +3075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6160 .loc 1 3075 16 view .LVU1809 + 6161 05ac 1048 ldr r0, .L480+8 + 6162 05ae C4E7 b .L423 + 6163 .LVL461: + 6164 .L441: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6165 .loc 1 2930 5 view .LVU1810 + 6166 05b0 0120 movs r0, #1 + 6167 05b2 0CE0 b .L404 + 6168 .LVL462: + 6169 .L442: +2930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6170 .loc 1 2930 5 view .LVU1811 + 6171 05b4 0120 movs r0, #1 + 6172 05b6 0AE0 b .L404 + 6173 .LVL463: + ARM GAS /tmp/ccizsdzp.s page 209 + + + 6174 .L447: +2975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6175 .loc 1 2975 13 view .LVU1812 + 6176 05b8 0120 movs r0, #1 + 6177 05ba 08E0 b .L404 + 6178 .L448: + 6179 05bc 0120 movs r0, #1 + 6180 05be 06E0 b .L404 + 6181 .LVL464: + 6182 .L449: +2988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6183 .loc 1 2988 15 view .LVU1813 + 6184 05c0 0120 movs r0, #1 + 6185 .LVL465: +2988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6186 .loc 1 2988 15 view .LVU1814 + 6187 05c2 04E0 b .L404 + 6188 .LVL466: + 6189 .L450: +2996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6190 .loc 1 2996 5 view .LVU1815 + 6191 05c4 0120 movs r0, #1 + 6192 05c6 02E0 b .L404 + 6193 .LVL467: + 6194 .L454: +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6195 .loc 1 3046 13 view .LVU1816 + 6196 05c8 0120 movs r0, #1 + 6197 .LVL468: +3046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6198 .loc 1 3046 13 view .LVU1817 + 6199 05ca 00E0 b .L404 + 6200 .LVL469: + 6201 .L455: +3052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6202 .loc 1 3052 5 view .LVU1818 + 6203 05cc 0120 movs r0, #1 + 6204 .LVL470: + 6205 .L404: +3106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->NbRxDataToProcess = 1; + 6206 .loc 1 3106 3 is_stmt 1 view .LVU1819 +3106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->NbRxDataToProcess = 1; + 6207 .loc 1 3106 28 is_stmt 0 view .LVU1820 + 6208 05ce 0123 movs r3, #1 + 6209 05d0 A4F86A30 strh r3, [r4, #106] @ movhi +3107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6210 .loc 1 3107 3 is_stmt 1 view .LVU1821 +3107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6211 .loc 1 3107 28 is_stmt 0 view .LVU1822 + 6212 05d4 A4F86830 strh r3, [r4, #104] @ movhi +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + 6213 .loc 1 3110 3 is_stmt 1 view .LVU1823 +3110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxISR = NULL; + 6214 .loc 1 3110 16 is_stmt 0 view .LVU1824 + 6215 05d8 0023 movs r3, #0 + 6216 05da E366 str r3, [r4, #108] +3111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 210 + + + 6217 .loc 1 3111 3 is_stmt 1 view .LVU1825 +3111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6218 .loc 1 3111 16 is_stmt 0 view .LVU1826 + 6219 05dc 2367 str r3, [r4, #112] +3113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6220 .loc 1 3113 3 is_stmt 1 view .LVU1827 +3114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6221 .loc 1 3114 1 is_stmt 0 view .LVU1828 + 6222 05de 06B0 add sp, sp, #24 + 6223 .LCFI36: + 6224 .cfi_remember_state + 6225 .cfi_def_cfa_offset 16 + 6226 @ sp needed + 6227 05e0 70BD pop {r4, r5, r6, pc} + 6228 .LVL471: + 6229 .L460: + 6230 .LCFI37: + 6231 .cfi_restore_state +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6232 .loc 1 3100 13 view .LVU1829 + 6233 05e2 0120 movs r0, #1 + 6234 .LVL472: +3100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6235 .loc 1 3100 13 view .LVU1830 + 6236 05e4 F3E7 b .L404 + 6237 .L481: + 6238 05e6 00BF .align 2 + 6239 .L480: + 6240 05e8 00000000 .word .LANCHOR0 + 6241 05ec 00440258 .word 1476543488 + 6242 05f0 0090D003 .word 64000000 + 6243 05f4 00093D00 .word 4000000 + 6244 .cfi_endproc + 6245 .LFE183: + 6247 .section .text.UART_AdvFeatureConfig,"ax",%progbits + 6248 .align 1 + 6249 .global UART_AdvFeatureConfig + 6250 .syntax unified + 6251 .thumb + 6252 .thumb_func + 6253 .fpu fpv5-d16 + 6255 UART_AdvFeatureConfig: + 6256 .LVL473: + 6257 .LFB184: +3122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check whether the set of advanced features to configure is properly set */ + 6258 .loc 1 3122 1 is_stmt 1 view -0 + 6259 .cfi_startproc + 6260 @ args = 0, pretend = 0, frame = 0 + 6261 @ frame_needed = 0, uses_anonymous_args = 0 + 6262 @ link register save eliminated. +3124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6263 .loc 1 3124 3 view .LVU1832 +3127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6264 .loc 1 3127 3 view .LVU1833 +3127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6265 .loc 1 3127 7 is_stmt 0 view .LVU1834 + 6266 0000 836A ldr r3, [r0, #40] + ARM GAS /tmp/ccizsdzp.s page 211 + + +3127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6267 .loc 1 3127 6 view .LVU1835 + 6268 0002 13F0010F tst r3, #1 + 6269 0006 06D0 beq .L483 +3129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 6270 .loc 1 3129 5 is_stmt 1 view .LVU1836 +3130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6271 .loc 1 3130 5 view .LVU1837 + 6272 0008 0268 ldr r2, [r0] + 6273 000a 5368 ldr r3, [r2, #4] + 6274 000c 23F40033 bic r3, r3, #131072 + 6275 0010 C16A ldr r1, [r0, #44] + 6276 0012 0B43 orrs r3, r3, r1 + 6277 0014 5360 str r3, [r2, #4] + 6278 .L483: +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6279 .loc 1 3134 3 view .LVU1838 +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6280 .loc 1 3134 7 is_stmt 0 view .LVU1839 + 6281 0016 836A ldr r3, [r0, #40] +3134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6282 .loc 1 3134 6 view .LVU1840 + 6283 0018 13F0020F tst r3, #2 + 6284 001c 06D0 beq .L484 +3136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 6285 .loc 1 3136 5 is_stmt 1 view .LVU1841 +3137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6286 .loc 1 3137 5 view .LVU1842 + 6287 001e 0268 ldr r2, [r0] + 6288 0020 5368 ldr r3, [r2, #4] + 6289 0022 23F48033 bic r3, r3, #65536 + 6290 0026 016B ldr r1, [r0, #48] + 6291 0028 0B43 orrs r3, r3, r1 + 6292 002a 5360 str r3, [r2, #4] + 6293 .L484: +3141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6294 .loc 1 3141 3 view .LVU1843 +3141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6295 .loc 1 3141 7 is_stmt 0 view .LVU1844 + 6296 002c 836A ldr r3, [r0, #40] +3141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6297 .loc 1 3141 6 view .LVU1845 + 6298 002e 13F0040F tst r3, #4 + 6299 0032 06D0 beq .L485 +3143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 6300 .loc 1 3143 5 is_stmt 1 view .LVU1846 +3144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6301 .loc 1 3144 5 view .LVU1847 + 6302 0034 0268 ldr r2, [r0] + 6303 0036 5368 ldr r3, [r2, #4] + 6304 0038 23F48023 bic r3, r3, #262144 + 6305 003c 416B ldr r1, [r0, #52] + 6306 003e 0B43 orrs r3, r3, r1 + 6307 0040 5360 str r3, [r2, #4] + 6308 .L485: +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6309 .loc 1 3148 3 view .LVU1848 + ARM GAS /tmp/ccizsdzp.s page 212 + + +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6310 .loc 1 3148 7 is_stmt 0 view .LVU1849 + 6311 0042 836A ldr r3, [r0, #40] +3148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6312 .loc 1 3148 6 view .LVU1850 + 6313 0044 13F0080F tst r3, #8 + 6314 0048 06D0 beq .L486 +3150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 6315 .loc 1 3150 5 is_stmt 1 view .LVU1851 +3151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6316 .loc 1 3151 5 view .LVU1852 + 6317 004a 0268 ldr r2, [r0] + 6318 004c 5368 ldr r3, [r2, #4] + 6319 004e 23F40043 bic r3, r3, #32768 + 6320 0052 816B ldr r1, [r0, #56] + 6321 0054 0B43 orrs r3, r3, r1 + 6322 0056 5360 str r3, [r2, #4] + 6323 .L486: +3155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6324 .loc 1 3155 3 view .LVU1853 +3155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6325 .loc 1 3155 7 is_stmt 0 view .LVU1854 + 6326 0058 836A ldr r3, [r0, #40] +3155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6327 .loc 1 3155 6 view .LVU1855 + 6328 005a 13F0100F tst r3, #16 + 6329 005e 06D0 beq .L487 +3157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 6330 .loc 1 3157 5 is_stmt 1 view .LVU1856 +3158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6331 .loc 1 3158 5 view .LVU1857 + 6332 0060 0268 ldr r2, [r0] + 6333 0062 9368 ldr r3, [r2, #8] + 6334 0064 23F48053 bic r3, r3, #4096 + 6335 0068 C16B ldr r1, [r0, #60] + 6336 006a 0B43 orrs r3, r3, r1 + 6337 006c 9360 str r3, [r2, #8] + 6338 .L487: +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6339 .loc 1 3162 3 view .LVU1858 +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6340 .loc 1 3162 7 is_stmt 0 view .LVU1859 + 6341 006e 836A ldr r3, [r0, #40] +3162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6342 .loc 1 3162 6 view .LVU1860 + 6343 0070 13F0200F tst r3, #32 + 6344 0074 06D0 beq .L488 +3164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 6345 .loc 1 3164 5 is_stmt 1 view .LVU1861 +3165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6346 .loc 1 3165 5 view .LVU1862 + 6347 0076 0268 ldr r2, [r0] + 6348 0078 9368 ldr r3, [r2, #8] + 6349 007a 23F40053 bic r3, r3, #8192 + 6350 007e 016C ldr r1, [r0, #64] + 6351 0080 0B43 orrs r3, r3, r1 + 6352 0082 9360 str r3, [r2, #8] + ARM GAS /tmp/ccizsdzp.s page 213 + + + 6353 .L488: +3169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6354 .loc 1 3169 3 view .LVU1863 +3169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6355 .loc 1 3169 7 is_stmt 0 view .LVU1864 + 6356 0084 836A ldr r3, [r0, #40] +3169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6357 .loc 1 3169 6 view .LVU1865 + 6358 0086 13F0400F tst r3, #64 + 6359 008a 0AD0 beq .L489 +3171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + 6360 .loc 1 3171 5 is_stmt 1 view .LVU1866 +3172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 6361 .loc 1 3172 5 view .LVU1867 +3173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* set auto Baudrate detection parameters if detection is enabled */ + 6362 .loc 1 3173 5 view .LVU1868 + 6363 008c 0268 ldr r2, [r0] + 6364 008e 5368 ldr r3, [r2, #4] + 6365 0090 23F48013 bic r3, r3, #1048576 + 6366 0094 416C ldr r1, [r0, #68] + 6367 0096 0B43 orrs r3, r3, r1 + 6368 0098 5360 str r3, [r2, #4] +3175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6369 .loc 1 3175 5 view .LVU1869 +3175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6370 .loc 1 3175 28 is_stmt 0 view .LVU1870 + 6371 009a 436C ldr r3, [r0, #68] +3175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6372 .loc 1 3175 8 view .LVU1871 + 6373 009c B3F5801F cmp r3, #1048576 + 6374 00a0 0BD0 beq .L491 + 6375 .L489: +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6376 .loc 1 3183 3 is_stmt 1 view .LVU1872 +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6377 .loc 1 3183 7 is_stmt 0 view .LVU1873 + 6378 00a2 836A ldr r3, [r0, #40] +3183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6379 .loc 1 3183 6 view .LVU1874 + 6380 00a4 13F0800F tst r3, #128 + 6381 00a8 06D0 beq .L482 +3185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 6382 .loc 1 3185 5 is_stmt 1 view .LVU1875 +3186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6383 .loc 1 3186 5 view .LVU1876 + 6384 00aa 0268 ldr r2, [r0] + 6385 00ac 5368 ldr r3, [r2, #4] + 6386 00ae 23F40023 bic r3, r3, #524288 + 6387 00b2 C16C ldr r1, [r0, #76] + 6388 00b4 0B43 orrs r3, r3, r1 + 6389 00b6 5360 str r3, [r2, #4] + 6390 .L482: +3188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6391 .loc 1 3188 1 is_stmt 0 view .LVU1877 + 6392 00b8 7047 bx lr + 6393 .L491: +3177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + ARM GAS /tmp/ccizsdzp.s page 214 + + + 6394 .loc 1 3177 7 is_stmt 1 view .LVU1878 +3178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6395 .loc 1 3178 7 view .LVU1879 + 6396 00ba 0268 ldr r2, [r0] + 6397 00bc 5368 ldr r3, [r2, #4] + 6398 00be 23F4C003 bic r3, r3, #6291456 + 6399 00c2 816C ldr r1, [r0, #72] + 6400 00c4 0B43 orrs r3, r3, r1 + 6401 00c6 5360 str r3, [r2, #4] + 6402 00c8 EBE7 b .L489 + 6403 .cfi_endproc + 6404 .LFE184: + 6406 .section .text.UART_WaitOnFlagUntilTimeout,"ax",%progbits + 6407 .align 1 + 6408 .global UART_WaitOnFlagUntilTimeout + 6409 .syntax unified + 6410 .thumb + 6411 .thumb_func + 6412 .fpu fpv5-d16 + 6414 UART_WaitOnFlagUntilTimeout: + 6415 .LVL474: + 6416 .LFB186: +3247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Wait until flag is set */ + 6417 .loc 1 3247 1 view -0 + 6418 .cfi_startproc + 6419 @ args = 4, pretend = 0, frame = 0 + 6420 @ frame_needed = 0, uses_anonymous_args = 0 +3247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Wait until flag is set */ + 6421 .loc 1 3247 1 is_stmt 0 view .LVU1881 + 6422 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 6423 .LCFI38: + 6424 .cfi_def_cfa_offset 32 + 6425 .cfi_offset 3, -32 + 6426 .cfi_offset 4, -28 + 6427 .cfi_offset 5, -24 + 6428 .cfi_offset 6, -20 + 6429 .cfi_offset 7, -16 + 6430 .cfi_offset 8, -12 + 6431 .cfi_offset 9, -8 + 6432 .cfi_offset 14, -4 + 6433 0004 0546 mov r5, r0 + 6434 0006 0F46 mov r7, r1 + 6435 0008 1646 mov r6, r2 + 6436 000a 9946 mov r9, r3 + 6437 000c DDF82080 ldr r8, [sp, #32] +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6438 .loc 1 3249 3 is_stmt 1 view .LVU1882 + 6439 .LVL475: + 6440 .L494: +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6441 .loc 1 3249 9 view .LVU1883 +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6442 .loc 1 3249 11 is_stmt 0 view .LVU1884 + 6443 0010 2C68 ldr r4, [r5] + 6444 0012 E469 ldr r4, [r4, #28] +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6445 .loc 1 3249 50 view .LVU1885 + ARM GAS /tmp/ccizsdzp.s page 215 + + + 6446 0014 37EA0403 bics r3, r7, r4 + 6447 0018 0CBF ite eq + 6448 001a 4FF0010C moveq ip, #1 + 6449 001e 4FF0000C movne ip, #0 +3249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6450 .loc 1 3249 9 view .LVU1886 + 6451 0022 B445 cmp ip, r6 + 6452 0024 41D1 bne .L500 +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6453 .loc 1 3252 5 is_stmt 1 view .LVU1887 +3252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6454 .loc 1 3252 8 is_stmt 0 view .LVU1888 + 6455 0026 B8F1FF3F cmp r8, #-1 + 6456 002a F1D0 beq .L494 +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6457 .loc 1 3254 7 is_stmt 1 view .LVU1889 +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6458 .loc 1 3254 13 is_stmt 0 view .LVU1890 + 6459 002c FFF7FEFF bl HAL_GetTick + 6460 .LVL476: +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6461 .loc 1 3254 27 view .LVU1891 + 6462 0030 A0EB0900 sub r0, r0, r9 +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6463 .loc 1 3254 10 view .LVU1892 + 6464 0034 4045 cmp r0, r8 + 6465 0036 24D8 bhi .L495 +3254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6466 .loc 1 3254 51 discriminator 1 view .LVU1893 + 6467 0038 B8F1000F cmp r8, #0 + 6468 003c 21D0 beq .L495 +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6469 .loc 1 3268 7 is_stmt 1 view .LVU1894 +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6470 .loc 1 3268 11 is_stmt 0 view .LVU1895 + 6471 003e 2B68 ldr r3, [r5] + 6472 0040 1A68 ldr r2, [r3] +3268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6473 .loc 1 3268 10 view .LVU1896 + 6474 0042 12F0040F tst r2, #4 + 6475 0046 E3D0 beq .L494 +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6476 .loc 1 3270 9 is_stmt 1 view .LVU1897 +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6477 .loc 1 3270 13 is_stmt 0 view .LVU1898 + 6478 0048 DA69 ldr r2, [r3, #28] +3270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6479 .loc 1 3270 12 view .LVU1899 + 6480 004a 12F4006F tst r2, #2048 + 6481 004e DFD0 beq .L494 +3273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6482 .loc 1 3273 11 is_stmt 1 view .LVU1900 + 6483 0050 4FF40062 mov r2, #2048 + 6484 0054 1A62 str r2, [r3, #32] +3276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6485 .loc 1 3276 11 view .LVU1901 + 6486 0056 2A68 ldr r2, [r5] + ARM GAS /tmp/ccizsdzp.s page 216 + + + 6487 0058 1368 ldr r3, [r2] + 6488 005a 23F4D073 bic r3, r3, #416 + 6489 005e 1360 str r3, [r2] +3277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6490 .loc 1 3277 11 view .LVU1902 + 6491 0060 2A68 ldr r2, [r5] + 6492 0062 9368 ldr r3, [r2, #8] + 6493 0064 23F00103 bic r3, r3, #1 + 6494 0068 9360 str r3, [r2, #8] +3279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 6495 .loc 1 3279 11 view .LVU1903 +3279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 6496 .loc 1 3279 25 is_stmt 0 view .LVU1904 + 6497 006a 2023 movs r3, #32 + 6498 006c C5F88030 str r3, [r5, #128] +3280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_RTO; + 6499 .loc 1 3280 11 is_stmt 1 view .LVU1905 +3280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_RTO; + 6500 .loc 1 3280 26 is_stmt 0 view .LVU1906 + 6501 0070 C5F88430 str r3, [r5, #132] +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6502 .loc 1 3281 11 is_stmt 1 view .LVU1907 +3281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6503 .loc 1 3281 28 is_stmt 0 view .LVU1908 + 6504 0074 C5F88830 str r3, [r5, #136] +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6505 .loc 1 3284 11 is_stmt 1 view .LVU1909 +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6506 .loc 1 3284 11 view .LVU1910 + 6507 0078 0023 movs r3, #0 + 6508 007a 85F87C30 strb r3, [r5, #124] +3284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6509 .loc 1 3284 11 view .LVU1911 +3286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6510 .loc 1 3286 11 view .LVU1912 +3286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6511 .loc 1 3286 18 is_stmt 0 view .LVU1913 + 6512 007e 0320 movs r0, #3 + 6513 0080 14E0 b .L497 + 6514 .L495: +3257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6515 .loc 1 3257 9 is_stmt 1 view .LVU1914 + 6516 0082 2A68 ldr r2, [r5] + 6517 0084 1368 ldr r3, [r2] + 6518 0086 23F4D073 bic r3, r3, #416 + 6519 008a 1360 str r3, [r2] +3258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6520 .loc 1 3258 9 view .LVU1915 + 6521 008c 2A68 ldr r2, [r5] + 6522 008e 9368 ldr r3, [r2, #8] + 6523 0090 23F00103 bic r3, r3, #1 + 6524 0094 9360 str r3, [r2, #8] +3260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 6525 .loc 1 3260 9 view .LVU1916 +3260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 6526 .loc 1 3260 23 is_stmt 0 view .LVU1917 + 6527 0096 2023 movs r3, #32 + ARM GAS /tmp/ccizsdzp.s page 217 + + + 6528 0098 C5F88030 str r3, [r5, #128] +3261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6529 .loc 1 3261 9 is_stmt 1 view .LVU1918 +3261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6530 .loc 1 3261 24 is_stmt 0 view .LVU1919 + 6531 009c C5F88430 str r3, [r5, #132] +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6532 .loc 1 3263 9 is_stmt 1 view .LVU1920 +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6533 .loc 1 3263 9 view .LVU1921 + 6534 00a0 0023 movs r3, #0 + 6535 00a2 85F87C30 strb r3, [r5, #124] +3263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6536 .loc 1 3263 9 view .LVU1922 +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6537 .loc 1 3265 9 view .LVU1923 +3265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6538 .loc 1 3265 16 is_stmt 0 view .LVU1924 + 6539 00a6 0320 movs r0, #3 + 6540 00a8 00E0 b .L497 + 6541 .L500: +3291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6542 .loc 1 3291 10 view .LVU1925 + 6543 00aa 0020 movs r0, #0 + 6544 .L497: +3292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6545 .loc 1 3292 1 view .LVU1926 + 6546 00ac BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} +3292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6547 .loc 1 3292 1 view .LVU1927 + 6548 .cfi_endproc + 6549 .LFE186: + 6551 .section .text.HAL_UART_Transmit,"ax",%progbits + 6552 .align 1 + 6553 .global HAL_UART_Transmit + 6554 .syntax unified + 6555 .thumb + 6556 .thumb_func + 6557 .fpu fpv5-d16 + 6559 HAL_UART_Transmit: + 6560 .LVL477: + 6561 .LFB148: +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint8_t *pdata8bits; + 6562 .loc 1 1034 1 is_stmt 1 view -0 + 6563 .cfi_startproc + 6564 @ args = 0, pretend = 0, frame = 0 + 6565 @ frame_needed = 0, uses_anonymous_args = 0 +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint8_t *pdata8bits; + 6566 .loc 1 1034 1 is_stmt 0 view .LVU1929 + 6567 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 6568 .LCFI39: + 6569 .cfi_def_cfa_offset 24 + 6570 .cfi_offset 4, -24 + 6571 .cfi_offset 5, -20 + 6572 .cfi_offset 6, -16 + 6573 .cfi_offset 7, -12 + 6574 .cfi_offset 8, -8 + ARM GAS /tmp/ccizsdzp.s page 218 + + + 6575 .cfi_offset 14, -4 + 6576 0004 82B0 sub sp, sp, #8 + 6577 .LCFI40: + 6578 .cfi_def_cfa_offset 32 + 6579 0006 1E46 mov r6, r3 +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *pdata16bits; + 6580 .loc 1 1035 3 is_stmt 1 view .LVU1930 +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; + 6581 .loc 1 1036 3 view .LVU1931 +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6582 .loc 1 1037 3 view .LVU1932 +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6583 .loc 1 1040 3 view .LVU1933 +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6584 .loc 1 1040 12 is_stmt 0 view .LVU1934 + 6585 0008 D0F88030 ldr r3, [r0, #128] + 6586 .LVL478: +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6587 .loc 1 1040 6 view .LVU1935 + 6588 000c 202B cmp r3, #32 + 6589 000e 58D1 bne .L508 + 6590 0010 0446 mov r4, r0 + 6591 0012 0D46 mov r5, r1 + 6592 0014 9046 mov r8, r2 +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6593 .loc 1 1042 5 is_stmt 1 view .LVU1936 +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6594 .loc 1 1042 8 is_stmt 0 view .LVU1937 + 6595 0016 002A cmp r2, #0 + 6596 0018 18BF it ne + 6597 001a 0029 cmpne r1, #0 + 6598 001c 55D0 beq .L509 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6599 .loc 1 1047 5 is_stmt 1 view .LVU1938 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6600 .loc 1 1047 5 view .LVU1939 + 6601 001e 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 6602 0022 012B cmp r3, #1 + 6603 0024 53D0 beq .L510 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6604 .loc 1 1047 5 discriminator 2 view .LVU1940 + 6605 0026 0123 movs r3, #1 + 6606 0028 80F87C30 strb r3, [r0, #124] +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6607 .loc 1 1047 5 discriminator 2 view .LVU1941 +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 6608 .loc 1 1049 5 discriminator 2 view .LVU1942 +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 6609 .loc 1 1049 22 is_stmt 0 discriminator 2 view .LVU1943 + 6610 002c 0023 movs r3, #0 + 6611 002e C0F88830 str r3, [r0, #136] +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6612 .loc 1 1050 5 is_stmt 1 discriminator 2 view .LVU1944 +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6613 .loc 1 1050 19 is_stmt 0 discriminator 2 view .LVU1945 + 6614 0032 2123 movs r3, #33 + 6615 0034 C0F88030 str r3, [r0, #128] + ARM GAS /tmp/ccizsdzp.s page 219 + + +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6616 .loc 1 1053 5 is_stmt 1 discriminator 2 view .LVU1946 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6617 .loc 1 1053 17 is_stmt 0 discriminator 2 view .LVU1947 + 6618 0038 FFF7FEFF bl HAL_GetTick + 6619 .LVL479: +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6620 .loc 1 1053 17 discriminator 2 view .LVU1948 + 6621 003c 0746 mov r7, r0 + 6622 .LVL480: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; + 6623 .loc 1 1055 5 is_stmt 1 discriminator 2 view .LVU1949 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->TxXferCount = Size; + 6624 .loc 1 1055 24 is_stmt 0 discriminator 2 view .LVU1950 + 6625 003e A4F85480 strh r8, [r4, #84] @ movhi +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6626 .loc 1 1056 5 is_stmt 1 discriminator 2 view .LVU1951 +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6627 .loc 1 1056 24 is_stmt 0 discriminator 2 view .LVU1952 + 6628 0042 A4F85680 strh r8, [r4, #86] @ movhi +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6629 .loc 1 1059 5 is_stmt 1 discriminator 2 view .LVU1953 +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6630 .loc 1 1059 21 is_stmt 0 discriminator 2 view .LVU1954 + 6631 0046 A368 ldr r3, [r4, #8] +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6632 .loc 1 1059 8 discriminator 2 view .LVU1955 + 6633 0048 B3F5805F cmp r3, #4096 + 6634 004c 05D0 beq .L516 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6635 .loc 1 1067 19 view .LVU1956 + 6636 004e 4FF00008 mov r8, #0 + 6637 .LVL481: + 6638 .L503: +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6639 .loc 1 1070 5 is_stmt 1 view .LVU1957 +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6640 .loc 1 1070 5 view .LVU1958 + 6641 0052 0023 movs r3, #0 + 6642 0054 84F87C30 strb r3, [r4, #124] +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6643 .loc 1 1070 5 view .LVU1959 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6644 .loc 1 1072 5 view .LVU1960 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6645 .loc 1 1072 11 is_stmt 0 view .LVU1961 + 6646 0058 12E0 b .L504 + 6647 .LVL482: + 6648 .L516: +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6649 .loc 1 1059 71 discriminator 1 view .LVU1962 + 6650 005a 2369 ldr r3, [r4, #16] +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6651 .loc 1 1059 56 discriminator 1 view .LVU1963 + 6652 005c 13B1 cbz r3, .L512 +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6653 .loc 1 1067 19 view .LVU1964 + ARM GAS /tmp/ccizsdzp.s page 220 + + + 6654 005e 4FF00008 mov r8, #0 + 6655 0062 F6E7 b .L503 + 6656 .L512: +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6657 .loc 1 1062 19 view .LVU1965 + 6658 0064 A846 mov r8, r5 +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; + 6659 .loc 1 1061 19 view .LVU1966 + 6660 0066 0025 movs r5, #0 + 6661 .LVL483: +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; + 6662 .loc 1 1061 19 view .LVU1967 + 6663 0068 F3E7 b .L503 + 6664 .LVL484: + 6665 .L505: +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 6666 .loc 1 1085 9 is_stmt 1 view .LVU1968 +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 6667 .loc 1 1085 42 is_stmt 0 view .LVU1969 + 6668 006a 15F8012B ldrb r2, [r5], #1 @ zero_extendqisi2 + 6669 .LVL485: +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 6670 .loc 1 1085 14 view .LVU1970 + 6671 006e 2368 ldr r3, [r4] +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 6672 .loc 1 1085 30 view .LVU1971 + 6673 0070 9A62 str r2, [r3, #40] +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6674 .loc 1 1086 9 is_stmt 1 view .LVU1972 + 6675 .LVL486: + 6676 .L506: +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6677 .loc 1 1088 7 view .LVU1973 +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6678 .loc 1 1088 12 is_stmt 0 view .LVU1974 + 6679 0072 B4F85620 ldrh r2, [r4, #86] + 6680 0076 92B2 uxth r2, r2 +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6681 .loc 1 1088 25 view .LVU1975 + 6682 0078 013A subs r2, r2, #1 + 6683 007a 92B2 uxth r2, r2 + 6684 007c A4F85620 strh r2, [r4, #86] @ movhi + 6685 .L504: +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6686 .loc 1 1072 11 is_stmt 1 view .LVU1976 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6687 .loc 1 1072 17 is_stmt 0 view .LVU1977 + 6688 0080 B4F85630 ldrh r3, [r4, #86] + 6689 0084 9BB2 uxth r3, r3 +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6690 .loc 1 1072 11 view .LVU1978 + 6691 0086 83B1 cbz r3, .L517 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6692 .loc 1 1074 7 is_stmt 1 view .LVU1979 +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6693 .loc 1 1074 11 is_stmt 0 view .LVU1980 + 6694 0088 0096 str r6, [sp] + ARM GAS /tmp/ccizsdzp.s page 221 + + + 6695 008a 3B46 mov r3, r7 + 6696 008c 0022 movs r2, #0 + 6697 008e 8021 movs r1, #128 + 6698 0090 2046 mov r0, r4 + 6699 0092 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 6700 .LVL487: +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6701 .loc 1 1074 10 view .LVU1981 + 6702 0096 E0B9 cbnz r0, .L513 +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6703 .loc 1 1078 7 is_stmt 1 view .LVU1982 +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6704 .loc 1 1078 10 is_stmt 0 view .LVU1983 + 6705 0098 002D cmp r5, #0 + 6706 009a E6D1 bne .L505 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6707 .loc 1 1080 9 is_stmt 1 view .LVU1984 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6708 .loc 1 1080 43 is_stmt 0 view .LVU1985 + 6709 009c 38F8023B ldrh r3, [r8], #2 + 6710 .LVL488: +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6711 .loc 1 1080 14 view .LVU1986 + 6712 00a0 2268 ldr r2, [r4] +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6713 .loc 1 1080 32 view .LVU1987 + 6714 00a2 C3F30803 ubfx r3, r3, #0, #9 +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6715 .loc 1 1080 30 view .LVU1988 + 6716 00a6 9362 str r3, [r2, #40] +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6717 .loc 1 1081 9 is_stmt 1 view .LVU1989 + 6718 .LVL489: +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6719 .loc 1 1081 9 is_stmt 0 view .LVU1990 + 6720 00a8 E3E7 b .L506 + 6721 .L517: +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6722 .loc 1 1091 5 is_stmt 1 view .LVU1991 +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6723 .loc 1 1091 9 is_stmt 0 view .LVU1992 + 6724 00aa 0096 str r6, [sp] + 6725 00ac 3B46 mov r3, r7 + 6726 00ae 0022 movs r2, #0 + 6727 00b0 4021 movs r1, #64 + 6728 00b2 2046 mov r0, r4 + 6729 00b4 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 6730 .LVL490: +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6731 .loc 1 1091 8 view .LVU1993 + 6732 00b8 68B9 cbnz r0, .L514 +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6733 .loc 1 1097 5 is_stmt 1 view .LVU1994 +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6734 .loc 1 1097 19 is_stmt 0 view .LVU1995 + 6735 00ba 2023 movs r3, #32 + 6736 00bc C4F88030 str r3, [r4, #128] + ARM GAS /tmp/ccizsdzp.s page 222 + + +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6737 .loc 1 1099 5 is_stmt 1 view .LVU1996 +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6738 .loc 1 1099 12 is_stmt 0 view .LVU1997 + 6739 00c0 00E0 b .L502 + 6740 .LVL491: + 6741 .L508: +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6742 .loc 1 1103 12 view .LVU1998 + 6743 00c2 0220 movs r0, #2 + 6744 .LVL492: + 6745 .L502: +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6746 .loc 1 1105 1 view .LVU1999 + 6747 00c4 02B0 add sp, sp, #8 + 6748 .LCFI41: + 6749 .cfi_remember_state + 6750 .cfi_def_cfa_offset 24 + 6751 @ sp needed + 6752 00c6 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 6753 .LVL493: + 6754 .L509: + 6755 .LCFI42: + 6756 .cfi_restore_state +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6757 .loc 1 1044 15 view .LVU2000 + 6758 00ca 0120 movs r0, #1 + 6759 .LVL494: +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6760 .loc 1 1044 15 view .LVU2001 + 6761 00cc FAE7 b .L502 + 6762 .LVL495: + 6763 .L510: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6764 .loc 1 1047 5 view .LVU2002 + 6765 00ce 0220 movs r0, #2 + 6766 .LVL496: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6767 .loc 1 1047 5 view .LVU2003 + 6768 00d0 F8E7 b .L502 + 6769 .LVL497: + 6770 .L513: +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6771 .loc 1 1076 16 view .LVU2004 + 6772 00d2 0320 movs r0, #3 + 6773 00d4 F6E7 b .L502 + 6774 .L514: +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6775 .loc 1 1093 14 view .LVU2005 + 6776 00d6 0320 movs r0, #3 + 6777 00d8 F4E7 b .L502 + 6778 .cfi_endproc + 6779 .LFE148: + 6781 .section .text.HAL_UART_Receive,"ax",%progbits + 6782 .align 1 + 6783 .global HAL_UART_Receive + 6784 .syntax unified + ARM GAS /tmp/ccizsdzp.s page 223 + + + 6785 .thumb + 6786 .thumb_func + 6787 .fpu fpv5-d16 + 6789 HAL_UART_Receive: + 6790 .LVL498: + 6791 .LFB149: +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint8_t *pdata8bits; + 6792 .loc 1 1123 1 is_stmt 1 view -0 + 6793 .cfi_startproc + 6794 @ args = 0, pretend = 0, frame = 0 + 6795 @ frame_needed = 0, uses_anonymous_args = 0 +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint8_t *pdata8bits; + 6796 .loc 1 1123 1 is_stmt 0 view .LVU2007 + 6797 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 6798 .LCFI43: + 6799 .cfi_def_cfa_offset 28 + 6800 .cfi_offset 4, -28 + 6801 .cfi_offset 5, -24 + 6802 .cfi_offset 6, -20 + 6803 .cfi_offset 7, -16 + 6804 .cfi_offset 8, -12 + 6805 .cfi_offset 9, -8 + 6806 .cfi_offset 14, -4 + 6807 0004 83B0 sub sp, sp, #12 + 6808 .LCFI44: + 6809 .cfi_def_cfa_offset 40 + 6810 0006 1E46 mov r6, r3 +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t *pdata16bits; + 6811 .loc 1 1124 3 is_stmt 1 view .LVU2008 +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint16_t uhMask; + 6812 .loc 1 1125 3 view .LVU2009 +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; + 6813 .loc 1 1126 3 view .LVU2010 +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6814 .loc 1 1127 3 view .LVU2011 +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6815 .loc 1 1130 3 view .LVU2012 +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6816 .loc 1 1130 12 is_stmt 0 view .LVU2013 + 6817 0008 D0F88430 ldr r3, [r0, #132] + 6818 .LVL499: +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6819 .loc 1 1130 6 view .LVU2014 + 6820 000c 202B cmp r3, #32 + 6821 000e 7FD1 bne .L532 + 6822 0010 0446 mov r4, r0 + 6823 0012 0D46 mov r5, r1 + 6824 0014 9046 mov r8, r2 +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6825 .loc 1 1132 5 is_stmt 1 view .LVU2015 +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6826 .loc 1 1132 8 is_stmt 0 view .LVU2016 + 6827 0016 002A cmp r2, #0 + 6828 0018 18BF it ne + 6829 001a 0029 cmpne r1, #0 + 6830 001c 7CD0 beq .L533 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 224 + + + 6831 .loc 1 1137 5 is_stmt 1 view .LVU2017 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6832 .loc 1 1137 5 view .LVU2018 + 6833 001e 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 6834 0022 012B cmp r3, #1 + 6835 0024 7AD0 beq .L534 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6836 .loc 1 1137 5 discriminator 2 view .LVU2019 + 6837 0026 0123 movs r3, #1 + 6838 0028 80F87C30 strb r3, [r0, #124] +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6839 .loc 1 1137 5 discriminator 2 view .LVU2020 +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 6840 .loc 1 1139 5 discriminator 2 view .LVU2021 +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 6841 .loc 1 1139 22 is_stmt 0 discriminator 2 view .LVU2022 + 6842 002c 0023 movs r3, #0 + 6843 002e C0F88830 str r3, [r0, #136] +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6844 .loc 1 1140 5 is_stmt 1 discriminator 2 view .LVU2023 +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6845 .loc 1 1140 20 is_stmt 0 discriminator 2 view .LVU2024 + 6846 0032 2223 movs r3, #34 + 6847 0034 C0F88430 str r3, [r0, #132] +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6848 .loc 1 1143 5 is_stmt 1 discriminator 2 view .LVU2025 +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6849 .loc 1 1143 17 is_stmt 0 discriminator 2 view .LVU2026 + 6850 0038 FFF7FEFF bl HAL_GetTick + 6851 .LVL500: +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6852 .loc 1 1143 17 discriminator 2 view .LVU2027 + 6853 003c 0746 mov r7, r0 + 6854 .LVL501: +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = Size; + 6855 .loc 1 1145 5 is_stmt 1 discriminator 2 view .LVU2028 +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxXferCount = Size; + 6856 .loc 1 1145 24 is_stmt 0 discriminator 2 view .LVU2029 + 6857 003e A4F85C80 strh r8, [r4, #92] @ movhi +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6858 .loc 1 1146 5 is_stmt 1 discriminator 2 view .LVU2030 +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6859 .loc 1 1146 24 is_stmt 0 discriminator 2 view .LVU2031 + 6860 0042 A4F85E80 strh r8, [r4, #94] @ movhi +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6861 .loc 1 1149 5 is_stmt 1 discriminator 2 view .LVU2032 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6862 .loc 1 1149 5 discriminator 2 view .LVU2033 + 6863 0046 A368 ldr r3, [r4, #8] + 6864 0048 B3F5805F cmp r3, #4096 + 6865 004c 06D0 beq .L539 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6866 .loc 1 1149 5 discriminator 2 view .LVU2034 + 6867 004e A3B9 cbnz r3, .L523 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6868 .loc 1 1149 5 discriminator 5 view .LVU2035 + 6869 0050 2269 ldr r2, [r4, #16] + ARM GAS /tmp/ccizsdzp.s page 225 + + + 6870 0052 72B9 cbnz r2, .L524 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6871 .loc 1 1149 5 discriminator 7 view .LVU2036 + 6872 0054 FF22 movs r2, #255 + 6873 0056 A4F86020 strh r2, [r4, #96] @ movhi + 6874 005a 14E0 b .L522 + 6875 .L539: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6876 .loc 1 1149 5 discriminator 1 view .LVU2037 + 6877 005c 2269 ldr r2, [r4, #16] + 6878 005e 22B9 cbnz r2, .L521 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6879 .loc 1 1149 5 discriminator 3 view .LVU2038 + 6880 0060 40F2FF12 movw r2, #511 + 6881 0064 A4F86020 strh r2, [r4, #96] @ movhi + 6882 0068 0DE0 b .L522 + 6883 .L521: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6884 .loc 1 1149 5 discriminator 4 view .LVU2039 + 6885 006a FF22 movs r2, #255 + 6886 006c A4F86020 strh r2, [r4, #96] @ movhi + 6887 0070 09E0 b .L522 + 6888 .L524: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6889 .loc 1 1149 5 discriminator 8 view .LVU2040 + 6890 0072 7F22 movs r2, #127 + 6891 0074 A4F86020 strh r2, [r4, #96] @ movhi + 6892 0078 05E0 b .L522 + 6893 .L523: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6894 .loc 1 1149 5 discriminator 6 view .LVU2041 + 6895 007a B3F1805F cmp r3, #268435456 + 6896 007e 0DD0 beq .L540 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6897 .loc 1 1149 5 discriminator 10 view .LVU2042 + 6898 0080 0022 movs r2, #0 + 6899 0082 A4F86020 strh r2, [r4, #96] @ movhi + 6900 .L522: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6901 .loc 1 1149 5 discriminator 13 view .LVU2043 +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6902 .loc 1 1150 5 discriminator 13 view .LVU2044 +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6903 .loc 1 1150 12 is_stmt 0 discriminator 13 view .LVU2045 + 6904 0086 B4F86080 ldrh r8, [r4, #96] + 6905 .LVL502: +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6906 .loc 1 1153 5 is_stmt 1 discriminator 13 view .LVU2046 +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6907 .loc 1 1153 8 is_stmt 0 discriminator 13 view .LVU2047 + 6908 008a B3F5805F cmp r3, #4096 + 6909 008e 0FD0 beq .L541 +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6910 .loc 1 1161 19 view .LVU2048 + 6911 0090 4FF00009 mov r9, #0 + 6912 .LVL503: + 6913 .L527: + ARM GAS /tmp/ccizsdzp.s page 226 + + +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6914 .loc 1 1164 5 is_stmt 1 view .LVU2049 +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6915 .loc 1 1164 5 view .LVU2050 + 6916 0094 0023 movs r3, #0 + 6917 0096 84F87C30 strb r3, [r4, #124] +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 6918 .loc 1 1164 5 view .LVU2051 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6919 .loc 1 1167 5 view .LVU2052 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6920 .loc 1 1167 11 is_stmt 0 view .LVU2053 + 6921 009a 1EE0 b .L528 + 6922 .LVL504: + 6923 .L540: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6924 .loc 1 1149 5 is_stmt 1 discriminator 9 view .LVU2054 + 6925 009c 2269 ldr r2, [r4, #16] + 6926 009e 1AB9 cbnz r2, .L526 +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6927 .loc 1 1149 5 discriminator 11 view .LVU2055 + 6928 00a0 7F22 movs r2, #127 + 6929 00a2 A4F86020 strh r2, [r4, #96] @ movhi + 6930 00a6 EEE7 b .L522 + 6931 .L526: +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uhMask = huart->Mask; + 6932 .loc 1 1149 5 discriminator 12 view .LVU2056 + 6933 00a8 3F22 movs r2, #63 + 6934 00aa A4F86020 strh r2, [r4, #96] @ movhi + 6935 00ae EAE7 b .L522 + 6936 .LVL505: + 6937 .L541: +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6938 .loc 1 1153 71 is_stmt 0 discriminator 1 view .LVU2057 + 6939 00b0 2369 ldr r3, [r4, #16] +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6940 .loc 1 1153 56 discriminator 1 view .LVU2058 + 6941 00b2 13B1 cbz r3, .L536 +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6942 .loc 1 1161 19 view .LVU2059 + 6943 00b4 4FF00009 mov r9, #0 + 6944 00b8 ECE7 b .L527 + 6945 .L536: +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6946 .loc 1 1156 19 view .LVU2060 + 6947 00ba A946 mov r9, r5 +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; + 6948 .loc 1 1155 19 view .LVU2061 + 6949 00bc 0025 movs r5, #0 + 6950 .LVL506: +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; + 6951 .loc 1 1155 19 view .LVU2062 + 6952 00be E9E7 b .L527 + 6953 .LVL507: + 6954 .L543: +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6955 .loc 1 1175 9 is_stmt 1 view .LVU2063 + ARM GAS /tmp/ccizsdzp.s page 227 + + +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6956 .loc 1 1175 40 is_stmt 0 view .LVU2064 + 6957 00c0 2368 ldr r3, [r4] +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6958 .loc 1 1175 50 view .LVU2065 + 6959 00c2 5B6A ldr r3, [r3, #36] +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6960 .loc 1 1175 24 view .LVU2066 + 6961 00c4 08EA0303 and r3, r8, r3 +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata16bits++; + 6962 .loc 1 1175 22 view .LVU2067 + 6963 00c8 29F8023B strh r3, [r9], #2 @ movhi + 6964 .LVL508: +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6965 .loc 1 1176 9 is_stmt 1 view .LVU2068 + 6966 .L530: +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6967 .loc 1 1183 7 view .LVU2069 +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6968 .loc 1 1183 12 is_stmt 0 view .LVU2070 + 6969 00cc B4F85E20 ldrh r2, [r4, #94] + 6970 00d0 92B2 uxth r2, r2 +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 6971 .loc 1 1183 25 view .LVU2071 + 6972 00d2 013A subs r2, r2, #1 + 6973 00d4 92B2 uxth r2, r2 + 6974 00d6 A4F85E20 strh r2, [r4, #94] @ movhi + 6975 .L528: +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6976 .loc 1 1167 11 is_stmt 1 view .LVU2072 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6977 .loc 1 1167 17 is_stmt 0 view .LVU2073 + 6978 00da B4F85E30 ldrh r3, [r4, #94] + 6979 00de 9BB2 uxth r3, r3 +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6980 .loc 1 1167 11 view .LVU2074 + 6981 00e0 8BB1 cbz r3, .L542 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6982 .loc 1 1169 7 is_stmt 1 view .LVU2075 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6983 .loc 1 1169 11 is_stmt 0 view .LVU2076 + 6984 00e2 0096 str r6, [sp] + 6985 00e4 3B46 mov r3, r7 + 6986 00e6 0022 movs r2, #0 + 6987 00e8 2021 movs r1, #32 + 6988 00ea 2046 mov r0, r4 + 6989 00ec FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 6990 .LVL509: +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6991 .loc 1 1169 10 view .LVU2077 + 6992 00f0 B0B9 cbnz r0, .L537 +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6993 .loc 1 1173 7 is_stmt 1 view .LVU2078 +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 6994 .loc 1 1173 10 is_stmt 0 view .LVU2079 + 6995 00f2 002D cmp r5, #0 + 6996 00f4 E4D0 beq .L543 + ARM GAS /tmp/ccizsdzp.s page 228 + + +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 6997 .loc 1 1180 9 is_stmt 1 view .LVU2080 +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 6998 .loc 1 1180 38 is_stmt 0 view .LVU2081 + 6999 00f6 2368 ldr r3, [r4] +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 7000 .loc 1 1180 48 view .LVU2082 + 7001 00f8 5A6A ldr r2, [r3, #36] +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 7002 .loc 1 1180 56 view .LVU2083 + 7003 00fa 5FFA88F3 uxtb r3, r8 +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 7004 .loc 1 1180 23 view .LVU2084 + 7005 00fe 1340 ands r3, r3, r2 +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** pdata8bits++; + 7006 .loc 1 1180 21 view .LVU2085 + 7007 0100 05F8013B strb r3, [r5], #1 + 7008 .LVL510: +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7009 .loc 1 1181 9 is_stmt 1 view .LVU2086 +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7010 .loc 1 1181 9 is_stmt 0 view .LVU2087 + 7011 0104 E2E7 b .L530 + 7012 .L542: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7013 .loc 1 1187 5 is_stmt 1 view .LVU2088 +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7014 .loc 1 1187 20 is_stmt 0 view .LVU2089 + 7015 0106 2023 movs r3, #32 + 7016 0108 C4F88430 str r3, [r4, #132] +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7017 .loc 1 1189 5 is_stmt 1 view .LVU2090 +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7018 .loc 1 1189 12 is_stmt 0 view .LVU2091 + 7019 010c 0020 movs r0, #0 + 7020 010e 00E0 b .L519 + 7021 .LVL511: + 7022 .L532: +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7023 .loc 1 1193 12 view .LVU2092 + 7024 0110 0220 movs r0, #2 + 7025 .LVL512: + 7026 .L519: +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7027 .loc 1 1195 1 view .LVU2093 + 7028 0112 03B0 add sp, sp, #12 + 7029 .LCFI45: + 7030 .cfi_remember_state + 7031 .cfi_def_cfa_offset 28 + 7032 @ sp needed + 7033 0114 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 7034 .LVL513: + 7035 .L533: + 7036 .LCFI46: + 7037 .cfi_restore_state +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7038 .loc 1 1134 15 view .LVU2094 + ARM GAS /tmp/ccizsdzp.s page 229 + + + 7039 0118 0120 movs r0, #1 + 7040 .LVL514: +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7041 .loc 1 1134 15 view .LVU2095 + 7042 011a FAE7 b .L519 + 7043 .LVL515: + 7044 .L534: +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7045 .loc 1 1137 5 view .LVU2096 + 7046 011c 0220 movs r0, #2 + 7047 .LVL516: +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7048 .loc 1 1137 5 view .LVU2097 + 7049 011e F8E7 b .L519 + 7050 .LVL517: + 7051 .L537: +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7052 .loc 1 1171 16 view .LVU2098 + 7053 0120 0320 movs r0, #3 + 7054 0122 F6E7 b .L519 + 7055 .cfi_endproc + 7056 .LFE149: + 7058 .section .text.UART_CheckIdleState,"ax",%progbits + 7059 .align 1 + 7060 .global UART_CheckIdleState + 7061 .syntax unified + 7062 .thumb + 7063 .thumb_func + 7064 .fpu fpv5-d16 + 7066 UART_CheckIdleState: + 7067 .LVL518: + 7068 .LFB185: +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; + 7069 .loc 1 3196 1 is_stmt 1 view -0 + 7070 .cfi_startproc + 7071 @ args = 0, pretend = 0, frame = 0 + 7072 @ frame_needed = 0, uses_anonymous_args = 0 +3196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** uint32_t tickstart; + 7073 .loc 1 3196 1 is_stmt 0 view .LVU2100 + 7074 0000 30B5 push {r4, r5, lr} + 7075 .LCFI47: + 7076 .cfi_def_cfa_offset 12 + 7077 .cfi_offset 4, -12 + 7078 .cfi_offset 5, -8 + 7079 .cfi_offset 14, -4 + 7080 0002 83B0 sub sp, sp, #12 + 7081 .LCFI48: + 7082 .cfi_def_cfa_offset 24 + 7083 0004 0446 mov r4, r0 +3197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7084 .loc 1 3197 3 is_stmt 1 view .LVU2101 +3200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7085 .loc 1 3200 3 view .LVU2102 +3200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7086 .loc 1 3200 20 is_stmt 0 view .LVU2103 + 7087 0006 0023 movs r3, #0 + 7088 0008 C0F88830 str r3, [r0, #136] + ARM GAS /tmp/ccizsdzp.s page 230 + + +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7089 .loc 1 3203 3 is_stmt 1 view .LVU2104 +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7090 .loc 1 3203 15 is_stmt 0 view .LVU2105 + 7091 000c FFF7FEFF bl HAL_GetTick + 7092 .LVL519: +3203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7093 .loc 1 3203 15 view .LVU2106 + 7094 0010 0546 mov r5, r0 + 7095 .LVL520: +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7096 .loc 1 3206 3 is_stmt 1 view .LVU2107 +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7097 .loc 1 3206 13 is_stmt 0 view .LVU2108 + 7098 0012 2268 ldr r2, [r4] +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7099 .loc 1 3206 23 view .LVU2109 + 7100 0014 1268 ldr r2, [r2] +3206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7101 .loc 1 3206 6 view .LVU2110 + 7102 0016 12F0080F tst r2, #8 + 7103 001a 0ED1 bne .L551 + 7104 .LVL521: + 7105 .L545: +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7106 .loc 1 3217 3 is_stmt 1 view .LVU2111 +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7107 .loc 1 3217 13 is_stmt 0 view .LVU2112 + 7108 001c 2368 ldr r3, [r4] +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7109 .loc 1 3217 23 view .LVU2113 + 7110 001e 1B68 ldr r3, [r3] +3217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7111 .loc 1 3217 6 view .LVU2114 + 7112 0020 13F0040F tst r3, #4 + 7113 0024 17D1 bne .L552 + 7114 .L547: +3228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 7115 .loc 1 3228 3 is_stmt 1 view .LVU2115 +3228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 7116 .loc 1 3228 17 is_stmt 0 view .LVU2116 + 7117 0026 2023 movs r3, #32 + 7118 0028 C4F88030 str r3, [r4, #128] +3229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7119 .loc 1 3229 3 is_stmt 1 view .LVU2117 +3229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7120 .loc 1 3229 18 is_stmt 0 view .LVU2118 + 7121 002c C4F88430 str r3, [r4, #132] +3231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7122 .loc 1 3231 3 is_stmt 1 view .LVU2119 +3231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7123 .loc 1 3231 3 view .LVU2120 + 7124 0030 0020 movs r0, #0 + 7125 0032 84F87C00 strb r0, [r4, #124] +3231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7126 .loc 1 3231 3 view .LVU2121 +3233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + ARM GAS /tmp/ccizsdzp.s page 231 + + + 7127 .loc 1 3233 3 view .LVU2122 + 7128 .L546: +3234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7129 .loc 1 3234 1 is_stmt 0 view .LVU2123 + 7130 0036 03B0 add sp, sp, #12 + 7131 .LCFI49: + 7132 .cfi_remember_state + 7133 .cfi_def_cfa_offset 12 + 7134 @ sp needed + 7135 0038 30BD pop {r4, r5, pc} + 7136 .LVL522: + 7137 .L551: + 7138 .LCFI50: + 7139 .cfi_restore_state +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7140 .loc 1 3209 5 is_stmt 1 view .LVU2124 +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7141 .loc 1 3209 9 is_stmt 0 view .LVU2125 + 7142 003a 6FF07E43 mvn r3, #-33554432 + 7143 003e 0093 str r3, [sp] + 7144 0040 0346 mov r3, r0 + 7145 0042 0022 movs r2, #0 + 7146 0044 4FF40011 mov r1, #2097152 + 7147 0048 2046 mov r0, r4 + 7148 .LVL523: +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7149 .loc 1 3209 9 view .LVU2126 + 7150 004a FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 7151 .LVL524: +3209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7152 .loc 1 3209 8 view .LVU2127 + 7153 004e 0028 cmp r0, #0 + 7154 0050 E4D0 beq .L545 +3212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7155 .loc 1 3212 14 view .LVU2128 + 7156 0052 0320 movs r0, #3 + 7157 0054 EFE7 b .L546 + 7158 .L552: +3220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7159 .loc 1 3220 5 is_stmt 1 view .LVU2129 +3220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7160 .loc 1 3220 9 is_stmt 0 view .LVU2130 + 7161 0056 6FF07E43 mvn r3, #-33554432 + 7162 005a 0093 str r3, [sp] + 7163 005c 2B46 mov r3, r5 + 7164 005e 0022 movs r2, #0 + 7165 0060 4FF48001 mov r1, #4194304 + 7166 0064 2046 mov r0, r4 + 7167 0066 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 7168 .LVL525: +3220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7169 .loc 1 3220 8 view .LVU2131 + 7170 006a 0028 cmp r0, #0 + 7171 006c DBD0 beq .L547 +3223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7172 .loc 1 3223 14 view .LVU2132 + 7173 006e 0320 movs r0, #3 + ARM GAS /tmp/ccizsdzp.s page 232 + + + 7174 0070 E1E7 b .L546 + 7175 .cfi_endproc + 7176 .LFE185: + 7178 .section .text.HAL_UART_Init,"ax",%progbits + 7179 .align 1 + 7180 .global HAL_UART_Init + 7181 .syntax unified + 7182 .thumb + 7183 .thumb_func + 7184 .fpu fpv5-d16 + 7186 HAL_UART_Init: + 7187 .LVL526: + 7188 .LFB141: + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7189 .loc 1 298 1 is_stmt 1 view -0 + 7190 .cfi_startproc + 7191 @ args = 0, pretend = 0, frame = 0 + 7192 @ frame_needed = 0, uses_anonymous_args = 0 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7193 .loc 1 300 3 view .LVU2134 + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7194 .loc 1 300 6 is_stmt 0 view .LVU2135 + 7195 0000 78B3 cbz r0, .L557 + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7196 .loc 1 298 1 view .LVU2136 + 7197 0002 10B5 push {r4, lr} + 7198 .LCFI51: + 7199 .cfi_def_cfa_offset 8 + 7200 .cfi_offset 4, -8 + 7201 .cfi_offset 14, -4 + 7202 0004 0446 mov r4, r0 + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7203 .loc 1 305 3 is_stmt 1 view .LVU2137 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7204 .loc 1 313 5 view .LVU2138 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7205 .loc 1 316 3 view .LVU2139 + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7206 .loc 1 316 12 is_stmt 0 view .LVU2140 + 7207 0006 D0F88030 ldr r3, [r0, #128] + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7208 .loc 1 316 6 view .LVU2141 + 7209 000a 0BB3 cbz r3, .L562 + 7210 .LVL527: + 7211 .L555: + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7212 .loc 1 337 3 is_stmt 1 view .LVU2142 + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7213 .loc 1 337 17 is_stmt 0 view .LVU2143 + 7214 000c 2423 movs r3, #36 + 7215 000e C4F88030 str r3, [r4, #128] + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7216 .loc 1 339 3 is_stmt 1 view .LVU2144 + 7217 0012 2268 ldr r2, [r4] + 7218 0014 1368 ldr r3, [r2] + 7219 0016 23F00103 bic r3, r3, #1 + 7220 001a 1360 str r3, [r2] + ARM GAS /tmp/ccizsdzp.s page 233 + + + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7221 .loc 1 342 3 view .LVU2145 + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7222 .loc 1 342 7 is_stmt 0 view .LVU2146 + 7223 001c 2046 mov r0, r4 + 7224 001e FFF7FEFF bl UART_SetConfig + 7225 .LVL528: + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7226 .loc 1 342 6 view .LVU2147 + 7227 0022 0128 cmp r0, #1 + 7228 0024 13D0 beq .L554 + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7229 .loc 1 347 3 is_stmt 1 view .LVU2148 + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7230 .loc 1 347 26 is_stmt 0 view .LVU2149 + 7231 0026 A36A ldr r3, [r4, #40] + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7232 .loc 1 347 6 view .LVU2150 + 7233 0028 BBB9 cbnz r3, .L563 + 7234 .L556: + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 7235 .loc 1 355 3 is_stmt 1 view .LVU2151 + 7236 002a 2268 ldr r2, [r4] + 7237 002c 5368 ldr r3, [r2, #4] + 7238 002e 23F49043 bic r3, r3, #18432 + 7239 0032 5360 str r3, [r2, #4] + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7240 .loc 1 356 3 view .LVU2152 + 7241 0034 2268 ldr r2, [r4] + 7242 0036 9368 ldr r3, [r2, #8] + 7243 0038 23F02A03 bic r3, r3, #42 + 7244 003c 9360 str r3, [r2, #8] + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7245 .loc 1 358 3 view .LVU2153 + 7246 003e 2268 ldr r2, [r4] + 7247 0040 1368 ldr r3, [r2] + 7248 0042 43F00103 orr r3, r3, #1 + 7249 0046 1360 str r3, [r2] + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7250 .loc 1 361 3 view .LVU2154 + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7251 .loc 1 361 11 is_stmt 0 view .LVU2155 + 7252 0048 2046 mov r0, r4 + 7253 004a FFF7FEFF bl UART_CheckIdleState + 7254 .LVL529: + 7255 .L554: + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7256 .loc 1 362 1 view .LVU2156 + 7257 004e 10BD pop {r4, pc} + 7258 .LVL530: + 7259 .L562: + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7260 .loc 1 319 5 is_stmt 1 view .LVU2157 + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7261 .loc 1 319 17 is_stmt 0 view .LVU2158 + 7262 0050 80F87C30 strb r3, [r0, #124] + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + ARM GAS /tmp/ccizsdzp.s page 234 + + + 7263 .loc 1 333 5 is_stmt 1 view .LVU2159 + 7264 0054 FFF7FEFF bl HAL_UART_MspInit + 7265 .LVL531: + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7266 .loc 1 333 5 is_stmt 0 view .LVU2160 + 7267 0058 D8E7 b .L555 + 7268 .L563: + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7269 .loc 1 349 5 is_stmt 1 view .LVU2161 + 7270 005a 2046 mov r0, r4 + 7271 005c FFF7FEFF bl UART_AdvFeatureConfig + 7272 .LVL532: + 7273 0060 E3E7 b .L556 + 7274 .LVL533: + 7275 .L557: + 7276 .LCFI52: + 7277 .cfi_def_cfa_offset 0 + 7278 .cfi_restore 4 + 7279 .cfi_restore 14 + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7280 .loc 1 302 12 is_stmt 0 view .LVU2162 + 7281 0062 0120 movs r0, #1 + 7282 .LVL534: + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7283 .loc 1 362 1 view .LVU2163 + 7284 0064 7047 bx lr + 7285 .cfi_endproc + 7286 .LFE141: + 7288 .section .text.HAL_HalfDuplex_Init,"ax",%progbits + 7289 .align 1 + 7290 .global HAL_HalfDuplex_Init + 7291 .syntax unified + 7292 .thumb + 7293 .thumb_func + 7294 .fpu fpv5-d16 + 7296 HAL_HalfDuplex_Init: + 7297 .LVL535: + 7298 .LFB142: + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7299 .loc 1 371 1 is_stmt 1 view -0 + 7300 .cfi_startproc + 7301 @ args = 0, pretend = 0, frame = 0 + 7302 @ frame_needed = 0, uses_anonymous_args = 0 + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7303 .loc 1 373 3 view .LVU2165 + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7304 .loc 1 373 6 is_stmt 0 view .LVU2166 + 7305 0000 0028 cmp r0, #0 + 7306 0002 34D0 beq .L568 + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7307 .loc 1 371 1 view .LVU2167 + 7308 0004 10B5 push {r4, lr} + 7309 .LCFI53: + 7310 .cfi_def_cfa_offset 8 + 7311 .cfi_offset 4, -8 + 7312 .cfi_offset 14, -4 + 7313 0006 0446 mov r4, r0 + ARM GAS /tmp/ccizsdzp.s page 235 + + + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7314 .loc 1 379 3 is_stmt 1 view .LVU2168 + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7315 .loc 1 381 3 view .LVU2169 + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7316 .loc 1 381 12 is_stmt 0 view .LVU2170 + 7317 0008 D0F88030 ldr r3, [r0, #128] + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7318 .loc 1 381 6 view .LVU2171 + 7319 000c 33B3 cbz r3, .L573 + 7320 .LVL536: + 7321 .L566: + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7322 .loc 1 402 3 is_stmt 1 view .LVU2172 + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7323 .loc 1 402 17 is_stmt 0 view .LVU2173 + 7324 000e 2423 movs r3, #36 + 7325 0010 C4F88030 str r3, [r4, #128] + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7326 .loc 1 404 3 is_stmt 1 view .LVU2174 + 7327 0014 2268 ldr r2, [r4] + 7328 0016 1368 ldr r3, [r2] + 7329 0018 23F00103 bic r3, r3, #1 + 7330 001c 1360 str r3, [r2] + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7331 .loc 1 407 3 view .LVU2175 + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7332 .loc 1 407 7 is_stmt 0 view .LVU2176 + 7333 001e 2046 mov r0, r4 + 7334 0020 FFF7FEFF bl UART_SetConfig + 7335 .LVL537: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7336 .loc 1 407 6 view .LVU2177 + 7337 0024 0128 cmp r0, #1 + 7338 0026 18D0 beq .L565 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7339 .loc 1 412 3 is_stmt 1 view .LVU2178 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7340 .loc 1 412 26 is_stmt 0 view .LVU2179 + 7341 0028 A36A ldr r3, [r4, #40] + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7342 .loc 1 412 6 view .LVU2180 + 7343 002a E3B9 cbnz r3, .L574 + 7344 .L567: + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + 7345 .loc 1 420 3 is_stmt 1 view .LVU2181 + 7346 002c 2268 ldr r2, [r4] + 7347 002e 5368 ldr r3, [r2, #4] + 7348 0030 23F49043 bic r3, r3, #18432 + 7349 0034 5360 str r3, [r2, #4] + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7350 .loc 1 421 3 view .LVU2182 + 7351 0036 2268 ldr r2, [r4] + 7352 0038 9368 ldr r3, [r2, #8] + 7353 003a 23F02203 bic r3, r3, #34 + 7354 003e 9360 str r3, [r2, #8] + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 236 + + + 7355 .loc 1 424 3 view .LVU2183 + 7356 0040 2268 ldr r2, [r4] + 7357 0042 9368 ldr r3, [r2, #8] + 7358 0044 43F00803 orr r3, r3, #8 + 7359 0048 9360 str r3, [r2, #8] + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7360 .loc 1 426 3 view .LVU2184 + 7361 004a 2268 ldr r2, [r4] + 7362 004c 1368 ldr r3, [r2] + 7363 004e 43F00103 orr r3, r3, #1 + 7364 0052 1360 str r3, [r2] + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7365 .loc 1 429 3 view .LVU2185 + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7366 .loc 1 429 11 is_stmt 0 view .LVU2186 + 7367 0054 2046 mov r0, r4 + 7368 0056 FFF7FEFF bl UART_CheckIdleState + 7369 .LVL538: + 7370 .L565: + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7371 .loc 1 430 1 view .LVU2187 + 7372 005a 10BD pop {r4, pc} + 7373 .LVL539: + 7374 .L573: + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7375 .loc 1 384 5 is_stmt 1 view .LVU2188 + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7376 .loc 1 384 17 is_stmt 0 view .LVU2189 + 7377 005c 80F87C30 strb r3, [r0, #124] + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7378 .loc 1 398 5 is_stmt 1 view .LVU2190 + 7379 0060 FFF7FEFF bl HAL_UART_MspInit + 7380 .LVL540: + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7381 .loc 1 398 5 is_stmt 0 view .LVU2191 + 7382 0064 D3E7 b .L566 + 7383 .L574: + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7384 .loc 1 414 5 is_stmt 1 view .LVU2192 + 7385 0066 2046 mov r0, r4 + 7386 0068 FFF7FEFF bl UART_AdvFeatureConfig + 7387 .LVL541: + 7388 006c DEE7 b .L567 + 7389 .LVL542: + 7390 .L568: + 7391 .LCFI54: + 7392 .cfi_def_cfa_offset 0 + 7393 .cfi_restore 4 + 7394 .cfi_restore 14 + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7395 .loc 1 375 12 is_stmt 0 view .LVU2193 + 7396 006e 0120 movs r0, #1 + 7397 .LVL543: + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7398 .loc 1 430 1 view .LVU2194 + 7399 0070 7047 bx lr + 7400 .cfi_endproc + ARM GAS /tmp/ccizsdzp.s page 237 + + + 7401 .LFE142: + 7403 .section .text.HAL_LIN_Init,"ax",%progbits + 7404 .align 1 + 7405 .global HAL_LIN_Init + 7406 .syntax unified + 7407 .thumb + 7408 .thumb_func + 7409 .fpu fpv5-d16 + 7411 HAL_LIN_Init: + 7412 .LVL544: + 7413 .LFB143: + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7414 .loc 1 444 1 is_stmt 1 view -0 + 7415 .cfi_startproc + 7416 @ args = 0, pretend = 0, frame = 0 + 7417 @ frame_needed = 0, uses_anonymous_args = 0 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7418 .loc 1 446 3 view .LVU2196 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7419 .loc 1 446 6 is_stmt 0 view .LVU2197 + 7420 0000 0028 cmp r0, #0 + 7421 0002 42D0 beq .L579 + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7422 .loc 1 444 1 view .LVU2198 + 7423 0004 38B5 push {r3, r4, r5, lr} + 7424 .LCFI55: + 7425 .cfi_def_cfa_offset 16 + 7426 .cfi_offset 3, -16 + 7427 .cfi_offset 4, -12 + 7428 .cfi_offset 5, -8 + 7429 .cfi_offset 14, -4 + 7430 0006 0D46 mov r5, r1 + 7431 0008 0446 mov r4, r0 + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the Break detection length parameter */ + 7432 .loc 1 452 3 is_stmt 1 view .LVU2199 + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7433 .loc 1 454 3 view .LVU2200 + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7434 .loc 1 457 3 view .LVU2201 + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7435 .loc 1 457 18 is_stmt 0 view .LVU2202 + 7436 000a C369 ldr r3, [r0, #28] + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7437 .loc 1 457 6 view .LVU2203 + 7438 000c B3F5004F cmp r3, #32768 + 7439 0010 3DD0 beq .L580 + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7440 .loc 1 462 3 is_stmt 1 view .LVU2204 + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7441 .loc 1 462 18 is_stmt 0 view .LVU2205 + 7442 0012 8368 ldr r3, [r0, #8] + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7443 .loc 1 462 6 view .LVU2206 + 7444 0014 002B cmp r3, #0 + 7445 0016 3CD1 bne .L581 + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7446 .loc 1 467 3 is_stmt 1 view .LVU2207 + ARM GAS /tmp/ccizsdzp.s page 238 + + + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7447 .loc 1 467 12 is_stmt 0 view .LVU2208 + 7448 0018 D0F88030 ldr r3, [r0, #128] + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7449 .loc 1 467 6 view .LVU2209 + 7450 001c 63B3 cbz r3, .L586 + 7451 .LVL545: + 7452 .L577: + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7453 .loc 1 488 3 is_stmt 1 view .LVU2210 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7454 .loc 1 488 17 is_stmt 0 view .LVU2211 + 7455 001e 2423 movs r3, #36 + 7456 0020 C4F88030 str r3, [r4, #128] + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7457 .loc 1 490 3 is_stmt 1 view .LVU2212 + 7458 0024 2268 ldr r2, [r4] + 7459 0026 1368 ldr r3, [r2] + 7460 0028 23F00103 bic r3, r3, #1 + 7461 002c 1360 str r3, [r2] + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7462 .loc 1 493 3 view .LVU2213 + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7463 .loc 1 493 7 is_stmt 0 view .LVU2214 + 7464 002e 2046 mov r0, r4 + 7465 0030 FFF7FEFF bl UART_SetConfig + 7466 .LVL546: + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7467 .loc 1 493 6 view .LVU2215 + 7468 0034 0128 cmp r0, #1 + 7469 0036 1ED0 beq .L576 + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7470 .loc 1 498 3 is_stmt 1 view .LVU2216 + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7471 .loc 1 498 26 is_stmt 0 view .LVU2217 + 7472 0038 A36A ldr r3, [r4, #40] + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7473 .loc 1 498 6 view .LVU2218 + 7474 003a 13BB cbnz r3, .L587 + 7475 .L578: + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + 7476 .loc 1 506 3 is_stmt 1 view .LVU2219 + 7477 003c 2268 ldr r2, [r4] + 7478 003e 5368 ldr r3, [r2, #4] + 7479 0040 23F40063 bic r3, r3, #2048 + 7480 0044 5360 str r3, [r2, #4] + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7481 .loc 1 507 3 view .LVU2220 + 7482 0046 2268 ldr r2, [r4] + 7483 0048 9368 ldr r3, [r2, #8] + 7484 004a 23F02A03 bic r3, r3, #42 + 7485 004e 9360 str r3, [r2, #8] + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7486 .loc 1 510 3 view .LVU2221 + 7487 0050 2268 ldr r2, [r4] + 7488 0052 5368 ldr r3, [r2, #4] + 7489 0054 43F48043 orr r3, r3, #16384 + ARM GAS /tmp/ccizsdzp.s page 239 + + + 7490 0058 5360 str r3, [r2, #4] + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7491 .loc 1 513 3 view .LVU2222 + 7492 005a 2268 ldr r2, [r4] + 7493 005c 5368 ldr r3, [r2, #4] + 7494 005e 23F02003 bic r3, r3, #32 + 7495 0062 2B43 orrs r3, r3, r5 + 7496 0064 5360 str r3, [r2, #4] + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7497 .loc 1 515 3 view .LVU2223 + 7498 0066 2268 ldr r2, [r4] + 7499 0068 1368 ldr r3, [r2] + 7500 006a 43F00103 orr r3, r3, #1 + 7501 006e 1360 str r3, [r2] + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7502 .loc 1 518 3 view .LVU2224 + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7503 .loc 1 518 11 is_stmt 0 view .LVU2225 + 7504 0070 2046 mov r0, r4 + 7505 0072 FFF7FEFF bl UART_CheckIdleState + 7506 .LVL547: + 7507 .L576: + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7508 .loc 1 519 1 view .LVU2226 + 7509 0076 38BD pop {r3, r4, r5, pc} + 7510 .LVL548: + 7511 .L586: + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7512 .loc 1 470 5 is_stmt 1 view .LVU2227 + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7513 .loc 1 470 17 is_stmt 0 view .LVU2228 + 7514 0078 80F87C30 strb r3, [r0, #124] + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7515 .loc 1 484 5 is_stmt 1 view .LVU2229 + 7516 007c FFF7FEFF bl HAL_UART_MspInit + 7517 .LVL549: + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7518 .loc 1 484 5 is_stmt 0 view .LVU2230 + 7519 0080 CDE7 b .L577 + 7520 .L587: + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7521 .loc 1 500 5 is_stmt 1 view .LVU2231 + 7522 0082 2046 mov r0, r4 + 7523 0084 FFF7FEFF bl UART_AdvFeatureConfig + 7524 .LVL550: + 7525 0088 D8E7 b .L578 + 7526 .LVL551: + 7527 .L579: + 7528 .LCFI56: + 7529 .cfi_def_cfa_offset 0 + 7530 .cfi_restore 3 + 7531 .cfi_restore 4 + 7532 .cfi_restore 5 + 7533 .cfi_restore 14 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7534 .loc 1 448 12 is_stmt 0 view .LVU2232 + 7535 008a 0120 movs r0, #1 + ARM GAS /tmp/ccizsdzp.s page 240 + + + 7536 .LVL552: + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7537 .loc 1 519 1 view .LVU2233 + 7538 008c 7047 bx lr + 7539 .LVL553: + 7540 .L580: + 7541 .LCFI57: + 7542 .cfi_def_cfa_offset 16 + 7543 .cfi_offset 3, -16 + 7544 .cfi_offset 4, -12 + 7545 .cfi_offset 5, -8 + 7546 .cfi_offset 14, -4 + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7547 .loc 1 459 12 view .LVU2234 + 7548 008e 0120 movs r0, #1 + 7549 .LVL554: + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7550 .loc 1 459 12 view .LVU2235 + 7551 0090 F1E7 b .L576 + 7552 .LVL555: + 7553 .L581: + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7554 .loc 1 464 12 view .LVU2236 + 7555 0092 0120 movs r0, #1 + 7556 .LVL556: + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7557 .loc 1 464 12 view .LVU2237 + 7558 0094 EFE7 b .L576 + 7559 .cfi_endproc + 7560 .LFE143: + 7562 .section .text.HAL_MultiProcessor_Init,"ax",%progbits + 7563 .align 1 + 7564 .global HAL_MultiProcessor_Init + 7565 .syntax unified + 7566 .thumb + 7567 .thumb_func + 7568 .fpu fpv5-d16 + 7570 HAL_MultiProcessor_Init: + 7571 .LVL557: + 7572 .LFB144: + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7573 .loc 1 541 1 is_stmt 1 view -0 + 7574 .cfi_startproc + 7575 @ args = 0, pretend = 0, frame = 0 + 7576 @ frame_needed = 0, uses_anonymous_args = 0 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7577 .loc 1 543 3 view .LVU2239 + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7578 .loc 1 543 6 is_stmt 0 view .LVU2240 + 7579 0000 0028 cmp r0, #0 + 7580 0002 42D0 beq .L593 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** /* Check the UART handle allocation */ + 7581 .loc 1 541 1 view .LVU2241 + 7582 0004 70B5 push {r4, r5, r6, lr} + 7583 .LCFI58: + 7584 .cfi_def_cfa_offset 16 + 7585 .cfi_offset 4, -16 + ARM GAS /tmp/ccizsdzp.s page 241 + + + 7586 .cfi_offset 5, -12 + 7587 .cfi_offset 6, -8 + 7588 .cfi_offset 14, -4 + 7589 0006 0E46 mov r6, r1 + 7590 0008 1546 mov r5, r2 + 7591 000a 0446 mov r4, r0 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7592 .loc 1 549 3 is_stmt 1 view .LVU2242 + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7593 .loc 1 551 3 view .LVU2243 + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7594 .loc 1 551 12 is_stmt 0 view .LVU2244 + 7595 000c D0F88030 ldr r3, [r0, #128] + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7596 .loc 1 551 6 view .LVU2245 + 7597 0010 53B3 cbz r3, .L598 + 7598 .LVL558: + 7599 .L590: + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7600 .loc 1 572 3 is_stmt 1 view .LVU2246 + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7601 .loc 1 572 17 is_stmt 0 view .LVU2247 + 7602 0012 2423 movs r3, #36 + 7603 0014 C4F88030 str r3, [r4, #128] + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7604 .loc 1 574 3 is_stmt 1 view .LVU2248 + 7605 0018 2268 ldr r2, [r4] + 7606 001a 1368 ldr r3, [r2] + 7607 001c 23F00103 bic r3, r3, #1 + 7608 0020 1360 str r3, [r2] + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7609 .loc 1 577 3 view .LVU2249 + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7610 .loc 1 577 7 is_stmt 0 view .LVU2250 + 7611 0022 2046 mov r0, r4 + 7612 0024 FFF7FEFF bl UART_SetConfig + 7613 .LVL559: + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7614 .loc 1 577 6 view .LVU2251 + 7615 0028 0128 cmp r0, #1 + 7616 002a 1CD0 beq .L589 + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7617 .loc 1 582 3 is_stmt 1 view .LVU2252 + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7618 .loc 1 582 26 is_stmt 0 view .LVU2253 + 7619 002c A36A ldr r3, [r4, #40] + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7620 .loc 1 582 6 view .LVU2254 + 7621 002e 03BB cbnz r3, .L599 + 7622 .L591: + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 7623 .loc 1 590 3 is_stmt 1 view .LVU2255 + 7624 0030 2268 ldr r2, [r4] + 7625 0032 5368 ldr r3, [r2, #4] + 7626 0034 23F49043 bic r3, r3, #18432 + 7627 0038 5360 str r3, [r2, #4] + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + ARM GAS /tmp/ccizsdzp.s page 242 + + + 7628 .loc 1 591 3 view .LVU2256 + 7629 003a 2268 ldr r2, [r4] + 7630 003c 9368 ldr r3, [r2, #8] + 7631 003e 23F02A03 bic r3, r3, #42 + 7632 0042 9360 str r3, [r2, #8] + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7633 .loc 1 593 3 view .LVU2257 + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** { + 7634 .loc 1 593 6 is_stmt 0 view .LVU2258 + 7635 0044 B5F5006F cmp r5, #2048 + 7636 0048 17D0 beq .L600 + 7637 .L592: + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7638 .loc 1 600 3 is_stmt 1 view .LVU2259 + 7639 004a 2368 ldr r3, [r4] + 7640 004c 1A68 ldr r2, [r3] + 7641 004e 22F40062 bic r2, r2, #2048 + 7642 0052 1543 orrs r5, r5, r2 + 7643 .LVL560: + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7644 .loc 1 600 3 is_stmt 0 view .LVU2260 + 7645 0054 1D60 str r5, [r3] + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7646 .loc 1 602 3 is_stmt 1 view .LVU2261 + 7647 0056 2268 ldr r2, [r4] + 7648 0058 1368 ldr r3, [r2] + 7649 005a 43F00103 orr r3, r3, #1 + 7650 005e 1360 str r3, [r2] + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7651 .loc 1 605 3 view .LVU2262 + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7652 .loc 1 605 11 is_stmt 0 view .LVU2263 + 7653 0060 2046 mov r0, r4 + 7654 0062 FFF7FEFF bl UART_CheckIdleState + 7655 .LVL561: + 7656 .L589: + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7657 .loc 1 606 1 view .LVU2264 + 7658 0066 70BD pop {r4, r5, r6, pc} + 7659 .LVL562: + 7660 .L598: + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7661 .loc 1 554 5 is_stmt 1 view .LVU2265 + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7662 .loc 1 554 17 is_stmt 0 view .LVU2266 + 7663 0068 80F87C30 strb r3, [r0, #124] + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7664 .loc 1 568 5 is_stmt 1 view .LVU2267 + 7665 006c FFF7FEFF bl HAL_UART_MspInit + 7666 .LVL563: + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 7667 .loc 1 568 5 is_stmt 0 view .LVU2268 + 7668 0070 CFE7 b .L590 + 7669 .L599: + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7670 .loc 1 584 5 is_stmt 1 view .LVU2269 + 7671 0072 2046 mov r0, r4 + ARM GAS /tmp/ccizsdzp.s page 243 + + + 7672 0074 FFF7FEFF bl UART_AdvFeatureConfig + 7673 .LVL564: + 7674 0078 DAE7 b .L591 + 7675 .L600: + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7676 .loc 1 596 5 view .LVU2270 + 7677 007a 2368 ldr r3, [r4] + 7678 007c 5968 ldr r1, [r3, #4] + 7679 007e 21F07F41 bic r1, r1, #-16777216 + 7680 0082 41EA0666 orr r6, r1, r6, lsl #24 + 7681 0086 5E60 str r6, [r3, #4] + 7682 0088 DFE7 b .L592 + 7683 .LVL565: + 7684 .L593: + 7685 .LCFI59: + 7686 .cfi_def_cfa_offset 0 + 7687 .cfi_restore 4 + 7688 .cfi_restore 5 + 7689 .cfi_restore 6 + 7690 .cfi_restore 14 + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7691 .loc 1 545 12 is_stmt 0 view .LVU2271 + 7692 008a 0120 movs r0, #1 + 7693 .LVL566: + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7694 .loc 1 606 1 view .LVU2272 + 7695 008c 7047 bx lr + 7696 .cfi_endproc + 7697 .LFE144: + 7699 .section .text.HAL_MultiProcessor_EnableMuteMode,"ax",%progbits + 7700 .align 1 + 7701 .global HAL_MultiProcessor_EnableMuteMode + 7702 .syntax unified + 7703 .thumb + 7704 .thumb_func + 7705 .fpu fpv5-d16 + 7707 HAL_MultiProcessor_EnableMuteMode: + 7708 .LVL567: + 7709 .LFB175: +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 7710 .loc 1 2655 1 is_stmt 1 view -0 + 7711 .cfi_startproc + 7712 @ args = 0, pretend = 0, frame = 0 + 7713 @ frame_needed = 0, uses_anonymous_args = 0 +2655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 7714 .loc 1 2655 1 is_stmt 0 view .LVU2274 + 7715 0000 08B5 push {r3, lr} + 7716 .LCFI60: + 7717 .cfi_def_cfa_offset 8 + 7718 .cfi_offset 3, -8 + 7719 .cfi_offset 14, -4 +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7720 .loc 1 2656 3 is_stmt 1 view .LVU2275 +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7721 .loc 1 2656 3 view .LVU2276 + 7722 0002 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 7723 0006 012B cmp r3, #1 + ARM GAS /tmp/ccizsdzp.s page 244 + + + 7724 0008 10D0 beq .L603 +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7725 .loc 1 2656 3 discriminator 2 view .LVU2277 + 7726 000a 0123 movs r3, #1 + 7727 000c 80F87C30 strb r3, [r0, #124] +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7728 .loc 1 2656 3 discriminator 2 view .LVU2278 +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7729 .loc 1 2658 3 discriminator 2 view .LVU2279 +2658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7730 .loc 1 2658 17 is_stmt 0 discriminator 2 view .LVU2280 + 7731 0010 2423 movs r3, #36 + 7732 0012 C0F88030 str r3, [r0, #128] +2661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7733 .loc 1 2661 3 is_stmt 1 discriminator 2 view .LVU2281 + 7734 0016 0268 ldr r2, [r0] + 7735 0018 1368 ldr r3, [r2] + 7736 001a 43F40053 orr r3, r3, #8192 + 7737 001e 1360 str r3, [r2] +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7738 .loc 1 2663 3 discriminator 2 view .LVU2282 +2663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7739 .loc 1 2663 17 is_stmt 0 discriminator 2 view .LVU2283 + 7740 0020 2023 movs r3, #32 + 7741 0022 C0F88030 str r3, [r0, #128] +2665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7742 .loc 1 2665 3 is_stmt 1 discriminator 2 view .LVU2284 +2665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7743 .loc 1 2665 11 is_stmt 0 discriminator 2 view .LVU2285 + 7744 0026 FFF7FEFF bl UART_CheckIdleState + 7745 .LVL568: + 7746 .L602: +2666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7747 .loc 1 2666 1 view .LVU2286 + 7748 002a 08BD pop {r3, pc} + 7749 .LVL569: + 7750 .L603: +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7751 .loc 1 2656 3 view .LVU2287 + 7752 002c 0220 movs r0, #2 + 7753 .LVL570: +2656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7754 .loc 1 2656 3 view .LVU2288 + 7755 002e FCE7 b .L602 + 7756 .cfi_endproc + 7757 .LFE175: + 7759 .section .text.HAL_MultiProcessor_DisableMuteMode,"ax",%progbits + 7760 .align 1 + 7761 .global HAL_MultiProcessor_DisableMuteMode + 7762 .syntax unified + 7763 .thumb + 7764 .thumb_func + 7765 .fpu fpv5-d16 + 7767 HAL_MultiProcessor_DisableMuteMode: + 7768 .LVL571: + 7769 .LFB176: +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + ARM GAS /tmp/ccizsdzp.s page 245 + + + 7770 .loc 1 2675 1 is_stmt 1 view -0 + 7771 .cfi_startproc + 7772 @ args = 0, pretend = 0, frame = 0 + 7773 @ frame_needed = 0, uses_anonymous_args = 0 +2675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** __HAL_LOCK(huart); + 7774 .loc 1 2675 1 is_stmt 0 view .LVU2290 + 7775 0000 08B5 push {r3, lr} + 7776 .LCFI61: + 7777 .cfi_def_cfa_offset 8 + 7778 .cfi_offset 3, -8 + 7779 .cfi_offset 14, -4 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7780 .loc 1 2676 3 is_stmt 1 view .LVU2291 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7781 .loc 1 2676 3 view .LVU2292 + 7782 0002 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 7783 0006 012B cmp r3, #1 + 7784 0008 10D0 beq .L607 +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7785 .loc 1 2676 3 discriminator 2 view .LVU2293 + 7786 000a 0123 movs r3, #1 + 7787 000c 80F87C30 strb r3, [r0, #124] +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7788 .loc 1 2676 3 discriminator 2 view .LVU2294 +2678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7789 .loc 1 2678 3 discriminator 2 view .LVU2295 +2678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7790 .loc 1 2678 17 is_stmt 0 discriminator 2 view .LVU2296 + 7791 0010 2423 movs r3, #36 + 7792 0012 C0F88030 str r3, [r0, #128] +2681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7793 .loc 1 2681 3 is_stmt 1 discriminator 2 view .LVU2297 + 7794 0016 0268 ldr r2, [r0] + 7795 0018 1368 ldr r3, [r2] + 7796 001a 23F40053 bic r3, r3, #8192 + 7797 001e 1360 str r3, [r2] +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7798 .loc 1 2683 3 discriminator 2 view .LVU2298 +2683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7799 .loc 1 2683 17 is_stmt 0 discriminator 2 view .LVU2299 + 7800 0020 2023 movs r3, #32 + 7801 0022 C0F88030 str r3, [r0, #128] +2685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7802 .loc 1 2685 3 is_stmt 1 discriminator 2 view .LVU2300 +2685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** } + 7803 .loc 1 2685 11 is_stmt 0 discriminator 2 view .LVU2301 + 7804 0026 FFF7FEFF bl UART_CheckIdleState + 7805 .LVL572: + 7806 .L606: +2686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7807 .loc 1 2686 1 view .LVU2302 + 7808 002a 08BD pop {r3, pc} + 7809 .LVL573: + 7810 .L607: +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7811 .loc 1 2676 3 view .LVU2303 + 7812 002c 0220 movs r0, #2 + ARM GAS /tmp/ccizsdzp.s page 246 + + + 7813 .LVL574: +2676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c **** + 7814 .loc 1 2676 3 view .LVU2304 + 7815 002e FCE7 b .L606 + 7816 .cfi_endproc + 7817 .LFE176: + 7819 .global UARTPrescTable + 7820 .section .rodata.UARTPrescTable,"a" + 7821 .align 2 + 7822 .set .LANCHOR0,. + 0 + 7825 UARTPrescTable: + 7826 0000 0100 .short 1 + 7827 0002 0200 .short 2 + 7828 0004 0400 .short 4 + 7829 0006 0600 .short 6 + 7830 0008 0800 .short 8 + 7831 000a 0A00 .short 10 + 7832 000c 0C00 .short 12 + 7833 000e 1000 .short 16 + 7834 0010 2000 .short 32 + 7835 0012 4000 .short 64 + 7836 0014 8000 .short 128 + 7837 0016 0001 .short 256 + 7838 .text + 7839 .Letext0: + 7840 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 7841 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 7842 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 7843 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 7844 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 7845 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h" + 7846 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 7847 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" + 7848 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 7849 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" + 7850 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h" + ARM GAS /tmp/ccizsdzp.s page 247 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_uart.c + /tmp/ccizsdzp.s:17 .text.UART_EndTxTransfer:0000000000000000 $t + /tmp/ccizsdzp.s:24 .text.UART_EndTxTransfer:0000000000000000 UART_EndTxTransfer + /tmp/ccizsdzp.s:53 .text.UART_EndRxTransfer:0000000000000000 $t + /tmp/ccizsdzp.s:59 .text.UART_EndRxTransfer:0000000000000000 UART_EndRxTransfer + /tmp/ccizsdzp.s:91 .text.UART_EndRxTransfer:0000000000000020 $d + /tmp/ccizsdzp.s:96 .text.UART_TxISR_8BIT:0000000000000000 $t + /tmp/ccizsdzp.s:102 .text.UART_TxISR_8BIT:0000000000000000 UART_TxISR_8BIT + /tmp/ccizsdzp.s:167 .text.UART_TxISR_16BIT:0000000000000000 $t + /tmp/ccizsdzp.s:173 .text.UART_TxISR_16BIT:0000000000000000 UART_TxISR_16BIT + /tmp/ccizsdzp.s:244 .text.UART_TxISR_8BIT_FIFOEN:0000000000000000 $t + /tmp/ccizsdzp.s:250 .text.UART_TxISR_8BIT_FIFOEN:0000000000000000 UART_TxISR_8BIT_FIFOEN + /tmp/ccizsdzp.s:345 .text.UART_TxISR_16BIT_FIFOEN:0000000000000000 $t + /tmp/ccizsdzp.s:351 .text.UART_TxISR_16BIT_FIFOEN:0000000000000000 UART_TxISR_16BIT_FIFOEN + /tmp/ccizsdzp.s:452 .text.HAL_UART_MspInit:0000000000000000 $t + /tmp/ccizsdzp.s:459 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit + /tmp/ccizsdzp.s:474 .text.HAL_UART_MspDeInit:0000000000000000 $t + /tmp/ccizsdzp.s:481 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit + /tmp/ccizsdzp.s:496 .text.HAL_UART_DeInit:0000000000000000 $t + /tmp/ccizsdzp.s:503 .text.HAL_UART_DeInit:0000000000000000 HAL_UART_DeInit + /tmp/ccizsdzp.s:586 .text.HAL_UART_Transmit_IT:0000000000000000 $t + /tmp/ccizsdzp.s:593 .text.HAL_UART_Transmit_IT:0000000000000000 HAL_UART_Transmit_IT + /tmp/ccizsdzp.s:755 .text.HAL_UART_Transmit_IT:00000000000000a0 $d + /tmp/ccizsdzp.s:763 .text.HAL_UART_Receive_IT:0000000000000000 $t + /tmp/ccizsdzp.s:770 .text.HAL_UART_Receive_IT:0000000000000000 HAL_UART_Receive_IT + /tmp/ccizsdzp.s:1005 .text.HAL_UART_Receive_IT:0000000000000114 $d + /tmp/ccizsdzp.s:2333 .text.UART_RxISR_8BIT:0000000000000000 UART_RxISR_8BIT + /tmp/ccizsdzp.s:2548 .text.UART_RxISR_8BIT_FIFOEN:0000000000000000 UART_RxISR_8BIT_FIFOEN + /tmp/ccizsdzp.s:2715 .text.UART_RxISR_16BIT_FIFOEN:0000000000000000 UART_RxISR_16BIT_FIFOEN + /tmp/ccizsdzp.s:2440 .text.UART_RxISR_16BIT:0000000000000000 UART_RxISR_16BIT + /tmp/ccizsdzp.s:1013 .text.HAL_UART_Transmit_DMA:0000000000000000 $t + /tmp/ccizsdzp.s:1020 .text.HAL_UART_Transmit_DMA:0000000000000000 HAL_UART_Transmit_DMA + /tmp/ccizsdzp.s:1186 .text.HAL_UART_Transmit_DMA:000000000000009c $d + /tmp/ccizsdzp.s:2152 .text.UART_DMATransmitCplt:0000000000000000 UART_DMATransmitCplt + /tmp/ccizsdzp.s:2278 .text.UART_DMATxHalfCplt:0000000000000000 UART_DMATxHalfCplt + /tmp/ccizsdzp.s:3024 .text.UART_DMAError:0000000000000000 UART_DMAError + /tmp/ccizsdzp.s:1193 .text.HAL_UART_Receive_DMA:0000000000000000 $t + /tmp/ccizsdzp.s:1200 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.text.HAL_UART_AbortReceiveCpltCallback:0000000000000000 $t + /tmp/ccizsdzp.s:4196 .text.HAL_UART_AbortReceiveCpltCallback:0000000000000000 HAL_UART_AbortReceiveCpltCallback + /tmp/ccizsdzp.s:4211 .text.HAL_UART_AbortReceive_IT:0000000000000000 $t + /tmp/ccizsdzp.s:4218 .text.HAL_UART_AbortReceive_IT:0000000000000000 HAL_UART_AbortReceive_IT + /tmp/ccizsdzp.s:4337 .text.HAL_UART_AbortReceive_IT:0000000000000080 $d + /tmp/ccizsdzp.s:4349 .text.UART_DMARxOnlyAbortCallback:0000000000000000 UART_DMARxOnlyAbortCallback + /tmp/ccizsdzp.s:4343 .text.UART_DMARxOnlyAbortCallback:0000000000000000 $t + /tmp/ccizsdzp.s:4392 .text.HAL_UART_ReceiverTimeout_Config:0000000000000000 $t + /tmp/ccizsdzp.s:4399 .text.HAL_UART_ReceiverTimeout_Config:0000000000000000 HAL_UART_ReceiverTimeout_Config + /tmp/ccizsdzp.s:4428 .text.HAL_UART_ReceiverTimeout_Config:0000000000000014 $d + /tmp/ccizsdzp.s:4433 .text.HAL_UART_EnableReceiverTimeout:0000000000000000 $t + /tmp/ccizsdzp.s:4440 .text.HAL_UART_EnableReceiverTimeout:0000000000000000 HAL_UART_EnableReceiverTimeout + /tmp/ccizsdzp.s:4517 .text.HAL_UART_EnableReceiverTimeout:0000000000000048 $d + /tmp/ccizsdzp.s:4522 .text.HAL_UART_DisableReceiverTimeout:0000000000000000 $t + ARM GAS /tmp/ccizsdzp.s page 249 + + + /tmp/ccizsdzp.s:4529 .text.HAL_UART_DisableReceiverTimeout:0000000000000000 HAL_UART_DisableReceiverTimeout + /tmp/ccizsdzp.s:4606 .text.HAL_UART_DisableReceiverTimeout:0000000000000048 $d + /tmp/ccizsdzp.s:4611 .text.HAL_MultiProcessor_EnterMuteMode:0000000000000000 $t + /tmp/ccizsdzp.s:4618 .text.HAL_MultiProcessor_EnterMuteMode:0000000000000000 HAL_MultiProcessor_EnterMuteMode + /tmp/ccizsdzp.s:4637 .text.HAL_HalfDuplex_EnableTransmitter:0000000000000000 $t + /tmp/ccizsdzp.s:4644 .text.HAL_HalfDuplex_EnableTransmitter:0000000000000000 HAL_HalfDuplex_EnableTransmitter + /tmp/ccizsdzp.s:4701 .text.HAL_HalfDuplex_EnableReceiver:0000000000000000 $t + /tmp/ccizsdzp.s:4708 .text.HAL_HalfDuplex_EnableReceiver:0000000000000000 HAL_HalfDuplex_EnableReceiver + /tmp/ccizsdzp.s:4765 .text.HAL_LIN_SendBreak:0000000000000000 $t + /tmp/ccizsdzp.s:4772 .text.HAL_LIN_SendBreak:0000000000000000 HAL_LIN_SendBreak + /tmp/ccizsdzp.s:4825 .text.HAL_UART_GetState:0000000000000000 $t + /tmp/ccizsdzp.s:4832 .text.HAL_UART_GetState:0000000000000000 HAL_UART_GetState + /tmp/ccizsdzp.s:4860 .text.HAL_UART_GetError:0000000000000000 $t + /tmp/ccizsdzp.s:4867 .text.HAL_UART_GetError:0000000000000000 HAL_UART_GetError + /tmp/ccizsdzp.s:4886 .text.UART_SetConfig:0000000000000000 $t + /tmp/ccizsdzp.s:4893 .text.UART_SetConfig:0000000000000000 UART_SetConfig + /tmp/ccizsdzp.s:5056 .text.UART_SetConfig:00000000000000b4 $d + /tmp/ccizsdzp.s:5097 .text.UART_SetConfig:0000000000000106 $t + /tmp/ccizsdzp.s:5128 .text.UART_SetConfig:000000000000012e $d + /tmp/ccizsdzp.s:5162 .text.UART_SetConfig:0000000000000170 $t + /tmp/ccizsdzp.s:5196 .text.UART_SetConfig:0000000000000190 $d + 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/tmp/ccizsdzp.s:6789 .text.HAL_UART_Receive:0000000000000000 HAL_UART_Receive + /tmp/ccizsdzp.s:7059 .text.UART_CheckIdleState:0000000000000000 $t + /tmp/ccizsdzp.s:7066 .text.UART_CheckIdleState:0000000000000000 UART_CheckIdleState + /tmp/ccizsdzp.s:7179 .text.HAL_UART_Init:0000000000000000 $t + /tmp/ccizsdzp.s:7186 .text.HAL_UART_Init:0000000000000000 HAL_UART_Init + /tmp/ccizsdzp.s:7289 .text.HAL_HalfDuplex_Init:0000000000000000 $t + /tmp/ccizsdzp.s:7296 .text.HAL_HalfDuplex_Init:0000000000000000 HAL_HalfDuplex_Init + ARM GAS /tmp/ccizsdzp.s page 250 + + + /tmp/ccizsdzp.s:7404 .text.HAL_LIN_Init:0000000000000000 $t + /tmp/ccizsdzp.s:7411 .text.HAL_LIN_Init:0000000000000000 HAL_LIN_Init + /tmp/ccizsdzp.s:7563 .text.HAL_MultiProcessor_Init:0000000000000000 $t + /tmp/ccizsdzp.s:7570 .text.HAL_MultiProcessor_Init:0000000000000000 HAL_MultiProcessor_Init + /tmp/ccizsdzp.s:7700 .text.HAL_MultiProcessor_EnableMuteMode:0000000000000000 $t + /tmp/ccizsdzp.s:7707 .text.HAL_MultiProcessor_EnableMuteMode:0000000000000000 HAL_MultiProcessor_EnableMuteMode + /tmp/ccizsdzp.s:7760 .text.HAL_MultiProcessor_DisableMuteMode:0000000000000000 $t + /tmp/ccizsdzp.s:7767 .text.HAL_MultiProcessor_DisableMuteMode:0000000000000000 HAL_MultiProcessor_DisableMuteMode + /tmp/ccizsdzp.s:7825 .rodata.UARTPrescTable:0000000000000000 UARTPrescTable + /tmp/ccizsdzp.s:7821 .rodata.UARTPrescTable:0000000000000000 $d + /tmp/ccizsdzp.s:5456 .text.UART_SetConfig:00000000000002a9 $d + /tmp/ccizsdzp.s:5456 .text.UART_SetConfig:00000000000002aa $t + /tmp/ccizsdzp.s:5909 .text.UART_SetConfig:00000000000004ab $d + /tmp/ccizsdzp.s:5909 .text.UART_SetConfig:00000000000004ac $t + +UNDEFINED SYMBOLS +HAL_DMA_Start_IT +HAL_DMA_Abort +HAL_DMA_GetError +HAL_DMA_Abort_IT +HAL_UARTEx_WakeupCallback +HAL_UARTEx_TxFifoEmptyCallback +HAL_UARTEx_RxFifoFullCallback +__aeabi_uldivmod +HAL_RCCEx_GetD3PCLK1Freq +HAL_RCCEx_GetPLL2ClockFreq +HAL_RCCEx_GetPLL3ClockFreq +HAL_RCC_GetPCLK1Freq +HAL_RCC_GetPCLK2Freq +HAL_GetTick diff --git a/build/stm32h7xx_hal_uart.o b/build/stm32h7xx_hal_uart.o new file mode 100644 index 0000000..4cbb53c Binary files /dev/null and b/build/stm32h7xx_hal_uart.o differ diff --git a/build/stm32h7xx_hal_uart_ex.d b/build/stm32h7xx_hal_uart_ex.d new file mode 100644 index 0000000..f658dec --- /dev/null +++ b/build/stm32h7xx_hal_uart_ex.d @@ -0,0 +1,68 @@ +build/stm32h7xx_hal_uart_ex.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_hal_uart_ex.lst b/build/stm32h7xx_hal_uart_ex.lst new file mode 100644 index 0000000..7a2e872 --- /dev/null +++ b/build/stm32h7xx_hal_uart_ex.lst @@ -0,0 +1,2161 @@ +ARM GAS /tmp/ccz0ib4C.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_hal_uart_ex.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.UARTEx_Wakeup_AddressConfig,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 UARTEx_Wakeup_AddressConfig: + 25 .LVL0: + 26 .LFB153: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @file stm32h7xx_hal_uart_ex.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Extended UART HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * This file provides firmware functions to manage the following extended + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + Peripheral Control functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @verbatim + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ============================================================================== + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ##### UART peripheral extended features ##### + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ============================================================================== + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (#) Declare a UART_HandleTypeDef handle structure. + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (#) For the UART RS485 Driver Enable mode, initialize the UART registers + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** by calling the HAL_RS485Ex_Init() API. + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** starting RX/TX transfers. Also RX/TX FIFO thresholds must be + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** configured prior starting RX/TX transfers. + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @endverbatim + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ****************************************************************************** + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @attention + 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + ARM GAS /tmp/ccz0ib4C.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** *

© Copyright (c) 2017 STMicroelectronics. + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * All rights reserved.

+ 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * the "License"; You may not use this file except in compliance with the + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * License. You may obtain a copy of the License at: + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * opensource.org/licenses/BSD-3-Clause + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ****************************************************************************** + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #include "stm32h7xx_hal.h" + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEx UARTEx + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief UART Extended HAL module driver + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #ifdef HAL_UART_MODULE_ENABLED + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Private define ------------------------------------------------------------*/ + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEX_Private_Constants UARTEx Private Constants + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* UART RX FIFO depth */ + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #define RX_FIFO_DEPTH 16U + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* UART TX FIFO depth */ + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #define TX_FIFO_DEPTH 16U + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @} + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Private macros ------------------------------------------------------------*/ + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Private variables ---------------------------------------------------------*/ + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Private_Functions UARTEx Private Functions + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @} + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Exported functions --------------------------------------------------------*/ + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + ARM GAS /tmp/ccz0ib4C.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Extended Initialization and Configuration Functions + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @verbatim + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** =============================================================================== + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ##### Initialization and Configuration functions ##### + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** =============================================================================== + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** [..] + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** in asynchronous mode. + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) For the asynchronous mode the parameters below can be configured: + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Baud Rate + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Word Length + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Stop Bit + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** in the data register is transmitted but is changed by the parity bit. + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Hardware flow control + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Receiver/transmitter modes + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) Over Sampling Method + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) One-Bit Sampling Method + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) For the asynchronous mode, the following advanced features can be configured as well: + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) TX and/or RX pin level inversion + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) data logical level inversion + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) RX and TX pins swap + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) RX overrun detection disabling + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) DMA disabling on RX error + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) MSB first on communication line + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (++) auto Baud rate detection + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** [..] + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** procedures (details for the procedures are available in reference manual). + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @endverbatim + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit, + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** 8-bit or 9-bit), the possible UART formats are listed in the + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** following table. + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** Table 1. UART frame format. + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | M1 bit | M0 bit | PCE bit | UART frame | + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | | + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | | + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | | + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + ARM GAS /tmp/ccz0ib4C.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Initialize the RS485 Driver enable feature according to the specified + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param Polarity Select the driver enable polarity. + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param AssertionTime Driver Enable assertion time: + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * 5-bit value defining the time between the activation of the DE (Driver Enable) + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * signal and the beginning of the start bit. It is expressed in sample time + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * units (1/8 or 1/16 bit time, depending on the oversampling rate) + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param DeassertionTime Driver Enable deassertion time: + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * 5-bit value defining the time between the end of the last stop bit, in a + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * transmitted message, and the de-activation of the DE (Driver Enable) signal. + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * oversampling rate). + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t Assertion + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t DeassertionTime) + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t temp; + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (huart == NULL) + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_ERROR; + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the Driver Enable UART instance */ + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the Driver Enable polarity */ + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_DE_POLARITY(Polarity)); + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the Driver Enable assertion time */ + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the Driver Enable deassertion time */ + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (huart->gState == HAL_UART_STATE_RESET) + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Allocate lock resource and initialize it */ + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->Lock = HAL_UNLOCKED; + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UART_InitCallbacksToDefault(huart); + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (huart->MspInitCallback == NULL) + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->MspInitCallback = HAL_UART_MspInit; + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Init the low level hardware */ + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->MspInitCallback(huart); + ARM GAS /tmp/ccz0ib4C.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #else + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_UART_MspInit(huart); + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the UART Communication parameters */ + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_ERROR; + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UART_AdvFeatureConfig(huart); + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the Driver Enable polarity */ + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the Driver Enable assertion and deassertion times */ + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @} + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Extended functions + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @verbatim + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** =============================================================================== + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ##### IO operation functions ##### + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** =============================================================================== + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** This subsection provides a set of Wakeup and FIFO mode related callback functions. + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (#) Wakeup from Stop mode Callback: + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_WakeupCallback() + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (#) TX/RX Fifos Callbacks: + ARM GAS /tmp/ccz0ib4C.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_RxFifoFullCallback() + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_TxFifoEmptyCallback() + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @endverbatim + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief UART wakeup from Stop mode callback. + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval None + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UNUSED(huart); + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** the HAL_UARTEx_WakeupCallback can be implemented in the user file. + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief UART RX Fifo full callback. + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval None + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UNUSED(huart); + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief UART TX Fifo empty callback. + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval None + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UNUSED(huart); + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @} + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + ARM GAS /tmp/ccz0ib4C.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Extended Peripheral Control functions + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @verbatim + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** =============================================================================== + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** ##### Peripheral Control functions ##### + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** =============================================================================== + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** [..] This section provides the following functions: + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** detection length to more than 4 bits for multiprocessor address mark wake up. + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** trigger: address match, Start Bit detection or RXNE bit status. + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** @endverbatim + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief By default in multiprocessor mode, when the wake up method is set + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * to address mark, the UART handles only 4-bit long addresses detection; + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * this API allows to enable longer addresses detection (6-, 7- or 8-bit + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * long). + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param AddressLength This parameter can be one of the following values: + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t Addres + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (huart == NULL) + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_ERROR; + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the address length parameter */ + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the address length */ + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + ARM GAS /tmp/ccz0ib4C.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState to Ready */ + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Set Wakeup from Stop mode interrupt flag selection. + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @note It is the application responsibility to enable the interrupt used as + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * usart_wkup interrupt source before entering low-power mode. + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_ADDRESS + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_STARTBIT + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeD + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tickstart; + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* check the wake-up from stop mode UART instance */ + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the wake-up selection scheme */ + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Init tickstart for timeout managment*/ + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tickstart = HAL_GetTick(); + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Wait until REACK flag is set */ + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** status = HAL_TIMEOUT; + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** else + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Initialize the UART State */ + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + ARM GAS /tmp/ccz0ib4C.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return status; + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Enable UART Stop Mode. + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set UESM bit */ + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_OK; + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Disable UART Stop Mode. + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Clear UESM bit */ + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_OK; + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Enable the FIFO mode. + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check parameters */ + ARM GAS /tmp/ccz0ib4C.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Save actual UART configuration */ + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable UART */ + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Enable FIFO mode */ + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** SET_BIT(tmpcr1, USART_CR1_FIFOEN); + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_ENABLE; + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Restore UART configuration */ + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */ + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart); + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_OK; + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Disable the FIFO mode. + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check parameters */ + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Save actual UART configuration */ + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable UART */ + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Enable FIFO mode */ + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_DISABLE; + ARM GAS /tmp/ccz0ib4C.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Restore UART configuration */ + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_OK; + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Set the TXFIFO threshold. + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param Threshold TX FIFO threshold value + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check parameters */ + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Save actual UART configuration */ + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable UART */ + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Update TX threshold configuration */ + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */ + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart); + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Restore UART configuration */ + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + ARM GAS /tmp/ccz0ib4C.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_OK; + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Set the RXFIFO threshold. + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param Threshold RX FIFO threshold value + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval HAL status + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the parameters */ + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Save actual UART configuration */ + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tmpcr1 = READ_REG(huart->Instance->CR1); + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Disable UART */ + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Update RX threshold configuration */ + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Determine the number of data to process during RX/TX ISR execution */ + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** UARTEx_SetNbDataToProcess(huart); + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Restore UART configuration */ + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** WRITE_REG(huart->Instance->CR1, tmpcr1); + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Unlocked */ + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** return HAL_OK; + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @} + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + ARM GAS /tmp/ccz0ib4C.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @} + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** @addtogroup UARTEx_Private_Functions + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @{ + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detectio + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param WakeUpSelection UART wake up from stop mode parameters. + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval None + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 28 .loc 1 674 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 674 1 is_stmt 0 view .LVU1 + 34 0000 82B0 sub sp, sp, #8 + 35 .LCFI0: + 36 .cfi_def_cfa_offset 8 + 37 0002 02AB add r3, sp, #8 + 38 0004 03E90600 stmdb r3, {r1, r2} + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + 39 .loc 1 675 3 is_stmt 1 view .LVU2 + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the USART address length */ + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + 40 .loc 1 678 3 view .LVU3 + 41 0008 0268 ldr r2, [r0] + 42 000a 5368 ldr r3, [r2, #4] + 43 000c 23F01003 bic r3, r3, #16 + 44 0010 BDF80410 ldrh r1, [sp, #4] + 45 0014 0B43 orrs r3, r3, r1 + 46 0016 5360 str r3, [r2, #4] + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Set the USART address node */ + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_AD + 47 .loc 1 681 3 view .LVU4 + 48 0018 0268 ldr r2, [r0] + 49 001a 5368 ldr r3, [r2, #4] + 50 001c 23F07F43 bic r3, r3, #-16777216 + 51 0020 9DF80610 ldrb r1, [sp, #6] @ zero_extendqisi2 + 52 0024 43EA0163 orr r3, r3, r1, lsl #24 + 53 0028 5360 str r3, [r2, #4] + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 54 .loc 1 682 1 is_stmt 0 view .LVU5 + 55 002a 02B0 add sp, sp, #8 + 56 .LCFI1: + 57 .cfi_def_cfa_offset 0 + 58 @ sp needed + 59 002c 7047 bx lr + 60 .cfi_endproc + ARM GAS /tmp/ccz0ib4C.s page 14 + + + 61 .LFE153: + 63 .section .rodata.UARTEx_SetNbDataToProcess.str1.4,"aMS",%progbits,1 + 64 .align 2 + 65 .LC1: + 66 0000 08040204 .ascii "\010\004\002\004\010\001\001\001\000" + 66 08010101 + 66 00 + 67 .section .text.UARTEx_SetNbDataToProcess,"ax",%progbits + 68 .align 1 + 69 .syntax unified + 70 .thumb + 71 .thumb_func + 72 .fpu fpv5-d16 + 74 UARTEx_SetNbDataToProcess: + 75 .LVL1: + 76 .LFB154: + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /** + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @brief Calculate the number of data to process in RX/TX ISR. + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @note The RX FIFO depth and the TX FIFO depth is extracted from + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * the UART configuration registers. + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @param huart UART handle. + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** * @retval None + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** */ + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 77 .loc 1 692 1 is_stmt 1 view -0 + 78 .cfi_startproc + 79 @ args = 0, pretend = 0, frame = 16 + 80 @ frame_needed = 0, uses_anonymous_args = 0 + 81 @ link register save eliminated. + 82 .loc 1 692 1 is_stmt 0 view .LVU7 + 83 0000 84B0 sub sp, sp, #16 + 84 .LCFI2: + 85 .cfi_def_cfa_offset 16 + 86 0002 0346 mov r3, r0 + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint8_t rx_fifo_depth; + 87 .loc 1 693 3 is_stmt 1 view .LVU8 + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint8_t tx_fifo_depth; + 88 .loc 1 694 3 view .LVU9 + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint8_t rx_fifo_threshold; + 89 .loc 1 695 3 view .LVU10 + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint8_t tx_fifo_threshold; + 90 .loc 1 696 3 view .LVU11 + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + 91 .loc 1 697 3 view .LVU12 + 92 .loc 1 697 11 is_stmt 0 view .LVU13 + 93 0004 184A ldr r2, .L7 + 94 0006 92E80300 ldm r2, {r0, r1} + 95 .LVL2: + 96 .loc 1 697 11 view .LVU14 + 97 000a 04AA add r2, sp, #16 + 98 000c 02E90300 stmdb r2, {r0, r1} + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + 99 .loc 1 698 3 is_stmt 1 view .LVU15 + 100 .loc 1 698 11 is_stmt 0 view .LVU16 + 101 0010 1649 ldr r1, .L7+4 + ARM GAS /tmp/ccz0ib4C.s page 15 + + + 102 0012 6A46 mov r2, sp + 103 0014 03C9 ldm r1, {r0, r1} + 104 0016 82E80300 stm r2, {r0, r1} + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** if (huart->FifoMode == UART_FIFOMODE_DISABLE) + 105 .loc 1 700 3 is_stmt 1 view .LVU17 + 106 .loc 1 700 12 is_stmt 0 view .LVU18 + 107 001a 5A6E ldr r2, [r3, #100] + 108 .loc 1 700 6 view .LVU19 + 109 001c 32B9 cbnz r2, .L4 + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbTxDataToProcess = 1U; + 110 .loc 1 702 5 is_stmt 1 view .LVU20 + 111 .loc 1 702 30 is_stmt 0 view .LVU21 + 112 001e 0122 movs r2, #1 + 113 0020 A3F86A20 strh r2, [r3, #106] @ movhi + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = 1U; + 114 .loc 1 703 5 is_stmt 1 view .LVU22 + 115 .loc 1 703 30 is_stmt 0 view .LVU23 + 116 0024 A3F86820 strh r2, [r3, #104] @ movhi + 117 .L3: + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** else + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** rx_fifo_depth = RX_FIFO_DEPTH; + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tx_fifo_depth = TX_FIFO_DEPTH; + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RX + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 118 .loc 1 714 1 view .LVU24 + 119 0028 04B0 add sp, sp, #16 + 120 .LCFI3: + 121 .cfi_remember_state + 122 .cfi_def_cfa_offset 0 + 123 @ sp needed + 124 002a 7047 bx lr + 125 .L4: + 126 .LCFI4: + 127 .cfi_restore_state + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tx_fifo_depth = TX_FIFO_DEPTH; + 128 .loc 1 707 5 is_stmt 1 view .LVU25 + 129 .LVL3: + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RX + 130 .loc 1 708 5 view .LVU26 + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX + 131 .loc 1 709 5 view .LVU27 + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX + 132 .loc 1 709 35 is_stmt 0 view .LVU28 + 133 002c 1968 ldr r1, [r3] + 134 002e 8A68 ldr r2, [r1, #8] + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TX + 135 .loc 1 709 23 view .LVU29 + 136 0030 C2F34262 ubfx r2, r2, #25, #3 + 137 .LVL4: + ARM GAS /tmp/ccz0ib4C.s page 16 + + + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t + 138 .loc 1 710 5 is_stmt 1 view .LVU30 + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t + 139 .loc 1 710 35 is_stmt 0 view .LVU31 + 140 0034 8868 ldr r0, [r1, #8] + 141 .LVL5: + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 142 .loc 1 711 5 is_stmt 1 view .LVU32 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 143 .loc 1 711 68 is_stmt 0 view .LVU33 + 144 0036 04A9 add r1, sp, #16 + 145 0038 01EB5070 add r0, r1, r0, lsr #29 + 146 .LVL6: + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 147 .loc 1 711 68 view .LVU34 + 148 003c 10F8081C ldrb r1, [r0, #-8] @ zero_extendqisi2 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 149 .loc 1 711 57 view .LVU35 + 150 0040 0901 lsls r1, r1, #4 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 151 .loc 1 711 112 view .LVU36 + 152 0042 10F8100C ldrb r0, [r0, #-16] @ zero_extendqisi2 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 153 .loc 1 711 89 view .LVU37 + 154 0046 91FBF0F1 sdiv r1, r1, r0 + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t + 155 .loc 1 711 30 view .LVU38 + 156 004a A3F86A10 strh r1, [r3, #106] @ movhi + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 157 .loc 1 712 5 is_stmt 1 view .LVU39 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 158 .loc 1 712 68 is_stmt 0 view .LVU40 + 159 004e 04A9 add r1, sp, #16 + 160 0050 0A44 add r2, r2, r1 + 161 .LVL7: + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 162 .loc 1 712 68 view .LVU41 + 163 0052 12F8081C ldrb r1, [r2, #-8] @ zero_extendqisi2 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 164 .loc 1 712 57 view .LVU42 + 165 0056 0901 lsls r1, r1, #4 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 166 .loc 1 712 112 view .LVU43 + 167 0058 12F8102C ldrb r2, [r2, #-16] @ zero_extendqisi2 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 168 .loc 1 712 89 view .LVU44 + 169 005c 91FBF2F2 sdiv r2, r1, r2 + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 170 .loc 1 712 30 view .LVU45 + 171 0060 A3F86820 strh r2, [r3, #104] @ movhi + 172 .loc 1 714 1 view .LVU46 + 173 0064 E0E7 b .L3 + 174 .L8: + 175 0066 00BF .align 2 + 176 .L7: + 177 0068 00000000 .word .LANCHOR0 + 178 006c 00000000 .word .LC1 + ARM GAS /tmp/ccz0ib4C.s page 17 + + + 179 .cfi_endproc + 180 .LFE154: + 182 .section .text.HAL_RS485Ex_Init,"ax",%progbits + 183 .align 1 + 184 .global HAL_RS485Ex_Init + 185 .syntax unified + 186 .thumb + 187 .thumb_func + 188 .fpu fpv5-d16 + 190 HAL_RS485Ex_Init: + 191 .LVL8: + 192 .LFB141: + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t temp; + 193 .loc 1 168 1 is_stmt 1 view -0 + 194 .cfi_startproc + 195 @ args = 0, pretend = 0, frame = 0 + 196 @ frame_needed = 0, uses_anonymous_args = 0 + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 197 .loc 1 169 3 view .LVU48 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 198 .loc 1 172 3 view .LVU49 + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 199 .loc 1 172 6 is_stmt 0 view .LVU50 + 200 0000 0028 cmp r0, #0 + 201 0002 3CD0 beq .L13 + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t temp; + 202 .loc 1 168 1 view .LVU51 + 203 0004 F8B5 push {r3, r4, r5, r6, r7, lr} + 204 .LCFI5: + 205 .cfi_def_cfa_offset 24 + 206 .cfi_offset 3, -24 + 207 .cfi_offset 4, -20 + 208 .cfi_offset 5, -16 + 209 .cfi_offset 6, -12 + 210 .cfi_offset 7, -8 + 211 .cfi_offset 14, -4 + 212 0006 0F46 mov r7, r1 + 213 0008 1646 mov r6, r2 + 214 000a 1D46 mov r5, r3 + 215 000c 0446 mov r4, r0 + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 216 .loc 1 177 3 is_stmt 1 view .LVU52 + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 217 .loc 1 180 3 view .LVU53 + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 218 .loc 1 183 3 view .LVU54 + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 219 .loc 1 186 3 view .LVU55 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 220 .loc 1 188 3 view .LVU56 + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 221 .loc 1 188 12 is_stmt 0 view .LVU57 + 222 000e D0F88030 ldr r3, [r0, #128] + 223 .LVL9: + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 224 .loc 1 188 6 view .LVU58 + 225 0012 5BB3 cbz r3, .L18 + ARM GAS /tmp/ccz0ib4C.s page 18 + + + 226 .LVL10: + 227 .L11: + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 228 .loc 1 209 3 is_stmt 1 view .LVU59 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 229 .loc 1 209 17 is_stmt 0 view .LVU60 + 230 0014 2423 movs r3, #36 + 231 0016 C4F88030 str r3, [r4, #128] + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 232 .loc 1 212 3 is_stmt 1 view .LVU61 + 233 001a 2268 ldr r2, [r4] + 234 001c 1368 ldr r3, [r2] + 235 001e 23F00103 bic r3, r3, #1 + 236 0022 1360 str r3, [r2] + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 237 .loc 1 215 3 view .LVU62 + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 238 .loc 1 215 7 is_stmt 0 view .LVU63 + 239 0024 2046 mov r0, r4 + 240 0026 FFF7FEFF bl UART_SetConfig + 241 .LVL11: + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 242 .loc 1 215 6 view .LVU64 + 243 002a 0128 cmp r0, #1 + 244 002c 1DD0 beq .L10 + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 245 .loc 1 220 3 is_stmt 1 view .LVU65 + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 246 .loc 1 220 26 is_stmt 0 view .LVU66 + 247 002e A36A ldr r3, [r4, #40] + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 248 .loc 1 220 6 view .LVU67 + 249 0030 0BBB cbnz r3, .L19 + 250 .L12: + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 251 .loc 1 226 3 is_stmt 1 view .LVU68 + 252 0032 2268 ldr r2, [r4] + 253 0034 9368 ldr r3, [r2, #8] + 254 0036 43F48043 orr r3, r3, #16384 + 255 003a 9360 str r3, [r2, #8] + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 256 .loc 1 229 3 view .LVU69 + 257 003c 2268 ldr r2, [r4] + 258 003e 9368 ldr r3, [r2, #8] + 259 0040 23F40043 bic r3, r3, #32768 + 260 0044 3B43 orrs r3, r3, r7 + 261 0046 9360 str r3, [r2, #8] + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + 262 .loc 1 232 3 view .LVU70 + 263 .LVL12: + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 264 .loc 1 233 3 view .LVU71 + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 265 .loc 1 233 28 is_stmt 0 view .LVU72 + 266 0048 2D04 lsls r5, r5, #16 + 267 .LVL13: + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + ARM GAS /tmp/ccz0ib4C.s page 19 + + + 268 .loc 1 233 8 view .LVU73 + 269 004a 45EA4655 orr r5, r5, r6, lsl #21 + 270 .LVL14: + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 271 .loc 1 234 3 is_stmt 1 view .LVU74 + 272 004e 2268 ldr r2, [r4] + 273 0050 1168 ldr r1, [r2] + 274 0052 0C4B ldr r3, .L20 + 275 0054 0B40 ands r3, r3, r1 + 276 0056 1D43 orrs r5, r5, r3 + 277 .LVL15: + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 278 .loc 1 234 3 is_stmt 0 view .LVU75 + 279 0058 1560 str r5, [r2] + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 280 .loc 1 237 3 is_stmt 1 view .LVU76 + 281 005a 2268 ldr r2, [r4] + 282 005c 1368 ldr r3, [r2] + 283 005e 43F00103 orr r3, r3, #1 + 284 0062 1360 str r3, [r2] + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 285 .loc 1 240 3 view .LVU77 + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 286 .loc 1 240 11 is_stmt 0 view .LVU78 + 287 0064 2046 mov r0, r4 + 288 0066 FFF7FEFF bl UART_CheckIdleState + 289 .LVL16: + 290 .L10: + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 291 .loc 1 241 1 view .LVU79 + 292 006a F8BD pop {r3, r4, r5, r6, r7, pc} + 293 .LVL17: + 294 .L18: + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 295 .loc 1 191 5 is_stmt 1 view .LVU80 + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 296 .loc 1 191 17 is_stmt 0 view .LVU81 + 297 006c 80F87C30 strb r3, [r0, #124] + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 298 .loc 1 205 5 is_stmt 1 view .LVU82 + 299 0070 FFF7FEFF bl HAL_UART_MspInit + 300 .LVL18: + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 301 .loc 1 205 5 is_stmt 0 view .LVU83 + 302 0074 CEE7 b .L11 + 303 .L19: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 304 .loc 1 222 5 is_stmt 1 view .LVU84 + 305 0076 2046 mov r0, r4 + 306 0078 FFF7FEFF bl UART_AdvFeatureConfig + 307 .LVL19: + 308 007c D9E7 b .L12 + 309 .LVL20: + 310 .L13: + 311 .LCFI6: + 312 .cfi_def_cfa_offset 0 + 313 .cfi_restore 3 + ARM GAS /tmp/ccz0ib4C.s page 20 + + + 314 .cfi_restore 4 + 315 .cfi_restore 5 + 316 .cfi_restore 6 + 317 .cfi_restore 7 + 318 .cfi_restore 14 + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 319 .loc 1 174 12 is_stmt 0 view .LVU85 + 320 007e 0120 movs r0, #1 + 321 .LVL21: + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 322 .loc 1 241 1 view .LVU86 + 323 0080 7047 bx lr + 324 .L21: + 325 0082 00BF .align 2 + 326 .L20: + 327 0084 FFFF00FC .word -67043329 + 328 .cfi_endproc + 329 .LFE141: + 331 .section .text.HAL_UARTEx_WakeupCallback,"ax",%progbits + 332 .align 1 + 333 .weak HAL_UARTEx_WakeupCallback + 334 .syntax unified + 335 .thumb + 336 .thumb_func + 337 .fpu fpv5-d16 + 339 HAL_UARTEx_WakeupCallback: + 340 .LVL22: + 341 .LFB142: + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 342 .loc 1 273 1 is_stmt 1 view -0 + 343 .cfi_startproc + 344 @ args = 0, pretend = 0, frame = 0 + 345 @ frame_needed = 0, uses_anonymous_args = 0 + 346 @ link register save eliminated. + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 347 .loc 1 275 3 view .LVU88 + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 348 .loc 1 280 1 is_stmt 0 view .LVU89 + 349 0000 7047 bx lr + 350 .cfi_endproc + 351 .LFE142: + 353 .section .text.HAL_UARTEx_RxFifoFullCallback,"ax",%progbits + 354 .align 1 + 355 .weak HAL_UARTEx_RxFifoFullCallback + 356 .syntax unified + 357 .thumb + 358 .thumb_func + 359 .fpu fpv5-d16 + 361 HAL_UARTEx_RxFifoFullCallback: + 362 .LVL23: + 363 .LFB143: + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 364 .loc 1 288 1 is_stmt 1 view -0 + 365 .cfi_startproc + 366 @ args = 0, pretend = 0, frame = 0 + 367 @ frame_needed = 0, uses_anonymous_args = 0 + 368 @ link register save eliminated. + ARM GAS /tmp/ccz0ib4C.s page 21 + + + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 369 .loc 1 290 3 view .LVU91 + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 370 .loc 1 295 1 is_stmt 0 view .LVU92 + 371 0000 7047 bx lr + 372 .cfi_endproc + 373 .LFE143: + 375 .section .text.HAL_UARTEx_TxFifoEmptyCallback,"ax",%progbits + 376 .align 1 + 377 .weak HAL_UARTEx_TxFifoEmptyCallback + 378 .syntax unified + 379 .thumb + 380 .thumb_func + 381 .fpu fpv5-d16 + 383 HAL_UARTEx_TxFifoEmptyCallback: + 384 .LVL24: + 385 .LFB144: + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Prevent unused argument(s) compilation warning */ + 386 .loc 1 303 1 is_stmt 1 view -0 + 387 .cfi_startproc + 388 @ args = 0, pretend = 0, frame = 0 + 389 @ frame_needed = 0, uses_anonymous_args = 0 + 390 @ link register save eliminated. + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 391 .loc 1 305 3 view .LVU94 + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 392 .loc 1 310 1 is_stmt 0 view .LVU95 + 393 0000 7047 bx lr + 394 .cfi_endproc + 395 .LFE144: + 397 .section .text.HAL_MultiProcessorEx_AddressLength_Set,"ax",%progbits + 398 .align 1 + 399 .global HAL_MultiProcessorEx_AddressLength_Set + 400 .syntax unified + 401 .thumb + 402 .thumb_func + 403 .fpu fpv5-d16 + 405 HAL_MultiProcessorEx_AddressLength_Set: + 406 .LVL25: + 407 .LFB145: + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 408 .loc 1 353 1 is_stmt 1 view -0 + 409 .cfi_startproc + 410 @ args = 0, pretend = 0, frame = 0 + 411 @ frame_needed = 0, uses_anonymous_args = 0 + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 412 .loc 1 355 3 view .LVU97 + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 413 .loc 1 355 6 is_stmt 0 view .LVU98 + 414 0000 C0B1 cbz r0, .L27 + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 415 .loc 1 353 1 view .LVU99 + 416 0002 08B5 push {r3, lr} + 417 .LCFI7: + 418 .cfi_def_cfa_offset 8 + 419 .cfi_offset 3, -8 + 420 .cfi_offset 14, -4 + ARM GAS /tmp/ccz0ib4C.s page 22 + + + 421 0004 0346 mov r3, r0 + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 422 .loc 1 361 3 is_stmt 1 view .LVU100 + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 423 .loc 1 363 3 view .LVU101 + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 424 .loc 1 363 17 is_stmt 0 view .LVU102 + 425 0006 2422 movs r2, #36 + 426 0008 C0F88020 str r2, [r0, #128] + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 427 .loc 1 366 3 is_stmt 1 view .LVU103 + 428 000c 0068 ldr r0, [r0] + 429 .LVL26: + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 430 .loc 1 366 3 is_stmt 0 view .LVU104 + 431 000e 0268 ldr r2, [r0] + 432 0010 22F00102 bic r2, r2, #1 + 433 0014 0260 str r2, [r0] + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 434 .loc 1 369 3 is_stmt 1 view .LVU105 + 435 0016 1868 ldr r0, [r3] + 436 0018 4268 ldr r2, [r0, #4] + 437 001a 22F01002 bic r2, r2, #16 + 438 001e 1143 orrs r1, r1, r2 + 439 .LVL27: + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 440 .loc 1 369 3 is_stmt 0 view .LVU106 + 441 0020 4160 str r1, [r0, #4] + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 442 .loc 1 372 3 is_stmt 1 view .LVU107 + 443 0022 1968 ldr r1, [r3] + 444 0024 0A68 ldr r2, [r1] + 445 0026 42F00102 orr r2, r2, #1 + 446 002a 0A60 str r2, [r1] + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 447 .loc 1 375 3 view .LVU108 + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 448 .loc 1 375 11 is_stmt 0 view .LVU109 + 449 002c 1846 mov r0, r3 + 450 002e FFF7FEFF bl UART_CheckIdleState + 451 .LVL28: + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 452 .loc 1 376 1 view .LVU110 + 453 0032 08BD pop {r3, pc} + 454 .LVL29: + 455 .L27: + 456 .LCFI8: + 457 .cfi_def_cfa_offset 0 + 458 .cfi_restore 3 + 459 .cfi_restore 14 + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 460 .loc 1 357 12 view .LVU111 + 461 0034 0120 movs r0, #1 + 462 .LVL30: + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 463 .loc 1 376 1 view .LVU112 + 464 0036 7047 bx lr + ARM GAS /tmp/ccz0ib4C.s page 23 + + + 465 .cfi_endproc + 466 .LFE145: + 468 .section .text.HAL_UARTEx_StopModeWakeUpSourceConfig,"ax",%progbits + 469 .align 1 + 470 .global HAL_UARTEx_StopModeWakeUpSourceConfig + 471 .syntax unified + 472 .thumb + 473 .thumb_func + 474 .fpu fpv5-d16 + 476 HAL_UARTEx_StopModeWakeUpSourceConfig: + 477 .LVL31: + 478 .LFB146: + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 479 .loc 1 391 1 is_stmt 1 view -0 + 480 .cfi_startproc + 481 @ args = 0, pretend = 0, frame = 8 + 482 @ frame_needed = 0, uses_anonymous_args = 0 + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 483 .loc 1 391 1 is_stmt 0 view .LVU114 + 484 0000 10B5 push {r4, lr} + 485 .LCFI9: + 486 .cfi_def_cfa_offset 8 + 487 .cfi_offset 4, -8 + 488 .cfi_offset 14, -4 + 489 0002 84B0 sub sp, sp, #16 + 490 .LCFI10: + 491 .cfi_def_cfa_offset 24 + 492 0004 04AB add r3, sp, #16 + 493 0006 03E90600 stmdb r3, {r1, r2} + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tickstart; + 494 .loc 1 392 3 is_stmt 1 view .LVU115 + 495 .LVL32: + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 496 .loc 1 393 3 view .LVU116 + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ + 497 .loc 1 396 3 view .LVU117 + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 498 .loc 1 398 3 view .LVU118 + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 499 .loc 1 401 3 view .LVU119 + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 500 .loc 1 401 3 view .LVU120 + 501 000a 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 502 000e 012B cmp r3, #1 + 503 0010 35D0 beq .L36 + 504 0012 0446 mov r4, r0 + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 505 .loc 1 401 3 discriminator 2 view .LVU121 + 506 0014 0123 movs r3, #1 + 507 0016 80F87C30 strb r3, [r0, #124] + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 508 .loc 1 401 3 discriminator 2 view .LVU122 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 509 .loc 1 403 3 discriminator 2 view .LVU123 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 510 .loc 1 403 17 is_stmt 0 discriminator 2 view .LVU124 + 511 001a 2423 movs r3, #36 + ARM GAS /tmp/ccz0ib4C.s page 24 + + + 512 001c C0F88030 str r3, [r0, #128] + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 513 .loc 1 406 3 is_stmt 1 discriminator 2 view .LVU125 + 514 0020 0268 ldr r2, [r0] + 515 0022 1368 ldr r3, [r2] + 516 0024 23F00103 bic r3, r3, #1 + 517 0028 1360 str r3, [r2] + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 518 .loc 1 409 3 discriminator 2 view .LVU126 + 519 002a 0168 ldr r1, [r0] + 520 002c 8B68 ldr r3, [r1, #8] + 521 002e 23F44013 bic r3, r3, #3145728 + 522 0032 029A ldr r2, [sp, #8] + 523 0034 1343 orrs r3, r3, r2 + 524 0036 8B60 str r3, [r1, #8] + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 525 .loc 1 411 3 discriminator 2 view .LVU127 + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 526 .loc 1 411 6 is_stmt 0 discriminator 2 view .LVU128 + 527 0038 AAB1 cbz r2, .L39 + 528 .LVL33: + 529 .L34: + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 530 .loc 1 417 3 is_stmt 1 view .LVU129 + 531 003a 2268 ldr r2, [r4] + 532 003c 1368 ldr r3, [r2] + 533 003e 43F00103 orr r3, r3, #1 + 534 0042 1360 str r3, [r2] + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 535 .loc 1 420 3 view .LVU130 + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 536 .loc 1 420 15 is_stmt 0 view .LVU131 + 537 0044 FFF7FEFF bl HAL_GetTick + 538 .LVL34: + 539 0048 0346 mov r3, r0 + 540 .LVL35: + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 541 .loc 1 423 3 is_stmt 1 view .LVU132 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 542 .loc 1 423 7 is_stmt 0 view .LVU133 + 543 004a 6FF07E42 mvn r2, #-33554432 + 544 004e 0092 str r2, [sp] + 545 0050 0022 movs r2, #0 + 546 0052 4FF48001 mov r1, #4194304 + 547 0056 2046 mov r0, r4 + 548 .LVL36: + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 549 .loc 1 423 7 view .LVU134 + 550 0058 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 551 .LVL37: + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** { + 552 .loc 1 423 6 view .LVU135 + 553 005c 48B9 cbnz r0, .L37 + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 554 .loc 1 430 5 is_stmt 1 view .LVU136 + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 555 .loc 1 430 19 is_stmt 0 view .LVU137 + ARM GAS /tmp/ccz0ib4C.s page 25 + + + 556 005e 2023 movs r3, #32 + 557 0060 C4F88030 str r3, [r4, #128] + 558 0064 06E0 b .L35 + 559 .LVL38: + 560 .L39: + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 561 .loc 1 413 5 is_stmt 1 view .LVU138 + 562 0066 04AB add r3, sp, #16 + 563 0068 13E90600 ldmdb r3, {r1, r2} + 564 006c FFF7FEFF bl UARTEx_Wakeup_AddressConfig + 565 .LVL39: + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 566 .loc 1 413 5 is_stmt 0 view .LVU139 + 567 0070 E3E7 b .L34 + 568 .L37: + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 569 .loc 1 425 12 view .LVU140 + 570 0072 0320 movs r0, #3 + 571 .L35: + 572 .LVL40: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 573 .loc 1 434 3 is_stmt 1 view .LVU141 + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 574 .loc 1 434 3 view .LVU142 + 575 0074 0023 movs r3, #0 + 576 0076 84F87C30 strb r3, [r4, #124] + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 577 .loc 1 434 3 view .LVU143 + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 578 .loc 1 436 3 view .LVU144 + 579 .LVL41: + 580 .L33: + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 581 .loc 1 437 1 is_stmt 0 view .LVU145 + 582 007a 04B0 add sp, sp, #16 + 583 .LCFI11: + 584 .cfi_remember_state + 585 .cfi_def_cfa_offset 8 + 586 @ sp needed + 587 007c 10BD pop {r4, pc} + 588 .LVL42: + 589 .L36: + 590 .LCFI12: + 591 .cfi_restore_state + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 592 .loc 1 401 3 view .LVU146 + 593 007e 0220 movs r0, #2 + 594 .LVL43: + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 595 .loc 1 401 3 view .LVU147 + 596 0080 FBE7 b .L33 + 597 .cfi_endproc + 598 .LFE146: + 600 .section .text.HAL_UARTEx_EnableStopMode,"ax",%progbits + 601 .align 1 + 602 .global HAL_UARTEx_EnableStopMode + 603 .syntax unified + ARM GAS /tmp/ccz0ib4C.s page 26 + + + 604 .thumb + 605 .thumb_func + 606 .fpu fpv5-d16 + 608 HAL_UARTEx_EnableStopMode: + 609 .LVL44: + 610 .LFB147: + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 611 .loc 1 446 1 is_stmt 1 view -0 + 612 .cfi_startproc + 613 @ args = 0, pretend = 0, frame = 0 + 614 @ frame_needed = 0, uses_anonymous_args = 0 + 615 @ link register save eliminated. + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 616 .loc 1 448 3 view .LVU149 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 617 .loc 1 448 3 view .LVU150 + 618 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 619 0004 012B cmp r3, #1 + 620 0006 0CD0 beq .L42 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 621 .loc 1 448 3 discriminator 2 view .LVU151 + 622 0008 0123 movs r3, #1 + 623 000a 80F87C30 strb r3, [r0, #124] + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 624 .loc 1 448 3 discriminator 2 view .LVU152 + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 625 .loc 1 451 3 discriminator 2 view .LVU153 + 626 000e 0268 ldr r2, [r0] + 627 0010 1368 ldr r3, [r2] + 628 0012 43F00203 orr r3, r3, #2 + 629 0016 1360 str r3, [r2] + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 630 .loc 1 454 3 discriminator 2 view .LVU154 + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 631 .loc 1 454 3 discriminator 2 view .LVU155 + 632 0018 0023 movs r3, #0 + 633 001a 80F87C30 strb r3, [r0, #124] + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 634 .loc 1 454 3 discriminator 2 view .LVU156 + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 635 .loc 1 456 3 discriminator 2 view .LVU157 + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 636 .loc 1 456 10 is_stmt 0 discriminator 2 view .LVU158 + 637 001e 1846 mov r0, r3 + 638 .LVL45: + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 639 .loc 1 456 10 discriminator 2 view .LVU159 + 640 0020 7047 bx lr + 641 .LVL46: + 642 .L42: + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 643 .loc 1 448 3 view .LVU160 + 644 0022 0220 movs r0, #2 + 645 .LVL47: + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 646 .loc 1 457 1 view .LVU161 + 647 0024 7047 bx lr + ARM GAS /tmp/ccz0ib4C.s page 27 + + + 648 .cfi_endproc + 649 .LFE147: + 651 .section .text.HAL_UARTEx_DisableStopMode,"ax",%progbits + 652 .align 1 + 653 .global HAL_UARTEx_DisableStopMode + 654 .syntax unified + 655 .thumb + 656 .thumb_func + 657 .fpu fpv5-d16 + 659 HAL_UARTEx_DisableStopMode: + 660 .LVL48: + 661 .LFB148: + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** /* Process Locked */ + 662 .loc 1 465 1 is_stmt 1 view -0 + 663 .cfi_startproc + 664 @ args = 0, pretend = 0, frame = 0 + 665 @ frame_needed = 0, uses_anonymous_args = 0 + 666 @ link register save eliminated. + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 667 .loc 1 467 3 view .LVU163 + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 668 .loc 1 467 3 view .LVU164 + 669 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 670 0004 012B cmp r3, #1 + 671 0006 0CD0 beq .L45 + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 672 .loc 1 467 3 discriminator 2 view .LVU165 + 673 0008 0123 movs r3, #1 + 674 000a 80F87C30 strb r3, [r0, #124] + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 675 .loc 1 467 3 discriminator 2 view .LVU166 + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 676 .loc 1 470 3 discriminator 2 view .LVU167 + 677 000e 0268 ldr r2, [r0] + 678 0010 1368 ldr r3, [r2] + 679 0012 23F00203 bic r3, r3, #2 + 680 0016 1360 str r3, [r2] + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 681 .loc 1 473 3 discriminator 2 view .LVU168 + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 682 .loc 1 473 3 discriminator 2 view .LVU169 + 683 0018 0023 movs r3, #0 + 684 001a 80F87C30 strb r3, [r0, #124] + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 685 .loc 1 473 3 discriminator 2 view .LVU170 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 686 .loc 1 475 3 discriminator 2 view .LVU171 + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 687 .loc 1 475 10 is_stmt 0 discriminator 2 view .LVU172 + 688 001e 1846 mov r0, r3 + 689 .LVL49: + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 690 .loc 1 475 10 discriminator 2 view .LVU173 + 691 0020 7047 bx lr + 692 .LVL50: + 693 .L45: + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + ARM GAS /tmp/ccz0ib4C.s page 28 + + + 694 .loc 1 467 3 view .LVU174 + 695 0022 0220 movs r0, #2 + 696 .LVL51: + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 697 .loc 1 476 1 view .LVU175 + 698 0024 7047 bx lr + 699 .cfi_endproc + 700 .LFE148: + 702 .section .text.HAL_UARTEx_EnableFifoMode,"ax",%progbits + 703 .align 1 + 704 .global HAL_UARTEx_EnableFifoMode + 705 .syntax unified + 706 .thumb + 707 .thumb_func + 708 .fpu fpv5-d16 + 710 HAL_UARTEx_EnableFifoMode: + 711 .LVL52: + 712 .LFB149: + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 713 .loc 1 484 1 is_stmt 1 view -0 + 714 .cfi_startproc + 715 @ args = 0, pretend = 0, frame = 0 + 716 @ frame_needed = 0, uses_anonymous_args = 0 + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 717 .loc 1 485 3 view .LVU177 + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 718 .loc 1 488 3 view .LVU178 + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 719 .loc 1 491 3 view .LVU179 + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 720 .loc 1 491 3 view .LVU180 + 721 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 722 0004 012B cmp r3, #1 + 723 0006 1DD0 beq .L48 + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 724 .loc 1 484 1 is_stmt 0 discriminator 2 view .LVU181 + 725 0008 10B5 push {r4, lr} + 726 .LCFI13: + 727 .cfi_def_cfa_offset 8 + 728 .cfi_offset 4, -8 + 729 .cfi_offset 14, -4 + 730 000a 0446 mov r4, r0 + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 731 .loc 1 491 3 is_stmt 1 discriminator 2 view .LVU182 + 732 000c 0123 movs r3, #1 + 733 000e 80F87C30 strb r3, [r0, #124] + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 734 .loc 1 491 3 discriminator 2 view .LVU183 + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 735 .loc 1 493 3 discriminator 2 view .LVU184 + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 736 .loc 1 493 17 is_stmt 0 discriminator 2 view .LVU185 + 737 0012 2423 movs r3, #36 + 738 0014 C0F88030 str r3, [r0, #128] + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 739 .loc 1 496 3 is_stmt 1 discriminator 2 view .LVU186 + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + ARM GAS /tmp/ccz0ib4C.s page 29 + + + 740 .loc 1 496 12 is_stmt 0 discriminator 2 view .LVU187 + 741 0018 0268 ldr r2, [r0] + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 742 .loc 1 496 10 discriminator 2 view .LVU188 + 743 001a 1368 ldr r3, [r2] + 744 .LVL53: + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 745 .loc 1 499 3 is_stmt 1 discriminator 2 view .LVU189 + 746 001c 1168 ldr r1, [r2] + 747 001e 21F00101 bic r1, r1, #1 + 748 0022 1160 str r1, [r2] + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_ENABLE; + 749 .loc 1 502 3 discriminator 2 view .LVU190 + 750 0024 43F00053 orr r3, r3, #536870912 + 751 .LVL54: + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 752 .loc 1 503 3 discriminator 2 view .LVU191 + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 753 .loc 1 503 19 is_stmt 0 discriminator 2 view .LVU192 + 754 0028 4FF00052 mov r2, #536870912 + 755 002c 4266 str r2, [r0, #100] + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 756 .loc 1 506 3 is_stmt 1 discriminator 2 view .LVU193 + 757 002e 0268 ldr r2, [r0] + 758 0030 1360 str r3, [r2] + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 759 .loc 1 509 3 discriminator 2 view .LVU194 + 760 0032 FFF7FEFF bl UARTEx_SetNbDataToProcess + 761 .LVL55: + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 762 .loc 1 511 3 discriminator 2 view .LVU195 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 763 .loc 1 511 17 is_stmt 0 discriminator 2 view .LVU196 + 764 0036 2023 movs r3, #32 + 765 0038 C4F88030 str r3, [r4, #128] + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 766 .loc 1 514 3 is_stmt 1 discriminator 2 view .LVU197 + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 767 .loc 1 514 3 discriminator 2 view .LVU198 + 768 003c 0020 movs r0, #0 + 769 003e 84F87C00 strb r0, [r4, #124] + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 770 .loc 1 514 3 discriminator 2 view .LVU199 + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 771 .loc 1 516 3 discriminator 2 view .LVU200 + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 772 .loc 1 517 1 is_stmt 0 discriminator 2 view .LVU201 + 773 0042 10BD pop {r4, pc} + 774 .LVL56: + 775 .L48: + 776 .LCFI14: + 777 .cfi_def_cfa_offset 0 + 778 .cfi_restore 4 + 779 .cfi_restore 14 + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 780 .loc 1 491 3 view .LVU202 + 781 0044 0220 movs r0, #2 + ARM GAS /tmp/ccz0ib4C.s page 30 + + + 782 .LVL57: + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 783 .loc 1 517 1 view .LVU203 + 784 0046 7047 bx lr + 785 .cfi_endproc + 786 .LFE149: + 788 .section .text.HAL_UARTEx_DisableFifoMode,"ax",%progbits + 789 .align 1 + 790 .global HAL_UARTEx_DisableFifoMode + 791 .syntax unified + 792 .thumb + 793 .thumb_func + 794 .fpu fpv5-d16 + 796 HAL_UARTEx_DisableFifoMode: + 797 .LVL58: + 798 .LFB150: + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 799 .loc 1 525 1 is_stmt 1 view -0 + 800 .cfi_startproc + 801 @ args = 0, pretend = 0, frame = 0 + 802 @ frame_needed = 0, uses_anonymous_args = 0 + 803 @ link register save eliminated. + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 804 .loc 1 526 3 view .LVU205 + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 805 .loc 1 529 3 view .LVU206 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 806 .loc 1 532 3 view .LVU207 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 807 .loc 1 532 3 view .LVU208 + 808 0000 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 809 0004 012B cmp r3, #1 + 810 0006 18D0 beq .L55 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 811 .loc 1 532 3 discriminator 2 view .LVU209 + 812 0008 0123 movs r3, #1 + 813 000a 80F87C30 strb r3, [r0, #124] + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 814 .loc 1 532 3 discriminator 2 view .LVU210 + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 815 .loc 1 534 3 discriminator 2 view .LVU211 + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 816 .loc 1 534 17 is_stmt 0 discriminator 2 view .LVU212 + 817 000e 2423 movs r3, #36 + 818 0010 C0F88030 str r3, [r0, #128] + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 819 .loc 1 537 3 is_stmt 1 discriminator 2 view .LVU213 + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 820 .loc 1 537 12 is_stmt 0 discriminator 2 view .LVU214 + 821 0014 0368 ldr r3, [r0] + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 822 .loc 1 537 10 discriminator 2 view .LVU215 + 823 0016 1A68 ldr r2, [r3] + 824 .LVL59: + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 825 .loc 1 540 3 is_stmt 1 discriminator 2 view .LVU216 + 826 0018 1968 ldr r1, [r3] + ARM GAS /tmp/ccz0ib4C.s page 31 + + + 827 001a 21F00101 bic r1, r1, #1 + 828 001e 1960 str r1, [r3] + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** huart->FifoMode = UART_FIFOMODE_DISABLE; + 829 .loc 1 543 3 discriminator 2 view .LVU217 + 830 0020 22F00052 bic r2, r2, #536870912 + 831 .LVL60: + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 832 .loc 1 544 3 discriminator 2 view .LVU218 + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 833 .loc 1 544 19 is_stmt 0 discriminator 2 view .LVU219 + 834 0024 0023 movs r3, #0 + 835 0026 4366 str r3, [r0, #100] + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 836 .loc 1 547 3 is_stmt 1 discriminator 2 view .LVU220 + 837 0028 0168 ldr r1, [r0] + 838 002a 0A60 str r2, [r1] + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 839 .loc 1 549 3 discriminator 2 view .LVU221 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 840 .loc 1 549 17 is_stmt 0 discriminator 2 view .LVU222 + 841 002c 2022 movs r2, #32 + 842 .LVL61: + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 843 .loc 1 549 17 discriminator 2 view .LVU223 + 844 002e C0F88020 str r2, [r0, #128] + 845 .LVL62: + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 846 .loc 1 552 3 is_stmt 1 discriminator 2 view .LVU224 + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 847 .loc 1 552 3 discriminator 2 view .LVU225 + 848 0032 80F87C30 strb r3, [r0, #124] + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 849 .loc 1 552 3 discriminator 2 view .LVU226 + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 850 .loc 1 554 3 discriminator 2 view .LVU227 + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 851 .loc 1 554 10 is_stmt 0 discriminator 2 view .LVU228 + 852 0036 1846 mov r0, r3 + 853 .LVL63: + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 854 .loc 1 554 10 discriminator 2 view .LVU229 + 855 0038 7047 bx lr + 856 .LVL64: + 857 .L55: + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 858 .loc 1 532 3 view .LVU230 + 859 003a 0220 movs r0, #2 + 860 .LVL65: + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 861 .loc 1 555 1 view .LVU231 + 862 003c 7047 bx lr + 863 .cfi_endproc + 864 .LFE150: + 866 .section .text.HAL_UARTEx_SetTxFifoThreshold,"ax",%progbits + 867 .align 1 + 868 .global HAL_UARTEx_SetTxFifoThreshold + 869 .syntax unified + ARM GAS /tmp/ccz0ib4C.s page 32 + + + 870 .thumb + 871 .thumb_func + 872 .fpu fpv5-d16 + 874 HAL_UARTEx_SetTxFifoThreshold: + 875 .LVL66: + 876 .LFB151: + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 877 .loc 1 571 1 is_stmt 1 view -0 + 878 .cfi_startproc + 879 @ args = 0, pretend = 0, frame = 0 + 880 @ frame_needed = 0, uses_anonymous_args = 0 + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 881 .loc 1 571 1 is_stmt 0 view .LVU233 + 882 0000 38B5 push {r3, r4, r5, lr} + 883 .LCFI15: + 884 .cfi_def_cfa_offset 16 + 885 .cfi_offset 3, -16 + 886 .cfi_offset 4, -12 + 887 .cfi_offset 5, -8 + 888 .cfi_offset 14, -4 + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 889 .loc 1 572 3 is_stmt 1 view .LVU234 + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + 890 .loc 1 575 3 view .LVU235 + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 891 .loc 1 576 3 view .LVU236 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 892 .loc 1 579 3 view .LVU237 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 893 .loc 1 579 3 view .LVU238 + 894 0002 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 895 0006 012B cmp r3, #1 + 896 0008 1DD0 beq .L58 + 897 000a 0446 mov r4, r0 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 898 .loc 1 579 3 discriminator 2 view .LVU239 + 899 000c 0123 movs r3, #1 + 900 000e 80F87C30 strb r3, [r0, #124] + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 901 .loc 1 579 3 discriminator 2 view .LVU240 + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 902 .loc 1 581 3 discriminator 2 view .LVU241 + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 903 .loc 1 581 17 is_stmt 0 discriminator 2 view .LVU242 + 904 0012 2423 movs r3, #36 + 905 0014 C0F88030 str r3, [r0, #128] + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 906 .loc 1 584 3 is_stmt 1 discriminator 2 view .LVU243 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 907 .loc 1 584 12 is_stmt 0 discriminator 2 view .LVU244 + 908 0018 0368 ldr r3, [r0] + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 909 .loc 1 584 10 discriminator 2 view .LVU245 + 910 001a 1D68 ldr r5, [r3] + 911 .LVL67: + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 912 .loc 1 587 3 is_stmt 1 discriminator 2 view .LVU246 + ARM GAS /tmp/ccz0ib4C.s page 33 + + + 913 001c 1A68 ldr r2, [r3] + 914 001e 22F00102 bic r2, r2, #1 + 915 0022 1A60 str r2, [r3] + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 916 .loc 1 590 3 discriminator 2 view .LVU247 + 917 0024 0268 ldr r2, [r0] + 918 0026 9368 ldr r3, [r2, #8] + 919 0028 23F06043 bic r3, r3, #-536870912 + 920 002c 1943 orrs r1, r1, r3 + 921 .LVL68: + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 922 .loc 1 590 3 is_stmt 0 discriminator 2 view .LVU248 + 923 002e 9160 str r1, [r2, #8] + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 924 .loc 1 593 3 is_stmt 1 discriminator 2 view .LVU249 + 925 0030 FFF7FEFF bl UARTEx_SetNbDataToProcess + 926 .LVL69: + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 927 .loc 1 596 3 discriminator 2 view .LVU250 + 928 0034 2368 ldr r3, [r4] + 929 0036 1D60 str r5, [r3] + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 930 .loc 1 598 3 discriminator 2 view .LVU251 + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 931 .loc 1 598 17 is_stmt 0 discriminator 2 view .LVU252 + 932 0038 2023 movs r3, #32 + 933 003a C4F88030 str r3, [r4, #128] + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 934 .loc 1 601 3 is_stmt 1 discriminator 2 view .LVU253 + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 935 .loc 1 601 3 discriminator 2 view .LVU254 + 936 003e 0020 movs r0, #0 + 937 0040 84F87C00 strb r0, [r4, #124] + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 938 .loc 1 601 3 discriminator 2 view .LVU255 + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 939 .loc 1 603 3 discriminator 2 view .LVU256 + 940 .LVL70: + 941 .L57: + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 942 .loc 1 604 1 is_stmt 0 view .LVU257 + 943 0044 38BD pop {r3, r4, r5, pc} + 944 .LVL71: + 945 .L58: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 946 .loc 1 579 3 view .LVU258 + 947 0046 0220 movs r0, #2 + 948 .LVL72: + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 949 .loc 1 579 3 view .LVU259 + 950 0048 FCE7 b .L57 + 951 .cfi_endproc + 952 .LFE151: + 954 .section .text.HAL_UARTEx_SetRxFifoThreshold,"ax",%progbits + 955 .align 1 + 956 .global HAL_UARTEx_SetRxFifoThreshold + 957 .syntax unified + ARM GAS /tmp/ccz0ib4C.s page 34 + + + 958 .thumb + 959 .thumb_func + 960 .fpu fpv5-d16 + 962 HAL_UARTEx_SetRxFifoThreshold: + 963 .LVL73: + 964 .LFB152: + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 965 .loc 1 620 1 is_stmt 1 view -0 + 966 .cfi_startproc + 967 @ args = 0, pretend = 0, frame = 0 + 968 @ frame_needed = 0, uses_anonymous_args = 0 + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** uint32_t tmpcr1; + 969 .loc 1 620 1 is_stmt 0 view .LVU261 + 970 0000 38B5 push {r3, r4, r5, lr} + 971 .LCFI16: + 972 .cfi_def_cfa_offset 16 + 973 .cfi_offset 3, -16 + 974 .cfi_offset 4, -12 + 975 .cfi_offset 5, -8 + 976 .cfi_offset 14, -4 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 977 .loc 1 621 3 is_stmt 1 view .LVU262 + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + 978 .loc 1 624 3 view .LVU263 + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 979 .loc 1 625 3 view .LVU264 + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 980 .loc 1 628 3 view .LVU265 + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 981 .loc 1 628 3 view .LVU266 + 982 0002 90F87C30 ldrb r3, [r0, #124] @ zero_extendqisi2 + 983 0006 012B cmp r3, #1 + 984 0008 1DD0 beq .L62 + 985 000a 0446 mov r4, r0 + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 986 .loc 1 628 3 discriminator 2 view .LVU267 + 987 000c 0123 movs r3, #1 + 988 000e 80F87C30 strb r3, [r0, #124] + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 989 .loc 1 628 3 discriminator 2 view .LVU268 + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 990 .loc 1 630 3 discriminator 2 view .LVU269 + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 991 .loc 1 630 17 is_stmt 0 discriminator 2 view .LVU270 + 992 0012 2423 movs r3, #36 + 993 0014 C0F88030 str r3, [r0, #128] + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 994 .loc 1 633 3 is_stmt 1 discriminator 2 view .LVU271 + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 995 .loc 1 633 12 is_stmt 0 discriminator 2 view .LVU272 + 996 0018 0368 ldr r3, [r0] + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 997 .loc 1 633 10 discriminator 2 view .LVU273 + 998 001a 1D68 ldr r5, [r3] + 999 .LVL74: + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1000 .loc 1 636 3 is_stmt 1 discriminator 2 view .LVU274 + ARM GAS /tmp/ccz0ib4C.s page 35 + + + 1001 001c 1A68 ldr r2, [r3] + 1002 001e 22F00102 bic r2, r2, #1 + 1003 0022 1A60 str r2, [r3] + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1004 .loc 1 639 3 discriminator 2 view .LVU275 + 1005 0024 0268 ldr r2, [r0] + 1006 0026 9368 ldr r3, [r2, #8] + 1007 0028 23F06063 bic r3, r3, #234881024 + 1008 002c 1943 orrs r1, r1, r3 + 1009 .LVL75: + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1010 .loc 1 639 3 is_stmt 0 discriminator 2 view .LVU276 + 1011 002e 9160 str r1, [r2, #8] + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1012 .loc 1 642 3 is_stmt 1 discriminator 2 view .LVU277 + 1013 0030 FFF7FEFF bl UARTEx_SetNbDataToProcess + 1014 .LVL76: + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1015 .loc 1 645 3 discriminator 2 view .LVU278 + 1016 0034 2368 ldr r3, [r4] + 1017 0036 1D60 str r5, [r3] + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1018 .loc 1 647 3 discriminator 2 view .LVU279 + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1019 .loc 1 647 17 is_stmt 0 discriminator 2 view .LVU280 + 1020 0038 2023 movs r3, #32 + 1021 003a C4F88030 str r3, [r4, #128] + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1022 .loc 1 650 3 is_stmt 1 discriminator 2 view .LVU281 + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1023 .loc 1 650 3 discriminator 2 view .LVU282 + 1024 003e 0020 movs r0, #0 + 1025 0040 84F87C00 strb r0, [r4, #124] + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1026 .loc 1 650 3 discriminator 2 view .LVU283 + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** } + 1027 .loc 1 652 3 discriminator 2 view .LVU284 + 1028 .LVL77: + 1029 .L61: + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1030 .loc 1 653 1 is_stmt 0 view .LVU285 + 1031 0044 38BD pop {r3, r4, r5, pc} + 1032 .LVL78: + 1033 .L62: + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1034 .loc 1 628 3 view .LVU286 + 1035 0046 0220 movs r0, #2 + 1036 .LVL79: + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c **** + 1037 .loc 1 628 3 view .LVU287 + 1038 0048 FCE7 b .L61 + 1039 .cfi_endproc + 1040 .LFE152: + 1042 .section .rodata + 1043 .align 2 + 1044 .set .LANCHOR0,. + 0 + 1045 .LC0: + ARM GAS /tmp/ccz0ib4C.s page 36 + + + 1046 0000 01010103 .ascii "\001\001\001\003\007\001\000\000" + 1046 07010000 + 1047 .text + 1048 .Letext0: + 1049 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1050 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1051 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1052 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 1053 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1054 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 1055 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" + 1056 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h" + 1057 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccz0ib4C.s page 37 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_hal_uart_ex.c + /tmp/ccz0ib4C.s:17 .text.UARTEx_Wakeup_AddressConfig:0000000000000000 $t + /tmp/ccz0ib4C.s:24 .text.UARTEx_Wakeup_AddressConfig:0000000000000000 UARTEx_Wakeup_AddressConfig + /tmp/ccz0ib4C.s:64 .rodata.UARTEx_SetNbDataToProcess.str1.4:0000000000000000 $d + /tmp/ccz0ib4C.s:68 .text.UARTEx_SetNbDataToProcess:0000000000000000 $t + /tmp/ccz0ib4C.s:74 .text.UARTEx_SetNbDataToProcess:0000000000000000 UARTEx_SetNbDataToProcess + /tmp/ccz0ib4C.s:177 .text.UARTEx_SetNbDataToProcess:0000000000000068 $d + /tmp/ccz0ib4C.s:183 .text.HAL_RS485Ex_Init:0000000000000000 $t + /tmp/ccz0ib4C.s:190 .text.HAL_RS485Ex_Init:0000000000000000 HAL_RS485Ex_Init + /tmp/ccz0ib4C.s:327 .text.HAL_RS485Ex_Init:0000000000000084 $d + /tmp/ccz0ib4C.s:332 .text.HAL_UARTEx_WakeupCallback:0000000000000000 $t + /tmp/ccz0ib4C.s:339 .text.HAL_UARTEx_WakeupCallback:0000000000000000 HAL_UARTEx_WakeupCallback + /tmp/ccz0ib4C.s:354 .text.HAL_UARTEx_RxFifoFullCallback:0000000000000000 $t + /tmp/ccz0ib4C.s:361 .text.HAL_UARTEx_RxFifoFullCallback:0000000000000000 HAL_UARTEx_RxFifoFullCallback + /tmp/ccz0ib4C.s:376 .text.HAL_UARTEx_TxFifoEmptyCallback:0000000000000000 $t + /tmp/ccz0ib4C.s:383 .text.HAL_UARTEx_TxFifoEmptyCallback:0000000000000000 HAL_UARTEx_TxFifoEmptyCallback + /tmp/ccz0ib4C.s:398 .text.HAL_MultiProcessorEx_AddressLength_Set:0000000000000000 $t + /tmp/ccz0ib4C.s:405 .text.HAL_MultiProcessorEx_AddressLength_Set:0000000000000000 HAL_MultiProcessorEx_AddressLength_Set + /tmp/ccz0ib4C.s:469 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:0000000000000000 $t + /tmp/ccz0ib4C.s:476 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:0000000000000000 HAL_UARTEx_StopModeWakeUpSourceConfig + /tmp/ccz0ib4C.s:601 .text.HAL_UARTEx_EnableStopMode:0000000000000000 $t + /tmp/ccz0ib4C.s:608 .text.HAL_UARTEx_EnableStopMode:0000000000000000 HAL_UARTEx_EnableStopMode + /tmp/ccz0ib4C.s:652 .text.HAL_UARTEx_DisableStopMode:0000000000000000 $t + /tmp/ccz0ib4C.s:659 .text.HAL_UARTEx_DisableStopMode:0000000000000000 HAL_UARTEx_DisableStopMode + /tmp/ccz0ib4C.s:703 .text.HAL_UARTEx_EnableFifoMode:0000000000000000 $t + /tmp/ccz0ib4C.s:710 .text.HAL_UARTEx_EnableFifoMode:0000000000000000 HAL_UARTEx_EnableFifoMode + /tmp/ccz0ib4C.s:789 .text.HAL_UARTEx_DisableFifoMode:0000000000000000 $t + /tmp/ccz0ib4C.s:796 .text.HAL_UARTEx_DisableFifoMode:0000000000000000 HAL_UARTEx_DisableFifoMode + /tmp/ccz0ib4C.s:867 .text.HAL_UARTEx_SetTxFifoThreshold:0000000000000000 $t + /tmp/ccz0ib4C.s:874 .text.HAL_UARTEx_SetTxFifoThreshold:0000000000000000 HAL_UARTEx_SetTxFifoThreshold + /tmp/ccz0ib4C.s:955 .text.HAL_UARTEx_SetRxFifoThreshold:0000000000000000 $t + /tmp/ccz0ib4C.s:962 .text.HAL_UARTEx_SetRxFifoThreshold:0000000000000000 HAL_UARTEx_SetRxFifoThreshold + /tmp/ccz0ib4C.s:1043 .rodata:0000000000000000 $d + +UNDEFINED SYMBOLS +UART_SetConfig +UART_CheckIdleState +HAL_UART_MspInit +UART_AdvFeatureConfig +HAL_GetTick +UART_WaitOnFlagUntilTimeout diff --git a/build/stm32h7xx_hal_uart_ex.o b/build/stm32h7xx_hal_uart_ex.o new file mode 100644 index 0000000..bda82e7 Binary files /dev/null and b/build/stm32h7xx_hal_uart_ex.o differ diff --git a/build/stm32h7xx_it.d b/build/stm32h7xx_it.d new file mode 100644 index 0000000..4396044 --- /dev/null +++ b/build/stm32h7xx_it.d @@ -0,0 +1,72 @@ +build/stm32h7xx_it.o: Core/Src/stm32h7xx_it.c Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/stm32h7xx_it.h +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/stm32h7xx_it.h: diff --git a/build/stm32h7xx_it.lst b/build/stm32h7xx_it.lst new file mode 100644 index 0000000..581d53b --- /dev/null +++ b/build/stm32h7xx_it.lst @@ -0,0 +1,929 @@ +ARM GAS /tmp/ccHBkk1J.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_it.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.NMI_Handler,"ax",%progbits + 17 .align 1 + 18 .global NMI_Handler + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 NMI_Handler: + 26 .LFB141: + 27 .file 1 "Core/Src/stm32h7xx_it.c" + 1:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32h7xx_it.c **** /** + 3:Core/Src/stm32h7xx_it.c **** ****************************************************************************** + 4:Core/Src/stm32h7xx_it.c **** * @file stm32h7xx_it.c + 5:Core/Src/stm32h7xx_it.c **** * @brief Interrupt Service Routines. + 6:Core/Src/stm32h7xx_it.c **** ****************************************************************************** + 7:Core/Src/stm32h7xx_it.c **** * @attention + 8:Core/Src/stm32h7xx_it.c **** * + 9:Core/Src/stm32h7xx_it.c **** *

© Copyright (c) 2019 STMicroelectronics. + 10:Core/Src/stm32h7xx_it.c **** * All rights reserved.

+ 11:Core/Src/stm32h7xx_it.c **** * + 12:Core/Src/stm32h7xx_it.c **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Core/Src/stm32h7xx_it.c **** * the "License"; You may not use this file except in compliance with the + 14:Core/Src/stm32h7xx_it.c **** * License. You may obtain a copy of the License at: + 15:Core/Src/stm32h7xx_it.c **** * opensource.org/licenses/BSD-3-Clause + 16:Core/Src/stm32h7xx_it.c **** * + 17:Core/Src/stm32h7xx_it.c **** ****************************************************************************** + 18:Core/Src/stm32h7xx_it.c **** */ + 19:Core/Src/stm32h7xx_it.c **** /* USER CODE END Header */ + 20:Core/Src/stm32h7xx_it.c **** + 21:Core/Src/stm32h7xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 22:Core/Src/stm32h7xx_it.c **** #include "main.h" + 23:Core/Src/stm32h7xx_it.c **** #include "stm32h7xx_it.h" + 24:Core/Src/stm32h7xx_it.c **** /* Private includes ----------------------------------------------------------*/ + 25:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN Includes */ + 26:Core/Src/stm32h7xx_it.c **** /* USER CODE END Includes */ + 27:Core/Src/stm32h7xx_it.c **** + 28:Core/Src/stm32h7xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 29:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN TD */ + 30:Core/Src/stm32h7xx_it.c **** + 31:Core/Src/stm32h7xx_it.c **** /* USER CODE END TD */ + ARM GAS /tmp/ccHBkk1J.s page 2 + + + 32:Core/Src/stm32h7xx_it.c **** + 33:Core/Src/stm32h7xx_it.c **** /* Private define ------------------------------------------------------------*/ + 34:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PD */ + 35:Core/Src/stm32h7xx_it.c **** + 36:Core/Src/stm32h7xx_it.c **** /* USER CODE END PD */ + 37:Core/Src/stm32h7xx_it.c **** + 38:Core/Src/stm32h7xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 39:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PM */ + 40:Core/Src/stm32h7xx_it.c **** + 41:Core/Src/stm32h7xx_it.c **** /* USER CODE END PM */ + 42:Core/Src/stm32h7xx_it.c **** + 43:Core/Src/stm32h7xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 44:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PV */ + 45:Core/Src/stm32h7xx_it.c **** + 46:Core/Src/stm32h7xx_it.c **** /* USER CODE END PV */ + 47:Core/Src/stm32h7xx_it.c **** + 48:Core/Src/stm32h7xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 49:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PFP */ + 50:Core/Src/stm32h7xx_it.c **** + 51:Core/Src/stm32h7xx_it.c **** /* USER CODE END PFP */ + 52:Core/Src/stm32h7xx_it.c **** + 53:Core/Src/stm32h7xx_it.c **** /* Private user code ---------------------------------------------------------*/ + 54:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN 0 */ + 55:Core/Src/stm32h7xx_it.c **** + 56:Core/Src/stm32h7xx_it.c **** /* USER CODE END 0 */ + 57:Core/Src/stm32h7xx_it.c **** + 58:Core/Src/stm32h7xx_it.c **** /* External variables --------------------------------------------------------*/ + 59:Core/Src/stm32h7xx_it.c **** extern PCD_HandleTypeDef hpcd_USB_OTG_FS; + 60:Core/Src/stm32h7xx_it.c **** extern QSPI_HandleTypeDef hqspi; + 61:Core/Src/stm32h7xx_it.c **** extern UART_HandleTypeDef huart1; + 62:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN EV */ + 63:Core/Src/stm32h7xx_it.c **** + 64:Core/Src/stm32h7xx_it.c **** /* USER CODE END EV */ + 65:Core/Src/stm32h7xx_it.c **** + 66:Core/Src/stm32h7xx_it.c **** /******************************************************************************/ + 67:Core/Src/stm32h7xx_it.c **** /* Cortex Processor Interruption and Exception Handlers */ + 68:Core/Src/stm32h7xx_it.c **** /******************************************************************************/ + 69:Core/Src/stm32h7xx_it.c **** /** + 70:Core/Src/stm32h7xx_it.c **** * @brief This function handles Non maskable interrupt. + 71:Core/Src/stm32h7xx_it.c **** */ + 72:Core/Src/stm32h7xx_it.c **** void NMI_Handler(void) + 73:Core/Src/stm32h7xx_it.c **** { + 28 .loc 1 73 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 74:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + 75:Core/Src/stm32h7xx_it.c **** + 76:Core/Src/stm32h7xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ + 77:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + 78:Core/Src/stm32h7xx_it.c **** + 79:Core/Src/stm32h7xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ + 80:Core/Src/stm32h7xx_it.c **** } + 33 .loc 1 80 1 view .LVU1 + 34 0000 7047 bx lr + 35 .cfi_endproc + ARM GAS /tmp/ccHBkk1J.s page 3 + + + 36 .LFE141: + 38 .section .text.HardFault_Handler,"ax",%progbits + 39 .align 1 + 40 .global HardFault_Handler + 41 .syntax unified + 42 .thumb + 43 .thumb_func + 44 .fpu fpv5-d16 + 46 HardFault_Handler: + 47 .LFB142: + 81:Core/Src/stm32h7xx_it.c **** + 82:Core/Src/stm32h7xx_it.c **** /** + 83:Core/Src/stm32h7xx_it.c **** * @brief This function handles Hard fault interrupt. + 84:Core/Src/stm32h7xx_it.c **** */ + 85:Core/Src/stm32h7xx_it.c **** void HardFault_Handler(void) + 86:Core/Src/stm32h7xx_it.c **** { + 48 .loc 1 86 1 view -0 + 49 .cfi_startproc + 50 @ Volatile: function does not return. + 51 @ args = 0, pretend = 0, frame = 0 + 52 @ frame_needed = 0, uses_anonymous_args = 0 + 53 @ link register save eliminated. + 54 .L3: + 87:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ + 88:Core/Src/stm32h7xx_it.c **** + 89:Core/Src/stm32h7xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ + 90:Core/Src/stm32h7xx_it.c **** while (1) + 55 .loc 1 90 3 discriminator 1 view .LVU3 + 91:Core/Src/stm32h7xx_it.c **** { + 92:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + 93:Core/Src/stm32h7xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ + 94:Core/Src/stm32h7xx_it.c **** } + 56 .loc 1 94 3 discriminator 1 view .LVU4 + 90:Core/Src/stm32h7xx_it.c **** { + 57 .loc 1 90 9 discriminator 1 view .LVU5 + 58 0000 FEE7 b .L3 + 59 .cfi_endproc + 60 .LFE142: + 62 .section .text.MemManage_Handler,"ax",%progbits + 63 .align 1 + 64 .global MemManage_Handler + 65 .syntax unified + 66 .thumb + 67 .thumb_func + 68 .fpu fpv5-d16 + 70 MemManage_Handler: + 71 .LFB143: + 95:Core/Src/stm32h7xx_it.c **** } + 96:Core/Src/stm32h7xx_it.c **** + 97:Core/Src/stm32h7xx_it.c **** /** + 98:Core/Src/stm32h7xx_it.c **** * @brief This function handles Memory management fault. + 99:Core/Src/stm32h7xx_it.c **** */ + 100:Core/Src/stm32h7xx_it.c **** void MemManage_Handler(void) + 101:Core/Src/stm32h7xx_it.c **** { + 72 .loc 1 101 1 view -0 + 73 .cfi_startproc + 74 @ Volatile: function does not return. + ARM GAS /tmp/ccHBkk1J.s page 4 + + + 75 @ args = 0, pretend = 0, frame = 0 + 76 @ frame_needed = 0, uses_anonymous_args = 0 + 77 @ link register save eliminated. + 78 .L5: + 102:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + 103:Core/Src/stm32h7xx_it.c **** + 104:Core/Src/stm32h7xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ + 105:Core/Src/stm32h7xx_it.c **** while (1) + 79 .loc 1 105 3 discriminator 1 view .LVU7 + 106:Core/Src/stm32h7xx_it.c **** { + 107:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + 108:Core/Src/stm32h7xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ + 109:Core/Src/stm32h7xx_it.c **** } + 80 .loc 1 109 3 discriminator 1 view .LVU8 + 105:Core/Src/stm32h7xx_it.c **** { + 81 .loc 1 105 9 discriminator 1 view .LVU9 + 82 0000 FEE7 b .L5 + 83 .cfi_endproc + 84 .LFE143: + 86 .section .text.BusFault_Handler,"ax",%progbits + 87 .align 1 + 88 .global BusFault_Handler + 89 .syntax unified + 90 .thumb + 91 .thumb_func + 92 .fpu fpv5-d16 + 94 BusFault_Handler: + 95 .LFB144: + 110:Core/Src/stm32h7xx_it.c **** } + 111:Core/Src/stm32h7xx_it.c **** + 112:Core/Src/stm32h7xx_it.c **** /** + 113:Core/Src/stm32h7xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault. + 114:Core/Src/stm32h7xx_it.c **** */ + 115:Core/Src/stm32h7xx_it.c **** void BusFault_Handler(void) + 116:Core/Src/stm32h7xx_it.c **** { + 96 .loc 1 116 1 view -0 + 97 .cfi_startproc + 98 @ Volatile: function does not return. + 99 @ args = 0, pretend = 0, frame = 0 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 101 @ link register save eliminated. + 102 .L7: + 117:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ + 118:Core/Src/stm32h7xx_it.c **** + 119:Core/Src/stm32h7xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ + 120:Core/Src/stm32h7xx_it.c **** while (1) + 103 .loc 1 120 3 discriminator 1 view .LVU11 + 121:Core/Src/stm32h7xx_it.c **** { + 122:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + 123:Core/Src/stm32h7xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ + 124:Core/Src/stm32h7xx_it.c **** } + 104 .loc 1 124 3 discriminator 1 view .LVU12 + 120:Core/Src/stm32h7xx_it.c **** { + 105 .loc 1 120 9 discriminator 1 view .LVU13 + 106 0000 FEE7 b .L7 + 107 .cfi_endproc + 108 .LFE144: + ARM GAS /tmp/ccHBkk1J.s page 5 + + + 110 .section .text.UsageFault_Handler,"ax",%progbits + 111 .align 1 + 112 .global UsageFault_Handler + 113 .syntax unified + 114 .thumb + 115 .thumb_func + 116 .fpu fpv5-d16 + 118 UsageFault_Handler: + 119 .LFB145: + 125:Core/Src/stm32h7xx_it.c **** } + 126:Core/Src/stm32h7xx_it.c **** + 127:Core/Src/stm32h7xx_it.c **** /** + 128:Core/Src/stm32h7xx_it.c **** * @brief This function handles Undefined instruction or illegal state. + 129:Core/Src/stm32h7xx_it.c **** */ + 130:Core/Src/stm32h7xx_it.c **** void UsageFault_Handler(void) + 131:Core/Src/stm32h7xx_it.c **** { + 120 .loc 1 131 1 view -0 + 121 .cfi_startproc + 122 @ Volatile: function does not return. + 123 @ args = 0, pretend = 0, frame = 0 + 124 @ frame_needed = 0, uses_anonymous_args = 0 + 125 @ link register save eliminated. + 126 .L9: + 132:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ + 133:Core/Src/stm32h7xx_it.c **** + 134:Core/Src/stm32h7xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ + 135:Core/Src/stm32h7xx_it.c **** while (1) + 127 .loc 1 135 3 discriminator 1 view .LVU15 + 136:Core/Src/stm32h7xx_it.c **** { + 137:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + 138:Core/Src/stm32h7xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ + 139:Core/Src/stm32h7xx_it.c **** } + 128 .loc 1 139 3 discriminator 1 view .LVU16 + 135:Core/Src/stm32h7xx_it.c **** { + 129 .loc 1 135 9 discriminator 1 view .LVU17 + 130 0000 FEE7 b .L9 + 131 .cfi_endproc + 132 .LFE145: + 134 .section .text.SVC_Handler,"ax",%progbits + 135 .align 1 + 136 .global SVC_Handler + 137 .syntax unified + 138 .thumb + 139 .thumb_func + 140 .fpu fpv5-d16 + 142 SVC_Handler: + 143 .LFB146: + 140:Core/Src/stm32h7xx_it.c **** } + 141:Core/Src/stm32h7xx_it.c **** + 142:Core/Src/stm32h7xx_it.c **** /** + 143:Core/Src/stm32h7xx_it.c **** * @brief This function handles System service call via SWI instruction. + 144:Core/Src/stm32h7xx_it.c **** */ + 145:Core/Src/stm32h7xx_it.c **** void SVC_Handler(void) + 146:Core/Src/stm32h7xx_it.c **** { + 144 .loc 1 146 1 view -0 + 145 .cfi_startproc + 146 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccHBkk1J.s page 6 + + + 147 @ frame_needed = 0, uses_anonymous_args = 0 + 148 @ link register save eliminated. + 147:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ + 148:Core/Src/stm32h7xx_it.c **** + 149:Core/Src/stm32h7xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ + 150:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ + 151:Core/Src/stm32h7xx_it.c **** + 152:Core/Src/stm32h7xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ + 153:Core/Src/stm32h7xx_it.c **** } + 149 .loc 1 153 1 view .LVU19 + 150 0000 7047 bx lr + 151 .cfi_endproc + 152 .LFE146: + 154 .section .text.DebugMon_Handler,"ax",%progbits + 155 .align 1 + 156 .global DebugMon_Handler + 157 .syntax unified + 158 .thumb + 159 .thumb_func + 160 .fpu fpv5-d16 + 162 DebugMon_Handler: + 163 .LFB147: + 154:Core/Src/stm32h7xx_it.c **** + 155:Core/Src/stm32h7xx_it.c **** /** + 156:Core/Src/stm32h7xx_it.c **** * @brief This function handles Debug monitor. + 157:Core/Src/stm32h7xx_it.c **** */ + 158:Core/Src/stm32h7xx_it.c **** void DebugMon_Handler(void) + 159:Core/Src/stm32h7xx_it.c **** { + 164 .loc 1 159 1 view -0 + 165 .cfi_startproc + 166 @ args = 0, pretend = 0, frame = 0 + 167 @ frame_needed = 0, uses_anonymous_args = 0 + 168 @ link register save eliminated. + 160:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + 161:Core/Src/stm32h7xx_it.c **** + 162:Core/Src/stm32h7xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ + 163:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + 164:Core/Src/stm32h7xx_it.c **** + 165:Core/Src/stm32h7xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ + 166:Core/Src/stm32h7xx_it.c **** } + 169 .loc 1 166 1 view .LVU21 + 170 0000 7047 bx lr + 171 .cfi_endproc + 172 .LFE147: + 174 .section .text.PendSV_Handler,"ax",%progbits + 175 .align 1 + 176 .global PendSV_Handler + 177 .syntax unified + 178 .thumb + 179 .thumb_func + 180 .fpu fpv5-d16 + 182 PendSV_Handler: + 183 .LFB148: + 167:Core/Src/stm32h7xx_it.c **** + 168:Core/Src/stm32h7xx_it.c **** /** + 169:Core/Src/stm32h7xx_it.c **** * @brief This function handles Pendable request for system service. + 170:Core/Src/stm32h7xx_it.c **** */ + ARM GAS /tmp/ccHBkk1J.s page 7 + + + 171:Core/Src/stm32h7xx_it.c **** void PendSV_Handler(void) + 172:Core/Src/stm32h7xx_it.c **** { + 184 .loc 1 172 1 view -0 + 185 .cfi_startproc + 186 @ args = 0, pretend = 0, frame = 0 + 187 @ frame_needed = 0, uses_anonymous_args = 0 + 188 @ link register save eliminated. + 173:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ + 174:Core/Src/stm32h7xx_it.c **** + 175:Core/Src/stm32h7xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ + 176:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ + 177:Core/Src/stm32h7xx_it.c **** + 178:Core/Src/stm32h7xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ + 179:Core/Src/stm32h7xx_it.c **** } + 189 .loc 1 179 1 view .LVU23 + 190 0000 7047 bx lr + 191 .cfi_endproc + 192 .LFE148: + 194 .section .text.SysTick_Handler,"ax",%progbits + 195 .align 1 + 196 .global SysTick_Handler + 197 .syntax unified + 198 .thumb + 199 .thumb_func + 200 .fpu fpv5-d16 + 202 SysTick_Handler: + 203 .LFB149: + 180:Core/Src/stm32h7xx_it.c **** + 181:Core/Src/stm32h7xx_it.c **** /** + 182:Core/Src/stm32h7xx_it.c **** * @brief This function handles System tick timer. + 183:Core/Src/stm32h7xx_it.c **** */ + 184:Core/Src/stm32h7xx_it.c **** void SysTick_Handler(void) + 185:Core/Src/stm32h7xx_it.c **** { + 204 .loc 1 185 1 view -0 + 205 .cfi_startproc + 206 @ args = 0, pretend = 0, frame = 0 + 207 @ frame_needed = 0, uses_anonymous_args = 0 + 208 0000 08B5 push {r3, lr} + 209 .LCFI0: + 210 .cfi_def_cfa_offset 8 + 211 .cfi_offset 3, -8 + 212 .cfi_offset 14, -4 + 186:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ + 187:Core/Src/stm32h7xx_it.c **** + 188:Core/Src/stm32h7xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ + 189:Core/Src/stm32h7xx_it.c **** HAL_IncTick(); + 213 .loc 1 189 3 view .LVU25 + 214 0002 FFF7FEFF bl HAL_IncTick + 215 .LVL0: + 190:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ + 191:Core/Src/stm32h7xx_it.c **** + 192:Core/Src/stm32h7xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ + 193:Core/Src/stm32h7xx_it.c **** } + 216 .loc 1 193 1 is_stmt 0 view .LVU26 + 217 0006 08BD pop {r3, pc} + 218 .cfi_endproc + 219 .LFE149: + ARM GAS /tmp/ccHBkk1J.s page 8 + + + 221 .section .text.PVD_AVD_IRQHandler,"ax",%progbits + 222 .align 1 + 223 .global PVD_AVD_IRQHandler + 224 .syntax unified + 225 .thumb + 226 .thumb_func + 227 .fpu fpv5-d16 + 229 PVD_AVD_IRQHandler: + 230 .LFB150: + 194:Core/Src/stm32h7xx_it.c **** + 195:Core/Src/stm32h7xx_it.c **** /******************************************************************************/ + 196:Core/Src/stm32h7xx_it.c **** /* STM32H7xx Peripheral Interrupt Handlers */ + 197:Core/Src/stm32h7xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */ + 198:Core/Src/stm32h7xx_it.c **** /* For the available peripheral interrupt handler names, */ + 199:Core/Src/stm32h7xx_it.c **** /* please refer to the startup file (startup_stm32h7xx.s). */ + 200:Core/Src/stm32h7xx_it.c **** /******************************************************************************/ + 201:Core/Src/stm32h7xx_it.c **** + 202:Core/Src/stm32h7xx_it.c **** /** + 203:Core/Src/stm32h7xx_it.c **** * @brief This function handles PVD and AVD interrupts through EXTI line 16. + 204:Core/Src/stm32h7xx_it.c **** */ + 205:Core/Src/stm32h7xx_it.c **** void PVD_AVD_IRQHandler(void) + 206:Core/Src/stm32h7xx_it.c **** { + 231 .loc 1 206 1 is_stmt 1 view -0 + 232 .cfi_startproc + 233 @ args = 0, pretend = 0, frame = 0 + 234 @ frame_needed = 0, uses_anonymous_args = 0 + 235 0000 08B5 push {r3, lr} + 236 .LCFI1: + 237 .cfi_def_cfa_offset 8 + 238 .cfi_offset 3, -8 + 239 .cfi_offset 14, -4 + 207:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PVD_AVD_IRQn 0 */ + 208:Core/Src/stm32h7xx_it.c **** + 209:Core/Src/stm32h7xx_it.c **** /* USER CODE END PVD_AVD_IRQn 0 */ + 210:Core/Src/stm32h7xx_it.c **** HAL_PWREx_PVD_AVD_IRQHandler(); + 240 .loc 1 210 3 view .LVU28 + 241 0002 FFF7FEFF bl HAL_PWREx_PVD_AVD_IRQHandler + 242 .LVL1: + 211:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN PVD_AVD_IRQn 1 */ + 212:Core/Src/stm32h7xx_it.c **** + 213:Core/Src/stm32h7xx_it.c **** /* USER CODE END PVD_AVD_IRQn 1 */ + 214:Core/Src/stm32h7xx_it.c **** } + 243 .loc 1 214 1 is_stmt 0 view .LVU29 + 244 0006 08BD pop {r3, pc} + 245 .cfi_endproc + 246 .LFE150: + 248 .section .text.FLASH_IRQHandler,"ax",%progbits + 249 .align 1 + 250 .global FLASH_IRQHandler + 251 .syntax unified + 252 .thumb + 253 .thumb_func + 254 .fpu fpv5-d16 + 256 FLASH_IRQHandler: + 257 .LFB151: + 215:Core/Src/stm32h7xx_it.c **** + 216:Core/Src/stm32h7xx_it.c **** /** + ARM GAS /tmp/ccHBkk1J.s page 9 + + + 217:Core/Src/stm32h7xx_it.c **** * @brief This function handles Flash global interrupt. + 218:Core/Src/stm32h7xx_it.c **** */ + 219:Core/Src/stm32h7xx_it.c **** void FLASH_IRQHandler(void) + 220:Core/Src/stm32h7xx_it.c **** { + 258 .loc 1 220 1 is_stmt 1 view -0 + 259 .cfi_startproc + 260 @ args = 0, pretend = 0, frame = 0 + 261 @ frame_needed = 0, uses_anonymous_args = 0 + 262 0000 08B5 push {r3, lr} + 263 .LCFI2: + 264 .cfi_def_cfa_offset 8 + 265 .cfi_offset 3, -8 + 266 .cfi_offset 14, -4 + 221:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN FLASH_IRQn 0 */ + 222:Core/Src/stm32h7xx_it.c **** + 223:Core/Src/stm32h7xx_it.c **** /* USER CODE END FLASH_IRQn 0 */ + 224:Core/Src/stm32h7xx_it.c **** HAL_FLASH_IRQHandler(); + 267 .loc 1 224 3 view .LVU31 + 268 0002 FFF7FEFF bl HAL_FLASH_IRQHandler + 269 .LVL2: + 225:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN FLASH_IRQn 1 */ + 226:Core/Src/stm32h7xx_it.c **** + 227:Core/Src/stm32h7xx_it.c **** /* USER CODE END FLASH_IRQn 1 */ + 228:Core/Src/stm32h7xx_it.c **** } + 270 .loc 1 228 1 is_stmt 0 view .LVU32 + 271 0006 08BD pop {r3, pc} + 272 .cfi_endproc + 273 .LFE151: + 275 .section .text.RCC_IRQHandler,"ax",%progbits + 276 .align 1 + 277 .global RCC_IRQHandler + 278 .syntax unified + 279 .thumb + 280 .thumb_func + 281 .fpu fpv5-d16 + 283 RCC_IRQHandler: + 284 .LFB152: + 229:Core/Src/stm32h7xx_it.c **** + 230:Core/Src/stm32h7xx_it.c **** /** + 231:Core/Src/stm32h7xx_it.c **** * @brief This function handles RCC global interrupt. + 232:Core/Src/stm32h7xx_it.c **** */ + 233:Core/Src/stm32h7xx_it.c **** void RCC_IRQHandler(void) + 234:Core/Src/stm32h7xx_it.c **** { + 285 .loc 1 234 1 is_stmt 1 view -0 + 286 .cfi_startproc + 287 @ args = 0, pretend = 0, frame = 0 + 288 @ frame_needed = 0, uses_anonymous_args = 0 + 289 @ link register save eliminated. + 235:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN RCC_IRQn 0 */ + 236:Core/Src/stm32h7xx_it.c **** + 237:Core/Src/stm32h7xx_it.c **** /* USER CODE END RCC_IRQn 0 */ + 238:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN RCC_IRQn 1 */ + 239:Core/Src/stm32h7xx_it.c **** + 240:Core/Src/stm32h7xx_it.c **** /* USER CODE END RCC_IRQn 1 */ + 241:Core/Src/stm32h7xx_it.c **** } + 290 .loc 1 241 1 view .LVU34 + 291 0000 7047 bx lr + ARM GAS /tmp/ccHBkk1J.s page 10 + + + 292 .cfi_endproc + 293 .LFE152: + 295 .section .text.USART1_IRQHandler,"ax",%progbits + 296 .align 1 + 297 .global USART1_IRQHandler + 298 .syntax unified + 299 .thumb + 300 .thumb_func + 301 .fpu fpv5-d16 + 303 USART1_IRQHandler: + 304 .LFB153: + 242:Core/Src/stm32h7xx_it.c **** + 243:Core/Src/stm32h7xx_it.c **** /** + 244:Core/Src/stm32h7xx_it.c **** * @brief This function handles USART1 global interrupt. + 245:Core/Src/stm32h7xx_it.c **** */ + 246:Core/Src/stm32h7xx_it.c **** void USART1_IRQHandler(void) + 247:Core/Src/stm32h7xx_it.c **** { + 305 .loc 1 247 1 view -0 + 306 .cfi_startproc + 307 @ args = 0, pretend = 0, frame = 0 + 308 @ frame_needed = 0, uses_anonymous_args = 0 + 309 0000 08B5 push {r3, lr} + 310 .LCFI3: + 311 .cfi_def_cfa_offset 8 + 312 .cfi_offset 3, -8 + 313 .cfi_offset 14, -4 + 248:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN USART1_IRQn 0 */ + 249:Core/Src/stm32h7xx_it.c **** + 250:Core/Src/stm32h7xx_it.c **** /* USER CODE END USART1_IRQn 0 */ + 251:Core/Src/stm32h7xx_it.c **** HAL_UART_IRQHandler(&huart1); + 314 .loc 1 251 3 view .LVU36 + 315 0002 0248 ldr r0, .L22 + 316 0004 FFF7FEFF bl HAL_UART_IRQHandler + 317 .LVL3: + 252:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN USART1_IRQn 1 */ + 253:Core/Src/stm32h7xx_it.c **** + 254:Core/Src/stm32h7xx_it.c **** /* USER CODE END USART1_IRQn 1 */ + 255:Core/Src/stm32h7xx_it.c **** } + 318 .loc 1 255 1 is_stmt 0 view .LVU37 + 319 0008 08BD pop {r3, pc} + 320 .L23: + 321 000a 00BF .align 2 + 322 .L22: + 323 000c 00000000 .word huart1 + 324 .cfi_endproc + 325 .LFE153: + 327 .section .text.FPU_IRQHandler,"ax",%progbits + 328 .align 1 + 329 .global FPU_IRQHandler + 330 .syntax unified + 331 .thumb + 332 .thumb_func + 333 .fpu fpv5-d16 + 335 FPU_IRQHandler: + 336 .LFB154: + 256:Core/Src/stm32h7xx_it.c **** + 257:Core/Src/stm32h7xx_it.c **** /** + ARM GAS /tmp/ccHBkk1J.s page 11 + + + 258:Core/Src/stm32h7xx_it.c **** * @brief This function handles FPU global interrupt. + 259:Core/Src/stm32h7xx_it.c **** */ + 260:Core/Src/stm32h7xx_it.c **** void FPU_IRQHandler(void) + 261:Core/Src/stm32h7xx_it.c **** { + 337 .loc 1 261 1 is_stmt 1 view -0 + 338 .cfi_startproc + 339 @ args = 0, pretend = 0, frame = 0 + 340 @ frame_needed = 0, uses_anonymous_args = 0 + 341 @ link register save eliminated. + 262:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN FPU_IRQn 0 */ + 263:Core/Src/stm32h7xx_it.c **** + 264:Core/Src/stm32h7xx_it.c **** /* USER CODE END FPU_IRQn 0 */ + 265:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN FPU_IRQn 1 */ + 266:Core/Src/stm32h7xx_it.c **** + 267:Core/Src/stm32h7xx_it.c **** /* USER CODE END FPU_IRQn 1 */ + 268:Core/Src/stm32h7xx_it.c **** } + 342 .loc 1 268 1 view .LVU39 + 343 0000 7047 bx lr + 344 .cfi_endproc + 345 .LFE154: + 347 .section .text.QUADSPI_IRQHandler,"ax",%progbits + 348 .align 1 + 349 .global QUADSPI_IRQHandler + 350 .syntax unified + 351 .thumb + 352 .thumb_func + 353 .fpu fpv5-d16 + 355 QUADSPI_IRQHandler: + 356 .LFB155: + 269:Core/Src/stm32h7xx_it.c **** + 270:Core/Src/stm32h7xx_it.c **** /** + 271:Core/Src/stm32h7xx_it.c **** * @brief This function handles QUADSPI global interrupt. + 272:Core/Src/stm32h7xx_it.c **** */ + 273:Core/Src/stm32h7xx_it.c **** void QUADSPI_IRQHandler(void) + 274:Core/Src/stm32h7xx_it.c **** { + 357 .loc 1 274 1 view -0 + 358 .cfi_startproc + 359 @ args = 0, pretend = 0, frame = 0 + 360 @ frame_needed = 0, uses_anonymous_args = 0 + 361 0000 08B5 push {r3, lr} + 362 .LCFI4: + 363 .cfi_def_cfa_offset 8 + 364 .cfi_offset 3, -8 + 365 .cfi_offset 14, -4 + 275:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN QUADSPI_IRQn 0 */ + 276:Core/Src/stm32h7xx_it.c **** + 277:Core/Src/stm32h7xx_it.c **** /* USER CODE END QUADSPI_IRQn 0 */ + 278:Core/Src/stm32h7xx_it.c **** HAL_QSPI_IRQHandler(&hqspi); + 366 .loc 1 278 3 view .LVU41 + 367 0002 0248 ldr r0, .L27 + 368 0004 FFF7FEFF bl HAL_QSPI_IRQHandler + 369 .LVL4: + 279:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN QUADSPI_IRQn 1 */ + 280:Core/Src/stm32h7xx_it.c **** + 281:Core/Src/stm32h7xx_it.c **** /* USER CODE END QUADSPI_IRQn 1 */ + 282:Core/Src/stm32h7xx_it.c **** } + 370 .loc 1 282 1 is_stmt 0 view .LVU42 + ARM GAS /tmp/ccHBkk1J.s page 12 + + + 371 0008 08BD pop {r3, pc} + 372 .L28: + 373 000a 00BF .align 2 + 374 .L27: + 375 000c 00000000 .word hqspi + 376 .cfi_endproc + 377 .LFE155: + 379 .section .text.OTG_FS_EP1_OUT_IRQHandler,"ax",%progbits + 380 .align 1 + 381 .global OTG_FS_EP1_OUT_IRQHandler + 382 .syntax unified + 383 .thumb + 384 .thumb_func + 385 .fpu fpv5-d16 + 387 OTG_FS_EP1_OUT_IRQHandler: + 388 .LFB156: + 283:Core/Src/stm32h7xx_it.c **** + 284:Core/Src/stm32h7xx_it.c **** /** + 285:Core/Src/stm32h7xx_it.c **** * @brief This function handles USB On The Go FS End Point 1 Out global interrupt. + 286:Core/Src/stm32h7xx_it.c **** */ + 287:Core/Src/stm32h7xx_it.c **** void OTG_FS_EP1_OUT_IRQHandler(void) + 288:Core/Src/stm32h7xx_it.c **** { + 389 .loc 1 288 1 is_stmt 1 view -0 + 390 .cfi_startproc + 391 @ args = 0, pretend = 0, frame = 0 + 392 @ frame_needed = 0, uses_anonymous_args = 0 + 393 0000 08B5 push {r3, lr} + 394 .LCFI5: + 395 .cfi_def_cfa_offset 8 + 396 .cfi_offset 3, -8 + 397 .cfi_offset 14, -4 + 289:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN OTG_FS_EP1_OUT_IRQn 0 */ + 290:Core/Src/stm32h7xx_it.c **** + 291:Core/Src/stm32h7xx_it.c **** /* USER CODE END OTG_FS_EP1_OUT_IRQn 0 */ + 292:Core/Src/stm32h7xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + 398 .loc 1 292 3 view .LVU44 + 399 0002 0248 ldr r0, .L31 + 400 0004 FFF7FEFF bl HAL_PCD_IRQHandler + 401 .LVL5: + 293:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN OTG_FS_EP1_OUT_IRQn 1 */ + 294:Core/Src/stm32h7xx_it.c **** + 295:Core/Src/stm32h7xx_it.c **** /* USER CODE END OTG_FS_EP1_OUT_IRQn 1 */ + 296:Core/Src/stm32h7xx_it.c **** } + 402 .loc 1 296 1 is_stmt 0 view .LVU45 + 403 0008 08BD pop {r3, pc} + 404 .L32: + 405 000a 00BF .align 2 + 406 .L31: + 407 000c 00000000 .word hpcd_USB_OTG_FS + 408 .cfi_endproc + 409 .LFE156: + 411 .section .text.OTG_FS_EP1_IN_IRQHandler,"ax",%progbits + 412 .align 1 + 413 .global OTG_FS_EP1_IN_IRQHandler + 414 .syntax unified + 415 .thumb + 416 .thumb_func + ARM GAS /tmp/ccHBkk1J.s page 13 + + + 417 .fpu fpv5-d16 + 419 OTG_FS_EP1_IN_IRQHandler: + 420 .LFB157: + 297:Core/Src/stm32h7xx_it.c **** + 298:Core/Src/stm32h7xx_it.c **** /** + 299:Core/Src/stm32h7xx_it.c **** * @brief This function handles USB On The Go FS End Point 1 In global interrupt. + 300:Core/Src/stm32h7xx_it.c **** */ + 301:Core/Src/stm32h7xx_it.c **** void OTG_FS_EP1_IN_IRQHandler(void) + 302:Core/Src/stm32h7xx_it.c **** { + 421 .loc 1 302 1 is_stmt 1 view -0 + 422 .cfi_startproc + 423 @ args = 0, pretend = 0, frame = 0 + 424 @ frame_needed = 0, uses_anonymous_args = 0 + 425 0000 08B5 push {r3, lr} + 426 .LCFI6: + 427 .cfi_def_cfa_offset 8 + 428 .cfi_offset 3, -8 + 429 .cfi_offset 14, -4 + 303:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN OTG_FS_EP1_IN_IRQn 0 */ + 304:Core/Src/stm32h7xx_it.c **** + 305:Core/Src/stm32h7xx_it.c **** /* USER CODE END OTG_FS_EP1_IN_IRQn 0 */ + 306:Core/Src/stm32h7xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + 430 .loc 1 306 3 view .LVU47 + 431 0002 0248 ldr r0, .L35 + 432 0004 FFF7FEFF bl HAL_PCD_IRQHandler + 433 .LVL6: + 307:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN OTG_FS_EP1_IN_IRQn 1 */ + 308:Core/Src/stm32h7xx_it.c **** + 309:Core/Src/stm32h7xx_it.c **** /* USER CODE END OTG_FS_EP1_IN_IRQn 1 */ + 310:Core/Src/stm32h7xx_it.c **** } + 434 .loc 1 310 1 is_stmt 0 view .LVU48 + 435 0008 08BD pop {r3, pc} + 436 .L36: + 437 000a 00BF .align 2 + 438 .L35: + 439 000c 00000000 .word hpcd_USB_OTG_FS + 440 .cfi_endproc + 441 .LFE157: + 443 .section .text.OTG_FS_IRQHandler,"ax",%progbits + 444 .align 1 + 445 .global OTG_FS_IRQHandler + 446 .syntax unified + 447 .thumb + 448 .thumb_func + 449 .fpu fpv5-d16 + 451 OTG_FS_IRQHandler: + 452 .LFB158: + 311:Core/Src/stm32h7xx_it.c **** + 312:Core/Src/stm32h7xx_it.c **** /** + 313:Core/Src/stm32h7xx_it.c **** * @brief This function handles USB On The Go FS global interrupt. + 314:Core/Src/stm32h7xx_it.c **** */ + 315:Core/Src/stm32h7xx_it.c **** void OTG_FS_IRQHandler(void) + 316:Core/Src/stm32h7xx_it.c **** { + 453 .loc 1 316 1 is_stmt 1 view -0 + 454 .cfi_startproc + 455 @ args = 0, pretend = 0, frame = 0 + 456 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccHBkk1J.s page 14 + + + 457 0000 08B5 push {r3, lr} + 458 .LCFI7: + 459 .cfi_def_cfa_offset 8 + 460 .cfi_offset 3, -8 + 461 .cfi_offset 14, -4 + 317:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 0 */ + 318:Core/Src/stm32h7xx_it.c **** + 319:Core/Src/stm32h7xx_it.c **** /* USER CODE END OTG_FS_IRQn 0 */ + 320:Core/Src/stm32h7xx_it.c **** HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + 462 .loc 1 320 3 view .LVU50 + 463 0002 0248 ldr r0, .L39 + 464 0004 FFF7FEFF bl HAL_PCD_IRQHandler + 465 .LVL7: + 321:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN OTG_FS_IRQn 1 */ + 322:Core/Src/stm32h7xx_it.c **** + 323:Core/Src/stm32h7xx_it.c **** /* USER CODE END OTG_FS_IRQn 1 */ + 324:Core/Src/stm32h7xx_it.c **** } + 466 .loc 1 324 1 is_stmt 0 view .LVU51 + 467 0008 08BD pop {r3, pc} + 468 .L40: + 469 000a 00BF .align 2 + 470 .L39: + 471 000c 00000000 .word hpcd_USB_OTG_FS + 472 .cfi_endproc + 473 .LFE158: + 475 .section .text.HSEM1_IRQHandler,"ax",%progbits + 476 .align 1 + 477 .global HSEM1_IRQHandler + 478 .syntax unified + 479 .thumb + 480 .thumb_func + 481 .fpu fpv5-d16 + 483 HSEM1_IRQHandler: + 484 .LFB159: + 325:Core/Src/stm32h7xx_it.c **** + 326:Core/Src/stm32h7xx_it.c **** /** + 327:Core/Src/stm32h7xx_it.c **** * @brief This function handles HSEM1 global interrupt. + 328:Core/Src/stm32h7xx_it.c **** */ + 329:Core/Src/stm32h7xx_it.c **** void HSEM1_IRQHandler(void) + 330:Core/Src/stm32h7xx_it.c **** { + 485 .loc 1 330 1 is_stmt 1 view -0 + 486 .cfi_startproc + 487 @ args = 0, pretend = 0, frame = 0 + 488 @ frame_needed = 0, uses_anonymous_args = 0 + 489 0000 08B5 push {r3, lr} + 490 .LCFI8: + 491 .cfi_def_cfa_offset 8 + 492 .cfi_offset 3, -8 + 493 .cfi_offset 14, -4 + 331:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN HSEM1_IRQn 0 */ + 332:Core/Src/stm32h7xx_it.c **** + 333:Core/Src/stm32h7xx_it.c **** /* USER CODE END HSEM1_IRQn 0 */ + 334:Core/Src/stm32h7xx_it.c **** HAL_HSEM_IRQHandler(); + 494 .loc 1 334 3 view .LVU53 + 495 0002 FFF7FEFF bl HAL_HSEM_IRQHandler + 496 .LVL8: + 335:Core/Src/stm32h7xx_it.c **** /* USER CODE BEGIN HSEM1_IRQn 1 */ + ARM GAS /tmp/ccHBkk1J.s page 15 + + + 336:Core/Src/stm32h7xx_it.c **** + 337:Core/Src/stm32h7xx_it.c **** /* USER CODE END HSEM1_IRQn 1 */ + 338:Core/Src/stm32h7xx_it.c **** } + 497 .loc 1 338 1 is_stmt 0 view .LVU54 + 498 0006 08BD pop {r3, pc} + 499 .cfi_endproc + 500 .LFE159: + 502 .text + 503 .Letext0: + 504 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 505 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 506 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 507 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 508 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" + 509 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 510 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" + 511 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h" + 512 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h" + 513 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h" + 514 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h" + 515 .file 13 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h" + 516 .file 14 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h" + 517 .file 15 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/ccHBkk1J.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_it.c + /tmp/ccHBkk1J.s:17 .text.NMI_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:25 .text.NMI_Handler:0000000000000000 NMI_Handler + /tmp/ccHBkk1J.s:39 .text.HardFault_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:46 .text.HardFault_Handler:0000000000000000 HardFault_Handler + /tmp/ccHBkk1J.s:63 .text.MemManage_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:70 .text.MemManage_Handler:0000000000000000 MemManage_Handler + /tmp/ccHBkk1J.s:87 .text.BusFault_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:94 .text.BusFault_Handler:0000000000000000 BusFault_Handler + /tmp/ccHBkk1J.s:111 .text.UsageFault_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:118 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler + /tmp/ccHBkk1J.s:135 .text.SVC_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:142 .text.SVC_Handler:0000000000000000 SVC_Handler + /tmp/ccHBkk1J.s:155 .text.DebugMon_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:162 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler + /tmp/ccHBkk1J.s:175 .text.PendSV_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:182 .text.PendSV_Handler:0000000000000000 PendSV_Handler + /tmp/ccHBkk1J.s:195 .text.SysTick_Handler:0000000000000000 $t + /tmp/ccHBkk1J.s:202 .text.SysTick_Handler:0000000000000000 SysTick_Handler + /tmp/ccHBkk1J.s:222 .text.PVD_AVD_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:229 .text.PVD_AVD_IRQHandler:0000000000000000 PVD_AVD_IRQHandler + /tmp/ccHBkk1J.s:249 .text.FLASH_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:256 .text.FLASH_IRQHandler:0000000000000000 FLASH_IRQHandler + /tmp/ccHBkk1J.s:276 .text.RCC_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:283 .text.RCC_IRQHandler:0000000000000000 RCC_IRQHandler + /tmp/ccHBkk1J.s:296 .text.USART1_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:303 .text.USART1_IRQHandler:0000000000000000 USART1_IRQHandler + /tmp/ccHBkk1J.s:323 .text.USART1_IRQHandler:000000000000000c $d + /tmp/ccHBkk1J.s:328 .text.FPU_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:335 .text.FPU_IRQHandler:0000000000000000 FPU_IRQHandler + /tmp/ccHBkk1J.s:348 .text.QUADSPI_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:355 .text.QUADSPI_IRQHandler:0000000000000000 QUADSPI_IRQHandler + /tmp/ccHBkk1J.s:375 .text.QUADSPI_IRQHandler:000000000000000c $d + /tmp/ccHBkk1J.s:380 .text.OTG_FS_EP1_OUT_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:387 .text.OTG_FS_EP1_OUT_IRQHandler:0000000000000000 OTG_FS_EP1_OUT_IRQHandler + /tmp/ccHBkk1J.s:407 .text.OTG_FS_EP1_OUT_IRQHandler:000000000000000c $d + /tmp/ccHBkk1J.s:412 .text.OTG_FS_EP1_IN_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:419 .text.OTG_FS_EP1_IN_IRQHandler:0000000000000000 OTG_FS_EP1_IN_IRQHandler + /tmp/ccHBkk1J.s:439 .text.OTG_FS_EP1_IN_IRQHandler:000000000000000c $d + /tmp/ccHBkk1J.s:444 .text.OTG_FS_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:451 .text.OTG_FS_IRQHandler:0000000000000000 OTG_FS_IRQHandler + /tmp/ccHBkk1J.s:471 .text.OTG_FS_IRQHandler:000000000000000c $d + /tmp/ccHBkk1J.s:476 .text.HSEM1_IRQHandler:0000000000000000 $t + /tmp/ccHBkk1J.s:483 .text.HSEM1_IRQHandler:0000000000000000 HSEM1_IRQHandler + +UNDEFINED SYMBOLS +HAL_IncTick +HAL_PWREx_PVD_AVD_IRQHandler +HAL_FLASH_IRQHandler +HAL_UART_IRQHandler +huart1 +HAL_QSPI_IRQHandler +hqspi +HAL_PCD_IRQHandler +hpcd_USB_OTG_FS +HAL_HSEM_IRQHandler + ARM GAS /tmp/ccHBkk1J.s page 17 + + diff --git a/build/stm32h7xx_it.o b/build/stm32h7xx_it.o new file mode 100644 index 0000000..19b10bc Binary files /dev/null and b/build/stm32h7xx_it.o differ diff --git a/build/stm32h7xx_ll_usb.d b/build/stm32h7xx_ll_usb.d new file mode 100644 index 0000000..a65abbc --- /dev/null +++ b/build/stm32h7xx_ll_usb.d @@ -0,0 +1,68 @@ +build/stm32h7xx_ll_usb.o: \ + Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/stm32h7xx_ll_usb.lst b/build/stm32h7xx_ll_usb.lst new file mode 100644 index 0000000..cc31733 --- /dev/null +++ b/build/stm32h7xx_ll_usb.lst @@ -0,0 +1,8637 @@ +ARM GAS /tmp/cc9mtr28.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "stm32h7xx_ll_usb.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.USB_CoreReset,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 USB_CoreReset: + 25 .LVL0: + 26 .LFB174: + 27 .file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c" + 1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ****************************************************************************** + 3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @file stm32h7xx_ll_usb.c + 4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @author MCD Application Team + 5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB Low Layer HAL module driver. + 6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + 7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This file provides firmware functions to manage the following + 8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * functionalities of the USB Peripheral Controller: + 9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + Initialization/de-initialization functions + 10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + I/O operation functions + 11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + Peripheral Control functions + 12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + Peripheral State functions + 13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + 14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** @verbatim + 15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ============================================================================== + 16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ##### How to use this driver ##### + 17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ============================================================================== + 18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** [..] + 19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + 20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + 22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + 24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** @endverbatim + 26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ****************************************************************************** + 27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @attention + 28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + 29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** *

© Copyright (c) 2017 STMicroelectronics. + 30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * All rights reserved.

+ 31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + ARM GAS /tmp/cc9mtr28.s page 2 + + + 32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This software component is licensed by ST under BSD 3-Clause license, + 33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * the "License"; You may not use this file except in compliance with the + 34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * License. You may obtain a copy of the License at: + 35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * opensource.org/licenses/BSD-3-Clause + 36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + 37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ****************************************************************************** + 38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Includes ------------------------------------------------------------------*/ + 41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** #include "stm32h7xx_hal.h" + 42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** @addtogroup STM32H7xx_LL_USB_DRIVER + 44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @{ + 45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) + 48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Private typedef -----------------------------------------------------------*/ + 50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Private define ------------------------------------------------------------*/ + 51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Private macro -------------------------------------------------------------*/ + 52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Private variables ---------------------------------------------------------*/ + 53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Private function prototypes -----------------------------------------------*/ + 54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Private functions ---------------------------------------------------------*/ + 55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** #if defined (USB_OTG_FS) || defined (USB_OTG_HS) + 56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + 57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Exported functions --------------------------------------------------------*/ + 59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + 60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @{ + 61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + 64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Initialization and Configuration functions + 65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * + 66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** @verbatim + 67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** =============================================================================== + 68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ##### Initialization/de-initialization functions ##### + 69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** =============================================================================== + 70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** @endverbatim + 72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @{ + 73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Initializes the USB Core + 77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx USB Instance + 78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + 79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * the configuration information for the specified USBx peripheral. + 80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret; + 85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.phy_itface == USB_OTG_ULPI_PHY) + 87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + ARM GAS /tmp/cc9mtr28.s page 3 + + + 89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Init The ULPI Interface */ + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + 92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Select vbus source */ + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.use_external_vbus == 1U) + 96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + 98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Reset after a PHY select */ + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = USB_CoreReset(USBx); + 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else /* FS interface (embedded Phy) */ + 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Select FS Embedded PHY */ + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Reset after a PHY select and set Host mode */ + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = USB_CoreReset(USBx); + 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.battery_charging_enable == 0U) + 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Activate the USB Transceiver */ + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Deactivate the USB Transceiver */ + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.dma_enable == 1U) + 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ret; + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Set the USB turnaround time + 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx USB Instance + 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param hclk: AHB clock frequency + 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval USB turnaround time In PHY Clocks number + 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t hclk, uint8_t speed) + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t UsbTrd; + 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* The USBTRD is configured according to the tables below, depending on AHB frequency + 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** used by application. In the low AHB frequency range it is used to stretch enough the USB response + 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + ARM GAS /tmp/cc9mtr28.s page 4 + + + 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** latency to the Data FIFO */ + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (speed == USBD_FS_SPEED) + 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((hclk >= 14200000U) && (hclk < 15000000U)) + 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 14.2-15 MHz */ + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0xFU; + 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 15000000U) && (hclk < 16000000U)) + 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 15-16 MHz */ + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0xEU; + 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 16000000U) && (hclk < 17200000U)) + 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 16-17.2 MHz */ + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0xDU; + 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 17200000U) && (hclk < 18500000U)) + 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 17.2-18.5 MHz */ + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0xCU; + 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 18500000U) && (hclk < 20000000U)) + 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 18.5-20 MHz */ + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0xBU; + 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 20000000U) && (hclk < 21800000U)) + 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 20-21.8 MHz */ + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0xAU; + 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 21800000U) && (hclk < 24000000U)) + 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 21.8-24 MHz */ + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0x9U; + 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 24000000U) && (hclk < 27700000U)) + 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 24-27.7 MHz */ + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0x8U; + 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((hclk >= 27700000U) && (hclk < 32000000U)) + 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 27.7-32 MHz */ + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0x7U; + 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else /* if(hclk >= 32000000) */ + 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* hclk Clock Range between 32-200 MHz */ + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = 0x6U; + 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if (speed == USBD_HS_SPEED) + 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = USBD_HS_TRDT_VALUE; + ARM GAS /tmp/cc9mtr28.s page 5 + + + 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** UsbTrd = USBD_DEFAULT_TRDT_VALUE; + 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_EnableGlobalInt + 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * Enables the controller's Global Int in the AHB Config reg + 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_DisableGlobalInt + 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * Disable the controller's Global Int in the AHB Config reg + 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_SetCurrentMode : Set functional mode + 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param mode current core mode + 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_DEVICE_MODE: Peripheral mode + 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_HOST_MODE: Host mode + 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_DRD_MODE: Dual Role Device mode + 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (mode == USB_HOST_MODE) + 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if (mode == USB_DEVICE_MODE) + 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + ARM GAS /tmp/cc9mtr28.s page 6 + + + 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_ERROR; + 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(50U); + 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_DevInit : Initializes the USB_OTG controller registers + 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * for device mode + 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * the configuration information for the specified USBx peripheral. + 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret = HAL_OK; + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < 15U; i++) + 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF[i] = 0U; + 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* VBUS Sensing setup */ + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.vbus_sensing_enable == 0U) + 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Deactivate VBUS Sensing B */ + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* B-peripheral session valid override enable */ + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable HW VBUS sensing */ + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Restart the Phy Clock */ + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_PCGCCTL = 0U; + 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Device mode configuration */ + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.phy_itface == USB_OTG_ULPI_PHY) + 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.speed == USBD_HS_SPEED) + 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 7 + + + 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set Core speed to High speed mode */ + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set Core speed to Full speed mode */ + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set Core speed to Full speed mode */ + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Flush the FIFOs */ + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = HAL_ERROR; + 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (USB_FlushRxFifo(USBx) != HAL_OK) + 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = HAL_ERROR; + 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear all pending Device Interrupts */ + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DIEPMSK = 0U; + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK = 0U; + 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < cfg.dev_endpoints; i++) + 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (i == 0U) + 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPCTL = 0U; + 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPTSIZ = 0U; + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPINT = 0xFB7FU; + 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < cfg.dev_endpoints; i++) + 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 8 + + + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (i == 0U) + 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPCTL = 0U; + 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPTSIZ = 0U; + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Disable all interrupts. */ + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK = 0U; + 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear any pending interrupts */ + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTSTS = 0xBFFFFFFFU; + 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable the common interrupts */ + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.dma_enable == 0U) + 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable interrupts matching to the Device mode ONLY */ + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.Sof_enable != 0U) + 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.vbus_sensing_enable == 1U) + 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ret; + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param num FIFO number + 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 1 to 15 + 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** 15 means Flush all Tx FIFOs + ARM GAS /tmp/cc9mtr28.s page 9 + + + 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0U; + 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 200000U) + 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_TIMEOUT; + 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_FlushRxFifo : Flush Rx FIFO + 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0; + 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 200000U) + 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_TIMEOUT; + 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * depending the PHY type and the enumeration speed of the device. + 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param speed device speed + 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_OTG_SPEED_HIGH: High speed mode + 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_OTG_SPEED_FULL: Full speed mode + 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval Hal status + 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + ARM GAS /tmp/cc9mtr28.s page 10 + + + 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCFG |= speed; + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_GetDevSpeed Return the Dev Speed + 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval speed device speed + 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg PCD_SPEED_HIGH: High speed mode + 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg PCD_SPEED_FULL: Full speed mode + 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t speed; + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** speed = USBD_HS_SPEED; + 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** speed = USBD_FS_SPEED; + 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** speed = 0xFU; + 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return speed; + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Activate and configure an endpoint + 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_USBAEP; + ARM GAS /tmp/cc9mtr28.s page 11 + + + 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << + 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_USBAEP; + 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Activate and configure a dedicated endpoint + 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Read DEPCTLn register */ + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_USBAEP; + 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_USBAEP; + 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << + 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + ARM GAS /tmp/cc9mtr28.s page 12 + + + 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief De-activate and de-initialize an endpoint + 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Read DEPCTLn register */ + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_MPSIZ | + 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_TXFNUM | + 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_EPTYP); + 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_MPSIZ | + 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_EPTYP); + 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief De-activate and de-initialize a dedicated endpoint + 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *e + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 13 + + + 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Read DEPCTLn register */ + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_EPStartXfer : setup and starts a transfer over an EP + 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dma USB dma enabled or disabled + 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : DMA feature not used + 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : DMA feature used + 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t pktcnt; + 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* IN endpoint */ + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Zero Length Packet? */ + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len == 0U) + 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Program the transfer size and packet count + 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * as follows: xfersize = N * maxpacket + + ARM GAS /tmp/cc9mtr28.s page 14 + + + 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * short_packet pktcnt = N + (short_packet + 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * exist ? 1 : 0) + 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->type == EP_TYPE_ISOC) + 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 1U) + 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((uint32_t)ep->dma_addr != 0U) + 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->type == EP_TYPE_ISOC) + 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable, IN data in FIFO */ + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable, IN data in FIFO */ + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->type != EP_TYPE_ISOC) + 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable the Tx FIFO Empty Interrupt for this EP */ + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len > 0U) + 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + ARM GAS /tmp/cc9mtr28.s page 15 + + + 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else /* OUT endpoint */ + 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Program the transfer size and packet count as follows: + 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * pktcnt = N + 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * xfersize = N * maxpacket + 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len == 0U) + 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 1U) + 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((uint32_t)ep->xfer_buff != 0U) + 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->type == EP_TYPE_ISOC) + 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable */ + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 + ARM GAS /tmp/cc9mtr28.s page 16 + + + 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dma USB dma enabled or disabled + 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : DMA feature not used + 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : DMA feature used + 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* IN endpoint */ + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Zero Length Packet? */ + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len == 0U) + 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Program the transfer size and packet count + 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * as follows: xfersize = N * maxpacket + + 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * short_packet pktcnt = N + (short_packet + 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * exist ? 1 : 0) + 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len > ep->maxpacket) + 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ep->xfer_len = ep->maxpacket; + 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 1U) + 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((uint32_t)ep->dma_addr != 0U) + 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable, IN data in FIFO */ + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else + 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable, IN data in FIFO */ + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable the Tx FIFO Empty Interrupt for this EP */ + ARM GAS /tmp/cc9mtr28.s page 17 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len > 0U) + 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else /* OUT endpoint */ + 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Program the transfer size and packet count as follows: + 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * pktcnt = N + 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * xfersize = N * maxpacket + 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->xfer_len > 0U) + 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ep->xfer_len = ep->maxpacket; + 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 1U) + 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((uint32_t)ep->xfer_buff != 0U) + 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable */ + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * with the EP/channel + 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param src pointer to source buffer + 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ch_ep_num endpoint or host channel number + 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param len Number of bytes to write + 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dma USB dma enabled or disabled + 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : DMA feature not used + 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : DMA feature used + 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uin + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t *pSrc = (uint32_t *)src; + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count32b, i; + 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 18 + + + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 0U) + 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** count32b = ((uint32_t)len + 3U) / 4U; + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < count32b; i++) + 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pSrc++; + 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_ReadPacket : read a packet from the RX FIFO + 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dest source pointer + 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param len Number of bytes to read + 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval pointer to destination buffer + 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t *pDest = (uint32_t *)dest; + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count32b = ((uint32_t)len + 3U) / 4U; + 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < count32b; i++) + 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pDest++; + 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((void *)pDest); + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_EPSetStall : set a stall condition over an EP + 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure + 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status + 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) + 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 19 + + +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) +1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); +1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; +1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_EPClearStall : Clear a stall condition over an EP +1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep pointer to endpoint structure +1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; +1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep->is_in == 1U) +1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) +1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ +1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) +1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ +1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_StopDevice : Stop the usb device mode +1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret; +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; +1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear Pending interrupt */ +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < 15U; i++) +1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPINT = 0xFB7FU; +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; +1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + ARM GAS /tmp/cc9mtr28.s page 20 + + +1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear interrupt masks */ +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DIEPMSK = 0U; +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK = 0U; +1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Flush the FIFO */ +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = USB_FlushRxFifo(USBx); +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) +1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ret; +1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = USB_FlushTxFifo(USBx, 0x10U); +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) +1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ret; +1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ret; +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_SetDevAddress : Stop the usb device mode +1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param address new device address to be assigned +1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 0 to 255 +1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; +1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down +1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(3U); +1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down +1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device + ARM GAS /tmp/cc9mtr28.s page 21 + + +1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(3U); +1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_ReadInterrupts: return the global USB interrupt status +1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; +1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx->GINTSTS; +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx->GINTMSK; +1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return tmpreg; +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status +1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; +1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_DEVICE->DAINT; +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; +1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((tmpreg & 0xffff0000U) >> 16); +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status +1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; +1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_DEVICE->DAINT; +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; +1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((tmpreg & 0xFFFFU)); + ARM GAS /tmp/cc9mtr28.s page 22 + + +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Returns Device OUT EP Interrupt register +1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param epnum endpoint number +1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 0 to 15 +1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval Device OUT EP Interrupt register +1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; +1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DOEPMSK; +1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return tmpreg; +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Returns Device IN EP Interrupt register +1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param epnum endpoint number +1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 0 to 15 +1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval Device IN EP Interrupt register +1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg, msk, emp; +1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** msk = USBx_DEVICE->DIEPMSK; +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** emp = USBx_DEVICE->DIEPEMPMSK; +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; +1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return tmpreg; +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_ClearInterrupts: clear a USB interrupt +1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param interrupt interrupt flag +1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval None +1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTSTS |= interrupt; +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Returns USB core mode +1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval return core mode : Host or Device +1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : Host + ARM GAS /tmp/cc9mtr28.s page 23 + + +1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : Device +1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((USBx->GINTSTS) & 0x1U); +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Activate EP0 for Setup transactions +1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set the MPS of the IN EP0 to 64 bytes */ +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; +1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; +1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Prepare the EP0 to start the first control setup +1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dma USB dma enabled or disabled +1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : DMA feature not used +1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : DMA feature used +1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param psetup pointer to setup packet +1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); +1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (gSNPSiD > USB_OTG_CORE_ID_300A) +1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) +1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ = 0U; +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; +1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 1U) +1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; +1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable */ +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + ARM GAS /tmp/cc9mtr28.s page 24 + + +1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Reset the USB Core (needed after USB clock settings change) +1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 28 .loc 1 1297 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0U; + 33 .loc 1 1298 3 view .LVU1 + 34 .loc 1 1298 12 is_stmt 0 view .LVU2 + 35 0000 0023 movs r3, #0 + 36 .LVL1: + 37 .L3: +1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Wait for AHB master IDLE state. */ +1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 38 .loc 1 1301 3 is_stmt 1 view .LVU3 +1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 200000U) + 39 .loc 1 1303 5 view .LVU4 + 40 .loc 1 1303 8 is_stmt 0 view .LVU5 + 41 0002 0133 adds r3, r3, #1 + 42 .LVL2: + 43 .loc 1 1303 8 view .LVU6 + 44 0004 0C4A ldr r2, .L7 + 45 0006 9342 cmp r3, r2 + 46 0008 11D8 bhi .L5 +1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_TIMEOUT; +1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + 47 .loc 1 1308 9 is_stmt 1 view .LVU7 + 48 .loc 1 1308 15 is_stmt 0 view .LVU8 + 49 000a 0269 ldr r2, [r0, #16] + 50 .loc 1 1308 3 view .LVU9 + 51 000c 002A cmp r2, #0 + 52 000e F8DA bge .L3 +1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Core Soft Reset */ +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** count = 0U; + 53 .loc 1 1311 3 is_stmt 1 view .LVU10 + 54 .LVL3: +1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + 55 .loc 1 1312 3 view .LVU11 + 56 .loc 1 1312 17 is_stmt 0 view .LVU12 + 57 0010 0369 ldr r3, [r0, #16] + ARM GAS /tmp/cc9mtr28.s page 25 + + + 58 0012 43F00103 orr r3, r3, #1 + 59 0016 0361 str r3, [r0, #16] +1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + 60 .loc 1 1311 9 view .LVU13 + 61 0018 0023 movs r3, #0 + 62 .LVL4: + 63 .L4: +1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 64 .loc 1 1314 3 is_stmt 1 view .LVU14 +1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 200000U) + 65 .loc 1 1316 5 view .LVU15 + 66 .loc 1 1316 8 is_stmt 0 view .LVU16 + 67 001a 0133 adds r3, r3, #1 + 68 .LVL5: + 69 .loc 1 1316 8 view .LVU17 + 70 001c 064A ldr r2, .L7 + 71 001e 9342 cmp r3, r2 + 72 0020 07D8 bhi .L6 +1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_TIMEOUT; +1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + 73 .loc 1 1321 9 is_stmt 1 view .LVU18 + 74 .loc 1 1321 15 is_stmt 0 view .LVU19 + 75 0022 0269 ldr r2, [r0, #16] + 76 .loc 1 1321 3 view .LVU20 + 77 0024 12F0010F tst r2, #1 + 78 0028 F7D1 bne .L4 +1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 79 .loc 1 1323 10 view .LVU21 + 80 002a 0020 movs r0, #0 + 81 .LVL6: + 82 .loc 1 1323 10 view .LVU22 + 83 002c 7047 bx lr + 84 .LVL7: + 85 .L5: +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 86 .loc 1 1305 14 view .LVU23 + 87 002e 0320 movs r0, #3 + 88 .LVL8: +1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 89 .loc 1 1305 14 view .LVU24 + 90 0030 7047 bx lr + 91 .LVL9: + 92 .L6: +1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 93 .loc 1 1318 14 view .LVU25 + 94 0032 0320 movs r0, #3 + 95 .LVL10: +1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 96 .loc 1 1324 1 view .LVU26 + 97 0034 7047 bx lr + 98 .L8: + ARM GAS /tmp/cc9mtr28.s page 26 + + + 99 0036 00BF .align 2 + 100 .L7: + 101 0038 400D0300 .word 200000 + 102 .cfi_endproc + 103 .LFE174: + 105 .section .text.USB_CoreInit,"ax",%progbits + 106 .align 1 + 107 .global USB_CoreInit + 108 .syntax unified + 109 .thumb + 110 .thumb_func + 111 .fpu fpv5-d16 + 113 USB_CoreInit: + 114 .LVL11: + 115 .LFB141: + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret; + 116 .loc 1 83 1 is_stmt 1 view -0 + 117 .cfi_startproc + 118 @ args = 56, pretend = 16, frame = 0 + 119 @ frame_needed = 0, uses_anonymous_args = 0 + 83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret; + 120 .loc 1 83 1 is_stmt 0 view .LVU28 + 121 0000 84B0 sub sp, sp, #16 + 122 .LCFI0: + 123 .cfi_def_cfa_offset 16 + 124 0002 10B5 push {r4, lr} + 125 .LCFI1: + 126 .cfi_def_cfa_offset 24 + 127 .cfi_offset 4, -24 + 128 .cfi_offset 14, -20 + 129 0004 0446 mov r4, r0 + 130 0006 03A8 add r0, sp, #12 + 131 0008 80E80E00 stm r0, {r1, r2, r3} + 84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 132 .loc 1 84 3 is_stmt 1 view .LVU29 + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 133 .loc 1 86 3 view .LVU30 + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 134 .loc 1 86 10 is_stmt 0 view .LVU31 + 135 000c 089B ldr r3, [sp, #32] + 86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 136 .loc 1 86 6 view .LVU32 + 137 000e 012B cmp r3, #1 + 138 0010 1DD1 bne .L10 + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 139 .loc 1 88 5 is_stmt 1 view .LVU33 + 88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 140 .loc 1 88 17 is_stmt 0 view .LVU34 + 141 0012 A36B ldr r3, [r4, #56] + 142 0014 23F48033 bic r3, r3, #65536 + 143 0018 A363 str r3, [r4, #56] + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 144 .loc 1 91 5 is_stmt 1 view .LVU35 + 91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 145 .loc 1 91 19 is_stmt 0 view .LVU36 + 146 001a E268 ldr r2, [r4, #12] + 147 001c 1A4B ldr r3, .L18 + ARM GAS /tmp/cc9mtr28.s page 27 + + + 148 001e 1340 ands r3, r3, r2 + 149 0020 E360 str r3, [r4, #12] + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.use_external_vbus == 1U) + 150 .loc 1 94 5 is_stmt 1 view .LVU37 + 94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.use_external_vbus == 1U) + 151 .loc 1 94 19 is_stmt 0 view .LVU38 + 152 0022 E368 ldr r3, [r4, #12] + 153 0024 23F44013 bic r3, r3, #3145728 + 154 0028 E360 str r3, [r4, #12] + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 155 .loc 1 95 5 is_stmt 1 view .LVU39 + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 156 .loc 1 95 12 is_stmt 0 view .LVU40 + 157 002a 0F9B ldr r3, [sp, #60] + 95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 158 .loc 1 95 8 view .LVU41 + 159 002c 012B cmp r3, #1 + 160 002e 09D0 beq .L16 + 161 .L11: + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 162 .loc 1 100 5 is_stmt 1 view .LVU42 + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 163 .loc 1 100 11 is_stmt 0 view .LVU43 + 164 0030 2046 mov r0, r4 + 165 .LVL12: + 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 166 .loc 1 100 11 view .LVU44 + 167 0032 FFF7FEFF bl USB_CoreReset + 168 .LVL13: + 169 .L12: + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 170 .loc 1 122 3 is_stmt 1 view .LVU45 + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 171 .loc 1 122 10 is_stmt 0 view .LVU46 + 172 0036 069B ldr r3, [sp, #24] + 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 173 .loc 1 122 6 view .LVU47 + 174 0038 012B cmp r3, #1 + 175 003a 1BD0 beq .L17 + 176 .L14: + 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 177 .loc 1 128 3 is_stmt 1 view .LVU48 + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 178 .loc 1 129 1 is_stmt 0 view .LVU49 + 179 003c BDE81040 pop {r4, lr} + 180 .LCFI2: + 181 .cfi_remember_state + 182 .cfi_restore 14 + 183 .cfi_restore 4 + 184 .cfi_def_cfa_offset 16 + 185 .LVL14: + 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 186 .loc 1 129 1 view .LVU50 + 187 0040 04B0 add sp, sp, #16 + 188 .LCFI3: + 189 .cfi_def_cfa_offset 0 + 190 0042 7047 bx lr + ARM GAS /tmp/cc9mtr28.s page 28 + + + 191 .LVL15: + 192 .L16: + 193 .LCFI4: + 194 .cfi_restore_state + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 195 .loc 1 97 7 is_stmt 1 view .LVU51 + 97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 196 .loc 1 97 21 is_stmt 0 view .LVU52 + 197 0044 E368 ldr r3, [r4, #12] + 198 0046 43F48013 orr r3, r3, #1048576 + 199 004a E360 str r3, [r4, #12] + 200 004c F0E7 b .L11 + 201 .L10: + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 202 .loc 1 105 5 is_stmt 1 view .LVU53 + 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 203 .loc 1 105 19 is_stmt 0 view .LVU54 + 204 004e E368 ldr r3, [r4, #12] + 205 0050 43F04003 orr r3, r3, #64 + 206 0054 E360 str r3, [r4, #12] + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 207 .loc 1 108 5 is_stmt 1 view .LVU55 + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 208 .loc 1 108 11 is_stmt 0 view .LVU56 + 209 0056 2046 mov r0, r4 + 210 .LVL16: + 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 211 .loc 1 108 11 view .LVU57 + 212 0058 FFF7FEFF bl USB_CoreReset + 213 .LVL17: + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 214 .loc 1 110 5 is_stmt 1 view .LVU58 + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 215 .loc 1 110 12 is_stmt 0 view .LVU59 + 216 005c 0C9B ldr r3, [sp, #48] + 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 217 .loc 1 110 8 view .LVU60 + 218 005e 23B9 cbnz r3, .L13 + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 219 .loc 1 113 7 is_stmt 1 view .LVU61 + 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 220 .loc 1 113 19 is_stmt 0 view .LVU62 + 221 0060 A36B ldr r3, [r4, #56] + 222 0062 43F48033 orr r3, r3, #65536 + 223 0066 A363 str r3, [r4, #56] + 224 0068 E5E7 b .L12 + 225 .L13: + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 226 .loc 1 118 7 is_stmt 1 view .LVU63 + 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 227 .loc 1 118 19 is_stmt 0 view .LVU64 + 228 006a A36B ldr r3, [r4, #56] + 229 006c 23F48033 bic r3, r3, #65536 + 230 0070 A363 str r3, [r4, #56] + 231 0072 E0E7 b .L12 + 232 .L17: + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + ARM GAS /tmp/cc9mtr28.s page 29 + + + 233 .loc 1 124 5 is_stmt 1 view .LVU65 + 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + 234 .loc 1 124 19 is_stmt 0 view .LVU66 + 235 0074 A368 ldr r3, [r4, #8] + 236 0076 43F00603 orr r3, r3, #6 + 237 007a A360 str r3, [r4, #8] + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 238 .loc 1 125 5 is_stmt 1 view .LVU67 + 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 239 .loc 1 125 19 is_stmt 0 view .LVU68 + 240 007c A368 ldr r3, [r4, #8] + 241 007e 43F02003 orr r3, r3, #32 + 242 0082 A360 str r3, [r4, #8] + 243 0084 DAE7 b .L14 + 244 .L19: + 245 0086 00BF .align 2 + 246 .L18: + 247 0088 BFFFBDFF .word -4325441 + 248 .cfi_endproc + 249 .LFE141: + 251 .section .text.USB_SetTurnaroundTime,"ax",%progbits + 252 .align 1 + 253 .global USB_SetTurnaroundTime + 254 .syntax unified + 255 .thumb + 256 .thumb_func + 257 .fpu fpv5-d16 + 259 USB_SetTurnaroundTime: + 260 .LVL18: + 261 .LFB142: + 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t UsbTrd; + 262 .loc 1 140 1 is_stmt 1 view -0 + 263 .cfi_startproc + 264 @ args = 0, pretend = 0, frame = 0 + 265 @ frame_needed = 0, uses_anonymous_args = 0 + 266 @ link register save eliminated. + 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 267 .loc 1 141 3 view .LVU70 + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 268 .loc 1 147 3 view .LVU71 + 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 269 .loc 1 147 6 is_stmt 0 view .LVU72 + 270 0000 022A cmp r2, #2 + 271 0002 0AD0 beq .L32 + 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 272 .loc 1 202 12 view .LVU73 + 273 0004 0921 movs r1, #9 + 274 .LVL19: + 275 .L21: + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + 276 .loc 1 209 3 is_stmt 1 view .LVU74 + 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + 277 .loc 1 209 17 is_stmt 0 view .LVU75 + 278 0006 C268 ldr r2, [r0, #12] + 279 0008 22F47052 bic r2, r2, #15360 + 280 000c C260 str r2, [r0, #12] + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 30 + + + 281 .loc 1 210 3 is_stmt 1 view .LVU76 + 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 282 .loc 1 210 17 is_stmt 0 view .LVU77 + 283 000e C368 ldr r3, [r0, #12] + 284 0010 43EA8123 orr r3, r3, r1, lsl #10 + 285 0014 C360 str r3, [r0, #12] + 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 286 .loc 1 212 3 is_stmt 1 view .LVU78 + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 287 .loc 1 213 1 is_stmt 0 view .LVU79 + 288 0016 0020 movs r0, #0 + 289 .LVL20: + 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 290 .loc 1 213 1 view .LVU80 + 291 0018 7047 bx lr + 292 .LVL21: + 293 .L32: + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 294 .loc 1 149 5 is_stmt 1 view .LVU81 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 295 .loc 1 149 29 is_stmt 0 view .LVU82 + 296 001a 204B ldr r3, .L33 + 297 001c 0B44 add r3, r3, r1 + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 298 .loc 1 149 8 view .LVU83 + 299 001e 204A ldr r2, .L33+4 + 300 .LVL22: + 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 301 .loc 1 149 8 view .LVU84 + 302 0020 9342 cmp r3, r2 + 303 0022 29D9 bls .L23 + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 304 .loc 1 154 10 is_stmt 1 view .LVU85 + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 305 .loc 1 154 34 is_stmt 0 view .LVU86 + 306 0024 1F4B ldr r3, .L33+8 + 307 0026 0B44 add r3, r3, r1 + 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 308 .loc 1 154 13 view .LVU87 + 309 0028 1F4A ldr r2, .L33+12 + 310 002a 9342 cmp r3, r2 + 311 002c 26D9 bls .L24 + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 312 .loc 1 159 10 is_stmt 1 view .LVU88 + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 313 .loc 1 159 34 is_stmt 0 view .LVU89 + 314 002e 1F4B ldr r3, .L33+16 + 315 0030 0B44 add r3, r3, r1 + 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 316 .loc 1 159 13 view .LVU90 + 317 0032 1F4A ldr r2, .L33+20 + 318 0034 9342 cmp r3, r2 + 319 0036 23D9 bls .L25 + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 320 .loc 1 164 10 is_stmt 1 view .LVU91 + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 321 .loc 1 164 34 is_stmt 0 view .LVU92 + ARM GAS /tmp/cc9mtr28.s page 31 + + + 322 0038 1E4B ldr r3, .L33+24 + 323 003a 0B44 add r3, r3, r1 + 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 324 .loc 1 164 13 view .LVU93 + 325 003c 1E4A ldr r2, .L33+28 + 326 003e 9342 cmp r3, r2 + 327 0040 20D3 bcc .L26 + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 328 .loc 1 169 10 is_stmt 1 view .LVU94 + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 329 .loc 1 169 34 is_stmt 0 view .LVU95 + 330 0042 1E4B ldr r3, .L33+32 + 331 0044 0B44 add r3, r3, r1 + 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 332 .loc 1 169 13 view .LVU96 + 333 0046 1E4A ldr r2, .L33+36 + 334 0048 9342 cmp r3, r2 + 335 004a 1DD9 bls .L27 + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 336 .loc 1 174 10 is_stmt 1 view .LVU97 + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 337 .loc 1 174 34 is_stmt 0 view .LVU98 + 338 004c 1D4B ldr r3, .L33+40 + 339 004e 0B44 add r3, r3, r1 + 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 340 .loc 1 174 13 view .LVU99 + 341 0050 1D4A ldr r2, .L33+44 + 342 0052 9342 cmp r3, r2 + 343 0054 1AD3 bcc .L28 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 344 .loc 1 179 10 is_stmt 1 view .LVU100 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 345 .loc 1 179 34 is_stmt 0 view .LVU101 + 346 0056 1D4B ldr r3, .L33+48 + 347 0058 0B44 add r3, r3, r1 + 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 348 .loc 1 179 13 view .LVU102 + 349 005a 1D4A ldr r2, .L33+52 + 350 005c 9342 cmp r3, r2 + 351 005e 17D3 bcc .L29 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 352 .loc 1 184 10 is_stmt 1 view .LVU103 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 353 .loc 1 184 34 is_stmt 0 view .LVU104 + 354 0060 1C4B ldr r3, .L33+56 + 355 0062 0B44 add r3, r3, r1 + 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 356 .loc 1 184 13 view .LVU105 + 357 0064 1C4A ldr r2, .L33+60 + 358 0066 9342 cmp r3, r2 + 359 0068 14D3 bcc .L30 + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 360 .loc 1 189 10 is_stmt 1 view .LVU106 + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 361 .loc 1 189 34 is_stmt 0 view .LVU107 + 362 006a 1C4B ldr r3, .L33+64 + 363 006c 0B44 add r3, r3, r1 + ARM GAS /tmp/cc9mtr28.s page 32 + + + 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 364 .loc 1 189 13 view .LVU108 + 365 006e 1C4A ldr r2, .L33+68 + 366 0070 9342 cmp r3, r2 + 367 0072 11D2 bcs .L31 + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 368 .loc 1 192 14 view .LVU109 + 369 0074 0721 movs r1, #7 + 370 .LVL23: + 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 371 .loc 1 192 14 view .LVU110 + 372 0076 C6E7 b .L21 + 373 .LVL24: + 374 .L23: + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 375 .loc 1 152 14 view .LVU111 + 376 0078 0F21 movs r1, #15 + 377 .LVL25: + 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 378 .loc 1 152 14 view .LVU112 + 379 007a C4E7 b .L21 + 380 .LVL26: + 381 .L24: + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 382 .loc 1 157 14 view .LVU113 + 383 007c 0E21 movs r1, #14 + 384 .LVL27: + 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 385 .loc 1 157 14 view .LVU114 + 386 007e C2E7 b .L21 + 387 .LVL28: + 388 .L25: + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 389 .loc 1 162 14 view .LVU115 + 390 0080 0D21 movs r1, #13 + 391 .LVL29: + 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 392 .loc 1 162 14 view .LVU116 + 393 0082 C0E7 b .L21 + 394 .LVL30: + 395 .L26: + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 396 .loc 1 167 14 view .LVU117 + 397 0084 0C21 movs r1, #12 + 398 .LVL31: + 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 399 .loc 1 167 14 view .LVU118 + 400 0086 BEE7 b .L21 + 401 .LVL32: + 402 .L27: + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 403 .loc 1 172 14 view .LVU119 + 404 0088 0B21 movs r1, #11 + 405 .LVL33: + 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 406 .loc 1 172 14 view .LVU120 + 407 008a BCE7 b .L21 + ARM GAS /tmp/cc9mtr28.s page 33 + + + 408 .LVL34: + 409 .L28: + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 410 .loc 1 177 14 view .LVU121 + 411 008c 0A21 movs r1, #10 + 412 .LVL35: + 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 413 .loc 1 177 14 view .LVU122 + 414 008e BAE7 b .L21 + 415 .LVL36: + 416 .L29: + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 417 .loc 1 182 14 view .LVU123 + 418 0090 0921 movs r1, #9 + 419 .LVL37: + 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 420 .loc 1 182 14 view .LVU124 + 421 0092 B8E7 b .L21 + 422 .LVL38: + 423 .L30: + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 424 .loc 1 187 14 view .LVU125 + 425 0094 0821 movs r1, #8 + 426 .LVL39: + 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 427 .loc 1 187 14 view .LVU126 + 428 0096 B6E7 b .L21 + 429 .LVL40: + 430 .L31: + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 431 .loc 1 197 14 view .LVU127 + 432 0098 0621 movs r1, #6 + 433 .LVL41: + 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 434 .loc 1 197 14 view .LVU128 + 435 009a B4E7 b .L21 + 436 .L34: + 437 .align 2 + 438 .L33: + 439 009c 405327FF .word -14200000 + 440 00a0 FF340C00 .word 799999 + 441 00a4 401E1BFF .word -15000000 + 442 00a8 3F420F00 .word 999999 + 443 00ac 00DC0BFF .word -16000000 + 444 00b0 7F4F1200 .word 1199999 + 445 00b4 808CF9FE .word -17200000 + 446 00b8 20D61300 .word 1300000 + 447 00bc 60B6E5FE .word -18500000 + 448 00c0 5FE31600 .word 1499999 + 449 00c4 00D3CEFE .word -20000000 + 450 00c8 40771B00 .word 1800000 + 451 00cc C05BB3FE .word -21800000 + 452 00d0 C0912100 .word 2200000 + 453 00d4 00CA91FE .word -24000000 + 454 00d8 20753800 .word 3700000 + 455 00dc E05459FE .word -27700000 + 456 00e0 E09C4100 .word 4300000 + ARM GAS /tmp/cc9mtr28.s page 34 + + + 457 .cfi_endproc + 458 .LFE142: + 460 .section .text.USB_EnableGlobalInt,"ax",%progbits + 461 .align 1 + 462 .global USB_EnableGlobalInt + 463 .syntax unified + 464 .thumb + 465 .thumb_func + 466 .fpu fpv5-d16 + 468 USB_EnableGlobalInt: + 469 .LVL42: + 470 .LFB143: + 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + 471 .loc 1 222 1 is_stmt 1 view -0 + 472 .cfi_startproc + 473 @ args = 0, pretend = 0, frame = 0 + 474 @ frame_needed = 0, uses_anonymous_args = 0 + 475 @ link register save eliminated. + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 476 .loc 1 223 3 view .LVU130 + 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 477 .loc 1 223 17 is_stmt 0 view .LVU131 + 478 0000 8368 ldr r3, [r0, #8] + 479 0002 43F00103 orr r3, r3, #1 + 480 0006 8360 str r3, [r0, #8] + 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 481 .loc 1 224 3 is_stmt 1 view .LVU132 + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 482 .loc 1 225 1 is_stmt 0 view .LVU133 + 483 0008 0020 movs r0, #0 + 484 .LVL43: + 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 485 .loc 1 225 1 view .LVU134 + 486 000a 7047 bx lr + 487 .cfi_endproc + 488 .LFE143: + 490 .section .text.USB_DisableGlobalInt,"ax",%progbits + 491 .align 1 + 492 .global USB_DisableGlobalInt + 493 .syntax unified + 494 .thumb + 495 .thumb_func + 496 .fpu fpv5-d16 + 498 USB_DisableGlobalInt: + 499 .LVL44: + 500 .LFB144: + 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + 501 .loc 1 234 1 is_stmt 1 view -0 + 502 .cfi_startproc + 503 @ args = 0, pretend = 0, frame = 0 + 504 @ frame_needed = 0, uses_anonymous_args = 0 + 505 @ link register save eliminated. + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 506 .loc 1 235 3 view .LVU136 + 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 507 .loc 1 235 17 is_stmt 0 view .LVU137 + 508 0000 8368 ldr r3, [r0, #8] + ARM GAS /tmp/cc9mtr28.s page 35 + + + 509 0002 23F00103 bic r3, r3, #1 + 510 0006 8360 str r3, [r0, #8] + 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 511 .loc 1 236 3 is_stmt 1 view .LVU138 + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 512 .loc 1 237 1 is_stmt 0 view .LVU139 + 513 0008 0020 movs r0, #0 + 514 .LVL45: + 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 515 .loc 1 237 1 view .LVU140 + 516 000a 7047 bx lr + 517 .cfi_endproc + 518 .LFE144: + 520 .section .text.USB_SetCurrentMode,"ax",%progbits + 521 .align 1 + 522 .global USB_SetCurrentMode + 523 .syntax unified + 524 .thumb + 525 .thumb_func + 526 .fpu fpv5-d16 + 528 USB_SetCurrentMode: + 529 .LVL46: + 530 .LFB145: + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + 531 .loc 1 250 1 is_stmt 1 view -0 + 532 .cfi_startproc + 533 @ args = 0, pretend = 0, frame = 0 + 534 @ frame_needed = 0, uses_anonymous_args = 0 + 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + 535 .loc 1 250 1 is_stmt 0 view .LVU142 + 536 0000 08B5 push {r3, lr} + 537 .LCFI5: + 538 .cfi_def_cfa_offset 8 + 539 .cfi_offset 3, -8 + 540 .cfi_offset 14, -4 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 541 .loc 1 251 3 is_stmt 1 view .LVU143 + 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 542 .loc 1 251 17 is_stmt 0 view .LVU144 + 543 0002 C368 ldr r3, [r0, #12] + 544 0004 23F0C043 bic r3, r3, #1610612736 + 545 0008 C360 str r3, [r0, #12] + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 546 .loc 1 253 3 is_stmt 1 view .LVU145 + 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 547 .loc 1 253 6 is_stmt 0 view .LVU146 + 548 000a 0129 cmp r1, #1 + 549 000c 09D0 beq .L43 + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 550 .loc 1 257 8 is_stmt 1 view .LVU147 + 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 551 .loc 1 257 11 is_stmt 0 view .LVU148 + 552 000e 69B9 cbnz r1, .L41 + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 553 .loc 1 259 5 is_stmt 1 view .LVU149 + 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 554 .loc 1 259 19 is_stmt 0 view .LVU150 + ARM GAS /tmp/cc9mtr28.s page 36 + + + 555 0010 C368 ldr r3, [r0, #12] + 556 0012 43F08043 orr r3, r3, #1073741824 + 557 0016 C360 str r3, [r0, #12] + 558 .L39: + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 559 .loc 1 265 3 is_stmt 1 view .LVU151 + 560 0018 3220 movs r0, #50 + 561 .LVL47: + 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 562 .loc 1 265 3 is_stmt 0 view .LVU152 + 563 001a FFF7FEFF bl HAL_Delay + 564 .LVL48: + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 565 .loc 1 267 3 is_stmt 1 view .LVU153 + 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 566 .loc 1 267 10 is_stmt 0 view .LVU154 + 567 001e 0020 movs r0, #0 + 568 .L40: + 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 569 .loc 1 268 1 view .LVU155 + 570 0020 08BD pop {r3, pc} + 571 .LVL49: + 572 .L43: + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 573 .loc 1 255 5 is_stmt 1 view .LVU156 + 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 574 .loc 1 255 19 is_stmt 0 view .LVU157 + 575 0022 C368 ldr r3, [r0, #12] + 576 0024 43F00053 orr r3, r3, #536870912 + 577 0028 C360 str r3, [r0, #12] + 578 002a F5E7 b .L39 + 579 .L41: + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 580 .loc 1 263 12 view .LVU158 + 581 002c 0120 movs r0, #1 + 582 .LVL50: + 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 583 .loc 1 263 12 view .LVU159 + 584 002e F7E7 b .L40 + 585 .cfi_endproc + 586 .LFE145: + 588 .section .text.USB_FlushTxFifo,"ax",%progbits + 589 .align 1 + 590 .global USB_FlushTxFifo + 591 .syntax unified + 592 .thumb + 593 .thumb_func + 594 .fpu fpv5-d16 + 596 USB_FlushTxFifo: + 597 .LVL51: + 598 .LFB147: + 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0U; + 599 .loc 1 434 1 is_stmt 1 view -0 + 600 .cfi_startproc + 601 @ args = 0, pretend = 0, frame = 0 + 602 @ frame_needed = 0, uses_anonymous_args = 0 + 603 @ link register save eliminated. + ARM GAS /tmp/cc9mtr28.s page 37 + + + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 604 .loc 1 435 3 view .LVU161 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 605 .loc 1 437 3 view .LVU162 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 606 .loc 1 437 51 is_stmt 0 view .LVU163 + 607 0000 8901 lsls r1, r1, #6 + 608 .LVL52: + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 609 .loc 1 437 44 view .LVU164 + 610 0002 41F02001 orr r1, r1, #32 + 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 611 .loc 1 437 17 view .LVU165 + 612 0006 0161 str r1, [r0, #16] + 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 613 .loc 1 435 12 view .LVU166 + 614 0008 0023 movs r3, #0 + 615 .LVL53: + 616 .L46: + 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 617 .loc 1 439 3 is_stmt 1 view .LVU167 + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 618 .loc 1 441 5 view .LVU168 + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 619 .loc 1 441 8 is_stmt 0 view .LVU169 + 620 000a 0133 adds r3, r3, #1 + 621 .LVL54: + 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 622 .loc 1 441 8 view .LVU170 + 623 000c 054A ldr r2, .L48 + 624 000e 9342 cmp r3, r2 + 625 0010 05D8 bhi .L47 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 626 .loc 1 446 9 is_stmt 1 view .LVU171 + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 627 .loc 1 446 15 is_stmt 0 view .LVU172 + 628 0012 0269 ldr r2, [r0, #16] + 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 629 .loc 1 446 3 view .LVU173 + 630 0014 12F0200F tst r2, #32 + 631 0018 F7D1 bne .L46 + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 632 .loc 1 448 10 view .LVU174 + 633 001a 0020 movs r0, #0 + 634 .LVL55: + 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 635 .loc 1 448 10 view .LVU175 + 636 001c 7047 bx lr + 637 .LVL56: + 638 .L47: + 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 639 .loc 1 443 14 view .LVU176 + 640 001e 0320 movs r0, #3 + 641 .LVL57: + 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 642 .loc 1 449 1 view .LVU177 + 643 0020 7047 bx lr + ARM GAS /tmp/cc9mtr28.s page 38 + + + 644 .L49: + 645 0022 00BF .align 2 + 646 .L48: + 647 0024 400D0300 .word 200000 + 648 .cfi_endproc + 649 .LFE147: + 651 .section .text.USB_FlushRxFifo,"ax",%progbits + 652 .align 1 + 653 .global USB_FlushRxFifo + 654 .syntax unified + 655 .thumb + 656 .thumb_func + 657 .fpu fpv5-d16 + 659 USB_FlushRxFifo: + 660 .LVL58: + 661 .LFB148: + 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0; + 662 .loc 1 457 1 is_stmt 1 view -0 + 663 .cfi_startproc + 664 @ args = 0, pretend = 0, frame = 0 + 665 @ frame_needed = 0, uses_anonymous_args = 0 + 666 @ link register save eliminated. + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 667 .loc 1 458 3 view .LVU179 + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 668 .loc 1 460 3 view .LVU180 + 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 669 .loc 1 460 17 is_stmt 0 view .LVU181 + 670 0000 1023 movs r3, #16 + 671 0002 0361 str r3, [r0, #16] + 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 672 .loc 1 458 12 view .LVU182 + 673 0004 0023 movs r3, #0 + 674 .LVL59: + 675 .L52: + 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 676 .loc 1 462 3 is_stmt 1 view .LVU183 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 677 .loc 1 464 5 view .LVU184 + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 678 .loc 1 464 8 is_stmt 0 view .LVU185 + 679 0006 0133 adds r3, r3, #1 + 680 .LVL60: + 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 681 .loc 1 464 8 view .LVU186 + 682 0008 054A ldr r2, .L54 + 683 000a 9342 cmp r3, r2 + 684 000c 05D8 bhi .L53 + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 685 .loc 1 469 9 is_stmt 1 view .LVU187 + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 686 .loc 1 469 15 is_stmt 0 view .LVU188 + 687 000e 0269 ldr r2, [r0, #16] + 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 688 .loc 1 469 3 view .LVU189 + 689 0010 12F0100F tst r2, #16 + 690 0014 F7D1 bne .L52 + ARM GAS /tmp/cc9mtr28.s page 39 + + + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 691 .loc 1 471 10 view .LVU190 + 692 0016 0020 movs r0, #0 + 693 .LVL61: + 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 694 .loc 1 471 10 view .LVU191 + 695 0018 7047 bx lr + 696 .LVL62: + 697 .L53: + 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 698 .loc 1 466 14 view .LVU192 + 699 001a 0320 movs r0, #3 + 700 .LVL63: + 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 701 .loc 1 472 1 view .LVU193 + 702 001c 7047 bx lr + 703 .L55: + 704 001e 00BF .align 2 + 705 .L54: + 706 0020 400D0300 .word 200000 + 707 .cfi_endproc + 708 .LFE148: + 710 .section .text.USB_SetDevSpeed,"ax",%progbits + 711 .align 1 + 712 .global USB_SetDevSpeed + 713 .syntax unified + 714 .thumb + 715 .thumb_func + 716 .fpu fpv5-d16 + 718 USB_SetDevSpeed: + 719 .LVL64: + 720 .LFB149: + 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 721 .loc 1 486 1 is_stmt 1 view -0 + 722 .cfi_startproc + 723 @ args = 0, pretend = 0, frame = 0 + 724 @ frame_needed = 0, uses_anonymous_args = 0 + 725 @ link register save eliminated. + 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 726 .loc 1 487 3 view .LVU195 + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 727 .loc 1 489 3 view .LVU196 + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 728 .loc 1 489 21 is_stmt 0 view .LVU197 + 729 0000 D0F80038 ldr r3, [r0, #2048] + 730 0004 1943 orrs r1, r1, r3 + 731 .LVL65: + 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 732 .loc 1 489 21 view .LVU198 + 733 0006 C0F80018 str r1, [r0, #2048] + 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 734 .loc 1 490 3 is_stmt 1 view .LVU199 + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 735 .loc 1 491 1 is_stmt 0 view .LVU200 + 736 000a 0020 movs r0, #0 + 737 .LVL66: + 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 40 + + + 738 .loc 1 491 1 view .LVU201 + 739 000c 7047 bx lr + 740 .cfi_endproc + 741 .LFE149: + 743 .section .text.USB_DevInit,"ax",%progbits + 744 .align 1 + 745 .global USB_DevInit + 746 .syntax unified + 747 .thumb + 748 .thumb_func + 749 .fpu fpv5-d16 + 751 USB_DevInit: + 752 .LVL67: + 753 .LFB146: + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret = HAL_OK; + 754 .loc 1 279 1 is_stmt 1 view -0 + 755 .cfi_startproc + 756 @ args = 56, pretend = 16, frame = 0 + 757 @ frame_needed = 0, uses_anonymous_args = 0 + 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret = HAL_OK; + 758 .loc 1 279 1 is_stmt 0 view .LVU203 + 759 0000 84B0 sub sp, sp, #16 + 760 .LCFI6: + 761 .cfi_def_cfa_offset 16 + 762 0002 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 763 .LCFI7: + 764 .cfi_def_cfa_offset 40 + 765 .cfi_offset 4, -40 + 766 .cfi_offset 5, -36 + 767 .cfi_offset 6, -32 + 768 .cfi_offset 7, -28 + 769 .cfi_offset 8, -24 + 770 .cfi_offset 14, -20 + 771 0006 0446 mov r4, r0 + 772 0008 07A8 add r0, sp, #28 + 773 000a 80E80E00 stm r0, {r1, r2, r3} + 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 774 .loc 1 280 3 is_stmt 1 view .LVU204 + 775 .LVL68: + 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 776 .loc 1 281 3 view .LVU205 + 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 777 .loc 1 282 3 view .LVU206 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 778 .loc 1 284 3 view .LVU207 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 779 .loc 1 284 10 is_stmt 0 view .LVU208 + 780 000e 0023 movs r3, #0 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 781 .loc 1 284 3 view .LVU209 + 782 0010 06E0 b .L58 + 783 .LVL69: + 784 .L59: + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 785 .loc 1 286 5 is_stmt 1 discriminator 3 view .LVU210 + 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 786 .loc 1 286 22 is_stmt 0 discriminator 3 view .LVU211 + ARM GAS /tmp/cc9mtr28.s page 41 + + + 787 0012 03F14002 add r2, r3, #64 + 788 0016 04EB8202 add r2, r4, r2, lsl #2 + 789 001a 0021 movs r1, #0 + 790 001c 5160 str r1, [r2, #4] + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 791 .loc 1 284 25 is_stmt 1 discriminator 3 view .LVU212 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 792 .loc 1 284 26 is_stmt 0 discriminator 3 view .LVU213 + 793 001e 0133 adds r3, r3, #1 + 794 .LVL70: + 795 .L58: + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 796 .loc 1 284 16 is_stmt 1 discriminator 1 view .LVU214 + 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 797 .loc 1 284 3 is_stmt 0 discriminator 1 view .LVU215 + 798 0020 0E2B cmp r3, #14 + 799 0022 F6D9 bls .L59 + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 800 .loc 1 290 3 is_stmt 1 view .LVU216 + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 801 .loc 1 290 10 is_stmt 0 view .LVU217 + 802 0024 119F ldr r7, [sp, #68] + 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 803 .loc 1 290 6 view .LVU218 + 804 0026 27BB cbnz r7, .L60 + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 805 .loc 1 292 5 is_stmt 1 view .LVU219 + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 806 .loc 1 292 23 is_stmt 0 view .LVU220 + 807 0028 D4F80438 ldr r3, [r4, #2052] + 808 .LVL71: + 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 809 .loc 1 292 23 view .LVU221 + 810 002c 43F00203 orr r3, r3, #2 + 811 0030 C4F80438 str r3, [r4, #2052] + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 812 .loc 1 295 5 is_stmt 1 view .LVU222 + 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 813 .loc 1 295 17 is_stmt 0 view .LVU223 + 814 0034 A36B ldr r3, [r4, #56] + 815 0036 23F40013 bic r3, r3, #2097152 + 816 003a A363 str r3, [r4, #56] + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + 817 .loc 1 298 5 is_stmt 1 view .LVU224 + 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + 818 .loc 1 298 19 is_stmt 0 view .LVU225 + 819 003c 2368 ldr r3, [r4] + 820 003e 43F04003 orr r3, r3, #64 + 821 0042 2360 str r3, [r4] + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 822 .loc 1 299 5 is_stmt 1 view .LVU226 + 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 823 .loc 1 299 19 is_stmt 0 view .LVU227 + 824 0044 2368 ldr r3, [r4] + 825 0046 43F08003 orr r3, r3, #128 + 826 004a 2360 str r3, [r4] + 827 .L61: + ARM GAS /tmp/cc9mtr28.s page 42 + + + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 828 .loc 1 308 3 is_stmt 1 view .LVU228 + 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 829 .loc 1 308 16 is_stmt 0 view .LVU229 + 830 004c 0023 movs r3, #0 + 831 004e C4F8003E str r3, [r4, #3584] + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 832 .loc 1 311 3 is_stmt 1 view .LVU230 + 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 833 .loc 1 311 21 is_stmt 0 view .LVU231 + 834 0052 04F50065 add r5, r4, #2048 + 835 0056 D4F80038 ldr r3, [r4, #2048] + 836 005a C4F80038 str r3, [r4, #2048] + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 837 .loc 1 313 3 is_stmt 1 view .LVU232 + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 838 .loc 1 313 10 is_stmt 0 view .LVU233 + 839 005e 0C9B ldr r3, [sp, #48] + 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 840 .loc 1 313 6 view .LVU234 + 841 0060 012B cmp r3, #1 + 842 0062 10D1 bne .L62 + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 843 .loc 1 315 5 is_stmt 1 view .LVU235 + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 844 .loc 1 315 12 is_stmt 0 view .LVU236 + 845 0064 099B ldr r3, [sp, #36] + 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 846 .loc 1 315 8 view .LVU237 + 847 0066 4BB9 cbnz r3, .L63 + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 848 .loc 1 318 7 is_stmt 1 view .LVU238 + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 849 .loc 1 318 13 is_stmt 0 view .LVU239 + 850 0068 0021 movs r1, #0 + 851 006a 2046 mov r0, r4 + 852 .LVL72: + 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 853 .loc 1 318 13 view .LVU240 + 854 006c FFF7FEFF bl USB_SetDevSpeed + 855 .LVL73: + 856 0070 0DE0 b .L64 + 857 .LVL74: + 858 .L60: + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 859 .loc 1 304 5 is_stmt 1 view .LVU241 + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 860 .loc 1 304 17 is_stmt 0 view .LVU242 + 861 0072 A36B ldr r3, [r4, #56] + 862 .LVL75: + 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 863 .loc 1 304 17 view .LVU243 + 864 0074 43F40013 orr r3, r3, #2097152 + 865 0078 A363 str r3, [r4, #56] + 866 007a E7E7 b .L61 + 867 .L63: + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + ARM GAS /tmp/cc9mtr28.s page 43 + + + 868 .loc 1 323 7 is_stmt 1 view .LVU244 + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 869 .loc 1 323 13 is_stmt 0 view .LVU245 + 870 007c 0121 movs r1, #1 + 871 007e 2046 mov r0, r4 + 872 .LVL76: + 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 873 .loc 1 323 13 view .LVU246 + 874 0080 FFF7FEFF bl USB_SetDevSpeed + 875 .LVL77: + 876 0084 03E0 b .L64 + 877 .LVL78: + 878 .L62: + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 879 .loc 1 329 5 is_stmt 1 view .LVU247 + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 880 .loc 1 329 11 is_stmt 0 view .LVU248 + 881 0086 0321 movs r1, #3 + 882 0088 2046 mov r0, r4 + 883 .LVL79: + 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 884 .loc 1 329 11 view .LVU249 + 885 008a FFF7FEFF bl USB_SetDevSpeed + 886 .LVL80: + 887 .L64: + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 888 .loc 1 333 3 is_stmt 1 view .LVU250 + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 889 .loc 1 333 7 is_stmt 0 view .LVU251 + 890 008e 1021 movs r1, #16 + 891 0090 2046 mov r0, r4 + 892 0092 FFF7FEFF bl USB_FlushTxFifo + 893 .LVL81: + 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 894 .loc 1 333 6 view .LVU252 + 895 0096 8046 mov r8, r0 + 896 0098 08B1 cbz r0, .L65 + 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 897 .loc 1 335 9 view .LVU253 + 898 009a 4FF00108 mov r8, #1 + 899 .L65: + 900 .LVL82: + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 901 .loc 1 338 3 is_stmt 1 view .LVU254 + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 902 .loc 1 338 7 is_stmt 0 view .LVU255 + 903 009e 2046 mov r0, r4 + 904 00a0 FFF7FEFF bl USB_FlushRxFifo + 905 .LVL83: + 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 906 .loc 1 338 6 view .LVU256 + 907 00a4 08B1 cbz r0, .L66 + 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 908 .loc 1 340 9 view .LVU257 + 909 00a6 4FF00108 mov r8, #1 + 910 .LVL84: + 911 .L66: + ARM GAS /tmp/cc9mtr28.s page 44 + + + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; + 912 .loc 1 344 3 is_stmt 1 view .LVU258 + 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; + 913 .loc 1 344 24 is_stmt 0 view .LVU259 + 914 00aa 0023 movs r3, #0 + 915 00ac 2B61 str r3, [r5, #16] + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK = 0U; + 916 .loc 1 345 3 is_stmt 1 view .LVU260 + 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK = 0U; + 917 .loc 1 345 24 is_stmt 0 view .LVU261 + 918 00ae 6B61 str r3, [r5, #20] + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 919 .loc 1 346 3 is_stmt 1 view .LVU262 + 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 920 .loc 1 346 25 is_stmt 0 view .LVU263 + 921 00b0 EB61 str r3, [r5, #28] + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 922 .loc 1 348 3 is_stmt 1 view .LVU264 + 923 .LVL85: + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 924 .loc 1 348 3 is_stmt 0 view .LVU265 + 925 00b2 0AE0 b .L67 + 926 .LVL86: + 927 .L84: + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 928 .loc 1 352 7 is_stmt 1 view .LVU266 + 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 929 .loc 1 352 10 is_stmt 0 view .LVU267 + 930 00b4 C3B9 cbnz r3, .L69 + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 931 .loc 1 354 9 is_stmt 1 view .LVU268 + 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 932 .loc 1 354 31 is_stmt 0 view .LVU269 + 933 00b6 4FF00060 mov r0, #134217728 + 934 00ba C2F80009 str r0, [r2, #2304] + 935 .L70: + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPINT = 0xFB7FU; + 936 .loc 1 366 5 is_stmt 1 discriminator 2 view .LVU270 + 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(i)->DIEPINT = 0xFB7FU; + 937 .loc 1 366 28 is_stmt 0 discriminator 2 view .LVU271 + 938 00be 0022 movs r2, #0 + 939 00c0 0A61 str r2, [r1, #16] + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 940 .loc 1 367 5 is_stmt 1 discriminator 2 view .LVU272 + 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 941 .loc 1 367 28 is_stmt 0 discriminator 2 view .LVU273 + 942 00c2 4FF67F32 movw r2, #64383 + 943 00c6 8A60 str r2, [r1, #8] + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 944 .loc 1 348 39 is_stmt 1 discriminator 2 view .LVU274 + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 945 .loc 1 348 40 is_stmt 0 discriminator 2 view .LVU275 + 946 00c8 0133 adds r3, r3, #1 + 947 .LVL87: + 948 .L67: + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 949 .loc 1 348 16 is_stmt 1 discriminator 1 view .LVU276 + ARM GAS /tmp/cc9mtr28.s page 45 + + + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 950 .loc 1 348 23 is_stmt 0 discriminator 1 view .LVU277 + 951 00ca 0799 ldr r1, [sp, #28] + 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 952 .loc 1 348 3 discriminator 1 view .LVU278 + 953 00cc 9942 cmp r1, r3 + 954 00ce 10D9 bls .L83 + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 955 .loc 1 350 5 is_stmt 1 view .LVU279 + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 956 .loc 1 350 10 is_stmt 0 view .LVU280 + 957 00d0 04EB4312 add r2, r4, r3, lsl #5 + 958 00d4 02F51061 add r1, r2, #2304 + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 959 .loc 1 350 22 view .LVU281 + 960 00d8 D2F80009 ldr r0, [r2, #2304] + 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 961 .loc 1 350 8 view .LVU282 + 962 00dc 0028 cmp r0, #0 + 963 00de E9DB blt .L84 + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 964 .loc 1 363 7 is_stmt 1 view .LVU283 + 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 965 .loc 1 363 29 is_stmt 0 view .LVU284 + 966 00e0 0020 movs r0, #0 + 967 00e2 C2F80009 str r0, [r2, #2304] + 968 00e6 EAE7 b .L70 + 969 .L69: + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 970 .loc 1 358 9 is_stmt 1 view .LVU285 + 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 971 .loc 1 358 31 is_stmt 0 view .LVU286 + 972 00e8 4FF09040 mov r0, #1207959552 + 973 00ec C2F80009 str r0, [r2, #2304] + 974 00f0 E5E7 b .L70 + 975 .L83: + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 976 .loc 1 370 10 view .LVU287 + 977 00f2 0023 movs r3, #0 + 978 .LVL88: + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 979 .loc 1 370 10 view .LVU288 + 980 00f4 0AE0 b .L72 + 981 .LVL89: + 982 .L87: + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 983 .loc 1 374 7 is_stmt 1 view .LVU289 + 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 984 .loc 1 374 10 is_stmt 0 view .LVU290 + 985 00f6 C3B1 cbz r3, .L85 + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 986 .loc 1 380 9 is_stmt 1 view .LVU291 + 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 987 .loc 1 380 32 is_stmt 0 view .LVU292 + 988 00f8 4FF0904C mov ip, #1207959552 + 989 00fc C2F800CB str ip, [r2, #2816] + 990 .L75: + ARM GAS /tmp/cc9mtr28.s page 46 + + + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 991 .loc 1 388 5 is_stmt 1 discriminator 2 view .LVU293 + 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 992 .loc 1 388 29 is_stmt 0 discriminator 2 view .LVU294 + 993 0100 0022 movs r2, #0 + 994 0102 0261 str r2, [r0, #16] + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 995 .loc 1 389 5 is_stmt 1 discriminator 2 view .LVU295 + 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 996 .loc 1 389 29 is_stmt 0 discriminator 2 view .LVU296 + 997 0104 4FF67F32 movw r2, #64383 + 998 0108 8260 str r2, [r0, #8] + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 999 .loc 1 370 39 is_stmt 1 discriminator 2 view .LVU297 + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1000 .loc 1 370 40 is_stmt 0 discriminator 2 view .LVU298 + 1001 010a 0133 adds r3, r3, #1 + 1002 .LVL90: + 1003 .L72: + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1004 .loc 1 370 16 is_stmt 1 discriminator 1 view .LVU299 + 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1005 .loc 1 370 3 is_stmt 0 discriminator 1 view .LVU300 + 1006 010c 9942 cmp r1, r3 + 1007 010e 11D9 bls .L86 + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1008 .loc 1 372 5 is_stmt 1 view .LVU301 + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1009 .loc 1 372 10 is_stmt 0 view .LVU302 + 1010 0110 04EB4312 add r2, r4, r3, lsl #5 + 1011 0114 02F53060 add r0, r2, #2816 + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1012 .loc 1 372 23 view .LVU303 + 1013 0118 D2F8006B ldr r6, [r2, #2816] + 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1014 .loc 1 372 8 view .LVU304 + 1015 011c 002E cmp r6, #0 + 1016 011e EADB blt .L87 + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1017 .loc 1 385 7 is_stmt 1 view .LVU305 + 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1018 .loc 1 385 30 is_stmt 0 view .LVU306 + 1019 0120 4FF0000C mov ip, #0 + 1020 0124 C2F800CB str ip, [r2, #2816] + 1021 0128 EAE7 b .L75 + 1022 .L85: + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1023 .loc 1 376 9 is_stmt 1 view .LVU307 + 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1024 .loc 1 376 32 is_stmt 0 view .LVU308 + 1025 012a 4FF0006C mov ip, #134217728 + 1026 012e C2F800CB str ip, [r2, #2816] + 1027 0132 E5E7 b .L75 + 1028 .L86: + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1029 .loc 1 392 3 is_stmt 1 view .LVU309 + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 47 + + + 1030 .loc 1 392 24 is_stmt 0 view .LVU310 + 1031 0134 2B69 ldr r3, [r5, #16] + 1032 .LVL91: + 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1033 .loc 1 392 24 view .LVU311 + 1034 0136 23F48073 bic r3, r3, #256 + 1035 013a 2B61 str r3, [r5, #16] + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1036 .loc 1 395 3 is_stmt 1 view .LVU312 + 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1037 .loc 1 395 17 is_stmt 0 view .LVU313 + 1038 013c 0023 movs r3, #0 + 1039 013e A361 str r3, [r4, #24] + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1040 .loc 1 398 3 is_stmt 1 view .LVU314 + 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1041 .loc 1 398 17 is_stmt 0 view .LVU315 + 1042 0140 6FF08043 mvn r3, #1073741824 + 1043 0144 6361 str r3, [r4, #20] + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1044 .loc 1 401 3 is_stmt 1 view .LVU316 + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1045 .loc 1 401 10 is_stmt 0 view .LVU317 + 1046 0146 0A9B ldr r3, [sp, #40] + 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1047 .loc 1 401 6 view .LVU318 + 1048 0148 1BB9 cbnz r3, .L77 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1049 .loc 1 403 5 is_stmt 1 view .LVU319 + 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1050 .loc 1 403 19 is_stmt 0 view .LVU320 + 1051 014a A369 ldr r3, [r4, #24] + 1052 014c 43F01003 orr r3, r3, #16 + 1053 0150 A361 str r3, [r4, #24] + 1054 .L77: + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + 1055 .loc 1 407 3 is_stmt 1 view .LVU321 + 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + 1056 .loc 1 407 17 is_stmt 0 view .LVU322 + 1057 0152 A269 ldr r2, [r4, #24] + 1058 0154 0A4B ldr r3, .L89 + 1059 0156 1343 orrs r3, r3, r2 + 1060 0158 A361 str r3, [r4, #24] + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1061 .loc 1 412 3 is_stmt 1 view .LVU323 + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1062 .loc 1 412 10 is_stmt 0 view .LVU324 + 1063 015a 0D9B ldr r3, [sp, #52] + 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1064 .loc 1 412 6 view .LVU325 + 1065 015c 1BB1 cbz r3, .L78 + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1066 .loc 1 414 5 is_stmt 1 view .LVU326 + 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1067 .loc 1 414 19 is_stmt 0 view .LVU327 + 1068 015e A369 ldr r3, [r4, #24] + 1069 0160 43F00803 orr r3, r3, #8 + ARM GAS /tmp/cc9mtr28.s page 48 + + + 1070 0164 A361 str r3, [r4, #24] + 1071 .L78: + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1072 .loc 1 417 3 is_stmt 1 view .LVU328 + 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1073 .loc 1 417 6 is_stmt 0 view .LVU329 + 1074 0166 012F cmp r7, #1 + 1075 0168 04D0 beq .L88 + 1076 .L79: + 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1077 .loc 1 422 3 is_stmt 1 view .LVU330 + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1078 .loc 1 423 1 is_stmt 0 view .LVU331 + 1079 016a 4046 mov r0, r8 + 1080 016c BDE8F041 pop {r4, r5, r6, r7, r8, lr} + 1081 .LCFI8: + 1082 .cfi_remember_state + 1083 .cfi_restore 14 + 1084 .cfi_restore 8 + 1085 .cfi_restore 7 + 1086 .cfi_restore 6 + 1087 .cfi_restore 5 + 1088 .cfi_restore 4 + 1089 .cfi_def_cfa_offset 16 + 1090 .LVL92: + 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1091 .loc 1 423 1 view .LVU332 + 1092 0170 04B0 add sp, sp, #16 + 1093 .LCFI9: + 1094 .cfi_def_cfa_offset 0 + 1095 0172 7047 bx lr + 1096 .LVL93: + 1097 .L88: + 1098 .LCFI10: + 1099 .cfi_restore_state + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1100 .loc 1 419 5 is_stmt 1 view .LVU333 + 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1101 .loc 1 419 19 is_stmt 0 view .LVU334 + 1102 0174 A269 ldr r2, [r4, #24] + 1103 0176 034B ldr r3, .L89+4 + 1104 0178 1343 orrs r3, r3, r2 + 1105 017a A361 str r3, [r4, #24] + 1106 017c F5E7 b .L79 + 1107 .L90: + 1108 017e 00BF .align 2 + 1109 .L89: + 1110 0180 00383C80 .word -2143537152 + 1111 0184 04000040 .word 1073741828 + 1112 .cfi_endproc + 1113 .LFE146: + 1115 .section .text.USB_GetDevSpeed,"ax",%progbits + 1116 .align 1 + 1117 .global USB_GetDevSpeed + 1118 .syntax unified + 1119 .thumb + 1120 .thumb_func + ARM GAS /tmp/cc9mtr28.s page 49 + + + 1121 .fpu fpv5-d16 + 1123 USB_GetDevSpeed: + 1124 .LVL94: + 1125 .LFB150: + 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1126 .loc 1 502 1 is_stmt 1 view -0 + 1127 .cfi_startproc + 1128 @ args = 0, pretend = 0, frame = 0 + 1129 @ frame_needed = 0, uses_anonymous_args = 0 + 1130 @ link register save eliminated. + 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t speed; + 1131 .loc 1 503 3 view .LVU336 + 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + 1132 .loc 1 504 3 view .LVU337 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1133 .loc 1 505 3 view .LVU338 + 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1134 .loc 1 505 38 is_stmt 0 view .LVU339 + 1135 0000 D0F80838 ldr r3, [r0, #2056] + 1136 .LVL95: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1137 .loc 1 507 3 is_stmt 1 view .LVU340 + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1138 .loc 1 507 6 is_stmt 0 view .LVU341 + 1139 0004 13F00603 ands r3, r3, #6 + 1140 .LVL96: + 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1141 .loc 1 507 6 view .LVU342 + 1142 0008 05D0 beq .L93 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + 1143 .loc 1 511 8 is_stmt 1 view .LVU343 + 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + 1144 .loc 1 511 11 is_stmt 0 view .LVU344 + 1145 000a 062B cmp r3, #6 + 1146 000c 18BF it ne + 1147 000e 022B cmpne r3, #2 + 1148 0010 03D1 bne .L94 + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1149 .loc 1 514 11 view .LVU345 + 1150 0012 0220 movs r0, #2 + 1151 .LVL97: + 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1152 .loc 1 514 11 view .LVU346 + 1153 0014 7047 bx lr + 1154 .LVL98: + 1155 .L93: + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1156 .loc 1 509 11 view .LVU347 + 1157 0016 0020 movs r0, #0 + 1158 .LVL99: + 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1159 .loc 1 509 11 view .LVU348 + 1160 0018 7047 bx lr + 1161 .LVL100: + 1162 .L94: + 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1163 .loc 1 518 11 view .LVU349 + ARM GAS /tmp/cc9mtr28.s page 50 + + + 1164 001a 0F20 movs r0, #15 + 1165 .LVL101: + 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1166 .loc 1 521 3 is_stmt 1 view .LVU350 + 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1167 .loc 1 522 1 is_stmt 0 view .LVU351 + 1168 001c 7047 bx lr + 1169 .cfi_endproc + 1170 .LFE150: + 1172 .section .text.USB_ActivateEndpoint,"ax",%progbits + 1173 .align 1 + 1174 .global USB_ActivateEndpoint + 1175 .syntax unified + 1176 .thumb + 1177 .thumb_func + 1178 .fpu fpv5-d16 + 1180 USB_ActivateEndpoint: + 1181 .LVL102: + 1182 .LFB151: + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1183 .loc 1 531 1 is_stmt 1 view -0 + 1184 .cfi_startproc + 1185 @ args = 0, pretend = 0, frame = 0 + 1186 @ frame_needed = 0, uses_anonymous_args = 0 + 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1187 .loc 1 531 1 is_stmt 0 view .LVU353 + 1188 0000 10B5 push {r4, lr} + 1189 .LCFI11: + 1190 .cfi_def_cfa_offset 8 + 1191 .cfi_offset 4, -8 + 1192 .cfi_offset 14, -4 + 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 1193 .loc 1 532 3 is_stmt 1 view .LVU354 + 1194 .LVL103: + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1195 .loc 1 533 3 view .LVU355 + 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1196 .loc 1 533 32 is_stmt 0 view .LVU356 + 1197 0002 91F800C0 ldrb ip, [r1] @ zero_extendqisi2 + 1198 .LVL104: + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1199 .loc 1 535 3 is_stmt 1 view .LVU357 + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1200 .loc 1 535 9 is_stmt 0 view .LVU358 + 1201 0006 4B78 ldrb r3, [r1, #1] @ zero_extendqisi2 + 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1202 .loc 1 535 6 view .LVU359 + 1203 0008 012B cmp r3, #1 + 1204 000a 21D0 beq .L99 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1205 .loc 1 549 5 is_stmt 1 view .LVU360 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1206 .loc 1 549 27 is_stmt 0 view .LVU361 + 1207 000c 00F5006E add lr, r0, #2048 + 1208 0010 D0F81C38 ldr r3, [r0, #2076] + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1209 .loc 1 549 82 view .LVU362 + ARM GAS /tmp/cc9mtr28.s page 51 + + + 1210 0014 0CF00F04 and r4, ip, #15 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1211 .loc 1 549 55 view .LVU363 + 1212 0018 0122 movs r2, #1 + 1213 001a A240 lsls r2, r2, r4 + 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1214 .loc 1 549 27 view .LVU364 + 1215 001c 43EA0243 orr r3, r3, r2, lsl #16 + 1216 0020 C0F81C38 str r3, [r0, #2076] + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1217 .loc 1 551 5 is_stmt 1 view .LVU365 + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1218 .loc 1 551 11 is_stmt 0 view .LVU366 + 1219 0024 00EB4C10 add r0, r0, ip, lsl #5 + 1220 .LVL105: + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1221 .loc 1 551 28 view .LVU367 + 1222 0028 D0F8003B ldr r3, [r0, #2816] + 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1223 .loc 1 551 8 view .LVU368 + 1224 002c 13F4004F tst r3, #32768 + 1225 0030 0CD1 bne .L97 + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 1226 .loc 1 553 7 is_stmt 1 view .LVU369 + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 1227 .loc 1 553 34 is_stmt 0 view .LVU370 + 1228 0032 D0F8002B ldr r2, [r0, #2816] + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 1229 .loc 1 553 40 view .LVU371 + 1230 0036 8B68 ldr r3, [r1, #8] + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 1231 .loc 1 553 52 view .LVU372 + 1232 0038 C3F30A03 ubfx r3, r3, #0, #11 + 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 1233 .loc 1 554 50 view .LVU373 + 1234 003c C978 ldrb r1, [r1, #3] @ zero_extendqisi2 + 1235 .LVL106: + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 1236 .loc 1 553 77 view .LVU374 + 1237 003e 43EA8143 orr r3, r3, r1, lsl #18 + 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | + 1238 .loc 1 553 34 view .LVU375 + 1239 0042 1343 orrs r3, r3, r2 + 1240 0044 144A ldr r2, .L100 + 1241 0046 1A43 orrs r2, r2, r3 + 1242 0048 C0F8002B str r2, [r0, #2816] + 1243 .LVL107: + 1244 .L97: + 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1245 .loc 1 559 3 is_stmt 1 view .LVU376 + 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1246 .loc 1 560 1 is_stmt 0 view .LVU377 + 1247 004c 0020 movs r0, #0 + 1248 004e 10BD pop {r4, pc} + 1249 .LVL108: + 1250 .L99: + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 52 + + + 1251 .loc 1 537 5 is_stmt 1 view .LVU378 + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1252 .loc 1 537 27 is_stmt 0 view .LVU379 + 1253 0050 D0F81C28 ldr r2, [r0, #2076] + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1254 .loc 1 537 81 view .LVU380 + 1255 0054 0CF00F0E and lr, ip, #15 + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1256 .loc 1 537 54 view .LVU381 + 1257 0058 03FA0EF3 lsl r3, r3, lr + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1258 .loc 1 537 52 view .LVU382 + 1259 005c 9BB2 uxth r3, r3 + 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1260 .loc 1 537 27 view .LVU383 + 1261 005e 1343 orrs r3, r3, r2 + 1262 0060 C0F81C38 str r3, [r0, #2076] + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1263 .loc 1 539 5 is_stmt 1 view .LVU384 + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1264 .loc 1 539 10 is_stmt 0 view .LVU385 + 1265 0064 00EB4C10 add r0, r0, ip, lsl #5 + 1266 .LVL109: + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1267 .loc 1 539 26 view .LVU386 + 1268 0068 D0F80039 ldr r3, [r0, #2304] + 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1269 .loc 1 539 8 view .LVU387 + 1270 006c 13F4004F tst r3, #32768 + 1271 0070 ECD1 bne .L97 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1272 .loc 1 541 7 is_stmt 1 view .LVU388 + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1273 .loc 1 541 33 is_stmt 0 view .LVU389 + 1274 0072 D0F80029 ldr r2, [r0, #2304] + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1275 .loc 1 541 39 view .LVU390 + 1276 0076 8B68 ldr r3, [r1, #8] + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1277 .loc 1 541 51 view .LVU391 + 1278 0078 C3F30A03 ubfx r3, r3, #0, #11 + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 1279 .loc 1 542 49 view .LVU392 + 1280 007c C978 ldrb r1, [r1, #3] @ zero_extendqisi2 + 1281 .LVL110: + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1282 .loc 1 541 76 view .LVU393 + 1283 007e 43EA8143 orr r3, r3, r1, lsl #18 + 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 1284 .loc 1 542 63 view .LVU394 + 1285 0082 43EA8C5C orr ip, r3, ip, lsl #22 + 1286 .LVL111: + 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1287 .loc 1 541 33 view .LVU395 + 1288 0086 42EA0C0C orr ip, r2, ip + 1289 008a 034B ldr r3, .L100 + 1290 008c 4CEA0303 orr r3, ip, r3 + ARM GAS /tmp/cc9mtr28.s page 53 + + + 1291 0090 C0F80039 str r3, [r0, #2304] + 1292 0094 DAE7 b .L97 + 1293 .L101: + 1294 0096 00BF .align 2 + 1295 .L100: + 1296 0098 00800010 .word 268468224 + 1297 .cfi_endproc + 1298 .LFE151: + 1300 .section .text.USB_ActivateDedicatedEndpoint,"ax",%progbits + 1301 .align 1 + 1302 .global USB_ActivateDedicatedEndpoint + 1303 .syntax unified + 1304 .thumb + 1305 .thumb_func + 1306 .fpu fpv5-d16 + 1308 USB_ActivateDedicatedEndpoint: + 1309 .LVL112: + 1310 .LFB152: + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1311 .loc 1 569 1 is_stmt 1 view -0 + 1312 .cfi_startproc + 1313 @ args = 0, pretend = 0, frame = 0 + 1314 @ frame_needed = 0, uses_anonymous_args = 0 + 1315 @ link register save eliminated. + 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1316 .loc 1 569 1 is_stmt 0 view .LVU397 + 1317 0000 30B4 push {r4, r5} + 1318 .LCFI12: + 1319 .cfi_def_cfa_offset 8 + 1320 .cfi_offset 4, -8 + 1321 .cfi_offset 5, -4 + 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 1322 .loc 1 570 3 is_stmt 1 view .LVU398 + 1323 .LVL113: + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1324 .loc 1 571 3 view .LVU399 + 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1325 .loc 1 571 32 is_stmt 0 view .LVU400 + 1326 0002 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 1327 .LVL114: + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1328 .loc 1 574 3 is_stmt 1 view .LVU401 + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1329 .loc 1 574 9 is_stmt 0 view .LVU402 + 1330 0004 4B78 ldrb r3, [r1, #1] @ zero_extendqisi2 + 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1331 .loc 1 574 6 view .LVU403 + 1332 0006 012B cmp r3, #1 + 1333 0008 23D0 beq .L108 + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1334 .loc 1 588 5 is_stmt 1 view .LVU404 + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1335 .loc 1 588 11 is_stmt 0 view .LVU405 + 1336 000a 00EB421C add ip, r0, r2, lsl #5 + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1337 .loc 1 588 28 view .LVU406 + 1338 000e DCF8003B ldr r3, [ip, #2816] + ARM GAS /tmp/cc9mtr28.s page 54 + + + 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1339 .loc 1 588 8 view .LVU407 + 1340 0012 13F4004F tst r3, #32768 + 1341 0016 0ED1 bne .L106 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1342 .loc 1 590 7 is_stmt 1 view .LVU408 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1343 .loc 1 590 34 is_stmt 0 view .LVU409 + 1344 0018 DCF8004B ldr r4, [ip, #2816] + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1345 .loc 1 590 40 view .LVU410 + 1346 001c 8B68 ldr r3, [r1, #8] + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1347 .loc 1 590 52 view .LVU411 + 1348 001e C3F30A03 ubfx r3, r3, #0, #11 + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_USBAEP; + 1349 .loc 1 591 50 view .LVU412 + 1350 0022 CD78 ldrb r5, [r1, #3] @ zero_extendqisi2 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1351 .loc 1 590 77 view .LVU413 + 1352 0024 43EA8543 orr r3, r3, r5, lsl #18 + 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_USBAEP; + 1353 .loc 1 591 64 view .LVU414 + 1354 0028 43EA8253 orr r3, r3, r2, lsl #22 + 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1355 .loc 1 590 34 view .LVU415 + 1356 002c 2343 orrs r3, r3, r4 + 1357 002e 43F40043 orr r3, r3, #32768 + 1358 0032 CCF8003B str r3, [ip, #2816] + 1359 .L106: + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1360 .loc 1 595 5 is_stmt 1 view .LVU416 + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1361 .loc 1 595 27 is_stmt 0 view .LVU417 + 1362 0036 D0F83C38 ldr r3, [r0, #2108] + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1363 .loc 1 595 76 view .LVU418 + 1364 003a 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 1365 .LVL115: + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1366 .loc 1 595 82 view .LVU419 + 1367 003c 02F00F01 and r1, r2, #15 + 1368 .LVL116: + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1369 .loc 1 595 55 view .LVU420 + 1370 0040 0122 movs r2, #1 + 1371 0042 8A40 lsls r2, r2, r1 + 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1372 .loc 1 595 27 view .LVU421 + 1373 0044 43EA0243 orr r3, r3, r2, lsl #16 + 1374 0048 C0F83C38 str r3, [r0, #2108] + 1375 .L105: + 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1376 .loc 1 598 3 is_stmt 1 view .LVU422 + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1377 .loc 1 599 1 is_stmt 0 view .LVU423 + 1378 004c 0020 movs r0, #0 + ARM GAS /tmp/cc9mtr28.s page 55 + + + 1379 .LVL117: + 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1380 .loc 1 599 1 view .LVU424 + 1381 004e 30BC pop {r4, r5} + 1382 .LCFI13: + 1383 .cfi_remember_state + 1384 .cfi_restore 5 + 1385 .cfi_restore 4 + 1386 .cfi_def_cfa_offset 0 + 1387 0050 7047 bx lr + 1388 .LVL118: + 1389 .L108: + 1390 .LCFI14: + 1391 .cfi_restore_state + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1392 .loc 1 576 5 is_stmt 1 view .LVU425 + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1393 .loc 1 576 11 is_stmt 0 view .LVU426 + 1394 0052 00EB4214 add r4, r0, r2, lsl #5 + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1395 .loc 1 576 27 view .LVU427 + 1396 0056 D4F80039 ldr r3, [r4, #2304] + 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1397 .loc 1 576 8 view .LVU428 + 1398 005a 13F4004F tst r3, #32768 + 1399 005e 0FD1 bne .L104 + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1400 .loc 1 578 7 is_stmt 1 view .LVU429 + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1401 .loc 1 578 33 is_stmt 0 view .LVU430 + 1402 0060 D4F80059 ldr r5, [r4, #2304] + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1403 .loc 1 578 39 view .LVU431 + 1404 0064 8B68 ldr r3, [r1, #8] + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1405 .loc 1 578 51 view .LVU432 + 1406 0066 C3F30A03 ubfx r3, r3, #0, #11 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 1407 .loc 1 579 49 view .LVU433 + 1408 006a 91F803C0 ldrb ip, [r1, #3] @ zero_extendqisi2 + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1409 .loc 1 578 76 view .LVU434 + 1410 006e 43EA8C43 orr r3, r3, ip, lsl #18 + 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + 1411 .loc 1 579 63 view .LVU435 + 1412 0072 43EA8253 orr r3, r3, r2, lsl #22 + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1413 .loc 1 578 33 view .LVU436 + 1414 0076 2B43 orrs r3, r3, r5 + 1415 0078 074A ldr r2, .L109 + 1416 .LVL119: + 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)ep->type << 18) | (epnum << 22) | + 1417 .loc 1 578 33 view .LVU437 + 1418 007a 1A43 orrs r2, r2, r3 + 1419 007c C4F80029 str r2, [r4, #2304] + 1420 .LVL120: + 1421 .L104: + ARM GAS /tmp/cc9mtr28.s page 56 + + + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1422 .loc 1 584 5 is_stmt 1 view .LVU438 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1423 .loc 1 584 27 is_stmt 0 view .LVU439 + 1424 0080 D0F83C28 ldr r2, [r0, #2108] + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1425 .loc 1 584 75 view .LVU440 + 1426 0084 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1427 .loc 1 584 81 view .LVU441 + 1428 0086 03F00F01 and r1, r3, #15 + 1429 .LVL121: + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1430 .loc 1 584 54 view .LVU442 + 1431 008a 0123 movs r3, #1 + 1432 008c 8B40 lsls r3, r3, r1 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1433 .loc 1 584 52 view .LVU443 + 1434 008e 9BB2 uxth r3, r3 + 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1435 .loc 1 584 27 view .LVU444 + 1436 0090 1343 orrs r3, r3, r2 + 1437 0092 C0F83C38 str r3, [r0, #2108] + 1438 0096 D9E7 b .L105 + 1439 .L110: + 1440 .align 2 + 1441 .L109: + 1442 0098 00800010 .word 268468224 + 1443 .cfi_endproc + 1444 .LFE152: + 1446 .section .text.USB_DeactivateEndpoint,"ax",%progbits + 1447 .align 1 + 1448 .global USB_DeactivateEndpoint + 1449 .syntax unified + 1450 .thumb + 1451 .thumb_func + 1452 .fpu fpv5-d16 + 1454 USB_DeactivateEndpoint: + 1455 .LVL122: + 1456 .LFB153: + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1457 .loc 1 608 1 is_stmt 1 view -0 + 1458 .cfi_startproc + 1459 @ args = 0, pretend = 0, frame = 0 + 1460 @ frame_needed = 0, uses_anonymous_args = 0 + 1461 @ link register save eliminated. + 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1462 .loc 1 608 1 is_stmt 0 view .LVU446 + 1463 0000 30B4 push {r4, r5} + 1464 .LCFI15: + 1465 .cfi_def_cfa_offset 8 + 1466 .cfi_offset 4, -8 + 1467 .cfi_offset 5, -4 + 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 1468 .loc 1 609 3 is_stmt 1 view .LVU447 + 1469 .LVL123: + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 57 + + + 1470 .loc 1 610 3 view .LVU448 + 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1471 .loc 1 610 32 is_stmt 0 view .LVU449 + 1472 0002 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 1473 .LVL124: + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1474 .loc 1 613 3 is_stmt 1 view .LVU450 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1475 .loc 1 613 9 is_stmt 0 view .LVU451 + 1476 0004 4A78 ldrb r2, [r1, #1] @ zero_extendqisi2 + 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1477 .loc 1 613 6 view .LVU452 + 1478 0006 012A cmp r2, #1 + 1479 0008 26D0 beq .L117 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1480 .loc 1 631 5 is_stmt 1 view .LVU453 + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1481 .loc 1 631 10 is_stmt 0 view .LVU454 + 1482 000a 00EB4313 add r3, r0, r3, lsl #5 + 1483 .LVL125: + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1484 .loc 1 631 27 view .LVU455 + 1485 000e D3F8002B ldr r2, [r3, #2816] + 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1486 .loc 1 631 8 view .LVU456 + 1487 0012 002A cmp r2, #0 + 1488 0014 52DB blt .L118 + 1489 .LVL126: + 1490 .L115: + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1491 .loc 1 637 5 is_stmt 1 view .LVU457 + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1492 .loc 1 637 27 is_stmt 0 view .LVU458 + 1493 0016 D0F83C48 ldr r4, [r0, #2108] + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1494 .loc 1 637 78 view .LVU459 + 1495 001a 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1496 .loc 1 637 84 view .LVU460 + 1497 001c 02F00F02 and r2, r2, #15 + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1498 .loc 1 637 57 view .LVU461 + 1499 0020 4FF0010C mov ip, #1 + 1500 0024 0CFA02F2 lsl r2, ip, r2 + 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1501 .loc 1 637 27 view .LVU462 + 1502 0028 24EA0242 bic r2, r4, r2, lsl #16 + 1503 002c C0F83C28 str r2, [r0, #2108] + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 1504 .loc 1 638 5 is_stmt 1 view .LVU463 + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 1505 .loc 1 638 27 is_stmt 0 view .LVU464 + 1506 0030 D0F81C28 ldr r2, [r0, #2076] + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 1507 .loc 1 638 78 view .LVU465 + 1508 0034 0978 ldrb r1, [r1] @ zero_extendqisi2 + 1509 .LVL127: + ARM GAS /tmp/cc9mtr28.s page 58 + + + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 1510 .loc 1 638 84 view .LVU466 + 1511 0036 01F00F01 and r1, r1, #15 + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 1512 .loc 1 638 57 view .LVU467 + 1513 003a 0CFA01FC lsl ip, ip, r1 + 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + 1514 .loc 1 638 27 view .LVU468 + 1515 003e 22EA0C42 bic r2, r2, ip, lsl #16 + 1516 0042 C0F81C28 str r2, [r0, #2076] + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_MPSIZ | + 1517 .loc 1 639 5 is_stmt 1 view .LVU469 + 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DOEPCTL_MPSIZ | + 1518 .loc 1 639 32 is_stmt 0 view .LVU470 + 1519 0046 D3F8001B ldr r1, [r3, #2816] + 1520 004a 234A ldr r2, .L120 + 1521 004c 0A40 ands r2, r2, r1 + 1522 004e C3F8002B str r2, [r3, #2816] + 1523 .L114: + 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1524 .loc 1 645 3 is_stmt 1 view .LVU471 + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1525 .loc 1 646 1 is_stmt 0 view .LVU472 + 1526 0052 0020 movs r0, #0 + 1527 .LVL128: + 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1528 .loc 1 646 1 view .LVU473 + 1529 0054 30BC pop {r4, r5} + 1530 .LCFI16: + 1531 .cfi_remember_state + 1532 .cfi_restore 5 + 1533 .cfi_restore 4 + 1534 .cfi_def_cfa_offset 0 + 1535 0056 7047 bx lr + 1536 .LVL129: + 1537 .L117: + 1538 .LCFI17: + 1539 .cfi_restore_state + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1540 .loc 1 615 5 is_stmt 1 view .LVU474 + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1541 .loc 1 615 10 is_stmt 0 view .LVU475 + 1542 0058 00EB4313 add r3, r0, r3, lsl #5 + 1543 .LVL130: + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1544 .loc 1 615 26 view .LVU476 + 1545 005c D3F80029 ldr r2, [r3, #2304] + 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1546 .loc 1 615 8 view .LVU477 + 1547 0060 002A cmp r2, #0 + 1548 0062 1EDB blt .L119 + 1549 .LVL131: + 1550 .L113: + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1551 .loc 1 621 5 is_stmt 1 view .LVU478 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1552 .loc 1 621 27 is_stmt 0 view .LVU479 + ARM GAS /tmp/cc9mtr28.s page 59 + + + 1553 0064 D0F83C58 ldr r5, [r0, #2108] + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1554 .loc 1 621 77 view .LVU480 + 1555 0068 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1556 .loc 1 621 83 view .LVU481 + 1557 006a 02F00F02 and r2, r2, #15 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1558 .loc 1 621 56 view .LVU482 + 1559 006e 0124 movs r4, #1 + 1560 0070 04FA02F2 lsl r2, r4, r2 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1561 .loc 1 621 54 view .LVU483 + 1562 0074 92B2 uxth r2, r2 + 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1563 .loc 1 621 27 view .LVU484 + 1564 0076 25EA0202 bic r2, r5, r2 + 1565 007a C0F83C28 str r2, [r0, #2108] + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1566 .loc 1 622 5 is_stmt 1 view .LVU485 + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1567 .loc 1 622 27 is_stmt 0 view .LVU486 + 1568 007e D0F81C28 ldr r2, [r0, #2076] + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1569 .loc 1 622 77 view .LVU487 + 1570 0082 0978 ldrb r1, [r1] @ zero_extendqisi2 + 1571 .LVL132: + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1572 .loc 1 622 83 view .LVU488 + 1573 0084 01F00F01 and r1, r1, #15 + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1574 .loc 1 622 56 view .LVU489 + 1575 0088 8C40 lsls r4, r4, r1 + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1576 .loc 1 622 54 view .LVU490 + 1577 008a A4B2 uxth r4, r4 + 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + 1578 .loc 1 622 27 view .LVU491 + 1579 008c 22EA0404 bic r4, r2, r4 + 1580 0090 C0F81C48 str r4, [r0, #2076] + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_MPSIZ | + 1581 .loc 1 623 5 is_stmt 1 view .LVU492 + 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_DIEPCTL_MPSIZ | + 1582 .loc 1 623 31 is_stmt 0 view .LVU493 + 1583 0094 D3F80019 ldr r1, [r3, #2304] + 1584 0098 104A ldr r2, .L120+4 + 1585 009a 0A40 ands r2, r2, r1 + 1586 009c C3F80029 str r2, [r3, #2304] + 1587 00a0 D7E7 b .L114 + 1588 .LVL133: + 1589 .L119: + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + 1590 .loc 1 617 7 is_stmt 1 view .LVU494 + 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + 1591 .loc 1 617 33 is_stmt 0 view .LVU495 + 1592 00a2 D3F80029 ldr r2, [r3, #2304] + 1593 00a6 42F00062 orr r2, r2, #134217728 + ARM GAS /tmp/cc9mtr28.s page 60 + + + 1594 00aa C3F80029 str r2, [r3, #2304] + 1595 .LVL134: + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1596 .loc 1 618 7 is_stmt 1 view .LVU496 + 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1597 .loc 1 618 33 is_stmt 0 view .LVU497 + 1598 00ae D3F80029 ldr r2, [r3, #2304] + 1599 00b2 42F08042 orr r2, r2, #1073741824 + 1600 00b6 C3F80029 str r2, [r3, #2304] + 1601 00ba D3E7 b .L113 + 1602 .LVL135: + 1603 .L118: + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + 1604 .loc 1 633 7 is_stmt 1 view .LVU498 + 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + 1605 .loc 1 633 34 is_stmt 0 view .LVU499 + 1606 00bc D3F8002B ldr r2, [r3, #2816] + 1607 00c0 42F00062 orr r2, r2, #134217728 + 1608 00c4 C3F8002B str r2, [r3, #2816] + 1609 .LVL136: + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1610 .loc 1 634 7 is_stmt 1 view .LVU500 + 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1611 .loc 1 634 34 is_stmt 0 view .LVU501 + 1612 00c8 D3F8002B ldr r2, [r3, #2816] + 1613 00cc 42F08042 orr r2, r2, #1073741824 + 1614 00d0 C3F8002B str r2, [r3, #2816] + 1615 00d4 9FE7 b .L115 + 1616 .L121: + 1617 00d6 00BF .align 2 + 1618 .L120: + 1619 00d8 0078F3EF .word -269256704 + 1620 00dc 007833EC .word -332171264 + 1621 .cfi_endproc + 1622 .LFE153: + 1624 .section .text.USB_DeactivateDedicatedEndpoint,"ax",%progbits + 1625 .align 1 + 1626 .global USB_DeactivateDedicatedEndpoint + 1627 .syntax unified + 1628 .thumb + 1629 .thumb_func + 1630 .fpu fpv5-d16 + 1632 USB_DeactivateDedicatedEndpoint: + 1633 .LVL137: + 1634 .LFB154: + 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1635 .loc 1 655 1 is_stmt 1 view -0 + 1636 .cfi_startproc + 1637 @ args = 0, pretend = 0, frame = 0 + 1638 @ frame_needed = 0, uses_anonymous_args = 0 + 1639 @ link register save eliminated. + 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 1640 .loc 1 656 3 view .LVU503 + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1641 .loc 1 657 3 view .LVU504 + 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1642 .loc 1 657 32 is_stmt 0 view .LVU505 + ARM GAS /tmp/cc9mtr28.s page 61 + + + 1643 0000 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 1644 .LVL138: + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1645 .loc 1 660 3 is_stmt 1 view .LVU506 + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1646 .loc 1 660 9 is_stmt 0 view .LVU507 + 1647 0002 4A78 ldrb r2, [r1, #1] @ zero_extendqisi2 + 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1648 .loc 1 660 6 view .LVU508 + 1649 0004 012A cmp r2, #1 + 1650 0006 18D0 beq .L127 + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1651 .loc 1 673 5 is_stmt 1 view .LVU509 + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1652 .loc 1 673 10 is_stmt 0 view .LVU510 + 1653 0008 00EB4313 add r3, r0, r3, lsl #5 + 1654 .LVL139: + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1655 .loc 1 673 27 view .LVU511 + 1656 000c D3F8002B ldr r2, [r3, #2816] + 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1657 .loc 1 673 8 view .LVU512 + 1658 0010 002A cmp r2, #0 + 1659 0012 38DB blt .L128 + 1660 .LVL140: + 1661 .L126: + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1662 .loc 1 679 5 is_stmt 1 view .LVU513 + 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) + 1663 .loc 1 679 32 is_stmt 0 view .LVU514 + 1664 0014 D3F8002B ldr r2, [r3, #2816] + 1665 0018 22F40042 bic r2, r2, #32768 + 1666 001c C3F8002B str r2, [r3, #2816] + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1667 .loc 1 680 5 is_stmt 1 view .LVU515 + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1668 .loc 1 680 27 is_stmt 0 view .LVU516 + 1669 0020 D0F81C38 ldr r3, [r0, #2076] + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1670 .loc 1 680 78 view .LVU517 + 1671 0024 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1672 .loc 1 680 84 view .LVU518 + 1673 0026 02F00F01 and r1, r2, #15 + 1674 .LVL141: + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1675 .loc 1 680 57 view .LVU519 + 1676 002a 0122 movs r2, #1 + 1677 002c 8A40 lsls r2, r2, r1 + 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1678 .loc 1 680 27 view .LVU520 + 1679 002e 23EA0243 bic r3, r3, r2, lsl #16 + 1680 0032 C0F81C38 str r3, [r0, #2076] + 1681 .L125: + 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1682 .loc 1 683 3 is_stmt 1 view .LVU521 + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + ARM GAS /tmp/cc9mtr28.s page 62 + + + 1683 .loc 1 684 1 is_stmt 0 view .LVU522 + 1684 0036 0020 movs r0, #0 + 1685 .LVL142: + 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1686 .loc 1 684 1 view .LVU523 + 1687 0038 7047 bx lr + 1688 .LVL143: + 1689 .L127: + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1690 .loc 1 662 5 is_stmt 1 view .LVU524 + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1691 .loc 1 662 10 is_stmt 0 view .LVU525 + 1692 003a 00EB4313 add r3, r0, r3, lsl #5 + 1693 .LVL144: + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1694 .loc 1 662 26 view .LVU526 + 1695 003e D3F80029 ldr r2, [r3, #2304] + 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1696 .loc 1 662 8 view .LVU527 + 1697 0042 002A cmp r2, #0 + 1698 0044 12DB blt .L129 + 1699 .LVL145: + 1700 .L124: + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1701 .loc 1 668 5 is_stmt 1 view .LVU528 + 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + 1702 .loc 1 668 31 is_stmt 0 view .LVU529 + 1703 0046 D3F80029 ldr r2, [r3, #2304] + 1704 004a 22F40042 bic r2, r2, #32768 + 1705 004e C3F80029 str r2, [r3, #2304] + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1706 .loc 1 669 5 is_stmt 1 view .LVU530 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1707 .loc 1 669 27 is_stmt 0 view .LVU531 + 1708 0052 D0F81C28 ldr r2, [r0, #2076] + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1709 .loc 1 669 77 view .LVU532 + 1710 0056 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1711 .loc 1 669 83 view .LVU533 + 1712 0058 03F00F01 and r1, r3, #15 + 1713 .LVL146: + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1714 .loc 1 669 56 view .LVU534 + 1715 005c 0123 movs r3, #1 + 1716 005e 8B40 lsls r3, r3, r1 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1717 .loc 1 669 54 view .LVU535 + 1718 0060 9BB2 uxth r3, r3 + 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1719 .loc 1 669 27 view .LVU536 + 1720 0062 22EA0303 bic r3, r2, r3 + 1721 0066 C0F81C38 str r3, [r0, #2076] + 1722 006a E4E7 b .L125 + 1723 .LVL147: + 1724 .L129: + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + ARM GAS /tmp/cc9mtr28.s page 63 + + + 1725 .loc 1 664 7 is_stmt 1 view .LVU537 + 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + 1726 .loc 1 664 34 is_stmt 0 view .LVU538 + 1727 006c D3F80029 ldr r2, [r3, #2304] + 1728 0070 42F00062 orr r2, r2, #134217728 + 1729 0074 C3F80029 str r2, [r3, #2304] + 1730 .LVL148: + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1731 .loc 1 665 7 is_stmt 1 view .LVU539 + 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1732 .loc 1 665 34 is_stmt 0 view .LVU540 + 1733 0078 D3F80029 ldr r2, [r3, #2304] + 1734 007c 42F08042 orr r2, r2, #1073741824 + 1735 0080 C3F80029 str r2, [r3, #2304] + 1736 0084 DFE7 b .L124 + 1737 .LVL149: + 1738 .L128: + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + 1739 .loc 1 675 7 is_stmt 1 view .LVU541 + 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + 1740 .loc 1 675 35 is_stmt 0 view .LVU542 + 1741 0086 D3F8002B ldr r2, [r3, #2816] + 1742 008a 42F00062 orr r2, r2, #134217728 + 1743 008e C3F8002B str r2, [r3, #2816] + 1744 .LVL150: + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1745 .loc 1 676 7 is_stmt 1 view .LVU543 + 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1746 .loc 1 676 35 is_stmt 0 view .LVU544 + 1747 0092 D3F8002B ldr r2, [r3, #2816] + 1748 0096 42F08042 orr r2, r2, #1073741824 + 1749 009a C3F8002B str r2, [r3, #2816] + 1750 009e B9E7 b .L126 + 1751 .cfi_endproc + 1752 .LFE154: + 1754 .section .text.USB_EP0StartXfer,"ax",%progbits + 1755 .align 1 + 1756 .global USB_EP0StartXfer + 1757 .syntax unified + 1758 .thumb + 1759 .thumb_func + 1760 .fpu fpv5-d16 + 1762 USB_EP0StartXfer: + 1763 .LVL151: + 1764 .LFB156: + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1765 .loc 1 839 1 is_stmt 1 view -0 + 1766 .cfi_startproc + 1767 @ args = 0, pretend = 0, frame = 0 + 1768 @ frame_needed = 0, uses_anonymous_args = 0 + 1769 @ link register save eliminated. + 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 1770 .loc 1 839 1 is_stmt 0 view .LVU546 + 1771 0000 70B4 push {r4, r5, r6} + 1772 .LCFI18: + 1773 .cfi_def_cfa_offset 12 + 1774 .cfi_offset 4, -12 + ARM GAS /tmp/cc9mtr28.s page 64 + + + 1775 .cfi_offset 5, -8 + 1776 .cfi_offset 6, -4 + 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 1777 .loc 1 840 3 is_stmt 1 view .LVU547 + 1778 .LVL152: + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1779 .loc 1 841 3 view .LVU548 + 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1780 .loc 1 841 32 is_stmt 0 view .LVU549 + 1781 0002 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 1782 .LVL153: + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1783 .loc 1 844 3 is_stmt 1 view .LVU550 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1784 .loc 1 844 9 is_stmt 0 view .LVU551 + 1785 0004 4C78 ldrb r4, [r1, #1] @ zero_extendqisi2 + 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1786 .loc 1 844 6 view .LVU552 + 1787 0006 012C cmp r4, #1 + 1788 0008 25D0 beq .L141 + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 1789 .loc 1 899 5 is_stmt 1 view .LVU553 + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 1790 .loc 1 899 33 is_stmt 0 view .LVU554 + 1791 000a 00EB4310 add r0, r0, r3, lsl #5 + 1792 .LVL154: + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 1793 .loc 1 899 33 view .LVU555 + 1794 000e 00F53063 add r3, r0, #2816 + 1795 .LVL155: + 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 1796 .loc 1 899 33 view .LVU556 + 1797 0012 1D69 ldr r5, [r3, #16] + 1798 0014 3F4C ldr r4, .L144 + 1799 0016 2C40 ands r4, r4, r5 + 1800 0018 1C61 str r4, [r3, #16] + 1801 .LVL156: + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1802 .loc 1 900 5 is_stmt 1 view .LVU557 + 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1803 .loc 1 900 33 is_stmt 0 view .LVU558 + 1804 001a 1D69 ldr r5, [r3, #16] + 1805 001c 3E4C ldr r4, .L144+4 + 1806 001e 2C40 ands r4, r4, r5 + 1807 0020 1C61 str r4, [r3, #16] + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1808 .loc 1 902 5 is_stmt 1 view .LVU559 + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1809 .loc 1 902 11 is_stmt 0 view .LVU560 + 1810 0022 4C69 ldr r4, [r1, #20] + 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1811 .loc 1 902 8 view .LVU561 + 1812 0024 0CB1 cbz r4, .L138 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1813 .loc 1 904 7 is_stmt 1 view .LVU562 + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1814 .loc 1 904 24 is_stmt 0 view .LVU563 + ARM GAS /tmp/cc9mtr28.s page 65 + + + 1815 0026 8C68 ldr r4, [r1, #8] + 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1816 .loc 1 904 20 view .LVU564 + 1817 0028 4C61 str r4, [r1, #20] + 1818 .L138: + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + 1819 .loc 1 907 5 is_stmt 1 view .LVU565 + 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + 1820 .loc 1 907 33 is_stmt 0 view .LVU566 + 1821 002a 1C69 ldr r4, [r3, #16] + 1822 002c 44F40024 orr r4, r4, #524288 + 1823 0030 1C61 str r4, [r3, #16] + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1824 .loc 1 908 5 is_stmt 1 view .LVU567 + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1825 .loc 1 908 33 is_stmt 0 view .LVU568 + 1826 0032 1C69 ldr r4, [r3, #16] + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1827 .loc 1 908 61 view .LVU569 + 1828 0034 8D68 ldr r5, [r1, #8] + 1829 0036 C5F3120C ubfx ip, r5, #0, #19 + 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1830 .loc 1 908 33 view .LVU570 + 1831 003a 44EA0C04 orr r4, r4, ip + 1832 003e 1C61 str r4, [r3, #16] + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1833 .loc 1 910 5 is_stmt 1 view .LVU571 + 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1834 .loc 1 910 8 is_stmt 0 view .LVU572 + 1835 0040 012A cmp r2, #1 + 1836 0042 62D0 beq .L142 + 1837 .LVL157: + 1838 .L139: + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1839 .loc 1 919 5 is_stmt 1 view .LVU573 + 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1840 .loc 1 919 32 is_stmt 0 view .LVU574 + 1841 0044 D0F8003B ldr r3, [r0, #2816] + 1842 0048 43F00443 orr r3, r3, #-2080374784 + 1843 004c C0F8003B str r3, [r0, #2816] + 1844 .LVL158: + 1845 .L137: + 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1846 .loc 1 922 3 is_stmt 1 view .LVU575 + 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1847 .loc 1 923 1 is_stmt 0 view .LVU576 + 1848 0050 0020 movs r0, #0 + 1849 0052 70BC pop {r4, r5, r6} + 1850 .LCFI19: + 1851 .cfi_remember_state + 1852 .cfi_restore 6 + 1853 .cfi_restore 5 + 1854 .cfi_restore 4 + 1855 .cfi_def_cfa_offset 0 + 1856 0054 7047 bx lr + 1857 .LVL159: + 1858 .L141: + ARM GAS /tmp/cc9mtr28.s page 66 + + + 1859 .LCFI20: + 1860 .cfi_restore_state + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1861 .loc 1 847 5 is_stmt 1 view .LVU577 + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1862 .loc 1 847 11 is_stmt 0 view .LVU578 + 1863 0056 4C69 ldr r4, [r1, #20] + 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1864 .loc 1 847 8 view .LVU579 + 1865 0058 5CBB cbnz r4, .L132 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 1866 .loc 1 849 7 is_stmt 1 view .LVU580 + 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 1867 .loc 1 849 34 is_stmt 0 view .LVU581 + 1868 005a 00EB4314 add r4, r0, r3, lsl #5 + 1869 005e D4F81069 ldr r6, [r4, #2320] + 1870 0062 2D4D ldr r5, .L144+4 + 1871 0064 3540 ands r5, r5, r6 + 1872 0066 C4F81059 str r5, [r4, #2320] + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 1873 .loc 1 850 7 is_stmt 1 view .LVU582 + 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 1874 .loc 1 850 34 is_stmt 0 view .LVU583 + 1875 006a D4F81059 ldr r5, [r4, #2320] + 1876 006e 45F40025 orr r5, r5, #524288 + 1877 0072 C4F81059 str r5, [r4, #2320] + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1878 .loc 1 851 7 is_stmt 1 view .LVU584 + 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1879 .loc 1 851 34 is_stmt 0 view .LVU585 + 1880 0076 D4F81069 ldr r6, [r4, #2320] + 1881 007a 264D ldr r5, .L144 + 1882 007c 3540 ands r5, r5, r6 + 1883 007e C4F81059 str r5, [r4, #2320] + 1884 .L133: + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1885 .loc 1 871 5 is_stmt 1 view .LVU586 + 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1886 .loc 1 871 8 is_stmt 0 view .LVU587 + 1887 0082 012A cmp r2, #1 + 1888 0084 32D0 beq .L143 + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1889 .loc 1 884 7 is_stmt 1 view .LVU588 + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1890 .loc 1 884 33 is_stmt 0 view .LVU589 + 1891 0086 00EB4313 add r3, r0, r3, lsl #5 + 1892 .LVL160: + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1893 .loc 1 884 33 view .LVU590 + 1894 008a D3F80029 ldr r2, [r3, #2304] + 1895 .LVL161: + 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1896 .loc 1 884 33 view .LVU591 + 1897 008e 42F00442 orr r2, r2, #-2080374784 + 1898 0092 C3F80029 str r2, [r3, #2304] + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1899 .loc 1 887 7 is_stmt 1 view .LVU592 + ARM GAS /tmp/cc9mtr28.s page 67 + + + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1900 .loc 1 887 13 is_stmt 0 view .LVU593 + 1901 0096 4B69 ldr r3, [r1, #20] + 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1902 .loc 1 887 10 view .LVU594 + 1903 0098 002B cmp r3, #0 + 1904 009a D9D0 beq .L137 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1905 .loc 1 889 9 is_stmt 1 view .LVU595 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1906 .loc 1 889 33 is_stmt 0 view .LVU596 + 1907 009c D0F83438 ldr r3, [r0, #2100] + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1908 .loc 1 889 46 view .LVU597 + 1909 00a0 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1910 .loc 1 889 52 view .LVU598 + 1911 00a2 02F00F01 and r1, r2, #15 + 1912 .LVL162: + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1913 .loc 1 889 40 view .LVU599 + 1914 00a6 0122 movs r2, #1 + 1915 00a8 8A40 lsls r2, r2, r1 + 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1916 .loc 1 889 33 view .LVU600 + 1917 00aa 1343 orrs r3, r3, r2 + 1918 00ac C0F83438 str r3, [r0, #2100] + 1919 00b0 CEE7 b .L137 + 1920 .LVL163: + 1921 .L132: + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 1922 .loc 1 860 7 is_stmt 1 view .LVU601 + 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 1923 .loc 1 860 34 is_stmt 0 view .LVU602 + 1924 00b2 00EB4314 add r4, r0, r3, lsl #5 + 1925 00b6 04F51064 add r4, r4, #2304 + 1926 00ba 2669 ldr r6, [r4, #16] + 1927 00bc 154D ldr r5, .L144 + 1928 00be 3540 ands r5, r5, r6 + 1929 00c0 2561 str r5, [r4, #16] + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1930 .loc 1 861 7 is_stmt 1 view .LVU603 + 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 1931 .loc 1 861 34 is_stmt 0 view .LVU604 + 1932 00c2 2669 ldr r6, [r4, #16] + 1933 00c4 144D ldr r5, .L144+4 + 1934 00c6 3540 ands r5, r5, r6 + 1935 00c8 2561 str r5, [r4, #16] + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1936 .loc 1 863 7 is_stmt 1 view .LVU605 + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1937 .loc 1 863 28 is_stmt 0 view .LVU606 + 1938 00ca 8D68 ldr r5, [r1, #8] + 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1939 .loc 1 863 10 view .LVU607 + 1940 00cc 4E69 ldr r6, [r1, #20] + 1941 00ce AE42 cmp r6, r5 + ARM GAS /tmp/cc9mtr28.s page 68 + + + 1942 00d0 00D9 bls .L134 + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1943 .loc 1 865 9 is_stmt 1 view .LVU608 + 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1944 .loc 1 865 22 is_stmt 0 view .LVU609 + 1945 00d2 4D61 str r5, [r1, #20] + 1946 .L134: + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 1947 .loc 1 867 7 is_stmt 1 view .LVU610 + 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 1948 .loc 1 867 34 is_stmt 0 view .LVU611 + 1949 00d4 2569 ldr r5, [r4, #16] + 1950 00d6 45F40025 orr r5, r5, #524288 + 1951 00da 2561 str r5, [r4, #16] + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1952 .loc 1 868 7 is_stmt 1 view .LVU612 + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1953 .loc 1 868 34 is_stmt 0 view .LVU613 + 1954 00dc 2569 ldr r5, [r4, #16] + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1955 .loc 1 868 62 view .LVU614 + 1956 00de 4E69 ldr r6, [r1, #20] + 1957 00e0 C6F3120C ubfx ip, r6, #0, #19 + 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1958 .loc 1 868 34 view .LVU615 + 1959 00e4 45EA0C05 orr r5, r5, ip + 1960 00e8 2561 str r5, [r4, #16] + 1961 00ea CAE7 b .L133 + 1962 .L143: + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1963 .loc 1 873 7 is_stmt 1 view .LVU616 + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1964 .loc 1 873 23 is_stmt 0 view .LVU617 + 1965 00ec 0A69 ldr r2, [r1, #16] + 1966 .LVL164: + 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1967 .loc 1 873 10 view .LVU618 + 1968 00ee 1AB1 cbz r2, .L136 + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1969 .loc 1 875 9 is_stmt 1 view .LVU619 + 1970 00f0 00EB4311 add r1, r0, r3, lsl #5 + 1971 .LVL165: + 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1972 .loc 1 875 35 is_stmt 0 view .LVU620 + 1973 00f4 C1F81429 str r2, [r1, #2324] + 1974 .L136: + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1975 .loc 1 879 7 is_stmt 1 view .LVU621 + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1976 .loc 1 879 33 is_stmt 0 view .LVU622 + 1977 00f8 00EB4310 add r0, r0, r3, lsl #5 + 1978 .LVL166: + 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1979 .loc 1 879 33 view .LVU623 + 1980 00fc D0F80029 ldr r2, [r0, #2304] + 1981 0100 42F00442 orr r2, r2, #-2080374784 + 1982 0104 C0F80029 str r2, [r0, #2304] + ARM GAS /tmp/cc9mtr28.s page 69 + + + 1983 0108 A2E7 b .L137 + 1984 .LVL167: + 1985 .L142: + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1986 .loc 1 912 7 is_stmt 1 view .LVU624 + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1987 .loc 1 912 23 is_stmt 0 view .LVU625 + 1988 010a CA68 ldr r2, [r1, #12] + 1989 .LVL168: + 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 1990 .loc 1 912 10 view .LVU626 + 1991 010c 002A cmp r2, #0 + 1992 010e 99D0 beq .L139 + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1993 .loc 1 914 9 is_stmt 1 view .LVU627 + 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 1994 .loc 1 914 36 is_stmt 0 view .LVU628 + 1995 0110 5A61 str r2, [r3, #20] + 1996 0112 97E7 b .L139 + 1997 .L145: + 1998 .align 2 + 1999 .L144: + 2000 0114 0000F8FF .word -524288 + 2001 0118 FFFF07E0 .word -536346625 + 2002 .cfi_endproc + 2003 .LFE156: + 2005 .section .text.USB_WritePacket,"ax",%progbits + 2006 .align 1 + 2007 .global USB_WritePacket + 2008 .syntax unified + 2009 .thumb + 2010 .thumb_func + 2011 .fpu fpv5-d16 + 2013 USB_WritePacket: + 2014 .LVL169: + 2015 .LFB157: + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2016 .loc 1 939 1 is_stmt 1 view -0 + 2017 .cfi_startproc + 2018 @ args = 4, pretend = 0, frame = 0 + 2019 @ frame_needed = 0, uses_anonymous_args = 0 + 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2020 .loc 1 939 1 is_stmt 0 view .LVU630 + 2021 0000 10B5 push {r4, lr} + 2022 .LCFI21: + 2023 .cfi_def_cfa_offset 8 + 2024 .cfi_offset 4, -8 + 2025 .cfi_offset 14, -4 + 2026 0002 9DF80840 ldrb r4, [sp, #8] @ zero_extendqisi2 + 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t *pSrc = (uint32_t *)src; + 2027 .loc 1 940 3 is_stmt 1 view .LVU631 + 2028 .LVL170: + 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count32b, i; + 2029 .loc 1 941 3 view .LVU632 + 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2030 .loc 1 942 3 view .LVU633 + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 70 + + + 2031 .loc 1 944 3 view .LVU634 + 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2032 .loc 1 944 6 is_stmt 0 view .LVU635 + 2033 0006 84B9 cbnz r4, .L147 + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < count32b; i++) + 2034 .loc 1 946 5 is_stmt 1 view .LVU636 + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < count32b; i++) + 2035 .loc 1 946 31 is_stmt 0 view .LVU637 + 2036 0008 0333 adds r3, r3, #3 + 2037 .LVL171: + 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < count32b; i++) + 2038 .loc 1 946 14 view .LVU638 + 2039 000a 4FEA930E lsr lr, r3, #2 + 2040 .LVL172: + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2041 .loc 1 947 5 is_stmt 1 view .LVU639 + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2042 .loc 1 947 12 is_stmt 0 view .LVU640 + 2043 000e 4FF0000C mov ip, #0 + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2044 .loc 1 947 5 view .LVU641 + 2045 0012 08E0 b .L148 + 2046 .LVL173: + 2047 .L149: + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pSrc++; + 2048 .loc 1 949 7 is_stmt 1 discriminator 3 view .LVU642 + 2049 0014 00EB0233 add r3, r0, r2, lsl #12 + 2050 0018 03F58053 add r3, r3, #4096 + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pSrc++; + 2051 .loc 1 949 41 is_stmt 0 discriminator 3 view .LVU643 + 2052 001c 51F8044B ldr r4, [r1], #4 @ unaligned + 2053 .LVL174: + 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pSrc++; + 2054 .loc 1 949 39 discriminator 3 view .LVU644 + 2055 0020 1C60 str r4, [r3] + 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2056 .loc 1 950 7 is_stmt 1 discriminator 3 view .LVU645 + 2057 .LVL175: + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2058 .loc 1 947 32 discriminator 3 view .LVU646 + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2059 .loc 1 947 33 is_stmt 0 discriminator 3 view .LVU647 + 2060 0022 0CF1010C add ip, ip, #1 + 2061 .LVL176: + 2062 .L148: + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2063 .loc 1 947 18 is_stmt 1 discriminator 1 view .LVU648 + 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2064 .loc 1 947 5 is_stmt 0 discriminator 1 view .LVU649 + 2065 0026 F445 cmp ip, lr + 2066 0028 F4D3 bcc .L149 + 2067 .LVL177: + 2068 .L147: + 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2069 .loc 1 954 3 is_stmt 1 view .LVU650 + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2070 .loc 1 955 1 is_stmt 0 view .LVU651 + ARM GAS /tmp/cc9mtr28.s page 71 + + + 2071 002a 0020 movs r0, #0 + 2072 .LVL178: + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2073 .loc 1 955 1 view .LVU652 + 2074 002c 10BD pop {r4, pc} + 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2075 .loc 1 955 1 view .LVU653 + 2076 .cfi_endproc + 2077 .LFE157: + 2079 .section .text.USB_EPStartXfer,"ax",%progbits + 2080 .align 1 + 2081 .global USB_EPStartXfer + 2082 .syntax unified + 2083 .thumb + 2084 .thumb_func + 2085 .fpu fpv5-d16 + 2087 USB_EPStartXfer: + 2088 .LVL179: + 2089 .LFB155: + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2090 .loc 1 697 1 is_stmt 1 view -0 + 2091 .cfi_startproc + 2092 @ args = 0, pretend = 0, frame = 0 + 2093 @ frame_needed = 0, uses_anonymous_args = 0 + 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2094 .loc 1 697 1 is_stmt 0 view .LVU655 + 2095 0000 F0B5 push {r4, r5, r6, r7, lr} + 2096 .LCFI22: + 2097 .cfi_def_cfa_offset 20 + 2098 .cfi_offset 4, -20 + 2099 .cfi_offset 5, -16 + 2100 .cfi_offset 6, -12 + 2101 .cfi_offset 7, -8 + 2102 .cfi_offset 14, -4 + 2103 0002 83B0 sub sp, sp, #12 + 2104 .LCFI23: + 2105 .cfi_def_cfa_offset 32 + 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 2106 .loc 1 698 3 is_stmt 1 view .LVU656 + 2107 .LVL180: + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t pktcnt; + 2108 .loc 1 699 3 view .LVU657 + 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t pktcnt; + 2109 .loc 1 699 32 is_stmt 0 view .LVU658 + 2110 0004 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 2111 .LVL181: + 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2112 .loc 1 700 3 is_stmt 1 view .LVU659 + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2113 .loc 1 703 3 view .LVU660 + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2114 .loc 1 703 9 is_stmt 0 view .LVU661 + 2115 0006 4C78 ldrb r4, [r1, #1] @ zero_extendqisi2 + 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2116 .loc 1 703 6 view .LVU662 + 2117 0008 012C cmp r4, #1 + 2118 000a 31D0 beq .L169 + ARM GAS /tmp/cc9mtr28.s page 72 + + + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 2119 .loc 1 787 5 is_stmt 1 view .LVU663 + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 2120 .loc 1 787 33 is_stmt 0 view .LVU664 + 2121 000c 00EB4313 add r3, r0, r3, lsl #5 + 2122 .LVL182: + 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + 2123 .loc 1 787 33 view .LVU665 + 2124 0010 03F5306C add ip, r3, #2816 + 2125 0014 DCF81050 ldr r5, [ip, #16] + 2126 0018 834C ldr r4, .L174 + 2127 001a 2C40 ands r4, r4, r5 + 2128 001c CCF81040 str r4, [ip, #16] + 2129 .LVL183: + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2130 .loc 1 788 5 is_stmt 1 view .LVU666 + 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2131 .loc 1 788 33 is_stmt 0 view .LVU667 + 2132 0020 DCF81050 ldr r5, [ip, #16] + 2133 0024 814C ldr r4, .L174+4 + 2134 0026 2C40 ands r4, r4, r5 + 2135 0028 CCF81040 str r4, [ip, #16] + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2136 .loc 1 790 5 is_stmt 1 view .LVU668 + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2137 .loc 1 790 11 is_stmt 0 view .LVU669 + 2138 002c 4C69 ldr r4, [r1, #20] + 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2139 .loc 1 790 8 view .LVU670 + 2140 002e 002C cmp r4, #0 + 2141 0030 40F0C680 bne .L163 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 2142 .loc 1 792 7 is_stmt 1 view .LVU671 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 2143 .loc 1 792 35 is_stmt 0 view .LVU672 + 2144 0034 DCF81040 ldr r4, [ip, #16] + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 2145 .loc 1 792 67 view .LVU673 + 2146 0038 8D68 ldr r5, [r1, #8] + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 2147 .loc 1 792 63 view .LVU674 + 2148 003a C5F31205 ubfx r5, r5, #0, #19 + 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 2149 .loc 1 792 35 view .LVU675 + 2150 003e 2C43 orrs r4, r4, r5 + 2151 0040 CCF81040 str r4, [ip, #16] + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2152 .loc 1 793 7 is_stmt 1 view .LVU676 + 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2153 .loc 1 793 35 is_stmt 0 view .LVU677 + 2154 0044 DCF81040 ldr r4, [ip, #16] + 2155 0048 44F40024 orr r4, r4, #524288 + 2156 004c CCF81040 str r4, [ip, #16] + 2157 .L164: + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2158 .loc 1 802 5 is_stmt 1 view .LVU678 + 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 73 + + + 2159 .loc 1 802 8 is_stmt 0 view .LVU679 + 2160 0050 012A cmp r2, #1 + 2161 0052 00F0CF80 beq .L170 + 2162 .LVL184: + 2163 .L165: + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2164 .loc 1 810 5 is_stmt 1 view .LVU680 + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2165 .loc 1 810 11 is_stmt 0 view .LVU681 + 2166 0056 CA78 ldrb r2, [r1, #3] @ zero_extendqisi2 + 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2167 .loc 1 810 8 view .LVU682 + 2168 0058 012A cmp r2, #1 + 2169 005a 00F0D280 beq .L171 + 2170 .L166: + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2171 .loc 1 822 5 is_stmt 1 view .LVU683 + 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2172 .loc 1 822 32 is_stmt 0 view .LVU684 + 2173 005e D3F8002B ldr r2, [r3, #2816] + 2174 0062 42F00442 orr r2, r2, #-2080374784 + 2175 0066 C3F8002B str r2, [r3, #2816] + 2176 .LVL185: + 2177 .L159: + 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2178 .loc 1 825 3 is_stmt 1 view .LVU685 + 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2179 .loc 1 826 1 is_stmt 0 view .LVU686 + 2180 006a 0020 movs r0, #0 + 2181 006c 03B0 add sp, sp, #12 + 2182 .LCFI24: + 2183 .cfi_remember_state + 2184 .cfi_def_cfa_offset 20 + 2185 @ sp needed + 2186 006e F0BD pop {r4, r5, r6, r7, pc} + 2187 .LVL186: + 2188 .L169: + 2189 .LCFI25: + 2190 .cfi_restore_state + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2191 .loc 1 706 5 is_stmt 1 view .LVU687 + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2192 .loc 1 706 11 is_stmt 0 view .LVU688 + 2193 0070 4C69 ldr r4, [r1, #20] + 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2194 .loc 1 706 8 view .LVU689 + 2195 0072 74BB cbnz r4, .L153 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 2196 .loc 1 708 7 is_stmt 1 view .LVU690 + 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + 2197 .loc 1 708 34 is_stmt 0 view .LVU691 + 2198 0074 00EB4314 add r4, r0, r3, lsl #5 + 2199 0078 D4F81069 ldr r6, [r4, #2320] + 2200 007c 6B4D ldr r5, .L174+4 + 2201 007e 3540 ands r5, r5, r6 + 2202 0080 C4F81059 str r5, [r4, #2320] + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + ARM GAS /tmp/cc9mtr28.s page 74 + + + 2203 .loc 1 709 7 is_stmt 1 view .LVU692 + 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + 2204 .loc 1 709 34 is_stmt 0 view .LVU693 + 2205 0084 D4F81059 ldr r5, [r4, #2320] + 2206 0088 45F40025 orr r5, r5, #524288 + 2207 008c C4F81059 str r5, [r4, #2320] + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2208 .loc 1 710 7 is_stmt 1 view .LVU694 + 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2209 .loc 1 710 34 is_stmt 0 view .LVU695 + 2210 0090 D4F81069 ldr r6, [r4, #2320] + 2211 0094 644D ldr r5, .L174 + 2212 0096 3540 ands r5, r5, r6 + 2213 0098 C4F81059 str r5, [r4, #2320] + 2214 .L154: + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2215 .loc 1 731 5 is_stmt 1 view .LVU696 + 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2216 .loc 1 731 8 is_stmt 0 view .LVU697 + 2217 009c 012A cmp r2, #1 + 2218 009e 4DD0 beq .L172 + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2219 .loc 1 756 7 is_stmt 1 view .LVU698 + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2220 .loc 1 756 33 is_stmt 0 view .LVU699 + 2221 00a0 00EB4313 add r3, r0, r3, lsl #5 + 2222 .LVL187: + 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2223 .loc 1 756 33 view .LVU700 + 2224 00a4 D3F80049 ldr r4, [r3, #2304] + 2225 00a8 44F00444 orr r4, r4, #-2080374784 + 2226 00ac C3F80049 str r4, [r3, #2304] + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2227 .loc 1 758 7 is_stmt 1 view .LVU701 + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2228 .loc 1 758 13 is_stmt 0 view .LVU702 + 2229 00b0 CC78 ldrb r4, [r1, #3] @ zero_extendqisi2 + 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2230 .loc 1 758 10 view .LVU703 + 2231 00b2 012C cmp r4, #1 + 2232 00b4 6BD0 beq .L160 + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2233 .loc 1 761 9 is_stmt 1 view .LVU704 + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2234 .loc 1 761 15 is_stmt 0 view .LVU705 + 2235 00b6 4B69 ldr r3, [r1, #20] + 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2236 .loc 1 761 12 view .LVU706 + 2237 00b8 002B cmp r3, #0 + 2238 00ba D6D0 beq .L159 + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2239 .loc 1 763 11 is_stmt 1 view .LVU707 + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2240 .loc 1 763 35 is_stmt 0 view .LVU708 + 2241 00bc D0F83438 ldr r3, [r0, #2100] + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2242 .loc 1 763 48 view .LVU709 + ARM GAS /tmp/cc9mtr28.s page 75 + + + 2243 00c0 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 2244 .LVL188: + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2245 .loc 1 763 54 view .LVU710 + 2246 00c2 02F00F01 and r1, r2, #15 + 2247 .LVL189: + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2248 .loc 1 763 42 view .LVU711 + 2249 00c6 0122 movs r2, #1 + 2250 00c8 8A40 lsls r2, r2, r1 + 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2251 .loc 1 763 35 view .LVU712 + 2252 00ca 1343 orrs r3, r3, r2 + 2253 00cc C0F83438 str r3, [r0, #2100] + 2254 00d0 CBE7 b .L159 + 2255 .LVL190: + 2256 .L153: + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 2257 .loc 1 719 7 is_stmt 1 view .LVU713 + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 2258 .loc 1 719 34 is_stmt 0 view .LVU714 + 2259 00d2 00EB4314 add r4, r0, r3, lsl #5 + 2260 00d6 D4F81069 ldr r6, [r4, #2320] + 2261 00da 534D ldr r5, .L174 + 2262 00dc 3540 ands r5, r5, r6 + 2263 00de C4F81059 str r5, [r4, #2320] + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U + 2264 .loc 1 720 7 is_stmt 1 view .LVU715 + 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U + 2265 .loc 1 720 34 is_stmt 0 view .LVU716 + 2266 00e2 D4F81069 ldr r6, [r4, #2320] + 2267 00e6 514D ldr r5, .L174+4 + 2268 00e8 3540 ands r5, r5, r6 + 2269 00ea C4F81059 str r5, [r4, #2320] + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2270 .loc 1 721 7 is_stmt 1 view .LVU717 + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2271 .loc 1 721 34 is_stmt 0 view .LVU718 + 2272 00ee D4F81059 ldr r5, [r4, #2320] + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2273 .loc 1 721 84 view .LVU719 + 2274 00f2 8E68 ldr r6, [r1, #8] + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2275 .loc 1 721 80 view .LVU720 + 2276 00f4 4F69 ldr r7, [r1, #20] + 2277 00f6 07EB060C add ip, r7, r6 + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2278 .loc 1 721 96 view .LVU721 + 2279 00fa 0CF1FF3C add ip, ip, #-1 + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2280 .loc 1 721 102 view .LVU722 + 2281 00fe BCFBF6FC udiv ip, ip, r6 + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + 2282 .loc 1 721 62 view .LVU723 + 2283 0102 4B4E ldr r6, .L174+8 + 2284 0104 06EACC4C and ip, r6, ip, lsl #19 + 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + ARM GAS /tmp/cc9mtr28.s page 76 + + + 2285 .loc 1 721 34 view .LVU724 + 2286 0108 45EA0C05 orr r5, r5, ip + 2287 010c C4F81059 str r5, [r4, #2320] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2288 .loc 1 722 7 is_stmt 1 view .LVU725 + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2289 .loc 1 722 34 is_stmt 0 view .LVU726 + 2290 0110 D4F81059 ldr r5, [r4, #2320] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2291 .loc 1 722 66 view .LVU727 + 2292 0114 4E69 ldr r6, [r1, #20] + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2293 .loc 1 722 62 view .LVU728 + 2294 0116 C6F31206 ubfx r6, r6, #0, #19 + 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2295 .loc 1 722 34 view .LVU729 + 2296 011a 3543 orrs r5, r5, r6 + 2297 011c C4F81059 str r5, [r4, #2320] + 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + 2298 .loc 1 719 34 view .LVU730 + 2299 0120 04F51064 add r4, r4, #2304 + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2300 .loc 1 724 7 is_stmt 1 view .LVU731 + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2301 .loc 1 724 13 is_stmt 0 view .LVU732 + 2302 0124 CD78 ldrb r5, [r1, #3] @ zero_extendqisi2 + 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2303 .loc 1 724 10 view .LVU733 + 2304 0126 012D cmp r5, #1 + 2305 0128 B8D1 bne .L154 + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + 2306 .loc 1 726 9 is_stmt 1 view .LVU734 + 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + 2307 .loc 1 726 36 is_stmt 0 view .LVU735 + 2308 012a 2569 ldr r5, [r4, #16] + 2309 012c 25F0C045 bic r5, r5, #1610612736 + 2310 0130 2561 str r5, [r4, #16] + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2311 .loc 1 727 9 is_stmt 1 view .LVU736 + 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2312 .loc 1 727 36 is_stmt 0 view .LVU737 + 2313 0132 2569 ldr r5, [r4, #16] + 2314 0134 45F00055 orr r5, r5, #536870912 + 2315 0138 2561 str r5, [r4, #16] + 2316 013a AFE7 b .L154 + 2317 .L172: + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2318 .loc 1 733 7 is_stmt 1 view .LVU738 + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2319 .loc 1 733 23 is_stmt 0 view .LVU739 + 2320 013c 0A69 ldr r2, [r1, #16] + 2321 .LVL191: + 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2322 .loc 1 733 10 view .LVU740 + 2323 013e 1AB1 cbz r2, .L156 + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2324 .loc 1 735 9 is_stmt 1 view .LVU741 + ARM GAS /tmp/cc9mtr28.s page 77 + + + 2325 0140 00EB4314 add r4, r0, r3, lsl #5 + 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2326 .loc 1 735 35 is_stmt 0 view .LVU742 + 2327 0144 C4F81429 str r2, [r4, #2324] + 2328 .L156: + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2329 .loc 1 738 7 is_stmt 1 view .LVU743 + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2330 .loc 1 738 13 is_stmt 0 view .LVU744 + 2331 0148 CA78 ldrb r2, [r1, #3] @ zero_extendqisi2 + 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2332 .loc 1 738 10 view .LVU745 + 2333 014a 012A cmp r2, #1 + 2334 014c 08D0 beq .L173 + 2335 .LVL192: + 2336 .L157: + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2337 .loc 1 751 7 is_stmt 1 view .LVU746 + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2338 .loc 1 751 33 is_stmt 0 view .LVU747 + 2339 014e 00EB4313 add r3, r0, r3, lsl #5 + 2340 .LVL193: + 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2341 .loc 1 751 33 view .LVU748 + 2342 0152 D3F80029 ldr r2, [r3, #2304] + 2343 0156 42F00442 orr r2, r2, #-2080374784 + 2344 015a C3F80029 str r2, [r3, #2304] + 2345 015e 84E7 b .L159 + 2346 .LVL194: + 2347 .L173: + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2348 .loc 1 740 9 is_stmt 1 view .LVU749 + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2349 .loc 1 740 25 is_stmt 0 view .LVU750 + 2350 0160 D0F80828 ldr r2, [r0, #2056] + 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2351 .loc 1 740 12 view .LVU751 + 2352 0164 12F4807F tst r2, #256 + 2353 0168 08D1 bne .L158 + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2354 .loc 1 742 11 is_stmt 1 view .LVU752 + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2355 .loc 1 742 37 is_stmt 0 view .LVU753 + 2356 016a 00EB4311 add r1, r0, r3, lsl #5 + 2357 .LVL195: + 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2358 .loc 1 742 37 view .LVU754 + 2359 016e D1F80029 ldr r2, [r1, #2304] + 2360 0172 42F00052 orr r2, r2, #536870912 + 2361 0176 C1F80029 str r2, [r1, #2304] + 2362 017a E8E7 b .L157 + 2363 .LVL196: + 2364 .L158: + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2365 .loc 1 746 11 is_stmt 1 view .LVU755 + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2366 .loc 1 746 37 is_stmt 0 view .LVU756 + ARM GAS /tmp/cc9mtr28.s page 78 + + + 2367 017c 00EB4311 add r1, r0, r3, lsl #5 + 2368 .LVL197: + 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2369 .loc 1 746 37 view .LVU757 + 2370 0180 D1F80029 ldr r2, [r1, #2304] + 2371 0184 42F08052 orr r2, r2, #268435456 + 2372 0188 C1F80029 str r2, [r1, #2304] + 2373 018c DFE7 b .L157 + 2374 .LVL198: + 2375 .L160: + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2376 .loc 1 768 9 is_stmt 1 view .LVU758 + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2377 .loc 1 768 25 is_stmt 0 view .LVU759 + 2378 018e D0F80848 ldr r4, [r0, #2056] + 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2379 .loc 1 768 12 view .LVU760 + 2380 0192 14F4807F tst r4, #256 + 2381 0196 0CD1 bne .L161 + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2382 .loc 1 770 11 is_stmt 1 view .LVU761 + 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2383 .loc 1 770 37 is_stmt 0 view .LVU762 + 2384 0198 D3F80049 ldr r4, [r3, #2304] + 2385 019c 44F00054 orr r4, r4, #536870912 + 2386 01a0 C3F80049 str r4, [r3, #2304] + 2387 .L162: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2388 .loc 1 777 9 is_stmt 1 view .LVU763 + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2389 .loc 1 777 15 is_stmt 0 view .LVU764 + 2390 01a4 0092 str r2, [sp] + 2391 01a6 8B8A ldrh r3, [r1, #20] + 2392 01a8 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 2393 .LVL199: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2394 .loc 1 777 15 view .LVU765 + 2395 01aa C968 ldr r1, [r1, #12] + 2396 .LVL200: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2397 .loc 1 777 15 view .LVU766 + 2398 01ac FFF7FEFF bl USB_WritePacket + 2399 .LVL201: + 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2400 .loc 1 777 15 view .LVU767 + 2401 01b0 5BE7 b .L159 + 2402 .LVL202: + 2403 .L161: + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2404 .loc 1 774 11 is_stmt 1 view .LVU768 + 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2405 .loc 1 774 37 is_stmt 0 view .LVU769 + 2406 01b2 D3F80049 ldr r4, [r3, #2304] + 2407 01b6 44F08054 orr r4, r4, #268435456 + 2408 01ba C3F80049 str r4, [r3, #2304] + 2409 01be F1E7 b .L162 + 2410 .L163: + ARM GAS /tmp/cc9mtr28.s page 79 + + + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + 2411 .loc 1 797 7 is_stmt 1 view .LVU770 + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + 2412 .loc 1 797 45 is_stmt 0 view .LVU771 + 2413 01c0 8D68 ldr r5, [r1, #8] + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + 2414 .loc 1 797 41 view .LVU772 + 2415 01c2 2C44 add r4, r4, r5 + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + 2416 .loc 1 797 57 view .LVU773 + 2417 01c4 013C subs r4, r4, #1 + 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + 2418 .loc 1 797 63 view .LVU774 + 2419 01c6 B4FBF5F4 udiv r4, r4, r5 + 2420 .LVL203: + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + 2421 .loc 1 798 7 is_stmt 1 view .LVU775 + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + 2422 .loc 1 798 35 is_stmt 0 view .LVU776 + 2423 01ca DCF81050 ldr r5, [ip, #16] + 2424 01ce 1FFA84FE uxth lr, r4 + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + 2425 .loc 1 798 62 view .LVU777 + 2426 01d2 174E ldr r6, .L174+8 + 2427 01d4 06EAC444 and r4, r6, r4, lsl #19 + 2428 .LVL204: + 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + 2429 .loc 1 798 35 view .LVU778 + 2430 01d8 2543 orrs r5, r5, r4 + 2431 01da CCF81050 str r5, [ip, #16] + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2432 .loc 1 799 7 is_stmt 1 view .LVU779 + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2433 .loc 1 799 35 is_stmt 0 view .LVU780 + 2434 01de DCF81050 ldr r5, [ip, #16] + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2435 .loc 1 799 67 view .LVU781 + 2436 01e2 8C68 ldr r4, [r1, #8] + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2437 .loc 1 799 79 view .LVU782 + 2438 01e4 0EFB04F4 mul r4, lr, r4 + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2439 .loc 1 799 62 view .LVU783 + 2440 01e8 C4F31204 ubfx r4, r4, #0, #19 + 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2441 .loc 1 799 35 view .LVU784 + 2442 01ec 2C43 orrs r4, r4, r5 + 2443 01ee CCF81040 str r4, [ip, #16] + 2444 01f2 2DE7 b .L164 + 2445 .LVL205: + 2446 .L170: + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2447 .loc 1 804 7 is_stmt 1 view .LVU785 + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2448 .loc 1 804 23 is_stmt 0 view .LVU786 + 2449 01f4 CA68 ldr r2, [r1, #12] + 2450 .LVL206: + ARM GAS /tmp/cc9mtr28.s page 80 + + + 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2451 .loc 1 804 10 view .LVU787 + 2452 01f6 002A cmp r2, #0 + 2453 01f8 3FF42DAF beq .L165 + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2454 .loc 1 806 9 is_stmt 1 view .LVU788 + 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2455 .loc 1 806 36 is_stmt 0 view .LVU789 + 2456 01fc CCF81420 str r2, [ip, #20] + 2457 0200 29E7 b .L165 + 2458 .L171: + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2459 .loc 1 812 7 is_stmt 1 view .LVU790 + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2460 .loc 1 812 23 is_stmt 0 view .LVU791 + 2461 0202 D0F80828 ldr r2, [r0, #2056] + 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2462 .loc 1 812 10 view .LVU792 + 2463 0206 12F4807F tst r2, #256 + 2464 020a 06D1 bne .L167 + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2465 .loc 1 814 9 is_stmt 1 view .LVU793 + 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2466 .loc 1 814 36 is_stmt 0 view .LVU794 + 2467 020c D3F8002B ldr r2, [r3, #2816] + 2468 0210 42F00052 orr r2, r2, #536870912 + 2469 0214 C3F8002B str r2, [r3, #2816] + 2470 0218 21E7 b .L166 + 2471 .L167: + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2472 .loc 1 818 9 is_stmt 1 view .LVU795 + 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2473 .loc 1 818 36 is_stmt 0 view .LVU796 + 2474 021a D3F8002B ldr r2, [r3, #2816] + 2475 021e 42F08052 orr r2, r2, #268435456 + 2476 0222 C3F8002B str r2, [r3, #2816] + 2477 0226 1AE7 b .L166 + 2478 .L175: + 2479 .align 2 + 2480 .L174: + 2481 0228 0000F8FF .word -524288 + 2482 022c FFFF07E0 .word -536346625 + 2483 0230 0000F81F .word 536346624 + 2484 .cfi_endproc + 2485 .LFE155: + 2487 .section .text.USB_ReadPacket,"ax",%progbits + 2488 .align 1 + 2489 .global USB_ReadPacket + 2490 .syntax unified + 2491 .thumb + 2492 .thumb_func + 2493 .fpu fpv5-d16 + 2495 USB_ReadPacket: + 2496 .LVL207: + 2497 .LFB158: + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2498 .loc 1 965 1 is_stmt 1 view -0 + ARM GAS /tmp/cc9mtr28.s page 81 + + + 2499 .cfi_startproc + 2500 @ args = 0, pretend = 0, frame = 0 + 2501 @ frame_needed = 0, uses_anonymous_args = 0 + 2502 @ link register save eliminated. + 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2503 .loc 1 965 1 is_stmt 0 view .LVU798 + 2504 0000 8446 mov ip, r0 + 2505 0002 0846 mov r0, r1 + 2506 .LVL208: + 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t *pDest = (uint32_t *)dest; + 2507 .loc 1 966 3 is_stmt 1 view .LVU799 + 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 2508 .loc 1 967 3 view .LVU800 + 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count32b = ((uint32_t)len + 3U) / 4U; + 2509 .loc 1 968 3 view .LVU801 + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2510 .loc 1 969 3 view .LVU802 + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2511 .loc 1 969 38 is_stmt 0 view .LVU803 + 2512 0004 D11C adds r1, r2, #3 + 2513 .LVL209: + 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2514 .loc 1 969 12 view .LVU804 + 2515 0006 8908 lsrs r1, r1, #2 + 2516 .LVL210: + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2517 .loc 1 971 3 is_stmt 1 view .LVU805 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2518 .loc 1 971 10 is_stmt 0 view .LVU806 + 2519 0008 0023 movs r3, #0 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2520 .loc 1 971 3 view .LVU807 + 2521 000a 05E0 b .L177 + 2522 .LVL211: + 2523 .L178: + 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** pDest++; + 2524 .loc 1 973 5 is_stmt 1 discriminator 3 view .LVU808 + 2525 000c 0CF58052 add r2, ip, #4096 + 2526 0010 1268 ldr r2, [r2] + 2527 0012 40F8042B str r2, [r0], #4 @ unaligned + 2528 .LVL212: + 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2529 .loc 1 974 5 discriminator 3 view .LVU809 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2530 .loc 1 971 30 discriminator 3 view .LVU810 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2531 .loc 1 971 31 is_stmt 0 discriminator 3 view .LVU811 + 2532 0016 0133 adds r3, r3, #1 + 2533 .LVL213: + 2534 .L177: + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2535 .loc 1 971 16 is_stmt 1 discriminator 1 view .LVU812 + 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2536 .loc 1 971 3 is_stmt 0 discriminator 1 view .LVU813 + 2537 0018 8B42 cmp r3, r1 + 2538 001a F7D3 bcc .L178 + 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + ARM GAS /tmp/cc9mtr28.s page 82 + + + 2539 .loc 1 977 3 is_stmt 1 view .LVU814 + 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2540 .loc 1 978 1 is_stmt 0 view .LVU815 + 2541 001c 7047 bx lr + 2542 .cfi_endproc + 2543 .LFE158: + 2545 .section .text.USB_EPSetStall,"ax",%progbits + 2546 .align 1 + 2547 .global USB_EPSetStall + 2548 .syntax unified + 2549 .thumb + 2550 .thumb_func + 2551 .fpu fpv5-d16 + 2553 USB_EPSetStall: + 2554 .LVL214: + 2555 .LFB159: + 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2556 .loc 1 987 1 is_stmt 1 view -0 + 2557 .cfi_startproc + 2558 @ args = 0, pretend = 0, frame = 0 + 2559 @ frame_needed = 0, uses_anonymous_args = 0 + 2560 @ link register save eliminated. + 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 2561 .loc 1 988 3 view .LVU817 + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2562 .loc 1 989 3 view .LVU818 + 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2563 .loc 1 989 32 is_stmt 0 view .LVU819 + 2564 0000 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 2565 .LVL215: + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2566 .loc 1 991 3 is_stmt 1 view .LVU820 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2567 .loc 1 991 9 is_stmt 0 view .LVU821 + 2568 0002 4A78 ldrb r2, [r1, #1] @ zero_extendqisi2 + 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2569 .loc 1 991 6 view .LVU822 + 2570 0004 012A cmp r2, #1 + 2571 0006 14D0 beq .L184 +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2572 .loc 1 1001 5 is_stmt 1 view .LVU823 +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2573 .loc 1 1001 11 is_stmt 0 view .LVU824 + 2574 0008 00EB4310 add r0, r0, r3, lsl #5 + 2575 .LVL216: +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2576 .loc 1 1001 28 view .LVU825 + 2577 000c D0F8002B ldr r2, [r0, #2816] +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2578 .loc 1 1001 8 view .LVU826 + 2579 0010 002A cmp r2, #0 + 2580 0012 06DB blt .L183 +1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2581 .loc 1 1001 70 discriminator 1 view .LVU827 + 2582 0014 2BB1 cbz r3, .L183 +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2583 .loc 1 1003 7 is_stmt 1 view .LVU828 + ARM GAS /tmp/cc9mtr28.s page 83 + + +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2584 .loc 1 1003 34 is_stmt 0 view .LVU829 + 2585 0016 D0F8003B ldr r3, [r0, #2816] + 2586 .LVL217: +1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2587 .loc 1 1003 34 view .LVU830 + 2588 001a 23F08043 bic r3, r3, #1073741824 + 2589 001e C0F8003B str r3, [r0, #2816] + 2590 .LVL218: + 2591 .L183: +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2592 .loc 1 1005 5 is_stmt 1 view .LVU831 +1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2593 .loc 1 1005 32 is_stmt 0 view .LVU832 + 2594 0022 D0F8003B ldr r3, [r0, #2816] + 2595 0026 43F40013 orr r3, r3, #2097152 + 2596 002a C0F8003B str r3, [r0, #2816] + 2597 .L182: +1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2598 .loc 1 1008 3 is_stmt 1 view .LVU833 +1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2599 .loc 1 1009 1 is_stmt 0 view .LVU834 + 2600 002e 0020 movs r0, #0 + 2601 0030 7047 bx lr + 2602 .LVL219: + 2603 .L184: + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2604 .loc 1 993 5 is_stmt 1 view .LVU835 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2605 .loc 1 993 11 is_stmt 0 view .LVU836 + 2606 0032 00EB4310 add r0, r0, r3, lsl #5 + 2607 .LVL220: + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2608 .loc 1 993 27 view .LVU837 + 2609 0036 D0F80029 ldr r2, [r0, #2304] + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2610 .loc 1 993 8 view .LVU838 + 2611 003a 002A cmp r2, #0 + 2612 003c 06DB blt .L181 + 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2613 .loc 1 993 69 discriminator 1 view .LVU839 + 2614 003e 2BB1 cbz r3, .L181 + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2615 .loc 1 995 7 is_stmt 1 view .LVU840 + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2616 .loc 1 995 33 is_stmt 0 view .LVU841 + 2617 0040 D0F80039 ldr r3, [r0, #2304] + 2618 .LVL221: + 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2619 .loc 1 995 33 view .LVU842 + 2620 0044 23F08043 bic r3, r3, #1073741824 + 2621 0048 C0F80039 str r3, [r0, #2304] + 2622 .LVL222: + 2623 .L181: + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2624 .loc 1 997 5 is_stmt 1 view .LVU843 + 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + ARM GAS /tmp/cc9mtr28.s page 84 + + + 2625 .loc 1 997 31 is_stmt 0 view .LVU844 + 2626 004c D0F80039 ldr r3, [r0, #2304] + 2627 0050 43F40013 orr r3, r3, #2097152 + 2628 0054 C0F80039 str r3, [r0, #2304] + 2629 0058 E9E7 b .L182 + 2630 .cfi_endproc + 2631 .LFE159: + 2633 .section .text.USB_EPClearStall,"ax",%progbits + 2634 .align 1 + 2635 .global USB_EPClearStall + 2636 .syntax unified + 2637 .thumb + 2638 .thumb_func + 2639 .fpu fpv5-d16 + 2641 USB_EPClearStall: + 2642 .LVL223: + 2643 .LFB160: +1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2644 .loc 1 1018 1 is_stmt 1 view -0 + 2645 .cfi_startproc + 2646 @ args = 0, pretend = 0, frame = 0 + 2647 @ frame_needed = 0, uses_anonymous_args = 0 + 2648 @ link register save eliminated. +1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t epnum = (uint32_t)ep->num; + 2649 .loc 1 1019 3 view .LVU846 +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2650 .loc 1 1020 3 view .LVU847 +1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2651 .loc 1 1020 32 is_stmt 0 view .LVU848 + 2652 0000 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 2653 .LVL224: +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2654 .loc 1 1022 3 is_stmt 1 view .LVU849 +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2655 .loc 1 1022 9 is_stmt 0 view .LVU850 + 2656 0002 4A78 ldrb r2, [r1, #1] @ zero_extendqisi2 +1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2657 .loc 1 1022 6 view .LVU851 + 2658 0004 012A cmp r2, #1 + 2659 0006 0ED0 beq .L188 +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2660 .loc 1 1032 5 is_stmt 1 view .LVU852 +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2661 .loc 1 1032 32 is_stmt 0 view .LVU853 + 2662 0008 00EB4310 add r0, r0, r3, lsl #5 + 2663 .LVL225: +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2664 .loc 1 1032 32 view .LVU854 + 2665 000c D0F8003B ldr r3, [r0, #2816] + 2666 .LVL226: +1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2667 .loc 1 1032 32 view .LVU855 + 2668 0010 23F40013 bic r3, r3, #2097152 + 2669 0014 C0F8003B str r3, [r0, #2816] + 2670 .LVL227: +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2671 .loc 1 1033 5 is_stmt 1 view .LVU856 + ARM GAS /tmp/cc9mtr28.s page 85 + + +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2672 .loc 1 1033 12 is_stmt 0 view .LVU857 + 2673 0018 CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2674 .loc 1 1033 36 view .LVU858 + 2675 001a 023B subs r3, r3, #2 + 2676 001c DBB2 uxtb r3, r3 +1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2677 .loc 1 1033 8 view .LVU859 + 2678 001e 012B cmp r3, #1 + 2679 0020 15D9 bls .L189 + 2680 .L187: +1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2681 .loc 1 1038 3 is_stmt 1 view .LVU860 +1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2682 .loc 1 1039 1 is_stmt 0 view .LVU861 + 2683 0022 0020 movs r0, #0 + 2684 0024 7047 bx lr + 2685 .LVL228: + 2686 .L188: +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2687 .loc 1 1024 5 is_stmt 1 view .LVU862 +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2688 .loc 1 1024 31 is_stmt 0 view .LVU863 + 2689 0026 00EB4310 add r0, r0, r3, lsl #5 + 2690 .LVL229: +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2691 .loc 1 1024 31 view .LVU864 + 2692 002a D0F80039 ldr r3, [r0, #2304] + 2693 .LVL230: +1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + 2694 .loc 1 1024 31 view .LVU865 + 2695 002e 23F40013 bic r3, r3, #2097152 + 2696 0032 C0F80039 str r3, [r0, #2304] + 2697 .LVL231: +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2698 .loc 1 1025 5 is_stmt 1 view .LVU866 +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2699 .loc 1 1025 12 is_stmt 0 view .LVU867 + 2700 0036 CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2701 .loc 1 1025 36 view .LVU868 + 2702 0038 023B subs r3, r3, #2 + 2703 003a DBB2 uxtb r3, r3 +1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2704 .loc 1 1025 8 view .LVU869 + 2705 003c 012B cmp r3, #1 + 2706 003e F0D8 bhi .L187 +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2707 .loc 1 1027 7 is_stmt 1 view .LVU870 +1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2708 .loc 1 1027 33 is_stmt 0 view .LVU871 + 2709 0040 D0F80039 ldr r3, [r0, #2304] + 2710 0044 43F08053 orr r3, r3, #268435456 + 2711 0048 C0F80039 str r3, [r0, #2304] + 2712 004c E9E7 b .L187 + 2713 .L189: + ARM GAS /tmp/cc9mtr28.s page 86 + + +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2714 .loc 1 1035 7 is_stmt 1 view .LVU872 +1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2715 .loc 1 1035 34 is_stmt 0 view .LVU873 + 2716 004e D0F8003B ldr r3, [r0, #2816] + 2717 0052 43F08053 orr r3, r3, #268435456 + 2718 0056 C0F8003B str r3, [r0, #2816] + 2719 005a E2E7 b .L187 + 2720 .cfi_endproc + 2721 .LFE160: + 2723 .section .text.USB_StopDevice,"ax",%progbits + 2724 .align 1 + 2725 .global USB_StopDevice + 2726 .syntax unified + 2727 .thumb + 2728 .thumb_func + 2729 .fpu fpv5-d16 + 2731 USB_StopDevice: + 2732 .LVL232: + 2733 .LFB161: +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret; + 2734 .loc 1 1047 1 is_stmt 1 view -0 + 2735 .cfi_startproc + 2736 @ args = 0, pretend = 0, frame = 0 + 2737 @ frame_needed = 0, uses_anonymous_args = 0 +1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret; + 2738 .loc 1 1047 1 is_stmt 0 view .LVU875 + 2739 0000 10B5 push {r4, lr} + 2740 .LCFI26: + 2741 .cfi_def_cfa_offset 8 + 2742 .cfi_offset 4, -8 + 2743 .cfi_offset 14, -4 + 2744 0002 0446 mov r4, r0 +1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2745 .loc 1 1048 3 is_stmt 1 view .LVU876 +1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 2746 .loc 1 1049 3 view .LVU877 + 2747 .LVL233: +1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2748 .loc 1 1050 3 view .LVU878 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2749 .loc 1 1053 3 view .LVU879 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2750 .loc 1 1053 10 is_stmt 0 view .LVU880 + 2751 0004 0022 movs r2, #0 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2752 .loc 1 1053 3 view .LVU881 + 2753 0006 08E0 b .L191 + 2754 .LVL234: + 2755 .L192: +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 2756 .loc 1 1055 5 is_stmt 1 discriminator 3 view .LVU882 + 2757 0008 04EB4213 add r3, r4, r2, lsl #5 +1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + 2758 .loc 1 1055 27 is_stmt 0 discriminator 3 view .LVU883 + 2759 000c 4FF67F31 movw r1, #64383 + 2760 0010 C3F80819 str r1, [r3, #2312] + ARM GAS /tmp/cc9mtr28.s page 87 + + +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2761 .loc 1 1056 5 is_stmt 1 discriminator 3 view .LVU884 +1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2762 .loc 1 1056 28 is_stmt 0 discriminator 3 view .LVU885 + 2763 0014 C3F8081B str r1, [r3, #2824] +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2764 .loc 1 1053 25 is_stmt 1 discriminator 3 view .LVU886 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2765 .loc 1 1053 26 is_stmt 0 discriminator 3 view .LVU887 + 2766 0018 0132 adds r2, r2, #1 + 2767 .LVL235: + 2768 .L191: +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2769 .loc 1 1053 16 is_stmt 1 discriminator 1 view .LVU888 +1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2770 .loc 1 1053 3 is_stmt 0 discriminator 1 view .LVU889 + 2771 001a 0E2A cmp r2, #14 + 2772 001c F4D9 bls .L192 +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; + 2773 .loc 1 1060 3 is_stmt 1 view .LVU890 +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; + 2774 .loc 1 1060 25 is_stmt 0 view .LVU891 + 2775 001e 0022 movs r2, #0 + 2776 .LVL236: +1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DOEPMSK = 0U; + 2777 .loc 1 1060 25 view .LVU892 + 2778 0020 C4F81028 str r2, [r4, #2064] +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK = 0U; + 2779 .loc 1 1061 3 is_stmt 1 view .LVU893 +1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DAINTMSK = 0U; + 2780 .loc 1 1061 25 is_stmt 0 view .LVU894 + 2781 0024 C4F81428 str r2, [r4, #2068] +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2782 .loc 1 1062 3 is_stmt 1 view .LVU895 +1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2783 .loc 1 1062 25 is_stmt 0 view .LVU896 + 2784 0028 C4F81C28 str r2, [r4, #2076] +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) + 2785 .loc 1 1065 3 is_stmt 1 view .LVU897 +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) + 2786 .loc 1 1065 9 is_stmt 0 view .LVU898 + 2787 002c 2046 mov r0, r4 + 2788 .LVL237: +1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) + 2789 .loc 1 1065 9 view .LVU899 + 2790 002e FFF7FEFF bl USB_FlushRxFifo + 2791 .LVL238: +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2792 .loc 1 1066 3 is_stmt 1 view .LVU900 +1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2793 .loc 1 1066 6 is_stmt 0 view .LVU901 + 2794 0032 00B1 cbz r0, .L195 + 2795 .L193: +1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2796 .loc 1 1078 1 view .LVU902 + 2797 0034 10BD pop {r4, pc} + 2798 .LVL239: + ARM GAS /tmp/cc9mtr28.s page 88 + + + 2799 .L195: +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) + 2800 .loc 1 1071 3 is_stmt 1 view .LVU903 +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) + 2801 .loc 1 1071 9 is_stmt 0 view .LVU904 + 2802 0036 1021 movs r1, #16 + 2803 0038 2046 mov r0, r4 + 2804 .LVL240: +1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ret != HAL_OK) + 2805 .loc 1 1071 9 view .LVU905 + 2806 003a FFF7FEFF bl USB_FlushTxFifo + 2807 .LVL241: +1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 2808 .loc 1 1072 3 is_stmt 1 view .LVU906 + 2809 003e F9E7 b .L193 + 2810 .cfi_endproc + 2811 .LFE161: + 2813 .section .text.USB_SetDevAddress,"ax",%progbits + 2814 .align 1 + 2815 .global USB_SetDevAddress + 2816 .syntax unified + 2817 .thumb + 2818 .thumb_func + 2819 .fpu fpv5-d16 + 2821 USB_SetDevAddress: + 2822 .LVL242: + 2823 .LFB162: +1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2824 .loc 1 1088 1 view -0 + 2825 .cfi_startproc + 2826 @ args = 0, pretend = 0, frame = 0 + 2827 @ frame_needed = 0, uses_anonymous_args = 0 + 2828 @ link register save eliminated. +1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2829 .loc 1 1089 3 view .LVU908 +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + 2830 .loc 1 1091 3 view .LVU909 +1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + 2831 .loc 1 1091 21 is_stmt 0 view .LVU910 + 2832 0000 D0F80038 ldr r3, [r0, #2048] + 2833 0004 23F4FE63 bic r3, r3, #2032 + 2834 0008 C0F80038 str r3, [r0, #2048] +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2835 .loc 1 1092 3 is_stmt 1 view .LVU911 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2836 .loc 1 1092 21 is_stmt 0 view .LVU912 + 2837 000c D0F80038 ldr r3, [r0, #2048] +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2838 .loc 1 1092 43 view .LVU913 + 2839 0010 0901 lsls r1, r1, #4 + 2840 .LVL243: +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2841 .loc 1 1092 49 view .LVU914 + 2842 0012 01F4FE61 and r1, r1, #2032 +1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2843 .loc 1 1092 21 view .LVU915 + 2844 0016 1943 orrs r1, r1, r3 + ARM GAS /tmp/cc9mtr28.s page 89 + + + 2845 0018 C0F80018 str r1, [r0, #2048] +1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2846 .loc 1 1094 3 is_stmt 1 view .LVU916 +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2847 .loc 1 1095 1 is_stmt 0 view .LVU917 + 2848 001c 0020 movs r0, #0 + 2849 .LVL244: +1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2850 .loc 1 1095 1 view .LVU918 + 2851 001e 7047 bx lr + 2852 .cfi_endproc + 2853 .LFE162: + 2855 .section .text.USB_DevConnect,"ax",%progbits + 2856 .align 1 + 2857 .global USB_DevConnect + 2858 .syntax unified + 2859 .thumb + 2860 .thumb_func + 2861 .fpu fpv5-d16 + 2863 USB_DevConnect: + 2864 .LVL245: + 2865 .LFB163: +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2866 .loc 1 1103 1 is_stmt 1 view -0 + 2867 .cfi_startproc + 2868 @ args = 0, pretend = 0, frame = 0 + 2869 @ frame_needed = 0, uses_anonymous_args = 0 +1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2870 .loc 1 1103 1 is_stmt 0 view .LVU920 + 2871 0000 08B5 push {r3, lr} + 2872 .LCFI27: + 2873 .cfi_def_cfa_offset 8 + 2874 .cfi_offset 3, -8 + 2875 .cfi_offset 14, -4 +1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2876 .loc 1 1104 3 is_stmt 1 view .LVU921 + 2877 .LVL246: +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(3U); + 2878 .loc 1 1106 3 view .LVU922 +1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(3U); + 2879 .loc 1 1106 21 is_stmt 0 view .LVU923 + 2880 0002 D0F80438 ldr r3, [r0, #2052] + 2881 0006 23F00203 bic r3, r3, #2 + 2882 000a C0F80438 str r3, [r0, #2052] +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2883 .loc 1 1107 3 is_stmt 1 view .LVU924 + 2884 000e 0320 movs r0, #3 + 2885 .LVL247: +1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2886 .loc 1 1107 3 is_stmt 0 view .LVU925 + 2887 0010 FFF7FEFF bl HAL_Delay + 2888 .LVL248: +1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2889 .loc 1 1109 3 is_stmt 1 view .LVU926 +1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2890 .loc 1 1110 1 is_stmt 0 view .LVU927 + 2891 0014 0020 movs r0, #0 + ARM GAS /tmp/cc9mtr28.s page 90 + + + 2892 0016 08BD pop {r3, pc} + 2893 .cfi_endproc + 2894 .LFE163: + 2896 .section .text.USB_DevDisconnect,"ax",%progbits + 2897 .align 1 + 2898 .global USB_DevDisconnect + 2899 .syntax unified + 2900 .thumb + 2901 .thumb_func + 2902 .fpu fpv5-d16 + 2904 USB_DevDisconnect: + 2905 .LVL249: + 2906 .LFB164: +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2907 .loc 1 1118 1 is_stmt 1 view -0 + 2908 .cfi_startproc + 2909 @ args = 0, pretend = 0, frame = 0 + 2910 @ frame_needed = 0, uses_anonymous_args = 0 +1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2911 .loc 1 1118 1 is_stmt 0 view .LVU929 + 2912 0000 08B5 push {r3, lr} + 2913 .LCFI28: + 2914 .cfi_def_cfa_offset 8 + 2915 .cfi_offset 3, -8 + 2916 .cfi_offset 14, -4 +1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2917 .loc 1 1119 3 is_stmt 1 view .LVU930 + 2918 .LVL250: +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(3U); + 2919 .loc 1 1121 3 view .LVU931 +1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(3U); + 2920 .loc 1 1121 21 is_stmt 0 view .LVU932 + 2921 0002 D0F80438 ldr r3, [r0, #2052] + 2922 0006 43F00203 orr r3, r3, #2 + 2923 000a C0F80438 str r3, [r0, #2052] +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2924 .loc 1 1122 3 is_stmt 1 view .LVU933 + 2925 000e 0320 movs r0, #3 + 2926 .LVL251: +1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2927 .loc 1 1122 3 is_stmt 0 view .LVU934 + 2928 0010 FFF7FEFF bl HAL_Delay + 2929 .LVL252: +1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2930 .loc 1 1124 3 is_stmt 1 view .LVU935 +1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2931 .loc 1 1125 1 is_stmt 0 view .LVU936 + 2932 0014 0020 movs r0, #0 + 2933 0016 08BD pop {r3, pc} + 2934 .cfi_endproc + 2935 .LFE164: + 2937 .section .text.USB_ReadInterrupts,"ax",%progbits + 2938 .align 1 + 2939 .global USB_ReadInterrupts + 2940 .syntax unified + 2941 .thumb + 2942 .thumb_func + ARM GAS /tmp/cc9mtr28.s page 91 + + + 2943 .fpu fpv5-d16 + 2945 USB_ReadInterrupts: + 2946 .LVL253: + 2947 .LFB165: +1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; + 2948 .loc 1 1133 1 is_stmt 1 view -0 + 2949 .cfi_startproc + 2950 @ args = 0, pretend = 0, frame = 0 + 2951 @ frame_needed = 0, uses_anonymous_args = 0 + 2952 @ link register save eliminated. +1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2953 .loc 1 1134 3 view .LVU938 +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx->GINTMSK; + 2954 .loc 1 1136 3 view .LVU939 +1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx->GINTMSK; + 2955 .loc 1 1136 10 is_stmt 0 view .LVU940 + 2956 0000 4269 ldr r2, [r0, #20] + 2957 .LVL254: +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2958 .loc 1 1137 3 is_stmt 1 view .LVU941 +1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2959 .loc 1 1137 17 is_stmt 0 view .LVU942 + 2960 0002 8069 ldr r0, [r0, #24] + 2961 .LVL255: +1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 2962 .loc 1 1139 3 is_stmt 1 view .LVU943 +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2963 .loc 1 1140 1 is_stmt 0 view .LVU944 + 2964 0004 1040 ands r0, r0, r2 + 2965 .LVL256: +1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2966 .loc 1 1140 1 view .LVU945 + 2967 0006 7047 bx lr + 2968 .cfi_endproc + 2969 .LFE165: + 2971 .section .text.USB_ReadDevAllOutEpInterrupt,"ax",%progbits + 2972 .align 1 + 2973 .global USB_ReadDevAllOutEpInterrupt + 2974 .syntax unified + 2975 .thumb + 2976 .thumb_func + 2977 .fpu fpv5-d16 + 2979 USB_ReadDevAllOutEpInterrupt: + 2980 .LVL257: + 2981 .LFB166: +1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 2982 .loc 1 1148 1 is_stmt 1 view -0 + 2983 .cfi_startproc + 2984 @ args = 0, pretend = 0, frame = 0 + 2985 @ frame_needed = 0, uses_anonymous_args = 0 + 2986 @ link register save eliminated. +1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; + 2987 .loc 1 1149 3 view .LVU947 +1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2988 .loc 1 1150 3 view .LVU948 +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; + 2989 .loc 1 1152 3 view .LVU949 + ARM GAS /tmp/cc9mtr28.s page 92 + + +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; + 2990 .loc 1 1152 11 is_stmt 0 view .LVU950 + 2991 0000 D0F81838 ldr r3, [r0, #2072] +1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; + 2992 .loc 1 1152 13 view .LVU951 + 2993 0004 00F50060 add r0, r0, #2048 + 2994 .LVL258: +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2995 .loc 1 1153 3 is_stmt 1 view .LVU952 +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2996 .loc 1 1153 24 is_stmt 0 view .LVU953 + 2997 0008 C069 ldr r0, [r0, #28] + 2998 .LVL259: +1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 2999 .loc 1 1153 10 view .LVU954 + 3000 000a 1840 ands r0, r0, r3 + 3001 .LVL260: +1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3002 .loc 1 1155 3 is_stmt 1 view .LVU955 +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3003 .loc 1 1156 1 is_stmt 0 view .LVU956 + 3004 000c 000C lsrs r0, r0, #16 + 3005 .LVL261: +1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3006 .loc 1 1156 1 view .LVU957 + 3007 000e 7047 bx lr + 3008 .cfi_endproc + 3009 .LFE166: + 3011 .section .text.USB_ReadDevAllInEpInterrupt,"ax",%progbits + 3012 .align 1 + 3013 .global USB_ReadDevAllInEpInterrupt + 3014 .syntax unified + 3015 .thumb + 3016 .thumb_func + 3017 .fpu fpv5-d16 + 3019 USB_ReadDevAllInEpInterrupt: + 3020 .LVL262: + 3021 .LFB167: +1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3022 .loc 1 1164 1 is_stmt 1 view -0 + 3023 .cfi_startproc + 3024 @ args = 0, pretend = 0, frame = 0 + 3025 @ frame_needed = 0, uses_anonymous_args = 0 + 3026 @ link register save eliminated. +1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; + 3027 .loc 1 1165 3 view .LVU959 +1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3028 .loc 1 1166 3 view .LVU960 +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; + 3029 .loc 1 1168 3 view .LVU961 +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; + 3030 .loc 1 1168 11 is_stmt 0 view .LVU962 + 3031 0000 D0F81838 ldr r3, [r0, #2072] +1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DAINTMSK; + 3032 .loc 1 1168 13 view .LVU963 + 3033 0004 00F50060 add r0, r0, #2048 + 3034 .LVL263: + ARM GAS /tmp/cc9mtr28.s page 93 + + +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3035 .loc 1 1169 3 is_stmt 1 view .LVU964 +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3036 .loc 1 1169 24 is_stmt 0 view .LVU965 + 3037 0008 C069 ldr r0, [r0, #28] + 3038 .LVL264: +1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3039 .loc 1 1169 10 view .LVU966 + 3040 000a 1840 ands r0, r0, r3 + 3041 .LVL265: +1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3042 .loc 1 1171 3 is_stmt 1 view .LVU967 +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3043 .loc 1 1172 1 is_stmt 0 view .LVU968 + 3044 000c 80B2 uxth r0, r0 + 3045 .LVL266: +1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3046 .loc 1 1172 1 view .LVU969 + 3047 000e 7047 bx lr + 3048 .cfi_endproc + 3049 .LFE167: + 3051 .section .text.USB_ReadDevOutEPInterrupt,"ax",%progbits + 3052 .align 1 + 3053 .global USB_ReadDevOutEPInterrupt + 3054 .syntax unified + 3055 .thumb + 3056 .thumb_func + 3057 .fpu fpv5-d16 + 3059 USB_ReadDevOutEPInterrupt: + 3060 .LVL267: + 3061 .LFB168: +1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3062 .loc 1 1182 1 is_stmt 1 view -0 + 3063 .cfi_startproc + 3064 @ args = 0, pretend = 0, frame = 0 + 3065 @ frame_needed = 0, uses_anonymous_args = 0 + 3066 @ link register save eliminated. +1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; + 3067 .loc 1 1183 3 view .LVU971 +1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3068 .loc 1 1184 3 view .LVU972 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DOEPMSK; + 3069 .loc 1 1186 3 view .LVU973 +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DOEPMSK; + 3070 .loc 1 1186 13 is_stmt 0 view .LVU974 + 3071 0000 00EB4111 add r1, r0, r1, lsl #5 + 3072 .LVL268: +1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= USBx_DEVICE->DOEPMSK; + 3073 .loc 1 1186 11 view .LVU975 + 3074 0004 D1F8082B ldr r2, [r1, #2824] + 3075 .LVL269: +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3076 .loc 1 1187 3 is_stmt 1 view .LVU976 +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3077 .loc 1 1187 13 is_stmt 0 view .LVU977 + 3078 0008 00F50060 add r0, r0, #2048 + 3079 .LVL270: + ARM GAS /tmp/cc9mtr28.s page 94 + + +1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3080 .loc 1 1187 24 view .LVU978 + 3081 000c 4069 ldr r0, [r0, #20] + 3082 .LVL271: +1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3083 .loc 1 1189 3 is_stmt 1 view .LVU979 +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3084 .loc 1 1190 1 is_stmt 0 view .LVU980 + 3085 000e 1040 ands r0, r0, r2 + 3086 .LVL272: +1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3087 .loc 1 1190 1 view .LVU981 + 3088 0010 7047 bx lr + 3089 .cfi_endproc + 3090 .LFE168: + 3092 .section .text.USB_ReadDevInEPInterrupt,"ax",%progbits + 3093 .align 1 + 3094 .global USB_ReadDevInEPInterrupt + 3095 .syntax unified + 3096 .thumb + 3097 .thumb_func + 3098 .fpu fpv5-d16 + 3100 USB_ReadDevInEPInterrupt: + 3101 .LVL273: + 3102 .LFB169: +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3103 .loc 1 1200 1 is_stmt 1 view -0 + 3104 .cfi_startproc + 3105 @ args = 0, pretend = 0, frame = 0 + 3106 @ frame_needed = 0, uses_anonymous_args = 0 + 3107 @ link register save eliminated. +1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3108 .loc 1 1200 1 is_stmt 0 view .LVU983 + 3109 0000 10B4 push {r4} + 3110 .LCFI29: + 3111 .cfi_def_cfa_offset 4 + 3112 .cfi_offset 4, -4 +1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg, msk, emp; + 3113 .loc 1 1201 3 is_stmt 1 view .LVU984 + 3114 .LVL274: +1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3115 .loc 1 1202 3 view .LVU985 +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** emp = USBx_DEVICE->DIEPEMPMSK; + 3116 .loc 1 1204 3 view .LVU986 +1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** emp = USBx_DEVICE->DIEPEMPMSK; + 3117 .loc 1 1204 7 is_stmt 0 view .LVU987 + 3118 0002 D0F81048 ldr r4, [r0, #2064] + 3119 .LVL275: +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + 3120 .loc 1 1205 3 is_stmt 1 view .LVU988 +1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + 3121 .loc 1 1205 7 is_stmt 0 view .LVU989 + 3122 0006 D0F83438 ldr r3, [r0, #2100] + 3123 .LVL276: +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + 3124 .loc 1 1206 3 is_stmt 1 view .LVU990 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + ARM GAS /tmp/cc9mtr28.s page 95 + + + 3125 .loc 1 1206 26 is_stmt 0 view .LVU991 + 3126 000a 01F00F02 and r2, r1, #15 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + 3127 .loc 1 1206 16 view .LVU992 + 3128 000e D340 lsrs r3, r3, r2 + 3129 .LVL277: +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + 3130 .loc 1 1206 50 view .LVU993 + 3131 0010 DB01 lsls r3, r3, #7 + 3132 0012 DBB2 uxtb r3, r3 +1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + 3133 .loc 1 1206 7 view .LVU994 + 3134 0014 2343 orrs r3, r3, r4 + 3135 .LVL278: +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3136 .loc 1 1207 3 is_stmt 1 view .LVU995 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3137 .loc 1 1207 12 is_stmt 0 view .LVU996 + 3138 0016 00EB4110 add r0, r0, r1, lsl #5 + 3139 .LVL279: +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3140 .loc 1 1207 12 view .LVU997 + 3141 001a 00F51060 add r0, r0, #2304 +1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3142 .loc 1 1207 38 view .LVU998 + 3143 001e 8068 ldr r0, [r0, #8] + 3144 .LVL280: +1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3145 .loc 1 1209 3 is_stmt 1 view .LVU999 +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3146 .loc 1 1210 1 is_stmt 0 view .LVU1000 + 3147 0020 1840 ands r0, r0, r3 + 3148 .LVL281: +1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3149 .loc 1 1210 1 view .LVU1001 + 3150 0022 5DF8044B ldr r4, [sp], #4 + 3151 .LCFI30: + 3152 .cfi_restore 4 + 3153 .cfi_def_cfa_offset 0 + 3154 0026 7047 bx lr + 3155 .cfi_endproc + 3156 .LFE169: + 3158 .section .text.USB_ClearInterrupts,"ax",%progbits + 3159 .align 1 + 3160 .global USB_ClearInterrupts + 3161 .syntax unified + 3162 .thumb + 3163 .thumb_func + 3164 .fpu fpv5-d16 + 3166 USB_ClearInterrupts: + 3167 .LVL282: + 3168 .LFB170: +1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTSTS |= interrupt; + 3169 .loc 1 1219 1 is_stmt 1 view -0 + 3170 .cfi_startproc + 3171 @ args = 0, pretend = 0, frame = 0 + 3172 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc9mtr28.s page 96 + + + 3173 @ link register save eliminated. +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3174 .loc 1 1220 3 view .LVU1003 +1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3175 .loc 1 1220 17 is_stmt 0 view .LVU1004 + 3176 0000 4369 ldr r3, [r0, #20] + 3177 0002 0B43 orrs r3, r3, r1 + 3178 0004 4361 str r3, [r0, #20] +1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3179 .loc 1 1221 1 view .LVU1005 + 3180 0006 7047 bx lr + 3181 .cfi_endproc + 3182 .LFE170: + 3184 .section .text.USB_GetMode,"ax",%progbits + 3185 .align 1 + 3186 .global USB_GetMode + 3187 .syntax unified + 3188 .thumb + 3189 .thumb_func + 3190 .fpu fpv5-d16 + 3192 USB_GetMode: + 3193 .LVL283: + 3194 .LFB171: +1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((USBx->GINTSTS) & 0x1U); + 3195 .loc 1 1232 1 is_stmt 1 view -0 + 3196 .cfi_startproc + 3197 @ args = 0, pretend = 0, frame = 0 + 3198 @ frame_needed = 0, uses_anonymous_args = 0 + 3199 @ link register save eliminated. +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3200 .loc 1 1233 3 view .LVU1007 +1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3201 .loc 1 1233 16 is_stmt 0 view .LVU1008 + 3202 0000 4069 ldr r0, [r0, #20] + 3203 .LVL284: +1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3204 .loc 1 1234 1 view .LVU1009 + 3205 0002 00F00100 and r0, r0, #1 + 3206 0006 7047 bx lr + 3207 .cfi_endproc + 3208 .LFE171: + 3210 .section .text.USB_ActivateSetup,"ax",%progbits + 3211 .align 1 + 3212 .global USB_ActivateSetup + 3213 .syntax unified + 3214 .thumb + 3215 .thumb_func + 3216 .fpu fpv5-d16 + 3218 USB_ActivateSetup: + 3219 .LVL285: + 3220 .LFB172: +1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3221 .loc 1 1242 1 is_stmt 1 view -0 + 3222 .cfi_startproc + 3223 @ args = 0, pretend = 0, frame = 0 + 3224 @ frame_needed = 0, uses_anonymous_args = 0 + 3225 @ link register save eliminated. + ARM GAS /tmp/cc9mtr28.s page 97 + + +1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3226 .loc 1 1243 3 view .LVU1011 +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3227 .loc 1 1246 3 view .LVU1012 +1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3228 .loc 1 1246 26 is_stmt 0 view .LVU1013 + 3229 0000 D0F80029 ldr r2, [r0, #2304] + 3230 0004 054B ldr r3, .L210 + 3231 0006 1340 ands r3, r3, r2 + 3232 0008 C0F80039 str r3, [r0, #2304] +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3233 .loc 1 1248 3 is_stmt 1 view .LVU1014 +1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3234 .loc 1 1248 21 is_stmt 0 view .LVU1015 + 3235 000c D0F80438 ldr r3, [r0, #2052] + 3236 0010 43F48073 orr r3, r3, #256 + 3237 0014 C0F80438 str r3, [r0, #2052] +1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3238 .loc 1 1250 3 is_stmt 1 view .LVU1016 +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3239 .loc 1 1251 1 is_stmt 0 view .LVU1017 + 3240 0018 0020 movs r0, #0 + 3241 .LVL286: +1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3242 .loc 1 1251 1 view .LVU1018 + 3243 001a 7047 bx lr + 3244 .L211: + 3245 .align 2 + 3246 .L210: + 3247 001c 00F8FFFF .word -2048 + 3248 .cfi_endproc + 3249 .LFE172: + 3251 .section .text.USB_EP0_OutStart,"ax",%progbits + 3252 .align 1 + 3253 .global USB_EP0_OutStart + 3254 .syntax unified + 3255 .thumb + 3256 .thumb_func + 3257 .fpu fpv5-d16 + 3259 USB_EP0_OutStart: + 3260 .LVL287: + 3261 .LFB173: +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3262 .loc 1 1264 1 is_stmt 1 view -0 + 3263 .cfi_startproc + 3264 @ args = 0, pretend = 0, frame = 0 + 3265 @ frame_needed = 0, uses_anonymous_args = 0 + 3266 @ link register save eliminated. +1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3267 .loc 1 1264 1 is_stmt 0 view .LVU1020 + 3268 0000 10B4 push {r4} + 3269 .LCFI31: + 3270 .cfi_def_cfa_offset 4 + 3271 .cfi_offset 4, -4 +1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + 3272 .loc 1 1265 3 is_stmt 1 view .LVU1021 + 3273 .LVL288: + ARM GAS /tmp/cc9mtr28.s page 98 + + +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3274 .loc 1 1266 3 view .LVU1022 +1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3275 .loc 1 1266 12 is_stmt 0 view .LVU1023 + 3276 0002 046C ldr r4, [r0, #64] + 3277 .LVL289: +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3278 .loc 1 1268 3 is_stmt 1 view .LVU1024 +1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3279 .loc 1 1268 6 is_stmt 0 view .LVU1025 + 3280 0004 154B ldr r3, .L217 + 3281 0006 9C42 cmp r4, r3 + 3282 0008 03D9 bls .L213 +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3283 .loc 1 1270 5 is_stmt 1 view .LVU1026 +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3284 .loc 1 1270 24 is_stmt 0 view .LVU1027 + 3285 000a D0F8003B ldr r3, [r0, #2816] +1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3286 .loc 1 1270 8 view .LVU1028 + 3287 000e 002B cmp r3, #0 + 3288 0010 16DB blt .L214 + 3289 .L213: +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 3290 .loc 1 1276 3 is_stmt 1 view .LVU1029 +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 3291 .loc 1 1276 28 is_stmt 0 view .LVU1030 + 3292 0012 0024 movs r4, #0 + 3293 .LVL290: +1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + 3294 .loc 1 1276 28 view .LVU1031 + 3295 0014 C0F8104B str r4, [r0, #2832] +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + 3296 .loc 1 1277 3 is_stmt 1 view .LVU1032 +1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + 3297 .loc 1 1277 28 is_stmt 0 view .LVU1033 + 3298 0018 D0F8104B ldr r4, [r0, #2832] + 3299 001c 44F40024 orr r4, r4, #524288 + 3300 0020 C0F8104B str r4, [r0, #2832] +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + 3301 .loc 1 1278 3 is_stmt 1 view .LVU1034 +1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + 3302 .loc 1 1278 28 is_stmt 0 view .LVU1035 + 3303 0024 D0F8104B ldr r4, [r0, #2832] + 3304 0028 44F01804 orr r4, r4, #24 + 3305 002c C0F8104B str r4, [r0, #2832] +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3306 .loc 1 1279 3 is_stmt 1 view .LVU1036 +1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3307 .loc 1 1279 28 is_stmt 0 view .LVU1037 + 3308 0030 D0F8104B ldr r4, [r0, #2832] + 3309 0034 44F0C044 orr r4, r4, #1610612736 + 3310 0038 C0F8104B str r4, [r0, #2832] +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3311 .loc 1 1281 3 is_stmt 1 view .LVU1038 +1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3312 .loc 1 1281 6 is_stmt 0 view .LVU1039 + ARM GAS /tmp/cc9mtr28.s page 99 + + + 3313 003c 0129 cmp r1, #1 + 3314 003e 03D0 beq .L216 + 3315 .L214: +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3316 .loc 1 1289 1 view .LVU1040 + 3317 0040 0020 movs r0, #0 + 3318 .LVL291: +1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3319 .loc 1 1289 1 view .LVU1041 + 3320 0042 5DF8044B ldr r4, [sp], #4 + 3321 .LCFI32: + 3322 .cfi_remember_state + 3323 .cfi_restore 4 + 3324 .cfi_def_cfa_offset 0 + 3325 0046 7047 bx lr + 3326 .LVL292: + 3327 .L216: + 3328 .LCFI33: + 3329 .cfi_restore_state +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable */ + 3330 .loc 1 1283 5 is_stmt 1 view .LVU1042 +1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* EP enable */ + 3331 .loc 1 1283 29 is_stmt 0 view .LVU1043 + 3332 0048 C0F8142B str r2, [r0, #2836] +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3333 .loc 1 1285 5 is_stmt 1 view .LVU1044 +1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3334 .loc 1 1285 29 is_stmt 0 view .LVU1045 + 3335 004c D0F8003B ldr r3, [r0, #2816] + 3336 0050 43F08023 orr r3, r3, #-2147450880 + 3337 0054 C0F8003B str r3, [r0, #2816] + 3338 0058 F2E7 b .L214 + 3339 .L218: + 3340 005a 00BF .align 2 + 3341 .L217: + 3342 005c 0A30544F .word 1330917386 + 3343 .cfi_endproc + 3344 .LFE173: + 3346 .section .text.USB_InitFSLSPClkSel,"ax",%progbits + 3347 .align 1 + 3348 .global USB_InitFSLSPClkSel + 3349 .syntax unified + 3350 .thumb + 3351 .thumb_func + 3352 .fpu fpv5-d16 + 3354 USB_InitFSLSPClkSel: + 3355 .LVL293: + 3356 .LFB176: +1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_HostInit : Initializes the USB OTG controller registers +1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * for Host mode +1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains +1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * the configuration information for the specified USBx peripheral. +1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + ARM GAS /tmp/cc9mtr28.s page 100 + + +1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; +1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Restart the Phy Clock */ +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_PCGCCTL = 0U; +1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Disable VBUS sensing */ +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); +1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Disable Battery chargin detector */ +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); +1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx->CID & (0x1U << 8)) != 0U) +1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.speed == USBH_FSLS_SPEED) +1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Force Device Enumeration to FS/LS mode only */ +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; +1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set default Max speed support */ +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); +1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set default Max speed support */ +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); +1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Make sure the FIFOs are flushed. */ +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushRxFifo(USBx); +1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear all pending HC Interrupts */ +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i < cfg.Host_channels; i++) +1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(i)->HCINT = 0xFFFFFFFFU; +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(i)->HCINTMSK = 0U; +1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable VBUS driving */ +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_DriveVbus(USBx, 1U); +1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(200U); +1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Disable all interrupts. */ +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK = 0U; +1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear any pending interrupts */ +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTSTS = 0xFFFFFFFFU; +1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx->CID & (0x1U << 8)) != 0U) + ARM GAS /tmp/cc9mtr28.s page 101 + + +1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* set Rx FIFO size */ +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GRXFSIZ = 0x200U; +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); +1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* set Rx FIFO size */ +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GRXFSIZ = 0x80U; +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); +1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable the common interrupts */ +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (cfg.dma_enable == 0U) +1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; +1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable interrupts matching to the Host mode ONLY */ +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ +1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ +1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); +1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the +1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * HCFG register on the PHY type and set the right frame interval +1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param freq clock frequency +1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * HCFG_48_MHZ : Full Speed 48 MHz Clock +1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * HCFG_6_MHZ : Low Speed 6 MHz Clock +1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3357 .loc 1 1430 1 is_stmt 1 view -0 + 3358 .cfi_startproc + 3359 @ args = 0, pretend = 0, frame = 0 + 3360 @ frame_needed = 0, uses_anonymous_args = 0 + 3361 @ link register save eliminated. +1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3362 .loc 1 1431 3 view .LVU1047 +1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + 3363 .loc 1 1433 3 view .LVU1048 + 3364 .loc 1 1433 19 is_stmt 0 view .LVU1049 + 3365 0000 00F5806C add ip, r0, #1024 + 3366 0004 D0F80034 ldr r3, [r0, #1024] + 3367 0008 23F00303 bic r3, r3, #3 + 3368 000c C0F80034 str r3, [r0, #1024] +1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + 3369 .loc 1 1434 3 is_stmt 1 view .LVU1050 + ARM GAS /tmp/cc9mtr28.s page 102 + + + 3370 .loc 1 1434 19 is_stmt 0 view .LVU1051 + 3371 0010 D0F80034 ldr r3, [r0, #1024] + 3372 .loc 1 1434 37 view .LVU1052 + 3373 0014 01F00302 and r2, r1, #3 + 3374 .loc 1 1434 19 view .LVU1053 + 3375 0018 1343 orrs r3, r3, r2 + 3376 001a C0F80034 str r3, [r0, #1024] +1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (freq == HCFG_48_MHZ) + 3377 .loc 1 1436 3 is_stmt 1 view .LVU1054 + 3378 .loc 1 1436 6 is_stmt 0 view .LVU1055 + 3379 001e 0129 cmp r1, #1 + 3380 0020 03D0 beq .L222 +1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HFIR = 48000U; +1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if (freq == HCFG_6_MHZ) + 3381 .loc 1 1440 8 is_stmt 1 view .LVU1056 + 3382 .loc 1 1440 11 is_stmt 0 view .LVU1057 + 3383 0022 0229 cmp r1, #2 + 3384 0024 06D0 beq .L223 + 3385 .L221: +1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HFIR = 6000U; +1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* ... */ +1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3386 .loc 1 1447 3 is_stmt 1 view .LVU1058 +1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 3387 .loc 1 1449 3 view .LVU1059 +1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3388 .loc 1 1450 1 is_stmt 0 view .LVU1060 + 3389 0026 0020 movs r0, #0 + 3390 .LVL294: + 3391 .loc 1 1450 1 view .LVU1061 + 3392 0028 7047 bx lr + 3393 .LVL295: + 3394 .L222: +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3395 .loc 1 1438 5 is_stmt 1 view .LVU1062 +1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3396 .loc 1 1438 21 is_stmt 0 view .LVU1063 + 3397 002a 4BF68033 movw r3, #48000 + 3398 002e CCF80430 str r3, [ip, #4] + 3399 0032 F8E7 b .L221 + 3400 .L223: +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3401 .loc 1 1442 5 is_stmt 1 view .LVU1064 +1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3402 .loc 1 1442 21 is_stmt 0 view .LVU1065 + 3403 0034 41F27073 movw r3, #6000 + 3404 0038 CCF80430 str r3, [ip, #4] + 3405 003c F3E7 b .L221 + 3406 .cfi_endproc + ARM GAS /tmp/cc9mtr28.s page 103 + + + 3407 .LFE176: + 3409 .section .text.USB_ResetPort,"ax",%progbits + 3410 .align 1 + 3411 .global USB_ResetPort + 3412 .syntax unified + 3413 .thumb + 3414 .thumb_func + 3415 .fpu fpv5-d16 + 3417 USB_ResetPort: + 3418 .LVL296: + 3419 .LFB177: +1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_OTG_ResetPort : Reset Host Port +1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @note (1)The application must wait at least 10 ms +1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * before clearing the reset bit. +1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3420 .loc 1 1460 1 is_stmt 1 view -0 + 3421 .cfi_startproc + 3422 @ args = 0, pretend = 0, frame = 8 + 3423 @ frame_needed = 0, uses_anonymous_args = 0 + 3424 .loc 1 1460 1 is_stmt 0 view .LVU1067 + 3425 0000 30B5 push {r4, r5, lr} + 3426 .LCFI34: + 3427 .cfi_def_cfa_offset 12 + 3428 .cfi_offset 4, -12 + 3429 .cfi_offset 5, -8 + 3430 .cfi_offset 14, -4 + 3431 0002 83B0 sub sp, sp, #12 + 3432 .LCFI35: + 3433 .cfi_def_cfa_offset 24 + 3434 0004 0446 mov r4, r0 +1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3435 .loc 1 1461 3 is_stmt 1 view .LVU1068 + 3436 .LVL297: +1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** __IO uint32_t hprt0 = 0U; + 3437 .loc 1 1463 3 view .LVU1069 + 3438 .loc 1 1463 17 is_stmt 0 view .LVU1070 + 3439 0006 0025 movs r5, #0 + 3440 0008 0195 str r5, [sp, #4] +1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hprt0 = USBx_HPRT0; + 3441 .loc 1 1465 3 is_stmt 1 view .LVU1071 + 3442 .loc 1 1465 11 is_stmt 0 view .LVU1072 + 3443 000a D0F84034 ldr r3, [r0, #1088] + 3444 .loc 1 1465 9 view .LVU1073 + 3445 000e 0193 str r3, [sp, #4] +1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + 3446 .loc 1 1467 3 is_stmt 1 view .LVU1074 + 3447 .loc 1 1467 9 is_stmt 0 view .LVU1075 + 3448 0010 019B ldr r3, [sp, #4] + ARM GAS /tmp/cc9mtr28.s page 104 + + + 3449 0012 23F02E03 bic r3, r3, #46 + 3450 0016 0193 str r3, [sp, #4] +1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); +1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + 3451 .loc 1 1470 3 is_stmt 1 view .LVU1076 + 3452 .loc 1 1470 35 is_stmt 0 view .LVU1077 + 3453 0018 019B ldr r3, [sp, #4] + 3454 001a 43F48073 orr r3, r3, #256 + 3455 .loc 1 1470 14 view .LVU1078 + 3456 001e C0F84034 str r3, [r0, #1088] +1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(100U); /* See Note #1 */ + 3457 .loc 1 1471 3 is_stmt 1 view .LVU1079 + 3458 0022 6420 movs r0, #100 + 3459 .LVL298: + 3460 .loc 1 1471 3 is_stmt 0 view .LVU1080 + 3461 0024 FFF7FEFF bl HAL_Delay + 3462 .LVL299: +1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + 3463 .loc 1 1472 3 is_stmt 1 view .LVU1081 + 3464 .loc 1 1472 38 is_stmt 0 view .LVU1082 + 3465 0028 019B ldr r3, [sp, #4] + 3466 002a 23F48073 bic r3, r3, #256 + 3467 .loc 1 1472 14 view .LVU1083 + 3468 002e C4F84034 str r3, [r4, #1088] +1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_Delay(10U); + 3469 .loc 1 1473 3 is_stmt 1 view .LVU1084 + 3470 0032 0A20 movs r0, #10 + 3471 0034 FFF7FEFF bl HAL_Delay + 3472 .LVL300: +1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 3473 .loc 1 1475 3 view .LVU1085 +1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3474 .loc 1 1476 1 is_stmt 0 view .LVU1086 + 3475 0038 2846 mov r0, r5 + 3476 003a 03B0 add sp, sp, #12 + 3477 .LCFI36: + 3478 .cfi_def_cfa_offset 12 + 3479 @ sp needed + 3480 003c 30BD pop {r4, r5, pc} + 3481 .loc 1 1476 1 view .LVU1087 + 3482 .cfi_endproc + 3483 .LFE177: + 3485 .section .text.USB_DriveVbus,"ax",%progbits + 3486 .align 1 + 3487 .global USB_DriveVbus + 3488 .syntax unified + 3489 .thumb + 3490 .thumb_func + 3491 .fpu fpv5-d16 + 3493 USB_DriveVbus: + 3494 .LVL301: + 3495 .LFB178: +1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_DriveVbus : activate or de-activate vbus + ARM GAS /tmp/cc9mtr28.s page 105 + + +1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param state VBUS state +1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : VBUS Active +1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : VBUS Inactive +1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3496 .loc 1 1487 1 is_stmt 1 view -0 + 3497 .cfi_startproc + 3498 @ args = 0, pretend = 0, frame = 8 + 3499 @ frame_needed = 0, uses_anonymous_args = 0 + 3500 @ link register save eliminated. + 3501 .loc 1 1487 1 is_stmt 0 view .LVU1089 + 3502 0000 82B0 sub sp, sp, #8 + 3503 .LCFI37: + 3504 .cfi_def_cfa_offset 8 +1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3505 .loc 1 1488 3 is_stmt 1 view .LVU1090 + 3506 .LVL302: +1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** __IO uint32_t hprt0 = 0U; + 3507 .loc 1 1489 3 view .LVU1091 + 3508 .loc 1 1489 17 is_stmt 0 view .LVU1092 + 3509 0002 0023 movs r3, #0 + 3510 0004 0193 str r3, [sp, #4] +1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hprt0 = USBx_HPRT0; + 3511 .loc 1 1491 3 is_stmt 1 view .LVU1093 + 3512 .loc 1 1491 11 is_stmt 0 view .LVU1094 + 3513 0006 D0F84034 ldr r3, [r0, #1088] + 3514 .loc 1 1491 9 view .LVU1095 + 3515 000a 0193 str r3, [sp, #4] +1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + 3516 .loc 1 1493 3 is_stmt 1 view .LVU1096 + 3517 .loc 1 1493 9 is_stmt 0 view .LVU1097 + 3518 000c 019B ldr r3, [sp, #4] + 3519 000e 23F02E03 bic r3, r3, #46 + 3520 0012 0193 str r3, [sp, #4] +1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); +1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + 3521 .loc 1 1496 3 is_stmt 1 view .LVU1098 + 3522 .loc 1 1496 15 is_stmt 0 view .LVU1099 + 3523 0014 019B ldr r3, [sp, #4] + 3524 .loc 1 1496 6 view .LVU1100 + 3525 0016 13F4805F tst r3, #4096 + 3526 001a 01D1 bne .L227 + 3527 .loc 1 1496 43 discriminator 1 view .LVU1101 + 3528 001c 0129 cmp r1, #1 + 3529 001e 0CD0 beq .L230 + 3530 .L227: +1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); +1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + 3531 .loc 1 1500 3 is_stmt 1 view .LVU1102 + ARM GAS /tmp/cc9mtr28.s page 106 + + + 3532 .loc 1 1500 15 is_stmt 0 view .LVU1103 + 3533 0020 019B ldr r3, [sp, #4] + 3534 .loc 1 1500 6 view .LVU1104 + 3535 0022 13F4805F tst r3, #4096 + 3536 0026 05D0 beq .L228 + 3537 .loc 1 1500 58 discriminator 1 view .LVU1105 + 3538 0028 21B9 cbnz r1, .L228 +1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + 3539 .loc 1 1502 5 is_stmt 1 view .LVU1106 + 3540 .loc 1 1502 40 is_stmt 0 view .LVU1107 + 3541 002a 019B ldr r3, [sp, #4] + 3542 002c 23F48053 bic r3, r3, #4096 + 3543 .loc 1 1502 16 view .LVU1108 + 3544 0030 C0F84034 str r3, [r0, #1088] + 3545 .L228: +1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 3546 .loc 1 1504 3 is_stmt 1 view .LVU1109 +1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3547 .loc 1 1505 1 is_stmt 0 view .LVU1110 + 3548 0034 0020 movs r0, #0 + 3549 .LVL303: + 3550 .loc 1 1505 1 view .LVU1111 + 3551 0036 02B0 add sp, sp, #8 + 3552 .LCFI38: + 3553 .cfi_remember_state + 3554 .cfi_def_cfa_offset 0 + 3555 @ sp needed + 3556 0038 7047 bx lr + 3557 .LVL304: + 3558 .L230: + 3559 .LCFI39: + 3560 .cfi_restore_state +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3561 .loc 1 1498 5 is_stmt 1 view .LVU1112 +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3562 .loc 1 1498 37 is_stmt 0 view .LVU1113 + 3563 003a 019B ldr r3, [sp, #4] + 3564 003c 43F48053 orr r3, r3, #4096 +1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3565 .loc 1 1498 16 view .LVU1114 + 3566 0040 C0F84034 str r3, [r0, #1088] + 3567 0044 ECE7 b .L227 + 3568 .cfi_endproc + 3569 .LFE178: + 3571 .section .text.USB_HostInit,"ax",%progbits + 3572 .align 1 + 3573 .global USB_HostInit + 3574 .syntax unified + 3575 .thumb + 3576 .thumb_func + 3577 .fpu fpv5-d16 + 3579 USB_HostInit: + 3580 .LVL305: + 3581 .LFB175: +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + ARM GAS /tmp/cc9mtr28.s page 107 + + + 3582 .loc 1 1335 1 is_stmt 1 view -0 + 3583 .cfi_startproc + 3584 @ args = 56, pretend = 16, frame = 0 + 3585 @ frame_needed = 0, uses_anonymous_args = 0 +1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3586 .loc 1 1335 1 is_stmt 0 view .LVU1116 + 3587 0000 84B0 sub sp, sp, #16 + 3588 .LCFI40: + 3589 .cfi_def_cfa_offset 16 + 3590 0002 10B5 push {r4, lr} + 3591 .LCFI41: + 3592 .cfi_def_cfa_offset 24 + 3593 .cfi_offset 4, -24 + 3594 .cfi_offset 14, -20 + 3595 0004 0446 mov r4, r0 + 3596 0006 03A8 add r0, sp, #12 + 3597 0008 80E80E00 stm r0, {r1, r2, r3} +1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 3598 .loc 1 1336 3 is_stmt 1 view .LVU1117 + 3599 .LVL306: +1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3600 .loc 1 1337 3 view .LVU1118 +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3601 .loc 1 1340 3 view .LVU1119 +1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3602 .loc 1 1340 16 is_stmt 0 view .LVU1120 + 3603 000c 0023 movs r3, #0 + 3604 000e C4F8003E str r3, [r4, #3584] +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3605 .loc 1 1343 3 is_stmt 1 view .LVU1121 +1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3606 .loc 1 1343 15 is_stmt 0 view .LVU1122 + 3607 0012 A36B ldr r3, [r4, #56] + 3608 0014 23F40013 bic r3, r3, #2097152 + 3609 0018 A363 str r3, [r4, #56] +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3610 .loc 1 1346 3 is_stmt 1 view .LVU1123 +1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3611 .loc 1 1346 15 is_stmt 0 view .LVU1124 + 3612 001a A36B ldr r3, [r4, #56] + 3613 001c 23F40033 bic r3, r3, #131072 + 3614 0020 A363 str r3, [r4, #56] +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3615 .loc 1 1349 3 is_stmt 1 view .LVU1125 +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3616 .loc 1 1349 12 is_stmt 0 view .LVU1126 + 3617 0022 E36B ldr r3, [r4, #60] +1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3618 .loc 1 1349 6 view .LVU1127 + 3619 0024 13F4807F tst r3, #256 + 3620 0028 10D0 beq .L232 +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3621 .loc 1 1351 5 is_stmt 1 view .LVU1128 +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3622 .loc 1 1351 12 is_stmt 0 view .LVU1129 + 3623 002a 059B ldr r3, [sp, #20] +1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 108 + + + 3624 .loc 1 1351 8 view .LVU1130 + 3625 002c 012B cmp r3, #1 + 3626 002e 06D0 beq .L241 +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3627 .loc 1 1359 7 is_stmt 1 view .LVU1131 +1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3628 .loc 1 1359 23 is_stmt 0 view .LVU1132 + 3629 0030 D4F80034 ldr r3, [r4, #1024] + 3630 0034 23F00403 bic r3, r3, #4 + 3631 0038 C4F80034 str r3, [r4, #1024] + 3632 003c 0CE0 b .L234 + 3633 .L241: +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3634 .loc 1 1354 7 is_stmt 1 view .LVU1133 +1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3635 .loc 1 1354 23 is_stmt 0 view .LVU1134 + 3636 003e D4F80034 ldr r3, [r4, #1024] + 3637 0042 43F00403 orr r3, r3, #4 + 3638 0046 C4F80034 str r3, [r4, #1024] + 3639 004a 05E0 b .L234 + 3640 .L232: +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3641 .loc 1 1365 5 is_stmt 1 view .LVU1135 +1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3642 .loc 1 1365 21 is_stmt 0 view .LVU1136 + 3643 004c D4F80034 ldr r3, [r4, #1024] + 3644 0050 23F00403 bic r3, r3, #4 + 3645 0054 C4F80034 str r3, [r4, #1024] + 3646 .L234: +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushRxFifo(USBx); + 3647 .loc 1 1369 3 is_stmt 1 view .LVU1137 +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushRxFifo(USBx); + 3648 .loc 1 1369 9 is_stmt 0 view .LVU1138 + 3649 0058 1021 movs r1, #16 + 3650 005a 2046 mov r0, r4 + 3651 .LVL307: +1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushRxFifo(USBx); + 3652 .loc 1 1369 9 view .LVU1139 + 3653 005c FFF7FEFF bl USB_FlushTxFifo + 3654 .LVL308: +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3655 .loc 1 1370 3 is_stmt 1 view .LVU1140 +1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3656 .loc 1 1370 9 is_stmt 0 view .LVU1141 + 3657 0060 2046 mov r0, r4 + 3658 0062 FFF7FEFF bl USB_FlushRxFifo + 3659 .LVL309: +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3660 .loc 1 1373 3 is_stmt 1 view .LVU1142 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3661 .loc 1 1373 10 is_stmt 0 view .LVU1143 + 3662 0066 0022 movs r2, #0 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3663 .loc 1 1373 3 view .LVU1144 + 3664 0068 09E0 b .L235 + 3665 .LVL310: + 3666 .L236: + ARM GAS /tmp/cc9mtr28.s page 109 + + +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(i)->HCINTMSK = 0U; + 3667 .loc 1 1375 5 is_stmt 1 discriminator 3 view .LVU1145 + 3668 006a 04EB4213 add r3, r4, r2, lsl #5 +1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(i)->HCINTMSK = 0U; + 3669 .loc 1 1375 23 is_stmt 0 discriminator 3 view .LVU1146 + 3670 006e 4FF0FF31 mov r1, #-1 + 3671 0072 C3F80815 str r1, [r3, #1288] +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3672 .loc 1 1376 5 is_stmt 1 discriminator 3 view .LVU1147 +1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3673 .loc 1 1376 26 is_stmt 0 discriminator 3 view .LVU1148 + 3674 0076 0021 movs r1, #0 + 3675 0078 C3F80C15 str r1, [r3, #1292] +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3676 .loc 1 1373 39 is_stmt 1 discriminator 3 view .LVU1149 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3677 .loc 1 1373 40 is_stmt 0 discriminator 3 view .LVU1150 + 3678 007c 0132 adds r2, r2, #1 + 3679 .LVL311: + 3680 .L235: +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3681 .loc 1 1373 16 is_stmt 1 discriminator 1 view .LVU1151 +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3682 .loc 1 1373 23 is_stmt 0 discriminator 1 view .LVU1152 + 3683 007e 049B ldr r3, [sp, #16] +1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3684 .loc 1 1373 3 discriminator 1 view .LVU1153 + 3685 0080 9342 cmp r3, r2 + 3686 0082 F2D8 bhi .L236 +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3687 .loc 1 1380 3 is_stmt 1 view .LVU1154 +1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3688 .loc 1 1380 9 is_stmt 0 view .LVU1155 + 3689 0084 0121 movs r1, #1 + 3690 0086 2046 mov r0, r4 + 3691 0088 FFF7FEFF bl USB_DriveVbus + 3692 .LVL312: +1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3693 .loc 1 1382 3 is_stmt 1 view .LVU1156 + 3694 008c C820 movs r0, #200 + 3695 008e FFF7FEFF bl HAL_Delay + 3696 .LVL313: +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3697 .loc 1 1385 3 view .LVU1157 +1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3698 .loc 1 1385 17 is_stmt 0 view .LVU1158 + 3699 0092 0023 movs r3, #0 + 3700 0094 A361 str r3, [r4, #24] +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3701 .loc 1 1388 3 is_stmt 1 view .LVU1159 +1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3702 .loc 1 1388 17 is_stmt 0 view .LVU1160 + 3703 0096 4FF0FF33 mov r3, #-1 + 3704 009a 6361 str r3, [r4, #20] +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3705 .loc 1 1390 3 is_stmt 1 view .LVU1161 +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 110 + + + 3706 .loc 1 1390 12 is_stmt 0 view .LVU1162 + 3707 009c E36B ldr r3, [r4, #60] +1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3708 .loc 1 1390 6 view .LVU1163 + 3709 009e 13F4807F tst r3, #256 + 3710 00a2 17D0 beq .L237 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + 3711 .loc 1 1393 5 is_stmt 1 view .LVU1164 +1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + 3712 .loc 1 1393 20 is_stmt 0 view .LVU1165 + 3713 00a4 4FF40073 mov r3, #512 + 3714 00a8 6362 str r3, [r4, #36] +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + 3715 .loc 1 1394 5 is_stmt 1 view .LVU1166 +1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + 3716 .loc 1 1394 30 is_stmt 0 view .LVU1167 + 3717 00aa 03F18073 add r3, r3, #16777216 + 3718 00ae A362 str r3, [r4, #40] +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3719 .loc 1 1395 5 is_stmt 1 view .LVU1168 +1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3720 .loc 1 1395 20 is_stmt 0 view .LVU1169 + 3721 00b0 0D4B ldr r3, .L242 + 3722 00b2 C4F80031 str r3, [r4, #256] + 3723 .L238: +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3724 .loc 1 1406 3 is_stmt 1 view .LVU1170 +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3725 .loc 1 1406 10 is_stmt 0 view .LVU1171 + 3726 00b6 069B ldr r3, [sp, #24] +1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3727 .loc 1 1406 6 view .LVU1172 + 3728 00b8 1BB9 cbnz r3, .L239 +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3729 .loc 1 1408 5 is_stmt 1 view .LVU1173 +1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3730 .loc 1 1408 19 is_stmt 0 view .LVU1174 + 3731 00ba A369 ldr r3, [r4, #24] + 3732 00bc 43F01003 orr r3, r3, #16 + 3733 00c0 A361 str r3, [r4, #24] + 3734 .L239: +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + 3735 .loc 1 1412 3 is_stmt 1 view .LVU1175 +1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + 3736 .loc 1 1412 17 is_stmt 0 view .LVU1176 + 3737 00c2 A269 ldr r2, [r4, #24] + 3738 00c4 094B ldr r3, .L242+4 + 3739 00c6 1343 orrs r3, r3, r2 + 3740 00c8 A361 str r3, [r4, #24] +1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3741 .loc 1 1416 3 is_stmt 1 view .LVU1177 +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3742 .loc 1 1417 1 is_stmt 0 view .LVU1178 + 3743 00ca 0020 movs r0, #0 + 3744 00cc BDE81040 pop {r4, lr} + 3745 .LCFI42: + 3746 .cfi_remember_state + ARM GAS /tmp/cc9mtr28.s page 111 + + + 3747 .cfi_restore 14 + 3748 .cfi_restore 4 + 3749 .cfi_def_cfa_offset 16 + 3750 .LVL314: +1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 3751 .loc 1 1417 1 view .LVU1179 + 3752 00d0 04B0 add sp, sp, #16 + 3753 .LCFI43: + 3754 .cfi_def_cfa_offset 0 + 3755 00d2 7047 bx lr + 3756 .LVL315: + 3757 .L237: + 3758 .LCFI44: + 3759 .cfi_restore_state +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + 3760 .loc 1 1400 5 is_stmt 1 view .LVU1180 +1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + 3761 .loc 1 1400 20 is_stmt 0 view .LVU1181 + 3762 00d4 8023 movs r3, #128 + 3763 00d6 6362 str r3, [r4, #36] +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + 3764 .loc 1 1401 5 is_stmt 1 view .LVU1182 +1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + 3765 .loc 1 1401 30 is_stmt 0 view .LVU1183 + 3766 00d8 03F5C003 add r3, r3, #6291456 + 3767 00dc A362 str r3, [r4, #40] +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3768 .loc 1 1402 5 is_stmt 1 view .LVU1184 +1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3769 .loc 1 1402 20 is_stmt 0 view .LVU1185 + 3770 00de 044B ldr r3, .L242+8 + 3771 00e0 C4F80031 str r3, [r4, #256] + 3772 00e4 E7E7 b .L238 + 3773 .L243: + 3774 00e6 00BF .align 2 + 3775 .L242: + 3776 00e8 0003E000 .word 14680832 + 3777 00ec 080020A3 .word -1558183928 + 3778 00f0 E0004000 .word 4194528 + 3779 .cfi_endproc + 3780 .LFE175: + 3782 .section .text.USB_GetHostSpeed,"ax",%progbits + 3783 .align 1 + 3784 .global USB_GetHostSpeed + 3785 .syntax unified + 3786 .thumb + 3787 .thumb_func + 3788 .fpu fpv5-d16 + 3790 USB_GetHostSpeed: + 3791 .LVL316: + 3792 .LFB179: +1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Return Host Core speed +1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval speed : Host speed +1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: + ARM GAS /tmp/cc9mtr28.s page 112 + + +1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg HCD_SPEED_HIGH: High speed mode +1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg HCD_SPEED_FULL: Full speed mode +1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg HCD_SPEED_LOW: Low speed mode +1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3793 .loc 1 1517 1 is_stmt 1 view -0 + 3794 .cfi_startproc + 3795 @ args = 0, pretend = 0, frame = 8 + 3796 @ frame_needed = 0, uses_anonymous_args = 0 + 3797 @ link register save eliminated. + 3798 .loc 1 1517 1 is_stmt 0 view .LVU1187 + 3799 0000 82B0 sub sp, sp, #8 + 3800 .LCFI45: + 3801 .cfi_def_cfa_offset 8 +1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3802 .loc 1 1518 3 is_stmt 1 view .LVU1188 + 3803 .LVL317: +1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** __IO uint32_t hprt0 = 0U; + 3804 .loc 1 1519 3 view .LVU1189 + 3805 .loc 1 1519 17 is_stmt 0 view .LVU1190 + 3806 0002 0023 movs r3, #0 + 3807 0004 0193 str r3, [sp, #4] +1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hprt0 = USBx_HPRT0; + 3808 .loc 1 1521 3 is_stmt 1 view .LVU1191 + 3809 .loc 1 1521 11 is_stmt 0 view .LVU1192 + 3810 0006 D0F84034 ldr r3, [r0, #1088] + 3811 .loc 1 1521 9 view .LVU1193 + 3812 000a 0193 str r3, [sp, #4] +1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); + 3813 .loc 1 1522 3 is_stmt 1 view .LVU1194 + 3814 .loc 1 1522 39 is_stmt 0 view .LVU1195 + 3815 000c 0198 ldr r0, [sp, #4] + 3816 .LVL318: +1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3817 .loc 1 1523 1 view .LVU1196 + 3818 000e C0F34140 ubfx r0, r0, #17, #2 + 3819 0012 02B0 add sp, sp, #8 + 3820 .LCFI46: + 3821 .cfi_def_cfa_offset 0 + 3822 @ sp needed + 3823 0014 7047 bx lr + 3824 .cfi_endproc + 3825 .LFE179: + 3827 .section .text.USB_GetCurrentFrame,"ax",%progbits + 3828 .align 1 + 3829 .global USB_GetCurrentFrame + 3830 .syntax unified + 3831 .thumb + 3832 .thumb_func + 3833 .fpu fpv5-d16 + 3835 USB_GetCurrentFrame: + 3836 .LVL319: + 3837 .LFB180: +1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** + ARM GAS /tmp/cc9mtr28.s page 113 + + +1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Return Host Current Frame number +1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval current frame number +1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3838 .loc 1 1531 1 is_stmt 1 view -0 + 3839 .cfi_startproc + 3840 @ args = 0, pretend = 0, frame = 0 + 3841 @ frame_needed = 0, uses_anonymous_args = 0 + 3842 @ link register save eliminated. +1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3843 .loc 1 1532 3 view .LVU1198 +1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); + 3844 .loc 1 1534 3 view .LVU1199 + 3845 .loc 1 1534 11 is_stmt 0 view .LVU1200 + 3846 0000 00F58060 add r0, r0, #1024 + 3847 .LVL320: + 3848 .loc 1 1534 20 view .LVU1201 + 3849 0004 8068 ldr r0, [r0, #8] + 3850 .LVL321: +1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3851 .loc 1 1535 1 view .LVU1202 + 3852 0006 80B2 uxth r0, r0 + 3853 0008 7047 bx lr + 3854 .cfi_endproc + 3855 .LFE180: + 3857 .section .text.USB_HC_Init,"ax",%progbits + 3858 .align 1 + 3859 .global USB_HC_Init + 3860 .syntax unified + 3861 .thumb + 3862 .thumb_func + 3863 .fpu fpv5-d16 + 3865 USB_HC_Init: + 3866 .LVL322: + 3867 .LFB181: +1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Initialize a host channel +1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ch_num Channel number +1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 1 to 15 +1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param epnum Endpoint number +1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 1 to 15 +1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dev_address Current device address +1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 0 to 255 +1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param speed Current device speed +1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_OTG_SPEED_HIGH: High speed mode +1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_OTG_SPEED_FULL: Full speed mode +1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg USB_OTG_SPEED_LOW: Low speed mode +1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param ep_type Endpoint Type +1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg EP_TYPE_CTRL: Control type +1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg EP_TYPE_ISOC: Isochronous type + ARM GAS /tmp/cc9mtr28.s page 114 + + +1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg EP_TYPE_BULK: Bulk type +1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @arg EP_TYPE_INTR: Interrupt type +1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param mps Max Packet Size +1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 0 to32K +1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL state +1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, +1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t ch_num, +1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t epnum, +1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t dev_address, +1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t speed, +1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t ep_type, +1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t mps) +1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 3868 .loc 1 1568 1 is_stmt 1 view -0 + 3869 .cfi_startproc + 3870 @ args = 12, pretend = 0, frame = 0 + 3871 @ frame_needed = 0, uses_anonymous_args = 0 + 3872 .loc 1 1568 1 is_stmt 0 view .LVU1204 + 3873 0000 F0B5 push {r4, r5, r6, r7, lr} + 3874 .LCFI47: + 3875 .cfi_def_cfa_offset 20 + 3876 .cfi_offset 4, -20 + 3877 .cfi_offset 5, -16 + 3878 .cfi_offset 6, -12 + 3879 .cfi_offset 7, -8 + 3880 .cfi_offset 14, -4 + 3881 0002 0446 mov r4, r0 + 3882 0004 9DF818C0 ldrb ip, [sp, #24] @ zero_extendqisi2 +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef ret = HAL_OK; + 3883 .loc 1 1569 3 is_stmt 1 view .LVU1205 + 3884 .LVL323: +1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3885 .loc 1 1570 3 view .LVU1206 +1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t HCcharEpDir, HCcharLowSpeed; + 3886 .loc 1 1571 3 view .LVU1207 +1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear old interrupt conditions for this host channel. */ +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + 3887 .loc 1 1574 3 view .LVU1208 + 3888 0008 00EB411E add lr, r0, r1, lsl #5 + 3889 000c 0EF5A060 add r0, lr, #1280 + 3890 .LVL324: + 3891 .loc 1 1574 36 is_stmt 0 view .LVU1209 + 3892 0010 4FF0FF35 mov r5, #-1 + 3893 0014 8560 str r5, [r0, #8] +1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable channel interrupts required for this transfer. */ +1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** switch (ep_type) + 3894 .loc 1 1577 3 is_stmt 1 view .LVU1210 + 3895 0016 BCF1030F cmp ip, #3 + 3896 001a 64D8 bhi .L257 + 3897 001c DFE80CF0 tbb [pc, ip] + 3898 .L250: + 3899 0020 02 .byte (.L251-.L250)/2 + 3900 0021 55 .byte (.L252-.L250)/2 + 3901 0022 02 .byte (.L251-.L250)/2 + ARM GAS /tmp/cc9mtr28.s page 115 + + + 3902 0023 18 .byte (.L249-.L250)/2 + 3903 .p2align 1 + 3904 .L251: +1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_CTRL: +1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_BULK: +1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + 3905 .loc 1 1581 7 view .LVU1211 + 3906 .loc 1 1581 43 is_stmt 0 view .LVU1212 + 3907 0024 40F29D45 movw r5, #1181 + 3908 0028 C560 str r5, [r0, #12] +1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_STALLM | +1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_TXERRM | +1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_DTERRM | +1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_AHBERR | +1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_NAKM; +1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((epnum & 0x80U) == 0x80U) + 3909 .loc 1 1588 7 is_stmt 1 view .LVU1213 + 3910 .loc 1 1588 10 is_stmt 0 view .LVU1214 + 3911 002a 12F0800F tst r2, #128 + 3912 002e 09D1 bne .L264 +1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; +1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx->CID & (0x1U << 8)) != 0U) + 3913 .loc 1 1594 9 is_stmt 1 view .LVU1215 + 3914 .loc 1 1594 18 is_stmt 0 view .LVU1216 + 3915 0030 E56B ldr r5, [r4, #60] + 3916 .loc 1 1594 12 view .LVU1217 + 3917 0032 15F4807F tst r5, #256 + 3918 0036 58D0 beq .L258 +1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + 3919 .loc 1 1596 11 is_stmt 1 view .LVU1218 + 3920 .loc 1 1596 47 is_stmt 0 view .LVU1219 + 3921 0038 C568 ldr r5, [r0, #12] + 3922 003a 45F06005 orr r5, r5, #96 + 3923 003e C560 str r5, [r0, #12] +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3924 .loc 1 1569 21 view .LVU1220 + 3925 0040 0020 movs r0, #0 + 3926 0042 0CE0 b .L248 + 3927 .L264: +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3928 .loc 1 1590 9 is_stmt 1 view .LVU1221 +1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 3929 .loc 1 1590 45 is_stmt 0 view .LVU1222 + 3930 0044 C568 ldr r5, [r0, #12] + 3931 0046 45F48075 orr r5, r5, #256 + 3932 004a C560 str r5, [r0, #12] +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3933 .loc 1 1569 21 view .LVU1223 + 3934 004c 0020 movs r0, #0 + 3935 004e 06E0 b .L248 + ARM GAS /tmp/cc9mtr28.s page 116 + + + 3936 .L249: +1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_INTR: +1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + 3937 .loc 1 1602 7 is_stmt 1 view .LVU1224 + 3938 .loc 1 1602 43 is_stmt 0 view .LVU1225 + 3939 0050 40F29D65 movw r5, #1693 + 3940 0054 C560 str r5, [r0, #12] +1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_STALLM | +1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_TXERRM | +1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_DTERRM | +1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_NAKM | +1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_AHBERR | +1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_FRMORM; +1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((epnum & 0x80U) == 0x80U) + 3941 .loc 1 1610 7 is_stmt 1 view .LVU1226 + 3942 .loc 1 1610 10 is_stmt 0 view .LVU1227 + 3943 0056 12F0800F tst r2, #128 + 3944 005a 30D1 bne .L265 +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 3945 .loc 1 1569 21 view .LVU1228 + 3946 005c 0020 movs r0, #0 + 3947 .L248: + 3948 .LVL325: +1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; +1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_ISOC: +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | +1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_ACKM | +1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_AHBERR | +1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_FRMORM; +1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((epnum & 0x80U) == 0x80U) +1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); +1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** default: +1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ret = HAL_ERROR; +1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Enable the top level host channel interrupt. */ +1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + 3949 .loc 1 1635 3 is_stmt 1 view .LVU1229 + 3950 .loc 1 1635 23 is_stmt 0 view .LVU1230 + 3951 005e D4F81854 ldr r5, [r4, #1048] + 3952 .loc 1 1635 41 view .LVU1231 + ARM GAS /tmp/cc9mtr28.s page 117 + + + 3953 0062 01F00F01 and r1, r1, #15 + 3954 .LVL326: + 3955 .loc 1 1635 30 view .LVU1232 + 3956 0066 0126 movs r6, #1 + 3957 0068 06FA01F1 lsl r1, r6, r1 + 3958 .loc 1 1635 23 view .LVU1233 + 3959 006c 2943 orrs r1, r1, r5 + 3960 006e C4F81814 str r1, [r4, #1048] +1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Make sure host channel interrupts are enabled. */ +1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + 3961 .loc 1 1638 3 is_stmt 1 view .LVU1234 + 3962 .loc 1 1638 17 is_stmt 0 view .LVU1235 + 3963 0072 A169 ldr r1, [r4, #24] + 3964 0074 41F00071 orr r1, r1, #33554432 + 3965 0078 A161 str r1, [r4, #24] +1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Program the HCCHAR register */ +1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((epnum & 0x80U) == 0x80U) + 3966 .loc 1 1641 3 is_stmt 1 view .LVU1236 + 3967 .loc 1 1641 6 is_stmt 0 view .LVU1237 + 3968 007a 12F0800F tst r2, #128 + 3969 007e 36D1 bne .L266 +1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; +1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HCcharEpDir = 0U; + 3970 .loc 1 1647 17 view .LVU1238 + 3971 0080 0024 movs r4, #0 + 3972 .LVL327: + 3973 .L254: +1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (speed == HPRT0_PRTSPD_LOW_SPEED) + 3974 .loc 1 1650 3 is_stmt 1 view .LVU1239 + 3975 .loc 1 1650 6 is_stmt 0 view .LVU1240 + 3976 0082 9DF81410 ldrb r1, [sp, #20] @ zero_extendqisi2 + 3977 0086 0229 cmp r1, #2 + 3978 0088 34D0 beq .L267 +1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; +1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HCcharLowSpeed = 0U; + 3979 .loc 1 1656 20 view .LVU1241 + 3980 008a 0021 movs r1, #0 + 3981 .L255: + 3982 .LVL328: +1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + 3983 .loc 1 1659 3 is_stmt 1 view .LVU1242 + 3984 .loc 1 1659 63 is_stmt 0 view .LVU1243 + 3985 008c 9B05 lsls r3, r3, #22 + ARM GAS /tmp/cc9mtr28.s page 118 + + + 3986 .LVL329: + 3987 .loc 1 1659 70 view .LVU1244 + 3988 008e 03F0FE53 and r3, r3, #532676608 +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + 3989 .loc 1 1660 67 view .LVU1245 + 3990 0092 D202 lsls r2, r2, #11 + 3991 .LVL330: + 3992 .loc 1 1660 74 view .LVU1246 + 3993 0094 02F4F042 and r2, r2, #30720 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + 3994 .loc 1 1659 92 view .LVU1247 + 3995 0098 1343 orrs r3, r3, r2 +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + 3996 .loc 1 1661 59 view .LVU1248 + 3997 009a 4FEA8C42 lsl r2, ip, #18 + 3998 .loc 1 1661 66 view .LVU1249 + 3999 009e 02F44022 and r2, r2, #786432 +1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + 4000 .loc 1 1660 98 view .LVU1250 + 4001 00a2 1343 orrs r3, r3, r2 +1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCchar + 4002 .loc 1 1662 54 view .LVU1251 + 4003 00a4 BDF81C20 ldrh r2, [sp, #28] + 4004 00a8 C2F30A02 ubfx r2, r2, #0, #11 +1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + 4005 .loc 1 1661 90 view .LVU1252 + 4006 00ac 1343 orrs r3, r3, r2 + 4007 .loc 1 1662 78 view .LVU1253 + 4008 00ae 2343 orrs r3, r3, r4 + 4009 .loc 1 1662 92 view .LVU1254 + 4010 00b0 0B43 orrs r3, r3, r1 +1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + 4011 .loc 1 1659 37 view .LVU1255 + 4012 00b2 CEF80035 str r3, [lr, #1280] +1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (ep_type == EP_TYPE_INTR) + 4013 .loc 1 1664 3 is_stmt 1 view .LVU1256 + 4014 .loc 1 1664 6 is_stmt 0 view .LVU1257 + 4015 00b6 BCF1030F cmp ip, #3 + 4016 00ba 1ED0 beq .L268 + 4017 .L256: +1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; +1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ret; + 4018 .loc 1 1669 3 is_stmt 1 view .LVU1258 +1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4019 .loc 1 1670 1 is_stmt 0 view .LVU1259 + 4020 00bc F0BD pop {r4, r5, r6, r7, pc} + 4021 .LVL331: + 4022 .L265: +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4023 .loc 1 1612 9 is_stmt 1 view .LVU1260 +1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4024 .loc 1 1612 45 is_stmt 0 view .LVU1261 + 4025 00be C568 ldr r5, [r0, #12] + ARM GAS /tmp/cc9mtr28.s page 119 + + + 4026 00c0 45F48075 orr r5, r5, #256 + 4027 00c4 C560 str r5, [r0, #12] +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4028 .loc 1 1569 21 view .LVU1262 + 4029 00c6 0020 movs r0, #0 + 4030 00c8 C9E7 b .L248 + 4031 .L252: +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_ACKM | + 4032 .loc 1 1618 7 is_stmt 1 view .LVU1263 +1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCINTMSK_ACKM | + 4033 .loc 1 1618 43 is_stmt 0 view .LVU1264 + 4034 00ca 40F22525 movw r5, #549 + 4035 00ce C560 str r5, [r0, #12] +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4036 .loc 1 1623 7 is_stmt 1 view .LVU1265 +1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4037 .loc 1 1623 10 is_stmt 0 view .LVU1266 + 4038 00d0 12F0800F tst r2, #128 + 4039 00d4 01D1 bne .L269 +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4040 .loc 1 1569 21 view .LVU1267 + 4041 00d6 0020 movs r0, #0 + 4042 00d8 C1E7 b .L248 + 4043 .L269: +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4044 .loc 1 1625 9 is_stmt 1 view .LVU1268 +1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4045 .loc 1 1625 45 is_stmt 0 view .LVU1269 + 4046 00da C568 ldr r5, [r0, #12] + 4047 00dc 45F4C075 orr r5, r5, #384 + 4048 00e0 C560 str r5, [r0, #12] +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4049 .loc 1 1569 21 view .LVU1270 + 4050 00e2 0020 movs r0, #0 + 4051 00e4 BBE7 b .L248 + 4052 .L257: +1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4053 .loc 1 1574 36 view .LVU1271 + 4054 00e6 0120 movs r0, #1 + 4055 00e8 B9E7 b .L248 + 4056 .L258: +1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4057 .loc 1 1569 21 view .LVU1272 + 4058 00ea 0020 movs r0, #0 + 4059 00ec B7E7 b .L248 + 4060 .LVL332: + 4061 .L266: +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4062 .loc 1 1643 17 view .LVU1273 + 4063 00ee 4FF40044 mov r4, #32768 + 4064 .LVL333: +1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4065 .loc 1 1643 17 view .LVU1274 + 4066 00f2 C6E7 b .L254 + 4067 .LVL334: + 4068 .L267: +1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + ARM GAS /tmp/cc9mtr28.s page 120 + + + 4069 .loc 1 1652 20 view .LVU1275 + 4070 00f4 4FF40031 mov r1, #131072 + 4071 00f8 C8E7 b .L255 + 4072 .LVL335: + 4073 .L268: +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4074 .loc 1 1666 5 is_stmt 1 view .LVU1276 +1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4075 .loc 1 1666 39 is_stmt 0 view .LVU1277 + 4076 00fa DEF80035 ldr r3, [lr, #1280] + 4077 00fe 43F00053 orr r3, r3, #536870912 + 4078 0102 CEF80035 str r3, [lr, #1280] + 4079 0106 D9E7 b .L256 + 4080 .cfi_endproc + 4081 .LFE181: + 4083 .section .text.USB_HC_ReadInterrupt,"ax",%progbits + 4084 .align 1 + 4085 .global USB_HC_ReadInterrupt + 4086 .syntax unified + 4087 .thumb + 4088 .thumb_func + 4089 .fpu fpv5-d16 + 4091 USB_HC_ReadInterrupt: + 4092 .LVL336: + 4093 .LFB183: +1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Start a transfer over a host channel +1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param hc pointer to host channel structure +1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param dma USB dma enabled or disabled +1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be one of these values: +1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 0 : DMA feature not used +1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * 1 : DMA feature used +1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL state +1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t ch_num = (uint32_t)hc->ch_num; +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** static __IO uint32_t tmpreg = 0U; +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t is_oddframe; +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t len_words; +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t num_packets; +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t max_hc_pkt_count = 256U; +1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) +1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((dma == 0U) && (hc->do_ping == 1U)) +1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_DoPing(USBx, hc->ch_num); +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else if (dma == 1U) +1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->do_ping = 0U; + ARM GAS /tmp/cc9mtr28.s page 121 + + +1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* ... */ +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Compute the expected number of packets associated to the transfer */ +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (hc->xfer_len > 0U) +1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); +1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (num_packets > max_hc_pkt_count) +1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** num_packets = max_hc_pkt_count; +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->xfer_len = (uint32_t)num_packets * hc->max_packet; +1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** num_packets = 1U; +1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (hc->ep_is_in != 0U) +1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->xfer_len = (uint32_t)num_packets * hc->max_packet; +1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Initialize the HCTSIZn register */ +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); +1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma != 0U) +1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* xfer_buff MUST be 32-bits aligned */ +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; +1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; +1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set host channel enable */ +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_HC(ch_num)->HCCHAR; +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= ~USB_OTG_HCCHAR_CHDIS; +1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* make sure to set the correct ep direction */ +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (hc->ep_is_in != 0U) +1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg |= USB_OTG_HCCHAR_EPDIR; +1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= ~USB_OTG_HCCHAR_EPDIR; +1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg |= USB_OTG_HCCHAR_CHENA; +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR = tmpreg; + ARM GAS /tmp/cc9mtr28.s page 122 + + +1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (dma == 0U) /* Slave mode */ +1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) +1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** switch (hc->ep_type) +1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Non periodic transfer */ +1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_CTRL: +1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_BULK: +1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); +1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* check if there is enough space in FIFO space */ +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) +1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* need to process data in nptxfempty interrupt */ +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; +1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Periodic transfer */ +1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_INTR: +1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** case EP_TYPE_ISOC: +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); +1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* check if there is enough space in FIFO space */ +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ +1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* need to process data in ptxfempty interrupt */ +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; +1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** default: +1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Write packet into the Tx FIFO. */ +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); +1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Read all host channel interrupts status +1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL state +1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4094 .loc 1 1811 1 is_stmt 1 view -0 + 4095 .cfi_startproc + 4096 @ args = 0, pretend = 0, frame = 0 + 4097 @ frame_needed = 0, uses_anonymous_args = 0 + 4098 @ link register save eliminated. + ARM GAS /tmp/cc9mtr28.s page 123 + + +1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4099 .loc 1 1812 3 view .LVU1279 +1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return ((USBx_HOST->HAINT) & 0xFFFFU); + 4100 .loc 1 1814 3 view .LVU1280 + 4101 .loc 1 1814 12 is_stmt 0 view .LVU1281 + 4102 0000 00F58060 add r0, r0, #1024 + 4103 .LVL337: + 4104 .loc 1 1814 21 view .LVU1282 + 4105 0004 4069 ldr r0, [r0, #20] + 4106 .LVL338: +1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4107 .loc 1 1815 1 view .LVU1283 + 4108 0006 80B2 uxth r0, r0 + 4109 0008 7047 bx lr + 4110 .cfi_endproc + 4111 .LFE183: + 4113 .section .text.USB_HC_Halt,"ax",%progbits + 4114 .align 1 + 4115 .global USB_HC_Halt + 4116 .syntax unified + 4117 .thumb + 4118 .thumb_func + 4119 .fpu fpv5-d16 + 4121 USB_HC_Halt: + 4122 .LVL339: + 4123 .LFB184: +1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Halt a host channel +1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param hc_num Host Channel number +1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 1 to 15 +1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL state +1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4124 .loc 1 1825 1 is_stmt 1 view -0 + 4125 .cfi_startproc + 4126 @ args = 0, pretend = 0, frame = 0 + 4127 @ frame_needed = 0, uses_anonymous_args = 0 + 4128 @ link register save eliminated. +1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4129 .loc 1 1826 3 view .LVU1285 +1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t hcnum = (uint32_t)hc_num; + 4130 .loc 1 1827 3 view .LVU1286 +1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0U; + 4131 .loc 1 1828 3 view .LVU1287 +1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + 4132 .loc 1 1829 3 view .LVU1288 + 4133 .loc 1 1829 24 is_stmt 0 view .LVU1289 + 4134 0000 00EB4111 add r1, r0, r1, lsl #5 + 4135 .LVL340: + 4136 .loc 1 1829 24 view .LVU1290 + 4137 0004 01F5A06C add ip, r1, #1280 + 4138 .loc 1 1829 38 view .LVU1291 + 4139 0008 D1F80035 ldr r3, [r1, #1280] + ARM GAS /tmp/cc9mtr28.s page 124 + + + 4140 .loc 1 1829 12 view .LVU1292 + 4141 000c C3F38142 ubfx r2, r3, #18, #2 + 4142 .LVL341: +1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Check for space in the request queue to issue the halt. */ +1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + 4143 .loc 1 1832 3 is_stmt 1 view .LVU1293 + 4144 .loc 1 1832 17 is_stmt 0 view .LVU1294 + 4145 0010 13F4402F tst r3, #786432 + 4146 0014 0CBF ite eq + 4147 0016 0123 moveq r3, #1 + 4148 0018 0023 movne r3, #0 + 4149 .loc 1 1832 33 view .LVU1295 + 4150 001a 022A cmp r2, #2 + 4151 001c 08BF it eq + 4152 001e 43F00103 orreq r3, r3, #1 + 4153 .loc 1 1832 6 view .LVU1296 + 4154 0022 63B3 cbz r3, .L272 +1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + 4155 .loc 1 1834 5 is_stmt 1 view .LVU1297 + 4156 .loc 1 1834 28 is_stmt 0 view .LVU1298 + 4157 0024 D1F80035 ldr r3, [r1, #1280] + 4158 0028 43F08043 orr r3, r3, #1073741824 + 4159 002c C1F80035 str r3, [r1, #1280] +1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + 4160 .loc 1 1836 5 is_stmt 1 view .LVU1299 + 4161 .loc 1 1836 14 is_stmt 0 view .LVU1300 + 4162 0030 C36A ldr r3, [r0, #44] + 4163 .loc 1 1836 8 view .LVU1301 + 4164 0032 13F47F03 ands r3, r3, #16711680 + 4165 0036 1AD1 bne .L273 +1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + 4166 .loc 1 1838 7 is_stmt 1 view .LVU1302 + 4167 .loc 1 1838 30 is_stmt 0 view .LVU1303 + 4168 0038 D1F80025 ldr r2, [r1, #1280] + 4169 .LVL342: + 4170 .loc 1 1838 30 view .LVU1304 + 4171 003c 22F00042 bic r2, r2, #-2147483648 + 4172 0040 C1F80025 str r2, [r1, #1280] +1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 4173 .loc 1 1839 7 is_stmt 1 view .LVU1305 + 4174 .loc 1 1839 30 is_stmt 0 view .LVU1306 + 4175 0044 D1F80025 ldr r2, [r1, #1280] + 4176 0048 42F00042 orr r2, r2, #-2147483648 + 4177 004c C1F80025 str r2, [r1, #1280] +1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + 4178 .loc 1 1840 7 is_stmt 1 view .LVU1307 + 4179 .loc 1 1840 30 is_stmt 0 view .LVU1308 + 4180 0050 D1F80025 ldr r2, [r1, #1280] + 4181 0054 22F40042 bic r2, r2, #32768 + 4182 0058 C1F80025 str r2, [r1, #1280] + 4183 .LVL343: + 4184 .L275: +1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + ARM GAS /tmp/cc9mtr28.s page 125 + + + 4185 .loc 1 1841 7 is_stmt 1 view .LVU1309 +1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 1000U) + 4186 .loc 1 1843 9 view .LVU1310 + 4187 .loc 1 1843 12 is_stmt 0 view .LVU1311 + 4188 005c 0133 adds r3, r3, #1 + 4189 .LVL344: + 4190 .loc 1 1843 12 view .LVU1312 + 4191 005e B3F57A7F cmp r3, #1000 + 4192 0062 0AD8 bhi .L274 +1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + 4193 .loc 1 1848 13 is_stmt 1 view .LVU1313 + 4194 .loc 1 1848 29 is_stmt 0 view .LVU1314 + 4195 0064 DCF80020 ldr r2, [ip] + 4196 .loc 1 1848 7 view .LVU1315 + 4197 0068 002A cmp r2, #0 + 4198 006a F7DB blt .L275 + 4199 006c 05E0 b .L274 + 4200 .LVL345: + 4201 .L273: +1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 4202 .loc 1 1852 7 is_stmt 1 view .LVU1316 + 4203 .loc 1 1852 30 is_stmt 0 view .LVU1317 + 4204 006e D1F80035 ldr r3, [r1, #1280] + 4205 0072 43F00043 orr r3, r3, #-2147483648 + 4206 0076 C1F80035 str r3, [r1, #1280] + 4207 .LVL346: + 4208 .L274: +1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; +1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) +1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do +1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 1000U) +1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); +1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** else +1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 126 + + +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; +1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4209 .loc 1 1879 3 is_stmt 1 view .LVU1318 +1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4210 .loc 1 1880 1 is_stmt 0 view .LVU1319 + 4211 007a 0020 movs r0, #0 + 4212 .LVL347: + 4213 .loc 1 1880 1 view .LVU1320 + 4214 007c 7047 bx lr + 4215 .LVL348: + 4216 .L272: +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4217 .loc 1 1857 5 is_stmt 1 view .LVU1321 +1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4218 .loc 1 1857 28 is_stmt 0 view .LVU1322 + 4219 007e D1F80035 ldr r3, [r1, #1280] + 4220 0082 43F08043 orr r3, r3, #1073741824 + 4221 0086 C1F80035 str r3, [r1, #1280] +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4222 .loc 1 1859 5 is_stmt 1 view .LVU1323 +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4223 .loc 1 1859 19 is_stmt 0 view .LVU1324 + 4224 008a D0F81034 ldr r3, [r0, #1040] +1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4225 .loc 1 1859 8 view .LVU1325 + 4226 008e 13F47F03 ands r3, r3, #16711680 + 4227 0092 1AD1 bne .L276 +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 4228 .loc 1 1861 7 is_stmt 1 view .LVU1326 +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 4229 .loc 1 1861 30 is_stmt 0 view .LVU1327 + 4230 0094 D1F80025 ldr r2, [r1, #1280] + 4231 .LVL349: +1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + 4232 .loc 1 1861 30 view .LVU1328 + 4233 0098 22F00042 bic r2, r2, #-2147483648 + 4234 009c C1F80025 str r2, [r1, #1280] +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + 4235 .loc 1 1862 7 is_stmt 1 view .LVU1329 +1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + 4236 .loc 1 1862 30 is_stmt 0 view .LVU1330 + 4237 00a0 D1F80025 ldr r2, [r1, #1280] + 4238 00a4 42F00042 orr r2, r2, #-2147483648 + 4239 00a8 C1F80025 str r2, [r1, #1280] +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 4240 .loc 1 1863 7 is_stmt 1 view .LVU1331 +1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 4241 .loc 1 1863 30 is_stmt 0 view .LVU1332 + 4242 00ac D1F80025 ldr r2, [r1, #1280] + 4243 00b0 22F40042 bic r2, r2, #32768 + 4244 00b4 C1F80025 str r2, [r1, #1280] + 4245 .LVL350: + 4246 .L277: +1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + ARM GAS /tmp/cc9mtr28.s page 127 + + + 4247 .loc 1 1864 7 is_stmt 1 view .LVU1333 +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4248 .loc 1 1866 9 view .LVU1334 +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4249 .loc 1 1866 12 is_stmt 0 view .LVU1335 + 4250 00b8 0133 adds r3, r3, #1 + 4251 .LVL351: +1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4252 .loc 1 1866 12 view .LVU1336 + 4253 00ba B3F57A7F cmp r3, #1000 + 4254 00be DCD8 bhi .L274 +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4255 .loc 1 1871 13 is_stmt 1 view .LVU1337 +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4256 .loc 1 1871 29 is_stmt 0 view .LVU1338 + 4257 00c0 DCF80020 ldr r2, [ip] +1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4258 .loc 1 1871 7 view .LVU1339 + 4259 00c4 002A cmp r2, #0 + 4260 00c6 F7DB blt .L277 + 4261 00c8 D7E7 b .L274 + 4262 .LVL352: + 4263 .L276: +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4264 .loc 1 1875 7 is_stmt 1 view .LVU1340 +1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4265 .loc 1 1875 30 is_stmt 0 view .LVU1341 + 4266 00ca D1F80035 ldr r3, [r1, #1280] + 4267 00ce 43F00043 orr r3, r3, #-2147483648 + 4268 00d2 C1F80035 str r3, [r1, #1280] + 4269 00d6 D0E7 b .L274 + 4270 .cfi_endproc + 4271 .LFE184: + 4273 .section .text.USB_DoPing,"ax",%progbits + 4274 .align 1 + 4275 .global USB_DoPing + 4276 .syntax unified + 4277 .thumb + 4278 .thumb_func + 4279 .fpu fpv5-d16 + 4281 USB_DoPing: + 4282 .LVL353: + 4283 .LFB185: +1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Initiate Do Ping protocol +1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param hc_num Host Channel number +1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * This parameter can be a value from 1 to 15 +1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL state +1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4284 .loc 1 1890 1 is_stmt 1 view -0 + 4285 .cfi_startproc + 4286 @ args = 0, pretend = 0, frame = 0 + 4287 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc9mtr28.s page 128 + + + 4288 @ link register save eliminated. +1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4289 .loc 1 1891 3 view .LVU1343 +1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t chnum = (uint32_t)ch_num; + 4290 .loc 1 1892 3 view .LVU1344 +1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t num_packets = 1U; + 4291 .loc 1 1893 3 view .LVU1345 +1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t tmpreg; + 4292 .loc 1 1894 3 view .LVU1346 +1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 4293 .loc 1 1896 3 view .LVU1347 + 4294 0000 00EB4111 add r1, r0, r1, lsl #5 + 4295 .LVL354: + 4296 .loc 1 1896 26 is_stmt 0 view .LVU1348 + 4297 0004 064A ldr r2, .L279 + 4298 0006 C1F81025 str r2, [r1, #1296] +1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USB_OTG_HCTSIZ_DOPING; +1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Set host channel enable */ +1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg = USBx_HC(chnum)->HCCHAR; + 4299 .loc 1 1900 3 is_stmt 1 view .LVU1349 + 4300 .loc 1 1900 10 is_stmt 0 view .LVU1350 + 4301 000a D1F80035 ldr r3, [r1, #1280] + 4302 .LVL355: +1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 4303 .loc 1 1901 3 is_stmt 1 view .LVU1351 + 4304 .loc 1 1901 10 is_stmt 0 view .LVU1352 + 4305 000e 23F08043 bic r3, r3, #1073741824 + 4306 .LVL356: +1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg |= USB_OTG_HCCHAR_CHENA; + 4307 .loc 1 1902 3 is_stmt 1 view .LVU1353 + 4308 .loc 1 1902 10 is_stmt 0 view .LVU1354 + 4309 0012 43F00043 orr r3, r3, #-2147483648 + 4310 .LVL357: +1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(chnum)->HCCHAR = tmpreg; + 4311 .loc 1 1903 3 is_stmt 1 view .LVU1355 + 4312 .loc 1 1903 26 is_stmt 0 view .LVU1356 + 4313 0016 C1F80035 str r3, [r1, #1280] +1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4314 .loc 1 1905 3 is_stmt 1 view .LVU1357 +1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4315 .loc 1 1906 1 is_stmt 0 view .LVU1358 + 4316 001a 0020 movs r0, #0 + 4317 .LVL358: + 4318 .loc 1 1906 1 view .LVU1359 + 4319 001c 7047 bx lr + 4320 .L280: + 4321 001e 00BF .align 2 + 4322 .L279: + 4323 0020 00000880 .word -2146959360 + 4324 .cfi_endproc + 4325 .LFE185: + 4327 .section .text.USB_HC_StartXfer,"ax",%progbits + 4328 .align 1 + 4329 .global USB_HC_StartXfer + ARM GAS /tmp/cc9mtr28.s page 129 + + + 4330 .syntax unified + 4331 .thumb + 4332 .thumb_func + 4333 .fpu fpv5-d16 + 4335 USB_HC_StartXfer: + 4336 .LVL359: + 4337 .LFB182: +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4338 .loc 1 1683 1 is_stmt 1 view -0 + 4339 .cfi_startproc + 4340 @ args = 0, pretend = 0, frame = 0 + 4341 @ frame_needed = 0, uses_anonymous_args = 0 +1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4342 .loc 1 1683 1 is_stmt 0 view .LVU1361 + 4343 0000 30B5 push {r4, r5, lr} + 4344 .LCFI48: + 4345 .cfi_def_cfa_offset 12 + 4346 .cfi_offset 4, -12 + 4347 .cfi_offset 5, -8 + 4348 .cfi_offset 14, -4 + 4349 0002 83B0 sub sp, sp, #12 + 4350 .LCFI49: + 4351 .cfi_def_cfa_offset 24 +1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t ch_num = (uint32_t)hc->ch_num; + 4352 .loc 1 1684 3 is_stmt 1 view .LVU1362 + 4353 .LVL360: +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** static __IO uint32_t tmpreg = 0U; + 4354 .loc 1 1685 3 view .LVU1363 +1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** static __IO uint32_t tmpreg = 0U; + 4355 .loc 1 1685 33 is_stmt 0 view .LVU1364 + 4356 0004 91F801C0 ldrb ip, [r1, #1] @ zero_extendqisi2 + 4357 .LVL361: +1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint8_t is_oddframe; + 4358 .loc 1 1686 3 is_stmt 1 view .LVU1365 +1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t len_words; + 4359 .loc 1 1687 3 view .LVU1366 +1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t num_packets; + 4360 .loc 1 1688 3 view .LVU1367 +1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint16_t max_hc_pkt_count = 256U; + 4361 .loc 1 1689 3 view .LVU1368 +1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4362 .loc 1 1690 3 view .LVU1369 +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4363 .loc 1 1692 3 view .LVU1370 +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4364 .loc 1 1692 13 is_stmt 0 view .LVU1371 + 4365 0008 C36B ldr r3, [r0, #60] +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4366 .loc 1 1692 6 view .LVU1372 + 4367 000a 13F4807F tst r3, #256 + 4368 000e 07D0 beq .L282 +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4369 .loc 1 1692 47 discriminator 1 view .LVU1373 + 4370 0010 0B79 ldrb r3, [r1, #4] @ zero_extendqisi2 +1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4371 .loc 1 1692 41 discriminator 1 view .LVU1374 + 4372 0012 2BB9 cbnz r3, .L282 + ARM GAS /tmp/cc9mtr28.s page 130 + + +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4373 .loc 1 1694 5 is_stmt 1 view .LVU1375 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4374 .loc 1 1694 8 is_stmt 0 view .LVU1376 + 4375 0014 12B9 cbnz r2, .L283 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4376 .loc 1 1694 27 discriminator 1 view .LVU1377 + 4377 0016 4B79 ldrb r3, [r1, #5] @ zero_extendqisi2 +1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4378 .loc 1 1694 21 discriminator 1 view .LVU1378 + 4379 0018 012B cmp r3, #1 + 4380 001a 11D0 beq .L296 + 4381 .L283: +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4382 .loc 1 1699 10 is_stmt 1 view .LVU1379 +1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4383 .loc 1 1699 13 is_stmt 0 view .LVU1380 + 4384 001c 012A cmp r2, #1 + 4385 001e 13D0 beq .L297 + 4386 .L282: +1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4387 .loc 1 1707 5 is_stmt 1 view .LVU1381 +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4388 .loc 1 1711 3 view .LVU1382 +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4389 .loc 1 1711 9 is_stmt 0 view .LVU1383 + 4390 0020 0B69 ldr r3, [r1, #16] +1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4391 .loc 1 1711 6 view .LVU1384 + 4392 0022 E3B1 cbz r3, .L294 +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4393 .loc 1 1713 5 is_stmt 1 view .LVU1385 +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4394 .loc 1 1713 48 is_stmt 0 view .LVU1386 + 4395 0024 0C89 ldrh r4, [r1, #8] +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4396 .loc 1 1713 44 view .LVU1387 + 4397 0026 2344 add r3, r3, r4 +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4398 .loc 1 1713 61 view .LVU1388 + 4399 0028 013B subs r3, r3, #1 +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4400 .loc 1 1713 67 view .LVU1389 + 4401 002a B3FBF4F3 udiv r3, r3, r4 +1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4402 .loc 1 1713 17 view .LVU1390 + 4403 002e 9BB2 uxth r3, r3 + 4404 .LVL362: +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4405 .loc 1 1715 5 is_stmt 1 view .LVU1391 +1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4406 .loc 1 1715 8 is_stmt 0 view .LVU1392 + 4407 0030 B3F5807F cmp r3, #256 + 4408 0034 14D9 bls .L285 +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + 4409 .loc 1 1717 7 is_stmt 1 view .LVU1393 + 4410 .LVL363: + ARM GAS /tmp/cc9mtr28.s page 131 + + +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4411 .loc 1 1718 7 view .LVU1394 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4412 .loc 1 1718 44 is_stmt 0 view .LVU1395 + 4413 0036 2402 lsls r4, r4, #8 +1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4414 .loc 1 1718 20 view .LVU1396 + 4415 0038 0C61 str r4, [r1, #16] +1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + 4416 .loc 1 1717 19 view .LVU1397 + 4417 003a 4FF48073 mov r3, #256 + 4418 003e 0FE0 b .L285 + 4419 .LVL364: + 4420 .L296: +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4421 .loc 1 1696 7 is_stmt 1 view .LVU1398 +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4422 .loc 1 1696 13 is_stmt 0 view .LVU1399 + 4423 0040 6146 mov r1, ip + 4424 .LVL365: +1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4425 .loc 1 1696 13 view .LVU1400 + 4426 0042 FFF7FEFF bl USB_DoPing + 4427 .LVL366: +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4428 .loc 1 1697 7 is_stmt 1 view .LVU1401 +1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4429 .loc 1 1697 14 is_stmt 0 view .LVU1402 + 4430 0046 79E0 b .L284 + 4431 .LVL367: + 4432 .L297: +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->do_ping = 0U; + 4433 .loc 1 1701 7 is_stmt 1 view .LVU1403 +1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** hc->do_ping = 0U; + 4434 .loc 1 1701 33 is_stmt 0 view .LVU1404 + 4435 0048 00EB4C13 add r3, r0, ip, lsl #5 + 4436 004c D3F80C45 ldr r4, [r3, #1292] + 4437 0050 24F06004 bic r4, r4, #96 + 4438 0054 C3F80C45 str r4, [r3, #1292] +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4439 .loc 1 1702 7 is_stmt 1 view .LVU1405 +1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4440 .loc 1 1702 19 is_stmt 0 view .LVU1406 + 4441 0058 0023 movs r3, #0 + 4442 005a 4B71 strb r3, [r1, #5] + 4443 005c E0E7 b .L282 + 4444 .L294: +1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4445 .loc 1 1723 17 view .LVU1407 + 4446 005e 0123 movs r3, #1 + 4447 .L285: + 4448 .LVL368: +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4449 .loc 1 1725 3 is_stmt 1 view .LVU1408 +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4450 .loc 1 1725 9 is_stmt 0 view .LVU1409 + 4451 0060 CC78 ldrb r4, [r1, #3] @ zero_extendqisi2 + ARM GAS /tmp/cc9mtr28.s page 132 + + +1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4452 .loc 1 1725 6 view .LVU1410 + 4453 0062 1CB1 cbz r4, .L286 +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4454 .loc 1 1727 5 is_stmt 1 view .LVU1411 +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4455 .loc 1 1727 46 is_stmt 0 view .LVU1412 + 4456 0064 0C89 ldrh r4, [r1, #8] +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4457 .loc 1 1727 42 view .LVU1413 + 4458 0066 03FB04F4 mul r4, r3, r4 +1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4459 .loc 1 1727 18 view .LVU1414 + 4460 006a 0C61 str r4, [r1, #16] + 4461 .L286: +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 4462 .loc 1 1731 3 is_stmt 1 view .LVU1415 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 4463 .loc 1 1731 43 is_stmt 0 view .LVU1416 + 4464 006c 0C69 ldr r4, [r1, #16] + 4465 006e C4F3120E ubfx lr, r4, #0, #19 +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + 4466 .loc 1 1732 60 view .LVU1417 + 4467 0072 3A4C ldr r4, .L298 + 4468 0074 04EAC343 and r3, r4, r3, lsl #19 + 4469 .LVL369: +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 4470 .loc 1 1731 68 view .LVU1418 + 4471 0078 4EEA0303 orr r3, lr, r3 +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4472 .loc 1 1733 43 view .LVU1419 + 4473 007c 91F80AE0 ldrb lr, [r1, #10] @ zero_extendqisi2 +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4474 .loc 1 1733 54 view .LVU1420 + 4475 0080 4FEA4E7E lsl lr, lr, #29 +1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4476 .loc 1 1733 61 view .LVU1421 + 4477 0084 0EF0C04E and lr, lr, #1610612736 +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 4478 .loc 1 1731 3 view .LVU1422 + 4479 0088 00EB4C1C add ip, r0, ip, lsl #5 + 4480 .LVL370: +1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + 4481 .loc 1 1732 85 view .LVU1423 + 4482 008c 43EA0E03 orr r3, r3, lr +1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + 4483 .loc 1 1731 27 view .LVU1424 + 4484 0090 CCF81035 str r3, [ip, #1296] +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4485 .loc 1 1735 3 is_stmt 1 view .LVU1425 +1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4486 .loc 1 1735 6 is_stmt 0 view .LVU1426 + 4487 0094 12B1 cbz r2, .L287 +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4488 .loc 1 1738 5 is_stmt 1 view .LVU1427 +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4489 .loc 1 1738 42 is_stmt 0 view .LVU1428 + ARM GAS /tmp/cc9mtr28.s page 133 + + + 4490 0096 CB68 ldr r3, [r1, #12] +1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4491 .loc 1 1738 28 view .LVU1429 + 4492 0098 CCF81435 str r3, [ip, #1300] + 4493 .L287: +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + 4494 .loc 1 1741 3 is_stmt 1 view .LVU1430 +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + 4495 .loc 1 1741 29 is_stmt 0 view .LVU1431 + 4496 009c 00F5806E add lr, r0, #1024 +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + 4497 .loc 1 1741 38 view .LVU1432 + 4498 00a0 DEF80830 ldr r3, [lr, #8] +1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + 4499 .loc 1 1741 67 view .LVU1433 + 4500 00a4 13F0010F tst r3, #1 + 4501 00a8 0CBF ite eq + 4502 00aa 0125 moveq r5, #1 + 4503 00ac 0025 movne r5, #0 + 4504 .LVL371: +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + 4505 .loc 1 1742 3 is_stmt 1 view .LVU1434 +1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + 4506 .loc 1 1742 27 is_stmt 0 view .LVU1435 + 4507 00ae DCF80045 ldr r4, [ip, #1280] + 4508 00b2 24F00054 bic r4, r4, #536870912 + 4509 00b6 CCF80045 str r4, [ip, #1280] +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4510 .loc 1 1743 3 is_stmt 1 view .LVU1436 +1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4511 .loc 1 1743 27 is_stmt 0 view .LVU1437 + 4512 00ba DCF80035 ldr r3, [ip, #1280] + 4513 00be 43EA4573 orr r3, r3, r5, lsl #29 + 4514 00c2 CCF80035 str r3, [ip, #1280] +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 4515 .loc 1 1746 3 is_stmt 1 view .LVU1438 +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 4516 .loc 1 1746 27 is_stmt 0 view .LVU1439 + 4517 00c6 DCF80045 ldr r4, [ip, #1280] +1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + 4518 .loc 1 1746 10 view .LVU1440 + 4519 00ca 254B ldr r3, .L298+4 + 4520 00cc 1C60 str r4, [r3] +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4521 .loc 1 1747 3 is_stmt 1 view .LVU1441 +1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4522 .loc 1 1747 10 is_stmt 0 view .LVU1442 + 4523 00ce 1C68 ldr r4, [r3] + 4524 00d0 24F08044 bic r4, r4, #1073741824 + 4525 00d4 1C60 str r4, [r3] +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4526 .loc 1 1750 3 is_stmt 1 view .LVU1443 +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4527 .loc 1 1750 9 is_stmt 0 view .LVU1444 + 4528 00d6 CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 +1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4529 .loc 1 1750 6 view .LVU1445 + ARM GAS /tmp/cc9mtr28.s page 134 + + + 4530 00d8 C3B1 cbz r3, .L288 +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4531 .loc 1 1752 5 is_stmt 1 view .LVU1446 +1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4532 .loc 1 1752 12 is_stmt 0 view .LVU1447 + 4533 00da 214C ldr r4, .L298+4 + 4534 00dc 2368 ldr r3, [r4] + 4535 00de 43F40043 orr r3, r3, #32768 + 4536 00e2 2360 str r3, [r4] + 4537 .L289: +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR = tmpreg; + 4538 .loc 1 1758 3 is_stmt 1 view .LVU1448 +1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(ch_num)->HCCHAR = tmpreg; + 4539 .loc 1 1758 10 is_stmt 0 view .LVU1449 + 4540 00e4 1E4B ldr r3, .L298+4 + 4541 00e6 1C68 ldr r4, [r3] + 4542 00e8 44F00044 orr r4, r4, #-2147483648 + 4543 00ec 1C60 str r4, [r3] +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4544 .loc 1 1759 3 is_stmt 1 view .LVU1450 +1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4545 .loc 1 1759 27 is_stmt 0 view .LVU1451 + 4546 00ee 1B68 ldr r3, [r3] + 4547 00f0 CCF80035 str r3, [ip, #1280] +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4548 .loc 1 1761 3 is_stmt 1 view .LVU1452 +1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4549 .loc 1 1761 6 is_stmt 0 view .LVU1453 + 4550 00f4 12BB cbnz r2, .L284 +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4551 .loc 1 1763 5 is_stmt 1 view .LVU1454 +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4552 .loc 1 1763 12 is_stmt 0 view .LVU1455 + 4553 00f6 CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4554 .loc 1 1763 8 view .LVU1456 + 4555 00f8 03BB cbnz r3, .L284 +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4556 .loc 1 1763 36 discriminator 1 view .LVU1457 + 4557 00fa 0B69 ldr r3, [r1, #16] +1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4558 .loc 1 1763 30 discriminator 1 view .LVU1458 + 4559 00fc F3B1 cbz r3, .L284 +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4560 .loc 1 1765 7 is_stmt 1 view .LVU1459 +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4561 .loc 1 1765 17 is_stmt 0 view .LVU1460 + 4562 00fe CA79 ldrb r2, [r1, #7] @ zero_extendqisi2 + 4563 .LVL372: +1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4564 .loc 1 1765 17 view .LVU1461 + 4565 0100 032A cmp r2, #3 + 4566 0102 14D8 bhi .L290 + 4567 0104 DFE802F0 tbb [pc, r2] + 4568 .L292: + 4569 0108 08 .byte (.L293-.L292)/2 + 4570 0109 1D .byte (.L291-.L292)/2 + ARM GAS /tmp/cc9mtr28.s page 135 + + + 4571 010a 08 .byte (.L293-.L292)/2 + 4572 010b 1D .byte (.L291-.L292)/2 + 4573 .LVL373: + 4574 .p2align 1 + 4575 .L288: +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4576 .loc 1 1756 5 is_stmt 1 view .LVU1462 +1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4577 .loc 1 1756 12 is_stmt 0 view .LVU1463 + 4578 010c 144C ldr r4, .L298+4 + 4579 010e 2368 ldr r3, [r4] + 4580 0110 23F40043 bic r3, r3, #32768 + 4581 0114 2360 str r3, [r4] + 4582 0116 E5E7 b .L289 + 4583 .LVL374: + 4584 .L293: +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4585 .loc 1 1771 11 is_stmt 1 view .LVU1464 +1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4586 .loc 1 1771 48 is_stmt 0 view .LVU1465 + 4587 0118 0333 adds r3, r3, #3 + 4588 .LVL375: +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4589 .loc 1 1774 11 is_stmt 1 view .LVU1466 +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4590 .loc 1 1774 32 is_stmt 0 view .LVU1467 + 4591 011a C26A ldr r2, [r0, #44] +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4592 .loc 1 1774 43 view .LVU1468 + 4593 011c 92B2 uxth r2, r2 +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4594 .loc 1 1774 14 view .LVU1469 + 4595 011e C3F38F03 ubfx r3, r3, #2, #16 + 4596 .LVL376: +1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4597 .loc 1 1774 14 view .LVU1470 + 4598 0122 9A42 cmp r2, r3 + 4599 0124 03D2 bcs .L290 +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4600 .loc 1 1777 13 is_stmt 1 view .LVU1471 +1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4601 .loc 1 1777 27 is_stmt 0 view .LVU1472 + 4602 0126 8369 ldr r3, [r0, #24] + 4603 0128 43F02003 orr r3, r3, #32 + 4604 012c 8361 str r3, [r0, #24] + 4605 .LVL377: + 4606 .L290: +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4607 .loc 1 1798 7 is_stmt 1 view .LVU1473 +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4608 .loc 1 1798 13 is_stmt 0 view .LVU1474 + 4609 012e 0023 movs r3, #0 + 4610 0130 0093 str r3, [sp] + 4611 0132 0B8A ldrh r3, [r1, #16] + 4612 0134 4A78 ldrb r2, [r1, #1] @ zero_extendqisi2 + 4613 0136 C968 ldr r1, [r1, #12] + 4614 .LVL378: + ARM GAS /tmp/cc9mtr28.s page 136 + + +1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4615 .loc 1 1798 13 view .LVU1475 + 4616 0138 FFF7FEFF bl USB_WritePacket + 4617 .LVL379: + 4618 .L284: +1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** + 4619 .loc 1 1803 1 view .LVU1476 + 4620 013c 0020 movs r0, #0 + 4621 013e 03B0 add sp, sp, #12 + 4622 .LCFI50: + 4623 .cfi_remember_state + 4624 .cfi_def_cfa_offset 12 + 4625 @ sp needed + 4626 0140 30BD pop {r4, r5, pc} + 4627 .LVL380: + 4628 .L291: + 4629 .LCFI51: + 4630 .cfi_restore_state +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* check if there is enough space in FIFO space */ + 4631 .loc 1 1784 11 is_stmt 1 view .LVU1477 +1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* check if there is enough space in FIFO space */ + 4632 .loc 1 1784 48 is_stmt 0 view .LVU1478 + 4633 0142 0333 adds r3, r3, #3 + 4634 .LVL381: +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4635 .loc 1 1786 11 is_stmt 1 view .LVU1479 +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4636 .loc 1 1786 37 is_stmt 0 view .LVU1480 + 4637 0144 DEF81020 ldr r2, [lr, #16] +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4638 .loc 1 1786 47 view .LVU1481 + 4639 0148 92B2 uxth r2, r2 +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4640 .loc 1 1786 14 view .LVU1482 + 4641 014a C3F38F03 ubfx r3, r3, #2, #16 + 4642 .LVL382: +1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4643 .loc 1 1786 14 view .LVU1483 + 4644 014e 9A42 cmp r2, r3 + 4645 0150 EDD2 bcs .L290 +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4646 .loc 1 1789 13 is_stmt 1 view .LVU1484 +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4647 .loc 1 1789 27 is_stmt 0 view .LVU1485 + 4648 0152 8369 ldr r3, [r0, #24] + 4649 0154 43F08063 orr r3, r3, #67108864 + 4650 0158 8361 str r3, [r0, #24] + 4651 .LVL383: +1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4652 .loc 1 1789 27 view .LVU1486 + 4653 015a E8E7 b .L290 + 4654 .L299: + 4655 .align 2 + 4656 .L298: + 4657 015c 0000F81F .word 536346624 + 4658 0160 00000000 .word .LANCHOR0 + 4659 .cfi_endproc + ARM GAS /tmp/cc9mtr28.s page 137 + + + 4660 .LFE182: + 4662 .section .text.USB_StopHost,"ax",%progbits + 4663 .align 1 + 4664 .global USB_StopHost + 4665 .syntax unified + 4666 .thumb + 4667 .thumb_func + 4668 .fpu fpv5-d16 + 4670 USB_StopHost: + 4671 .LVL384: + 4672 .LFB186: +1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief Stop Host Core +1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL state +1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ +1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4673 .loc 1 1914 1 is_stmt 1 view -0 + 4674 .cfi_startproc + 4675 @ args = 0, pretend = 0, frame = 0 + 4676 @ frame_needed = 0, uses_anonymous_args = 0 + 4677 .loc 1 1914 1 is_stmt 0 view .LVU1488 + 4678 0000 10B5 push {r4, lr} + 4679 .LCFI52: + 4680 .cfi_def_cfa_offset 8 + 4681 .cfi_offset 4, -8 + 4682 .cfi_offset 14, -4 + 4683 0002 0446 mov r4, r0 +1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4684 .loc 1 1915 3 is_stmt 1 view .LVU1489 + 4685 .LVL385: +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t count = 0U; + 4686 .loc 1 1916 3 view .LVU1490 +1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t value; + 4687 .loc 1 1917 3 view .LVU1491 +1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t i; + 4688 .loc 1 1918 3 view .LVU1492 +1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_DisableGlobalInt(USBx); + 4689 .loc 1 1920 3 view .LVU1493 + 4690 .loc 1 1920 9 is_stmt 0 view .LVU1494 + 4691 0004 FFF7FEFF bl USB_DisableGlobalInt + 4692 .LVL386: +1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Flush FIFO */ +1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushTxFifo(USBx, 0x10U); + 4693 .loc 1 1923 3 is_stmt 1 view .LVU1495 + 4694 .loc 1 1923 9 is_stmt 0 view .LVU1496 + 4695 0008 1021 movs r1, #16 + 4696 000a 2046 mov r0, r4 + 4697 000c FFF7FEFF bl USB_FlushTxFifo + 4698 .LVL387: +1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_FlushRxFifo(USBx); + 4699 .loc 1 1924 3 is_stmt 1 view .LVU1497 + 4700 .loc 1 1924 9 is_stmt 0 view .LVU1498 + ARM GAS /tmp/cc9mtr28.s page 138 + + + 4701 0010 2046 mov r0, r4 + 4702 0012 FFF7FEFF bl USB_FlushRxFifo + 4703 .LVL388: +1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Flush out any leftover queued requests. */ +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i <= 15U; i++) + 4704 .loc 1 1927 3 is_stmt 1 view .LVU1499 + 4705 .loc 1 1927 10 is_stmt 0 view .LVU1500 + 4706 0016 0022 movs r2, #0 + 4707 .loc 1 1927 3 view .LVU1501 + 4708 0018 0AE0 b .L301 + 4709 .LVL389: + 4710 .L302: +1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value = USBx_HC(i)->HCCHAR; + 4711 .loc 1 1929 5 is_stmt 1 discriminator 3 view .LVU1502 + 4712 .loc 1 1929 13 is_stmt 0 discriminator 3 view .LVU1503 + 4713 001a 04EB4211 add r1, r4, r2, lsl #5 + 4714 .loc 1 1929 11 discriminator 3 view .LVU1504 + 4715 001e D1F80035 ldr r3, [r1, #1280] + 4716 .LVL390: +1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value |= USB_OTG_HCCHAR_CHDIS; + 4717 .loc 1 1930 5 is_stmt 1 discriminator 3 view .LVU1505 +1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value &= ~USB_OTG_HCCHAR_CHENA; + 4718 .loc 1 1931 5 discriminator 3 view .LVU1506 +1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value &= ~USB_OTG_HCCHAR_EPDIR; + 4719 .loc 1 1932 5 discriminator 3 view .LVU1507 + 4720 0022 23F08023 bic r3, r3, #-2147450880 + 4721 .LVL391: + 4722 .loc 1 1932 11 is_stmt 0 discriminator 3 view .LVU1508 + 4723 0026 43F08043 orr r3, r3, #1073741824 + 4724 .LVL392: +1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(i)->HCCHAR = value; + 4725 .loc 1 1933 5 is_stmt 1 discriminator 3 view .LVU1509 + 4726 .loc 1 1933 24 is_stmt 0 discriminator 3 view .LVU1510 + 4727 002a C1F80035 str r3, [r1, #1280] +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4728 .loc 1 1927 26 is_stmt 1 discriminator 3 view .LVU1511 +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4729 .loc 1 1927 27 is_stmt 0 discriminator 3 view .LVU1512 + 4730 002e 0132 adds r2, r2, #1 + 4731 .LVL393: + 4732 .L301: +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4733 .loc 1 1927 16 is_stmt 1 discriminator 1 view .LVU1513 +1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4734 .loc 1 1927 3 is_stmt 0 discriminator 1 view .LVU1514 + 4735 0030 0F2A cmp r2, #15 + 4736 0032 F2D9 bls .L302 +1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Halt all channels to put them into a known state. */ +1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** for (i = 0U; i <= 15U; i++) + 4737 .loc 1 1937 10 view .LVU1515 + 4738 0034 0020 movs r0, #0 +1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t value; + 4739 .loc 1 1916 12 view .LVU1516 + ARM GAS /tmp/cc9mtr28.s page 139 + + + 4740 0036 0346 mov r3, r0 + 4741 0038 00E0 b .L303 + 4742 .LVL394: + 4743 .L304: + 4744 .loc 1 1937 26 is_stmt 1 discriminator 2 view .LVU1517 + 4745 .loc 1 1937 27 is_stmt 0 discriminator 2 view .LVU1518 + 4746 003a 0130 adds r0, r0, #1 + 4747 .LVL395: + 4748 .L303: + 4749 .loc 1 1937 16 is_stmt 1 discriminator 1 view .LVU1519 + 4750 .loc 1 1937 3 is_stmt 0 discriminator 1 view .LVU1520 + 4751 003c 0F28 cmp r0, #15 + 4752 003e 13D8 bhi .L308 +1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value = USBx_HC(i)->HCCHAR; + 4753 .loc 1 1939 5 is_stmt 1 view .LVU1521 + 4754 .loc 1 1939 13 is_stmt 0 view .LVU1522 + 4755 0040 04EB401C add ip, r4, r0, lsl #5 + 4756 0044 0CF5A061 add r1, ip, #1280 + 4757 .loc 1 1939 11 view .LVU1523 + 4758 0048 DCF80025 ldr r2, [ip, #1280] + 4759 .LVL396: +1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value |= USB_OTG_HCCHAR_CHDIS; + 4760 .loc 1 1940 5 is_stmt 1 view .LVU1524 +1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value |= USB_OTG_HCCHAR_CHENA; + 4761 .loc 1 1941 5 view .LVU1525 +1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** value &= ~USB_OTG_HCCHAR_EPDIR; + 4762 .loc 1 1942 5 view .LVU1526 + 4763 004c 22F40042 bic r2, r2, #32768 + 4764 .LVL397: + 4765 .loc 1 1942 11 is_stmt 0 view .LVU1527 + 4766 0050 42F04042 orr r2, r2, #-1073741824 + 4767 .LVL398: +1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HC(i)->HCCHAR = value; + 4768 .loc 1 1943 5 is_stmt 1 view .LVU1528 + 4769 .loc 1 1943 24 is_stmt 0 view .LVU1529 + 4770 0054 CCF80025 str r2, [ip, #1280] + 4771 .LVL399: + 4772 .L305: +1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** do + 4773 .loc 1 1945 5 is_stmt 1 view .LVU1530 +1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if (++count > 1000U) + 4774 .loc 1 1947 7 view .LVU1531 + 4775 .loc 1 1947 10 is_stmt 0 view .LVU1532 + 4776 0058 0133 adds r3, r3, #1 + 4777 .LVL400: + 4778 .loc 1 1947 10 view .LVU1533 + 4779 005a B3F57A7F cmp r3, #1000 + 4780 005e ECD8 bhi .L304 +1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** break; +1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + 4781 .loc 1 1952 11 is_stmt 1 view .LVU1534 + ARM GAS /tmp/cc9mtr28.s page 140 + + + 4782 .loc 1 1952 23 is_stmt 0 view .LVU1535 + 4783 0060 0A68 ldr r2, [r1] + 4784 .loc 1 1952 5 view .LVU1536 + 4785 0062 002A cmp r2, #0 + 4786 0064 F8DB blt .L305 + 4787 0066 E8E7 b .L304 + 4788 .LVL401: + 4789 .L308: +1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* Clear any pending Host interrupts */ +1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_HOST->HAINT = 0xFFFFFFFFU; + 4790 .loc 1 1956 3 is_stmt 1 view .LVU1537 + 4791 .loc 1 1956 20 is_stmt 0 view .LVU1538 + 4792 0068 4FF0FF33 mov r3, #-1 + 4793 .LVL402: + 4794 .loc 1 1956 20 view .LVU1539 + 4795 006c C4F81434 str r3, [r4, #1044] +1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx->GINTSTS = 0xFFFFFFFFU; + 4796 .loc 1 1957 3 is_stmt 1 view .LVU1540 + 4797 .loc 1 1957 17 is_stmt 0 view .LVU1541 + 4798 0070 6361 str r3, [r4, #20] +1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** (void)USB_EnableGlobalInt(USBx); + 4799 .loc 1 1959 3 is_stmt 1 view .LVU1542 + 4800 .loc 1 1959 9 is_stmt 0 view .LVU1543 + 4801 0072 2046 mov r0, r4 + 4802 .LVL403: + 4803 .loc 1 1959 9 view .LVU1544 + 4804 0074 FFF7FEFF bl USB_EnableGlobalInt + 4805 .LVL404: +1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4806 .loc 1 1961 3 is_stmt 1 view .LVU1545 +1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4807 .loc 1 1962 1 is_stmt 0 view .LVU1546 + 4808 0078 0020 movs r0, #0 + 4809 007a 10BD pop {r4, pc} + 4810 .loc 1 1962 1 view .LVU1547 + 4811 .cfi_endproc + 4812 .LFE186: + 4814 .section .text.USB_ActivateRemoteWakeup,"ax",%progbits + 4815 .align 1 + 4816 .global USB_ActivateRemoteWakeup + 4817 .syntax unified + 4818 .thumb + 4819 .thumb_func + 4820 .fpu fpv5-d16 + 4822 USB_ActivateRemoteWakeup: + 4823 .LVL405: + 4824 .LFB187: +1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_ActivateRemoteWakeup active remote wakeup signalling +1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + ARM GAS /tmp/cc9mtr28.s page 141 + + +1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4825 .loc 1 1970 1 is_stmt 1 view -0 + 4826 .cfi_startproc + 4827 @ args = 0, pretend = 0, frame = 0 + 4828 @ frame_needed = 0, uses_anonymous_args = 0 + 4829 @ link register save eliminated. +1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4830 .loc 1 1971 3 view .LVU1549 +1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + 4831 .loc 1 1973 3 view .LVU1550 + 4832 .loc 1 1973 19 is_stmt 0 view .LVU1551 + 4833 0000 D0F80838 ldr r3, [r0, #2056] + 4834 .loc 1 1973 8 view .LVU1552 + 4835 0004 00F50060 add r0, r0, #2048 + 4836 .LVL406: + 4837 .loc 1 1973 6 view .LVU1553 + 4838 0008 13F0010F tst r3, #1 + 4839 000c 03D0 beq .L310 +1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { +1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* active Remote wakeup signalling */ +1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + 4840 .loc 1 1976 5 is_stmt 1 view .LVU1554 + 4841 .loc 1 1976 23 is_stmt 0 view .LVU1555 + 4842 000e 4368 ldr r3, [r0, #4] + 4843 0010 43F00103 orr r3, r3, #1 + 4844 0014 4360 str r3, [r0, #4] + 4845 .L310: +1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } +1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4846 .loc 1 1979 3 is_stmt 1 view .LVU1556 +1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4847 .loc 1 1980 1 is_stmt 0 view .LVU1557 + 4848 0016 0020 movs r0, #0 + 4849 .LVL407: + 4850 .loc 1 1980 1 view .LVU1558 + 4851 0018 7047 bx lr + 4852 .cfi_endproc + 4853 .LFE187: + 4855 .section .text.USB_DeActivateRemoteWakeup,"ax",%progbits + 4856 .align 1 + 4857 .global USB_DeActivateRemoteWakeup + 4858 .syntax unified + 4859 .thumb + 4860 .thumb_func + 4861 .fpu fpv5-d16 + 4863 USB_DeActivateRemoteWakeup: + 4864 .LVL408: + 4865 .LFB188: +1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /** +1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling +1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @param USBx Selected device +1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** * @retval HAL status +1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** */ + ARM GAS /tmp/cc9mtr28.s page 142 + + +1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** { + 4866 .loc 1 1988 1 is_stmt 1 view -0 + 4867 .cfi_startproc + 4868 @ args = 0, pretend = 0, frame = 0 + 4869 @ frame_needed = 0, uses_anonymous_args = 0 + 4870 @ link register save eliminated. +1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** uint32_t USBx_BASE = (uint32_t)USBx; + 4871 .loc 1 1989 3 view .LVU1560 +1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** /* active Remote wakeup signalling */ +1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + 4872 .loc 1 1992 3 view .LVU1561 + 4873 .loc 1 1992 21 is_stmt 0 view .LVU1562 + 4874 0000 D0F80438 ldr r3, [r0, #2052] + 4875 0004 23F00103 bic r3, r3, #1 + 4876 0008 C0F80438 str r3, [r0, #2052] +1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** +1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** return HAL_OK; + 4877 .loc 1 1994 3 is_stmt 1 view .LVU1563 +1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c **** } + 4878 .loc 1 1995 1 is_stmt 0 view .LVU1564 + 4879 000c 0020 movs r0, #0 + 4880 .LVL409: + 4881 .loc 1 1995 1 view .LVU1565 + 4882 000e 7047 bx lr + 4883 .cfi_endproc + 4884 .LFE188: + 4886 .section .bss.tmpreg.0,"aw",%nobits + 4887 .align 2 + 4888 .set .LANCHOR0,. + 0 + 4891 tmpreg.0: + 4892 0000 00000000 .space 4 + 4893 .text + 4894 .Letext0: + 4895 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 4896 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 4897 .file 4 "Drivers/CMSIS/Include/cmsis_gcc.h" + 4898 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 4899 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 4900 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h" + 4901 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + ARM GAS /tmp/cc9mtr28.s page 143 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32h7xx_ll_usb.c + /tmp/cc9mtr28.s:17 .text.USB_CoreReset:0000000000000000 $t + /tmp/cc9mtr28.s:24 .text.USB_CoreReset:0000000000000000 USB_CoreReset + /tmp/cc9mtr28.s:101 .text.USB_CoreReset:0000000000000038 $d + /tmp/cc9mtr28.s:106 .text.USB_CoreInit:0000000000000000 $t + /tmp/cc9mtr28.s:113 .text.USB_CoreInit:0000000000000000 USB_CoreInit + /tmp/cc9mtr28.s:247 .text.USB_CoreInit:0000000000000088 $d + /tmp/cc9mtr28.s:252 .text.USB_SetTurnaroundTime:0000000000000000 $t + /tmp/cc9mtr28.s:259 .text.USB_SetTurnaroundTime:0000000000000000 USB_SetTurnaroundTime + /tmp/cc9mtr28.s:439 .text.USB_SetTurnaroundTime:000000000000009c $d + /tmp/cc9mtr28.s:461 .text.USB_EnableGlobalInt:0000000000000000 $t + /tmp/cc9mtr28.s:468 .text.USB_EnableGlobalInt:0000000000000000 USB_EnableGlobalInt + /tmp/cc9mtr28.s:491 .text.USB_DisableGlobalInt:0000000000000000 $t + /tmp/cc9mtr28.s:498 .text.USB_DisableGlobalInt:0000000000000000 USB_DisableGlobalInt + /tmp/cc9mtr28.s:521 .text.USB_SetCurrentMode:0000000000000000 $t + /tmp/cc9mtr28.s:528 .text.USB_SetCurrentMode:0000000000000000 USB_SetCurrentMode + /tmp/cc9mtr28.s:589 .text.USB_FlushTxFifo:0000000000000000 $t + /tmp/cc9mtr28.s:596 .text.USB_FlushTxFifo:0000000000000000 USB_FlushTxFifo + /tmp/cc9mtr28.s:647 .text.USB_FlushTxFifo:0000000000000024 $d + /tmp/cc9mtr28.s:652 .text.USB_FlushRxFifo:0000000000000000 $t + /tmp/cc9mtr28.s:659 .text.USB_FlushRxFifo:0000000000000000 USB_FlushRxFifo + /tmp/cc9mtr28.s:706 .text.USB_FlushRxFifo:0000000000000020 $d + /tmp/cc9mtr28.s:711 .text.USB_SetDevSpeed:0000000000000000 $t + /tmp/cc9mtr28.s:718 .text.USB_SetDevSpeed:0000000000000000 USB_SetDevSpeed + /tmp/cc9mtr28.s:744 .text.USB_DevInit:0000000000000000 $t + /tmp/cc9mtr28.s:751 .text.USB_DevInit:0000000000000000 USB_DevInit + /tmp/cc9mtr28.s:1110 .text.USB_DevInit:0000000000000180 $d + /tmp/cc9mtr28.s:1116 .text.USB_GetDevSpeed:0000000000000000 $t + /tmp/cc9mtr28.s:1123 .text.USB_GetDevSpeed:0000000000000000 USB_GetDevSpeed + /tmp/cc9mtr28.s:1173 .text.USB_ActivateEndpoint:0000000000000000 $t + /tmp/cc9mtr28.s:1180 .text.USB_ActivateEndpoint:0000000000000000 USB_ActivateEndpoint + /tmp/cc9mtr28.s:1296 .text.USB_ActivateEndpoint:0000000000000098 $d + /tmp/cc9mtr28.s:1301 .text.USB_ActivateDedicatedEndpoint:0000000000000000 $t + /tmp/cc9mtr28.s:1308 .text.USB_ActivateDedicatedEndpoint:0000000000000000 USB_ActivateDedicatedEndpoint + /tmp/cc9mtr28.s:1442 .text.USB_ActivateDedicatedEndpoint:0000000000000098 $d + /tmp/cc9mtr28.s:1447 .text.USB_DeactivateEndpoint:0000000000000000 $t + /tmp/cc9mtr28.s:1454 .text.USB_DeactivateEndpoint:0000000000000000 USB_DeactivateEndpoint + /tmp/cc9mtr28.s:1619 .text.USB_DeactivateEndpoint:00000000000000d8 $d + /tmp/cc9mtr28.s:1625 .text.USB_DeactivateDedicatedEndpoint:0000000000000000 $t + /tmp/cc9mtr28.s:1632 .text.USB_DeactivateDedicatedEndpoint:0000000000000000 USB_DeactivateDedicatedEndpoint + /tmp/cc9mtr28.s:1755 .text.USB_EP0StartXfer:0000000000000000 $t + /tmp/cc9mtr28.s:1762 .text.USB_EP0StartXfer:0000000000000000 USB_EP0StartXfer + /tmp/cc9mtr28.s:2000 .text.USB_EP0StartXfer:0000000000000114 $d + /tmp/cc9mtr28.s:2006 .text.USB_WritePacket:0000000000000000 $t + /tmp/cc9mtr28.s:2013 .text.USB_WritePacket:0000000000000000 USB_WritePacket + /tmp/cc9mtr28.s:2080 .text.USB_EPStartXfer:0000000000000000 $t + /tmp/cc9mtr28.s:2087 .text.USB_EPStartXfer:0000000000000000 USB_EPStartXfer + /tmp/cc9mtr28.s:2481 .text.USB_EPStartXfer:0000000000000228 $d + /tmp/cc9mtr28.s:2488 .text.USB_ReadPacket:0000000000000000 $t + /tmp/cc9mtr28.s:2495 .text.USB_ReadPacket:0000000000000000 USB_ReadPacket + /tmp/cc9mtr28.s:2546 .text.USB_EPSetStall:0000000000000000 $t + /tmp/cc9mtr28.s:2553 .text.USB_EPSetStall:0000000000000000 USB_EPSetStall + /tmp/cc9mtr28.s:2634 .text.USB_EPClearStall:0000000000000000 $t + /tmp/cc9mtr28.s:2641 .text.USB_EPClearStall:0000000000000000 USB_EPClearStall + /tmp/cc9mtr28.s:2724 .text.USB_StopDevice:0000000000000000 $t + /tmp/cc9mtr28.s:2731 .text.USB_StopDevice:0000000000000000 USB_StopDevice + ARM GAS /tmp/cc9mtr28.s page 144 + + + /tmp/cc9mtr28.s:2814 .text.USB_SetDevAddress:0000000000000000 $t + /tmp/cc9mtr28.s:2821 .text.USB_SetDevAddress:0000000000000000 USB_SetDevAddress + /tmp/cc9mtr28.s:2856 .text.USB_DevConnect:0000000000000000 $t + /tmp/cc9mtr28.s:2863 .text.USB_DevConnect:0000000000000000 USB_DevConnect + /tmp/cc9mtr28.s:2897 .text.USB_DevDisconnect:0000000000000000 $t + /tmp/cc9mtr28.s:2904 .text.USB_DevDisconnect:0000000000000000 USB_DevDisconnect + /tmp/cc9mtr28.s:2938 .text.USB_ReadInterrupts:0000000000000000 $t + /tmp/cc9mtr28.s:2945 .text.USB_ReadInterrupts:0000000000000000 USB_ReadInterrupts + /tmp/cc9mtr28.s:2972 .text.USB_ReadDevAllOutEpInterrupt:0000000000000000 $t + /tmp/cc9mtr28.s:2979 .text.USB_ReadDevAllOutEpInterrupt:0000000000000000 USB_ReadDevAllOutEpInterrupt + /tmp/cc9mtr28.s:3012 .text.USB_ReadDevAllInEpInterrupt:0000000000000000 $t + /tmp/cc9mtr28.s:3019 .text.USB_ReadDevAllInEpInterrupt:0000000000000000 USB_ReadDevAllInEpInterrupt + /tmp/cc9mtr28.s:3052 .text.USB_ReadDevOutEPInterrupt:0000000000000000 $t + /tmp/cc9mtr28.s:3059 .text.USB_ReadDevOutEPInterrupt:0000000000000000 USB_ReadDevOutEPInterrupt + /tmp/cc9mtr28.s:3093 .text.USB_ReadDevInEPInterrupt:0000000000000000 $t + /tmp/cc9mtr28.s:3100 .text.USB_ReadDevInEPInterrupt:0000000000000000 USB_ReadDevInEPInterrupt + /tmp/cc9mtr28.s:3159 .text.USB_ClearInterrupts:0000000000000000 $t + /tmp/cc9mtr28.s:3166 .text.USB_ClearInterrupts:0000000000000000 USB_ClearInterrupts + /tmp/cc9mtr28.s:3185 .text.USB_GetMode:0000000000000000 $t + /tmp/cc9mtr28.s:3192 .text.USB_GetMode:0000000000000000 USB_GetMode + /tmp/cc9mtr28.s:3211 .text.USB_ActivateSetup:0000000000000000 $t + /tmp/cc9mtr28.s:3218 .text.USB_ActivateSetup:0000000000000000 USB_ActivateSetup + /tmp/cc9mtr28.s:3247 .text.USB_ActivateSetup:000000000000001c $d + /tmp/cc9mtr28.s:3252 .text.USB_EP0_OutStart:0000000000000000 $t + /tmp/cc9mtr28.s:3259 .text.USB_EP0_OutStart:0000000000000000 USB_EP0_OutStart + /tmp/cc9mtr28.s:3342 .text.USB_EP0_OutStart:000000000000005c $d + /tmp/cc9mtr28.s:3347 .text.USB_InitFSLSPClkSel:0000000000000000 $t + /tmp/cc9mtr28.s:3354 .text.USB_InitFSLSPClkSel:0000000000000000 USB_InitFSLSPClkSel + /tmp/cc9mtr28.s:3410 .text.USB_ResetPort:0000000000000000 $t + /tmp/cc9mtr28.s:3417 .text.USB_ResetPort:0000000000000000 USB_ResetPort + /tmp/cc9mtr28.s:3486 .text.USB_DriveVbus:0000000000000000 $t + /tmp/cc9mtr28.s:3493 .text.USB_DriveVbus:0000000000000000 USB_DriveVbus + /tmp/cc9mtr28.s:3572 .text.USB_HostInit:0000000000000000 $t + /tmp/cc9mtr28.s:3579 .text.USB_HostInit:0000000000000000 USB_HostInit + /tmp/cc9mtr28.s:3776 .text.USB_HostInit:00000000000000e8 $d + /tmp/cc9mtr28.s:3783 .text.USB_GetHostSpeed:0000000000000000 $t + /tmp/cc9mtr28.s:3790 .text.USB_GetHostSpeed:0000000000000000 USB_GetHostSpeed + /tmp/cc9mtr28.s:3828 .text.USB_GetCurrentFrame:0000000000000000 $t + /tmp/cc9mtr28.s:3835 .text.USB_GetCurrentFrame:0000000000000000 USB_GetCurrentFrame + /tmp/cc9mtr28.s:3858 .text.USB_HC_Init:0000000000000000 $t + /tmp/cc9mtr28.s:3865 .text.USB_HC_Init:0000000000000000 USB_HC_Init + /tmp/cc9mtr28.s:3899 .text.USB_HC_Init:0000000000000020 $d + /tmp/cc9mtr28.s:3903 .text.USB_HC_Init:0000000000000024 $t + /tmp/cc9mtr28.s:4084 .text.USB_HC_ReadInterrupt:0000000000000000 $t + /tmp/cc9mtr28.s:4091 .text.USB_HC_ReadInterrupt:0000000000000000 USB_HC_ReadInterrupt + /tmp/cc9mtr28.s:4114 .text.USB_HC_Halt:0000000000000000 $t + /tmp/cc9mtr28.s:4121 .text.USB_HC_Halt:0000000000000000 USB_HC_Halt + /tmp/cc9mtr28.s:4274 .text.USB_DoPing:0000000000000000 $t + /tmp/cc9mtr28.s:4281 .text.USB_DoPing:0000000000000000 USB_DoPing + /tmp/cc9mtr28.s:4323 .text.USB_DoPing:0000000000000020 $d + /tmp/cc9mtr28.s:4328 .text.USB_HC_StartXfer:0000000000000000 $t + /tmp/cc9mtr28.s:4335 .text.USB_HC_StartXfer:0000000000000000 USB_HC_StartXfer + /tmp/cc9mtr28.s:4569 .text.USB_HC_StartXfer:0000000000000108 $d + /tmp/cc9mtr28.s:4574 .text.USB_HC_StartXfer:000000000000010c $t + /tmp/cc9mtr28.s:4657 .text.USB_HC_StartXfer:000000000000015c $d + /tmp/cc9mtr28.s:4663 .text.USB_StopHost:0000000000000000 $t + /tmp/cc9mtr28.s:4670 .text.USB_StopHost:0000000000000000 USB_StopHost + ARM GAS /tmp/cc9mtr28.s page 145 + + + /tmp/cc9mtr28.s:4815 .text.USB_ActivateRemoteWakeup:0000000000000000 $t + /tmp/cc9mtr28.s:4822 .text.USB_ActivateRemoteWakeup:0000000000000000 USB_ActivateRemoteWakeup + /tmp/cc9mtr28.s:4856 .text.USB_DeActivateRemoteWakeup:0000000000000000 $t + /tmp/cc9mtr28.s:4863 .text.USB_DeActivateRemoteWakeup:0000000000000000 USB_DeActivateRemoteWakeup + /tmp/cc9mtr28.s:4887 .bss.tmpreg.0:0000000000000000 $d + /tmp/cc9mtr28.s:4891 .bss.tmpreg.0:0000000000000000 tmpreg.0 + +UNDEFINED SYMBOLS +HAL_Delay diff --git a/build/stm32h7xx_ll_usb.o b/build/stm32h7xx_ll_usb.o new file mode 100644 index 0000000..aaa28ce Binary files /dev/null and b/build/stm32h7xx_ll_usb.o differ diff --git a/build/system_stm32h7xx.d b/build/system_stm32h7xx.d new file mode 100644 index 0000000..545befb --- /dev/null +++ b/build/system_stm32h7xx.d @@ -0,0 +1,67 @@ +build/system_stm32h7xx.o: Core/Src/system_stm32h7xx.c \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: diff --git a/build/system_stm32h7xx.lst b/build/system_stm32h7xx.lst new file mode 100644 index 0000000..bbf6e1f --- /dev/null +++ b/build/system_stm32h7xx.lst @@ -0,0 +1,1028 @@ +ARM GAS /tmp/ccLsdpLF.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "system_stm32h7xx.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.SystemInit,"ax",%progbits + 17 .align 1 + 18 .global SystemInit + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 SystemInit: + 26 .LFB141: + 27 .file 1 "Core/Src/system_stm32h7xx.c" + 1:Core/Src/system_stm32h7xx.c **** /** + 2:Core/Src/system_stm32h7xx.c **** ****************************************************************************** + 3:Core/Src/system_stm32h7xx.c **** * @file system_stm32h7xx.c + 4:Core/Src/system_stm32h7xx.c **** * @author MCD Application Team + 5:Core/Src/system_stm32h7xx.c **** * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + 6:Core/Src/system_stm32h7xx.c **** * + 7:Core/Src/system_stm32h7xx.c **** * This file provides two functions and one global variable to be called from + 8:Core/Src/system_stm32h7xx.c **** * user application: + 9:Core/Src/system_stm32h7xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:Core/Src/system_stm32h7xx.c **** * before branch to main program. This call is made inside + 11:Core/Src/system_stm32h7xx.c **** * the "startup_stm32h7xx.s" file. + 12:Core/Src/system_stm32h7xx.c **** * + 13:Core/Src/system_stm32h7xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:Core/Src/system_stm32h7xx.c **** * by the user application to setup the SysTick + 15:Core/Src/system_stm32h7xx.c **** * timer or configure other parameters. + 16:Core/Src/system_stm32h7xx.c **** * + 17:Core/Src/system_stm32h7xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:Core/Src/system_stm32h7xx.c **** * be called whenever the core clock is changed + 19:Core/Src/system_stm32h7xx.c **** * during program execution. + 20:Core/Src/system_stm32h7xx.c **** * + 21:Core/Src/system_stm32h7xx.c **** * + 22:Core/Src/system_stm32h7xx.c **** ****************************************************************************** + 23:Core/Src/system_stm32h7xx.c **** * @attention + 24:Core/Src/system_stm32h7xx.c **** * + 25:Core/Src/system_stm32h7xx.c **** *

© Copyright (c) 2017 STMicroelectronics. + 26:Core/Src/system_stm32h7xx.c **** * All rights reserved.

+ 27:Core/Src/system_stm32h7xx.c **** * + 28:Core/Src/system_stm32h7xx.c **** * This software component is licensed by ST under BSD 3-Clause license, + 29:Core/Src/system_stm32h7xx.c **** * the "License"; You may not use this file except in compliance with the + 30:Core/Src/system_stm32h7xx.c **** * License. You may obtain a copy of the License at: + 31:Core/Src/system_stm32h7xx.c **** * opensource.org/licenses/BSD-3-Clause + ARM GAS /tmp/ccLsdpLF.s page 2 + + + 32:Core/Src/system_stm32h7xx.c **** * + 33:Core/Src/system_stm32h7xx.c **** ****************************************************************************** + 34:Core/Src/system_stm32h7xx.c **** */ + 35:Core/Src/system_stm32h7xx.c **** + 36:Core/Src/system_stm32h7xx.c **** /** @addtogroup CMSIS + 37:Core/Src/system_stm32h7xx.c **** * @{ + 38:Core/Src/system_stm32h7xx.c **** */ + 39:Core/Src/system_stm32h7xx.c **** + 40:Core/Src/system_stm32h7xx.c **** /** @addtogroup stm32h7xx_system + 41:Core/Src/system_stm32h7xx.c **** * @{ + 42:Core/Src/system_stm32h7xx.c **** */ + 43:Core/Src/system_stm32h7xx.c **** + 44:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Includes + 45:Core/Src/system_stm32h7xx.c **** * @{ + 46:Core/Src/system_stm32h7xx.c **** */ + 47:Core/Src/system_stm32h7xx.c **** + 48:Core/Src/system_stm32h7xx.c **** #include "stm32h7xx.h" + 49:Core/Src/system_stm32h7xx.c **** #include + 50:Core/Src/system_stm32h7xx.c **** #if !defined (HSE_VALUE) + 51:Core/Src/system_stm32h7xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + 52:Core/Src/system_stm32h7xx.c **** #endif /* HSE_VALUE */ + 53:Core/Src/system_stm32h7xx.c **** + 54:Core/Src/system_stm32h7xx.c **** #if !defined (CSI_VALUE) + 55:Core/Src/system_stm32h7xx.c **** #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ + 56:Core/Src/system_stm32h7xx.c **** #endif /* CSI_VALUE */ + 57:Core/Src/system_stm32h7xx.c **** + 58:Core/Src/system_stm32h7xx.c **** #if !defined (HSI_VALUE) + 59:Core/Src/system_stm32h7xx.c **** #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ + 60:Core/Src/system_stm32h7xx.c **** #endif /* HSI_VALUE */ + 61:Core/Src/system_stm32h7xx.c **** + 62:Core/Src/system_stm32h7xx.c **** + 63:Core/Src/system_stm32h7xx.c **** /** + 64:Core/Src/system_stm32h7xx.c **** * @} + 65:Core/Src/system_stm32h7xx.c **** */ + 66:Core/Src/system_stm32h7xx.c **** + 67:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_TypesDefinitions + 68:Core/Src/system_stm32h7xx.c **** * @{ + 69:Core/Src/system_stm32h7xx.c **** */ + 70:Core/Src/system_stm32h7xx.c **** + 71:Core/Src/system_stm32h7xx.c **** /** + 72:Core/Src/system_stm32h7xx.c **** * @} + 73:Core/Src/system_stm32h7xx.c **** */ + 74:Core/Src/system_stm32h7xx.c **** + 75:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Defines + 76:Core/Src/system_stm32h7xx.c **** * @{ + 77:Core/Src/system_stm32h7xx.c **** */ + 78:Core/Src/system_stm32h7xx.c **** + 79:Core/Src/system_stm32h7xx.c **** /************************* Miscellaneous Configuration ************************/ + 80:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) + 81:Core/Src/system_stm32h7xx.c **** /* #define DATA_IN_D2_SRAM */ + 82:Core/Src/system_stm32h7xx.c **** + 83:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in + 84:Core/Src/system_stm32h7xx.c **** Internal SRAM. */ + 85:Core/Src/system_stm32h7xx.c **** /* #define VECT_TAB_SRAM */ + 86:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + 87:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x200. */ + 88:Core/Src/system_stm32h7xx.c **** /******************************************************************************/ + ARM GAS /tmp/ccLsdpLF.s page 3 + + + 89:Core/Src/system_stm32h7xx.c **** + 90:Core/Src/system_stm32h7xx.c **** /** + 91:Core/Src/system_stm32h7xx.c **** * @} + 92:Core/Src/system_stm32h7xx.c **** */ + 93:Core/Src/system_stm32h7xx.c **** + 94:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Macros + 95:Core/Src/system_stm32h7xx.c **** * @{ + 96:Core/Src/system_stm32h7xx.c **** */ + 97:Core/Src/system_stm32h7xx.c **** + 98:Core/Src/system_stm32h7xx.c **** /** + 99:Core/Src/system_stm32h7xx.c **** * @} + 100:Core/Src/system_stm32h7xx.c **** */ + 101:Core/Src/system_stm32h7xx.c **** + 102:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Variables + 103:Core/Src/system_stm32h7xx.c **** * @{ + 104:Core/Src/system_stm32h7xx.c **** */ + 105:Core/Src/system_stm32h7xx.c **** /* This variable is updated in three ways: + 106:Core/Src/system_stm32h7xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 107:Core/Src/system_stm32h7xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 108:Core/Src/system_stm32h7xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 109:Core/Src/system_stm32h7xx.c **** Note: If you use this function to configure the system clock; then there + 110:Core/Src/system_stm32h7xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock + 111:Core/Src/system_stm32h7xx.c **** variable is updated automatically. + 112:Core/Src/system_stm32h7xx.c **** */ + 113:Core/Src/system_stm32h7xx.c **** uint32_t SystemCoreClock = 64000000; + 114:Core/Src/system_stm32h7xx.c **** uint32_t SystemD2Clock = 64000000; + 115:Core/Src/system_stm32h7xx.c **** const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + 116:Core/Src/system_stm32h7xx.c **** + 117:Core/Src/system_stm32h7xx.c **** /** + 118:Core/Src/system_stm32h7xx.c **** * @} + 119:Core/Src/system_stm32h7xx.c **** */ + 120:Core/Src/system_stm32h7xx.c **** + 121:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + 122:Core/Src/system_stm32h7xx.c **** * @{ + 123:Core/Src/system_stm32h7xx.c **** */ + 124:Core/Src/system_stm32h7xx.c **** + 125:Core/Src/system_stm32h7xx.c **** /** + 126:Core/Src/system_stm32h7xx.c **** * @} + 127:Core/Src/system_stm32h7xx.c **** */ + 128:Core/Src/system_stm32h7xx.c **** + 129:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Functions + 130:Core/Src/system_stm32h7xx.c **** * @{ + 131:Core/Src/system_stm32h7xx.c **** */ + 132:Core/Src/system_stm32h7xx.c **** + 133:Core/Src/system_stm32h7xx.c **** /** + 134:Core/Src/system_stm32h7xx.c **** * @brief Setup the microcontroller system + 135:Core/Src/system_stm32h7xx.c **** * Initialize the FPU setting and vector table location + 136:Core/Src/system_stm32h7xx.c **** * configuration. + 137:Core/Src/system_stm32h7xx.c **** * @param None + 138:Core/Src/system_stm32h7xx.c **** * @retval None + 139:Core/Src/system_stm32h7xx.c **** */ + 140:Core/Src/system_stm32h7xx.c **** void SystemInit (void) + 141:Core/Src/system_stm32h7xx.c **** { + 28 .loc 1 141 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccLsdpLF.s page 4 + + + 32 @ link register save eliminated. + 142:Core/Src/system_stm32h7xx.c **** #if defined (DATA_IN_D2_SRAM) + 143:Core/Src/system_stm32h7xx.c **** __IO uint32_t tmpreg; + 144:Core/Src/system_stm32h7xx.c **** #endif /* DATA_IN_D2_SRAM */ + 145:Core/Src/system_stm32h7xx.c **** + 146:Core/Src/system_stm32h7xx.c **** /* FPU settings ------------------------------------------------------------*/ + 147:Core/Src/system_stm32h7xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + 148:Core/Src/system_stm32h7xx.c **** SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + 33 .loc 1 148 5 view .LVU1 + 34 .loc 1 148 16 is_stmt 0 view .LVU2 + 35 0000 184A ldr r2, .L3 + 36 0002 D2F88830 ldr r3, [r2, #136] + 37 0006 43F47003 orr r3, r3, #15728640 + 38 000a C2F88830 str r3, [r2, #136] + 149:Core/Src/system_stm32h7xx.c **** #endif + 150:Core/Src/system_stm32h7xx.c **** /* Reset the RCC clock configuration to the default reset state ------------*/ + 151:Core/Src/system_stm32h7xx.c **** /* Set HSION bit */ + 152:Core/Src/system_stm32h7xx.c **** RCC->CR |= RCC_CR_HSION; + 39 .loc 1 152 3 is_stmt 1 view .LVU3 + 40 .loc 1 152 11 is_stmt 0 view .LVU4 + 41 000e 164B ldr r3, .L3+4 + 42 0010 1A68 ldr r2, [r3] + 43 0012 42F00102 orr r2, r2, #1 + 44 0016 1A60 str r2, [r3] + 153:Core/Src/system_stm32h7xx.c **** + 154:Core/Src/system_stm32h7xx.c **** /* Reset CFGR register */ + 155:Core/Src/system_stm32h7xx.c **** RCC->CFGR = 0x00000000; + 45 .loc 1 155 3 is_stmt 1 view .LVU5 + 46 .loc 1 155 13 is_stmt 0 view .LVU6 + 47 0018 0022 movs r2, #0 + 48 001a 1A61 str r2, [r3, #16] + 156:Core/Src/system_stm32h7xx.c **** + 157:Core/Src/system_stm32h7xx.c **** /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + 158:Core/Src/system_stm32h7xx.c **** RCC->CR &= 0xEAF6ED7FU; + 49 .loc 1 158 3 is_stmt 1 view .LVU7 + 50 .loc 1 158 11 is_stmt 0 view .LVU8 + 51 001c 1868 ldr r0, [r3] + 52 001e 1349 ldr r1, .L3+8 + 53 0020 0140 ands r1, r1, r0 + 54 0022 1960 str r1, [r3] + 159:Core/Src/system_stm32h7xx.c **** + 160:Core/Src/system_stm32h7xx.c **** /* Reset D1CFGR register */ + 161:Core/Src/system_stm32h7xx.c **** RCC->D1CFGR = 0x00000000; + 55 .loc 1 161 3 is_stmt 1 view .LVU9 + 56 .loc 1 161 15 is_stmt 0 view .LVU10 + 57 0024 9A61 str r2, [r3, #24] + 162:Core/Src/system_stm32h7xx.c **** + 163:Core/Src/system_stm32h7xx.c **** /* Reset D2CFGR register */ + 164:Core/Src/system_stm32h7xx.c **** RCC->D2CFGR = 0x00000000; + 58 .loc 1 164 3 is_stmt 1 view .LVU11 + 59 .loc 1 164 15 is_stmt 0 view .LVU12 + 60 0026 DA61 str r2, [r3, #28] + 165:Core/Src/system_stm32h7xx.c **** + 166:Core/Src/system_stm32h7xx.c **** /* Reset D3CFGR register */ + 167:Core/Src/system_stm32h7xx.c **** RCC->D3CFGR = 0x00000000; + 61 .loc 1 167 3 is_stmt 1 view .LVU13 + 62 .loc 1 167 15 is_stmt 0 view .LVU14 + ARM GAS /tmp/ccLsdpLF.s page 5 + + + 63 0028 1A62 str r2, [r3, #32] + 168:Core/Src/system_stm32h7xx.c **** + 169:Core/Src/system_stm32h7xx.c **** /* Reset PLLCKSELR register */ + 170:Core/Src/system_stm32h7xx.c **** RCC->PLLCKSELR = 0x00000000; + 64 .loc 1 170 3 is_stmt 1 view .LVU15 + 65 .loc 1 170 18 is_stmt 0 view .LVU16 + 66 002a 9A62 str r2, [r3, #40] + 171:Core/Src/system_stm32h7xx.c **** + 172:Core/Src/system_stm32h7xx.c **** /* Reset PLLCFGR register */ + 173:Core/Src/system_stm32h7xx.c **** RCC->PLLCFGR = 0x00000000; + 67 .loc 1 173 3 is_stmt 1 view .LVU17 + 68 .loc 1 173 16 is_stmt 0 view .LVU18 + 69 002c DA62 str r2, [r3, #44] + 174:Core/Src/system_stm32h7xx.c **** /* Reset PLL1DIVR register */ + 175:Core/Src/system_stm32h7xx.c **** RCC->PLL1DIVR = 0x00000000; + 70 .loc 1 175 3 is_stmt 1 view .LVU19 + 71 .loc 1 175 17 is_stmt 0 view .LVU20 + 72 002e 1A63 str r2, [r3, #48] + 176:Core/Src/system_stm32h7xx.c **** /* Reset PLL1FRACR register */ + 177:Core/Src/system_stm32h7xx.c **** RCC->PLL1FRACR = 0x00000000; + 73 .loc 1 177 3 is_stmt 1 view .LVU21 + 74 .loc 1 177 18 is_stmt 0 view .LVU22 + 75 0030 5A63 str r2, [r3, #52] + 178:Core/Src/system_stm32h7xx.c **** + 179:Core/Src/system_stm32h7xx.c **** /* Reset PLL2DIVR register */ + 180:Core/Src/system_stm32h7xx.c **** RCC->PLL2DIVR = 0x00000000; + 76 .loc 1 180 3 is_stmt 1 view .LVU23 + 77 .loc 1 180 17 is_stmt 0 view .LVU24 + 78 0032 9A63 str r2, [r3, #56] + 181:Core/Src/system_stm32h7xx.c **** + 182:Core/Src/system_stm32h7xx.c **** /* Reset PLL2FRACR register */ + 183:Core/Src/system_stm32h7xx.c **** + 184:Core/Src/system_stm32h7xx.c **** RCC->PLL2FRACR = 0x00000000; + 79 .loc 1 184 3 is_stmt 1 view .LVU25 + 80 .loc 1 184 18 is_stmt 0 view .LVU26 + 81 0034 DA63 str r2, [r3, #60] + 185:Core/Src/system_stm32h7xx.c **** /* Reset PLL3DIVR register */ + 186:Core/Src/system_stm32h7xx.c **** RCC->PLL3DIVR = 0x00000000; + 82 .loc 1 186 3 is_stmt 1 view .LVU27 + 83 .loc 1 186 17 is_stmt 0 view .LVU28 + 84 0036 1A64 str r2, [r3, #64] + 187:Core/Src/system_stm32h7xx.c **** + 188:Core/Src/system_stm32h7xx.c **** /* Reset PLL3FRACR register */ + 189:Core/Src/system_stm32h7xx.c **** RCC->PLL3FRACR = 0x00000000; + 85 .loc 1 189 3 is_stmt 1 view .LVU29 + 86 .loc 1 189 18 is_stmt 0 view .LVU30 + 87 0038 5A64 str r2, [r3, #68] + 190:Core/Src/system_stm32h7xx.c **** + 191:Core/Src/system_stm32h7xx.c **** /* Reset HSEBYP bit */ + 192:Core/Src/system_stm32h7xx.c **** RCC->CR &= 0xFFFBFFFFU; + 88 .loc 1 192 3 is_stmt 1 view .LVU31 + 89 .loc 1 192 11 is_stmt 0 view .LVU32 + 90 003a 1968 ldr r1, [r3] + 91 003c 21F48021 bic r1, r1, #262144 + 92 0040 1960 str r1, [r3] + 193:Core/Src/system_stm32h7xx.c **** + 194:Core/Src/system_stm32h7xx.c **** /* Disable all interrupts */ + ARM GAS /tmp/ccLsdpLF.s page 6 + + + 195:Core/Src/system_stm32h7xx.c **** RCC->CIER = 0x00000000; + 93 .loc 1 195 3 is_stmt 1 view .LVU33 + 94 .loc 1 195 13 is_stmt 0 view .LVU34 + 95 0042 1A66 str r2, [r3, #96] + 196:Core/Src/system_stm32h7xx.c **** + 197:Core/Src/system_stm32h7xx.c **** #if defined (DATA_IN_D2_SRAM) + 198:Core/Src/system_stm32h7xx.c **** /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock ((AHB SRAM clock) + 199:Core/Src/system_stm32h7xx.c **** #if defined(RCC_AHB2ENR_D2SRAM1EN) + 200:Core/Src/system_stm32h7xx.c **** RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); + 201:Core/Src/system_stm32h7xx.c **** #else + 202:Core/Src/system_stm32h7xx.c **** RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); + 203:Core/Src/system_stm32h7xx.c **** #endif /* RCC_AHB2ENR_D2SRAM1EN */ + 204:Core/Src/system_stm32h7xx.c **** + 205:Core/Src/system_stm32h7xx.c **** tmpreg = RCC->AHB2ENR; + 206:Core/Src/system_stm32h7xx.c **** (void) tmpreg; + 207:Core/Src/system_stm32h7xx.c **** #endif /* DATA_IN_D2_SRAM */ + 208:Core/Src/system_stm32h7xx.c **** + 209:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4) + 210:Core/Src/system_stm32h7xx.c **** /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ + 211:Core/Src/system_stm32h7xx.c **** #ifdef VECT_TAB_SRAM + 212:Core/Src/system_stm32h7xx.c **** SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + 213:Core/Src/system_stm32h7xx.c **** #else + 214:Core/Src/system_stm32h7xx.c **** SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 215:Core/Src/system_stm32h7xx.c **** #endif /* VECT_TAB_SRAM */ + 216:Core/Src/system_stm32h7xx.c **** + 217:Core/Src/system_stm32h7xx.c **** #else + 218:Core/Src/system_stm32h7xx.c **** /* dual core CM7 or single core line */ + 219:Core/Src/system_stm32h7xx.c **** if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + 96 .loc 1 219 3 is_stmt 1 view .LVU35 + 97 .loc 1 219 13 is_stmt 0 view .LVU36 + 98 0044 0A4B ldr r3, .L3+12 + 99 0046 1A68 ldr r2, [r3] + 100 .loc 1 219 22 view .LVU37 + 101 0048 0A4B ldr r3, .L3+16 + 102 004a 1340 ands r3, r3, r2 + 103 .loc 1 219 5 view .LVU38 + 104 004c B3F1005F cmp r3, #536870912 + 105 0050 03D2 bcs .L2 + 220:Core/Src/system_stm32h7xx.c **** { + 221:Core/Src/system_stm32h7xx.c **** /* if stm32h7 revY*/ + 222:Core/Src/system_stm32h7xx.c **** /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + 223:Core/Src/system_stm32h7xx.c **** *((__IO uint32_t*)0x51008108) = 0x000000001U; + 106 .loc 1 223 5 is_stmt 1 view .LVU39 + 107 .loc 1 223 35 is_stmt 0 view .LVU40 + 108 0052 094B ldr r3, .L3+20 + 109 0054 0122 movs r2, #1 + 110 0056 C3F80821 str r2, [r3, #264] + 111 .L2: + 224:Core/Src/system_stm32h7xx.c **** } + 225:Core/Src/system_stm32h7xx.c **** + 226:Core/Src/system_stm32h7xx.c **** /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/ + 227:Core/Src/system_stm32h7xx.c **** #ifdef VECT_TAB_SRAM + 228:Core/Src/system_stm32h7xx.c **** SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM + 229:Core/Src/system_stm32h7xx.c **** #else + 230:Core/Src/system_stm32h7xx.c **** SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 112 .loc 1 230 3 is_stmt 1 view .LVU41 + 113 .loc 1 230 13 is_stmt 0 view .LVU42 + ARM GAS /tmp/ccLsdpLF.s page 7 + + + 114 005a 024B ldr r3, .L3 + 115 005c 4FF00062 mov r2, #134217728 + 116 0060 9A60 str r2, [r3, #8] + 231:Core/Src/system_stm32h7xx.c **** #endif + 232:Core/Src/system_stm32h7xx.c **** + 233:Core/Src/system_stm32h7xx.c **** #endif /*DUAL_CORE && CORE_CM4*/ + 234:Core/Src/system_stm32h7xx.c **** + 235:Core/Src/system_stm32h7xx.c **** } + 117 .loc 1 235 1 view .LVU43 + 118 0062 7047 bx lr + 119 .L4: + 120 .align 2 + 121 .L3: + 122 0064 00ED00E0 .word -536810240 + 123 0068 00440258 .word 1476543488 + 124 006c 7FEDF6EA .word -352916097 + 125 0070 0010005C .word 1543507968 + 126 0074 0000FFFF .word -65536 + 127 0078 00800051 .word 1358987264 + 128 .cfi_endproc + 129 .LFE141: + 131 .section .text.SystemCoreClockUpdate,"ax",%progbits + 132 .align 1 + 133 .global SystemCoreClockUpdate + 134 .syntax unified + 135 .thumb + 136 .thumb_func + 137 .fpu fpv5-d16 + 139 SystemCoreClockUpdate: + 140 .LFB142: + 236:Core/Src/system_stm32h7xx.c **** + 237:Core/Src/system_stm32h7xx.c **** /** + 238:Core/Src/system_stm32h7xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. + 239:Core/Src/system_stm32h7xx.c **** * The SystemCoreClock variable contains the core clock , it can + 240:Core/Src/system_stm32h7xx.c **** * be used by the user application to setup the SysTick timer or configure + 241:Core/Src/system_stm32h7xx.c **** * other parameters. + 242:Core/Src/system_stm32h7xx.c **** * + 243:Core/Src/system_stm32h7xx.c **** * @note Each time the core clock changes, this function must be called + 244:Core/Src/system_stm32h7xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 245:Core/Src/system_stm32h7xx.c **** * based on this variable will be incorrect. + 246:Core/Src/system_stm32h7xx.c **** * + 247:Core/Src/system_stm32h7xx.c **** * @note - The system frequency computed by this function is not the real + 248:Core/Src/system_stm32h7xx.c **** * frequency in the chip. It is calculated based on the predefined + 249:Core/Src/system_stm32h7xx.c **** * constant and the selected clock source: + 250:Core/Src/system_stm32h7xx.c **** * + 251:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + 252:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + 253:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + 254:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + 255:Core/Src/system_stm32h7xx.c **** * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + 256:Core/Src/system_stm32h7xx.c **** * + 257:Core/Src/system_stm32h7xx.c **** * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + 258:Core/Src/system_stm32h7xx.c **** * 4 MHz) but the real value may vary depending on the variations + 259:Core/Src/system_stm32h7xx.c **** * in voltage and temperature. + 260:Core/Src/system_stm32h7xx.c **** * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + 261:Core/Src/system_stm32h7xx.c **** * 64 MHz) but the real value may vary depending on the variations + 262:Core/Src/system_stm32h7xx.c **** * in voltage and temperature. + ARM GAS /tmp/ccLsdpLF.s page 8 + + + 263:Core/Src/system_stm32h7xx.c **** * + 264:Core/Src/system_stm32h7xx.c **** * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + 265:Core/Src/system_stm32h7xx.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real + 266:Core/Src/system_stm32h7xx.c **** * frequency of the crystal used. Otherwise, this function may + 267:Core/Src/system_stm32h7xx.c **** * have wrong result. + 268:Core/Src/system_stm32h7xx.c **** * + 269:Core/Src/system_stm32h7xx.c **** * - The result of this function could be not correct when using fractional + 270:Core/Src/system_stm32h7xx.c **** * value for HSE crystal. + 271:Core/Src/system_stm32h7xx.c **** * @param None + 272:Core/Src/system_stm32h7xx.c **** * @retval None + 273:Core/Src/system_stm32h7xx.c **** */ + 274:Core/Src/system_stm32h7xx.c **** void SystemCoreClockUpdate (void) + 275:Core/Src/system_stm32h7xx.c **** { + 141 .loc 1 275 1 is_stmt 1 view -0 + 142 .cfi_startproc + 143 @ args = 0, pretend = 0, frame = 0 + 144 @ frame_needed = 0, uses_anonymous_args = 0 + 145 @ link register save eliminated. + 146 0000 10B4 push {r4} + 147 .LCFI0: + 148 .cfi_def_cfa_offset 4 + 149 .cfi_offset 4, -4 + 276:Core/Src/system_stm32h7xx.c **** uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + 150 .loc 1 276 3 view .LVU45 + 277:Core/Src/system_stm32h7xx.c **** float_t fracn1, pllvco; + 151 .loc 1 277 3 view .LVU46 + 278:Core/Src/system_stm32h7xx.c **** + 279:Core/Src/system_stm32h7xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 280:Core/Src/system_stm32h7xx.c **** + 281:Core/Src/system_stm32h7xx.c **** switch (RCC->CFGR & RCC_CFGR_SWS) + 152 .loc 1 281 3 view .LVU47 + 153 .loc 1 281 14 is_stmt 0 view .LVU48 + 154 0002 7C4B ldr r3, .L20 + 155 0004 1B69 ldr r3, [r3, #16] + 156 .loc 1 281 21 view .LVU49 + 157 0006 03F03803 and r3, r3, #56 + 158 000a 182B cmp r3, #24 + 159 000c 00F2EE80 bhi .L6 + 160 0010 DFE813F0 tbh [pc, r3, lsl #1] + 161 .L8: + 162 0014 1900 .2byte (.L11-.L8)/2 + 163 0016 EC00 .2byte (.L6-.L8)/2 + 164 0018 EC00 .2byte (.L6-.L8)/2 + 165 001a EC00 .2byte (.L6-.L8)/2 + 166 001c EC00 .2byte (.L6-.L8)/2 + 167 001e EC00 .2byte (.L6-.L8)/2 + 168 0020 EC00 .2byte (.L6-.L8)/2 + 169 0022 EC00 .2byte (.L6-.L8)/2 + 170 0024 3900 .2byte (.L10-.L8)/2 + 171 0026 EC00 .2byte (.L6-.L8)/2 + 172 0028 EC00 .2byte (.L6-.L8)/2 + 173 002a EC00 .2byte (.L6-.L8)/2 + 174 002c EC00 .2byte (.L6-.L8)/2 + 175 002e EC00 .2byte (.L6-.L8)/2 + 176 0030 EC00 .2byte (.L6-.L8)/2 + 177 0032 EC00 .2byte (.L6-.L8)/2 + 178 0034 3D00 .2byte (.L9-.L8)/2 + ARM GAS /tmp/ccLsdpLF.s page 9 + + + 179 0036 EC00 .2byte (.L6-.L8)/2 + 180 0038 EC00 .2byte (.L6-.L8)/2 + 181 003a EC00 .2byte (.L6-.L8)/2 + 182 003c EC00 .2byte (.L6-.L8)/2 + 183 003e EC00 .2byte (.L6-.L8)/2 + 184 0040 EC00 .2byte (.L6-.L8)/2 + 185 0042 EC00 .2byte (.L6-.L8)/2 + 186 0044 4100 .2byte (.L7-.L8)/2 + 187 .p2align 1 + 188 .L11: + 282:Core/Src/system_stm32h7xx.c **** { + 283:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + 284:Core/Src/system_stm32h7xx.c **** SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + 189 .loc 1 284 5 is_stmt 1 view .LVU50 + 190 .loc 1 284 53 is_stmt 0 view .LVU51 + 191 0046 6B4B ldr r3, .L20 + 192 0048 1A68 ldr r2, [r3] + 193 .loc 1 284 74 view .LVU52 + 194 004a C2F3C102 ubfx r2, r2, #3, #2 + 195 .loc 1 284 23 view .LVU53 + 196 004e 6A4B ldr r3, .L20+4 + 197 0050 D340 lsrs r3, r3, r2 + 198 .loc 1 284 21 view .LVU54 + 199 0052 6A4A ldr r2, .L20+8 + 200 0054 1360 str r3, [r2] + 285:Core/Src/system_stm32h7xx.c **** break; + 201 .loc 1 285 5 is_stmt 1 view .LVU55 + 202 .L12: + 286:Core/Src/system_stm32h7xx.c **** + 287:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + 288:Core/Src/system_stm32h7xx.c **** SystemCoreClock = CSI_VALUE; + 289:Core/Src/system_stm32h7xx.c **** break; + 290:Core/Src/system_stm32h7xx.c **** + 291:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + 292:Core/Src/system_stm32h7xx.c **** SystemCoreClock = HSE_VALUE; + 293:Core/Src/system_stm32h7xx.c **** break; + 294:Core/Src/system_stm32h7xx.c **** + 295:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + 296:Core/Src/system_stm32h7xx.c **** + 297:Core/Src/system_stm32h7xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + 298:Core/Src/system_stm32h7xx.c **** SYSCLK = PLL_VCO / PLLR + 299:Core/Src/system_stm32h7xx.c **** */ + 300:Core/Src/system_stm32h7xx.c **** pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + 301:Core/Src/system_stm32h7xx.c **** pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + 302:Core/Src/system_stm32h7xx.c **** pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + 303:Core/Src/system_stm32h7xx.c **** fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 304:Core/Src/system_stm32h7xx.c **** + 305:Core/Src/system_stm32h7xx.c **** if (pllm != 0U) + 306:Core/Src/system_stm32h7xx.c **** { + 307:Core/Src/system_stm32h7xx.c **** switch (pllsource) + 308:Core/Src/system_stm32h7xx.c **** { + 309:Core/Src/system_stm32h7xx.c **** case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + 310:Core/Src/system_stm32h7xx.c **** + 311:Core/Src/system_stm32h7xx.c **** hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + 312:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 313:Core/Src/system_stm32h7xx.c **** + 314:Core/Src/system_stm32h7xx.c **** break; + ARM GAS /tmp/ccLsdpLF.s page 10 + + + 315:Core/Src/system_stm32h7xx.c **** + 316:Core/Src/system_stm32h7xx.c **** case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + 317:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 318:Core/Src/system_stm32h7xx.c **** break; + 319:Core/Src/system_stm32h7xx.c **** + 320:Core/Src/system_stm32h7xx.c **** case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + 321:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 322:Core/Src/system_stm32h7xx.c **** break; + 323:Core/Src/system_stm32h7xx.c **** + 324:Core/Src/system_stm32h7xx.c **** default: + 325:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_ + 326:Core/Src/system_stm32h7xx.c **** break; + 327:Core/Src/system_stm32h7xx.c **** } + 328:Core/Src/system_stm32h7xx.c **** pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + 329:Core/Src/system_stm32h7xx.c **** SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + 330:Core/Src/system_stm32h7xx.c **** } + 331:Core/Src/system_stm32h7xx.c **** else + 332:Core/Src/system_stm32h7xx.c **** { + 333:Core/Src/system_stm32h7xx.c **** SystemCoreClock = 0U; + 334:Core/Src/system_stm32h7xx.c **** } + 335:Core/Src/system_stm32h7xx.c **** break; + 336:Core/Src/system_stm32h7xx.c **** + 337:Core/Src/system_stm32h7xx.c **** default: + 338:Core/Src/system_stm32h7xx.c **** SystemCoreClock = CSI_VALUE; + 339:Core/Src/system_stm32h7xx.c **** break; + 340:Core/Src/system_stm32h7xx.c **** } + 341:Core/Src/system_stm32h7xx.c **** + 342:Core/Src/system_stm32h7xx.c **** /* Compute SystemClock frequency --------------------------------------------------*/ + 343:Core/Src/system_stm32h7xx.c **** tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + 203 .loc 1 343 3 view .LVU56 + 204 .loc 1 343 30 is_stmt 0 view .LVU57 + 205 0056 674A ldr r2, .L20 + 206 0058 9369 ldr r3, [r2, #24] + 207 .loc 1 343 59 view .LVU58 + 208 005a C3F30323 ubfx r3, r3, #8, #4 + 209 .loc 1 343 25 view .LVU59 + 210 005e 6849 ldr r1, .L20+12 + 211 0060 11F803C0 ldrb ip, [r1, r3] @ zero_extendqisi2 + 212 .LVL0: + 344:Core/Src/system_stm32h7xx.c **** + 345:Core/Src/system_stm32h7xx.c **** /* SystemCoreClock frequency : CM7 CPU frequency */ + 346:Core/Src/system_stm32h7xx.c **** SystemCoreClock >>= tmp; + 213 .loc 1 346 3 is_stmt 1 view .LVU60 + 214 .loc 1 346 19 is_stmt 0 view .LVU61 + 215 0064 6548 ldr r0, .L20+8 + 216 0066 0368 ldr r3, [r0] + 217 0068 23FA0CF3 lsr r3, r3, ip + 218 006c 0360 str r3, [r0] + 347:Core/Src/system_stm32h7xx.c **** + 348:Core/Src/system_stm32h7xx.c **** /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + 349:Core/Src/system_stm32h7xx.c **** SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CF + 219 .loc 1 349 3 is_stmt 1 view .LVU62 + 220 .loc 1 349 62 is_stmt 0 view .LVU63 + 221 006e 9269 ldr r2, [r2, #24] + 222 .loc 1 349 89 view .LVU64 + 223 0070 02F00F02 and r2, r2, #15 + 224 .loc 1 349 57 view .LVU65 + ARM GAS /tmp/ccLsdpLF.s page 11 + + + 225 0074 8A5C ldrb r2, [r1, r2] @ zero_extendqisi2 + 226 .loc 1 349 114 view .LVU66 + 227 0076 02F01F02 and r2, r2, #31 + 228 .loc 1 349 36 view .LVU67 + 229 007a D340 lsrs r3, r3, r2 + 230 .loc 1 349 17 view .LVU68 + 231 007c 614A ldr r2, .L20+16 + 232 007e 1360 str r3, [r2] + 350:Core/Src/system_stm32h7xx.c **** + 351:Core/Src/system_stm32h7xx.c **** } + 233 .loc 1 351 1 view .LVU69 + 234 0080 5DF8044B ldr r4, [sp], #4 + 235 .LCFI1: + 236 .cfi_remember_state + 237 .cfi_restore 4 + 238 .cfi_def_cfa_offset 0 + 239 0084 7047 bx lr + 240 .LVL1: + 241 .L10: + 242 .LCFI2: + 243 .cfi_restore_state + 288:Core/Src/system_stm32h7xx.c **** break; + 244 .loc 1 288 5 is_stmt 1 view .LVU70 + 288:Core/Src/system_stm32h7xx.c **** break; + 245 .loc 1 288 21 is_stmt 0 view .LVU71 + 246 0086 5D4B ldr r3, .L20+8 + 247 0088 5F4A ldr r2, .L20+20 + 248 008a 1A60 str r2, [r3] + 289:Core/Src/system_stm32h7xx.c **** + 249 .loc 1 289 5 is_stmt 1 view .LVU72 + 250 008c E3E7 b .L12 + 251 .L9: + 292:Core/Src/system_stm32h7xx.c **** break; + 252 .loc 1 292 5 view .LVU73 + 292:Core/Src/system_stm32h7xx.c **** break; + 253 .loc 1 292 21 is_stmt 0 view .LVU74 + 254 008e 5B4B ldr r3, .L20+8 + 255 0090 5E4A ldr r2, .L20+24 + 256 0092 1A60 str r2, [r3] + 293:Core/Src/system_stm32h7xx.c **** + 257 .loc 1 293 5 is_stmt 1 view .LVU75 + 258 0094 DFE7 b .L12 + 259 .L7: + 300:Core/Src/system_stm32h7xx.c **** pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + 260 .loc 1 300 5 view .LVU76 + 300:Core/Src/system_stm32h7xx.c **** pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + 261 .loc 1 300 21 is_stmt 0 view .LVU77 + 262 0096 574A ldr r2, .L20 + 263 0098 916A ldr r1, [r2, #40] + 300:Core/Src/system_stm32h7xx.c **** pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + 264 .loc 1 300 15 view .LVU78 + 265 009a 01F00301 and r1, r1, #3 + 266 .LVL2: + 301:Core/Src/system_stm32h7xx.c **** pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + 267 .loc 1 301 5 is_stmt 1 view .LVU79 + 301:Core/Src/system_stm32h7xx.c **** pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + 268 .loc 1 301 17 is_stmt 0 view .LVU80 + ARM GAS /tmp/ccLsdpLF.s page 12 + + + 269 009e 946A ldr r4, [r2, #40] + 301:Core/Src/system_stm32h7xx.c **** pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + 270 .loc 1 301 10 view .LVU81 + 271 00a0 C4F3051C ubfx ip, r4, #4, #6 + 272 .LVL3: + 302:Core/Src/system_stm32h7xx.c **** fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 273 .loc 1 302 5 is_stmt 1 view .LVU82 + 302:Core/Src/system_stm32h7xx.c **** fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 274 .loc 1 302 22 is_stmt 0 view .LVU83 + 275 00a4 D06A ldr r0, [r2, #44] + 302:Core/Src/system_stm32h7xx.c **** fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + 276 .loc 1 302 15 view .LVU84 + 277 00a6 00F00100 and r0, r0, #1 + 278 .LVL4: + 303:Core/Src/system_stm32h7xx.c **** + 279 .loc 1 303 5 is_stmt 1 view .LVU85 + 303:Core/Src/system_stm32h7xx.c **** + 280 .loc 1 303 50 is_stmt 0 view .LVU86 + 281 00aa 536B ldr r3, [r2, #52] + 303:Core/Src/system_stm32h7xx.c **** + 282 .loc 1 303 85 view .LVU87 + 283 00ac C3F3CC03 ubfx r3, r3, #3, #13 + 303:Core/Src/system_stm32h7xx.c **** + 284 .loc 1 303 23 view .LVU88 + 285 00b0 00FB03F3 mul r3, r0, r3 + 303:Core/Src/system_stm32h7xx.c **** + 286 .loc 1 303 12 view .LVU89 + 287 00b4 07EE903A vmov s15, r3 @ int + 288 00b8 F8EE677A vcvt.f32.u32 s15, s15 + 289 .LVL5: + 305:Core/Src/system_stm32h7xx.c **** { + 290 .loc 1 305 5 is_stmt 1 view .LVU90 + 305:Core/Src/system_stm32h7xx.c **** { + 291 .loc 1 305 8 is_stmt 0 view .LVU91 + 292 00bc 14F47C7F tst r4, #1008 + 293 00c0 00F09080 beq .L13 + 307:Core/Src/system_stm32h7xx.c **** { + 294 .loc 1 307 7 is_stmt 1 view .LVU92 + 295 00c4 0129 cmp r1, #1 + 296 00c6 53D0 beq .L14 + 297 00c8 0229 cmp r1, #2 + 298 00ca 6ED0 beq .L15 + 299 00cc E1B1 cbz r1, .L19 + 325:Core/Src/system_stm32h7xx.c **** break; + 300 .loc 1 325 11 view .LVU93 + 325:Core/Src/system_stm32h7xx.c **** break; + 301 .loc 1 325 42 is_stmt 0 view .LVU94 + 302 00ce 07EE10CA vmov s14, ip @ int + 303 00d2 B8EE477A vcvt.f32.u32 s14, s14 + 325:Core/Src/system_stm32h7xx.c **** break; + 304 .loc 1 325 40 view .LVU95 + 305 00d6 9FED4E6A vldr.32 s12, .L20+28 + 306 00da C6EE076A vdiv.f32 s13, s12, s14 + 325:Core/Src/system_stm32h7xx.c **** break; + 307 .loc 1 325 83 view .LVU96 + 308 00de 454B ldr r3, .L20 + 309 00e0 1B6B ldr r3, [r3, #48] + ARM GAS /tmp/ccLsdpLF.s page 13 + + + 325:Core/Src/system_stm32h7xx.c **** break; + 310 .loc 1 325 69 view .LVU97 + 311 00e2 C3F30803 ubfx r3, r3, #0, #9 + 325:Core/Src/system_stm32h7xx.c **** break; + 312 .loc 1 325 60 view .LVU98 + 313 00e6 07EE103A vmov s14, r3 @ int + 314 00ea B8EE477A vcvt.f32.u32 s14, s14 + 325:Core/Src/system_stm32h7xx.c **** break; + 315 .loc 1 325 122 view .LVU99 + 316 00ee 9FED496A vldr.32 s12, .L20+32 + 317 00f2 67EE867A vmul.f32 s15, s15, s12 + 318 .LVL6: + 325:Core/Src/system_stm32h7xx.c **** break; + 319 .loc 1 325 113 view .LVU100 + 320 00f6 77EE277A vadd.f32 s15, s14, s15 + 325:Core/Src/system_stm32h7xx.c **** break; + 321 .loc 1 325 140 view .LVU101 + 322 00fa B7EE007A vmov.f32 s14, #1.0e+0 + 323 00fe 77EE877A vadd.f32 s15, s15, s14 + 325:Core/Src/system_stm32h7xx.c **** break; + 324 .loc 1 325 18 view .LVU102 + 325 0102 66EEA76A vmul.f32 s13, s13, s15 + 326 .LVL7: + 326:Core/Src/system_stm32h7xx.c **** } + 327 .loc 1 326 9 is_stmt 1 view .LVU103 + 328 0106 22E0 b .L17 + 329 .LVL8: + 330 .L19: + 311:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 331 .loc 1 311 9 view .LVU104 + 311:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 332 .loc 1 311 39 is_stmt 0 view .LVU105 + 333 0108 1146 mov r1, r2 + 334 .LVL9: + 311:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 335 .loc 1 311 39 view .LVU106 + 336 010a 1268 ldr r2, [r2] + 311:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 337 .loc 1 311 60 view .LVU107 + 338 010c C2F3C102 ubfx r2, r2, #3, #2 + 311:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL + 339 .loc 1 311 18 view .LVU108 + 340 0110 394B ldr r3, .L20+4 + 341 0112 D340 lsrs r3, r3, r2 + 342 .LVL10: + 312:Core/Src/system_stm32h7xx.c **** + 343 .loc 1 312 9 is_stmt 1 view .LVU109 + 312:Core/Src/system_stm32h7xx.c **** + 344 .loc 1 312 20 is_stmt 0 view .LVU110 + 345 0114 07EE103A vmov s14, r3 @ int + 346 0118 B8EE476A vcvt.f32.u32 s12, s14 + 312:Core/Src/system_stm32h7xx.c **** + 347 .loc 1 312 40 view .LVU111 + 348 011c 07EE10CA vmov s14, ip @ int + 349 0120 B8EE477A vcvt.f32.u32 s14, s14 + 312:Core/Src/system_stm32h7xx.c **** + 350 .loc 1 312 38 view .LVU112 + ARM GAS /tmp/ccLsdpLF.s page 14 + + + 351 0124 C6EE076A vdiv.f32 s13, s12, s14 + 312:Core/Src/system_stm32h7xx.c **** + 352 .loc 1 312 81 view .LVU113 + 353 0128 0B6B ldr r3, [r1, #48] + 354 .LVL11: + 312:Core/Src/system_stm32h7xx.c **** + 355 .loc 1 312 67 view .LVU114 + 356 012a C3F30803 ubfx r3, r3, #0, #9 + 312:Core/Src/system_stm32h7xx.c **** + 357 .loc 1 312 58 view .LVU115 + 358 012e 07EE103A vmov s14, r3 @ int + 359 0132 B8EE477A vcvt.f32.u32 s14, s14 + 312:Core/Src/system_stm32h7xx.c **** + 360 .loc 1 312 120 view .LVU116 + 361 0136 9FED376A vldr.32 s12, .L20+32 + 362 013a 67EE867A vmul.f32 s15, s15, s12 + 363 .LVL12: + 312:Core/Src/system_stm32h7xx.c **** + 364 .loc 1 312 111 view .LVU117 + 365 013e 77EE277A vadd.f32 s15, s14, s15 + 312:Core/Src/system_stm32h7xx.c **** + 366 .loc 1 312 138 view .LVU118 + 367 0142 B7EE007A vmov.f32 s14, #1.0e+0 + 368 0146 77EE877A vadd.f32 s15, s15, s14 + 312:Core/Src/system_stm32h7xx.c **** + 369 .loc 1 312 16 view .LVU119 + 370 014a 66EEA76A vmul.f32 s13, s13, s15 + 371 .LVL13: + 314:Core/Src/system_stm32h7xx.c **** + 372 .loc 1 314 9 is_stmt 1 view .LVU120 + 373 .L17: + 328:Core/Src/system_stm32h7xx.c **** SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + 374 .loc 1 328 7 view .LVU121 + 328:Core/Src/system_stm32h7xx.c **** SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + 375 .loc 1 328 20 is_stmt 0 view .LVU122 + 376 014e 294B ldr r3, .L20 + 377 0150 1B6B ldr r3, [r3, #48] + 328:Core/Src/system_stm32h7xx.c **** SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + 378 .loc 1 328 50 view .LVU123 + 379 0152 C3F34623 ubfx r3, r3, #9, #7 + 328:Core/Src/system_stm32h7xx.c **** SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + 380 .loc 1 328 12 view .LVU124 + 381 0156 0133 adds r3, r3, #1 + 382 .LVL14: + 329:Core/Src/system_stm32h7xx.c **** } + 383 .loc 1 329 7 is_stmt 1 view .LVU125 + 329:Core/Src/system_stm32h7xx.c **** } + 384 .loc 1 329 53 is_stmt 0 view .LVU126 + 385 0158 07EE903A vmov s15, r3 @ int + 386 015c F8EE677A vcvt.f32.u32 s15, s15 + 329:Core/Src/system_stm32h7xx.c **** } + 387 .loc 1 329 36 view .LVU127 + 388 0160 86EEA77A vdiv.f32 s14, s13, s15 + 329:Core/Src/system_stm32h7xx.c **** } + 389 .loc 1 329 26 view .LVU128 + 390 0164 BCEEC77A vcvt.u32.f32 s14, s14 + 329:Core/Src/system_stm32h7xx.c **** } + ARM GAS /tmp/ccLsdpLF.s page 15 + + + 391 .loc 1 329 23 view .LVU129 + 392 0168 244B ldr r3, .L20+8 + 393 .LVL15: + 329:Core/Src/system_stm32h7xx.c **** } + 394 .loc 1 329 23 view .LVU130 + 395 016a 83ED007A vstr.32 s14, [r3] @ int + 396 016e 72E7 b .L12 + 397 .LVL16: + 398 .L14: + 317:Core/Src/system_stm32h7xx.c **** break; + 399 .loc 1 317 11 is_stmt 1 view .LVU131 + 317:Core/Src/system_stm32h7xx.c **** break; + 400 .loc 1 317 42 is_stmt 0 view .LVU132 + 401 0170 07EE10CA vmov s14, ip @ int + 402 0174 B8EE477A vcvt.f32.u32 s14, s14 + 317:Core/Src/system_stm32h7xx.c **** break; + 403 .loc 1 317 40 view .LVU133 + 404 0178 9FED256A vldr.32 s12, .L20+28 + 405 017c C6EE076A vdiv.f32 s13, s12, s14 + 317:Core/Src/system_stm32h7xx.c **** break; + 406 .loc 1 317 83 view .LVU134 + 407 0180 1C4B ldr r3, .L20 + 408 0182 1B6B ldr r3, [r3, #48] + 317:Core/Src/system_stm32h7xx.c **** break; + 409 .loc 1 317 69 view .LVU135 + 410 0184 C3F30803 ubfx r3, r3, #0, #9 + 317:Core/Src/system_stm32h7xx.c **** break; + 411 .loc 1 317 60 view .LVU136 + 412 0188 07EE103A vmov s14, r3 @ int + 413 018c B8EE477A vcvt.f32.u32 s14, s14 + 317:Core/Src/system_stm32h7xx.c **** break; + 414 .loc 1 317 122 view .LVU137 + 415 0190 9FED206A vldr.32 s12, .L20+32 + 416 0194 67EE867A vmul.f32 s15, s15, s12 + 417 .LVL17: + 317:Core/Src/system_stm32h7xx.c **** break; + 418 .loc 1 317 113 view .LVU138 + 419 0198 77EE277A vadd.f32 s15, s14, s15 + 317:Core/Src/system_stm32h7xx.c **** break; + 420 .loc 1 317 140 view .LVU139 + 421 019c B7EE007A vmov.f32 s14, #1.0e+0 + 422 01a0 77EE877A vadd.f32 s15, s15, s14 + 317:Core/Src/system_stm32h7xx.c **** break; + 423 .loc 1 317 18 view .LVU140 + 424 01a4 66EEA76A vmul.f32 s13, s13, s15 + 425 .LVL18: + 318:Core/Src/system_stm32h7xx.c **** + 426 .loc 1 318 9 is_stmt 1 view .LVU141 + 427 01a8 D1E7 b .L17 + 428 .LVL19: + 429 .L15: + 321:Core/Src/system_stm32h7xx.c **** break; + 430 .loc 1 321 11 view .LVU142 + 321:Core/Src/system_stm32h7xx.c **** break; + 431 .loc 1 321 42 is_stmt 0 view .LVU143 + 432 01aa 07EE10CA vmov s14, ip @ int + 433 01ae B8EE477A vcvt.f32.u32 s14, s14 + ARM GAS /tmp/ccLsdpLF.s page 16 + + + 321:Core/Src/system_stm32h7xx.c **** break; + 434 .loc 1 321 40 view .LVU144 + 435 01b2 9FED196A vldr.32 s12, .L20+36 + 436 01b6 C6EE076A vdiv.f32 s13, s12, s14 + 321:Core/Src/system_stm32h7xx.c **** break; + 437 .loc 1 321 83 view .LVU145 + 438 01ba 0E4B ldr r3, .L20 + 439 01bc 1B6B ldr r3, [r3, #48] + 321:Core/Src/system_stm32h7xx.c **** break; + 440 .loc 1 321 69 view .LVU146 + 441 01be C3F30803 ubfx r3, r3, #0, #9 + 321:Core/Src/system_stm32h7xx.c **** break; + 442 .loc 1 321 60 view .LVU147 + 443 01c2 07EE103A vmov s14, r3 @ int + 444 01c6 B8EE477A vcvt.f32.u32 s14, s14 + 321:Core/Src/system_stm32h7xx.c **** break; + 445 .loc 1 321 122 view .LVU148 + 446 01ca 9FED126A vldr.32 s12, .L20+32 + 447 01ce 67EE867A vmul.f32 s15, s15, s12 + 448 .LVL20: + 321:Core/Src/system_stm32h7xx.c **** break; + 449 .loc 1 321 113 view .LVU149 + 450 01d2 77EE277A vadd.f32 s15, s14, s15 + 321:Core/Src/system_stm32h7xx.c **** break; + 451 .loc 1 321 140 view .LVU150 + 452 01d6 B7EE007A vmov.f32 s14, #1.0e+0 + 453 01da 77EE877A vadd.f32 s15, s15, s14 + 321:Core/Src/system_stm32h7xx.c **** break; + 454 .loc 1 321 18 view .LVU151 + 455 01de 66EEA76A vmul.f32 s13, s13, s15 + 456 .LVL21: + 322:Core/Src/system_stm32h7xx.c **** + 457 .loc 1 322 9 is_stmt 1 view .LVU152 + 458 01e2 B4E7 b .L17 + 459 .LVL22: + 460 .L13: + 333:Core/Src/system_stm32h7xx.c **** } + 461 .loc 1 333 7 view .LVU153 + 333:Core/Src/system_stm32h7xx.c **** } + 462 .loc 1 333 23 is_stmt 0 view .LVU154 + 463 01e4 054B ldr r3, .L20+8 + 464 01e6 0022 movs r2, #0 + 465 01e8 1A60 str r2, [r3] + 466 01ea 34E7 b .L12 + 467 .LVL23: + 468 .L6: + 338:Core/Src/system_stm32h7xx.c **** break; + 469 .loc 1 338 5 is_stmt 1 view .LVU155 + 338:Core/Src/system_stm32h7xx.c **** break; + 470 .loc 1 338 21 is_stmt 0 view .LVU156 + 471 01ec 034B ldr r3, .L20+8 + 472 01ee 064A ldr r2, .L20+20 + 473 01f0 1A60 str r2, [r3] + 339:Core/Src/system_stm32h7xx.c **** } + 474 .loc 1 339 5 is_stmt 1 view .LVU157 + 475 01f2 30E7 b .L12 + 476 .L21: + ARM GAS /tmp/ccLsdpLF.s page 17 + + + 477 .align 2 + 478 .L20: + 479 01f4 00440258 .word 1476543488 + 480 01f8 0090D003 .word 64000000 + 481 01fc 00000000 .word .LANCHOR0 + 482 0200 00000000 .word .LANCHOR1 + 483 0204 00000000 .word .LANCHOR2 + 484 0208 00093D00 .word 4000000 + 485 020c 00127A00 .word 8000000 + 486 0210 0024744A .word 1249125376 + 487 0214 00000039 .word 956301312 + 488 0218 0024F44A .word 1257513984 + 489 .cfi_endproc + 490 .LFE142: + 492 .global D1CorePrescTable + 493 .global SystemD2Clock + 494 .global SystemCoreClock + 495 .section .data.SystemCoreClock,"aw" + 496 .align 2 + 497 .set .LANCHOR0,. + 0 + 500 SystemCoreClock: + 501 0000 0090D003 .word 64000000 + 502 .section .data.SystemD2Clock,"aw" + 503 .align 2 + 504 .set .LANCHOR2,. + 0 + 507 SystemD2Clock: + 508 0000 0090D003 .word 64000000 + 509 .section .rodata.D1CorePrescTable,"a" + 510 .align 2 + 511 .set .LANCHOR1,. + 0 + 514 D1CorePrescTable: + 515 0000 00000000 .ascii "\000\000\000\000\001\002\003\004\001\002\003\004\006" + 515 01020304 + 515 01020304 + 515 06 + 516 000d 070809 .ascii "\007\010\011" + 517 .text + 518 .Letext0: + 519 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 520 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 521 .file 4 "Drivers/CMSIS/Include/core_cm7.h" + 522 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + 523 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 524 .file 7 "/usr/arm-none-eabi/include/math.h" + ARM GAS /tmp/ccLsdpLF.s page 18 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 system_stm32h7xx.c + /tmp/ccLsdpLF.s:17 .text.SystemInit:0000000000000000 $t + /tmp/ccLsdpLF.s:25 .text.SystemInit:0000000000000000 SystemInit + /tmp/ccLsdpLF.s:122 .text.SystemInit:0000000000000064 $d + /tmp/ccLsdpLF.s:132 .text.SystemCoreClockUpdate:0000000000000000 $t + /tmp/ccLsdpLF.s:139 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate + /tmp/ccLsdpLF.s:162 .text.SystemCoreClockUpdate:0000000000000014 $d + /tmp/ccLsdpLF.s:187 .text.SystemCoreClockUpdate:0000000000000046 $t + /tmp/ccLsdpLF.s:479 .text.SystemCoreClockUpdate:00000000000001f4 $d + /tmp/ccLsdpLF.s:514 .rodata.D1CorePrescTable:0000000000000000 D1CorePrescTable + /tmp/ccLsdpLF.s:507 .data.SystemD2Clock:0000000000000000 SystemD2Clock + /tmp/ccLsdpLF.s:500 .data.SystemCoreClock:0000000000000000 SystemCoreClock + /tmp/ccLsdpLF.s:496 .data.SystemCoreClock:0000000000000000 $d + /tmp/ccLsdpLF.s:503 .data.SystemD2Clock:0000000000000000 $d + /tmp/ccLsdpLF.s:510 .rodata.D1CorePrescTable:0000000000000000 $d + +NO UNDEFINED SYMBOLS diff --git a/build/system_stm32h7xx.o b/build/system_stm32h7xx.o new file mode 100644 index 0000000..38ab90f Binary files /dev/null and b/build/system_stm32h7xx.o differ diff --git a/build/usb_device.d b/build/usb_device.d new file mode 100644 index 0000000..d606d26 --- /dev/null +++ b/build/usb_device.d @@ -0,0 +1,97 @@ +build/usb_device.o: USB_DEVICE/App/usb_device.c \ + USB_DEVICE/App/usb_device.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h Core/Inc/pin_config.h \ + Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + USB_DEVICE/App/usbd_desc.h \ + Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + USB_DEVICE/App/usbd_dfu_if.h Core/Inc/pin_config.h +USB_DEVICE/App/usb_device.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +USB_DEVICE/App/usbd_desc.h: +Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +USB_DEVICE/App/usbd_dfu_if.h: +Core/Inc/pin_config.h: diff --git a/build/usb_device.lst b/build/usb_device.lst new file mode 100644 index 0000000..2f83814 --- /dev/null +++ b/build/usb_device.lst @@ -0,0 +1,294 @@ +ARM GAS /tmp/cc4KSNif.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usb_device.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.MX_USB_DEVICE_Init,"ax",%progbits + 17 .align 1 + 18 .global MX_USB_DEVICE_Init + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 MX_USB_DEVICE_Init: + 26 .LFB145: + 27 .file 1 "USB_DEVICE/App/usb_device.c" + 1:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN Header */ + 2:USB_DEVICE/App/usb_device.c **** /** + 3:USB_DEVICE/App/usb_device.c **** ****************************************************************************** + 4:USB_DEVICE/App/usb_device.c **** * @file : usb_device.c + 5:USB_DEVICE/App/usb_device.c **** * @version : v1.0_Cube + 6:USB_DEVICE/App/usb_device.c **** * @brief : This file implements the USB Device + 7:USB_DEVICE/App/usb_device.c **** ****************************************************************************** + 8:USB_DEVICE/App/usb_device.c **** * @attention + 9:USB_DEVICE/App/usb_device.c **** * + 10:USB_DEVICE/App/usb_device.c **** *

© Copyright (c) 2019 STMicroelectronics. + 11:USB_DEVICE/App/usb_device.c **** * All rights reserved.

+ 12:USB_DEVICE/App/usb_device.c **** * + 13:USB_DEVICE/App/usb_device.c **** * This software component is licensed by ST under Ultimate Liberty license + 14:USB_DEVICE/App/usb_device.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 15:USB_DEVICE/App/usb_device.c **** * the License. You may obtain a copy of the License at: + 16:USB_DEVICE/App/usb_device.c **** * www.st.com/SLA0044 + 17:USB_DEVICE/App/usb_device.c **** * + 18:USB_DEVICE/App/usb_device.c **** ****************************************************************************** + 19:USB_DEVICE/App/usb_device.c **** */ + 20:USB_DEVICE/App/usb_device.c **** /* USER CODE END Header */ + 21:USB_DEVICE/App/usb_device.c **** + 22:USB_DEVICE/App/usb_device.c **** /* Includes ------------------------------------------------------------------*/ + 23:USB_DEVICE/App/usb_device.c **** + 24:USB_DEVICE/App/usb_device.c **** #include "usb_device.h" + 25:USB_DEVICE/App/usb_device.c **** #include "usbd_core.h" + 26:USB_DEVICE/App/usb_device.c **** #include "usbd_desc.h" + 27:USB_DEVICE/App/usb_device.c **** #include "usbd_dfu.h" + 28:USB_DEVICE/App/usb_device.c **** #include "usbd_dfu_if.h" + 29:USB_DEVICE/App/usb_device.c **** + 30:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN Includes */ + 31:USB_DEVICE/App/usb_device.c **** + ARM GAS /tmp/cc4KSNif.s page 2 + + + 32:USB_DEVICE/App/usb_device.c **** #include "stm32h7xx_hal.h" + 33:USB_DEVICE/App/usb_device.c **** #include "pin_config.h" + 34:USB_DEVICE/App/usb_device.c **** + 35:USB_DEVICE/App/usb_device.c **** /* USER CODE END Includes */ + 36:USB_DEVICE/App/usb_device.c **** + 37:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN PV */ + 38:USB_DEVICE/App/usb_device.c **** /* Private variables ---------------------------------------------------------*/ + 39:USB_DEVICE/App/usb_device.c **** + 40:USB_DEVICE/App/usb_device.c **** extern uint8_t g_DFU; + 41:USB_DEVICE/App/usb_device.c **** + 42:USB_DEVICE/App/usb_device.c **** /* USER CODE END PV */ + 43:USB_DEVICE/App/usb_device.c **** + 44:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN PFP */ + 45:USB_DEVICE/App/usb_device.c **** /* Private function prototypes -----------------------------------------------*/ + 46:USB_DEVICE/App/usb_device.c **** + 47:USB_DEVICE/App/usb_device.c **** /* USER CODE END PFP */ + 48:USB_DEVICE/App/usb_device.c **** + 49:USB_DEVICE/App/usb_device.c **** /* USB Device Core handle declaration. */ + 50:USB_DEVICE/App/usb_device.c **** USBD_HandleTypeDef hUsbDeviceFS; + 51:USB_DEVICE/App/usb_device.c **** + 52:USB_DEVICE/App/usb_device.c **** /* + 53:USB_DEVICE/App/usb_device.c **** * -- Insert your variables declaration here -- + 54:USB_DEVICE/App/usb_device.c **** */ + 55:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN 0 */ + 56:USB_DEVICE/App/usb_device.c **** + 57:USB_DEVICE/App/usb_device.c **** /* USER CODE END 0 */ + 58:USB_DEVICE/App/usb_device.c **** + 59:USB_DEVICE/App/usb_device.c **** /* + 60:USB_DEVICE/App/usb_device.c **** * -- Insert your external function declaration here -- + 61:USB_DEVICE/App/usb_device.c **** */ + 62:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN 1 */ + 63:USB_DEVICE/App/usb_device.c **** + 64:USB_DEVICE/App/usb_device.c **** /* USER CODE END 1 */ + 65:USB_DEVICE/App/usb_device.c **** + 66:USB_DEVICE/App/usb_device.c **** /** + 67:USB_DEVICE/App/usb_device.c **** * Init USB device Library, add supported class and start the library + 68:USB_DEVICE/App/usb_device.c **** * @retval None + 69:USB_DEVICE/App/usb_device.c **** */ + 70:USB_DEVICE/App/usb_device.c **** void MX_USB_DEVICE_Init(void) + 71:USB_DEVICE/App/usb_device.c **** { + 28 .loc 1 71 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 08B5 push {r3, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 3, -8 + 36 .cfi_offset 14, -4 + 72:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ + 73:USB_DEVICE/App/usb_device.c **** + 74:USB_DEVICE/App/usb_device.c **** if(HAL_GPIO_ReadPin(BTN_PORT, BTN_PIN) == BTN_INACTIVE_STATE && g_DFU == 0) return; + 37 .loc 1 74 3 view .LVU1 + 38 .loc 1 74 6 is_stmt 0 view .LVU2 + 39 0002 0821 movs r1, #8 + 40 0004 1648 ldr r0, .L13 + 41 0006 FFF7FEFF bl HAL_GPIO_ReadPin + ARM GAS /tmp/cc4KSNif.s page 3 + + + 42 .LVL0: + 43 .loc 1 74 5 view .LVU3 + 44 000a 0128 cmp r0, #1 + 45 000c 02D1 bne .L2 + 46 .loc 1 74 73 discriminator 1 view .LVU4 + 47 000e 154B ldr r3, .L13+4 + 48 0010 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 49 .loc 1 74 64 discriminator 1 view .LVU5 + 50 0012 C3B1 cbz r3, .L1 + 51 .L2: + 75:USB_DEVICE/App/usb_device.c **** g_DFU = 1; + 52 .loc 1 75 3 is_stmt 1 view .LVU6 + 53 .loc 1 75 9 is_stmt 0 view .LVU7 + 54 0014 134B ldr r3, .L13+4 + 55 0016 0122 movs r2, #1 + 56 0018 1A70 strb r2, [r3] + 76:USB_DEVICE/App/usb_device.c **** + 77:USB_DEVICE/App/usb_device.c **** /* USER CODE END USB_DEVICE_Init_PreTreatment */ + 78:USB_DEVICE/App/usb_device.c **** + 79:USB_DEVICE/App/usb_device.c **** /* Init Device Library, add supported class and start the library. */ + 80:USB_DEVICE/App/usb_device.c **** if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) + 57 .loc 1 80 3 is_stmt 1 view .LVU8 + 58 .loc 1 80 7 is_stmt 0 view .LVU9 + 59 001a 0022 movs r2, #0 + 60 001c 1249 ldr r1, .L13+8 + 61 001e 1348 ldr r0, .L13+12 + 62 0020 FFF7FEFF bl USBD_Init + 63 .LVL1: + 64 .loc 1 80 6 view .LVU10 + 65 0024 80B9 cbnz r0, .L9 + 66 .L4: + 81:USB_DEVICE/App/usb_device.c **** { + 82:USB_DEVICE/App/usb_device.c **** Error_Handler(); + 83:USB_DEVICE/App/usb_device.c **** } + 84:USB_DEVICE/App/usb_device.c **** if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_DFU) != USBD_OK) + 67 .loc 1 84 3 is_stmt 1 view .LVU11 + 68 .loc 1 84 7 is_stmt 0 view .LVU12 + 69 0026 1249 ldr r1, .L13+16 + 70 0028 1048 ldr r0, .L13+12 + 71 002a FFF7FEFF bl USBD_RegisterClass + 72 .LVL2: + 73 .loc 1 84 6 view .LVU13 + 74 002e 70B9 cbnz r0, .L10 + 75 .L5: + 85:USB_DEVICE/App/usb_device.c **** { + 86:USB_DEVICE/App/usb_device.c **** Error_Handler(); + 87:USB_DEVICE/App/usb_device.c **** } + 88:USB_DEVICE/App/usb_device.c **** if (USBD_DFU_RegisterMedia(&hUsbDeviceFS, &USBD_DFU_fops_FS) != USBD_OK) + 76 .loc 1 88 3 is_stmt 1 view .LVU14 + 77 .loc 1 88 7 is_stmt 0 view .LVU15 + 78 0030 1049 ldr r1, .L13+20 + 79 0032 0E48 ldr r0, .L13+12 + 80 0034 FFF7FEFF bl USBD_DFU_RegisterMedia + 81 .LVL3: + 82 .loc 1 88 6 view .LVU16 + 83 0038 60B9 cbnz r0, .L11 + 84 .L6: + ARM GAS /tmp/cc4KSNif.s page 4 + + + 89:USB_DEVICE/App/usb_device.c **** { + 90:USB_DEVICE/App/usb_device.c **** Error_Handler(); + 91:USB_DEVICE/App/usb_device.c **** } + 92:USB_DEVICE/App/usb_device.c **** if (USBD_Start(&hUsbDeviceFS) != USBD_OK) + 85 .loc 1 92 3 is_stmt 1 view .LVU17 + 86 .loc 1 92 7 is_stmt 0 view .LVU18 + 87 003a 0C48 ldr r0, .L13+12 + 88 003c FFF7FEFF bl USBD_Start + 89 .LVL4: + 90 .loc 1 92 6 view .LVU19 + 91 0040 58B9 cbnz r0, .L12 + 92 .L7: + 93:USB_DEVICE/App/usb_device.c **** { + 94:USB_DEVICE/App/usb_device.c **** Error_Handler(); + 95:USB_DEVICE/App/usb_device.c **** } + 96:USB_DEVICE/App/usb_device.c **** + 97:USB_DEVICE/App/usb_device.c **** /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ + 98:USB_DEVICE/App/usb_device.c **** HAL_PWREx_EnableUSBVoltageDetector(); + 93 .loc 1 98 3 is_stmt 1 view .LVU20 + 94 0042 FFF7FEFF bl HAL_PWREx_EnableUSBVoltageDetector + 95 .LVL5: + 96 .L1: + 99:USB_DEVICE/App/usb_device.c **** + 100:USB_DEVICE/App/usb_device.c **** /* USER CODE END USB_DEVICE_Init_PostTreatment */ + 101:USB_DEVICE/App/usb_device.c **** } + 97 .loc 1 101 1 is_stmt 0 view .LVU21 + 98 0046 08BD pop {r3, pc} + 99 .L9: + 82:USB_DEVICE/App/usb_device.c **** } + 100 .loc 1 82 5 is_stmt 1 view .LVU22 + 101 0048 FFF7FEFF bl Error_Handler + 102 .LVL6: + 103 004c EBE7 b .L4 + 104 .L10: + 86:USB_DEVICE/App/usb_device.c **** } + 105 .loc 1 86 5 view .LVU23 + 106 004e FFF7FEFF bl Error_Handler + 107 .LVL7: + 108 0052 EDE7 b .L5 + 109 .L11: + 90:USB_DEVICE/App/usb_device.c **** } + 110 .loc 1 90 5 view .LVU24 + 111 0054 FFF7FEFF bl Error_Handler + 112 .LVL8: + 113 0058 EFE7 b .L6 + 114 .L12: + 94:USB_DEVICE/App/usb_device.c **** } + 115 .loc 1 94 5 view .LVU25 + 116 005a FFF7FEFF bl Error_Handler + 117 .LVL9: + 118 005e F0E7 b .L7 + 119 .L14: + 120 .align 2 + 121 .L13: + 122 0060 00100258 .word 1476530176 + 123 0064 00000000 .word g_DFU + 124 0068 00000000 .word FS_Desc + ARM GAS /tmp/cc4KSNif.s page 5 + + + 125 006c 00000000 .word .LANCHOR0 + 126 0070 00000000 .word USBD_DFU + 127 0074 00000000 .word USBD_DFU_fops_FS + 128 .cfi_endproc + 129 .LFE145: + 131 .global hUsbDeviceFS + 132 .section .bss.hUsbDeviceFS,"aw",%nobits + 133 .align 2 + 134 .set .LANCHOR0,. + 0 + 137 hUsbDeviceFS: + 138 0000 00000000 .space 720 + 138 00000000 + 138 00000000 + 138 00000000 + 138 00000000 + 139 .text + 140 .Letext0: + 141 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 142 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 143 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 144 .file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 145 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + 146 .file 7 "Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h" + 147 .file 8 "USB_DEVICE/App/usbd_desc.h" + 148 .file 9 "USB_DEVICE/App/usbd_dfu_if.h" + 149 .file 10 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h" + 150 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h" + 151 .file 12 "Core/Inc/main.h" + ARM GAS /tmp/cc4KSNif.s page 6 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usb_device.c + /tmp/cc4KSNif.s:17 .text.MX_USB_DEVICE_Init:0000000000000000 $t + /tmp/cc4KSNif.s:25 .text.MX_USB_DEVICE_Init:0000000000000000 MX_USB_DEVICE_Init + /tmp/cc4KSNif.s:122 .text.MX_USB_DEVICE_Init:0000000000000060 $d + /tmp/cc4KSNif.s:137 .bss.hUsbDeviceFS:0000000000000000 hUsbDeviceFS + /tmp/cc4KSNif.s:133 .bss.hUsbDeviceFS:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_ReadPin +USBD_Init +USBD_RegisterClass +USBD_DFU_RegisterMedia +USBD_Start +HAL_PWREx_EnableUSBVoltageDetector +Error_Handler +g_DFU +FS_Desc +USBD_DFU +USBD_DFU_fops_FS diff --git a/build/usb_device.o b/build/usb_device.o new file mode 100644 index 0000000..9908315 Binary files /dev/null and b/build/usb_device.o differ diff --git a/build/usbd_conf.d b/build/usbd_conf.d new file mode 100644 index 0000000..81f4ca7 --- /dev/null +++ b/build/usbd_conf.d @@ -0,0 +1,86 @@ +build/usbd_conf.o: USB_DEVICE/Target/usbd_conf.c \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h Core/Inc/pin_config.h \ + Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/build/usbd_conf.lst b/build/usbd_conf.lst new file mode 100644 index 0000000..e0e5e1f --- /dev/null +++ b/build/usbd_conf.lst @@ -0,0 +1,2432 @@ +ARM GAS /tmp/ccTqS6pK.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_conf.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.HAL_PCD_MspInit,"ax",%progbits + 17 .align 1 + 18 .global HAL_PCD_MspInit + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 HAL_PCD_MspInit: + 26 .LVL0: + 27 .LFB145: + 28 .file 1 "USB_DEVICE/Target/usbd_conf.c" + 1:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN Header */ + 2:USB_DEVICE/Target/usbd_conf.c **** /** + 3:USB_DEVICE/Target/usbd_conf.c **** ****************************************************************************** + 4:USB_DEVICE/Target/usbd_conf.c **** * @file : Target/usbd_conf.c + 5:USB_DEVICE/Target/usbd_conf.c **** * @version : v1.0_Cube + 6:USB_DEVICE/Target/usbd_conf.c **** * @brief : This file implements the board support package for the USB device library + 7:USB_DEVICE/Target/usbd_conf.c **** ****************************************************************************** + 8:USB_DEVICE/Target/usbd_conf.c **** * @attention + 9:USB_DEVICE/Target/usbd_conf.c **** * + 10:USB_DEVICE/Target/usbd_conf.c **** *

© Copyright (c) 2019 STMicroelectronics. + 11:USB_DEVICE/Target/usbd_conf.c **** * All rights reserved.

+ 12:USB_DEVICE/Target/usbd_conf.c **** * + 13:USB_DEVICE/Target/usbd_conf.c **** * This software component is licensed by ST under Ultimate Liberty license + 14:USB_DEVICE/Target/usbd_conf.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 15:USB_DEVICE/Target/usbd_conf.c **** * the License. You may obtain a copy of the License at: + 16:USB_DEVICE/Target/usbd_conf.c **** * www.st.com/SLA0044 + 17:USB_DEVICE/Target/usbd_conf.c **** * + 18:USB_DEVICE/Target/usbd_conf.c **** ****************************************************************************** + 19:USB_DEVICE/Target/usbd_conf.c **** */ + 20:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END Header */ + 21:USB_DEVICE/Target/usbd_conf.c **** + 22:USB_DEVICE/Target/usbd_conf.c **** /* Includes ------------------------------------------------------------------*/ + 23:USB_DEVICE/Target/usbd_conf.c **** #include "stm32h7xx.h" + 24:USB_DEVICE/Target/usbd_conf.c **** #include "stm32h7xx_hal.h" + 25:USB_DEVICE/Target/usbd_conf.c **** #include "usbd_def.h" + 26:USB_DEVICE/Target/usbd_conf.c **** #include "usbd_core.h" + 27:USB_DEVICE/Target/usbd_conf.c **** + 28:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN Includes */ + 29:USB_DEVICE/Target/usbd_conf.c **** + 30:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END Includes */ + ARM GAS /tmp/ccTqS6pK.s page 2 + + + 31:USB_DEVICE/Target/usbd_conf.c **** + 32:USB_DEVICE/Target/usbd_conf.c **** /* Private typedef -----------------------------------------------------------*/ + 33:USB_DEVICE/Target/usbd_conf.c **** /* Private define ------------------------------------------------------------*/ + 34:USB_DEVICE/Target/usbd_conf.c **** /* Private macro -------------------------------------------------------------*/ + 35:USB_DEVICE/Target/usbd_conf.c **** + 36:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN PV */ + 37:USB_DEVICE/Target/usbd_conf.c **** /* Private variables ---------------------------------------------------------*/ + 38:USB_DEVICE/Target/usbd_conf.c **** + 39:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END PV */ + 40:USB_DEVICE/Target/usbd_conf.c **** + 41:USB_DEVICE/Target/usbd_conf.c **** PCD_HandleTypeDef hpcd_USB_OTG_FS; + 42:USB_DEVICE/Target/usbd_conf.c **** void Error_Handler(void); + 43:USB_DEVICE/Target/usbd_conf.c **** + 44:USB_DEVICE/Target/usbd_conf.c **** /* External functions --------------------------------------------------------*/ + 45:USB_DEVICE/Target/usbd_conf.c **** + 46:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN 0 */ + 47:USB_DEVICE/Target/usbd_conf.c **** + 48:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END 0 */ + 49:USB_DEVICE/Target/usbd_conf.c **** + 50:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN PFP */ + 51:USB_DEVICE/Target/usbd_conf.c **** /* Private function prototypes -----------------------------------------------*/ + 52:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status); + 53:USB_DEVICE/Target/usbd_conf.c **** + 54:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END PFP */ + 55:USB_DEVICE/Target/usbd_conf.c **** + 56:USB_DEVICE/Target/usbd_conf.c **** /* Private functions ---------------------------------------------------------*/ + 57:USB_DEVICE/Target/usbd_conf.c **** + 58:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN 1 */ + 59:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END 1 */ + 60:USB_DEVICE/Target/usbd_conf.c **** + 61:USB_DEVICE/Target/usbd_conf.c **** /******************************************************************************* + 62:USB_DEVICE/Target/usbd_conf.c **** LL Driver Callbacks (PCD -> USB Device Library) + 63:USB_DEVICE/Target/usbd_conf.c **** *******************************************************************************/ + 64:USB_DEVICE/Target/usbd_conf.c **** /* MSP Init */ + 65:USB_DEVICE/Target/usbd_conf.c **** + 66:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) + 67:USB_DEVICE/Target/usbd_conf.c **** { + 29 .loc 1 67 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 32 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 67 1 is_stmt 0 view .LVU1 + 34 0000 30B5 push {r4, r5, lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 12 + 37 .cfi_offset 4, -12 + 38 .cfi_offset 5, -8 + 39 .cfi_offset 14, -4 + 40 0002 89B0 sub sp, sp, #36 + 41 .LCFI1: + 42 .cfi_def_cfa_offset 48 + 68:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 43 .loc 1 68 3 is_stmt 1 view .LVU2 + 44 .loc 1 68 20 is_stmt 0 view .LVU3 + 45 0004 0023 movs r3, #0 + 46 0006 0393 str r3, [sp, #12] + 47 0008 0493 str r3, [sp, #16] + ARM GAS /tmp/ccTqS6pK.s page 3 + + + 48 000a 0593 str r3, [sp, #20] + 49 000c 0693 str r3, [sp, #24] + 50 000e 0793 str r3, [sp, #28] + 69:USB_DEVICE/Target/usbd_conf.c **** if(pcdHandle->Instance==USB_OTG_FS) + 51 .loc 1 69 3 is_stmt 1 view .LVU4 + 52 .loc 1 69 15 is_stmt 0 view .LVU5 + 53 0010 0268 ldr r2, [r0] + 54 .loc 1 69 5 view .LVU6 + 55 0012 214B ldr r3, .L5 + 56 0014 9A42 cmp r2, r3 + 57 0016 01D0 beq .L4 + 58 .LVL1: + 59 .L1: + 70:USB_DEVICE/Target/usbd_conf.c **** { + 71:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + 72:USB_DEVICE/Target/usbd_conf.c **** + 73:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END USB_OTG_FS_MspInit 0 */ + 74:USB_DEVICE/Target/usbd_conf.c **** + 75:USB_DEVICE/Target/usbd_conf.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 76:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 77:USB_DEVICE/Target/usbd_conf.c **** PA11 ------> USB_OTG_FS_DM + 78:USB_DEVICE/Target/usbd_conf.c **** PA12 ------> USB_OTG_FS_DP + 79:USB_DEVICE/Target/usbd_conf.c **** */ + 80:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 81:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 82:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 83:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 84:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; + 85:USB_DEVICE/Target/usbd_conf.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 86:USB_DEVICE/Target/usbd_conf.c **** + 87:USB_DEVICE/Target/usbd_conf.c **** /* Peripheral clock enable */ + 88:USB_DEVICE/Target/usbd_conf.c **** __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + 89:USB_DEVICE/Target/usbd_conf.c **** + 90:USB_DEVICE/Target/usbd_conf.c **** /* Peripheral interrupt init */ + 91:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_SetPriority(OTG_FS_EP1_OUT_IRQn, 1, 0); + 92:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_EnableIRQ(OTG_FS_EP1_OUT_IRQn); + 93:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_SetPriority(OTG_FS_EP1_IN_IRQn, 1, 0); + 94:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_EnableIRQ(OTG_FS_EP1_IN_IRQn); + 95:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_SetPriority(OTG_FS_IRQn, 2, 0); + 96:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + 97:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + 98:USB_DEVICE/Target/usbd_conf.c **** + 99:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END USB_OTG_FS_MspInit 1 */ + 100:USB_DEVICE/Target/usbd_conf.c **** } + 101:USB_DEVICE/Target/usbd_conf.c **** } + 60 .loc 1 101 1 view .LVU7 + 61 0018 09B0 add sp, sp, #36 + 62 .LCFI2: + 63 .cfi_remember_state + 64 .cfi_def_cfa_offset 12 + 65 @ sp needed + 66 001a 30BD pop {r4, r5, pc} + 67 .LVL2: + 68 .L4: + 69 .LCFI3: + 70 .cfi_restore_state + 75:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + ARM GAS /tmp/ccTqS6pK.s page 4 + + + 71 .loc 1 75 5 is_stmt 1 view .LVU8 + 72 .LBB2: + 75:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 73 .loc 1 75 5 view .LVU9 + 75:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 74 .loc 1 75 5 view .LVU10 + 75 001c 1F4C ldr r4, .L5+4 + 76 001e D4F8E030 ldr r3, [r4, #224] + 77 0022 43F00103 orr r3, r3, #1 + 78 0026 C4F8E030 str r3, [r4, #224] + 75:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 79 .loc 1 75 5 view .LVU11 + 80 002a D4F8E030 ldr r3, [r4, #224] + 81 002e 03F00103 and r3, r3, #1 + 82 0032 0193 str r3, [sp, #4] + 75:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 83 .loc 1 75 5 view .LVU12 + 84 0034 019B ldr r3, [sp, #4] + 85 .LBE2: + 75:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 86 .loc 1 75 5 view .LVU13 + 80:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 87 .loc 1 80 5 view .LVU14 + 80:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 88 .loc 1 80 25 is_stmt 0 view .LVU15 + 89 0036 4FF4C053 mov r3, #6144 + 90 003a 0393 str r3, [sp, #12] + 81:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 91 .loc 1 81 5 is_stmt 1 view .LVU16 + 81:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 92 .loc 1 81 26 is_stmt 0 view .LVU17 + 93 003c 0225 movs r5, #2 + 94 003e 0495 str r5, [sp, #16] + 82:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 95 .loc 1 82 5 is_stmt 1 view .LVU18 + 83:USB_DEVICE/Target/usbd_conf.c **** GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; + 96 .loc 1 83 5 view .LVU19 + 84:USB_DEVICE/Target/usbd_conf.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 97 .loc 1 84 5 view .LVU20 + 84:USB_DEVICE/Target/usbd_conf.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 98 .loc 1 84 31 is_stmt 0 view .LVU21 + 99 0040 0A23 movs r3, #10 + 100 0042 0793 str r3, [sp, #28] + 85:USB_DEVICE/Target/usbd_conf.c **** + 101 .loc 1 85 5 is_stmt 1 view .LVU22 + 102 0044 03A9 add r1, sp, #12 + 103 0046 1648 ldr r0, .L5+8 + 104 .LVL3: + 85:USB_DEVICE/Target/usbd_conf.c **** + 105 .loc 1 85 5 is_stmt 0 view .LVU23 + 106 0048 FFF7FEFF bl HAL_GPIO_Init + 107 .LVL4: + 88:USB_DEVICE/Target/usbd_conf.c **** + 108 .loc 1 88 5 is_stmt 1 view .LVU24 + 109 .LBB3: + 88:USB_DEVICE/Target/usbd_conf.c **** + 110 .loc 1 88 5 view .LVU25 + ARM GAS /tmp/ccTqS6pK.s page 5 + + + 88:USB_DEVICE/Target/usbd_conf.c **** + 111 .loc 1 88 5 view .LVU26 + 112 004c D4F8D830 ldr r3, [r4, #216] + 113 0050 43F00063 orr r3, r3, #134217728 + 114 0054 C4F8D830 str r3, [r4, #216] + 88:USB_DEVICE/Target/usbd_conf.c **** + 115 .loc 1 88 5 view .LVU27 + 116 0058 D4F8D830 ldr r3, [r4, #216] + 117 005c 03F00063 and r3, r3, #134217728 + 118 0060 0293 str r3, [sp, #8] + 88:USB_DEVICE/Target/usbd_conf.c **** + 119 .loc 1 88 5 view .LVU28 + 120 0062 029B ldr r3, [sp, #8] + 121 .LBE3: + 88:USB_DEVICE/Target/usbd_conf.c **** + 122 .loc 1 88 5 view .LVU29 + 91:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_EnableIRQ(OTG_FS_EP1_OUT_IRQn); + 123 .loc 1 91 5 view .LVU30 + 124 0064 0022 movs r2, #0 + 125 0066 0121 movs r1, #1 + 126 0068 6220 movs r0, #98 + 127 006a FFF7FEFF bl HAL_NVIC_SetPriority + 128 .LVL5: + 92:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_SetPriority(OTG_FS_EP1_IN_IRQn, 1, 0); + 129 .loc 1 92 5 view .LVU31 + 130 006e 6220 movs r0, #98 + 131 0070 FFF7FEFF bl HAL_NVIC_EnableIRQ + 132 .LVL6: + 93:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_EnableIRQ(OTG_FS_EP1_IN_IRQn); + 133 .loc 1 93 5 view .LVU32 + 134 0074 0022 movs r2, #0 + 135 0076 0121 movs r1, #1 + 136 0078 6320 movs r0, #99 + 137 007a FFF7FEFF bl HAL_NVIC_SetPriority + 138 .LVL7: + 94:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_SetPriority(OTG_FS_IRQn, 2, 0); + 139 .loc 1 94 5 view .LVU33 + 140 007e 6320 movs r0, #99 + 141 0080 FFF7FEFF bl HAL_NVIC_EnableIRQ + 142 .LVL8: + 95:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + 143 .loc 1 95 5 view .LVU34 + 144 0084 0022 movs r2, #0 + 145 0086 2946 mov r1, r5 + 146 0088 6520 movs r0, #101 + 147 008a FFF7FEFF bl HAL_NVIC_SetPriority + 148 .LVL9: + 96:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + 149 .loc 1 96 5 view .LVU35 + 150 008e 6520 movs r0, #101 + 151 0090 FFF7FEFF bl HAL_NVIC_EnableIRQ + 152 .LVL10: + 153 .loc 1 101 1 is_stmt 0 view .LVU36 + 154 0094 C0E7 b .L1 + 155 .L6: + 156 0096 00BF .align 2 + 157 .L5: + ARM GAS /tmp/ccTqS6pK.s page 6 + + + 158 0098 00000840 .word 1074266112 + 159 009c 00440258 .word 1476543488 + 160 00a0 00000258 .word 1476526080 + 161 .cfi_endproc + 162 .LFE145: + 164 .section .text.HAL_PCD_MspDeInit,"ax",%progbits + 165 .align 1 + 166 .global HAL_PCD_MspDeInit + 167 .syntax unified + 168 .thumb + 169 .thumb_func + 170 .fpu fpv5-d16 + 172 HAL_PCD_MspDeInit: + 173 .LVL11: + 174 .LFB146: + 102:USB_DEVICE/Target/usbd_conf.c **** + 103:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) + 104:USB_DEVICE/Target/usbd_conf.c **** { + 175 .loc 1 104 1 is_stmt 1 view -0 + 176 .cfi_startproc + 177 @ args = 0, pretend = 0, frame = 0 + 178 @ frame_needed = 0, uses_anonymous_args = 0 + 179 .loc 1 104 1 is_stmt 0 view .LVU38 + 180 0000 08B5 push {r3, lr} + 181 .LCFI4: + 182 .cfi_def_cfa_offset 8 + 183 .cfi_offset 3, -8 + 184 .cfi_offset 14, -4 + 105:USB_DEVICE/Target/usbd_conf.c **** if(pcdHandle->Instance==USB_OTG_FS) + 185 .loc 1 105 3 is_stmt 1 view .LVU39 + 186 .loc 1 105 15 is_stmt 0 view .LVU40 + 187 0002 0268 ldr r2, [r0] + 188 .loc 1 105 5 view .LVU41 + 189 0004 0C4B ldr r3, .L11 + 190 0006 9A42 cmp r2, r3 + 191 0008 00D0 beq .L10 + 192 .LVL12: + 193 .L7: + 106:USB_DEVICE/Target/usbd_conf.c **** { + 107:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + 108:USB_DEVICE/Target/usbd_conf.c **** + 109:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + 110:USB_DEVICE/Target/usbd_conf.c **** /* Peripheral clock disable */ + 111:USB_DEVICE/Target/usbd_conf.c **** __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + 112:USB_DEVICE/Target/usbd_conf.c **** + 113:USB_DEVICE/Target/usbd_conf.c **** /**USB_OTG_FS GPIO Configuration + 114:USB_DEVICE/Target/usbd_conf.c **** PA11 ------> USB_OTG_FS_DM + 115:USB_DEVICE/Target/usbd_conf.c **** PA12 ------> USB_OTG_FS_DP + 116:USB_DEVICE/Target/usbd_conf.c **** */ + 117:USB_DEVICE/Target/usbd_conf.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + 118:USB_DEVICE/Target/usbd_conf.c **** + 119:USB_DEVICE/Target/usbd_conf.c **** /* Peripheral interrupt Deinit*/ + 120:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_DisableIRQ(OTG_FS_EP1_OUT_IRQn); + 121:USB_DEVICE/Target/usbd_conf.c **** + 122:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_DisableIRQ(OTG_FS_EP1_IN_IRQn); + 123:USB_DEVICE/Target/usbd_conf.c **** + 124:USB_DEVICE/Target/usbd_conf.c **** HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + ARM GAS /tmp/ccTqS6pK.s page 7 + + + 125:USB_DEVICE/Target/usbd_conf.c **** + 126:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + 127:USB_DEVICE/Target/usbd_conf.c **** + 128:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + 129:USB_DEVICE/Target/usbd_conf.c **** } + 130:USB_DEVICE/Target/usbd_conf.c **** } + 194 .loc 1 130 1 view .LVU42 + 195 000a 08BD pop {r3, pc} + 196 .LVL13: + 197 .L10: + 111:USB_DEVICE/Target/usbd_conf.c **** + 198 .loc 1 111 5 is_stmt 1 view .LVU43 + 199 000c 0B4A ldr r2, .L11+4 + 200 000e D2F8D830 ldr r3, [r2, #216] + 201 0012 23F00063 bic r3, r3, #134217728 + 202 0016 C2F8D830 str r3, [r2, #216] + 117:USB_DEVICE/Target/usbd_conf.c **** + 203 .loc 1 117 5 view .LVU44 + 204 001a 4FF4C051 mov r1, #6144 + 205 001e 0848 ldr r0, .L11+8 + 206 .LVL14: + 117:USB_DEVICE/Target/usbd_conf.c **** + 207 .loc 1 117 5 is_stmt 0 view .LVU45 + 208 0020 FFF7FEFF bl HAL_GPIO_DeInit + 209 .LVL15: + 120:USB_DEVICE/Target/usbd_conf.c **** + 210 .loc 1 120 5 is_stmt 1 view .LVU46 + 211 0024 6220 movs r0, #98 + 212 0026 FFF7FEFF bl HAL_NVIC_DisableIRQ + 213 .LVL16: + 122:USB_DEVICE/Target/usbd_conf.c **** + 214 .loc 1 122 5 view .LVU47 + 215 002a 6320 movs r0, #99 + 216 002c FFF7FEFF bl HAL_NVIC_DisableIRQ + 217 .LVL17: + 124:USB_DEVICE/Target/usbd_conf.c **** + 218 .loc 1 124 5 view .LVU48 + 219 0030 6520 movs r0, #101 + 220 0032 FFF7FEFF bl HAL_NVIC_DisableIRQ + 221 .LVL18: + 222 .loc 1 130 1 is_stmt 0 view .LVU49 + 223 0036 E8E7 b .L7 + 224 .L12: + 225 .align 2 + 226 .L11: + 227 0038 00000840 .word 1074266112 + 228 003c 00440258 .word 1476543488 + 229 0040 00000258 .word 1476526080 + 230 .cfi_endproc + 231 .LFE146: + 233 .section .text.HAL_PCD_SetupStageCallback,"ax",%progbits + 234 .align 1 + 235 .global HAL_PCD_SetupStageCallback + 236 .syntax unified + 237 .thumb + 238 .thumb_func + 239 .fpu fpv5-d16 + ARM GAS /tmp/ccTqS6pK.s page 8 + + + 241 HAL_PCD_SetupStageCallback: + 242 .LVL19: + 243 .LFB147: + 131:USB_DEVICE/Target/usbd_conf.c **** + 132:USB_DEVICE/Target/usbd_conf.c **** /** + 133:USB_DEVICE/Target/usbd_conf.c **** * @brief Setup stage callback + 134:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 135:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 136:USB_DEVICE/Target/usbd_conf.c **** */ + 137:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 138:USB_DEVICE/Target/usbd_conf.c **** static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) + 139:USB_DEVICE/Target/usbd_conf.c **** #else + 140:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) + 141:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 142:USB_DEVICE/Target/usbd_conf.c **** { + 244 .loc 1 142 1 is_stmt 1 view -0 + 245 .cfi_startproc + 246 @ args = 0, pretend = 0, frame = 0 + 247 @ frame_needed = 0, uses_anonymous_args = 0 + 248 .loc 1 142 1 is_stmt 0 view .LVU51 + 249 0000 08B5 push {r3, lr} + 250 .LCFI5: + 251 .cfi_def_cfa_offset 8 + 252 .cfi_offset 3, -8 + 253 .cfi_offset 14, -4 + 143:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); + 254 .loc 1 143 3 is_stmt 1 view .LVU52 + 255 0002 00F57171 add r1, r0, #964 + 256 0006 D0F80404 ldr r0, [r0, #1028] + 257 .LVL20: + 258 .loc 1 143 3 is_stmt 0 view .LVU53 + 259 000a FFF7FEFF bl USBD_LL_SetupStage + 260 .LVL21: + 144:USB_DEVICE/Target/usbd_conf.c **** } + 261 .loc 1 144 1 view .LVU54 + 262 000e 08BD pop {r3, pc} + 263 .cfi_endproc + 264 .LFE147: + 266 .section .text.HAL_PCD_DataOutStageCallback,"ax",%progbits + 267 .align 1 + 268 .global HAL_PCD_DataOutStageCallback + 269 .syntax unified + 270 .thumb + 271 .thumb_func + 272 .fpu fpv5-d16 + 274 HAL_PCD_DataOutStageCallback: + 275 .LVL22: + 276 .LFB148: + 145:USB_DEVICE/Target/usbd_conf.c **** + 146:USB_DEVICE/Target/usbd_conf.c **** /** + 147:USB_DEVICE/Target/usbd_conf.c **** * @brief Data Out stage callback. + 148:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 149:USB_DEVICE/Target/usbd_conf.c **** * @param epnum: Endpoint number + 150:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 151:USB_DEVICE/Target/usbd_conf.c **** */ + 152:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 153:USB_DEVICE/Target/usbd_conf.c **** static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + ARM GAS /tmp/ccTqS6pK.s page 9 + + + 154:USB_DEVICE/Target/usbd_conf.c **** #else + 155:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 156:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 157:USB_DEVICE/Target/usbd_conf.c **** { + 277 .loc 1 157 1 is_stmt 1 view -0 + 278 .cfi_startproc + 279 @ args = 0, pretend = 0, frame = 0 + 280 @ frame_needed = 0, uses_anonymous_args = 0 + 281 .loc 1 157 1 is_stmt 0 view .LVU56 + 282 0000 08B5 push {r3, lr} + 283 .LCFI6: + 284 .cfi_def_cfa_offset 8 + 285 .cfi_offset 3, -8 + 286 .cfi_offset 14, -4 + 158:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); + 287 .loc 1 158 3 is_stmt 1 view .LVU57 + 288 0002 C1EBC103 rsb r3, r1, r1, lsl #3 + 289 0006 00EB8303 add r3, r0, r3, lsl #2 + 290 000a D3F80822 ldr r2, [r3, #520] + 291 000e D0F80404 ldr r0, [r0, #1028] + 292 .LVL23: + 293 .loc 1 158 3 is_stmt 0 view .LVU58 + 294 0012 FFF7FEFF bl USBD_LL_DataOutStage + 295 .LVL24: + 159:USB_DEVICE/Target/usbd_conf.c **** } + 296 .loc 1 159 1 view .LVU59 + 297 0016 08BD pop {r3, pc} + 298 .cfi_endproc + 299 .LFE148: + 301 .section .text.HAL_PCD_DataInStageCallback,"ax",%progbits + 302 .align 1 + 303 .global HAL_PCD_DataInStageCallback + 304 .syntax unified + 305 .thumb + 306 .thumb_func + 307 .fpu fpv5-d16 + 309 HAL_PCD_DataInStageCallback: + 310 .LVL25: + 311 .LFB149: + 160:USB_DEVICE/Target/usbd_conf.c **** + 161:USB_DEVICE/Target/usbd_conf.c **** /** + 162:USB_DEVICE/Target/usbd_conf.c **** * @brief Data In stage callback. + 163:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 164:USB_DEVICE/Target/usbd_conf.c **** * @param epnum: Endpoint number + 165:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 166:USB_DEVICE/Target/usbd_conf.c **** */ + 167:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 168:USB_DEVICE/Target/usbd_conf.c **** static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 169:USB_DEVICE/Target/usbd_conf.c **** #else + 170:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 171:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 172:USB_DEVICE/Target/usbd_conf.c **** { + 312 .loc 1 172 1 is_stmt 1 view -0 + 313 .cfi_startproc + 314 @ args = 0, pretend = 0, frame = 0 + 315 @ frame_needed = 0, uses_anonymous_args = 0 + 316 .loc 1 172 1 is_stmt 0 view .LVU61 + ARM GAS /tmp/ccTqS6pK.s page 10 + + + 317 0000 08B5 push {r3, lr} + 318 .LCFI7: + 319 .cfi_def_cfa_offset 8 + 320 .cfi_offset 3, -8 + 321 .cfi_offset 14, -4 + 173:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); + 322 .loc 1 173 3 is_stmt 1 view .LVU62 + 323 0002 C1EBC103 rsb r3, r1, r1, lsl #3 + 324 0006 00EB8303 add r3, r0, r3, lsl #2 + 325 000a 9A6C ldr r2, [r3, #72] + 326 000c D0F80404 ldr r0, [r0, #1028] + 327 .LVL26: + 328 .loc 1 173 3 is_stmt 0 view .LVU63 + 329 0010 FFF7FEFF bl USBD_LL_DataInStage + 330 .LVL27: + 174:USB_DEVICE/Target/usbd_conf.c **** } + 331 .loc 1 174 1 view .LVU64 + 332 0014 08BD pop {r3, pc} + 333 .cfi_endproc + 334 .LFE149: + 336 .section .text.HAL_PCD_SOFCallback,"ax",%progbits + 337 .align 1 + 338 .global HAL_PCD_SOFCallback + 339 .syntax unified + 340 .thumb + 341 .thumb_func + 342 .fpu fpv5-d16 + 344 HAL_PCD_SOFCallback: + 345 .LVL28: + 346 .LFB150: + 175:USB_DEVICE/Target/usbd_conf.c **** + 176:USB_DEVICE/Target/usbd_conf.c **** /** + 177:USB_DEVICE/Target/usbd_conf.c **** * @brief SOF callback. + 178:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 179:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 180:USB_DEVICE/Target/usbd_conf.c **** */ + 181:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 182:USB_DEVICE/Target/usbd_conf.c **** static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd) + 183:USB_DEVICE/Target/usbd_conf.c **** #else + 184:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) + 185:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 186:USB_DEVICE/Target/usbd_conf.c **** { + 347 .loc 1 186 1 is_stmt 1 view -0 + 348 .cfi_startproc + 349 @ args = 0, pretend = 0, frame = 0 + 350 @ frame_needed = 0, uses_anonymous_args = 0 + 351 .loc 1 186 1 is_stmt 0 view .LVU66 + 352 0000 08B5 push {r3, lr} + 353 .LCFI8: + 354 .cfi_def_cfa_offset 8 + 355 .cfi_offset 3, -8 + 356 .cfi_offset 14, -4 + 187:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); + 357 .loc 1 187 3 is_stmt 1 view .LVU67 + 358 0002 D0F80404 ldr r0, [r0, #1028] + 359 .LVL29: + 360 .loc 1 187 3 is_stmt 0 view .LVU68 + ARM GAS /tmp/ccTqS6pK.s page 11 + + + 361 0006 FFF7FEFF bl USBD_LL_SOF + 362 .LVL30: + 188:USB_DEVICE/Target/usbd_conf.c **** } + 363 .loc 1 188 1 view .LVU69 + 364 000a 08BD pop {r3, pc} + 365 .cfi_endproc + 366 .LFE150: + 368 .section .text.HAL_PCD_ResetCallback,"ax",%progbits + 369 .align 1 + 370 .global HAL_PCD_ResetCallback + 371 .syntax unified + 372 .thumb + 373 .thumb_func + 374 .fpu fpv5-d16 + 376 HAL_PCD_ResetCallback: + 377 .LVL31: + 378 .LFB151: + 189:USB_DEVICE/Target/usbd_conf.c **** + 190:USB_DEVICE/Target/usbd_conf.c **** /** + 191:USB_DEVICE/Target/usbd_conf.c **** * @brief Reset callback. + 192:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 193:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 194:USB_DEVICE/Target/usbd_conf.c **** */ + 195:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 196:USB_DEVICE/Target/usbd_conf.c **** static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd) + 197:USB_DEVICE/Target/usbd_conf.c **** #else + 198:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) + 199:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 200:USB_DEVICE/Target/usbd_conf.c **** { + 379 .loc 1 200 1 is_stmt 1 view -0 + 380 .cfi_startproc + 381 @ args = 0, pretend = 0, frame = 0 + 382 @ frame_needed = 0, uses_anonymous_args = 0 + 383 .loc 1 200 1 is_stmt 0 view .LVU71 + 384 0000 10B5 push {r4, lr} + 385 .LCFI9: + 386 .cfi_def_cfa_offset 8 + 387 .cfi_offset 4, -8 + 388 .cfi_offset 14, -4 + 389 0002 0446 mov r4, r0 + 201:USB_DEVICE/Target/usbd_conf.c **** USBD_SpeedTypeDef speed = USBD_SPEED_FULL; + 390 .loc 1 201 3 is_stmt 1 view .LVU72 + 391 .LVL32: + 202:USB_DEVICE/Target/usbd_conf.c **** + 203:USB_DEVICE/Target/usbd_conf.c **** if ( hpcd->Init.speed == PCD_SPEED_HIGH) + 392 .loc 1 203 3 view .LVU73 + 393 .loc 1 203 18 is_stmt 0 view .LVU74 + 394 0004 C368 ldr r3, [r0, #12] + 395 .loc 1 203 6 view .LVU75 + 396 0006 3BB1 cbz r3, .L23 + 204:USB_DEVICE/Target/usbd_conf.c **** { + 205:USB_DEVICE/Target/usbd_conf.c **** speed = USBD_SPEED_HIGH; + 206:USB_DEVICE/Target/usbd_conf.c **** } + 207:USB_DEVICE/Target/usbd_conf.c **** else if ( hpcd->Init.speed == PCD_SPEED_FULL) + 397 .loc 1 207 8 is_stmt 1 view .LVU76 + 398 .loc 1 207 11 is_stmt 0 view .LVU77 + 399 0008 022B cmp r3, #2 + ARM GAS /tmp/ccTqS6pK.s page 12 + + + 400 000a 01D1 bne .L26 + 208:USB_DEVICE/Target/usbd_conf.c **** { + 209:USB_DEVICE/Target/usbd_conf.c **** speed = USBD_SPEED_FULL; + 401 .loc 1 209 11 view .LVU78 + 402 000c 0121 movs r1, #1 + 403 000e 04E0 b .L22 + 404 .L26: + 210:USB_DEVICE/Target/usbd_conf.c **** } + 211:USB_DEVICE/Target/usbd_conf.c **** else + 212:USB_DEVICE/Target/usbd_conf.c **** { + 213:USB_DEVICE/Target/usbd_conf.c **** Error_Handler(); + 405 .loc 1 213 5 is_stmt 1 view .LVU79 + 406 0010 FFF7FEFF bl Error_Handler + 407 .LVL33: + 201:USB_DEVICE/Target/usbd_conf.c **** + 408 .loc 1 201 21 is_stmt 0 view .LVU80 + 409 0014 0121 movs r1, #1 + 410 0016 00E0 b .L22 + 411 .LVL34: + 412 .L23: + 205:USB_DEVICE/Target/usbd_conf.c **** } + 413 .loc 1 205 11 view .LVU81 + 414 0018 0021 movs r1, #0 + 415 .LVL35: + 416 .L22: + 214:USB_DEVICE/Target/usbd_conf.c **** } + 215:USB_DEVICE/Target/usbd_conf.c **** /* Set Speed. */ + 216:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + 417 .loc 1 216 3 is_stmt 1 view .LVU82 + 418 001a D4F80404 ldr r0, [r4, #1028] + 419 001e FFF7FEFF bl USBD_LL_SetSpeed + 420 .LVL36: + 217:USB_DEVICE/Target/usbd_conf.c **** + 218:USB_DEVICE/Target/usbd_conf.c **** /* Reset Device. */ + 219:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); + 421 .loc 1 219 3 view .LVU83 + 422 0022 D4F80404 ldr r0, [r4, #1028] + 423 0026 FFF7FEFF bl USBD_LL_Reset + 424 .LVL37: + 220:USB_DEVICE/Target/usbd_conf.c **** } + 425 .loc 1 220 1 is_stmt 0 view .LVU84 + 426 002a 10BD pop {r4, pc} + 427 .loc 1 220 1 view .LVU85 + 428 .cfi_endproc + 429 .LFE151: + 431 .section .text.HAL_PCD_SuspendCallback,"ax",%progbits + 432 .align 1 + 433 .global HAL_PCD_SuspendCallback + 434 .syntax unified + 435 .thumb + 436 .thumb_func + 437 .fpu fpv5-d16 + 439 HAL_PCD_SuspendCallback: + 440 .LVL38: + 441 .LFB152: + 221:USB_DEVICE/Target/usbd_conf.c **** + 222:USB_DEVICE/Target/usbd_conf.c **** /** + ARM GAS /tmp/ccTqS6pK.s page 13 + + + 223:USB_DEVICE/Target/usbd_conf.c **** * @brief Suspend callback. + 224:USB_DEVICE/Target/usbd_conf.c **** * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + 225:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 226:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 227:USB_DEVICE/Target/usbd_conf.c **** */ + 228:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 229:USB_DEVICE/Target/usbd_conf.c **** static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) + 230:USB_DEVICE/Target/usbd_conf.c **** #else + 231:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) + 232:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 233:USB_DEVICE/Target/usbd_conf.c **** { + 442 .loc 1 233 1 is_stmt 1 view -0 + 443 .cfi_startproc + 444 @ args = 0, pretend = 0, frame = 0 + 445 @ frame_needed = 0, uses_anonymous_args = 0 + 446 .loc 1 233 1 is_stmt 0 view .LVU87 + 447 0000 10B5 push {r4, lr} + 448 .LCFI10: + 449 .cfi_def_cfa_offset 8 + 450 .cfi_offset 4, -8 + 451 .cfi_offset 14, -4 + 452 0002 0446 mov r4, r0 + 234:USB_DEVICE/Target/usbd_conf.c **** /* Inform USB library that core enters in suspend Mode. */ + 235:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); + 453 .loc 1 235 3 is_stmt 1 view .LVU88 + 454 0004 D0F80404 ldr r0, [r0, #1028] + 455 .LVL39: + 456 .loc 1 235 3 is_stmt 0 view .LVU89 + 457 0008 FFF7FEFF bl USBD_LL_Suspend + 458 .LVL40: + 236:USB_DEVICE/Target/usbd_conf.c **** __HAL_PCD_GATE_PHYCLOCK(hpcd); + 459 .loc 1 236 3 is_stmt 1 view .LVU90 + 460 000c 2268 ldr r2, [r4] + 461 000e D2F8003E ldr r3, [r2, #3584] + 462 0012 43F00103 orr r3, r3, #1 + 463 0016 C2F8003E str r3, [r2, #3584] + 237:USB_DEVICE/Target/usbd_conf.c **** /* Enter in STOP mode. */ + 238:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN 2 */ + 239:USB_DEVICE/Target/usbd_conf.c **** if (hpcd->Init.low_power_enable) + 464 .loc 1 239 3 view .LVU91 + 465 .loc 1 239 17 is_stmt 0 view .LVU92 + 466 001a 236A ldr r3, [r4, #32] + 467 .loc 1 239 6 view .LVU93 + 468 001c 23B1 cbz r3, .L27 + 240:USB_DEVICE/Target/usbd_conf.c **** { + 241:USB_DEVICE/Target/usbd_conf.c **** /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ + 242:USB_DEVICE/Target/usbd_conf.c **** SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); + 469 .loc 1 242 5 is_stmt 1 view .LVU94 + 470 .loc 1 242 14 is_stmt 0 view .LVU95 + 471 001e 034A ldr r2, .L30 + 472 0020 1369 ldr r3, [r2, #16] + 473 0022 43F00603 orr r3, r3, #6 + 474 0026 1361 str r3, [r2, #16] + 475 .L27: + 243:USB_DEVICE/Target/usbd_conf.c **** } + 244:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END 2 */ + 245:USB_DEVICE/Target/usbd_conf.c **** } + ARM GAS /tmp/ccTqS6pK.s page 14 + + + 476 .loc 1 245 1 view .LVU96 + 477 0028 10BD pop {r4, pc} + 478 .LVL41: + 479 .L31: + 480 .loc 1 245 1 view .LVU97 + 481 002a 00BF .align 2 + 482 .L30: + 483 002c 00ED00E0 .word -536810240 + 484 .cfi_endproc + 485 .LFE152: + 487 .section .text.HAL_PCD_ResumeCallback,"ax",%progbits + 488 .align 1 + 489 .global HAL_PCD_ResumeCallback + 490 .syntax unified + 491 .thumb + 492 .thumb_func + 493 .fpu fpv5-d16 + 495 HAL_PCD_ResumeCallback: + 496 .LVL42: + 497 .LFB153: + 246:USB_DEVICE/Target/usbd_conf.c **** + 247:USB_DEVICE/Target/usbd_conf.c **** /** + 248:USB_DEVICE/Target/usbd_conf.c **** * @brief Resume callback. + 249:USB_DEVICE/Target/usbd_conf.c **** * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + 250:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 251:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 252:USB_DEVICE/Target/usbd_conf.c **** */ + 253:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 254:USB_DEVICE/Target/usbd_conf.c **** static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) + 255:USB_DEVICE/Target/usbd_conf.c **** #else + 256:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) + 257:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 258:USB_DEVICE/Target/usbd_conf.c **** { + 498 .loc 1 258 1 is_stmt 1 view -0 + 499 .cfi_startproc + 500 @ args = 0, pretend = 0, frame = 0 + 501 @ frame_needed = 0, uses_anonymous_args = 0 + 502 .loc 1 258 1 is_stmt 0 view .LVU99 + 503 0000 08B5 push {r3, lr} + 504 .LCFI11: + 505 .cfi_def_cfa_offset 8 + 506 .cfi_offset 3, -8 + 507 .cfi_offset 14, -4 + 259:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE BEGIN 3 */ + 260:USB_DEVICE/Target/usbd_conf.c **** + 261:USB_DEVICE/Target/usbd_conf.c **** /* USER CODE END 3 */ + 262:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); + 508 .loc 1 262 3 is_stmt 1 view .LVU100 + 509 0002 D0F80404 ldr r0, [r0, #1028] + 510 .LVL43: + 511 .loc 1 262 3 is_stmt 0 view .LVU101 + 512 0006 FFF7FEFF bl USBD_LL_Resume + 513 .LVL44: + 263:USB_DEVICE/Target/usbd_conf.c **** } + 514 .loc 1 263 1 view .LVU102 + 515 000a 08BD pop {r3, pc} + 516 .cfi_endproc + ARM GAS /tmp/ccTqS6pK.s page 15 + + + 517 .LFE153: + 519 .section .text.HAL_PCD_ISOOUTIncompleteCallback,"ax",%progbits + 520 .align 1 + 521 .global HAL_PCD_ISOOUTIncompleteCallback + 522 .syntax unified + 523 .thumb + 524 .thumb_func + 525 .fpu fpv5-d16 + 527 HAL_PCD_ISOOUTIncompleteCallback: + 528 .LVL45: + 529 .LFB154: + 264:USB_DEVICE/Target/usbd_conf.c **** + 265:USB_DEVICE/Target/usbd_conf.c **** /** + 266:USB_DEVICE/Target/usbd_conf.c **** * @brief ISOOUTIncomplete callback. + 267:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 268:USB_DEVICE/Target/usbd_conf.c **** * @param epnum: Endpoint number + 269:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 270:USB_DEVICE/Target/usbd_conf.c **** */ + 271:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 272:USB_DEVICE/Target/usbd_conf.c **** static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 273:USB_DEVICE/Target/usbd_conf.c **** #else + 274:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 275:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 276:USB_DEVICE/Target/usbd_conf.c **** { + 530 .loc 1 276 1 is_stmt 1 view -0 + 531 .cfi_startproc + 532 @ args = 0, pretend = 0, frame = 0 + 533 @ frame_needed = 0, uses_anonymous_args = 0 + 534 .loc 1 276 1 is_stmt 0 view .LVU104 + 535 0000 08B5 push {r3, lr} + 536 .LCFI12: + 537 .cfi_def_cfa_offset 8 + 538 .cfi_offset 3, -8 + 539 .cfi_offset 14, -4 + 277:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); + 540 .loc 1 277 3 is_stmt 1 view .LVU105 + 541 0002 D0F80404 ldr r0, [r0, #1028] + 542 .LVL46: + 543 .loc 1 277 3 is_stmt 0 view .LVU106 + 544 0006 FFF7FEFF bl USBD_LL_IsoOUTIncomplete + 545 .LVL47: + 278:USB_DEVICE/Target/usbd_conf.c **** } + 546 .loc 1 278 1 view .LVU107 + 547 000a 08BD pop {r3, pc} + 548 .cfi_endproc + 549 .LFE154: + 551 .section .text.HAL_PCD_ISOINIncompleteCallback,"ax",%progbits + 552 .align 1 + 553 .global HAL_PCD_ISOINIncompleteCallback + 554 .syntax unified + 555 .thumb + 556 .thumb_func + 557 .fpu fpv5-d16 + 559 HAL_PCD_ISOINIncompleteCallback: + 560 .LVL48: + 561 .LFB155: + 279:USB_DEVICE/Target/usbd_conf.c **** + ARM GAS /tmp/ccTqS6pK.s page 16 + + + 280:USB_DEVICE/Target/usbd_conf.c **** /** + 281:USB_DEVICE/Target/usbd_conf.c **** * @brief ISOINIncomplete callback. + 282:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 283:USB_DEVICE/Target/usbd_conf.c **** * @param epnum: Endpoint number + 284:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 285:USB_DEVICE/Target/usbd_conf.c **** */ + 286:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 287:USB_DEVICE/Target/usbd_conf.c **** static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 288:USB_DEVICE/Target/usbd_conf.c **** #else + 289:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) + 290:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 291:USB_DEVICE/Target/usbd_conf.c **** { + 562 .loc 1 291 1 is_stmt 1 view -0 + 563 .cfi_startproc + 564 @ args = 0, pretend = 0, frame = 0 + 565 @ frame_needed = 0, uses_anonymous_args = 0 + 566 .loc 1 291 1 is_stmt 0 view .LVU109 + 567 0000 08B5 push {r3, lr} + 568 .LCFI13: + 569 .cfi_def_cfa_offset 8 + 570 .cfi_offset 3, -8 + 571 .cfi_offset 14, -4 + 292:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); + 572 .loc 1 292 3 is_stmt 1 view .LVU110 + 573 0002 D0F80404 ldr r0, [r0, #1028] + 574 .LVL49: + 575 .loc 1 292 3 is_stmt 0 view .LVU111 + 576 0006 FFF7FEFF bl USBD_LL_IsoINIncomplete + 577 .LVL50: + 293:USB_DEVICE/Target/usbd_conf.c **** } + 578 .loc 1 293 1 view .LVU112 + 579 000a 08BD pop {r3, pc} + 580 .cfi_endproc + 581 .LFE155: + 583 .section .text.HAL_PCD_ConnectCallback,"ax",%progbits + 584 .align 1 + 585 .global HAL_PCD_ConnectCallback + 586 .syntax unified + 587 .thumb + 588 .thumb_func + 589 .fpu fpv5-d16 + 591 HAL_PCD_ConnectCallback: + 592 .LVL51: + 593 .LFB156: + 294:USB_DEVICE/Target/usbd_conf.c **** + 295:USB_DEVICE/Target/usbd_conf.c **** /** + 296:USB_DEVICE/Target/usbd_conf.c **** * @brief Connect callback. + 297:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 298:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 299:USB_DEVICE/Target/usbd_conf.c **** */ + 300:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 301:USB_DEVICE/Target/usbd_conf.c **** static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) + 302:USB_DEVICE/Target/usbd_conf.c **** #else + 303:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) + 304:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 305:USB_DEVICE/Target/usbd_conf.c **** { + 594 .loc 1 305 1 is_stmt 1 view -0 + ARM GAS /tmp/ccTqS6pK.s page 17 + + + 595 .cfi_startproc + 596 @ args = 0, pretend = 0, frame = 0 + 597 @ frame_needed = 0, uses_anonymous_args = 0 + 598 .loc 1 305 1 is_stmt 0 view .LVU114 + 599 0000 08B5 push {r3, lr} + 600 .LCFI14: + 601 .cfi_def_cfa_offset 8 + 602 .cfi_offset 3, -8 + 603 .cfi_offset 14, -4 + 306:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); + 604 .loc 1 306 3 is_stmt 1 view .LVU115 + 605 0002 D0F80404 ldr r0, [r0, #1028] + 606 .LVL52: + 607 .loc 1 306 3 is_stmt 0 view .LVU116 + 608 0006 FFF7FEFF bl USBD_LL_DevConnected + 609 .LVL53: + 307:USB_DEVICE/Target/usbd_conf.c **** } + 610 .loc 1 307 1 view .LVU117 + 611 000a 08BD pop {r3, pc} + 612 .cfi_endproc + 613 .LFE156: + 615 .section .text.HAL_PCD_DisconnectCallback,"ax",%progbits + 616 .align 1 + 617 .global HAL_PCD_DisconnectCallback + 618 .syntax unified + 619 .thumb + 620 .thumb_func + 621 .fpu fpv5-d16 + 623 HAL_PCD_DisconnectCallback: + 624 .LVL54: + 625 .LFB157: + 308:USB_DEVICE/Target/usbd_conf.c **** + 309:USB_DEVICE/Target/usbd_conf.c **** /** + 310:USB_DEVICE/Target/usbd_conf.c **** * @brief Disconnect callback. + 311:USB_DEVICE/Target/usbd_conf.c **** * @param hpcd: PCD handle + 312:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 313:USB_DEVICE/Target/usbd_conf.c **** */ + 314:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 315:USB_DEVICE/Target/usbd_conf.c **** static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) + 316:USB_DEVICE/Target/usbd_conf.c **** #else + 317:USB_DEVICE/Target/usbd_conf.c **** void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) + 318:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 319:USB_DEVICE/Target/usbd_conf.c **** { + 626 .loc 1 319 1 is_stmt 1 view -0 + 627 .cfi_startproc + 628 @ args = 0, pretend = 0, frame = 0 + 629 @ frame_needed = 0, uses_anonymous_args = 0 + 630 .loc 1 319 1 is_stmt 0 view .LVU119 + 631 0000 08B5 push {r3, lr} + 632 .LCFI15: + 633 .cfi_def_cfa_offset 8 + 634 .cfi_offset 3, -8 + 635 .cfi_offset 14, -4 + 320:USB_DEVICE/Target/usbd_conf.c **** USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); + 636 .loc 1 320 3 is_stmt 1 view .LVU120 + 637 0002 D0F80404 ldr r0, [r0, #1028] + 638 .LVL55: + ARM GAS /tmp/ccTqS6pK.s page 18 + + + 639 .loc 1 320 3 is_stmt 0 view .LVU121 + 640 0006 FFF7FEFF bl USBD_LL_DevDisconnected + 641 .LVL56: + 321:USB_DEVICE/Target/usbd_conf.c **** } + 642 .loc 1 321 1 view .LVU122 + 643 000a 08BD pop {r3, pc} + 644 .cfi_endproc + 645 .LFE157: + 647 .section .text.USBD_LL_Init,"ax",%progbits + 648 .align 1 + 649 .global USBD_LL_Init + 650 .syntax unified + 651 .thumb + 652 .thumb_func + 653 .fpu fpv5-d16 + 655 USBD_LL_Init: + 656 .LVL57: + 657 .LFB158: + 322:USB_DEVICE/Target/usbd_conf.c **** + 323:USB_DEVICE/Target/usbd_conf.c **** /******************************************************************************* + 324:USB_DEVICE/Target/usbd_conf.c **** LL Driver Interface (USB Device Library --> PCD) + 325:USB_DEVICE/Target/usbd_conf.c **** *******************************************************************************/ + 326:USB_DEVICE/Target/usbd_conf.c **** + 327:USB_DEVICE/Target/usbd_conf.c **** /** + 328:USB_DEVICE/Target/usbd_conf.c **** * @brief Initializes the low level portion of the device driver. + 329:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 330:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 331:USB_DEVICE/Target/usbd_conf.c **** */ + 332:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) + 333:USB_DEVICE/Target/usbd_conf.c **** { + 658 .loc 1 333 1 is_stmt 1 view -0 + 659 .cfi_startproc + 660 @ args = 0, pretend = 0, frame = 0 + 661 @ frame_needed = 0, uses_anonymous_args = 0 + 334:USB_DEVICE/Target/usbd_conf.c **** /* Init USB Ip. */ + 335:USB_DEVICE/Target/usbd_conf.c **** if (pdev->id == DEVICE_FS) { + 662 .loc 1 335 3 view .LVU124 + 663 .loc 1 335 11 is_stmt 0 view .LVU125 + 664 0000 0278 ldrb r2, [r0] @ zero_extendqisi2 + 665 .loc 1 335 6 view .LVU126 + 666 0002 0AB1 cbz r2, .L49 + 336:USB_DEVICE/Target/usbd_conf.c **** /* Link the driver to the stack. */ + 337:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.pData = pdev; + 338:USB_DEVICE/Target/usbd_conf.c **** pdev->pData = &hpcd_USB_OTG_FS; + 339:USB_DEVICE/Target/usbd_conf.c **** + 340:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + 341:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dev_endpoints = 9; + 342:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + 343:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + 344:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + 345:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + 346:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + 347:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + 348:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; + 349:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + 350:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + 351:USB_DEVICE/Target/usbd_conf.c **** if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + ARM GAS /tmp/ccTqS6pK.s page 19 + + + 352:USB_DEVICE/Target/usbd_conf.c **** { + 353:USB_DEVICE/Target/usbd_conf.c **** Error_Handler( ); + 354:USB_DEVICE/Target/usbd_conf.c **** } + 355:USB_DEVICE/Target/usbd_conf.c **** + 356:USB_DEVICE/Target/usbd_conf.c **** #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + 357:USB_DEVICE/Target/usbd_conf.c **** /* Register USB PCD CallBacks */ + 358:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback); + 359:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback); + 360:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback); + 361:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback); + 362:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback); + 363:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback); + 364:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback); + 365:USB_DEVICE/Target/usbd_conf.c **** + 366:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback); + 367:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback); + 368:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback); + 369:USB_DEVICE/Target/usbd_conf.c **** HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback); + 370:USB_DEVICE/Target/usbd_conf.c **** #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + 371:USB_DEVICE/Target/usbd_conf.c **** HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); + 372:USB_DEVICE/Target/usbd_conf.c **** HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); + 373:USB_DEVICE/Target/usbd_conf.c **** HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + 374:USB_DEVICE/Target/usbd_conf.c **** } + 375:USB_DEVICE/Target/usbd_conf.c **** return USBD_OK; + 667 .loc 1 375 3 is_stmt 1 view .LVU127 + 376:USB_DEVICE/Target/usbd_conf.c **** } + 668 .loc 1 376 1 is_stmt 0 view .LVU128 + 669 0004 0020 movs r0, #0 + 670 .LVL58: + 671 .loc 1 376 1 view .LVU129 + 672 0006 7047 bx lr + 673 .LVL59: + 674 .L49: + 333:USB_DEVICE/Target/usbd_conf.c **** /* Init USB Ip. */ + 675 .loc 1 333 1 view .LVU130 + 676 0008 10B5 push {r4, lr} + 677 .LCFI16: + 678 .cfi_def_cfa_offset 8 + 679 .cfi_offset 4, -8 + 680 .cfi_offset 14, -4 + 681 000a 0346 mov r3, r0 + 337:USB_DEVICE/Target/usbd_conf.c **** pdev->pData = &hpcd_USB_OTG_FS; + 682 .loc 1 337 3 is_stmt 1 view .LVU131 + 337:USB_DEVICE/Target/usbd_conf.c **** pdev->pData = &hpcd_USB_OTG_FS; + 683 .loc 1 337 25 is_stmt 0 view .LVU132 + 684 000c 1548 ldr r0, .L51 + 685 .LVL60: + 337:USB_DEVICE/Target/usbd_conf.c **** pdev->pData = &hpcd_USB_OTG_FS; + 686 .loc 1 337 25 view .LVU133 + 687 000e C0F80434 str r3, [r0, #1028] + 338:USB_DEVICE/Target/usbd_conf.c **** + 688 .loc 1 338 3 is_stmt 1 view .LVU134 + 338:USB_DEVICE/Target/usbd_conf.c **** + 689 .loc 1 338 15 is_stmt 0 view .LVU135 + 690 0012 C3F8C402 str r0, [r3, #708] + 340:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dev_endpoints = 9; + 691 .loc 1 340 3 is_stmt 1 view .LVU136 + ARM GAS /tmp/ccTqS6pK.s page 20 + + + 340:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dev_endpoints = 9; + 692 .loc 1 340 28 is_stmt 0 view .LVU137 + 693 0016 144B ldr r3, .L51+4 + 694 .LVL61: + 340:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dev_endpoints = 9; + 695 .loc 1 340 28 view .LVU138 + 696 0018 0360 str r3, [r0] + 341:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + 697 .loc 1 341 3 is_stmt 1 view .LVU139 + 341:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + 698 .loc 1 341 38 is_stmt 0 view .LVU140 + 699 001a 0923 movs r3, #9 + 700 001c 4360 str r3, [r0, #4] + 342:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + 701 .loc 1 342 3 is_stmt 1 view .LVU141 + 342:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + 702 .loc 1 342 30 is_stmt 0 view .LVU142 + 703 001e 0222 movs r2, #2 + 704 0020 C260 str r2, [r0, #12] + 343:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + 705 .loc 1 343 3 is_stmt 1 view .LVU143 + 343:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + 706 .loc 1 343 35 is_stmt 0 view .LVU144 + 707 0022 0023 movs r3, #0 + 708 0024 0361 str r3, [r0, #16] + 344:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + 709 .loc 1 344 3 is_stmt 1 view .LVU145 + 344:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + 710 .loc 1 344 35 is_stmt 0 view .LVU146 + 711 0026 8261 str r2, [r0, #24] + 345:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + 712 .loc 1 345 3 is_stmt 1 view .LVU147 + 345:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + 713 .loc 1 345 35 is_stmt 0 view .LVU148 + 714 0028 C361 str r3, [r0, #28] + 346:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + 715 .loc 1 346 3 is_stmt 1 view .LVU149 + 346:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + 716 .loc 1 346 41 is_stmt 0 view .LVU150 + 717 002a 0362 str r3, [r0, #32] + 347:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; + 718 .loc 1 347 3 is_stmt 1 view .LVU151 + 347:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; + 719 .loc 1 347 35 is_stmt 0 view .LVU152 + 720 002c 4362 str r3, [r0, #36] + 348:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + 721 .loc 1 348 3 is_stmt 1 view .LVU153 + 348:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + 722 .loc 1 348 48 is_stmt 0 view .LVU154 + 723 002e 8362 str r3, [r0, #40] + 349:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + 724 .loc 1 349 3 is_stmt 1 view .LVU155 + 349:USB_DEVICE/Target/usbd_conf.c **** hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + 725 .loc 1 349 44 is_stmt 0 view .LVU156 + 726 0030 C362 str r3, [r0, #44] + 350:USB_DEVICE/Target/usbd_conf.c **** if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + 727 .loc 1 350 3 is_stmt 1 view .LVU157 + ARM GAS /tmp/ccTqS6pK.s page 21 + + + 350:USB_DEVICE/Target/usbd_conf.c **** if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + 728 .loc 1 350 42 is_stmt 0 view .LVU158 + 729 0032 0363 str r3, [r0, #48] + 351:USB_DEVICE/Target/usbd_conf.c **** { + 730 .loc 1 351 3 is_stmt 1 view .LVU159 + 351:USB_DEVICE/Target/usbd_conf.c **** { + 731 .loc 1 351 7 is_stmt 0 view .LVU160 + 732 0034 FFF7FEFF bl HAL_PCD_Init + 733 .LVL62: + 351:USB_DEVICE/Target/usbd_conf.c **** { + 734 .loc 1 351 6 view .LVU161 + 735 0038 80B9 cbnz r0, .L50 + 736 .L44: + 371:USB_DEVICE/Target/usbd_conf.c **** HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); + 737 .loc 1 371 3 is_stmt 1 view .LVU162 + 738 003a 0A4C ldr r4, .L51 + 739 003c 8021 movs r1, #128 + 740 003e 2046 mov r0, r4 + 741 0040 FFF7FEFF bl HAL_PCDEx_SetRxFiFo + 742 .LVL63: + 372:USB_DEVICE/Target/usbd_conf.c **** HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); + 743 .loc 1 372 3 view .LVU163 + 744 0044 4022 movs r2, #64 + 745 0046 0021 movs r1, #0 + 746 0048 2046 mov r0, r4 + 747 004a FFF7FEFF bl HAL_PCDEx_SetTxFiFo + 748 .LVL64: + 373:USB_DEVICE/Target/usbd_conf.c **** } + 749 .loc 1 373 3 view .LVU164 + 750 004e 8022 movs r2, #128 + 751 0050 0121 movs r1, #1 + 752 0052 2046 mov r0, r4 + 753 0054 FFF7FEFF bl HAL_PCDEx_SetTxFiFo + 754 .LVL65: + 375:USB_DEVICE/Target/usbd_conf.c **** } + 755 .loc 1 375 3 view .LVU165 + 756 .loc 1 376 1 is_stmt 0 view .LVU166 + 757 0058 0020 movs r0, #0 + 758 005a 10BD pop {r4, pc} + 759 .L50: + 353:USB_DEVICE/Target/usbd_conf.c **** } + 760 .loc 1 353 5 is_stmt 1 view .LVU167 + 761 005c FFF7FEFF bl Error_Handler + 762 .LVL66: + 763 0060 EBE7 b .L44 + 764 .L52: + 765 0062 00BF .align 2 + 766 .L51: + 767 0064 00000000 .word .LANCHOR0 + 768 0068 00000840 .word 1074266112 + 769 .cfi_endproc + 770 .LFE158: + 772 .section .text.USBD_LL_IsStallEP,"ax",%progbits + 773 .align 1 + 774 .global USBD_LL_IsStallEP + 775 .syntax unified + 776 .thumb + ARM GAS /tmp/ccTqS6pK.s page 22 + + + 777 .thumb_func + 778 .fpu fpv5-d16 + 780 USBD_LL_IsStallEP: + 781 .LVL67: + 782 .LFB167: + 377:USB_DEVICE/Target/usbd_conf.c **** + 378:USB_DEVICE/Target/usbd_conf.c **** /** + 379:USB_DEVICE/Target/usbd_conf.c **** * @brief De-Initializes the low level portion of the device driver. + 380:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 381:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 382:USB_DEVICE/Target/usbd_conf.c **** */ + 383:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) + 384:USB_DEVICE/Target/usbd_conf.c **** { + 385:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 386:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 387:USB_DEVICE/Target/usbd_conf.c **** + 388:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_DeInit(pdev->pData); + 389:USB_DEVICE/Target/usbd_conf.c **** + 390:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 391:USB_DEVICE/Target/usbd_conf.c **** + 392:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 393:USB_DEVICE/Target/usbd_conf.c **** } + 394:USB_DEVICE/Target/usbd_conf.c **** + 395:USB_DEVICE/Target/usbd_conf.c **** /** + 396:USB_DEVICE/Target/usbd_conf.c **** * @brief Starts the low level portion of the device driver. + 397:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 398:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 399:USB_DEVICE/Target/usbd_conf.c **** */ + 400:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) + 401:USB_DEVICE/Target/usbd_conf.c **** { + 402:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 403:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 404:USB_DEVICE/Target/usbd_conf.c **** + 405:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_Start(pdev->pData); + 406:USB_DEVICE/Target/usbd_conf.c **** + 407:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 408:USB_DEVICE/Target/usbd_conf.c **** + 409:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 410:USB_DEVICE/Target/usbd_conf.c **** } + 411:USB_DEVICE/Target/usbd_conf.c **** + 412:USB_DEVICE/Target/usbd_conf.c **** /** + 413:USB_DEVICE/Target/usbd_conf.c **** * @brief Stops the low level portion of the device driver. + 414:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 415:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 416:USB_DEVICE/Target/usbd_conf.c **** */ + 417:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) + 418:USB_DEVICE/Target/usbd_conf.c **** { + 419:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 420:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 421:USB_DEVICE/Target/usbd_conf.c **** + 422:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_Stop(pdev->pData); + 423:USB_DEVICE/Target/usbd_conf.c **** + 424:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 425:USB_DEVICE/Target/usbd_conf.c **** + 426:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 427:USB_DEVICE/Target/usbd_conf.c **** } + 428:USB_DEVICE/Target/usbd_conf.c **** + ARM GAS /tmp/ccTqS6pK.s page 23 + + + 429:USB_DEVICE/Target/usbd_conf.c **** /** + 430:USB_DEVICE/Target/usbd_conf.c **** * @brief Opens an endpoint of the low level driver. + 431:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 432:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 433:USB_DEVICE/Target/usbd_conf.c **** * @param ep_type: Endpoint type + 434:USB_DEVICE/Target/usbd_conf.c **** * @param ep_mps: Endpoint max packet size + 435:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 436:USB_DEVICE/Target/usbd_conf.c **** */ + 437:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint1 + 438:USB_DEVICE/Target/usbd_conf.c **** { + 439:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 440:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 441:USB_DEVICE/Target/usbd_conf.c **** + 442:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + 443:USB_DEVICE/Target/usbd_conf.c **** + 444:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 445:USB_DEVICE/Target/usbd_conf.c **** + 446:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 447:USB_DEVICE/Target/usbd_conf.c **** } + 448:USB_DEVICE/Target/usbd_conf.c **** + 449:USB_DEVICE/Target/usbd_conf.c **** /** + 450:USB_DEVICE/Target/usbd_conf.c **** * @brief Closes an endpoint of the low level driver. + 451:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 452:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 453:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 454:USB_DEVICE/Target/usbd_conf.c **** */ + 455:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 456:USB_DEVICE/Target/usbd_conf.c **** { + 457:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 458:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 459:USB_DEVICE/Target/usbd_conf.c **** + 460:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); + 461:USB_DEVICE/Target/usbd_conf.c **** + 462:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 463:USB_DEVICE/Target/usbd_conf.c **** + 464:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 465:USB_DEVICE/Target/usbd_conf.c **** } + 466:USB_DEVICE/Target/usbd_conf.c **** + 467:USB_DEVICE/Target/usbd_conf.c **** /** + 468:USB_DEVICE/Target/usbd_conf.c **** * @brief Flushes an endpoint of the Low Level Driver. + 469:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 470:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 471:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 472:USB_DEVICE/Target/usbd_conf.c **** */ + 473:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 474:USB_DEVICE/Target/usbd_conf.c **** { + 475:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 476:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 477:USB_DEVICE/Target/usbd_conf.c **** + 478:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); + 479:USB_DEVICE/Target/usbd_conf.c **** + 480:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 481:USB_DEVICE/Target/usbd_conf.c **** + 482:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 483:USB_DEVICE/Target/usbd_conf.c **** } + 484:USB_DEVICE/Target/usbd_conf.c **** + 485:USB_DEVICE/Target/usbd_conf.c **** /** + ARM GAS /tmp/ccTqS6pK.s page 24 + + + 486:USB_DEVICE/Target/usbd_conf.c **** * @brief Sets a Stall condition on an endpoint of the Low Level Driver. + 487:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 488:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 489:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 490:USB_DEVICE/Target/usbd_conf.c **** */ + 491:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 492:USB_DEVICE/Target/usbd_conf.c **** { + 493:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 494:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 495:USB_DEVICE/Target/usbd_conf.c **** + 496:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); + 497:USB_DEVICE/Target/usbd_conf.c **** + 498:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 499:USB_DEVICE/Target/usbd_conf.c **** + 500:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 501:USB_DEVICE/Target/usbd_conf.c **** } + 502:USB_DEVICE/Target/usbd_conf.c **** + 503:USB_DEVICE/Target/usbd_conf.c **** /** + 504:USB_DEVICE/Target/usbd_conf.c **** * @brief Clears a Stall condition on an endpoint of the Low Level Driver. + 505:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 506:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 507:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 508:USB_DEVICE/Target/usbd_conf.c **** */ + 509:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 510:USB_DEVICE/Target/usbd_conf.c **** { + 511:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 512:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 513:USB_DEVICE/Target/usbd_conf.c **** + 514:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); + 515:USB_DEVICE/Target/usbd_conf.c **** + 516:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 517:USB_DEVICE/Target/usbd_conf.c **** + 518:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 519:USB_DEVICE/Target/usbd_conf.c **** } + 520:USB_DEVICE/Target/usbd_conf.c **** + 521:USB_DEVICE/Target/usbd_conf.c **** /** + 522:USB_DEVICE/Target/usbd_conf.c **** * @brief Returns Stall condition. + 523:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 524:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 525:USB_DEVICE/Target/usbd_conf.c **** * @retval Stall (1: Yes, 0: No) + 526:USB_DEVICE/Target/usbd_conf.c **** */ + 527:USB_DEVICE/Target/usbd_conf.c **** uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 528:USB_DEVICE/Target/usbd_conf.c **** { + 783 .loc 1 528 1 view -0 + 784 .cfi_startproc + 785 @ args = 0, pretend = 0, frame = 0 + 786 @ frame_needed = 0, uses_anonymous_args = 0 + 787 @ link register save eliminated. + 529:USB_DEVICE/Target/usbd_conf.c **** PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; + 788 .loc 1 529 3 view .LVU169 + 789 .loc 1 529 22 is_stmt 0 view .LVU170 + 790 0000 D0F8C432 ldr r3, [r0, #708] + 791 .LVL68: + 530:USB_DEVICE/Target/usbd_conf.c **** + 531:USB_DEVICE/Target/usbd_conf.c **** if((ep_addr & 0x80) == 0x80) + 792 .loc 1 531 3 is_stmt 1 view .LVU171 + 793 .loc 1 531 5 is_stmt 0 view .LVU172 + ARM GAS /tmp/ccTqS6pK.s page 25 + + + 794 0004 11F0800F tst r1, #128 + 795 0008 08D1 bne .L56 + 532:USB_DEVICE/Target/usbd_conf.c **** { + 533:USB_DEVICE/Target/usbd_conf.c **** return hpcd->IN_ep[ep_addr & 0x7F].is_stall; + 534:USB_DEVICE/Target/usbd_conf.c **** } + 535:USB_DEVICE/Target/usbd_conf.c **** else + 536:USB_DEVICE/Target/usbd_conf.c **** { + 537:USB_DEVICE/Target/usbd_conf.c **** return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; + 796 .loc 1 537 5 is_stmt 1 view .LVU173 + 797 .loc 1 537 33 is_stmt 0 view .LVU174 + 798 000a 01F07F01 and r1, r1, #127 + 799 .LVL69: + 800 .loc 1 537 40 view .LVU175 + 801 000e C1EBC101 rsb r1, r1, r1, lsl #3 + 802 0012 03EB8101 add r1, r3, r1, lsl #2 + 803 0016 91F8FE01 ldrb r0, [r1, #510] @ zero_extendqisi2 + 804 .LVL70: + 538:USB_DEVICE/Target/usbd_conf.c **** } + 539:USB_DEVICE/Target/usbd_conf.c **** } + 805 .loc 1 539 1 view .LVU176 + 806 001a 7047 bx lr + 807 .LVL71: + 808 .L56: + 533:USB_DEVICE/Target/usbd_conf.c **** } + 809 .loc 1 533 5 is_stmt 1 view .LVU177 + 533:USB_DEVICE/Target/usbd_conf.c **** } + 810 .loc 1 533 32 is_stmt 0 view .LVU178 + 811 001c 01F07F01 and r1, r1, #127 + 812 .LVL72: + 533:USB_DEVICE/Target/usbd_conf.c **** } + 813 .loc 1 533 39 view .LVU179 + 814 0020 C1EBC101 rsb r1, r1, r1, lsl #3 + 815 0024 03EB8101 add r1, r3, r1, lsl #2 + 816 0028 91F83E00 ldrb r0, [r1, #62] @ zero_extendqisi2 + 817 .LVL73: + 533:USB_DEVICE/Target/usbd_conf.c **** } + 818 .loc 1 533 39 view .LVU180 + 819 002c 7047 bx lr + 820 .cfi_endproc + 821 .LFE167: + 823 .section .text.USBD_LL_GetRxDataSize,"ax",%progbits + 824 .align 1 + 825 .global USBD_LL_GetRxDataSize + 826 .syntax unified + 827 .thumb + 828 .thumb_func + 829 .fpu fpv5-d16 + 831 USBD_LL_GetRxDataSize: + 832 .LVL74: + 833 .LFB171: + 540:USB_DEVICE/Target/usbd_conf.c **** + 541:USB_DEVICE/Target/usbd_conf.c **** /** + 542:USB_DEVICE/Target/usbd_conf.c **** * @brief Assigns a USB address to the device. + 543:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 544:USB_DEVICE/Target/usbd_conf.c **** * @param dev_addr: Device address + 545:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 546:USB_DEVICE/Target/usbd_conf.c **** */ + ARM GAS /tmp/ccTqS6pK.s page 26 + + + 547:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) + 548:USB_DEVICE/Target/usbd_conf.c **** { + 549:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 550:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 551:USB_DEVICE/Target/usbd_conf.c **** + 552:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); + 553:USB_DEVICE/Target/usbd_conf.c **** + 554:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 555:USB_DEVICE/Target/usbd_conf.c **** + 556:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 557:USB_DEVICE/Target/usbd_conf.c **** } + 558:USB_DEVICE/Target/usbd_conf.c **** + 559:USB_DEVICE/Target/usbd_conf.c **** /** + 560:USB_DEVICE/Target/usbd_conf.c **** * @brief Transmits data over an endpoint. + 561:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 562:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 563:USB_DEVICE/Target/usbd_conf.c **** * @param pbuf: Pointer to data to be sent + 564:USB_DEVICE/Target/usbd_conf.c **** * @param size: Data size + 565:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 566:USB_DEVICE/Target/usbd_conf.c **** */ + 567:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint3 + 568:USB_DEVICE/Target/usbd_conf.c **** { + 569:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 570:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 571:USB_DEVICE/Target/usbd_conf.c **** + 572:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); + 573:USB_DEVICE/Target/usbd_conf.c **** + 574:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 575:USB_DEVICE/Target/usbd_conf.c **** + 576:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 577:USB_DEVICE/Target/usbd_conf.c **** } + 578:USB_DEVICE/Target/usbd_conf.c **** + 579:USB_DEVICE/Target/usbd_conf.c **** /** + 580:USB_DEVICE/Target/usbd_conf.c **** * @brief Prepares an endpoint for reception. + 581:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 582:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 583:USB_DEVICE/Target/usbd_conf.c **** * @param pbuf: Pointer to data to be received + 584:USB_DEVICE/Target/usbd_conf.c **** * @param size: Data size + 585:USB_DEVICE/Target/usbd_conf.c **** * @retval USBD status + 586:USB_DEVICE/Target/usbd_conf.c **** */ + 587:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, + 588:USB_DEVICE/Target/usbd_conf.c **** { + 589:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 590:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 591:USB_DEVICE/Target/usbd_conf.c **** + 592:USB_DEVICE/Target/usbd_conf.c **** hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); + 593:USB_DEVICE/Target/usbd_conf.c **** + 594:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_Get_USB_Status(hal_status); + 595:USB_DEVICE/Target/usbd_conf.c **** + 596:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 597:USB_DEVICE/Target/usbd_conf.c **** } + 598:USB_DEVICE/Target/usbd_conf.c **** + 599:USB_DEVICE/Target/usbd_conf.c **** /** + 600:USB_DEVICE/Target/usbd_conf.c **** * @brief Returns the last transfered packet size. + 601:USB_DEVICE/Target/usbd_conf.c **** * @param pdev: Device handle + 602:USB_DEVICE/Target/usbd_conf.c **** * @param ep_addr: Endpoint number + 603:USB_DEVICE/Target/usbd_conf.c **** * @retval Recived Data Size + ARM GAS /tmp/ccTqS6pK.s page 27 + + + 604:USB_DEVICE/Target/usbd_conf.c **** */ + 605:USB_DEVICE/Target/usbd_conf.c **** uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 606:USB_DEVICE/Target/usbd_conf.c **** { + 834 .loc 1 606 1 is_stmt 1 view -0 + 835 .cfi_startproc + 836 @ args = 0, pretend = 0, frame = 0 + 837 @ frame_needed = 0, uses_anonymous_args = 0 + 838 .loc 1 606 1 is_stmt 0 view .LVU182 + 839 0000 08B5 push {r3, lr} + 840 .LCFI17: + 841 .cfi_def_cfa_offset 8 + 842 .cfi_offset 3, -8 + 843 .cfi_offset 14, -4 + 607:USB_DEVICE/Target/usbd_conf.c **** return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); + 844 .loc 1 607 3 is_stmt 1 view .LVU183 + 845 .loc 1 607 10 is_stmt 0 view .LVU184 + 846 0002 D0F8C402 ldr r0, [r0, #708] + 847 .LVL75: + 848 .loc 1 607 10 view .LVU185 + 849 0006 FFF7FEFF bl HAL_PCD_EP_GetRxCount + 850 .LVL76: + 608:USB_DEVICE/Target/usbd_conf.c **** } + 851 .loc 1 608 1 view .LVU186 + 852 000a 08BD pop {r3, pc} + 853 .cfi_endproc + 854 .LFE171: + 856 .section .text.USBD_LL_Delay,"ax",%progbits + 857 .align 1 + 858 .global USBD_LL_Delay + 859 .syntax unified + 860 .thumb + 861 .thumb_func + 862 .fpu fpv5-d16 + 864 USBD_LL_Delay: + 865 .LVL77: + 866 .LFB172: + 609:USB_DEVICE/Target/usbd_conf.c **** + 610:USB_DEVICE/Target/usbd_conf.c **** /** + 611:USB_DEVICE/Target/usbd_conf.c **** * @brief Delays routine for the USB device library. + 612:USB_DEVICE/Target/usbd_conf.c **** * @param Delay: Delay in ms + 613:USB_DEVICE/Target/usbd_conf.c **** * @retval None + 614:USB_DEVICE/Target/usbd_conf.c **** */ + 615:USB_DEVICE/Target/usbd_conf.c **** void USBD_LL_Delay(uint32_t Delay) + 616:USB_DEVICE/Target/usbd_conf.c **** { + 867 .loc 1 616 1 is_stmt 1 view -0 + 868 .cfi_startproc + 869 @ args = 0, pretend = 0, frame = 0 + 870 @ frame_needed = 0, uses_anonymous_args = 0 + 871 .loc 1 616 1 is_stmt 0 view .LVU188 + 872 0000 08B5 push {r3, lr} + 873 .LCFI18: + 874 .cfi_def_cfa_offset 8 + 875 .cfi_offset 3, -8 + 876 .cfi_offset 14, -4 + 617:USB_DEVICE/Target/usbd_conf.c **** HAL_Delay(Delay); + 877 .loc 1 617 3 is_stmt 1 view .LVU189 + 878 0002 FFF7FEFF bl HAL_Delay + ARM GAS /tmp/ccTqS6pK.s page 28 + + + 879 .LVL78: + 618:USB_DEVICE/Target/usbd_conf.c **** } + 880 .loc 1 618 1 is_stmt 0 view .LVU190 + 881 0006 08BD pop {r3, pc} + 882 .cfi_endproc + 883 .LFE172: + 885 .section .text.USBD_Get_USB_Status,"ax",%progbits + 886 .align 1 + 887 .global USBD_Get_USB_Status + 888 .syntax unified + 889 .thumb + 890 .thumb_func + 891 .fpu fpv5-d16 + 893 USBD_Get_USB_Status: + 894 .LVL79: + 895 .LFB173: + 619:USB_DEVICE/Target/usbd_conf.c **** + 620:USB_DEVICE/Target/usbd_conf.c **** /** + 621:USB_DEVICE/Target/usbd_conf.c **** * @brief Retuns the USB status depending on the HAL status: + 622:USB_DEVICE/Target/usbd_conf.c **** * @param hal_status: HAL status + 623:USB_DEVICE/Target/usbd_conf.c **** * @retval USB status + 624:USB_DEVICE/Target/usbd_conf.c **** */ + 625:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status) + 626:USB_DEVICE/Target/usbd_conf.c **** { + 896 .loc 1 626 1 is_stmt 1 view -0 + 897 .cfi_startproc + 898 @ args = 0, pretend = 0, frame = 0 + 899 @ frame_needed = 0, uses_anonymous_args = 0 + 900 @ link register save eliminated. + 627:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 901 .loc 1 627 3 view .LVU192 + 628:USB_DEVICE/Target/usbd_conf.c **** + 629:USB_DEVICE/Target/usbd_conf.c **** switch (hal_status) + 902 .loc 1 629 3 view .LVU193 + 903 0000 0328 cmp r0, #3 + 904 0002 05D8 bhi .L67 + 905 0004 DFE800F0 tbb [pc, r0] + 906 .L64: + 907 0008 05 .byte (.L62-.L64)/2 + 908 0009 04 .byte (.L67-.L64)/2 + 909 000a 02 .byte (.L65-.L64)/2 + 910 000b 05 .byte (.L62-.L64)/2 + 911 .p2align 1 + 912 .L65: + 630:USB_DEVICE/Target/usbd_conf.c **** { + 631:USB_DEVICE/Target/usbd_conf.c **** case HAL_OK : + 632:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_OK; + 633:USB_DEVICE/Target/usbd_conf.c **** break; + 634:USB_DEVICE/Target/usbd_conf.c **** case HAL_ERROR : + 635:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_FAIL; + 636:USB_DEVICE/Target/usbd_conf.c **** break; + 637:USB_DEVICE/Target/usbd_conf.c **** case HAL_BUSY : + 638:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_BUSY; + 913 .loc 1 638 7 view .LVU194 + 914 .LVL80: + 639:USB_DEVICE/Target/usbd_conf.c **** break; + 915 .loc 1 639 5 view .LVU195 + ARM GAS /tmp/ccTqS6pK.s page 29 + + + 638:USB_DEVICE/Target/usbd_conf.c **** break; + 916 .loc 1 638 18 is_stmt 0 view .LVU196 + 917 000c 0120 movs r0, #1 + 918 .LVL81: + 919 .loc 1 639 5 view .LVU197 + 920 000e 7047 bx lr + 921 .LVL82: + 922 .L67: + 635:USB_DEVICE/Target/usbd_conf.c **** break; + 923 .loc 1 635 18 view .LVU198 + 924 0010 0320 movs r0, #3 + 925 .LVL83: + 926 .L62: + 640:USB_DEVICE/Target/usbd_conf.c **** case HAL_TIMEOUT : + 641:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_FAIL; + 642:USB_DEVICE/Target/usbd_conf.c **** break; + 643:USB_DEVICE/Target/usbd_conf.c **** default : + 644:USB_DEVICE/Target/usbd_conf.c **** usb_status = USBD_FAIL; + 645:USB_DEVICE/Target/usbd_conf.c **** break; + 646:USB_DEVICE/Target/usbd_conf.c **** } + 647:USB_DEVICE/Target/usbd_conf.c **** return usb_status; + 927 .loc 1 647 3 is_stmt 1 view .LVU199 + 648:USB_DEVICE/Target/usbd_conf.c **** } + 928 .loc 1 648 1 is_stmt 0 view .LVU200 + 929 0012 7047 bx lr + 930 .cfi_endproc + 931 .LFE173: + 933 .section .text.USBD_LL_DeInit,"ax",%progbits + 934 .align 1 + 935 .global USBD_LL_DeInit + 936 .syntax unified + 937 .thumb + 938 .thumb_func + 939 .fpu fpv5-d16 + 941 USBD_LL_DeInit: + 942 .LVL84: + 943 .LFB159: + 384:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 944 .loc 1 384 1 is_stmt 1 view -0 + 945 .cfi_startproc + 946 @ args = 0, pretend = 0, frame = 0 + 947 @ frame_needed = 0, uses_anonymous_args = 0 + 384:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 948 .loc 1 384 1 is_stmt 0 view .LVU202 + 949 0000 08B5 push {r3, lr} + 950 .LCFI19: + 951 .cfi_def_cfa_offset 8 + 952 .cfi_offset 3, -8 + 953 .cfi_offset 14, -4 + 385:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 954 .loc 1 385 3 is_stmt 1 view .LVU203 + 955 .LVL85: + 386:USB_DEVICE/Target/usbd_conf.c **** + 956 .loc 1 386 3 view .LVU204 + 388:USB_DEVICE/Target/usbd_conf.c **** + 957 .loc 1 388 3 view .LVU205 + 388:USB_DEVICE/Target/usbd_conf.c **** + ARM GAS /tmp/ccTqS6pK.s page 30 + + + 958 .loc 1 388 16 is_stmt 0 view .LVU206 + 959 0002 D0F8C402 ldr r0, [r0, #708] + 960 .LVL86: + 388:USB_DEVICE/Target/usbd_conf.c **** + 961 .loc 1 388 16 view .LVU207 + 962 0006 FFF7FEFF bl HAL_PCD_DeInit + 963 .LVL87: + 390:USB_DEVICE/Target/usbd_conf.c **** + 964 .loc 1 390 3 is_stmt 1 view .LVU208 + 390:USB_DEVICE/Target/usbd_conf.c **** + 965 .loc 1 390 17 is_stmt 0 view .LVU209 + 966 000a FFF7FEFF bl USBD_Get_USB_Status + 967 .LVL88: + 392:USB_DEVICE/Target/usbd_conf.c **** } + 968 .loc 1 392 3 is_stmt 1 view .LVU210 + 393:USB_DEVICE/Target/usbd_conf.c **** + 969 .loc 1 393 1 is_stmt 0 view .LVU211 + 970 000e 08BD pop {r3, pc} + 971 .cfi_endproc + 972 .LFE159: + 974 .section .text.USBD_LL_Start,"ax",%progbits + 975 .align 1 + 976 .global USBD_LL_Start + 977 .syntax unified + 978 .thumb + 979 .thumb_func + 980 .fpu fpv5-d16 + 982 USBD_LL_Start: + 983 .LVL89: + 984 .LFB160: + 401:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 985 .loc 1 401 1 is_stmt 1 view -0 + 986 .cfi_startproc + 987 @ args = 0, pretend = 0, frame = 0 + 988 @ frame_needed = 0, uses_anonymous_args = 0 + 401:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 989 .loc 1 401 1 is_stmt 0 view .LVU213 + 990 0000 08B5 push {r3, lr} + 991 .LCFI20: + 992 .cfi_def_cfa_offset 8 + 993 .cfi_offset 3, -8 + 994 .cfi_offset 14, -4 + 402:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 995 .loc 1 402 3 is_stmt 1 view .LVU214 + 996 .LVL90: + 403:USB_DEVICE/Target/usbd_conf.c **** + 997 .loc 1 403 3 view .LVU215 + 405:USB_DEVICE/Target/usbd_conf.c **** + 998 .loc 1 405 3 view .LVU216 + 405:USB_DEVICE/Target/usbd_conf.c **** + 999 .loc 1 405 16 is_stmt 0 view .LVU217 + 1000 0002 D0F8C402 ldr r0, [r0, #708] + 1001 .LVL91: + 405:USB_DEVICE/Target/usbd_conf.c **** + 1002 .loc 1 405 16 view .LVU218 + 1003 0006 FFF7FEFF bl HAL_PCD_Start + 1004 .LVL92: + ARM GAS /tmp/ccTqS6pK.s page 31 + + + 407:USB_DEVICE/Target/usbd_conf.c **** + 1005 .loc 1 407 3 is_stmt 1 view .LVU219 + 407:USB_DEVICE/Target/usbd_conf.c **** + 1006 .loc 1 407 17 is_stmt 0 view .LVU220 + 1007 000a FFF7FEFF bl USBD_Get_USB_Status + 1008 .LVL93: + 409:USB_DEVICE/Target/usbd_conf.c **** } + 1009 .loc 1 409 3 is_stmt 1 view .LVU221 + 410:USB_DEVICE/Target/usbd_conf.c **** + 1010 .loc 1 410 1 is_stmt 0 view .LVU222 + 1011 000e 08BD pop {r3, pc} + 1012 .cfi_endproc + 1013 .LFE160: + 1015 .section .text.USBD_LL_Stop,"ax",%progbits + 1016 .align 1 + 1017 .global USBD_LL_Stop + 1018 .syntax unified + 1019 .thumb + 1020 .thumb_func + 1021 .fpu fpv5-d16 + 1023 USBD_LL_Stop: + 1024 .LVL94: + 1025 .LFB161: + 418:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1026 .loc 1 418 1 is_stmt 1 view -0 + 1027 .cfi_startproc + 1028 @ args = 0, pretend = 0, frame = 0 + 1029 @ frame_needed = 0, uses_anonymous_args = 0 + 418:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1030 .loc 1 418 1 is_stmt 0 view .LVU224 + 1031 0000 08B5 push {r3, lr} + 1032 .LCFI21: + 1033 .cfi_def_cfa_offset 8 + 1034 .cfi_offset 3, -8 + 1035 .cfi_offset 14, -4 + 419:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1036 .loc 1 419 3 is_stmt 1 view .LVU225 + 1037 .LVL95: + 420:USB_DEVICE/Target/usbd_conf.c **** + 1038 .loc 1 420 3 view .LVU226 + 422:USB_DEVICE/Target/usbd_conf.c **** + 1039 .loc 1 422 3 view .LVU227 + 422:USB_DEVICE/Target/usbd_conf.c **** + 1040 .loc 1 422 16 is_stmt 0 view .LVU228 + 1041 0002 D0F8C402 ldr r0, [r0, #708] + 1042 .LVL96: + 422:USB_DEVICE/Target/usbd_conf.c **** + 1043 .loc 1 422 16 view .LVU229 + 1044 0006 FFF7FEFF bl HAL_PCD_Stop + 1045 .LVL97: + 424:USB_DEVICE/Target/usbd_conf.c **** + 1046 .loc 1 424 3 is_stmt 1 view .LVU230 + 424:USB_DEVICE/Target/usbd_conf.c **** + 1047 .loc 1 424 17 is_stmt 0 view .LVU231 + 1048 000a FFF7FEFF bl USBD_Get_USB_Status + 1049 .LVL98: + 426:USB_DEVICE/Target/usbd_conf.c **** } + ARM GAS /tmp/ccTqS6pK.s page 32 + + + 1050 .loc 1 426 3 is_stmt 1 view .LVU232 + 427:USB_DEVICE/Target/usbd_conf.c **** + 1051 .loc 1 427 1 is_stmt 0 view .LVU233 + 1052 000e 08BD pop {r3, pc} + 1053 .cfi_endproc + 1054 .LFE161: + 1056 .section .text.USBD_LL_OpenEP,"ax",%progbits + 1057 .align 1 + 1058 .global USBD_LL_OpenEP + 1059 .syntax unified + 1060 .thumb + 1061 .thumb_func + 1062 .fpu fpv5-d16 + 1064 USBD_LL_OpenEP: + 1065 .LVL99: + 1066 .LFB162: + 438:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1067 .loc 1 438 1 is_stmt 1 view -0 + 1068 .cfi_startproc + 1069 @ args = 0, pretend = 0, frame = 0 + 1070 @ frame_needed = 0, uses_anonymous_args = 0 + 438:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1071 .loc 1 438 1 is_stmt 0 view .LVU235 + 1072 0000 08B5 push {r3, lr} + 1073 .LCFI22: + 1074 .cfi_def_cfa_offset 8 + 1075 .cfi_offset 3, -8 + 1076 .cfi_offset 14, -4 + 1077 0002 9446 mov ip, r2 + 1078 0004 1A46 mov r2, r3 + 1079 .LVL100: + 439:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1080 .loc 1 439 3 is_stmt 1 view .LVU236 + 440:USB_DEVICE/Target/usbd_conf.c **** + 1081 .loc 1 440 3 view .LVU237 + 442:USB_DEVICE/Target/usbd_conf.c **** + 1082 .loc 1 442 3 view .LVU238 + 442:USB_DEVICE/Target/usbd_conf.c **** + 1083 .loc 1 442 16 is_stmt 0 view .LVU239 + 1084 0006 6346 mov r3, ip + 1085 .LVL101: + 442:USB_DEVICE/Target/usbd_conf.c **** + 1086 .loc 1 442 16 view .LVU240 + 1087 0008 D0F8C402 ldr r0, [r0, #708] + 1088 .LVL102: + 442:USB_DEVICE/Target/usbd_conf.c **** + 1089 .loc 1 442 16 view .LVU241 + 1090 000c FFF7FEFF bl HAL_PCD_EP_Open + 1091 .LVL103: + 444:USB_DEVICE/Target/usbd_conf.c **** + 1092 .loc 1 444 3 is_stmt 1 view .LVU242 + 444:USB_DEVICE/Target/usbd_conf.c **** + 1093 .loc 1 444 17 is_stmt 0 view .LVU243 + 1094 0010 FFF7FEFF bl USBD_Get_USB_Status + 1095 .LVL104: + 446:USB_DEVICE/Target/usbd_conf.c **** } + 1096 .loc 1 446 3 is_stmt 1 view .LVU244 + ARM GAS /tmp/ccTqS6pK.s page 33 + + + 447:USB_DEVICE/Target/usbd_conf.c **** + 1097 .loc 1 447 1 is_stmt 0 view .LVU245 + 1098 0014 08BD pop {r3, pc} + 1099 .cfi_endproc + 1100 .LFE162: + 1102 .section .text.USBD_LL_CloseEP,"ax",%progbits + 1103 .align 1 + 1104 .global USBD_LL_CloseEP + 1105 .syntax unified + 1106 .thumb + 1107 .thumb_func + 1108 .fpu fpv5-d16 + 1110 USBD_LL_CloseEP: + 1111 .LVL105: + 1112 .LFB163: + 456:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1113 .loc 1 456 1 is_stmt 1 view -0 + 1114 .cfi_startproc + 1115 @ args = 0, pretend = 0, frame = 0 + 1116 @ frame_needed = 0, uses_anonymous_args = 0 + 456:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1117 .loc 1 456 1 is_stmt 0 view .LVU247 + 1118 0000 08B5 push {r3, lr} + 1119 .LCFI23: + 1120 .cfi_def_cfa_offset 8 + 1121 .cfi_offset 3, -8 + 1122 .cfi_offset 14, -4 + 457:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1123 .loc 1 457 3 is_stmt 1 view .LVU248 + 1124 .LVL106: + 458:USB_DEVICE/Target/usbd_conf.c **** + 1125 .loc 1 458 3 view .LVU249 + 460:USB_DEVICE/Target/usbd_conf.c **** + 1126 .loc 1 460 3 view .LVU250 + 460:USB_DEVICE/Target/usbd_conf.c **** + 1127 .loc 1 460 16 is_stmt 0 view .LVU251 + 1128 0002 D0F8C402 ldr r0, [r0, #708] + 1129 .LVL107: + 460:USB_DEVICE/Target/usbd_conf.c **** + 1130 .loc 1 460 16 view .LVU252 + 1131 0006 FFF7FEFF bl HAL_PCD_EP_Close + 1132 .LVL108: + 462:USB_DEVICE/Target/usbd_conf.c **** + 1133 .loc 1 462 3 is_stmt 1 view .LVU253 + 462:USB_DEVICE/Target/usbd_conf.c **** + 1134 .loc 1 462 17 is_stmt 0 view .LVU254 + 1135 000a FFF7FEFF bl USBD_Get_USB_Status + 1136 .LVL109: + 464:USB_DEVICE/Target/usbd_conf.c **** } + 1137 .loc 1 464 3 is_stmt 1 view .LVU255 + 465:USB_DEVICE/Target/usbd_conf.c **** + 1138 .loc 1 465 1 is_stmt 0 view .LVU256 + 1139 000e 08BD pop {r3, pc} + 1140 .cfi_endproc + 1141 .LFE163: + 1143 .section .text.USBD_LL_FlushEP,"ax",%progbits + 1144 .align 1 + ARM GAS /tmp/ccTqS6pK.s page 34 + + + 1145 .global USBD_LL_FlushEP + 1146 .syntax unified + 1147 .thumb + 1148 .thumb_func + 1149 .fpu fpv5-d16 + 1151 USBD_LL_FlushEP: + 1152 .LVL110: + 1153 .LFB164: + 474:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1154 .loc 1 474 1 is_stmt 1 view -0 + 1155 .cfi_startproc + 1156 @ args = 0, pretend = 0, frame = 0 + 1157 @ frame_needed = 0, uses_anonymous_args = 0 + 474:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1158 .loc 1 474 1 is_stmt 0 view .LVU258 + 1159 0000 08B5 push {r3, lr} + 1160 .LCFI24: + 1161 .cfi_def_cfa_offset 8 + 1162 .cfi_offset 3, -8 + 1163 .cfi_offset 14, -4 + 475:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1164 .loc 1 475 3 is_stmt 1 view .LVU259 + 1165 .LVL111: + 476:USB_DEVICE/Target/usbd_conf.c **** + 1166 .loc 1 476 3 view .LVU260 + 478:USB_DEVICE/Target/usbd_conf.c **** + 1167 .loc 1 478 3 view .LVU261 + 478:USB_DEVICE/Target/usbd_conf.c **** + 1168 .loc 1 478 16 is_stmt 0 view .LVU262 + 1169 0002 D0F8C402 ldr r0, [r0, #708] + 1170 .LVL112: + 478:USB_DEVICE/Target/usbd_conf.c **** + 1171 .loc 1 478 16 view .LVU263 + 1172 0006 FFF7FEFF bl HAL_PCD_EP_Flush + 1173 .LVL113: + 480:USB_DEVICE/Target/usbd_conf.c **** + 1174 .loc 1 480 3 is_stmt 1 view .LVU264 + 480:USB_DEVICE/Target/usbd_conf.c **** + 1175 .loc 1 480 17 is_stmt 0 view .LVU265 + 1176 000a FFF7FEFF bl USBD_Get_USB_Status + 1177 .LVL114: + 482:USB_DEVICE/Target/usbd_conf.c **** } + 1178 .loc 1 482 3 is_stmt 1 view .LVU266 + 483:USB_DEVICE/Target/usbd_conf.c **** + 1179 .loc 1 483 1 is_stmt 0 view .LVU267 + 1180 000e 08BD pop {r3, pc} + 1181 .cfi_endproc + 1182 .LFE164: + 1184 .section .text.USBD_LL_StallEP,"ax",%progbits + 1185 .align 1 + 1186 .global USBD_LL_StallEP + 1187 .syntax unified + 1188 .thumb + 1189 .thumb_func + 1190 .fpu fpv5-d16 + 1192 USBD_LL_StallEP: + 1193 .LVL115: + ARM GAS /tmp/ccTqS6pK.s page 35 + + + 1194 .LFB165: + 492:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1195 .loc 1 492 1 is_stmt 1 view -0 + 1196 .cfi_startproc + 1197 @ args = 0, pretend = 0, frame = 0 + 1198 @ frame_needed = 0, uses_anonymous_args = 0 + 492:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1199 .loc 1 492 1 is_stmt 0 view .LVU269 + 1200 0000 08B5 push {r3, lr} + 1201 .LCFI25: + 1202 .cfi_def_cfa_offset 8 + 1203 .cfi_offset 3, -8 + 1204 .cfi_offset 14, -4 + 493:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1205 .loc 1 493 3 is_stmt 1 view .LVU270 + 1206 .LVL116: + 494:USB_DEVICE/Target/usbd_conf.c **** + 1207 .loc 1 494 3 view .LVU271 + 496:USB_DEVICE/Target/usbd_conf.c **** + 1208 .loc 1 496 3 view .LVU272 + 496:USB_DEVICE/Target/usbd_conf.c **** + 1209 .loc 1 496 16 is_stmt 0 view .LVU273 + 1210 0002 D0F8C402 ldr r0, [r0, #708] + 1211 .LVL117: + 496:USB_DEVICE/Target/usbd_conf.c **** + 1212 .loc 1 496 16 view .LVU274 + 1213 0006 FFF7FEFF bl HAL_PCD_EP_SetStall + 1214 .LVL118: + 498:USB_DEVICE/Target/usbd_conf.c **** + 1215 .loc 1 498 3 is_stmt 1 view .LVU275 + 498:USB_DEVICE/Target/usbd_conf.c **** + 1216 .loc 1 498 17 is_stmt 0 view .LVU276 + 1217 000a FFF7FEFF bl USBD_Get_USB_Status + 1218 .LVL119: + 500:USB_DEVICE/Target/usbd_conf.c **** } + 1219 .loc 1 500 3 is_stmt 1 view .LVU277 + 501:USB_DEVICE/Target/usbd_conf.c **** + 1220 .loc 1 501 1 is_stmt 0 view .LVU278 + 1221 000e 08BD pop {r3, pc} + 1222 .cfi_endproc + 1223 .LFE165: + 1225 .section .text.USBD_LL_ClearStallEP,"ax",%progbits + 1226 .align 1 + 1227 .global USBD_LL_ClearStallEP + 1228 .syntax unified + 1229 .thumb + 1230 .thumb_func + 1231 .fpu fpv5-d16 + 1233 USBD_LL_ClearStallEP: + 1234 .LVL120: + 1235 .LFB166: + 510:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1236 .loc 1 510 1 is_stmt 1 view -0 + 1237 .cfi_startproc + 1238 @ args = 0, pretend = 0, frame = 0 + 1239 @ frame_needed = 0, uses_anonymous_args = 0 + 510:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + ARM GAS /tmp/ccTqS6pK.s page 36 + + + 1240 .loc 1 510 1 is_stmt 0 view .LVU280 + 1241 0000 08B5 push {r3, lr} + 1242 .LCFI26: + 1243 .cfi_def_cfa_offset 8 + 1244 .cfi_offset 3, -8 + 1245 .cfi_offset 14, -4 + 511:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1246 .loc 1 511 3 is_stmt 1 view .LVU281 + 1247 .LVL121: + 512:USB_DEVICE/Target/usbd_conf.c **** + 1248 .loc 1 512 3 view .LVU282 + 514:USB_DEVICE/Target/usbd_conf.c **** + 1249 .loc 1 514 3 view .LVU283 + 514:USB_DEVICE/Target/usbd_conf.c **** + 1250 .loc 1 514 16 is_stmt 0 view .LVU284 + 1251 0002 D0F8C402 ldr r0, [r0, #708] + 1252 .LVL122: + 514:USB_DEVICE/Target/usbd_conf.c **** + 1253 .loc 1 514 16 view .LVU285 + 1254 0006 FFF7FEFF bl HAL_PCD_EP_ClrStall + 1255 .LVL123: + 516:USB_DEVICE/Target/usbd_conf.c **** + 1256 .loc 1 516 3 is_stmt 1 view .LVU286 + 516:USB_DEVICE/Target/usbd_conf.c **** + 1257 .loc 1 516 17 is_stmt 0 view .LVU287 + 1258 000a FFF7FEFF bl USBD_Get_USB_Status + 1259 .LVL124: + 518:USB_DEVICE/Target/usbd_conf.c **** } + 1260 .loc 1 518 3 is_stmt 1 view .LVU288 + 519:USB_DEVICE/Target/usbd_conf.c **** + 1261 .loc 1 519 1 is_stmt 0 view .LVU289 + 1262 000e 08BD pop {r3, pc} + 1263 .cfi_endproc + 1264 .LFE166: + 1266 .section .text.USBD_LL_SetUSBAddress,"ax",%progbits + 1267 .align 1 + 1268 .global USBD_LL_SetUSBAddress + 1269 .syntax unified + 1270 .thumb + 1271 .thumb_func + 1272 .fpu fpv5-d16 + 1274 USBD_LL_SetUSBAddress: + 1275 .LVL125: + 1276 .LFB168: + 548:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1277 .loc 1 548 1 is_stmt 1 view -0 + 1278 .cfi_startproc + 1279 @ args = 0, pretend = 0, frame = 0 + 1280 @ frame_needed = 0, uses_anonymous_args = 0 + 548:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1281 .loc 1 548 1 is_stmt 0 view .LVU291 + 1282 0000 08B5 push {r3, lr} + 1283 .LCFI27: + 1284 .cfi_def_cfa_offset 8 + 1285 .cfi_offset 3, -8 + 1286 .cfi_offset 14, -4 + 549:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + ARM GAS /tmp/ccTqS6pK.s page 37 + + + 1287 .loc 1 549 3 is_stmt 1 view .LVU292 + 1288 .LVL126: + 550:USB_DEVICE/Target/usbd_conf.c **** + 1289 .loc 1 550 3 view .LVU293 + 552:USB_DEVICE/Target/usbd_conf.c **** + 1290 .loc 1 552 3 view .LVU294 + 552:USB_DEVICE/Target/usbd_conf.c **** + 1291 .loc 1 552 16 is_stmt 0 view .LVU295 + 1292 0002 D0F8C402 ldr r0, [r0, #708] + 1293 .LVL127: + 552:USB_DEVICE/Target/usbd_conf.c **** + 1294 .loc 1 552 16 view .LVU296 + 1295 0006 FFF7FEFF bl HAL_PCD_SetAddress + 1296 .LVL128: + 554:USB_DEVICE/Target/usbd_conf.c **** + 1297 .loc 1 554 3 is_stmt 1 view .LVU297 + 554:USB_DEVICE/Target/usbd_conf.c **** + 1298 .loc 1 554 17 is_stmt 0 view .LVU298 + 1299 000a FFF7FEFF bl USBD_Get_USB_Status + 1300 .LVL129: + 556:USB_DEVICE/Target/usbd_conf.c **** } + 1301 .loc 1 556 3 is_stmt 1 view .LVU299 + 557:USB_DEVICE/Target/usbd_conf.c **** + 1302 .loc 1 557 1 is_stmt 0 view .LVU300 + 1303 000e 08BD pop {r3, pc} + 1304 .cfi_endproc + 1305 .LFE168: + 1307 .section .text.USBD_LL_Transmit,"ax",%progbits + 1308 .align 1 + 1309 .global USBD_LL_Transmit + 1310 .syntax unified + 1311 .thumb + 1312 .thumb_func + 1313 .fpu fpv5-d16 + 1315 USBD_LL_Transmit: + 1316 .LVL130: + 1317 .LFB169: + 568:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1318 .loc 1 568 1 is_stmt 1 view -0 + 1319 .cfi_startproc + 1320 @ args = 0, pretend = 0, frame = 0 + 1321 @ frame_needed = 0, uses_anonymous_args = 0 + 568:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1322 .loc 1 568 1 is_stmt 0 view .LVU302 + 1323 0000 08B5 push {r3, lr} + 1324 .LCFI28: + 1325 .cfi_def_cfa_offset 8 + 1326 .cfi_offset 3, -8 + 1327 .cfi_offset 14, -4 + 569:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1328 .loc 1 569 3 is_stmt 1 view .LVU303 + 1329 .LVL131: + 570:USB_DEVICE/Target/usbd_conf.c **** + 1330 .loc 1 570 3 view .LVU304 + 572:USB_DEVICE/Target/usbd_conf.c **** + 1331 .loc 1 572 3 view .LVU305 + 572:USB_DEVICE/Target/usbd_conf.c **** + ARM GAS /tmp/ccTqS6pK.s page 38 + + + 1332 .loc 1 572 16 is_stmt 0 view .LVU306 + 1333 0002 D0F8C402 ldr r0, [r0, #708] + 1334 .LVL132: + 572:USB_DEVICE/Target/usbd_conf.c **** + 1335 .loc 1 572 16 view .LVU307 + 1336 0006 FFF7FEFF bl HAL_PCD_EP_Transmit + 1337 .LVL133: + 574:USB_DEVICE/Target/usbd_conf.c **** + 1338 .loc 1 574 3 is_stmt 1 view .LVU308 + 574:USB_DEVICE/Target/usbd_conf.c **** + 1339 .loc 1 574 17 is_stmt 0 view .LVU309 + 1340 000a FFF7FEFF bl USBD_Get_USB_Status + 1341 .LVL134: + 576:USB_DEVICE/Target/usbd_conf.c **** } + 1342 .loc 1 576 3 is_stmt 1 view .LVU310 + 577:USB_DEVICE/Target/usbd_conf.c **** + 1343 .loc 1 577 1 is_stmt 0 view .LVU311 + 1344 000e 08BD pop {r3, pc} + 1345 .cfi_endproc + 1346 .LFE169: + 1348 .section .text.USBD_LL_PrepareReceive,"ax",%progbits + 1349 .align 1 + 1350 .global USBD_LL_PrepareReceive + 1351 .syntax unified + 1352 .thumb + 1353 .thumb_func + 1354 .fpu fpv5-d16 + 1356 USBD_LL_PrepareReceive: + 1357 .LVL135: + 1358 .LFB170: + 588:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1359 .loc 1 588 1 is_stmt 1 view -0 + 1360 .cfi_startproc + 1361 @ args = 0, pretend = 0, frame = 0 + 1362 @ frame_needed = 0, uses_anonymous_args = 0 + 588:USB_DEVICE/Target/usbd_conf.c **** HAL_StatusTypeDef hal_status = HAL_OK; + 1363 .loc 1 588 1 is_stmt 0 view .LVU313 + 1364 0000 08B5 push {r3, lr} + 1365 .LCFI29: + 1366 .cfi_def_cfa_offset 8 + 1367 .cfi_offset 3, -8 + 1368 .cfi_offset 14, -4 + 589:USB_DEVICE/Target/usbd_conf.c **** USBD_StatusTypeDef usb_status = USBD_OK; + 1369 .loc 1 589 3 is_stmt 1 view .LVU314 + 1370 .LVL136: + 590:USB_DEVICE/Target/usbd_conf.c **** + 1371 .loc 1 590 3 view .LVU315 + 592:USB_DEVICE/Target/usbd_conf.c **** + 1372 .loc 1 592 3 view .LVU316 + 592:USB_DEVICE/Target/usbd_conf.c **** + 1373 .loc 1 592 16 is_stmt 0 view .LVU317 + 1374 0002 D0F8C402 ldr r0, [r0, #708] + 1375 .LVL137: + 592:USB_DEVICE/Target/usbd_conf.c **** + 1376 .loc 1 592 16 view .LVU318 + 1377 0006 FFF7FEFF bl HAL_PCD_EP_Receive + 1378 .LVL138: + ARM GAS /tmp/ccTqS6pK.s page 39 + + + 594:USB_DEVICE/Target/usbd_conf.c **** + 1379 .loc 1 594 3 is_stmt 1 view .LVU319 + 594:USB_DEVICE/Target/usbd_conf.c **** + 1380 .loc 1 594 17 is_stmt 0 view .LVU320 + 1381 000a FFF7FEFF bl USBD_Get_USB_Status + 1382 .LVL139: + 596:USB_DEVICE/Target/usbd_conf.c **** } + 1383 .loc 1 596 3 is_stmt 1 view .LVU321 + 597:USB_DEVICE/Target/usbd_conf.c **** + 1384 .loc 1 597 1 is_stmt 0 view .LVU322 + 1385 000e 08BD pop {r3, pc} + 1386 .cfi_endproc + 1387 .LFE170: + 1389 .global hpcd_USB_OTG_FS + 1390 .section .bss.hpcd_USB_OTG_FS,"aw",%nobits + 1391 .align 2 + 1392 .set .LANCHOR0,. + 0 + 1395 hpcd_USB_OTG_FS: + 1396 0000 00000000 .space 1032 + 1396 00000000 + 1396 00000000 + 1396 00000000 + 1396 00000000 + 1397 .text + 1398 .Letext0: + 1399 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1400 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1401 .file 4 "Drivers/CMSIS/Include/core_cm7.h" + 1402 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1403 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + 1404 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1405 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + 1406 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h" + 1407 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h" + 1408 .file 11 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 1409 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 1410 .file 13 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h" + 1411 .file 14 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h" + 1412 .file 15 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h" + ARM GAS /tmp/ccTqS6pK.s page 40 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_conf.c + /tmp/ccTqS6pK.s:17 .text.HAL_PCD_MspInit:0000000000000000 $t + /tmp/ccTqS6pK.s:25 .text.HAL_PCD_MspInit:0000000000000000 HAL_PCD_MspInit + /tmp/ccTqS6pK.s:158 .text.HAL_PCD_MspInit:0000000000000098 $d + /tmp/ccTqS6pK.s:165 .text.HAL_PCD_MspDeInit:0000000000000000 $t + /tmp/ccTqS6pK.s:172 .text.HAL_PCD_MspDeInit:0000000000000000 HAL_PCD_MspDeInit + /tmp/ccTqS6pK.s:227 .text.HAL_PCD_MspDeInit:0000000000000038 $d + /tmp/ccTqS6pK.s:234 .text.HAL_PCD_SetupStageCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:241 .text.HAL_PCD_SetupStageCallback:0000000000000000 HAL_PCD_SetupStageCallback + /tmp/ccTqS6pK.s:267 .text.HAL_PCD_DataOutStageCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:274 .text.HAL_PCD_DataOutStageCallback:0000000000000000 HAL_PCD_DataOutStageCallback + /tmp/ccTqS6pK.s:302 .text.HAL_PCD_DataInStageCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:309 .text.HAL_PCD_DataInStageCallback:0000000000000000 HAL_PCD_DataInStageCallback + /tmp/ccTqS6pK.s:337 .text.HAL_PCD_SOFCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:344 .text.HAL_PCD_SOFCallback:0000000000000000 HAL_PCD_SOFCallback + /tmp/ccTqS6pK.s:369 .text.HAL_PCD_ResetCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:376 .text.HAL_PCD_ResetCallback:0000000000000000 HAL_PCD_ResetCallback + /tmp/ccTqS6pK.s:432 .text.HAL_PCD_SuspendCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:439 .text.HAL_PCD_SuspendCallback:0000000000000000 HAL_PCD_SuspendCallback + /tmp/ccTqS6pK.s:483 .text.HAL_PCD_SuspendCallback:000000000000002c $d + /tmp/ccTqS6pK.s:488 .text.HAL_PCD_ResumeCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:495 .text.HAL_PCD_ResumeCallback:0000000000000000 HAL_PCD_ResumeCallback + /tmp/ccTqS6pK.s:520 .text.HAL_PCD_ISOOUTIncompleteCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:527 .text.HAL_PCD_ISOOUTIncompleteCallback:0000000000000000 HAL_PCD_ISOOUTIncompleteCallback + /tmp/ccTqS6pK.s:552 .text.HAL_PCD_ISOINIncompleteCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:559 .text.HAL_PCD_ISOINIncompleteCallback:0000000000000000 HAL_PCD_ISOINIncompleteCallback + /tmp/ccTqS6pK.s:584 .text.HAL_PCD_ConnectCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:591 .text.HAL_PCD_ConnectCallback:0000000000000000 HAL_PCD_ConnectCallback + /tmp/ccTqS6pK.s:616 .text.HAL_PCD_DisconnectCallback:0000000000000000 $t + /tmp/ccTqS6pK.s:623 .text.HAL_PCD_DisconnectCallback:0000000000000000 HAL_PCD_DisconnectCallback + /tmp/ccTqS6pK.s:648 .text.USBD_LL_Init:0000000000000000 $t + /tmp/ccTqS6pK.s:655 .text.USBD_LL_Init:0000000000000000 USBD_LL_Init + /tmp/ccTqS6pK.s:767 .text.USBD_LL_Init:0000000000000064 $d + /tmp/ccTqS6pK.s:773 .text.USBD_LL_IsStallEP:0000000000000000 $t + /tmp/ccTqS6pK.s:780 .text.USBD_LL_IsStallEP:0000000000000000 USBD_LL_IsStallEP + /tmp/ccTqS6pK.s:824 .text.USBD_LL_GetRxDataSize:0000000000000000 $t + /tmp/ccTqS6pK.s:831 .text.USBD_LL_GetRxDataSize:0000000000000000 USBD_LL_GetRxDataSize + /tmp/ccTqS6pK.s:857 .text.USBD_LL_Delay:0000000000000000 $t + /tmp/ccTqS6pK.s:864 .text.USBD_LL_Delay:0000000000000000 USBD_LL_Delay + /tmp/ccTqS6pK.s:886 .text.USBD_Get_USB_Status:0000000000000000 $t + /tmp/ccTqS6pK.s:893 .text.USBD_Get_USB_Status:0000000000000000 USBD_Get_USB_Status + /tmp/ccTqS6pK.s:907 .text.USBD_Get_USB_Status:0000000000000008 $d + /tmp/ccTqS6pK.s:911 .text.USBD_Get_USB_Status:000000000000000c $t + /tmp/ccTqS6pK.s:934 .text.USBD_LL_DeInit:0000000000000000 $t + /tmp/ccTqS6pK.s:941 .text.USBD_LL_DeInit:0000000000000000 USBD_LL_DeInit + /tmp/ccTqS6pK.s:975 .text.USBD_LL_Start:0000000000000000 $t + /tmp/ccTqS6pK.s:982 .text.USBD_LL_Start:0000000000000000 USBD_LL_Start + /tmp/ccTqS6pK.s:1016 .text.USBD_LL_Stop:0000000000000000 $t + /tmp/ccTqS6pK.s:1023 .text.USBD_LL_Stop:0000000000000000 USBD_LL_Stop + /tmp/ccTqS6pK.s:1057 .text.USBD_LL_OpenEP:0000000000000000 $t + /tmp/ccTqS6pK.s:1064 .text.USBD_LL_OpenEP:0000000000000000 USBD_LL_OpenEP + /tmp/ccTqS6pK.s:1103 .text.USBD_LL_CloseEP:0000000000000000 $t + /tmp/ccTqS6pK.s:1110 .text.USBD_LL_CloseEP:0000000000000000 USBD_LL_CloseEP + /tmp/ccTqS6pK.s:1144 .text.USBD_LL_FlushEP:0000000000000000 $t + /tmp/ccTqS6pK.s:1151 .text.USBD_LL_FlushEP:0000000000000000 USBD_LL_FlushEP + /tmp/ccTqS6pK.s:1185 .text.USBD_LL_StallEP:0000000000000000 $t + ARM GAS /tmp/ccTqS6pK.s page 41 + + + /tmp/ccTqS6pK.s:1192 .text.USBD_LL_StallEP:0000000000000000 USBD_LL_StallEP + /tmp/ccTqS6pK.s:1226 .text.USBD_LL_ClearStallEP:0000000000000000 $t + /tmp/ccTqS6pK.s:1233 .text.USBD_LL_ClearStallEP:0000000000000000 USBD_LL_ClearStallEP + /tmp/ccTqS6pK.s:1267 .text.USBD_LL_SetUSBAddress:0000000000000000 $t + /tmp/ccTqS6pK.s:1274 .text.USBD_LL_SetUSBAddress:0000000000000000 USBD_LL_SetUSBAddress + /tmp/ccTqS6pK.s:1308 .text.USBD_LL_Transmit:0000000000000000 $t + /tmp/ccTqS6pK.s:1315 .text.USBD_LL_Transmit:0000000000000000 USBD_LL_Transmit + /tmp/ccTqS6pK.s:1349 .text.USBD_LL_PrepareReceive:0000000000000000 $t + /tmp/ccTqS6pK.s:1356 .text.USBD_LL_PrepareReceive:0000000000000000 USBD_LL_PrepareReceive + /tmp/ccTqS6pK.s:1395 .bss.hpcd_USB_OTG_FS:0000000000000000 hpcd_USB_OTG_FS + /tmp/ccTqS6pK.s:1391 .bss.hpcd_USB_OTG_FS:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_Init +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +HAL_GPIO_DeInit +HAL_NVIC_DisableIRQ +USBD_LL_SetupStage +USBD_LL_DataOutStage +USBD_LL_DataInStage +USBD_LL_SOF +Error_Handler +USBD_LL_SetSpeed +USBD_LL_Reset +USBD_LL_Suspend +USBD_LL_Resume +USBD_LL_IsoOUTIncomplete +USBD_LL_IsoINIncomplete +USBD_LL_DevConnected +USBD_LL_DevDisconnected +HAL_PCD_Init +HAL_PCDEx_SetRxFiFo +HAL_PCDEx_SetTxFiFo +HAL_PCD_EP_GetRxCount +HAL_Delay +HAL_PCD_DeInit +HAL_PCD_Start +HAL_PCD_Stop +HAL_PCD_EP_Open +HAL_PCD_EP_Close +HAL_PCD_EP_Flush +HAL_PCD_EP_SetStall +HAL_PCD_EP_ClrStall +HAL_PCD_SetAddress +HAL_PCD_EP_Transmit +HAL_PCD_EP_Receive diff --git a/build/usbd_conf.o b/build/usbd_conf.o new file mode 100644 index 0000000..523cfd9 Binary files /dev/null and b/build/usbd_conf.o differ diff --git a/build/usbd_core.d b/build/usbd_core.d new file mode 100644 index 0000000..cf932c8 --- /dev/null +++ b/build/usbd_core.d @@ -0,0 +1,85 @@ +build/usbd_core.o: \ + Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/build/usbd_core.lst b/build/usbd_core.lst new file mode 100644 index 0000000..9eea0dc --- /dev/null +++ b/build/usbd_core.lst @@ -0,0 +1,2171 @@ +ARM GAS /tmp/cc0ngCj0.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_core.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.USBD_Init,"ax",%progbits + 17 .align 1 + 18 .global USBD_Init + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 USBD_Init: + 26 .LVL0: + 27 .LFB145: + 28 .file 1 "Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c" + 1:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 2:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ****************************************************************************** + 3:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @file usbd_core.c + 4:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @author MCD Application Team + 5:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief This file provides all the USBD core functions. + 6:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ****************************************************************************** + 7:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @attention + 8:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * + 9:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** *

© Copyright (c) 2015 STMicroelectronics. + 10:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * All rights reserved.

+ 11:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * + 12:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * This software component is licensed by ST under Ultimate Liberty license + 13:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 14:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * the License. You may obtain a copy of the License at: + 15:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * www.st.com/SLA0044 + 16:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * + 17:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ****************************************************************************** + 18:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 19:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 20:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Includes ------------------------------------------------------------------*/ + 21:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #include "usbd_core.h" + 22:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 23:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @addtogroup STM32_USBD_DEVICE_LIBRARY + 24:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 25:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 26:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 27:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 28:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE + 29:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief usbd core module + 30:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + ARM GAS /tmp/cc0ngCj0.s page 2 + + + 31:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 32:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 33:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_TypesDefinitions + 34:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 35:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 36:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 37:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 38:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @} + 39:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 40:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 41:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 42:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Defines + 43:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 44:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 45:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 46:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 47:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @} + 48:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 49:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 50:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 51:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Macros + 52:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 53:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 54:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 55:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 56:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @} + 57:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 58:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 59:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 60:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_FunctionPrototypes + 61:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 62:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 63:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 64:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 65:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @} + 66:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 67:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 68:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Variables + 69:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 70:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 71:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 72:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 73:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @} + 74:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 75:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 76:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 77:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** @defgroup USBD_CORE_Private_Functions + 78:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @{ + 79:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 80:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 81:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 82:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_Init + 83:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Initializes the device stack and load the class driver + 84:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 85:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdesc: Descriptor structure address + 86:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param id: Low level core index + 87:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval None + ARM GAS /tmp/cc0ngCj0.s page 3 + + + 88:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 89:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, + 90:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_DescriptorsTypeDef *pdesc, uint8_t id) + 91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 29 .loc 1 91 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 92:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 33 .loc 1 92 3 view .LVU1 + 93:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 94:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Check whether the USB Host handle is valid */ + 95:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev == NULL) + 34 .loc 1 95 3 view .LVU2 + 35 .loc 1 95 6 is_stmt 0 view .LVU3 + 36 0000 C0B1 cbz r0, .L6 + 91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 37 .loc 1 91 1 view .LVU4 + 38 0002 08B5 push {r3, lr} + 39 .LCFI0: + 40 .cfi_def_cfa_offset 8 + 41 .cfi_offset 3, -8 + 42 .cfi_offset 14, -4 + 43 0004 0346 mov r3, r0 + 96:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 97:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if (USBD_DEBUG_LEVEL > 1U) + 98:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_ErrLog("Invalid Device handle"); + 99:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif + 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_FAIL; + 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 103:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Unlink previous class */ + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass != NULL) + 44 .loc 1 104 3 is_stmt 1 view .LVU5 + 45 .loc 1 104 11 is_stmt 0 view .LVU6 + 46 0006 D0F8B802 ldr r0, [r0, #696] + 47 .LVL1: + 48 .loc 1 104 6 view .LVU7 + 49 000a 10B1 cbz r0, .L3 + 105:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 106:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass = NULL; + 50 .loc 1 106 5 is_stmt 1 view .LVU8 + 51 .loc 1 106 18 is_stmt 0 view .LVU9 + 52 000c 0020 movs r0, #0 + 53 000e C3F8B802 str r0, [r3, #696] + 54 .L3: + 107:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pConfDesc != NULL) + 55 .loc 1 109 3 is_stmt 1 view .LVU10 + 56 .loc 1 109 11 is_stmt 0 view .LVU11 + 57 0012 D3F8CC02 ldr r0, [r3, #716] + 58 .loc 1 109 6 view .LVU12 + 59 0016 10B1 cbz r0, .L4 + 110:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 111:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pConfDesc = NULL; + 60 .loc 1 111 5 is_stmt 1 view .LVU13 + ARM GAS /tmp/cc0ngCj0.s page 4 + + + 61 .loc 1 111 21 is_stmt 0 view .LVU14 + 62 0018 0020 movs r0, #0 + 63 001a C3F8CC02 str r0, [r3, #716] + 64 .L4: + 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 113:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 114:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Assign USBD Descriptors */ + 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdesc != NULL) + 65 .loc 1 115 3 is_stmt 1 view .LVU15 + 66 .loc 1 115 6 is_stmt 0 view .LVU16 + 67 001e 09B1 cbz r1, .L5 + 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 117:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pDesc = pdesc; + 68 .loc 1 117 5 is_stmt 1 view .LVU17 + 69 .loc 1 117 17 is_stmt 0 view .LVU18 + 70 0020 C3F8B412 str r1, [r3, #692] + 71 .L5: + 118:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Set Device initial State */ + 121:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_state = USBD_STATE_DEFAULT; + 72 .loc 1 121 3 is_stmt 1 view .LVU19 + 73 .loc 1 121 19 is_stmt 0 view .LVU20 + 74 0024 0121 movs r1, #1 + 75 .LVL2: + 76 .loc 1 121 19 view .LVU21 + 77 0026 83F89C12 strb r1, [r3, #668] + 122:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->id = id; + 78 .loc 1 122 3 is_stmt 1 view .LVU22 + 79 .loc 1 122 12 is_stmt 0 view .LVU23 + 80 002a 1A70 strb r2, [r3] + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Initialize low level driver */ + 125:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_LL_Init(pdev); + 81 .loc 1 125 3 is_stmt 1 view .LVU24 + 82 .loc 1 125 9 is_stmt 0 view .LVU25 + 83 002c 1846 mov r0, r3 + 84 002e FFF7FEFF bl USBD_LL_Init + 85 .LVL3: + 126:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 86 .loc 1 127 3 is_stmt 1 view .LVU26 + 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 87 .loc 1 128 1 is_stmt 0 view .LVU27 + 88 0032 08BD pop {r3, pc} + 89 .LVL4: + 90 .L6: + 91 .LCFI1: + 92 .cfi_def_cfa_offset 0 + 93 .cfi_restore 3 + 94 .cfi_restore 14 + 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 95 .loc 1 100 12 view .LVU28 + 96 0034 0320 movs r0, #3 + 97 .LVL5: + 98 .loc 1 128 1 view .LVU29 + 99 0036 7047 bx lr + ARM GAS /tmp/cc0ngCj0.s page 5 + + + 100 .cfi_endproc + 101 .LFE145: + 103 .section .text.USBD_DeInit,"ax",%progbits + 104 .align 1 + 105 .global USBD_DeInit + 106 .syntax unified + 107 .thumb + 108 .thumb_func + 109 .fpu fpv5-d16 + 111 USBD_DeInit: + 112 .LVL6: + 113 .LFB146: + 129:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 130:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_DeInit + 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Re-Initialize th device library + 133:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 134:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status: status + 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) + 137:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 114 .loc 1 137 1 is_stmt 1 view -0 + 115 .cfi_startproc + 116 @ args = 0, pretend = 0, frame = 0 + 117 @ frame_needed = 0, uses_anonymous_args = 0 + 118 .loc 1 137 1 is_stmt 0 view .LVU31 + 119 0000 10B5 push {r4, lr} + 120 .LCFI2: + 121 .cfi_def_cfa_offset 8 + 122 .cfi_offset 4, -8 + 123 .cfi_offset 14, -4 + 124 0002 0446 mov r4, r0 + 138:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 125 .loc 1 138 3 is_stmt 1 view .LVU32 + 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Set Default State */ + 141:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_state = USBD_STATE_DEFAULT; + 126 .loc 1 141 3 view .LVU33 + 127 .loc 1 141 19 is_stmt 0 view .LVU34 + 128 0004 0123 movs r3, #1 + 129 0006 80F89C32 strb r3, [r0, #668] + 142:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Free Class Resources */ + 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass != NULL) + 130 .loc 1 144 3 is_stmt 1 view .LVU35 + 131 .loc 1 144 11 is_stmt 0 view .LVU36 + 132 000a D0F8B832 ldr r3, [r0, #696] + 133 .loc 1 144 6 view .LVU37 + 134 000e 13B1 cbz r3, .L12 + 145:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 146:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + 135 .loc 1 146 5 is_stmt 1 view .LVU38 + 136 .loc 1 146 17 is_stmt 0 view .LVU39 + 137 0010 5B68 ldr r3, [r3, #4] + 138 .loc 1 146 5 view .LVU40 + 139 0012 0179 ldrb r1, [r0, #4] @ zero_extendqisi2 + 140 0014 9847 blx r3 + ARM GAS /tmp/cc0ngCj0.s page 6 + + + 141 .LVL7: + 142 .L12: + 147:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 148:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pConfDesc != NULL) + 143 .loc 1 149 3 is_stmt 1 view .LVU41 + 144 .loc 1 149 11 is_stmt 0 view .LVU42 + 145 0016 D4F8CC32 ldr r3, [r4, #716] + 146 .loc 1 149 6 view .LVU43 + 147 001a 13B1 cbz r3, .L13 + 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 151:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pConfDesc = NULL; + 148 .loc 1 151 5 is_stmt 1 view .LVU44 + 149 .loc 1 151 21 is_stmt 0 view .LVU45 + 150 001c 0023 movs r3, #0 + 151 001e C4F8CC32 str r3, [r4, #716] + 152 .L13: + 152:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Stop the low level driver */ + 155:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_LL_Stop(pdev); + 153 .loc 1 155 3 is_stmt 1 view .LVU46 + 154 .loc 1 155 9 is_stmt 0 view .LVU47 + 155 0022 2046 mov r0, r4 + 156 0024 FFF7FEFF bl USBD_LL_Stop + 157 .LVL8: + 156:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 157:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (ret != USBD_OK) + 158 .loc 1 157 3 is_stmt 1 view .LVU48 + 159 .loc 1 157 6 is_stmt 0 view .LVU49 + 160 0028 00B1 cbz r0, .L16 + 161 .L14: + 158:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 159:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 160:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 161:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 162:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Initialize low level driver */ + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_LL_DeInit(pdev); + 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 166:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 162 .loc 1 166 1 view .LVU50 + 163 002a 10BD pop {r4, pc} + 164 .LVL9: + 165 .L16: + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 166 .loc 1 163 3 is_stmt 1 view .LVU51 + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 167 .loc 1 163 9 is_stmt 0 view .LVU52 + 168 002c 2046 mov r0, r4 + 169 .LVL10: + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 170 .loc 1 163 9 view .LVU53 + 171 002e FFF7FEFF bl USBD_LL_DeInit + 172 .LVL11: + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 173 .loc 1 165 3 is_stmt 1 view .LVU54 + ARM GAS /tmp/cc0ngCj0.s page 7 + + + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 174 .loc 1 165 10 is_stmt 0 view .LVU55 + 175 0032 FAE7 b .L14 + 176 .cfi_endproc + 177 .LFE146: + 179 .section .text.USBD_RegisterClass,"ax",%progbits + 180 .align 1 + 181 .global USBD_RegisterClass + 182 .syntax unified + 183 .thumb + 184 .thumb_func + 185 .fpu fpv5-d16 + 187 USBD_RegisterClass: + 188 .LVL12: + 189 .LFB147: + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 168:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 169:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_RegisterClass + 170:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Link class driver to Device Core. + 171:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pDevice : Device Handle + 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pclass: Class handle + 173:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval USBD Status + 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 175:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) + 176:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 190 .loc 1 176 1 is_stmt 1 view -0 + 191 .cfi_startproc + 192 @ args = 0, pretend = 0, frame = 8 + 193 @ frame_needed = 0, uses_anonymous_args = 0 + 194 .loc 1 176 1 is_stmt 0 view .LVU57 + 195 0000 10B5 push {r4, lr} + 196 .LCFI3: + 197 .cfi_def_cfa_offset 8 + 198 .cfi_offset 4, -8 + 199 .cfi_offset 14, -4 + 200 0002 82B0 sub sp, sp, #8 + 201 .LCFI4: + 202 .cfi_def_cfa_offset 16 + 177:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** uint16_t len = 0U; + 203 .loc 1 177 3 is_stmt 1 view .LVU58 + 204 .loc 1 177 12 is_stmt 0 view .LVU59 + 205 0004 0023 movs r3, #0 + 206 0006 ADF80630 strh r3, [sp, #6] @ movhi + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 179:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pclass == NULL) + 207 .loc 1 179 3 is_stmt 1 view .LVU60 + 208 .loc 1 179 6 is_stmt 0 view .LVU61 + 209 000a 59B1 cbz r1, .L19 + 210 000c 0446 mov r4, r0 + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 181:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if (USBD_DEBUG_LEVEL > 1U) + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_ErrLog("Invalid Class handle"); + 183:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_FAIL; + 185:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 186:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 187:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* link the class to the USB Device handle */ + ARM GAS /tmp/cc0ngCj0.s page 8 + + + 188:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass = pclass; + 211 .loc 1 188 3 is_stmt 1 view .LVU62 + 212 .loc 1 188 16 is_stmt 0 view .LVU63 + 213 000e C0F8B812 str r1, [r0, #696] + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 190:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Get Device Configuration Descriptor */ + 191:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #ifdef USE_USB_FS + 192:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len); + 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #else /* USE_USB_HS */ + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len); + 214 .loc 1 194 3 is_stmt 1 view .LVU64 + 215 .loc 1 194 41 is_stmt 0 view .LVU65 + 216 0012 8B6A ldr r3, [r1, #40] + 217 .loc 1 194 29 view .LVU66 + 218 0014 0DF10600 add r0, sp, #6 + 219 .LVL13: + 220 .loc 1 194 29 view .LVU67 + 221 0018 9847 blx r3 + 222 .LVL14: + 223 .loc 1 194 19 view .LVU68 + 224 001a C4F8CC02 str r0, [r4, #716] + 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif /* USE_USB_FS */ + 196:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 197:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 198:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 225 .loc 1 198 3 is_stmt 1 view .LVU69 + 226 .loc 1 198 10 is_stmt 0 view .LVU70 + 227 001e 0020 movs r0, #0 + 228 .LVL15: + 229 .L18: + 199:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 230 .loc 1 199 1 view .LVU71 + 231 0020 02B0 add sp, sp, #8 + 232 .LCFI5: + 233 .cfi_remember_state + 234 .cfi_def_cfa_offset 8 + 235 @ sp needed + 236 0022 10BD pop {r4, pc} + 237 .LVL16: + 238 .L19: + 239 .LCFI6: + 240 .cfi_restore_state + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 241 .loc 1 184 12 view .LVU72 + 242 0024 0320 movs r0, #3 + 243 .LVL17: + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 244 .loc 1 184 12 view .LVU73 + 245 0026 FBE7 b .L18 + 246 .cfi_endproc + 247 .LFE147: + 249 .section .text.USBD_Start,"ax",%progbits + 250 .align 1 + 251 .global USBD_Start + 252 .syntax unified + 253 .thumb + 254 .thumb_func + ARM GAS /tmp/cc0ngCj0.s page 9 + + + 255 .fpu fpv5-d16 + 257 USBD_Start: + 258 .LVL18: + 259 .LFB148: + 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 202:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_Start + 203:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Start the USB Device Core. + 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: Device Handle + 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval USBD Status + 206:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 207:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) + 208:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 260 .loc 1 208 1 is_stmt 1 view -0 + 261 .cfi_startproc + 262 @ args = 0, pretend = 0, frame = 0 + 263 @ frame_needed = 0, uses_anonymous_args = 0 + 264 .loc 1 208 1 is_stmt 0 view .LVU75 + 265 0000 08B5 push {r3, lr} + 266 .LCFI7: + 267 .cfi_def_cfa_offset 8 + 268 .cfi_offset 3, -8 + 269 .cfi_offset 14, -4 + 209:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Start the low level driver */ + 210:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_LL_Start(pdev); + 270 .loc 1 210 3 is_stmt 1 view .LVU76 + 271 .loc 1 210 10 is_stmt 0 view .LVU77 + 272 0002 FFF7FEFF bl USBD_LL_Start + 273 .LVL19: + 211:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 274 .loc 1 211 1 view .LVU78 + 275 0006 08BD pop {r3, pc} + 276 .cfi_endproc + 277 .LFE148: + 279 .section .text.USBD_Stop,"ax",%progbits + 280 .align 1 + 281 .global USBD_Stop + 282 .syntax unified + 283 .thumb + 284 .thumb_func + 285 .fpu fpv5-d16 + 287 USBD_Stop: + 288 .LVL20: + 289 .LFB149: + 212:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 213:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 214:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_Stop + 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Stop the USB Device Core. + 216:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: Device Handle + 217:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval USBD Status + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) + 220:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 290 .loc 1 220 1 is_stmt 1 view -0 + 291 .cfi_startproc + 292 @ args = 0, pretend = 0, frame = 0 + 293 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc0ngCj0.s page 10 + + + 294 .loc 1 220 1 is_stmt 0 view .LVU80 + 295 0000 10B5 push {r4, lr} + 296 .LCFI8: + 297 .cfi_def_cfa_offset 8 + 298 .cfi_offset 4, -8 + 299 .cfi_offset 14, -4 + 300 0002 0446 mov r4, r0 + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 301 .loc 1 221 3 is_stmt 1 view .LVU81 + 222:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 223:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Free Class Resources */ + 224:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass != NULL) + 302 .loc 1 224 3 view .LVU82 + 303 .loc 1 224 11 is_stmt 0 view .LVU83 + 304 0004 D0F8B832 ldr r3, [r0, #696] + 305 .loc 1 224 6 view .LVU84 + 306 0008 13B1 cbz r3, .L24 + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 226:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + 307 .loc 1 226 5 is_stmt 1 view .LVU85 + 308 .loc 1 226 17 is_stmt 0 view .LVU86 + 309 000a 5B68 ldr r3, [r3, #4] + 310 .loc 1 226 5 view .LVU87 + 311 000c 0179 ldrb r1, [r0, #4] @ zero_extendqisi2 + 312 000e 9847 blx r3 + 313 .LVL21: + 314 .L24: + 227:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 228:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pConfDesc != NULL) + 315 .loc 1 229 3 is_stmt 1 view .LVU88 + 316 .loc 1 229 11 is_stmt 0 view .LVU89 + 317 0010 D4F8CC32 ldr r3, [r4, #716] + 318 .loc 1 229 6 view .LVU90 + 319 0014 13B1 cbz r3, .L25 + 230:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 231:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pConfDesc = NULL; + 320 .loc 1 231 5 is_stmt 1 view .LVU91 + 321 .loc 1 231 21 is_stmt 0 view .LVU92 + 322 0016 0023 movs r3, #0 + 323 0018 C4F8CC32 str r3, [r4, #716] + 324 .L25: + 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 233:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 234:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Stop the low level driver */ + 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_LL_Stop(pdev); + 325 .loc 1 235 3 is_stmt 1 view .LVU93 + 326 .loc 1 235 9 is_stmt 0 view .LVU94 + 327 001c 2046 mov r0, r4 + 328 001e FFF7FEFF bl USBD_LL_Stop + 329 .LVL22: + 236:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 330 .loc 1 237 3 is_stmt 1 view .LVU95 + 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 331 .loc 1 238 1 is_stmt 0 view .LVU96 + 332 0022 10BD pop {r4, pc} + ARM GAS /tmp/cc0ngCj0.s page 11 + + + 333 .loc 1 238 1 view .LVU97 + 334 .cfi_endproc + 335 .LFE149: + 337 .section .text.USBD_RunTestMode,"ax",%progbits + 338 .align 1 + 339 .global USBD_RunTestMode + 340 .syntax unified + 341 .thumb + 342 .thumb_func + 343 .fpu fpv5-d16 + 345 USBD_RunTestMode: + 346 .LVL23: + 347 .LFB150: + 239:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 240:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 241:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_RunTestMode + 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Launch test mode process + 243:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 244:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 245:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 246:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) + 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 348 .loc 1 247 1 is_stmt 1 view -0 + 349 .cfi_startproc + 350 @ args = 0, pretend = 0, frame = 0 + 351 @ frame_needed = 0, uses_anonymous_args = 0 + 352 @ link register save eliminated. + 248:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Prevent unused argument compilation warning */ + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** UNUSED(pdev); + 353 .loc 1 249 3 view .LVU99 + 250:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 354 .loc 1 251 3 view .LVU100 + 252:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 355 .loc 1 252 1 is_stmt 0 view .LVU101 + 356 0000 0020 movs r0, #0 + 357 .LVL24: + 358 .loc 1 252 1 view .LVU102 + 359 0002 7047 bx lr + 360 .cfi_endproc + 361 .LFE150: + 363 .section .text.USBD_SetClassConfig,"ax",%progbits + 364 .align 1 + 365 .global USBD_SetClassConfig + 366 .syntax unified + 367 .thumb + 368 .thumb_func + 369 .fpu fpv5-d16 + 371 USBD_SetClassConfig: + 372 .LVL25: + 373 .LFB151: + 253:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 255:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_SetClassConfig + 256:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Configure device and start the interface + 257:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 258:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param cfgidx: configuration index + ARM GAS /tmp/cc0ngCj0.s page 12 + + + 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 260:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 261:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 262:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) + 263:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 374 .loc 1 263 1 is_stmt 1 view -0 + 375 .cfi_startproc + 376 @ args = 0, pretend = 0, frame = 0 + 377 @ frame_needed = 0, uses_anonymous_args = 0 + 378 .loc 1 263 1 is_stmt 0 view .LVU104 + 379 0000 08B5 push {r3, lr} + 380 .LCFI9: + 381 .cfi_def_cfa_offset 8 + 382 .cfi_offset 3, -8 + 383 .cfi_offset 14, -4 + 264:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret = USBD_FAIL; + 384 .loc 1 264 3 is_stmt 1 view .LVU105 + 385 .LVL26: + 265:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass != NULL) + 386 .loc 1 266 3 view .LVU106 + 387 .loc 1 266 11 is_stmt 0 view .LVU107 + 388 0002 D0F8B832 ldr r3, [r0, #696] + 389 .loc 1 266 6 view .LVU108 + 390 0006 13B1 cbz r3, .L30 + 267:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 268:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Set configuration and Start the Class */ + 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx); + 391 .loc 1 269 5 is_stmt 1 view .LVU109 + 392 .loc 1 269 43 is_stmt 0 view .LVU110 + 393 0008 1B68 ldr r3, [r3] + 394 .loc 1 269 31 view .LVU111 + 395 000a 9847 blx r3 + 396 .LVL27: + 397 .L29: + 270:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 398 .loc 1 272 3 is_stmt 1 view .LVU112 + 273:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 399 .loc 1 273 1 is_stmt 0 view .LVU113 + 400 000c 08BD pop {r3, pc} + 401 .LVL28: + 402 .L30: + 264:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 403 .loc 1 264 22 view .LVU114 + 404 000e 0320 movs r0, #3 + 405 .LVL29: + 264:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 406 .loc 1 264 22 view .LVU115 + 407 0010 FCE7 b .L29 + 408 .cfi_endproc + 409 .LFE151: + 411 .section .text.USBD_ClrClassConfig,"ax",%progbits + 412 .align 1 + 413 .global USBD_ClrClassConfig + 414 .syntax unified + ARM GAS /tmp/cc0ngCj0.s page 13 + + + 415 .thumb + 416 .thumb_func + 417 .fpu fpv5-d16 + 419 USBD_ClrClassConfig: + 420 .LVL30: + 421 .LFB152: + 274:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 275:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_ClrClassConfig + 277:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Clear current configuration + 278:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 279:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param cfgidx: configuration index + 280:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status: USBD_StatusTypeDef + 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 282:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) + 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 422 .loc 1 283 1 is_stmt 1 view -0 + 423 .cfi_startproc + 424 @ args = 0, pretend = 0, frame = 0 + 425 @ frame_needed = 0, uses_anonymous_args = 0 + 426 .loc 1 283 1 is_stmt 0 view .LVU117 + 427 0000 08B5 push {r3, lr} + 428 .LCFI10: + 429 .cfi_def_cfa_offset 8 + 430 .cfi_offset 3, -8 + 431 .cfi_offset 14, -4 + 284:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Clear configuration and De-initialize the Class process */ + 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass != NULL) + 432 .loc 1 285 3 is_stmt 1 view .LVU118 + 433 .loc 1 285 11 is_stmt 0 view .LVU119 + 434 0002 D0F8B832 ldr r3, [r0, #696] + 435 .loc 1 285 6 view .LVU120 + 436 0006 0BB1 cbz r3, .L33 + 286:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->DeInit(pdev, cfgidx); + 437 .loc 1 287 5 is_stmt 1 view .LVU121 + 438 .loc 1 287 17 is_stmt 0 view .LVU122 + 439 0008 5B68 ldr r3, [r3, #4] + 440 .loc 1 287 5 view .LVU123 + 441 000a 9847 blx r3 + 442 .LVL31: + 443 .L33: + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 289:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 290:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 444 .loc 1 290 3 is_stmt 1 view .LVU124 + 291:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 445 .loc 1 291 1 is_stmt 0 view .LVU125 + 446 000c 0020 movs r0, #0 + 447 000e 08BD pop {r3, pc} + 448 .cfi_endproc + 449 .LFE152: + 451 .section .text.USBD_LL_SetupStage,"ax",%progbits + 452 .align 1 + 453 .global USBD_LL_SetupStage + 454 .syntax unified + 455 .thumb + ARM GAS /tmp/cc0ngCj0.s page 14 + + + 456 .thumb_func + 457 .fpu fpv5-d16 + 459 USBD_LL_SetupStage: + 460 .LVL32: + 461 .LFB153: + 292:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 294:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 295:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_SetupStage + 296:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle the setup stage + 297:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 298:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 300:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) + 301:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 462 .loc 1 301 1 is_stmt 1 view -0 + 463 .cfi_startproc + 464 @ args = 0, pretend = 0, frame = 0 + 465 @ frame_needed = 0, uses_anonymous_args = 0 + 466 .loc 1 301 1 is_stmt 0 view .LVU127 + 467 0000 38B5 push {r3, r4, r5, lr} + 468 .LCFI11: + 469 .cfi_def_cfa_offset 16 + 470 .cfi_offset 3, -16 + 471 .cfi_offset 4, -12 + 472 .cfi_offset 5, -8 + 473 .cfi_offset 14, -4 + 474 0002 0446 mov r4, r0 + 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 475 .loc 1 302 3 is_stmt 1 view .LVU128 + 303:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 304:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_ParseSetupRequest(&pdev->request, psetup); + 476 .loc 1 304 3 view .LVU129 + 477 0004 00F2AA25 addw r5, r0, #682 + 478 0008 2846 mov r0, r5 + 479 .LVL33: + 480 .loc 1 304 3 is_stmt 0 view .LVU130 + 481 000a FFF7FEFF bl USBD_ParseSetupRequest + 482 .LVL34: + 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 306:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_state = USBD_EP0_SETUP; + 483 .loc 1 306 3 is_stmt 1 view .LVU131 + 484 .loc 1 306 19 is_stmt 0 view .LVU132 + 485 000e 0123 movs r3, #1 + 486 0010 C4F89432 str r3, [r4, #660] + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 308:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_data_len = pdev->request.wLength; + 487 .loc 1 308 3 is_stmt 1 view .LVU133 + 488 .loc 1 308 37 is_stmt 0 view .LVU134 + 489 0014 B4F8B032 ldrh r3, [r4, #688] + 490 .loc 1 308 22 view .LVU135 + 491 0018 C4F89832 str r3, [r4, #664] + 309:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** switch (pdev->request.bmRequest & 0x1FU) + 492 .loc 1 310 3 is_stmt 1 view .LVU136 + 493 .loc 1 310 24 is_stmt 0 view .LVU137 + 494 001c 94F8AA12 ldrb r1, [r4, #682] @ zero_extendqisi2 + ARM GAS /tmp/cc0ngCj0.s page 15 + + + 495 0020 01F01F03 and r3, r1, #31 + 496 .loc 1 310 3 view .LVU138 + 497 0024 012B cmp r3, #1 + 498 0026 0DD0 beq .L36 + 499 0028 022B cmp r3, #2 + 500 002a 10D0 beq .L37 + 501 002c 2BB1 cbz r3, .L41 + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** case USB_REQ_RECIPIENT_DEVICE: + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_StdDevReq(pdev, &pdev->request); + 314:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** case USB_REQ_RECIPIENT_INTERFACE: + 317:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_StdItfReq(pdev, &pdev->request); + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 319:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 320:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** case USB_REQ_RECIPIENT_ENDPOINT: + 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_StdEPReq(pdev, &pdev->request); + 322:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 323:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 324:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** default: + 325:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); + 502 .loc 1 325 7 is_stmt 1 view .LVU139 + 503 .loc 1 325 13 is_stmt 0 view .LVU140 + 504 002e 01F08001 and r1, r1, #128 + 505 0032 2046 mov r0, r4 + 506 0034 FFF7FEFF bl USBD_LL_StallEP + 507 .LVL35: + 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 508 .loc 1 326 7 is_stmt 1 view .LVU141 + 509 0038 03E0 b .L39 + 510 .LVL36: + 511 .L41: + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 512 .loc 1 313 7 view .LVU142 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 513 .loc 1 313 13 is_stmt 0 view .LVU143 + 514 003a 2946 mov r1, r5 + 515 003c 2046 mov r0, r4 + 516 003e FFF7FEFF bl USBD_StdDevReq + 517 .LVL37: + 314:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 518 .loc 1 314 7 is_stmt 1 view .LVU144 + 519 .L39: + 327:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 328:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 520 .loc 1 329 3 view .LVU145 + 330:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 521 .loc 1 330 1 is_stmt 0 view .LVU146 + 522 0042 38BD pop {r3, r4, r5, pc} + 523 .LVL38: + 524 .L36: + 317:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 525 .loc 1 317 7 is_stmt 1 view .LVU147 + 317:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 526 .loc 1 317 13 is_stmt 0 view .LVU148 + ARM GAS /tmp/cc0ngCj0.s page 16 + + + 527 0044 2946 mov r1, r5 + 528 0046 2046 mov r0, r4 + 529 0048 FFF7FEFF bl USBD_StdItfReq + 530 .LVL39: + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 531 .loc 1 318 7 is_stmt 1 view .LVU149 + 532 004c F9E7 b .L39 + 533 .LVL40: + 534 .L37: + 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 535 .loc 1 321 7 view .LVU150 + 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** break; + 536 .loc 1 321 13 is_stmt 0 view .LVU151 + 537 004e 2946 mov r1, r5 + 538 0050 2046 mov r0, r4 + 539 0052 FFF7FEFF bl USBD_StdEPReq + 540 .LVL41: + 322:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 541 .loc 1 322 7 is_stmt 1 view .LVU152 + 542 0056 F4E7 b .L39 + 543 .cfi_endproc + 544 .LFE153: + 546 .section .text.USBD_LL_DataOutStage,"ax",%progbits + 547 .align 1 + 548 .global USBD_LL_DataOutStage + 549 .syntax unified + 550 .thumb + 551 .thumb_func + 552 .fpu fpv5-d16 + 554 USBD_LL_DataOutStage: + 555 .LVL42: + 556 .LFB154: + 331:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 332:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_DataOutStage + 334:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle data OUT stage + 335:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param epnum: endpoint index + 337:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 339:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, + 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** uint8_t epnum, uint8_t *pdata) + 341:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 557 .loc 1 341 1 view -0 + 558 .cfi_startproc + 559 @ args = 0, pretend = 0, frame = 0 + 560 @ frame_needed = 0, uses_anonymous_args = 0 + 561 .loc 1 341 1 is_stmt 0 view .LVU154 + 562 0000 38B5 push {r3, r4, r5, lr} + 563 .LCFI12: + 564 .cfi_def_cfa_offset 16 + 565 .cfi_offset 3, -16 + 566 .cfi_offset 4, -12 + 567 .cfi_offset 5, -8 + 568 .cfi_offset 14, -4 + 569 0002 0446 mov r4, r0 + 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_EndpointTypeDef *pep; + ARM GAS /tmp/cc0ngCj0.s page 17 + + + 570 .loc 1 342 3 is_stmt 1 view .LVU155 + 343:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 571 .loc 1 343 3 view .LVU156 + 344:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 345:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (epnum == 0U) + 572 .loc 1 345 3 view .LVU157 + 573 .loc 1 345 6 is_stmt 0 view .LVU158 + 574 0004 0D46 mov r5, r1 + 575 0006 31BB cbnz r1, .L43 + 576 0008 1346 mov r3, r2 + 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 347:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pep = &pdev->ep_out[0]; + 577 .loc 1 347 5 is_stmt 1 view .LVU159 + 578 .LVL43: + 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->ep0_state == USBD_EP0_DATA_OUT) + 579 .loc 1 349 5 view .LVU160 + 580 .loc 1 349 13 is_stmt 0 view .LVU161 + 581 000a D0F89422 ldr r2, [r0, #660] + 582 .LVL44: + 583 .loc 1 349 8 view .LVU162 + 584 000e 032A cmp r2, #3 + 585 0010 01D0 beq .L51 + 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pep->rem_length > pep->maxpacket) + 352:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pep->rem_length -= pep->maxpacket; + 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 355:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); + 356:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 357:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 358:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if ((pdev->pClass->EP0_RxReady != NULL) && + 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 361:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 362:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->EP0_RxReady(pdev); + 363:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 364:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlSendStatus(pdev); + 365:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 367:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 368:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 369:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if 0 + 370:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->ep0_state == USBD_EP0_STATUS_OUT) + 371:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 372:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* + 373:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * STATUS PHASE completed, update ep0_state to idle + 374:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_state = USBD_EP0_IDLE; + 376:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_StallEP(pdev, 0U); + 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 378:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif + 379:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 380:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else if ((pdev->pClass->DataOut != NULL) && + 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 383:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + ARM GAS /tmp/cc0ngCj0.s page 18 + + + 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum); + 385:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (ret != USBD_OK) + 387:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 388:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 391:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 393:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* should never be in this condition */ + 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_FAIL; + 395:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 396:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 586 .loc 1 397 10 view .LVU163 + 587 0012 0846 mov r0, r1 + 588 .LVL45: + 589 .L44: + 398:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 590 .loc 1 398 1 view .LVU164 + 591 0014 38BD pop {r3, r4, r5, pc} + 592 .LVL46: + 593 .L51: + 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 594 .loc 1 351 7 is_stmt 1 view .LVU165 + 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 595 .loc 1 351 14 is_stmt 0 view .LVU166 + 596 0016 D0F85C11 ldr r1, [r0, #348] + 597 .LVL47: + 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 598 .loc 1 351 32 view .LVU167 + 599 001a D0F86021 ldr r2, [r0, #352] + 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 600 .loc 1 351 10 view .LVU168 + 601 001e 9142 cmp r1, r2 + 602 0020 0CD8 bhi .L52 + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 603 .loc 1 359 9 is_stmt 1 view .LVU169 + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 604 .loc 1 359 18 is_stmt 0 view .LVU170 + 605 0022 D0F8B832 ldr r3, [r0, #696] + 606 .LVL48: + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 607 .loc 1 359 26 view .LVU171 + 608 0026 1B69 ldr r3, [r3, #16] + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 609 .loc 1 359 12 view .LVU172 + 610 0028 1BB1 cbz r3, .L46 + 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 611 .loc 1 360 18 discriminator 1 view .LVU173 + 612 002a 90F89C22 ldrb r2, [r0, #668] @ zero_extendqisi2 + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 613 .loc 1 359 49 discriminator 1 view .LVU174 + 614 002e 032A cmp r2, #3 + 615 0030 0FD0 beq .L53 + 616 .LVL49: + 617 .L46: + ARM GAS /tmp/cc0ngCj0.s page 19 + + + 364:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 618 .loc 1 364 9 is_stmt 1 view .LVU175 + 364:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 619 .loc 1 364 15 is_stmt 0 view .LVU176 + 620 0032 2046 mov r0, r4 + 621 0034 FFF7FEFF bl USBD_CtlSendStatus + 622 .LVL50: + 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 623 .loc 1 397 10 view .LVU177 + 624 0038 2846 mov r0, r5 + 625 003a EBE7 b .L44 + 626 .LVL51: + 627 .L52: + 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 628 .loc 1 353 9 is_stmt 1 view .LVU178 + 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 629 .loc 1 353 25 is_stmt 0 view .LVU179 + 630 003c 891A subs r1, r1, r2 + 631 003e C0F85C11 str r1, [r0, #348] + 355:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 632 .loc 1 355 9 is_stmt 1 view .LVU180 + 355:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 633 .loc 1 355 15 is_stmt 0 view .LVU181 + 634 0042 8A42 cmp r2, r1 + 635 0044 28BF it cs + 636 0046 0A46 movcs r2, r1 + 637 0048 1946 mov r1, r3 + 638 004a FFF7FEFF bl USBD_CtlContinueRx + 639 .LVL52: + 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 640 .loc 1 397 10 view .LVU182 + 641 004e 2846 mov r0, r5 + 642 0050 E0E7 b .L44 + 643 .LVL53: + 644 .L53: + 362:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 645 .loc 1 362 11 is_stmt 1 view .LVU183 + 646 0052 9847 blx r3 + 647 .LVL54: + 362:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 648 .loc 1 362 11 is_stmt 0 view .LVU184 + 649 0054 EDE7 b .L46 + 650 .LVL55: + 651 .L43: + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 652 .loc 1 381 8 is_stmt 1 view .LVU185 + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 653 .loc 1 381 17 is_stmt 0 view .LVU186 + 654 0056 D0F8B832 ldr r3, [r0, #696] + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 655 .loc 1 381 25 view .LVU187 + 656 005a 9B69 ldr r3, [r3, #24] + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 657 .loc 1 381 11 view .LVU188 + 658 005c 2BB1 cbz r3, .L48 + 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 659 .loc 1 382 17 discriminator 1 view .LVU189 + ARM GAS /tmp/cc0ngCj0.s page 20 + + + 660 005e 90F89C22 ldrb r2, [r0, #668] @ zero_extendqisi2 + 661 .LVL56: + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 662 .loc 1 381 44 discriminator 1 view .LVU190 + 663 0062 032A cmp r2, #3 + 664 0064 03D1 bne .L49 + 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 665 .loc 1 384 5 is_stmt 1 view .LVU191 + 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 666 .loc 1 384 31 is_stmt 0 view .LVU192 + 667 0066 9847 blx r3 + 668 .LVL57: + 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 669 .loc 1 386 5 is_stmt 1 view .LVU193 + 670 0068 D4E7 b .L44 + 671 .LVL58: + 672 .L48: + 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 673 .loc 1 394 12 is_stmt 0 view .LVU194 + 674 006a 0320 movs r0, #3 + 675 .LVL59: + 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 676 .loc 1 394 12 view .LVU195 + 677 006c D2E7 b .L44 + 678 .LVL60: + 679 .L49: + 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 680 .loc 1 394 12 view .LVU196 + 681 006e 0320 movs r0, #3 + 682 .LVL61: + 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 683 .loc 1 394 12 view .LVU197 + 684 0070 D0E7 b .L44 + 685 .cfi_endproc + 686 .LFE154: + 688 .section .text.USBD_LL_DataInStage,"ax",%progbits + 689 .align 1 + 690 .global USBD_LL_DataInStage + 691 .syntax unified + 692 .thumb + 693 .thumb_func + 694 .fpu fpv5-d16 + 696 USBD_LL_DataInStage: + 697 .LVL62: + 698 .LFB155: + 399:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 400:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 401:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_DataInStage + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle data in stage + 403:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 404:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param epnum: endpoint index + 405:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 407:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** uint8_t epnum, uint8_t *pdata) + 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 699 .loc 1 409 1 is_stmt 1 view -0 + ARM GAS /tmp/cc0ngCj0.s page 21 + + + 700 .cfi_startproc + 701 @ args = 0, pretend = 0, frame = 0 + 702 @ frame_needed = 0, uses_anonymous_args = 0 + 703 .loc 1 409 1 is_stmt 0 view .LVU199 + 704 0000 38B5 push {r3, r4, r5, lr} + 705 .LCFI13: + 706 .cfi_def_cfa_offset 16 + 707 .cfi_offset 3, -16 + 708 .cfi_offset 4, -12 + 709 .cfi_offset 5, -8 + 710 .cfi_offset 14, -4 + 711 0002 0446 mov r4, r0 + 410:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_EndpointTypeDef *pep; + 712 .loc 1 410 3 is_stmt 1 view .LVU200 + 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef ret; + 713 .loc 1 411 3 view .LVU201 + 412:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (epnum == 0U) + 714 .loc 1 413 3 view .LVU202 + 715 .loc 1 413 6 is_stmt 0 view .LVU203 + 716 0004 0D46 mov r5, r1 + 717 0006 0029 cmp r1, #0 + 718 0008 48D1 bne .L55 + 719 000a 1346 mov r3, r2 + 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 415:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pep = &pdev->ep_in[0]; + 720 .loc 1 415 5 is_stmt 1 view .LVU204 + 721 .LVL63: + 416:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 417:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->ep0_state == USBD_EP0_DATA_IN) + 722 .loc 1 417 5 view .LVU205 + 723 .loc 1 417 13 is_stmt 0 view .LVU206 + 724 000c D0F89422 ldr r2, [r0, #660] + 725 .LVL64: + 726 .loc 1 417 8 view .LVU207 + 727 0010 022A cmp r2, #2 + 728 0012 05D0 beq .L65 + 729 .LVL65: + 730 .L56: + 418:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pep->rem_length > pep->maxpacket) + 420:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 421:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pep->rem_length -= pep->maxpacket; + 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); + 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 425:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Prepare endpoint for premature end of transfer */ + 426:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + 427:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 429:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 430:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* last packet is MPS multiple, so send ZLP packet */ + 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if ((pep->maxpacket == pep->rem_length) && + 432:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length >= pep->maxpacket) && + 433:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length < pdev->ep0_data_len)) + 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlContinueSendData(pdev, NULL, 0U); + ARM GAS /tmp/cc0ngCj0.s page 22 + + + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_data_len = 0U; + 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 438:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Prepare endpoint for premature end of transfer */ + 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + 440:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 441:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 442:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if ((pdev->pClass->EP0_TxSent != NULL) && + 444:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 445:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->EP0_TxSent(pdev); + 447:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 449:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlReceiveStatus(pdev); + 450:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 451:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 452:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 453:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 454:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 455:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #if 0 + 456:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || + 457:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->ep0_state == USBD_EP0_IDLE)) + 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 459:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 461:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** #endif + 462:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 731 .loc 1 462 5 is_stmt 1 view .LVU208 + 463:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 464:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->dev_test_mode == 1U) + 732 .loc 1 464 5 view .LVU209 + 733 .loc 1 464 13 is_stmt 0 view .LVU210 + 734 0014 94F8A032 ldrb r3, [r4, #672] @ zero_extendqisi2 + 735 .loc 1 464 8 view .LVU211 + 736 0018 012B cmp r3, #1 + 737 001a 3AD0 beq .L66 + 465:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_RunTestMode(pdev); + 467:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_test_mode = 0U; + 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 469:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else if ((pdev->pClass->DataIn != NULL) && + 471:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 473:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum); + 474:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 475:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (ret != USBD_OK) + 476:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 477:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return ret; + 478:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 479:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** else + 481:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* should never be in this condition */ + 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_FAIL; + 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 485:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + ARM GAS /tmp/cc0ngCj0.s page 23 + + + 486:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 738 .loc 1 486 10 view .LVU212 + 739 001c 2846 mov r0, r5 + 740 .LVL66: + 741 .L60: + 487:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 742 .loc 1 487 1 view .LVU213 + 743 001e 38BD pop {r3, r4, r5, pc} + 744 .LVL67: + 745 .L65: + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 746 .loc 1 419 7 is_stmt 1 view .LVU214 + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 747 .loc 1 419 14 is_stmt 0 view .LVU215 + 748 0020 C269 ldr r2, [r0, #28] + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 749 .loc 1 419 32 view .LVU216 + 750 0022 016A ldr r1, [r0, #32] + 751 .LVL68: + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 752 .loc 1 419 10 view .LVU217 + 753 0024 8A42 cmp r2, r1 + 754 0026 11D8 bhi .L67 + 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length >= pep->maxpacket) && + 755 .loc 1 431 9 is_stmt 1 view .LVU218 + 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length >= pep->maxpacket) && + 756 .loc 1 431 12 is_stmt 0 view .LVU219 + 757 0028 8A42 cmp r2, r1 + 758 002a 1BD0 beq .L68 + 759 .LVL69: + 760 .L58: + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 761 .loc 1 443 11 is_stmt 1 view .LVU220 + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 762 .loc 1 443 20 is_stmt 0 view .LVU221 + 763 002c D4F8B832 ldr r3, [r4, #696] + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 764 .loc 1 443 28 view .LVU222 + 765 0030 DB68 ldr r3, [r3, #12] + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 766 .loc 1 443 14 view .LVU223 + 767 0032 1BB1 cbz r3, .L59 + 444:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 768 .loc 1 444 20 discriminator 1 view .LVU224 + 769 0034 94F89C22 ldrb r2, [r4, #668] @ zero_extendqisi2 + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 770 .loc 1 443 50 discriminator 1 view .LVU225 + 771 0038 032A cmp r2, #3 + 772 003a 27D0 beq .L69 + 773 .LVL70: + 774 .L59: + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlReceiveStatus(pdev); + 775 .loc 1 448 11 is_stmt 1 view .LVU226 + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_CtlReceiveStatus(pdev); + 776 .loc 1 448 17 is_stmt 0 view .LVU227 + 777 003c 8021 movs r1, #128 + 778 003e 2046 mov r0, r4 + ARM GAS /tmp/cc0ngCj0.s page 24 + + + 779 0040 FFF7FEFF bl USBD_LL_StallEP + 780 .LVL71: + 449:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 781 .loc 1 449 11 is_stmt 1 view .LVU228 + 449:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 782 .loc 1 449 17 is_stmt 0 view .LVU229 + 783 0044 2046 mov r0, r4 + 784 0046 FFF7FEFF bl USBD_CtlReceiveStatus + 785 .LVL72: + 786 004a E3E7 b .L56 + 787 .LVL73: + 788 .L67: + 421:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 789 .loc 1 421 9 is_stmt 1 view .LVU230 + 421:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 790 .loc 1 421 25 is_stmt 0 view .LVU231 + 791 004c 521A subs r2, r2, r1 + 792 004e C261 str r2, [r0, #28] + 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 793 .loc 1 423 9 is_stmt 1 view .LVU232 + 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 794 .loc 1 423 15 is_stmt 0 view .LVU233 + 795 0050 1946 mov r1, r3 + 796 0052 FFF7FEFF bl USBD_CtlContinueSendData + 797 .LVL74: + 426:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 798 .loc 1 426 8 is_stmt 1 view .LVU234 + 426:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 799 .loc 1 426 14 is_stmt 0 view .LVU235 + 800 0056 0023 movs r3, #0 + 801 0058 1A46 mov r2, r3 + 802 005a 1946 mov r1, r3 + 803 005c 2046 mov r0, r4 + 804 005e FFF7FEFF bl USBD_LL_PrepareReceive + 805 .LVL75: + 806 0062 D7E7 b .L56 + 807 .LVL76: + 808 .L68: + 432:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length < pdev->ep0_data_len)) + 809 .loc 1 432 17 discriminator 1 view .LVU236 + 810 0064 8369 ldr r3, [r0, #24] + 811 .LVL77: + 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length >= pep->maxpacket) && + 812 .loc 1 431 49 discriminator 1 view .LVU237 + 813 0066 9942 cmp r1, r3 + 814 0068 E0D8 bhi .L58 + 433:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 815 .loc 1 433 38 view .LVU238 + 816 006a D0F89822 ldr r2, [r0, #664] + 432:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pep->total_length < pdev->ep0_data_len)) + 817 .loc 1 432 51 view .LVU239 + 818 006e 9342 cmp r3, r2 + 819 0070 DCD2 bcs .L58 + 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_data_len = 0U; + 820 .loc 1 435 11 is_stmt 1 view .LVU240 + 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_data_len = 0U; + 821 .loc 1 435 17 is_stmt 0 view .LVU241 + ARM GAS /tmp/cc0ngCj0.s page 25 + + + 822 0072 0022 movs r2, #0 + 823 0074 1146 mov r1, r2 + 824 0076 FFF7FEFF bl USBD_CtlContinueSendData + 825 .LVL78: + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 826 .loc 1 436 11 is_stmt 1 view .LVU242 + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 827 .loc 1 436 30 is_stmt 0 view .LVU243 + 828 007a 0021 movs r1, #0 + 829 007c C4F89812 str r1, [r4, #664] + 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 830 .loc 1 439 11 is_stmt 1 view .LVU244 + 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 831 .loc 1 439 17 is_stmt 0 view .LVU245 + 832 0080 0B46 mov r3, r1 + 833 0082 0A46 mov r2, r1 + 834 0084 2046 mov r0, r4 + 835 0086 FFF7FEFF bl USBD_LL_PrepareReceive + 836 .LVL79: + 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 837 .loc 1 439 11 view .LVU246 + 838 008a C3E7 b .L56 + 839 .LVL80: + 840 .L69: + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 841 .loc 1 446 13 is_stmt 1 view .LVU247 + 842 008c 2046 mov r0, r4 + 843 .LVL81: + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 844 .loc 1 446 13 is_stmt 0 view .LVU248 + 845 008e 9847 blx r3 + 846 .LVL82: + 847 0090 D4E7 b .L59 + 848 .L66: + 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_test_mode = 0U; + 849 .loc 1 466 7 is_stmt 1 view .LVU249 + 467:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 850 .loc 1 467 7 view .LVU250 + 467:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 851 .loc 1 467 27 is_stmt 0 view .LVU251 + 852 0092 0023 movs r3, #0 + 853 0094 84F8A032 strb r3, [r4, #672] + 486:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 854 .loc 1 486 10 view .LVU252 + 855 0098 2846 mov r0, r5 + 856 009a C0E7 b .L60 + 857 .LVL83: + 858 .L55: + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 859 .loc 1 470 8 is_stmt 1 view .LVU253 + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 860 .loc 1 470 17 is_stmt 0 view .LVU254 + 861 009c D0F8B832 ldr r3, [r0, #696] + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 862 .loc 1 470 25 view .LVU255 + 863 00a0 5B69 ldr r3, [r3, #20] + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + ARM GAS /tmp/cc0ngCj0.s page 26 + + + 864 .loc 1 470 11 view .LVU256 + 865 00a2 2BB1 cbz r3, .L62 + 471:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 866 .loc 1 471 17 discriminator 1 view .LVU257 + 867 00a4 90F89C22 ldrb r2, [r0, #668] @ zero_extendqisi2 + 868 .LVL84: + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (pdev->dev_state == USBD_STATE_CONFIGURED)) + 869 .loc 1 470 43 discriminator 1 view .LVU258 + 870 00a8 032A cmp r2, #3 + 871 00aa 03D1 bne .L63 + 473:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 872 .loc 1 473 5 is_stmt 1 view .LVU259 + 473:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 873 .loc 1 473 31 is_stmt 0 view .LVU260 + 874 00ac 9847 blx r3 + 875 .LVL85: + 475:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 876 .loc 1 475 5 is_stmt 1 view .LVU261 + 877 00ae B6E7 b .L60 + 878 .LVL86: + 879 .L62: + 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 880 .loc 1 483 12 is_stmt 0 view .LVU262 + 881 00b0 0320 movs r0, #3 + 882 .LVL87: + 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 883 .loc 1 483 12 view .LVU263 + 884 00b2 B4E7 b .L60 + 885 .LVL88: + 886 .L63: + 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 887 .loc 1 483 12 view .LVU264 + 888 00b4 0320 movs r0, #3 + 889 .LVL89: + 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 890 .loc 1 483 12 view .LVU265 + 891 00b6 B2E7 b .L60 + 892 .cfi_endproc + 893 .LFE155: + 895 .section .text.USBD_LL_Reset,"ax",%progbits + 896 .align 1 + 897 .global USBD_LL_Reset + 898 .syntax unified + 899 .thumb + 900 .thumb_func + 901 .fpu fpv5-d16 + 903 USBD_LL_Reset: + 904 .LVL90: + 905 .LFB156: + 488:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 489:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 490:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_LL_Reset + 491:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle Reset event + 492:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 493:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 494:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + ARM GAS /tmp/cc0ngCj0.s page 27 + + + 496:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) + 497:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 906 .loc 1 497 1 is_stmt 1 view -0 + 907 .cfi_startproc + 908 @ args = 0, pretend = 0, frame = 0 + 909 @ frame_needed = 0, uses_anonymous_args = 0 + 910 .loc 1 497 1 is_stmt 0 view .LVU267 + 911 0000 70B5 push {r4, r5, r6, lr} + 912 .LCFI14: + 913 .cfi_def_cfa_offset 16 + 914 .cfi_offset 4, -16 + 915 .cfi_offset 5, -12 + 916 .cfi_offset 6, -8 + 917 .cfi_offset 14, -4 + 918 0002 0446 mov r4, r0 + 498:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Upon Reset call user call back */ + 499:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_state = USBD_STATE_DEFAULT; + 919 .loc 1 499 3 is_stmt 1 view .LVU268 + 920 .loc 1 499 19 is_stmt 0 view .LVU269 + 921 0004 0123 movs r3, #1 + 922 0006 80F89C32 strb r3, [r0, #668] + 500:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep0_state = USBD_EP0_IDLE; + 923 .loc 1 500 3 is_stmt 1 view .LVU270 + 924 .loc 1 500 19 is_stmt 0 view .LVU271 + 925 000a 0023 movs r3, #0 + 926 000c C0F89432 str r3, [r0, #660] + 501:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_config = 0U; + 927 .loc 1 501 3 is_stmt 1 view .LVU272 + 928 .loc 1 501 20 is_stmt 0 view .LVU273 + 929 0010 4360 str r3, [r0, #4] + 502:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_remote_wakeup = 0U; + 930 .loc 1 502 3 is_stmt 1 view .LVU274 + 931 .loc 1 502 27 is_stmt 0 view .LVU275 + 932 0012 C0F8A432 str r3, [r0, #676] + 503:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 504:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClassData != NULL) + 933 .loc 1 504 3 is_stmt 1 view .LVU276 + 934 .loc 1 504 11 is_stmt 0 view .LVU277 + 935 0016 D0F8BC32 ldr r3, [r0, #700] + 936 .loc 1 504 6 view .LVU278 + 937 001a 23B1 cbz r3, .L71 + 505:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 506:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + 938 .loc 1 506 5 is_stmt 1 view .LVU279 + 939 .loc 1 506 9 is_stmt 0 view .LVU280 + 940 001c D0F8B832 ldr r3, [r0, #696] + 941 .loc 1 506 17 view .LVU281 + 942 0020 5B68 ldr r3, [r3, #4] + 943 .loc 1 506 5 view .LVU282 + 944 0022 0021 movs r1, #0 + 945 0024 9847 blx r3 + 946 .LVL91: + 947 .L71: + 507:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 508:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 509:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Open EP0 OUT */ + 510:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + ARM GAS /tmp/cc0ngCj0.s page 28 + + + 948 .loc 1 510 3 is_stmt 1 view .LVU283 + 949 .loc 1 510 9 is_stmt 0 view .LVU284 + 950 0026 4023 movs r3, #64 + 951 0028 0022 movs r2, #0 + 952 002a 1146 mov r1, r2 + 953 002c 2046 mov r0, r4 + 954 002e FFF7FEFF bl USBD_LL_OpenEP + 955 .LVL92: + 511:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep_out[0x00U & 0xFU].is_used = 1U; + 956 .loc 1 511 3 is_stmt 1 view .LVU285 + 957 .loc 1 511 38 is_stmt 0 view .LVU286 + 958 0032 0126 movs r6, #1 + 959 0034 A4F86461 strh r6, [r4, #356] @ movhi + 512:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 513:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + 960 .loc 1 513 3 is_stmt 1 view .LVU287 + 961 .loc 1 513 29 is_stmt 0 view .LVU288 + 962 0038 4025 movs r5, #64 + 963 003a C4F86051 str r5, [r4, #352] + 514:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 515:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Open EP0 IN */ + 516:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + 964 .loc 1 516 3 is_stmt 1 view .LVU289 + 965 .loc 1 516 9 is_stmt 0 view .LVU290 + 966 003e 2B46 mov r3, r5 + 967 0040 0022 movs r2, #0 + 968 0042 8021 movs r1, #128 + 969 0044 2046 mov r0, r4 + 970 0046 FFF7FEFF bl USBD_LL_OpenEP + 971 .LVL93: + 517:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep_in[0x80U & 0xFU].is_used = 1U; + 972 .loc 1 517 3 is_stmt 1 view .LVU291 + 973 .loc 1 517 37 is_stmt 0 view .LVU292 + 974 004a A684 strh r6, [r4, #36] @ movhi + 518:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 519:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + 975 .loc 1 519 3 is_stmt 1 view .LVU293 + 976 .loc 1 519 28 is_stmt 0 view .LVU294 + 977 004c 2562 str r5, [r4, #32] + 520:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 521:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 978 .loc 1 521 3 is_stmt 1 view .LVU295 + 522:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 979 .loc 1 522 1 is_stmt 0 view .LVU296 + 980 004e 0020 movs r0, #0 + 981 0050 70BD pop {r4, r5, r6, pc} + 982 .loc 1 522 1 view .LVU297 + 983 .cfi_endproc + 984 .LFE156: + 986 .section .text.USBD_LL_SetSpeed,"ax",%progbits + 987 .align 1 + 988 .global USBD_LL_SetSpeed + 989 .syntax unified + 990 .thumb + 991 .thumb_func + 992 .fpu fpv5-d16 + 994 USBD_LL_SetSpeed: + ARM GAS /tmp/cc0ngCj0.s page 29 + + + 995 .LVL94: + 996 .LFB157: + 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 524:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_LL_Reset + 526:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle Reset event + 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 528:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 530:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, + 531:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_SpeedTypeDef speed) + 532:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 997 .loc 1 532 1 is_stmt 1 view -0 + 998 .cfi_startproc + 999 @ args = 0, pretend = 0, frame = 0 + 1000 @ frame_needed = 0, uses_anonymous_args = 0 + 1001 @ link register save eliminated. + 533:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_speed = speed; + 1002 .loc 1 533 3 view .LVU299 + 1003 .loc 1 533 19 is_stmt 0 view .LVU300 + 1004 0000 0174 strb r1, [r0, #16] + 534:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1005 .loc 1 535 3 is_stmt 1 view .LVU301 + 536:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1006 .loc 1 536 1 is_stmt 0 view .LVU302 + 1007 0002 0020 movs r0, #0 + 1008 .LVL95: + 1009 .loc 1 536 1 view .LVU303 + 1010 0004 7047 bx lr + 1011 .cfi_endproc + 1012 .LFE157: + 1014 .section .text.USBD_LL_Suspend,"ax",%progbits + 1015 .align 1 + 1016 .global USBD_LL_Suspend + 1017 .syntax unified + 1018 .thumb + 1019 .thumb_func + 1020 .fpu fpv5-d16 + 1022 USBD_LL_Suspend: + 1023 .LVL96: + 1024 .LFB158: + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 538:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_Suspend + 540:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle Suspend event + 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 543:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 544:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 545:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) + 546:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1025 .loc 1 546 1 is_stmt 1 view -0 + 1026 .cfi_startproc + 1027 @ args = 0, pretend = 0, frame = 0 + 1028 @ frame_needed = 0, uses_anonymous_args = 0 + 1029 @ link register save eliminated. + ARM GAS /tmp/cc0ngCj0.s page 30 + + + 547:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_old_state = pdev->dev_state; + 1030 .loc 1 547 3 view .LVU305 + 1031 .loc 1 547 29 is_stmt 0 view .LVU306 + 1032 0000 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 1033 .loc 1 547 23 view .LVU307 + 1034 0004 80F89D32 strb r3, [r0, #669] + 548:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_state = USBD_STATE_SUSPENDED; + 1035 .loc 1 548 3 is_stmt 1 view .LVU308 + 1036 .loc 1 548 19 is_stmt 0 view .LVU309 + 1037 0008 0423 movs r3, #4 + 1038 000a 80F89C32 strb r3, [r0, #668] + 549:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 550:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1039 .loc 1 550 3 is_stmt 1 view .LVU310 + 551:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1040 .loc 1 551 1 is_stmt 0 view .LVU311 + 1041 000e 0020 movs r0, #0 + 1042 .LVL97: + 1043 .loc 1 551 1 view .LVU312 + 1044 0010 7047 bx lr + 1045 .cfi_endproc + 1046 .LFE158: + 1048 .section .text.USBD_LL_Resume,"ax",%progbits + 1049 .align 1 + 1050 .global USBD_LL_Resume + 1051 .syntax unified + 1052 .thumb + 1053 .thumb_func + 1054 .fpu fpv5-d16 + 1056 USBD_LL_Resume: + 1057 .LVL98: + 1058 .LFB159: + 552:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 554:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_Resume + 555:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle Resume event + 556:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 558:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 560:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) + 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1059 .loc 1 561 1 is_stmt 1 view -0 + 1060 .cfi_startproc + 1061 @ args = 0, pretend = 0, frame = 0 + 1062 @ frame_needed = 0, uses_anonymous_args = 0 + 1063 @ link register save eliminated. + 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->dev_state == USBD_STATE_SUSPENDED) + 1064 .loc 1 562 3 view .LVU314 + 1065 .loc 1 562 11 is_stmt 0 view .LVU315 + 1066 0000 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 1067 .loc 1 562 6 view .LVU316 + 1068 0004 042B cmp r3, #4 + 1069 0006 01D0 beq .L77 + 1070 .L76: + 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_state = pdev->dev_old_state; + ARM GAS /tmp/cc0ngCj0.s page 31 + + + 565:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1071 .loc 1 567 3 is_stmt 1 view .LVU317 + 568:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1072 .loc 1 568 1 is_stmt 0 view .LVU318 + 1073 0008 0020 movs r0, #0 + 1074 .LVL99: + 1075 .loc 1 568 1 view .LVU319 + 1076 000a 7047 bx lr + 1077 .LVL100: + 1078 .L77: + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1079 .loc 1 564 5 is_stmt 1 view .LVU320 + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1080 .loc 1 564 27 is_stmt 0 view .LVU321 + 1081 000c 90F89D32 ldrb r3, [r0, #669] @ zero_extendqisi2 + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1082 .loc 1 564 21 view .LVU322 + 1083 0010 80F89C32 strb r3, [r0, #668] + 1084 0014 F8E7 b .L76 + 1085 .cfi_endproc + 1086 .LFE159: + 1088 .section .text.USBD_LL_SOF,"ax",%progbits + 1089 .align 1 + 1090 .global USBD_LL_SOF + 1091 .syntax unified + 1092 .thumb + 1093 .thumb_func + 1094 .fpu fpv5-d16 + 1096 USBD_LL_SOF: + 1097 .LVL101: + 1098 .LFB160: + 569:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 570:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 571:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_SOF + 572:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle SOF event + 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 574:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 575:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 577:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) + 578:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1099 .loc 1 578 1 is_stmt 1 view -0 + 1100 .cfi_startproc + 1101 @ args = 0, pretend = 0, frame = 0 + 1102 @ frame_needed = 0, uses_anonymous_args = 0 + 1103 .loc 1 578 1 is_stmt 0 view .LVU324 + 1104 0000 08B5 push {r3, lr} + 1105 .LCFI15: + 1106 .cfi_def_cfa_offset 8 + 1107 .cfi_offset 3, -8 + 1108 .cfi_offset 14, -4 + 579:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->dev_state == USBD_STATE_CONFIGURED) + 1109 .loc 1 579 3 is_stmt 1 view .LVU325 + 1110 .loc 1 579 11 is_stmt 0 view .LVU326 + 1111 0002 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + ARM GAS /tmp/cc0ngCj0.s page 32 + + + 1112 .loc 1 579 6 view .LVU327 + 1113 0006 032B cmp r3, #3 + 1114 0008 01D0 beq .L81 + 1115 .LVL102: + 1116 .L79: + 580:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass->SOF != NULL) + 582:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->SOF(pdev); + 584:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 585:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 586:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 587:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1117 .loc 1 587 3 is_stmt 1 view .LVU328 + 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1118 .loc 1 588 1 is_stmt 0 view .LVU329 + 1119 000a 0020 movs r0, #0 + 1120 000c 08BD pop {r3, pc} + 1121 .LVL103: + 1122 .L81: + 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1123 .loc 1 581 5 is_stmt 1 view .LVU330 + 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1124 .loc 1 581 13 is_stmt 0 view .LVU331 + 1125 000e D0F8B832 ldr r3, [r0, #696] + 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1126 .loc 1 581 21 view .LVU332 + 1127 0012 DB69 ldr r3, [r3, #28] + 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1128 .loc 1 581 8 view .LVU333 + 1129 0014 002B cmp r3, #0 + 1130 0016 F8D0 beq .L79 + 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1131 .loc 1 583 7 is_stmt 1 view .LVU334 + 1132 0018 9847 blx r3 + 1133 .LVL104: + 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1134 .loc 1 583 7 is_stmt 0 view .LVU335 + 1135 001a F6E7 b .L79 + 1136 .cfi_endproc + 1137 .LFE160: + 1139 .section .text.USBD_LL_IsoINIncomplete,"ax",%progbits + 1140 .align 1 + 1141 .global USBD_LL_IsoINIncomplete + 1142 .syntax unified + 1143 .thumb + 1144 .thumb_func + 1145 .fpu fpv5-d16 + 1147 USBD_LL_IsoINIncomplete: + 1148 .LVL105: + 1149 .LFB161: + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 591:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_IsoINIncomplete + 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle iso in incomplete event + 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + ARM GAS /tmp/cc0ngCj0.s page 33 + + + 595:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, + 597:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** uint8_t epnum) + 598:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1150 .loc 1 598 1 is_stmt 1 view -0 + 1151 .cfi_startproc + 1152 @ args = 0, pretend = 0, frame = 0 + 1153 @ frame_needed = 0, uses_anonymous_args = 0 + 1154 @ link register save eliminated. + 599:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Prevent unused arguments compilation warning */ + 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** UNUSED(pdev); + 1155 .loc 1 600 3 view .LVU337 + 601:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** UNUSED(epnum); + 1156 .loc 1 601 3 view .LVU338 + 602:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1157 .loc 1 603 3 view .LVU339 + 604:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1158 .loc 1 604 1 is_stmt 0 view .LVU340 + 1159 0000 0020 movs r0, #0 + 1160 .LVL106: + 1161 .loc 1 604 1 view .LVU341 + 1162 0002 7047 bx lr + 1163 .cfi_endproc + 1164 .LFE161: + 1166 .section .text.USBD_LL_IsoOUTIncomplete,"ax",%progbits + 1167 .align 1 + 1168 .global USBD_LL_IsoOUTIncomplete + 1169 .syntax unified + 1170 .thumb + 1171 .thumb_func + 1172 .fpu fpv5-d16 + 1174 USBD_LL_IsoOUTIncomplete: + 1175 .LVL107: + 1176 .LFB162: + 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 606:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 607:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_IsoOUTIncomplete + 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle iso out incomplete event + 609:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 610:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 611:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 612:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, + 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** uint8_t epnum) + 614:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1177 .loc 1 614 1 is_stmt 1 view -0 + 1178 .cfi_startproc + 1179 @ args = 0, pretend = 0, frame = 0 + 1180 @ frame_needed = 0, uses_anonymous_args = 0 + 1181 @ link register save eliminated. + 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Prevent unused arguments compilation warning */ + 616:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** UNUSED(pdev); + 1182 .loc 1 616 3 view .LVU343 + 617:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** UNUSED(epnum); + 1183 .loc 1 617 3 view .LVU344 + 618:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + ARM GAS /tmp/cc0ngCj0.s page 34 + + + 1184 .loc 1 619 3 view .LVU345 + 620:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1185 .loc 1 620 1 is_stmt 0 view .LVU346 + 1186 0000 0020 movs r0, #0 + 1187 .LVL108: + 1188 .loc 1 620 1 view .LVU347 + 1189 0002 7047 bx lr + 1190 .cfi_endproc + 1191 .LFE162: + 1193 .section .text.USBD_LL_DevConnected,"ax",%progbits + 1194 .align 1 + 1195 .global USBD_LL_DevConnected + 1196 .syntax unified + 1197 .thumb + 1198 .thumb_func + 1199 .fpu fpv5-d16 + 1201 USBD_LL_DevConnected: + 1202 .LVL109: + 1203 .LFB163: + 621:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 622:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 623:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_DevConnected + 624:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle device connection event + 625:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 626:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 627:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 628:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) + 629:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1204 .loc 1 629 1 is_stmt 1 view -0 + 1205 .cfi_startproc + 1206 @ args = 0, pretend = 0, frame = 0 + 1207 @ frame_needed = 0, uses_anonymous_args = 0 + 1208 @ link register save eliminated. + 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Prevent unused argument compilation warning */ + 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** UNUSED(pdev); + 1209 .loc 1 631 3 view .LVU349 + 632:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1210 .loc 1 633 3 view .LVU350 + 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1211 .loc 1 634 1 is_stmt 0 view .LVU351 + 1212 0000 0020 movs r0, #0 + 1213 .LVL110: + 1214 .loc 1 634 1 view .LVU352 + 1215 0002 7047 bx lr + 1216 .cfi_endproc + 1217 .LFE163: + 1219 .section .text.USBD_LL_DevDisconnected,"ax",%progbits + 1220 .align 1 + 1221 .global USBD_LL_DevDisconnected + 1222 .syntax unified + 1223 .thumb + 1224 .thumb_func + 1225 .fpu fpv5-d16 + 1227 USBD_LL_DevDisconnected: + 1228 .LVL111: + 1229 .LFB164: + ARM GAS /tmp/cc0ngCj0.s page 35 + + + 635:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /** + 637:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @brief USBD_DevDisconnected + 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * Handle device disconnection event + 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @param pdev: device instance + 640:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** * @retval status + 641:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** */ + 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) + 643:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 1230 .loc 1 643 1 is_stmt 1 view -0 + 1231 .cfi_startproc + 1232 @ args = 0, pretend = 0, frame = 0 + 1233 @ frame_needed = 0, uses_anonymous_args = 0 + 1234 .loc 1 643 1 is_stmt 0 view .LVU354 + 1235 0000 08B5 push {r3, lr} + 1236 .LCFI16: + 1237 .cfi_def_cfa_offset 8 + 1238 .cfi_offset 3, -8 + 1239 .cfi_offset 14, -4 + 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** /* Free Class Resources */ + 645:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->dev_state = USBD_STATE_DEFAULT; + 1240 .loc 1 645 3 is_stmt 1 view .LVU355 + 1241 .loc 1 645 19 is_stmt 0 view .LVU356 + 1242 0002 0123 movs r3, #1 + 1243 0004 80F89C32 strb r3, [r0, #668] + 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 647:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** if (pdev->pClass != NULL) + 1244 .loc 1 647 3 is_stmt 1 view .LVU357 + 1245 .loc 1 647 11 is_stmt 0 view .LVU358 + 1246 0008 D0F8B832 ldr r3, [r0, #696] + 1247 .loc 1 647 6 view .LVU359 + 1248 000c 13B1 cbz r3, .L86 + 648:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** { + 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + 1249 .loc 1 649 5 is_stmt 1 view .LVU360 + 1250 .loc 1 649 17 is_stmt 0 view .LVU361 + 1251 000e 5B68 ldr r3, [r3, #4] + 1252 .loc 1 649 5 view .LVU362 + 1253 0010 0179 ldrb r1, [r0, #4] @ zero_extendqisi2 + 1254 0012 9847 blx r3 + 1255 .LVL112: + 1256 .L86: + 650:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 651:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** + 652:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** return USBD_OK; + 1257 .loc 1 652 3 is_stmt 1 view .LVU363 + 653:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c **** } + 1258 .loc 1 653 1 is_stmt 0 view .LVU364 + 1259 0014 0020 movs r0, #0 + 1260 0016 08BD pop {r3, pc} + 1261 .cfi_endproc + 1262 .LFE164: + 1264 .text + 1265 .Letext0: + 1266 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1267 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1268 .file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + ARM GAS /tmp/cc0ngCj0.s page 36 + + + 1269 .file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h" + 1270 .file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h" + 1271 .file 7 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h" + ARM GAS /tmp/cc0ngCj0.s page 37 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_core.c + /tmp/cc0ngCj0.s:17 .text.USBD_Init:0000000000000000 $t + /tmp/cc0ngCj0.s:25 .text.USBD_Init:0000000000000000 USBD_Init + /tmp/cc0ngCj0.s:104 .text.USBD_DeInit:0000000000000000 $t + /tmp/cc0ngCj0.s:111 .text.USBD_DeInit:0000000000000000 USBD_DeInit + /tmp/cc0ngCj0.s:180 .text.USBD_RegisterClass:0000000000000000 $t + /tmp/cc0ngCj0.s:187 .text.USBD_RegisterClass:0000000000000000 USBD_RegisterClass + /tmp/cc0ngCj0.s:250 .text.USBD_Start:0000000000000000 $t + /tmp/cc0ngCj0.s:257 .text.USBD_Start:0000000000000000 USBD_Start + /tmp/cc0ngCj0.s:280 .text.USBD_Stop:0000000000000000 $t + /tmp/cc0ngCj0.s:287 .text.USBD_Stop:0000000000000000 USBD_Stop + /tmp/cc0ngCj0.s:338 .text.USBD_RunTestMode:0000000000000000 $t + /tmp/cc0ngCj0.s:345 .text.USBD_RunTestMode:0000000000000000 USBD_RunTestMode + /tmp/cc0ngCj0.s:364 .text.USBD_SetClassConfig:0000000000000000 $t + /tmp/cc0ngCj0.s:371 .text.USBD_SetClassConfig:0000000000000000 USBD_SetClassConfig + /tmp/cc0ngCj0.s:412 .text.USBD_ClrClassConfig:0000000000000000 $t + /tmp/cc0ngCj0.s:419 .text.USBD_ClrClassConfig:0000000000000000 USBD_ClrClassConfig + /tmp/cc0ngCj0.s:452 .text.USBD_LL_SetupStage:0000000000000000 $t + /tmp/cc0ngCj0.s:459 .text.USBD_LL_SetupStage:0000000000000000 USBD_LL_SetupStage + /tmp/cc0ngCj0.s:547 .text.USBD_LL_DataOutStage:0000000000000000 $t + /tmp/cc0ngCj0.s:554 .text.USBD_LL_DataOutStage:0000000000000000 USBD_LL_DataOutStage + /tmp/cc0ngCj0.s:689 .text.USBD_LL_DataInStage:0000000000000000 $t + /tmp/cc0ngCj0.s:696 .text.USBD_LL_DataInStage:0000000000000000 USBD_LL_DataInStage + /tmp/cc0ngCj0.s:896 .text.USBD_LL_Reset:0000000000000000 $t + /tmp/cc0ngCj0.s:903 .text.USBD_LL_Reset:0000000000000000 USBD_LL_Reset + /tmp/cc0ngCj0.s:987 .text.USBD_LL_SetSpeed:0000000000000000 $t + /tmp/cc0ngCj0.s:994 .text.USBD_LL_SetSpeed:0000000000000000 USBD_LL_SetSpeed + /tmp/cc0ngCj0.s:1015 .text.USBD_LL_Suspend:0000000000000000 $t + /tmp/cc0ngCj0.s:1022 .text.USBD_LL_Suspend:0000000000000000 USBD_LL_Suspend + /tmp/cc0ngCj0.s:1049 .text.USBD_LL_Resume:0000000000000000 $t + /tmp/cc0ngCj0.s:1056 .text.USBD_LL_Resume:0000000000000000 USBD_LL_Resume + /tmp/cc0ngCj0.s:1089 .text.USBD_LL_SOF:0000000000000000 $t + /tmp/cc0ngCj0.s:1096 .text.USBD_LL_SOF:0000000000000000 USBD_LL_SOF + /tmp/cc0ngCj0.s:1140 .text.USBD_LL_IsoINIncomplete:0000000000000000 $t + /tmp/cc0ngCj0.s:1147 .text.USBD_LL_IsoINIncomplete:0000000000000000 USBD_LL_IsoINIncomplete + /tmp/cc0ngCj0.s:1167 .text.USBD_LL_IsoOUTIncomplete:0000000000000000 $t + /tmp/cc0ngCj0.s:1174 .text.USBD_LL_IsoOUTIncomplete:0000000000000000 USBD_LL_IsoOUTIncomplete + /tmp/cc0ngCj0.s:1194 .text.USBD_LL_DevConnected:0000000000000000 $t + /tmp/cc0ngCj0.s:1201 .text.USBD_LL_DevConnected:0000000000000000 USBD_LL_DevConnected + /tmp/cc0ngCj0.s:1220 .text.USBD_LL_DevDisconnected:0000000000000000 $t + /tmp/cc0ngCj0.s:1227 .text.USBD_LL_DevDisconnected:0000000000000000 USBD_LL_DevDisconnected + +UNDEFINED SYMBOLS +USBD_LL_Init +USBD_LL_Stop +USBD_LL_DeInit +USBD_LL_Start +USBD_ParseSetupRequest +USBD_LL_StallEP +USBD_StdDevReq +USBD_StdItfReq +USBD_StdEPReq +USBD_CtlSendStatus +USBD_CtlContinueRx +USBD_CtlReceiveStatus +USBD_CtlContinueSendData + ARM GAS /tmp/cc0ngCj0.s page 38 + + +USBD_LL_PrepareReceive +USBD_LL_OpenEP diff --git a/build/usbd_core.o b/build/usbd_core.o new file mode 100644 index 0000000..b66b389 Binary files /dev/null and b/build/usbd_core.o differ diff --git a/build/usbd_ctlreq.d b/build/usbd_ctlreq.d new file mode 100644 index 0000000..c063e5c --- /dev/null +++ b/build/usbd_ctlreq.d @@ -0,0 +1,87 @@ +build/usbd_ctlreq.o: \ + Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/build/usbd_ctlreq.lst b/build/usbd_ctlreq.lst new file mode 100644 index 0000000..32d64ef --- /dev/null +++ b/build/usbd_ctlreq.lst @@ -0,0 +1,4286 @@ +ARM GAS /tmp/cc37ZWv9.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_ctlreq.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.USBD_GetLen,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 USBD_GetLen: + 25 .LVL0: + 26 .LFB158: + 27 .file 1 "Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c" + 1:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 2:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ****************************************************************************** + 3:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @file usbd_req.c + 4:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @author MCD Application Team + 5:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief This file provides the standard USB requests following chapter 9. + 6:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ****************************************************************************** + 7:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @attention + 8:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * + 9:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** *

© Copyright (c) 2015 STMicroelectronics. + 10:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * All rights reserved.

+ 11:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * + 12:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * This software component is licensed by ST under Ultimate Liberty license + 13:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 14:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * the License. You may obtain a copy of the License at: + 15:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * www.st.com/SLA0044 + 16:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * + 17:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ****************************************************************************** + 18:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 19:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 20:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /* Includes ------------------------------------------------------------------*/ + 21:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #include "usbd_ctlreq.h" + 22:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #include "usbd_ioreq.h" + 23:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 24:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 25:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY + 26:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 27:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 28:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 29:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 30:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ + 31:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USB standard requests module + ARM GAS /tmp/cc37ZWv9.s page 2 + + + 32:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 33:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 34:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 35:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_TypesDefinitions + 36:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 37:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 38:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 39:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 40:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @} + 41:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 42:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 43:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 44:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Defines + 45:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 46:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 47:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 48:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 49:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @} + 50:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 51:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 52:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 53:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Macros + 54:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 55:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 56:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 57:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 58:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @} + 59:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 60:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 61:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 62:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Variables + 63:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 64:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 65:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 66:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 67:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @} + 68:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 69:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 70:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 71:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_FunctionPrototypes + 72:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 73:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 74:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 75:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 76:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 77:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 78:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 79:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 80:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 81:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t USBD_GetLen(uint8_t *buf); + 82:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 83:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 84:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @} + 85:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 86:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 87:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 88:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** @defgroup USBD_REQ_Private_Functions + ARM GAS /tmp/cc37ZWv9.s page 3 + + + 89:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @{ + 90:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 92:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 93:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 94:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_StdDevReq + 95:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle standard usb device requests + 96:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 97:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 98:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 99:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 103:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (req->bmRequest & USB_REQ_TYPE_MASK) + 105:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 106:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_CLASS: + 107:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_VENDOR: + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 110:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 111:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_STANDARD: + 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (req->bRequest) + 113:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 114:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_GET_DESCRIPTOR: + 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_GetDescriptor(pdev, req); + 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 117:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 118:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_SET_ADDRESS: + 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_SetAddress(pdev, req); + 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 121:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 122:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_SET_CONFIGURATION: + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = USBD_SetConfig(pdev, req); + 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 125:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 126:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_GET_CONFIGURATION: + 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_GetConfig(pdev, req); + 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 129:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 130:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_GET_STATUS: + 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_GetStatus(pdev, req); + 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 133:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 134:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_SET_FEATURE: + 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_SetFeature(pdev, req); + 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 137:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 138:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_CLEAR_FEATURE: + 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_ClrFeature(pdev, req); + 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 141:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 142:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 145:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 4 + + + 146:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 147:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 148:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 151:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 152:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return ret; + 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 155:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 156:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 157:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_StdItfReq + 158:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle standard usb interface requests + 159:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 160:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 161:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 162:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 166:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (req->bmRequest & USB_REQ_TYPE_MASK) + 168:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 169:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_CLASS: + 170:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_VENDOR: + 171:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_STANDARD: + 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 173:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_DEFAULT: + 175:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 176:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 177:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + 179:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 181:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((req->wLength == 0U) && (ret == USBD_OK)) + 183:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 185:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 186:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 187:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 188:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 190:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 191:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 192:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 196:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 197:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 198:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 199:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 202:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 5 + + + 203:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return ret; + 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 206:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 207:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 208:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_StdEPReq + 209:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle standard usb endpoint requests + 210:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 211:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 212:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 213:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 214:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 216:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_EndpointTypeDef *pep; + 217:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t ep_addr; + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 220:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (req->bmRequest & USB_REQ_TYPE_MASK) + 222:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 223:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_CLASS: + 224:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_VENDOR: + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 226:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 227:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 228:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_TYPE_STANDARD: + 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (req->bRequest) + 230:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 231:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_SET_FEATURE: + 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 233:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 234:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + 236:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, ep_addr); + 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 239:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 240:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 241:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 243:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 244:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 245:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 246:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wValue == USB_FEATURE_EP_HALT) + 248:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) + 250:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, ep_addr); + 252:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 253:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 255:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 256:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 257:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 258:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + ARM GAS /tmp/cc37ZWv9.s page 6 + + + 260:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 261:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 262:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 263:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 264:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_CLEAR_FEATURE: + 265:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 267:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 268:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + 270:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, ep_addr); + 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 273:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 274:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 275:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 277:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 278:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 279:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 280:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wValue == USB_FEATURE_EP_HALT) + 282:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr & 0x7FU) != 0x00U) + 284:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_ClearStallEP(pdev, ep_addr); + 286:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 289:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 290:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 291:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 292:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 294:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 295:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 296:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 297:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 298:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_REQ_GET_STATUS: + 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 300:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 301:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + 303:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 304:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 306:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + 308:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 309:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pep->status = 0x0000U; + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 314:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr & 0x80U) == 0x80U) + ARM GAS /tmp/cc37ZWv9.s page 7 + + + 317:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) + 319:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 320:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 322:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 323:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 324:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 325:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) + 327:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 328:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 330:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 331:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 332:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + 334:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 335:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) + 337:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pep->status = 0x0000U; + 339:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) + 341:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pep->status = 0x0001U; + 343:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 344:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 345:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pep->status = 0x0000U; + 347:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 348:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 351:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 352:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 355:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 356:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 357:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 358:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 361:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 362:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 363:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 364:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 365:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 367:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 368:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 369:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return ret; + 370:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 371:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 372:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 373:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + ARM GAS /tmp/cc37ZWv9.s page 8 + + + 374:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_GetDescriptor + 375:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle Get Descriptor requests + 376:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 377:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 378:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 379:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 380:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint16_t len = 0U; + 383:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuf = NULL; + 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t err = 0U; + 385:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (req->wValue >> 8) + 387:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 388:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) + 389:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_DESC_TYPE_BOS: + 390:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetBOSDescriptor != NULL) + 391:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 392:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + 393:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 394:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 395:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 396:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 397:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 398:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 399:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 400:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif + 401:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_DESC_TYPE_DEVICE: + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + 403:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 404:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 405:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_DESC_TYPE_CONFIGURATION: + 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->dev_speed == USBD_SPEED_HIGH) + 407:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pClass->GetHSConfigDescriptor(&len); + 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 410:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 411:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 412:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pClass->GetFSConfigDescriptor(&len); + 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 415:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 416:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 417:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 418:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_DESC_TYPE_STRING: + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch ((uint8_t)(req->wValue)) + 420:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 421:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_IDX_LANGID_STR: + 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetLangIDStrDescriptor != NULL) + 423:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); + 425:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 426:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 427:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 429:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 430:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 9 + + + 431:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 432:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 433:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_IDX_MFC_STR: + 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) + 435:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); + 437:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 438:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 439:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 440:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 441:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 442:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 443:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 444:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 445:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_IDX_PRODUCT_STR: + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetProductStrDescriptor != NULL) + 447:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + 449:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 450:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 451:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 452:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 453:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 454:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 455:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 456:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 457:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_IDX_SERIAL_STR: + 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetSerialStrDescriptor != NULL) + 459:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + 461:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 462:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 463:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 464:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 465:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 466:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 467:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 468:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 469:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_IDX_CONFIG_STR: + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) + 471:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); + 473:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 474:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 475:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 476:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 477:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 478:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 479:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 480:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 481:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_IDX_INTERFACE_STR: + 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) + 483:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); + 485:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 486:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 487:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + ARM GAS /tmp/cc37ZWv9.s page 10 + + + 488:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 489:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 490:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 491:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 492:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 493:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 494:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U) + 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pClass->GetUsrStrDescriptor != NULL) + 496:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 497:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len); + 498:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 499:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 500:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 501:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 502:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 503:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 504:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #elif (USBD_CLASS_USER_STRING_DESC == 1U) + 505:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->pDesc->GetUserStrDescriptor != NULL) + 506:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 507:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pDesc->GetUserStrDescriptor(pdev->dev_speed, (req->wValue), &len); + 508:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 509:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 510:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 511:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 512:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 513:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 514:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else + 515:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 516:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 517:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif + 518:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 519:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 520:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 521:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 522:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_DESC_TYPE_DEVICE_QUALIFIER: + 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->dev_speed == USBD_SPEED_HIGH) + 524:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + 526:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 527:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 528:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 530:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 531:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 532:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 533:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 534:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->dev_speed == USBD_SPEED_HIGH) + 536:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + 538:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 539:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 540:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 541:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 543:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 544:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 11 + + + 545:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 546:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 547:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 548:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 549:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 550:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 551:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 552:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (err != 0U) + 554:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 555:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return; + 556:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 557:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 558:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wLength != 0U) + 560:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (len != 0U) + 562:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** len = MIN(len, req->wLength); + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, pbuf, len); + 565:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 566:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 567:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 568:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 569:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 570:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 571:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 572:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 574:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 575:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 577:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 578:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 579:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_SetAddress + 580:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Set device address + 581:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 582:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 583:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 584:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 585:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 586:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 587:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t dev_addr; + 588:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U)) + 590:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 591:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** dev_addr = (uint8_t)(req->wValue) & 0x7FU; + 592:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->dev_state == USBD_STATE_CONFIGURED) + 594:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 595:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 596:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 597:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 598:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 599:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_address = dev_addr; + 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_SetUSBAddress(pdev, dev_addr); + 601:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + ARM GAS /tmp/cc37ZWv9.s page 12 + + + 602:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (dev_addr != 0U) + 604:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_ADDRESSED; + 606:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 607:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 608:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 609:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_DEFAULT; + 610:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 611:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 612:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 613:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 614:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 616:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 617:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 618:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 619:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 620:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_SetConfig + 621:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle Set device configuration request + 622:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 623:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 624:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 625:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 626:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 627:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 628:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 629:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t cfgidx; + 630:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** cfgidx = (uint8_t)(req->wValue); + 632:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (cfgidx > USBD_MAX_NUM_CONFIGURATION) + 634:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 635:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return USBD_FAIL; + 637:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 638:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 640:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 641:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (cfgidx != 0U) + 643:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config = cfgidx; + 645:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = USBD_SetClassConfig(pdev, cfgidx); + 647:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 648:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (ret != USBD_OK) + 649:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 650:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 651:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 652:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 653:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 654:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 655:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_CONFIGURED; + 656:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 657:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 658:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + ARM GAS /tmp/cc37ZWv9.s page 13 + + + 659:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 660:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 661:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 662:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 663:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 664:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 665:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (cfgidx == 0U) + 666:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 667:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_ADDRESSED; + 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config = cfgidx; + 669:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, cfgidx); + 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 671:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else if (cfgidx != pdev->dev_config) + 673:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 674:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /* Clear old configuration */ + 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + 676:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 677:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /* set new configuration */ + 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config = cfgidx; + 679:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 680:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = USBD_SetClassConfig(pdev, cfgidx); + 681:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 682:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (ret != USBD_OK) + 683:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 684:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 685:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + 686:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_ADDRESSED; + 687:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 688:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 689:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 690:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 691:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 692:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 693:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 694:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 695:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 696:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 697:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 698:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 699:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 700:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 701:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, cfgidx); + 702:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = USBD_FAIL; + 703:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 704:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 705:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 706:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return ret; + 707:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 708:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 709:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 710:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_GetConfig + 711:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle Get device configuration request + 712:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 713:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 714:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 715:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + ARM GAS /tmp/cc37ZWv9.s page 14 + + + 716:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 717:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 718:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wLength != 1U) + 719:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 720:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 721:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 722:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** else + 723:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 724:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 725:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 726:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_DEFAULT: + 727:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 728:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_default_config = 0U; + 729:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + 730:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 731:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 732:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 733:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); + 734:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 735:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 736:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 737:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 738:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 739:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 740:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 741:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 742:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 743:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 744:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_GetStatus + 745:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle Get Status request + 746:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 747:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 748:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 749:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 750:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 751:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 752:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 753:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 754:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_DEFAULT: + 755:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 756:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 757:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wLength != 0x2U) + 758:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 759:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 760:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 761:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 762:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 763:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #if (USBD_SELF_POWERED == 1U) + 764:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config_status = USB_CONFIG_SELF_POWERED; + 765:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else + 766:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config_status = 0U; + 767:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #endif + 768:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 769:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (pdev->dev_remote_wakeup != 0U) + 770:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 771:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + 772:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 15 + + + 773:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); + 775:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 776:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 777:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 778:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 779:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 780:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 781:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 782:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 783:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 784:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 785:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_SetFeature + 786:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle Set device feature request + 787:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 788:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 789:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 790:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 791:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 792:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 793:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 794:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 795:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_remote_wakeup = 1U; + 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 797:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 798:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 799:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 800:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 801:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 802:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_ClrFeature + 803:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle clear device feature request + 804:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 805:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 806:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval status + 807:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 808:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 809:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 810:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 811:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 812:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_DEFAULT: + 813:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_ADDRESSED: + 814:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** case USBD_STATE_CONFIGURED: + 815:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 816:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 817:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_remote_wakeup = 0U; + 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 819:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 820:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 821:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 822:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** default: + 823:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_CtlError(pdev, req); + 824:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 825:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 826:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 827:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 828:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 829:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_ParseSetupRequest + ARM GAS /tmp/cc37ZWv9.s page 16 + + + 830:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Copy buffer into setup structure + 831:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 832:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 833:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval None + 834:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 835:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 836:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) + 837:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 838:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuff = pdata; + 839:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 840:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->bmRequest = *(uint8_t *)(pbuff); + 841:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 842:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->bRequest = *(uint8_t *)(pbuff); + 844:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 845:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->wValue = SWAPBYTE(pbuff); + 847:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 848:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 849:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 850:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->wIndex = SWAPBYTE(pbuff); + 851:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 852:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 853:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 854:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->wLength = SWAPBYTE(pbuff); + 855:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 856:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 857:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 858:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_CtlError + 859:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Handle USB low level Error + 860:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param pdev: device instance + 861:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param req: usb request + 862:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval None + 863:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 864:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 865:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 866:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 867:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** UNUSED(req); + 868:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 870:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0U); + 871:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 872:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 873:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 874:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 875:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_GetString + 876:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * Convert Ascii string into unicode one + 877:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param desc : descriptor buffer + 878:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param unicode : Formatted string buffer (unicode) + 879:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param len : descriptor length + 880:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval None + 881:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 882:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) + 883:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 884:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t idx = 0U; + 885:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pdesc; + 886:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + ARM GAS /tmp/cc37ZWv9.s page 17 + + + 887:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (desc == NULL) + 888:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 889:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return; + 890:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 891:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 892:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdesc = desc; + 893:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; + 894:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 895:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** unicode[idx] = *(uint8_t *)len; + 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 897:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** unicode[idx] = USB_DESC_TYPE_STRING; + 898:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 899:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** while (*pdesc != (uint8_t)'\0') + 901:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 902:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** unicode[idx] = *pdesc; + 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdesc++; + 904:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 905:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 906:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** unicode[idx] = 0U; + 907:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 908:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 909:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 910:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 911:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** /** + 912:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @brief USBD_GetLen + 913:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * return the string length + 914:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @param buf : pointer to the ascii string buffer + 915:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** * @retval string length + 916:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** */ + 917:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t USBD_GetLen(uint8_t *buf) + 918:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 28 .loc 1 918 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 918 1 is_stmt 0 view .LVU1 + 34 0000 0346 mov r3, r0 + 919:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t len = 0U; + 35 .loc 1 919 3 is_stmt 1 view .LVU2 + 36 .LVL1: + 920:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuff = buf; + 37 .loc 1 920 3 view .LVU3 + 921:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 922:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** while (*pbuff != (uint8_t)'\0') + 38 .loc 1 922 3 view .LVU4 + 919:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuff = buf; + 39 .loc 1 919 12 is_stmt 0 view .LVU5 + 40 0002 0020 movs r0, #0 + 41 .LVL2: + 42 .loc 1 922 9 view .LVU6 + 43 0004 02E0 b .L2 + 44 .LVL3: + 45 .L3: + 923:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 924:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** len++; + ARM GAS /tmp/cc37ZWv9.s page 18 + + + 46 .loc 1 924 5 is_stmt 1 view .LVU7 + 47 .loc 1 924 8 is_stmt 0 view .LVU8 + 48 0006 0130 adds r0, r0, #1 + 49 .LVL4: + 50 .loc 1 924 8 view .LVU9 + 51 0008 C0B2 uxtb r0, r0 + 52 .LVL5: + 925:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 53 .loc 1 925 5 is_stmt 1 view .LVU10 + 54 .loc 1 925 10 is_stmt 0 view .LVU11 + 55 000a 0133 adds r3, r3, #1 + 56 .LVL6: + 57 .L2: + 922:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 58 .loc 1 922 9 is_stmt 1 view .LVU12 + 922:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 59 .loc 1 922 10 is_stmt 0 view .LVU13 + 60 000c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 922:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 61 .loc 1 922 9 view .LVU14 + 62 000e 002A cmp r2, #0 + 63 0010 F9D1 bne .L3 + 926:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 927:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 928:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return len; + 64 .loc 1 928 3 is_stmt 1 view .LVU15 + 929:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 65 .loc 1 929 1 is_stmt 0 view .LVU16 + 66 0012 7047 bx lr + 67 .cfi_endproc + 68 .LFE158: + 70 .section .text.USBD_SetFeature,"ax",%progbits + 71 .align 1 + 72 .syntax unified + 73 .thumb + 74 .thumb_func + 75 .fpu fpv5-d16 + 77 USBD_SetFeature: + 78 .LVL7: + 79 .LFB153: + 792:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 80 .loc 1 792 1 is_stmt 1 view -0 + 81 .cfi_startproc + 82 @ args = 0, pretend = 0, frame = 0 + 83 @ frame_needed = 0, uses_anonymous_args = 0 + 792:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) + 84 .loc 1 792 1 is_stmt 0 view .LVU18 + 85 0000 08B5 push {r3, lr} + 86 .LCFI0: + 87 .cfi_def_cfa_offset 8 + 88 .cfi_offset 3, -8 + 89 .cfi_offset 14, -4 + 793:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 90 .loc 1 793 3 is_stmt 1 view .LVU19 + 793:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 91 .loc 1 793 10 is_stmt 0 view .LVU20 + 92 0002 4B88 ldrh r3, [r1, #2] + ARM GAS /tmp/cc37ZWv9.s page 19 + + + 793:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 93 .loc 1 793 6 view .LVU21 + 94 0004 012B cmp r3, #1 + 95 0006 00D0 beq .L7 + 96 .LVL8: + 97 .L4: + 798:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 98 .loc 1 798 1 view .LVU22 + 99 0008 08BD pop {r3, pc} + 100 .LVL9: + 101 .L7: + 795:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 102 .loc 1 795 5 is_stmt 1 view .LVU23 + 795:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 103 .loc 1 795 29 is_stmt 0 view .LVU24 + 104 000a C0F8A432 str r3, [r0, #676] + 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 105 .loc 1 796 5 is_stmt 1 view .LVU25 + 796:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 106 .loc 1 796 11 is_stmt 0 view .LVU26 + 107 000e FFF7FEFF bl USBD_CtlSendStatus + 108 .LVL10: + 798:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 109 .loc 1 798 1 view .LVU27 + 110 0012 F9E7 b .L4 + 111 .cfi_endproc + 112 .LFE153: + 114 .section .text.USBD_ParseSetupRequest,"ax",%progbits + 115 .align 1 + 116 .global USBD_ParseSetupRequest + 117 .syntax unified + 118 .thumb + 119 .thumb_func + 120 .fpu fpv5-d16 + 122 USBD_ParseSetupRequest: + 123 .LVL11: + 124 .LFB155: + 837:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuff = pdata; + 125 .loc 1 837 1 is_stmt 1 view -0 + 126 .cfi_startproc + 127 @ args = 0, pretend = 0, frame = 0 + 128 @ frame_needed = 0, uses_anonymous_args = 0 + 129 @ link register save eliminated. + 838:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 130 .loc 1 838 3 view .LVU29 + 840:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 131 .loc 1 840 3 view .LVU30 + 840:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 132 .loc 1 840 20 is_stmt 0 view .LVU31 + 133 0000 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 840:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 134 .loc 1 840 18 view .LVU32 + 135 0002 0370 strb r3, [r0] + 842:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->bRequest = *(uint8_t *)(pbuff); + 136 .loc 1 842 3 is_stmt 1 view .LVU33 + 137 .LVL12: + 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + ARM GAS /tmp/cc37ZWv9.s page 20 + + + 138 .loc 1 843 3 view .LVU34 + 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 139 .loc 1 843 19 is_stmt 0 view .LVU35 + 140 0004 4B78 ldrb r3, [r1, #1] @ zero_extendqisi2 + 843:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 141 .loc 1 843 17 view .LVU36 + 142 0006 4370 strb r3, [r0, #1] + 845:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->wValue = SWAPBYTE(pbuff); + 143 .loc 1 845 3 is_stmt 1 view .LVU37 + 144 .LVL13: + 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 145 .loc 1 846 3 view .LVU38 + 146 .LBB8: + 147 .LBI8: + 148 .file 2 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 1:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** + 2:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** ****************************************************************************** + 3:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @file usbd_def.h + 4:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @author MCD Application Team + 5:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @brief General defines for the usb device library + 6:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** ****************************************************************************** + 7:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @attention + 8:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * + 9:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** *

© Copyright (c) 2015 STMicroelectronics. + 10:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * All rights reserved.

+ 11:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * + 12:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * This software component is licensed by ST under Ultimate Liberty license + 13:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * SLA0044, the "License"; You may not use this file except in compliance with + 14:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * the License. You may obtain a copy of the License at: + 15:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * www.st.com/SLA0044 + 16:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * + 17:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** ****************************************************************************** + 18:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + 19:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 20:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef __USBD_DEF_H + 22:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define __USBD_DEF_H + 23:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 24:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifdef __cplusplus + 25:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** extern "C" { + 26:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif + 27:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 28:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Includes ------------------------------------------------------------------*/ + 29:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #include "usbd_conf.h" + 30:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 31:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @addtogroup STM32_USBD_DEVICE_LIBRARY + 32:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @{ + 33:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + 34:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 35:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USB_DEF + 36:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @brief general defines for the usb device library file + 37:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @{ + 38:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + 39:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 40:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USB_DEF_Exported_Defines + 41:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @{ + 42:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + ARM GAS /tmp/cc37ZWv9.s page 21 + + + 43:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 44:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef NULL + 45:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define NULL 0U + 46:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* NULL */ + 47:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 48:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_MAX_NUM_INTERFACES + 49:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_MAX_NUM_INTERFACES 1U + 50:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_MAX_NUM_CONFIGURATION */ + 51:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 52:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_MAX_NUM_CONFIGURATION + 53:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_MAX_NUM_CONFIGURATION 1U + 54:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_MAX_NUM_CONFIGURATION */ + 55:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 56:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_LPM_ENABLED + 57:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_LPM_ENABLED 0U + 58:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_LPM_ENABLED */ + 59:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 60:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_SELF_POWERED + 61:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_SELF_POWERED 1U + 62:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /*USBD_SELF_POWERED */ + 63:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 64:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_SUPPORT_USER_STRING_DESC + 65:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_SUPPORT_USER_STRING_DESC 0U + 66:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_SUPPORT_USER_STRING_DESC */ + 67:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 68:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #ifndef USBD_CLASS_USER_STRING_DESC + 69:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_CLASS_USER_STRING_DESC 0U + 70:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif /* USBD_CLASS_USER_STRING_DESC */ + 71:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 72:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_DEV_QUALIFIER_DESC 0x0AU + 73:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_DEV_DESC 0x12U + 74:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_CFG_DESC 0x09U + 75:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_IF_DESC 0x09U + 76:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_EP_DESC 0x07U + 77:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_OTG_DESC 0x03U + 78:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_LANGID_STR_DESC 0x04U + 79:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U + 80:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 81:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_IDX_LANGID_STR 0x00U + 82:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_IDX_MFC_STR 0x01U + 83:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_IDX_PRODUCT_STR 0x02U + 84:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_IDX_SERIAL_STR 0x03U + 85:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_IDX_CONFIG_STR 0x04U + 86:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_IDX_INTERFACE_STR 0x05U + 87:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 88:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_TYPE_STANDARD 0x00U + 89:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_TYPE_CLASS 0x20U + 90:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_TYPE_VENDOR 0x40U + 91:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_TYPE_MASK 0x60U + 92:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 93:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_RECIPIENT_DEVICE 0x00U + 94:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_RECIPIENT_INTERFACE 0x01U + 95:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_RECIPIENT_ENDPOINT 0x02U + 96:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_RECIPIENT_MASK 0x03U + 97:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 98:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_GET_STATUS 0x00U + 99:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_CLEAR_FEATURE 0x01U + ARM GAS /tmp/cc37ZWv9.s page 22 + + + 100:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_SET_FEATURE 0x03U + 101:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_SET_ADDRESS 0x05U + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_GET_DESCRIPTOR 0x06U + 103:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_SET_DESCRIPTOR 0x07U + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_GET_CONFIGURATION 0x08U + 105:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_SET_CONFIGURATION 0x09U + 106:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_GET_INTERFACE 0x0AU + 107:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_SET_INTERFACE 0x0BU + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_REQ_SYNCH_FRAME 0x0CU + 109:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 110:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_DEVICE 0x01U + 111:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_CONFIGURATION 0x02U + 112:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_STRING 0x03U + 113:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_INTERFACE 0x04U + 114:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_ENDPOINT 0x05U + 115:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U + 116:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U + 117:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DESC_TYPE_BOS 0x0FU + 118:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 119:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_CONFIG_REMOTE_WAKEUP 0x02U + 120:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_CONFIG_SELF_POWERED 0x01U + 121:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 122:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FEATURE_EP_HALT 0x00U + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FEATURE_REMOTE_WAKEUP 0x01U + 124:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FEATURE_TEST_MODE 0x02U + 125:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 126:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_DEVICE_CAPABITY_TYPE 0x10U + 127:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 128:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_HS_MAX_PACKET_SIZE 512U + 129:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_FS_MAX_PACKET_SIZE 64U + 130:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USB_MAX_EP0_SIZE 64U + 131:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 132:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Device Status */ + 133:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_DEFAULT 0x01U + 134:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_ADDRESSED 0x02U + 135:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_CONFIGURED 0x03U + 136:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_STATE_SUSPENDED 0x04U + 137:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 138:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 139:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* EP0 State */ + 140:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_IDLE 0x00U + 141:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_SETUP 0x01U + 142:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_DATA_IN 0x02U + 143:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_DATA_OUT 0x03U + 144:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_STATUS_IN 0x04U + 145:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_STATUS_OUT 0x05U + 146:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP0_STALL 0x06U + 147:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 148:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_CTRL 0x00U + 149:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_ISOC 0x01U + 150:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_BULK 0x02U + 151:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #define USBD_EP_TYPE_INTR 0x03U + 152:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 153:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 154:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** + 155:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @} + 156:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + ARM GAS /tmp/cc37ZWv9.s page 23 + + + 157:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 158:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 159:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USBD_DEF_Exported_TypesDefinitions + 160:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @{ + 161:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + 162:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct usb_setup_req + 164:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bmRequest; + 166:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bRequest; + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t wValue; + 168:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t wIndex; + 169:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t wLength; + 170:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_SetupReqTypedef; + 171:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 172:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct + 173:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 174:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bLength; + 175:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bDescriptorType; + 176:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t wDescriptorLengthLow; + 177:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t wDescriptorLengthHigh; + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bNumInterfaces; + 179:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bConfigurationValue; + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t iConfiguration; + 181:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bmAttributes; + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bMaxPower; + 183:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_ConfigDescTypedef; + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 185:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct + 186:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 187:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bLength; + 188:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bDescriptorType; + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t wTotalLength; + 190:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t bNumDeviceCaps; + 191:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_BosDescTypedef; + 192:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 193:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** struct _USBD_HandleTypeDef; + 195:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 196:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct _Device_cb + 197:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 198:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx); + 199:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx); + 200:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Control Endpoints*/ + 201:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 202:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev); + 203:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev); + 204:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Class Specific Endpoints*/ + 205:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + 206:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + 207:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev); + 208:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + 209:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum); + 210:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 211:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); + 212:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); + 213:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); + ARM GAS /tmp/cc37ZWv9.s page 24 + + + 214:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); + 215:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U) + 216:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *leng + 217:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 219:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_ClassTypeDef; + 220:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Following USB Device Speed */ + 222:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef enum + 223:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 224:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_SPEED_HIGH = 0U, + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_SPEED_FULL = 1U, + 226:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_SPEED_LOW = 2U, + 227:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_SpeedTypeDef; + 228:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 229:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* Following USB Device status */ + 230:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef enum + 231:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 232:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_OK = 0U, + 233:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_BUSY, + 234:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_EMEM, + 235:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_FAIL, + 236:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_StatusTypeDef; + 237:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 238:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* USB Device descriptors structure */ + 239:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct + 240:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 241:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 242:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 243:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 244:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 245:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 246:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 247:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 248:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #if (USBD_CLASS_USER_STRING_DESC == 1) + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); + 250:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif + 251:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1)) + 252:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + 253:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** #endif + 254:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_DescriptorsTypeDef; + 255:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 256:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* USB Device handle structure */ + 257:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct + 258:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 259:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t status; + 260:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t total_length; + 261:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t rem_length; + 262:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t maxpacket; + 263:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t is_used; + 264:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t bInterval; + 265:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_EndpointTypeDef; + 266:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 267:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /* USB Device handle structure */ + 268:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** typedef struct _USBD_HandleTypeDef + 269:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 270:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t id; + ARM GAS /tmp/cc37ZWv9.s page 25 + + + 271:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t dev_config; + 272:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t dev_default_config; + 273:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t dev_config_status; + 274:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_SpeedTypeDef dev_speed; + 275:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_EndpointTypeDef ep_in[16]; + 276:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_EndpointTypeDef ep_out[16]; + 277:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t ep0_state; + 278:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t ep0_data_len; + 279:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t dev_state; + 280:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t dev_old_state; + 281:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t dev_address; + 282:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t dev_connection_status; + 283:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t dev_test_mode; + 284:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint32_t dev_remote_wakeup; + 285:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t ConfIdx; + 286:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 287:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_SetupReqTypedef request; + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_DescriptorsTypeDef *pDesc; + 289:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** USBD_ClassTypeDef *pClass; + 290:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** void *pClassData; + 291:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** void *pUserData; + 292:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** void *pData; + 293:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** void *pBosDesc; + 294:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** void *pConfDesc; + 295:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** } USBD_HandleTypeDef; + 296:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 297:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** + 298:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @} + 299:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + 300:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 301:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 302:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 303:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** /** @defgroup USBD_DEF_Exported_Macros + 304:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** * @{ + 305:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** */ + 306:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** __STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) + 149 .loc 2 306 26 view .LVU39 + 150 .LBB9: + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 308:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint16_t _SwapVal, _Byte1, _Byte2; + 151 .loc 2 308 3 view .LVU40 + 309:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *_pbuff = addr; + 152 .loc 2 309 3 view .LVU41 + 310:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _Byte1 = *(uint8_t *)_pbuff; + 153 .loc 2 311 3 view .LVU42 + 154 .loc 2 311 12 is_stmt 0 view .LVU43 + 155 0008 8B78 ldrb r3, [r1, #2] @ zero_extendqisi2 + 156 .LVL14: + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _pbuff++; + 157 .loc 2 312 3 is_stmt 1 view .LVU44 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _Byte2 = *(uint8_t *)_pbuff; + 158 .loc 2 313 3 view .LVU45 + 159 .loc 2 313 12 is_stmt 0 view .LVU46 + 160 000a CA78 ldrb r2, [r1, #3] @ zero_extendqisi2 + 161 .LVL15: + 314:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + ARM GAS /tmp/cc37ZWv9.s page 26 + + + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _SwapVal = (_Byte2 << 8) | _Byte1; + 162 .loc 2 315 3 is_stmt 1 view .LVU47 + 163 .loc 2 315 12 is_stmt 0 view .LVU48 + 164 000c 43EA0223 orr r3, r3, r2, lsl #8 + 165 .LVL16: + 316:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 317:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** return _SwapVal; + 166 .loc 2 317 3 is_stmt 1 view .LVU49 + 167 .loc 2 317 3 is_stmt 0 view .LVU50 + 168 .LBE9: + 169 .LBE8: + 846:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 170 .loc 1 846 15 view .LVU51 + 171 0010 4380 strh r3, [r0, #2] @ movhi + 172 .LVL17: + 848:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 173 .loc 1 848 3 is_stmt 1 view .LVU52 + 849:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->wIndex = SWAPBYTE(pbuff); + 174 .loc 1 849 3 view .LVU53 + 850:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 175 .loc 1 850 3 view .LVU54 + 176 .LBB10: + 177 .LBI10: + 306:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 178 .loc 2 306 26 view .LVU55 + 179 .LBB11: + 308:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *_pbuff = addr; + 180 .loc 2 308 3 view .LVU56 + 309:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 181 .loc 2 309 3 view .LVU57 + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _pbuff++; + 182 .loc 2 311 3 view .LVU58 + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _pbuff++; + 183 .loc 2 311 12 is_stmt 0 view .LVU59 + 184 0012 0B79 ldrb r3, [r1, #4] @ zero_extendqisi2 + 185 .LVL18: + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _Byte2 = *(uint8_t *)_pbuff; + 186 .loc 2 312 3 is_stmt 1 view .LVU60 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 187 .loc 2 313 3 view .LVU61 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 188 .loc 2 313 12 is_stmt 0 view .LVU62 + 189 0014 4A79 ldrb r2, [r1, #5] @ zero_extendqisi2 + 190 .LVL19: + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 191 .loc 2 315 3 is_stmt 1 view .LVU63 + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 192 .loc 2 315 12 is_stmt 0 view .LVU64 + 193 0016 43EA0223 orr r3, r3, r2, lsl #8 + 194 .LVL20: + 195 .loc 2 317 3 is_stmt 1 view .LVU65 + 196 .loc 2 317 3 is_stmt 0 view .LVU66 + 197 .LBE11: + 198 .LBE10: + 850:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 199 .loc 1 850 15 view .LVU67 + 200 001a 8380 strh r3, [r0, #4] @ movhi + ARM GAS /tmp/cc37ZWv9.s page 27 + + + 201 .LVL21: + 852:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuff++; + 202 .loc 1 852 3 is_stmt 1 view .LVU68 + 853:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** req->wLength = SWAPBYTE(pbuff); + 203 .loc 1 853 3 view .LVU69 + 854:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 204 .loc 1 854 3 view .LVU70 + 205 .LBB12: + 206 .LBI12: + 306:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** { + 207 .loc 2 306 26 view .LVU71 + 208 .LBB13: + 308:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** uint8_t *_pbuff = addr; + 209 .loc 2 308 3 view .LVU72 + 309:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 210 .loc 2 309 3 view .LVU73 + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _pbuff++; + 211 .loc 2 311 3 view .LVU74 + 311:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _pbuff++; + 212 .loc 2 311 12 is_stmt 0 view .LVU75 + 213 001c 8B79 ldrb r3, [r1, #6] @ zero_extendqisi2 + 214 .LVL22: + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** _Byte2 = *(uint8_t *)_pbuff; + 215 .loc 2 312 3 is_stmt 1 view .LVU76 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 216 .loc 2 313 3 view .LVU77 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 217 .loc 2 313 12 is_stmt 0 view .LVU78 + 218 001e CA79 ldrb r2, [r1, #7] @ zero_extendqisi2 + 219 .LVL23: + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 220 .loc 2 315 3 is_stmt 1 view .LVU79 + 315:Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h **** + 221 .loc 2 315 12 is_stmt 0 view .LVU80 + 222 0020 43EA0223 orr r3, r3, r2, lsl #8 + 223 .LVL24: + 224 .loc 2 317 3 is_stmt 1 view .LVU81 + 225 .loc 2 317 3 is_stmt 0 view .LVU82 + 226 .LBE13: + 227 .LBE12: + 854:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 228 .loc 1 854 16 view .LVU83 + 229 0024 C380 strh r3, [r0, #6] @ movhi + 230 .LVL25: + 855:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 231 .loc 1 855 1 view .LVU84 + 232 0026 7047 bx lr + 233 .cfi_endproc + 234 .LFE155: + 236 .section .text.USBD_CtlError,"ax",%progbits + 237 .align 1 + 238 .global USBD_CtlError + 239 .syntax unified + 240 .thumb + 241 .thumb_func + 242 .fpu fpv5-d16 + 244 USBD_CtlError: + ARM GAS /tmp/cc37ZWv9.s page 28 + + + 245 .LVL26: + 246 .LFB156: + 866:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** UNUSED(req); + 247 .loc 1 866 1 is_stmt 1 view -0 + 248 .cfi_startproc + 249 @ args = 0, pretend = 0, frame = 0 + 250 @ frame_needed = 0, uses_anonymous_args = 0 + 866:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** UNUSED(req); + 251 .loc 1 866 1 is_stmt 0 view .LVU86 + 252 0000 10B5 push {r4, lr} + 253 .LCFI1: + 254 .cfi_def_cfa_offset 8 + 255 .cfi_offset 4, -8 + 256 .cfi_offset 14, -4 + 257 0002 0446 mov r4, r0 + 867:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 258 .loc 1 867 3 is_stmt 1 view .LVU87 + 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0U); + 259 .loc 1 869 3 view .LVU88 + 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0U); + 260 .loc 1 869 9 is_stmt 0 view .LVU89 + 261 0004 8021 movs r1, #128 + 262 .LVL27: + 869:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0U); + 263 .loc 1 869 9 view .LVU90 + 264 0006 FFF7FEFF bl USBD_LL_StallEP + 265 .LVL28: + 870:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 266 .loc 1 870 3 is_stmt 1 view .LVU91 + 870:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 267 .loc 1 870 9 is_stmt 0 view .LVU92 + 268 000a 0021 movs r1, #0 + 269 000c 2046 mov r0, r4 + 270 000e FFF7FEFF bl USBD_LL_StallEP + 271 .LVL29: + 871:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 272 .loc 1 871 1 view .LVU93 + 273 0012 10BD pop {r4, pc} + 871:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 274 .loc 1 871 1 view .LVU94 + 275 .cfi_endproc + 276 .LFE156: + 278 .section .text.USBD_GetDescriptor,"ax",%progbits + 279 .align 1 + 280 .syntax unified + 281 .thumb + 282 .thumb_func + 283 .fpu fpv5-d16 + 285 USBD_GetDescriptor: + 286 .LVL30: + 287 .LFB148: + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint16_t len = 0U; + 288 .loc 1 381 1 is_stmt 1 view -0 + 289 .cfi_startproc + 290 @ args = 0, pretend = 0, frame = 8 + 291 @ frame_needed = 0, uses_anonymous_args = 0 + 381:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint16_t len = 0U; + ARM GAS /tmp/cc37ZWv9.s page 29 + + + 292 .loc 1 381 1 is_stmt 0 view .LVU96 + 293 0000 30B5 push {r4, r5, lr} + 294 .LCFI2: + 295 .cfi_def_cfa_offset 12 + 296 .cfi_offset 4, -12 + 297 .cfi_offset 5, -8 + 298 .cfi_offset 14, -4 + 299 0002 83B0 sub sp, sp, #12 + 300 .LCFI3: + 301 .cfi_def_cfa_offset 24 + 302 0004 0446 mov r4, r0 + 303 0006 0D46 mov r5, r1 + 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuf = NULL; + 304 .loc 1 382 3 is_stmt 1 view .LVU97 + 382:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pbuf = NULL; + 305 .loc 1 382 12 is_stmt 0 view .LVU98 + 306 0008 0023 movs r3, #0 + 307 000a ADF80630 strh r3, [sp, #6] @ movhi + 383:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t err = 0U; + 308 .loc 1 383 3 is_stmt 1 view .LVU99 + 309 .LVL31: + 384:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 310 .loc 1 384 3 view .LVU100 + 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 311 .loc 1 386 3 view .LVU101 + 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 312 .loc 1 386 14 is_stmt 0 view .LVU102 + 313 000e 4988 ldrh r1, [r1, #2] + 314 .LVL32: + 386:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 315 .loc 1 386 23 view .LVU103 + 316 0010 0B0A lsrs r3, r1, #8 + 317 0012 013B subs r3, r3, #1 + 318 0014 062B cmp r3, #6 + 319 0016 00F2B380 bhi .L12 + 320 001a DFE803F0 tbb [pc, r3] + 321 .L14: + 322 001e 04 .byte (.L18-.L14)/2 + 323 001f 1F .byte (.L17-.L14)/2 + 324 0020 33 .byte (.L16-.L14)/2 + 325 0021 B1 .byte (.L12-.L14)/2 + 326 0022 B1 .byte (.L12-.L14)/2 + 327 0023 95 .byte (.L15-.L14)/2 + 328 0024 A2 .byte (.L13-.L14)/2 + 329 0025 00 .p2align 1 + 330 .L18: + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 331 .loc 1 402 5 is_stmt 1 view .LVU104 + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 332 .loc 1 402 16 is_stmt 0 view .LVU105 + 333 0026 D0F8B432 ldr r3, [r0, #692] + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 334 .loc 1 402 23 view .LVU106 + 335 002a 1B68 ldr r3, [r3] + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 336 .loc 1 402 12 view .LVU107 + 337 002c 0DF10601 add r1, sp, #6 + ARM GAS /tmp/cc37ZWv9.s page 30 + + + 338 0030 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 339 .LVL33: + 402:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 340 .loc 1 402 12 view .LVU108 + 341 0032 9847 blx r3 + 342 .LVL34: + 403:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 343 .loc 1 403 5 is_stmt 1 view .LVU109 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 344 .loc 1 553 3 view .LVU110 + 345 .L19: + 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 346 .loc 1 559 5 view .LVU111 + 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 347 .loc 1 559 12 is_stmt 0 view .LVU112 + 348 0034 EA88 ldrh r2, [r5, #6] + 559:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 349 .loc 1 559 8 view .LVU113 + 350 0036 002A cmp r2, #0 + 351 0038 00F0AB80 beq .L40 + 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 352 .loc 1 561 7 is_stmt 1 view .LVU114 + 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 353 .loc 1 561 15 is_stmt 0 view .LVU115 + 354 003c BDF80630 ldrh r3, [sp, #6] + 561:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 355 .loc 1 561 10 view .LVU116 + 356 0040 002B cmp r3, #0 + 357 0042 00F0A180 beq .L41 + 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, pbuf, len); + 358 .loc 1 563 9 is_stmt 1 view .LVU117 + 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, pbuf, len); + 359 .loc 1 563 15 is_stmt 0 view .LVU118 + 360 0046 9A42 cmp r2, r3 + 361 0048 28BF it cs + 362 004a 1A46 movcs r2, r3 + 563:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, pbuf, len); + 363 .loc 1 563 13 view .LVU119 + 364 004c ADF80620 strh r2, [sp, #6] @ movhi + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 365 .loc 1 564 9 is_stmt 1 view .LVU120 + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 366 .loc 1 564 15 is_stmt 0 view .LVU121 + 367 0050 0146 mov r1, r0 + 368 0052 2046 mov r0, r4 + 369 .LVL35: + 564:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 370 .loc 1 564 15 view .LVU122 + 371 0054 FFF7FEFF bl USBD_CtlSendData + 372 .LVL36: + 373 .L11: + 576:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 374 .loc 1 576 1 view .LVU123 + 375 0058 03B0 add sp, sp, #12 + 376 .LCFI4: + 377 .cfi_remember_state + 378 .cfi_def_cfa_offset 12 + ARM GAS /tmp/cc37ZWv9.s page 31 + + + 379 @ sp needed + 380 005a 30BD pop {r4, r5, pc} + 381 .LVL37: + 382 .L17: + 383 .LCFI5: + 384 .cfi_restore_state + 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 385 .loc 1 406 5 is_stmt 1 view .LVU124 + 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 386 .loc 1 406 13 is_stmt 0 view .LVU125 + 387 005c 037C ldrb r3, [r0, #16] @ zero_extendqisi2 + 406:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 388 .loc 1 406 8 view .LVU126 + 389 005e 43B9 cbnz r3, .L20 + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 390 .loc 1 408 7 is_stmt 1 view .LVU127 + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 391 .loc 1 408 18 is_stmt 0 view .LVU128 + 392 0060 D0F8B832 ldr r3, [r0, #696] + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 393 .loc 1 408 26 view .LVU129 + 394 0064 9B6A ldr r3, [r3, #40] + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 395 .loc 1 408 14 view .LVU130 + 396 0066 0DF10600 add r0, sp, #6 + 397 .LVL38: + 408:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 398 .loc 1 408 14 view .LVU131 + 399 006a 9847 blx r3 + 400 .LVL39: + 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 401 .loc 1 409 7 is_stmt 1 view .LVU132 + 409:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 402 .loc 1 409 15 is_stmt 0 view .LVU133 + 403 006c 0223 movs r3, #2 + 404 006e 4370 strb r3, [r0, #1] + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 405 .loc 1 553 3 is_stmt 1 view .LVU134 + 406 0070 E0E7 b .L19 + 407 .LVL40: + 408 .L20: + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 409 .loc 1 413 7 view .LVU135 + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 410 .loc 1 413 18 is_stmt 0 view .LVU136 + 411 0072 D0F8B832 ldr r3, [r0, #696] + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 412 .loc 1 413 26 view .LVU137 + 413 0076 DB6A ldr r3, [r3, #44] + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 414 .loc 1 413 14 view .LVU138 + 415 0078 0DF10600 add r0, sp, #6 + 416 .LVL41: + 413:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + 417 .loc 1 413 14 view .LVU139 + 418 007c 9847 blx r3 + 419 .LVL42: + ARM GAS /tmp/cc37ZWv9.s page 32 + + + 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 420 .loc 1 414 7 is_stmt 1 view .LVU140 + 414:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 421 .loc 1 414 15 is_stmt 0 view .LVU141 + 422 007e 0223 movs r3, #2 + 423 0080 4370 strb r3, [r0, #1] + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 424 .loc 1 553 3 is_stmt 1 view .LVU142 + 425 0082 D7E7 b .L19 + 426 .LVL43: + 427 .L16: + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 428 .loc 1 419 5 view .LVU143 + 419:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 429 .loc 1 419 13 is_stmt 0 view .LVU144 + 430 0084 C9B2 uxtb r1, r1 + 431 0086 0529 cmp r1, #5 + 432 0088 52D8 bhi .L21 + 433 008a DFE801F0 tbb [pc, r1] + 434 .L23: + 435 008e 03 .byte (.L28-.L23)/2 + 436 008f 10 .byte (.L27-.L23)/2 + 437 0090 1D .byte (.L26-.L23)/2 + 438 0091 2A .byte (.L25-.L23)/2 + 439 0092 37 .byte (.L24-.L23)/2 + 440 0093 44 .byte (.L22-.L23)/2 + 441 .p2align 1 + 442 .L28: + 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 443 .loc 1 422 7 is_stmt 1 view .LVU145 + 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 444 .loc 1 422 15 is_stmt 0 view .LVU146 + 445 0094 D0F8B432 ldr r3, [r0, #692] + 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 446 .loc 1 422 22 view .LVU147 + 447 0098 5B68 ldr r3, [r3, #4] + 422:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 448 .loc 1 422 10 view .LVU148 + 449 009a 23B1 cbz r3, .L29 + 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 450 .loc 1 424 9 is_stmt 1 view .LVU149 + 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 451 .loc 1 424 16 is_stmt 0 view .LVU150 + 452 009c 0DF10601 add r1, sp, #6 + 453 00a0 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 454 .LVL44: + 424:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 455 .loc 1 424 16 view .LVU151 + 456 00a2 9847 blx r3 + 457 .LVL45: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 458 .loc 1 553 3 is_stmt 1 view .LVU152 + 459 00a4 C6E7 b .L19 + 460 .LVL46: + 461 .L29: + 428:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 462 .loc 1 428 9 view .LVU153 + ARM GAS /tmp/cc37ZWv9.s page 33 + + + 463 00a6 2946 mov r1, r5 + 464 00a8 FFF7FEFF bl USBD_CtlError + 465 .LVL47: + 429:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 466 .loc 1 429 9 view .LVU154 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 467 .loc 1 553 3 view .LVU155 + 468 00ac D4E7 b .L11 + 469 .LVL48: + 470 .L27: + 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 471 .loc 1 434 7 view .LVU156 + 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 472 .loc 1 434 15 is_stmt 0 view .LVU157 + 473 00ae D0F8B432 ldr r3, [r0, #692] + 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 474 .loc 1 434 22 view .LVU158 + 475 00b2 9B68 ldr r3, [r3, #8] + 434:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 476 .loc 1 434 10 view .LVU159 + 477 00b4 23B1 cbz r3, .L31 + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 478 .loc 1 436 9 is_stmt 1 view .LVU160 + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 479 .loc 1 436 16 is_stmt 0 view .LVU161 + 480 00b6 0DF10601 add r1, sp, #6 + 481 00ba 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 482 .LVL49: + 436:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 483 .loc 1 436 16 view .LVU162 + 484 00bc 9847 blx r3 + 485 .LVL50: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 486 .loc 1 553 3 is_stmt 1 view .LVU163 + 487 00be B9E7 b .L19 + 488 .LVL51: + 489 .L31: + 440:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 490 .loc 1 440 9 view .LVU164 + 491 00c0 2946 mov r1, r5 + 492 00c2 FFF7FEFF bl USBD_CtlError + 493 .LVL52: + 441:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 494 .loc 1 441 9 view .LVU165 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 495 .loc 1 553 3 view .LVU166 + 496 00c6 C7E7 b .L11 + 497 .LVL53: + 498 .L26: + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 499 .loc 1 446 7 view .LVU167 + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 500 .loc 1 446 15 is_stmt 0 view .LVU168 + 501 00c8 D0F8B432 ldr r3, [r0, #692] + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 502 .loc 1 446 22 view .LVU169 + 503 00cc DB68 ldr r3, [r3, #12] + ARM GAS /tmp/cc37ZWv9.s page 34 + + + 446:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 504 .loc 1 446 10 view .LVU170 + 505 00ce 23B1 cbz r3, .L32 + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 506 .loc 1 448 9 is_stmt 1 view .LVU171 + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 507 .loc 1 448 16 is_stmt 0 view .LVU172 + 508 00d0 0DF10601 add r1, sp, #6 + 509 00d4 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 510 .LVL54: + 448:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 511 .loc 1 448 16 view .LVU173 + 512 00d6 9847 blx r3 + 513 .LVL55: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 514 .loc 1 553 3 is_stmt 1 view .LVU174 + 515 00d8 ACE7 b .L19 + 516 .LVL56: + 517 .L32: + 452:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 518 .loc 1 452 9 view .LVU175 + 519 00da 2946 mov r1, r5 + 520 00dc FFF7FEFF bl USBD_CtlError + 521 .LVL57: + 453:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 522 .loc 1 453 9 view .LVU176 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 523 .loc 1 553 3 view .LVU177 + 524 00e0 BAE7 b .L11 + 525 .LVL58: + 526 .L25: + 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 527 .loc 1 458 7 view .LVU178 + 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 528 .loc 1 458 15 is_stmt 0 view .LVU179 + 529 00e2 D0F8B432 ldr r3, [r0, #692] + 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 530 .loc 1 458 22 view .LVU180 + 531 00e6 1B69 ldr r3, [r3, #16] + 458:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 532 .loc 1 458 10 view .LVU181 + 533 00e8 23B1 cbz r3, .L33 + 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 534 .loc 1 460 9 is_stmt 1 view .LVU182 + 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 535 .loc 1 460 16 is_stmt 0 view .LVU183 + 536 00ea 0DF10601 add r1, sp, #6 + 537 00ee 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 538 .LVL59: + 460:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 539 .loc 1 460 16 view .LVU184 + 540 00f0 9847 blx r3 + 541 .LVL60: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 542 .loc 1 553 3 is_stmt 1 view .LVU185 + 543 00f2 9FE7 b .L19 + 544 .LVL61: + ARM GAS /tmp/cc37ZWv9.s page 35 + + + 545 .L33: + 464:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 546 .loc 1 464 9 view .LVU186 + 547 00f4 2946 mov r1, r5 + 548 00f6 FFF7FEFF bl USBD_CtlError + 549 .LVL62: + 465:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 550 .loc 1 465 9 view .LVU187 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 551 .loc 1 553 3 view .LVU188 + 552 00fa ADE7 b .L11 + 553 .LVL63: + 554 .L24: + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 555 .loc 1 470 7 view .LVU189 + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 556 .loc 1 470 15 is_stmt 0 view .LVU190 + 557 00fc D0F8B432 ldr r3, [r0, #692] + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 558 .loc 1 470 22 view .LVU191 + 559 0100 5B69 ldr r3, [r3, #20] + 470:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 560 .loc 1 470 10 view .LVU192 + 561 0102 23B1 cbz r3, .L34 + 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 562 .loc 1 472 9 is_stmt 1 view .LVU193 + 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 563 .loc 1 472 16 is_stmt 0 view .LVU194 + 564 0104 0DF10601 add r1, sp, #6 + 565 0108 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 566 .LVL64: + 472:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 567 .loc 1 472 16 view .LVU195 + 568 010a 9847 blx r3 + 569 .LVL65: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 570 .loc 1 553 3 is_stmt 1 view .LVU196 + 571 010c 92E7 b .L19 + 572 .LVL66: + 573 .L34: + 476:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 574 .loc 1 476 9 view .LVU197 + 575 010e 2946 mov r1, r5 + 576 0110 FFF7FEFF bl USBD_CtlError + 577 .LVL67: + 477:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 578 .loc 1 477 9 view .LVU198 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 579 .loc 1 553 3 view .LVU199 + 580 0114 A0E7 b .L11 + 581 .LVL68: + 582 .L22: + 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 583 .loc 1 482 7 view .LVU200 + 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 584 .loc 1 482 15 is_stmt 0 view .LVU201 + 585 0116 D0F8B432 ldr r3, [r0, #692] + ARM GAS /tmp/cc37ZWv9.s page 36 + + + 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 586 .loc 1 482 22 view .LVU202 + 587 011a 9B69 ldr r3, [r3, #24] + 482:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 588 .loc 1 482 10 view .LVU203 + 589 011c 23B1 cbz r3, .L35 + 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 590 .loc 1 484 9 is_stmt 1 view .LVU204 + 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 591 .loc 1 484 16 is_stmt 0 view .LVU205 + 592 011e 0DF10601 add r1, sp, #6 + 593 0122 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 594 .LVL69: + 484:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 595 .loc 1 484 16 view .LVU206 + 596 0124 9847 blx r3 + 597 .LVL70: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 598 .loc 1 553 3 is_stmt 1 view .LVU207 + 599 0126 85E7 b .L19 + 600 .LVL71: + 601 .L35: + 488:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 602 .loc 1 488 9 view .LVU208 + 603 0128 2946 mov r1, r5 + 604 012a FFF7FEFF bl USBD_CtlError + 605 .LVL72: + 489:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 606 .loc 1 489 9 view .LVU209 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 607 .loc 1 553 3 view .LVU210 + 608 012e 93E7 b .L11 + 609 .LVL73: + 610 .L21: + 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 611 .loc 1 495 7 view .LVU211 + 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 612 .loc 1 495 15 is_stmt 0 view .LVU212 + 613 0130 D0F8B832 ldr r3, [r0, #696] + 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 614 .loc 1 495 23 view .LVU213 + 615 0134 9B6B ldr r3, [r3, #56] + 495:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 616 .loc 1 495 10 view .LVU214 + 617 0136 1BB1 cbz r3, .L36 + 497:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 618 .loc 1 497 9 is_stmt 1 view .LVU215 + 497:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 619 .loc 1 497 16 is_stmt 0 view .LVU216 + 620 0138 0DF10602 add r2, sp, #6 + 621 013c 9847 blx r3 + 622 .LVL74: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 623 .loc 1 553 3 is_stmt 1 view .LVU217 + 624 013e 79E7 b .L19 + 625 .LVL75: + 626 .L36: + ARM GAS /tmp/cc37ZWv9.s page 37 + + + 501:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 627 .loc 1 501 9 view .LVU218 + 628 0140 2946 mov r1, r5 + 629 0142 FFF7FEFF bl USBD_CtlError + 630 .LVL76: + 502:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 631 .loc 1 502 9 view .LVU219 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 632 .loc 1 553 3 view .LVU220 + 633 0146 87E7 b .L11 + 634 .LVL77: + 635 .L15: + 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 636 .loc 1 523 5 view .LVU221 + 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 637 .loc 1 523 13 is_stmt 0 view .LVU222 + 638 0148 037C ldrb r3, [r0, #16] @ zero_extendqisi2 + 523:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 639 .loc 1 523 8 view .LVU223 + 640 014a 33B9 cbnz r3, .L37 + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 641 .loc 1 525 7 is_stmt 1 view .LVU224 + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 642 .loc 1 525 18 is_stmt 0 view .LVU225 + 643 014c D0F8B832 ldr r3, [r0, #696] + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 644 .loc 1 525 26 view .LVU226 + 645 0150 5B6B ldr r3, [r3, #52] + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 646 .loc 1 525 14 view .LVU227 + 647 0152 0DF10600 add r0, sp, #6 + 648 .LVL78: + 525:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 649 .loc 1 525 14 view .LVU228 + 650 0156 9847 blx r3 + 651 .LVL79: + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 652 .loc 1 553 3 is_stmt 1 view .LVU229 + 653 0158 6CE7 b .L19 + 654 .LVL80: + 655 .L37: + 529:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 656 .loc 1 529 7 view .LVU230 + 657 015a 2946 mov r1, r5 + 658 015c FFF7FEFF bl USBD_CtlError + 659 .LVL81: + 530:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 660 .loc 1 530 7 view .LVU231 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 661 .loc 1 553 3 view .LVU232 + 662 0160 7AE7 b .L11 + 663 .LVL82: + 664 .L13: + 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 665 .loc 1 535 5 view .LVU233 + 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 666 .loc 1 535 13 is_stmt 0 view .LVU234 + ARM GAS /tmp/cc37ZWv9.s page 38 + + + 667 0162 037C ldrb r3, [r0, #16] @ zero_extendqisi2 + 535:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 668 .loc 1 535 8 view .LVU235 + 669 0164 43B9 cbnz r3, .L38 + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 670 .loc 1 537 7 is_stmt 1 view .LVU236 + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 671 .loc 1 537 18 is_stmt 0 view .LVU237 + 672 0166 D0F8B832 ldr r3, [r0, #696] + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 673 .loc 1 537 26 view .LVU238 + 674 016a 1B6B ldr r3, [r3, #48] + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 675 .loc 1 537 14 view .LVU239 + 676 016c 0DF10600 add r0, sp, #6 + 677 .LVL83: + 537:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + 678 .loc 1 537 14 view .LVU240 + 679 0170 9847 blx r3 + 680 .LVL84: + 538:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 681 .loc 1 538 7 is_stmt 1 view .LVU241 + 538:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 682 .loc 1 538 15 is_stmt 0 view .LVU242 + 683 0172 0723 movs r3, #7 + 684 0174 4370 strb r3, [r0, #1] + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 685 .loc 1 553 3 is_stmt 1 view .LVU243 + 686 0176 5DE7 b .L19 + 687 .LVL85: + 688 .L38: + 542:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 689 .loc 1 542 7 view .LVU244 + 690 0178 2946 mov r1, r5 + 691 017a FFF7FEFF bl USBD_CtlError + 692 .LVL86: + 543:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 693 .loc 1 543 7 view .LVU245 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 694 .loc 1 553 3 view .LVU246 + 695 017e 6BE7 b .L11 + 696 .LVL87: + 697 .L12: + 548:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** err++; + 698 .loc 1 548 5 view .LVU247 + 699 0180 2946 mov r1, r5 + 700 0182 FFF7FEFF bl USBD_CtlError + 701 .LVL88: + 549:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 702 .loc 1 549 5 view .LVU248 + 550:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 703 .loc 1 550 5 view .LVU249 + 553:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 704 .loc 1 553 3 view .LVU250 + 555:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 705 .loc 1 555 5 view .LVU251 + 706 0186 67E7 b .L11 + ARM GAS /tmp/cc37ZWv9.s page 39 + + + 707 .LVL89: + 708 .L41: + 568:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 709 .loc 1 568 9 view .LVU252 + 710 0188 2946 mov r1, r5 + 711 018a 2046 mov r0, r4 + 712 .LVL90: + 568:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 713 .loc 1 568 9 is_stmt 0 view .LVU253 + 714 018c FFF7FEFF bl USBD_CtlError + 715 .LVL91: + 716 0190 62E7 b .L11 + 717 .LVL92: + 718 .L40: + 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 719 .loc 1 573 7 is_stmt 1 view .LVU254 + 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 720 .loc 1 573 13 is_stmt 0 view .LVU255 + 721 0192 2046 mov r0, r4 + 722 .LVL93: + 573:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 723 .loc 1 573 13 view .LVU256 + 724 0194 FFF7FEFF bl USBD_CtlSendStatus + 725 .LVL94: + 726 0198 5EE7 b .L11 + 727 .cfi_endproc + 728 .LFE148: + 730 .section .text.USBD_SetAddress,"ax",%progbits + 731 .align 1 + 732 .syntax unified + 733 .thumb + 734 .thumb_func + 735 .fpu fpv5-d16 + 737 USBD_SetAddress: + 738 .LVL95: + 739 .LFB149: + 586:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t dev_addr; + 740 .loc 1 586 1 is_stmt 1 view -0 + 741 .cfi_startproc + 742 @ args = 0, pretend = 0, frame = 0 + 743 @ frame_needed = 0, uses_anonymous_args = 0 + 586:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t dev_addr; + 744 .loc 1 586 1 is_stmt 0 view .LVU258 + 745 0000 38B5 push {r3, r4, r5, lr} + 746 .LCFI6: + 747 .cfi_def_cfa_offset 16 + 748 .cfi_offset 3, -16 + 749 .cfi_offset 4, -12 + 750 .cfi_offset 5, -8 + 751 .cfi_offset 14, -4 + 752 0002 0446 mov r4, r0 + 587:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 753 .loc 1 587 3 is_stmt 1 view .LVU259 + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 754 .loc 1 589 3 view .LVU260 + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 755 .loc 1 589 11 is_stmt 0 view .LVU261 + ARM GAS /tmp/cc37ZWv9.s page 40 + + + 756 0004 8B88 ldrh r3, [r1, #4] + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 757 .loc 1 589 6 view .LVU262 + 758 0006 F3B9 cbnz r3, .L45 + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 759 .loc 1 589 34 discriminator 1 view .LVU263 + 760 0008 CB88 ldrh r3, [r1, #6] + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 761 .loc 1 589 27 discriminator 1 view .LVU264 + 762 000a E3B9 cbnz r3, .L45 + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 763 .loc 1 589 58 discriminator 2 view .LVU265 + 764 000c 4B88 ldrh r3, [r1, #2] + 589:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 765 .loc 1 589 51 discriminator 2 view .LVU266 + 766 000e 7F2B cmp r3, #127 + 767 0010 19D8 bhi .L45 + 591:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 768 .loc 1 591 5 is_stmt 1 view .LVU267 + 591:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 769 .loc 1 591 14 is_stmt 0 view .LVU268 + 770 0012 03F07F05 and r5, r3, #127 + 771 .LVL96: + 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 772 .loc 1 593 5 is_stmt 1 view .LVU269 + 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 773 .loc 1 593 13 is_stmt 0 view .LVU270 + 774 0016 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 593:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 775 .loc 1 593 8 view .LVU271 + 776 001a 032B cmp r3, #3 + 777 001c 0CD0 beq .L50 + 599:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_SetUSBAddress(pdev, dev_addr); + 778 .loc 1 599 7 is_stmt 1 view .LVU272 + 599:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_SetUSBAddress(pdev, dev_addr); + 779 .loc 1 599 25 is_stmt 0 view .LVU273 + 780 001e 80F89E52 strb r5, [r0, #670] + 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 781 .loc 1 600 7 is_stmt 1 view .LVU274 + 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 782 .loc 1 600 13 is_stmt 0 view .LVU275 + 783 0022 2946 mov r1, r5 + 784 .LVL97: + 600:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 785 .loc 1 600 13 view .LVU276 + 786 0024 FFF7FEFF bl USBD_LL_SetUSBAddress + 787 .LVL98: + 601:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 788 .loc 1 601 7 is_stmt 1 view .LVU277 + 601:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 789 .loc 1 601 13 is_stmt 0 view .LVU278 + 790 0028 2046 mov r0, r4 + 791 002a FFF7FEFF bl USBD_CtlSendStatus + 792 .LVL99: + 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 793 .loc 1 603 7 is_stmt 1 view .LVU279 + 603:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + ARM GAS /tmp/cc37ZWv9.s page 41 + + + 794 .loc 1 603 10 is_stmt 0 view .LVU280 + 795 002e 35B1 cbz r5, .L48 + 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 796 .loc 1 605 9 is_stmt 1 view .LVU281 + 605:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 797 .loc 1 605 25 is_stmt 0 view .LVU282 + 798 0030 0223 movs r3, #2 + 799 0032 84F89C32 strb r3, [r4, #668] + 800 0036 09E0 b .L44 + 801 .LVL100: + 802 .L50: + 595:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 803 .loc 1 595 7 is_stmt 1 view .LVU283 + 804 0038 FFF7FEFF bl USBD_CtlError + 805 .LVL101: + 595:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 806 .loc 1 595 7 is_stmt 0 view .LVU284 + 807 003c 06E0 b .L44 + 808 .L48: + 609:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 809 .loc 1 609 9 is_stmt 1 view .LVU285 + 609:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 810 .loc 1 609 25 is_stmt 0 view .LVU286 + 811 003e 0123 movs r3, #1 + 812 0040 84F89C32 strb r3, [r4, #668] + 813 0044 02E0 b .L44 + 814 .LVL102: + 815 .L45: + 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 816 .loc 1 615 5 is_stmt 1 view .LVU287 + 817 0046 2046 mov r0, r4 + 818 .LVL103: + 615:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 819 .loc 1 615 5 is_stmt 0 view .LVU288 + 820 0048 FFF7FEFF bl USBD_CtlError + 821 .LVL104: + 822 .L44: + 617:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 823 .loc 1 617 1 view .LVU289 + 824 004c 38BD pop {r3, r4, r5, pc} + 617:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 825 .loc 1 617 1 view .LVU290 + 826 .cfi_endproc + 827 .LFE149: + 829 .section .text.USBD_SetConfig,"ax",%progbits + 830 .align 1 + 831 .syntax unified + 832 .thumb + 833 .thumb_func + 834 .fpu fpv5-d16 + 836 USBD_SetConfig: + 837 .LVL105: + 838 .LFB150: + 627:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 839 .loc 1 627 1 is_stmt 1 view -0 + 840 .cfi_startproc + 841 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/cc37ZWv9.s page 42 + + + 842 @ frame_needed = 0, uses_anonymous_args = 0 + 627:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 843 .loc 1 627 1 is_stmt 0 view .LVU292 + 844 0000 70B5 push {r4, r5, r6, lr} + 845 .LCFI7: + 846 .cfi_def_cfa_offset 16 + 847 .cfi_offset 4, -16 + 848 .cfi_offset 5, -12 + 849 .cfi_offset 6, -8 + 850 .cfi_offset 14, -4 + 851 0002 0446 mov r4, r0 + 852 0004 0E46 mov r6, r1 + 628:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t cfgidx; + 853 .loc 1 628 3 is_stmt 1 view .LVU293 + 854 .LVL106: + 629:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 855 .loc 1 629 3 view .LVU294 + 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 856 .loc 1 631 3 view .LVU295 + 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 857 .loc 1 631 12 is_stmt 0 view .LVU296 + 858 0006 8D78 ldrb r5, [r1, #2] @ zero_extendqisi2 + 631:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 859 .loc 1 631 10 view .LVU297 + 860 0008 2D4B ldr r3, .L66 + 861 000a 1D70 strb r5, [r3] + 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 862 .loc 1 633 3 is_stmt 1 view .LVU298 + 633:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 863 .loc 1 633 6 is_stmt 0 view .LVU299 + 864 000c 012D cmp r5, #1 + 865 000e 0FD8 bhi .L64 + 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 866 .loc 1 639 3 is_stmt 1 view .LVU300 + 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 867 .loc 1 639 15 is_stmt 0 view .LVU301 + 868 0010 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 639:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 869 .loc 1 639 3 view .LVU302 + 870 0014 022B cmp r3, #2 + 871 0016 0FD0 beq .L54 + 872 0018 032B cmp r3, #3 + 873 001a 23D0 beq .L55 + 700:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, cfgidx); + 874 .loc 1 700 5 is_stmt 1 view .LVU303 + 875 001c FFF7FEFF bl USBD_CtlError + 876 .LVL107: + 701:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = USBD_FAIL; + 877 .loc 1 701 5 view .LVU304 + 701:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ret = USBD_FAIL; + 878 .loc 1 701 11 is_stmt 0 view .LVU305 + 879 0020 274B ldr r3, .L66 + 880 0022 1978 ldrb r1, [r3] @ zero_extendqisi2 + 881 0024 2046 mov r0, r4 + 882 0026 FFF7FEFF bl USBD_ClrClassConfig + 883 .LVL108: + 702:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + ARM GAS /tmp/cc37ZWv9.s page 43 + + + 884 .loc 1 702 5 is_stmt 1 view .LVU306 + 703:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 885 .loc 1 703 5 view .LVU307 + 702:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 886 .loc 1 702 9 is_stmt 0 view .LVU308 + 887 002a 0325 movs r5, #3 + 888 .LVL109: + 889 .L53: + 707:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 890 .loc 1 707 1 view .LVU309 + 891 002c 2846 mov r0, r5 + 892 002e 70BD pop {r4, r5, r6, pc} + 893 .LVL110: + 894 .L64: + 635:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** return USBD_FAIL; + 895 .loc 1 635 5 is_stmt 1 view .LVU310 + 896 0030 FFF7FEFF bl USBD_CtlError + 897 .LVL111: + 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 898 .loc 1 636 5 view .LVU311 + 636:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 899 .loc 1 636 12 is_stmt 0 view .LVU312 + 900 0034 0325 movs r5, #3 + 901 0036 F9E7 b .L53 + 902 .LVL112: + 903 .L54: + 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 904 .loc 1 642 5 is_stmt 1 view .LVU313 + 642:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 905 .loc 1 642 8 is_stmt 0 view .LVU314 + 906 0038 8DB1 cbz r5, .L57 + 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 907 .loc 1 644 7 is_stmt 1 view .LVU315 + 644:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 908 .loc 1 644 24 is_stmt 0 view .LVU316 + 909 003a 4560 str r5, [r0, #4] + 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 910 .loc 1 646 7 is_stmt 1 view .LVU317 + 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 911 .loc 1 646 13 is_stmt 0 view .LVU318 + 912 003c 2946 mov r1, r5 + 913 .LVL113: + 646:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 914 .loc 1 646 13 view .LVU319 + 915 003e FFF7FEFF bl USBD_SetClassConfig + 916 .LVL114: + 648:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 917 .loc 1 648 7 is_stmt 1 view .LVU320 + 648:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 918 .loc 1 648 10 is_stmt 0 view .LVU321 + 919 0042 0546 mov r5, r0 + 920 0044 20B1 cbz r0, .L58 + 650:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 921 .loc 1 650 9 is_stmt 1 view .LVU322 + 922 0046 3146 mov r1, r6 + 923 0048 2046 mov r0, r4 + 924 .LVL115: + ARM GAS /tmp/cc37ZWv9.s page 44 + + + 650:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 925 .loc 1 650 9 is_stmt 0 view .LVU323 + 926 004a FFF7FEFF bl USBD_CtlError + 927 .LVL116: + 928 004e EDE7 b .L53 + 929 .LVL117: + 930 .L58: + 654:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_CONFIGURED; + 931 .loc 1 654 9 is_stmt 1 view .LVU324 + 654:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_CONFIGURED; + 932 .loc 1 654 15 is_stmt 0 view .LVU325 + 933 0050 2046 mov r0, r4 + 934 .LVL118: + 654:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_CONFIGURED; + 935 .loc 1 654 15 view .LVU326 + 936 0052 FFF7FEFF bl USBD_CtlSendStatus + 937 .LVL119: + 655:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 938 .loc 1 655 9 is_stmt 1 view .LVU327 + 655:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 939 .loc 1 655 25 is_stmt 0 view .LVU328 + 940 0056 0323 movs r3, #3 + 941 0058 84F89C32 strb r3, [r4, #668] + 942 005c E6E7 b .L53 + 943 .LVL120: + 944 .L57: + 660:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 945 .loc 1 660 7 is_stmt 1 view .LVU329 + 660:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 946 .loc 1 660 13 is_stmt 0 view .LVU330 + 947 005e FFF7FEFF bl USBD_CtlSendStatus + 948 .LVL121: + 660:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 949 .loc 1 660 13 view .LVU331 + 950 0062 E3E7 b .L53 + 951 .LVL122: + 952 .L55: + 665:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 953 .loc 1 665 5 is_stmt 1 view .LVU332 + 665:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 954 .loc 1 665 8 is_stmt 0 view .LVU333 + 955 0064 CDB1 cbz r5, .L65 + 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 956 .loc 1 672 10 is_stmt 1 view .LVU334 + 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 957 .loc 1 672 28 is_stmt 0 view .LVU335 + 958 0066 4168 ldr r1, [r0, #4] + 959 .LVL123: + 672:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 960 .loc 1 672 13 view .LVU336 + 961 0068 8D42 cmp r5, r1 + 962 006a 25D0 beq .L60 + 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 963 .loc 1 675 7 is_stmt 1 view .LVU337 + 675:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 964 .loc 1 675 13 is_stmt 0 view .LVU338 + 965 006c C9B2 uxtb r1, r1 + ARM GAS /tmp/cc37ZWv9.s page 45 + + + 966 006e FFF7FEFF bl USBD_ClrClassConfig + 967 .LVL124: + 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 968 .loc 1 678 7 is_stmt 1 view .LVU339 + 678:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 969 .loc 1 678 24 is_stmt 0 view .LVU340 + 970 0072 134B ldr r3, .L66 + 971 0074 1978 ldrb r1, [r3] @ zero_extendqisi2 + 972 0076 6160 str r1, [r4, #4] + 680:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 973 .loc 1 680 7 is_stmt 1 view .LVU341 + 680:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 974 .loc 1 680 13 is_stmt 0 view .LVU342 + 975 0078 2046 mov r0, r4 + 976 007a FFF7FEFF bl USBD_SetClassConfig + 977 .LVL125: + 682:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 978 .loc 1 682 7 is_stmt 1 view .LVU343 + 682:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 979 .loc 1 682 10 is_stmt 0 view .LVU344 + 980 007e 0546 mov r5, r0 + 981 0080 B0B1 cbz r0, .L61 + 684:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + 982 .loc 1 684 9 is_stmt 1 view .LVU345 + 983 0082 3146 mov r1, r6 + 984 0084 2046 mov r0, r4 + 985 .LVL126: + 684:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + 986 .loc 1 684 9 is_stmt 0 view .LVU346 + 987 0086 FFF7FEFF bl USBD_CtlError + 988 .LVL127: + 685:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_ADDRESSED; + 989 .loc 1 685 9 is_stmt 1 view .LVU347 + 685:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_state = USBD_STATE_ADDRESSED; + 990 .loc 1 685 15 is_stmt 0 view .LVU348 + 991 008a 2179 ldrb r1, [r4, #4] @ zero_extendqisi2 + 992 008c 2046 mov r0, r4 + 993 008e FFF7FEFF bl USBD_ClrClassConfig + 994 .LVL128: + 686:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 995 .loc 1 686 9 is_stmt 1 view .LVU349 + 686:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 996 .loc 1 686 25 is_stmt 0 view .LVU350 + 997 0092 0223 movs r3, #2 + 998 0094 84F89C32 strb r3, [r4, #668] + 999 0098 C8E7 b .L53 + 1000 .LVL129: + 1001 .L65: + 667:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config = cfgidx; + 1002 .loc 1 667 7 is_stmt 1 view .LVU351 + 667:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdev->dev_config = cfgidx; + 1003 .loc 1 667 23 is_stmt 0 view .LVU352 + 1004 009a 0223 movs r3, #2 + 1005 009c 80F89C32 strb r3, [r0, #668] + 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, cfgidx); + 1006 .loc 1 668 7 is_stmt 1 view .LVU353 + 668:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_ClrClassConfig(pdev, cfgidx); + ARM GAS /tmp/cc37ZWv9.s page 46 + + + 1007 .loc 1 668 24 is_stmt 0 view .LVU354 + 1008 00a0 4560 str r5, [r0, #4] + 669:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 1009 .loc 1 669 7 is_stmt 1 view .LVU355 + 669:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 1010 .loc 1 669 13 is_stmt 0 view .LVU356 + 1011 00a2 2946 mov r1, r5 + 1012 .LVL130: + 669:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 1013 .loc 1 669 13 view .LVU357 + 1014 00a4 FFF7FEFF bl USBD_ClrClassConfig + 1015 .LVL131: + 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1016 .loc 1 670 7 is_stmt 1 view .LVU358 + 670:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1017 .loc 1 670 13 is_stmt 0 view .LVU359 + 1018 00a8 2046 mov r0, r4 + 1019 00aa FFF7FEFF bl USBD_CtlSendStatus + 1020 .LVL132: + 1021 00ae BDE7 b .L53 + 1022 .LVL133: + 1023 .L61: + 690:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1024 .loc 1 690 9 is_stmt 1 view .LVU360 + 690:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1025 .loc 1 690 15 is_stmt 0 view .LVU361 + 1026 00b0 2046 mov r0, r4 + 1027 .LVL134: + 690:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1028 .loc 1 690 15 view .LVU362 + 1029 00b2 FFF7FEFF bl USBD_CtlSendStatus + 1030 .LVL135: + 1031 00b6 B9E7 b .L53 + 1032 .LVL136: + 1033 .L60: + 695:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1034 .loc 1 695 7 is_stmt 1 view .LVU363 + 695:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1035 .loc 1 695 13 is_stmt 0 view .LVU364 + 1036 00b8 FFF7FEFF bl USBD_CtlSendStatus + 1037 .LVL137: + 628:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** static uint8_t cfgidx; + 1038 .loc 1 628 22 view .LVU365 + 1039 00bc 0025 movs r5, #0 + 1040 00be B5E7 b .L53 + 1041 .L67: + 1042 .align 2 + 1043 .L66: + 1044 00c0 00000000 .word .LANCHOR0 + 1045 .cfi_endproc + 1046 .LFE150: + 1048 .section .text.USBD_GetConfig,"ax",%progbits + 1049 .align 1 + 1050 .syntax unified + 1051 .thumb + 1052 .thumb_func + 1053 .fpu fpv5-d16 + ARM GAS /tmp/cc37ZWv9.s page 47 + + + 1055 USBD_GetConfig: + 1056 .LVL138: + 1057 .LFB151: + 717:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wLength != 1U) + 1058 .loc 1 717 1 is_stmt 1 view -0 + 1059 .cfi_startproc + 1060 @ args = 0, pretend = 0, frame = 0 + 1061 @ frame_needed = 0, uses_anonymous_args = 0 + 717:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** if (req->wLength != 1U) + 1062 .loc 1 717 1 is_stmt 0 view .LVU367 + 1063 0000 08B5 push {r3, lr} + 1064 .LCFI8: + 1065 .cfi_def_cfa_offset 8 + 1066 .cfi_offset 3, -8 + 1067 .cfi_offset 14, -4 + 718:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1068 .loc 1 718 3 is_stmt 1 view .LVU368 + 718:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1069 .loc 1 718 10 is_stmt 0 view .LVU369 + 1070 0002 CB88 ldrh r3, [r1, #6] + 718:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1071 .loc 1 718 6 view .LVU370 + 1072 0004 012B cmp r3, #1 + 1073 0006 0AD1 bne .L76 + 724:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1074 .loc 1 724 5 is_stmt 1 view .LVU371 + 724:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1075 .loc 1 724 17 is_stmt 0 view .LVU372 + 1076 0008 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 724:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1077 .loc 1 724 5 view .LVU373 + 1078 000c 022B cmp r3, #2 + 1079 000e 09D9 bls .L77 + 1080 0010 032B cmp r3, #3 + 1081 0012 09D1 bne .L73 + 733:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1082 .loc 1 733 7 is_stmt 1 view .LVU374 + 733:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1083 .loc 1 733 13 is_stmt 0 view .LVU375 + 1084 0014 0122 movs r2, #1 + 1085 0016 011D adds r1, r0, #4 + 1086 .LVL139: + 733:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1087 .loc 1 733 13 view .LVU376 + 1088 0018 FFF7FEFF bl USBD_CtlSendData + 1089 .LVL140: + 734:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1090 .loc 1 734 7 is_stmt 1 view .LVU377 + 1091 001c 01E0 b .L68 + 1092 .LVL141: + 1093 .L76: + 720:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1094 .loc 1 720 5 view .LVU378 + 1095 001e FFF7FEFF bl USBD_CtlError + 1096 .LVL142: + 1097 .L68: + 741:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + ARM GAS /tmp/cc37ZWv9.s page 48 + + + 1098 .loc 1 741 1 is_stmt 0 view .LVU379 + 1099 0022 08BD pop {r3, pc} + 1100 .LVL143: + 1101 .L77: + 724:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1102 .loc 1 724 5 view .LVU380 + 1103 0024 5BB2 sxtb r3, r3 + 1104 0026 13B9 cbnz r3, .L78 + 1105 .L73: + 737:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1106 .loc 1 737 7 is_stmt 1 view .LVU381 + 1107 0028 FFF7FEFF bl USBD_CtlError + 1108 .LVL144: + 738:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1109 .loc 1 738 7 view .LVU382 + 741:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1110 .loc 1 741 1 is_stmt 0 view .LVU383 + 1111 002c F9E7 b .L68 + 1112 .LVL145: + 1113 .L78: + 728:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + 1114 .loc 1 728 7 is_stmt 1 view .LVU384 + 728:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + 1115 .loc 1 728 32 is_stmt 0 view .LVU385 + 1116 002e 0146 mov r1, r0 + 1117 .LVL146: + 728:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + 1118 .loc 1 728 32 view .LVU386 + 1119 0030 0023 movs r3, #0 + 1120 0032 41F8083F str r3, [r1, #8]! + 729:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1121 .loc 1 729 7 is_stmt 1 view .LVU387 + 729:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1122 .loc 1 729 13 is_stmt 0 view .LVU388 + 1123 0036 0122 movs r2, #1 + 1124 0038 FFF7FEFF bl USBD_CtlSendData + 1125 .LVL147: + 730:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1126 .loc 1 730 7 is_stmt 1 view .LVU389 + 1127 003c F1E7 b .L68 + 1128 .cfi_endproc + 1129 .LFE151: + 1131 .section .text.USBD_GetStatus,"ax",%progbits + 1132 .align 1 + 1133 .syntax unified + 1134 .thumb + 1135 .thumb_func + 1136 .fpu fpv5-d16 + 1138 USBD_GetStatus: + 1139 .LVL148: + 1140 .LFB152: + 751:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 1141 .loc 1 751 1 view -0 + 1142 .cfi_startproc + 1143 @ args = 0, pretend = 0, frame = 0 + 1144 @ frame_needed = 0, uses_anonymous_args = 0 + 751:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + ARM GAS /tmp/cc37ZWv9.s page 49 + + + 1145 .loc 1 751 1 is_stmt 0 view .LVU391 + 1146 0000 08B5 push {r3, lr} + 1147 .LCFI9: + 1148 .cfi_def_cfa_offset 8 + 1149 .cfi_offset 3, -8 + 1150 .cfi_offset 14, -4 + 752:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1151 .loc 1 752 3 is_stmt 1 view .LVU392 + 752:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1152 .loc 1 752 15 is_stmt 0 view .LVU393 + 1153 0002 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 752:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1154 .loc 1 752 3 view .LVU394 + 1155 0006 013B subs r3, r3, #1 + 1156 0008 022B cmp r3, #2 + 1157 000a 12D8 bhi .L80 + 757:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1158 .loc 1 757 5 is_stmt 1 view .LVU395 + 757:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1159 .loc 1 757 12 is_stmt 0 view .LVU396 + 1160 000c CB88 ldrh r3, [r1, #6] + 757:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1161 .loc 1 757 8 view .LVU397 + 1162 000e 022B cmp r3, #2 + 1163 0010 0CD1 bne .L85 + 764:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else + 1164 .loc 1 764 5 is_stmt 1 view .LVU398 + 764:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** #else + 1165 .loc 1 764 29 is_stmt 0 view .LVU399 + 1166 0012 0123 movs r3, #1 + 1167 0014 C360 str r3, [r0, #12] + 769:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1168 .loc 1 769 5 is_stmt 1 view .LVU400 + 769:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1169 .loc 1 769 13 is_stmt 0 view .LVU401 + 1170 0016 D0F8A432 ldr r3, [r0, #676] + 769:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1171 .loc 1 769 8 view .LVU402 + 1172 001a 0BB1 cbz r3, .L83 + 771:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1173 .loc 1 771 7 is_stmt 1 view .LVU403 + 771:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1174 .loc 1 771 31 is_stmt 0 view .LVU404 + 1175 001c 0323 movs r3, #3 + 1176 001e C360 str r3, [r0, #12] + 1177 .L83: + 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1178 .loc 1 774 5 is_stmt 1 view .LVU405 + 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1179 .loc 1 774 11 is_stmt 0 view .LVU406 + 1180 0020 0222 movs r2, #2 + 1181 0022 00F10C01 add r1, r0, #12 + 1182 .LVL149: + 774:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1183 .loc 1 774 11 view .LVU407 + 1184 0026 FFF7FEFF bl USBD_CtlSendData + 1185 .LVL150: + ARM GAS /tmp/cc37ZWv9.s page 50 + + + 775:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1186 .loc 1 775 5 is_stmt 1 view .LVU408 + 1187 .L79: + 781:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1188 .loc 1 781 1 is_stmt 0 view .LVU409 + 1189 002a 08BD pop {r3, pc} + 1190 .LVL151: + 1191 .L85: + 759:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1192 .loc 1 759 7 is_stmt 1 view .LVU410 + 1193 002c FFF7FEFF bl USBD_CtlError + 1194 .LVL152: + 760:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1195 .loc 1 760 7 view .LVU411 + 1196 0030 FBE7 b .L79 + 1197 .LVL153: + 1198 .L80: + 778:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1199 .loc 1 778 5 view .LVU412 + 1200 0032 FFF7FEFF bl USBD_CtlError + 1201 .LVL154: + 779:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1202 .loc 1 779 5 view .LVU413 + 781:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1203 .loc 1 781 1 is_stmt 0 view .LVU414 + 1204 0036 F8E7 b .L79 + 1205 .cfi_endproc + 1206 .LFE152: + 1208 .section .text.USBD_ClrFeature,"ax",%progbits + 1209 .align 1 + 1210 .syntax unified + 1211 .thumb + 1212 .thumb_func + 1213 .fpu fpv5-d16 + 1215 USBD_ClrFeature: + 1216 .LVL155: + 1217 .LFB154: + 809:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 1218 .loc 1 809 1 is_stmt 1 view -0 + 1219 .cfi_startproc + 1220 @ args = 0, pretend = 0, frame = 0 + 1221 @ frame_needed = 0, uses_anonymous_args = 0 + 809:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** switch (pdev->dev_state) + 1222 .loc 1 809 1 is_stmt 0 view .LVU416 + 1223 0000 08B5 push {r3, lr} + 1224 .LCFI10: + 1225 .cfi_def_cfa_offset 8 + 1226 .cfi_offset 3, -8 + 1227 .cfi_offset 14, -4 + 810:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1228 .loc 1 810 3 is_stmt 1 view .LVU417 + 810:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1229 .loc 1 810 15 is_stmt 0 view .LVU418 + 1230 0002 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 810:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1231 .loc 1 810 3 view .LVU419 + 1232 0006 013B subs r3, r3, #1 + ARM GAS /tmp/cc37ZWv9.s page 51 + + + 1233 0008 022B cmp r3, #2 + 1234 000a 09D8 bhi .L87 + 815:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1235 .loc 1 815 7 is_stmt 1 view .LVU420 + 815:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1236 .loc 1 815 14 is_stmt 0 view .LVU421 + 1237 000c 4B88 ldrh r3, [r1, #2] + 815:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1238 .loc 1 815 10 view .LVU422 + 1239 000e 012B cmp r3, #1 + 1240 0010 00D0 beq .L90 + 1241 .LVL156: + 1242 .L86: + 826:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1243 .loc 1 826 1 view .LVU423 + 1244 0012 08BD pop {r3, pc} + 1245 .LVL157: + 1246 .L90: + 817:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 1247 .loc 1 817 9 is_stmt 1 view .LVU424 + 817:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_CtlSendStatus(pdev); + 1248 .loc 1 817 33 is_stmt 0 view .LVU425 + 1249 0014 0023 movs r3, #0 + 1250 0016 C0F8A432 str r3, [r0, #676] + 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1251 .loc 1 818 9 is_stmt 1 view .LVU426 + 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1252 .loc 1 818 15 is_stmt 0 view .LVU427 + 1253 001a FFF7FEFF bl USBD_CtlSendStatus + 1254 .LVL158: + 818:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1255 .loc 1 818 15 view .LVU428 + 1256 001e F8E7 b .L86 + 1257 .LVL159: + 1258 .L87: + 823:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1259 .loc 1 823 7 is_stmt 1 view .LVU429 + 1260 0020 FFF7FEFF bl USBD_CtlError + 1261 .LVL160: + 824:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1262 .loc 1 824 7 view .LVU430 + 826:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1263 .loc 1 826 1 is_stmt 0 view .LVU431 + 1264 0024 F5E7 b .L86 + 1265 .cfi_endproc + 1266 .LFE154: + 1268 .section .text.USBD_StdDevReq,"ax",%progbits + 1269 .align 1 + 1270 .global USBD_StdDevReq + 1271 .syntax unified + 1272 .thumb + 1273 .thumb_func + 1274 .fpu fpv5-d16 + 1276 USBD_StdDevReq: + 1277 .LVL161: + 1278 .LFB145: + 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + ARM GAS /tmp/cc37ZWv9.s page 52 + + + 1279 .loc 1 101 1 is_stmt 1 view -0 + 1280 .cfi_startproc + 1281 @ args = 0, pretend = 0, frame = 0 + 1282 @ frame_needed = 0, uses_anonymous_args = 0 + 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 1283 .loc 1 101 1 is_stmt 0 view .LVU433 + 1284 0000 38B5 push {r3, r4, r5, lr} + 1285 .LCFI11: + 1286 .cfi_def_cfa_offset 16 + 1287 .cfi_offset 3, -16 + 1288 .cfi_offset 4, -12 + 1289 .cfi_offset 5, -8 + 1290 .cfi_offset 14, -4 + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1291 .loc 1 102 3 is_stmt 1 view .LVU434 + 1292 .LVL162: + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1293 .loc 1 104 3 view .LVU435 + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1294 .loc 1 104 14 is_stmt 0 view .LVU436 + 1295 0002 0C78 ldrb r4, [r1] @ zero_extendqisi2 + 1296 0004 04F06004 and r4, r4, #96 + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1297 .loc 1 104 3 view .LVU437 + 1298 0008 202C cmp r4, #32 + 1299 000a 06D0 beq .L92 + 1300 000c 402C cmp r4, #64 + 1301 000e 04D0 beq .L92 + 1302 0010 54B1 cbz r4, .L107 + 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1303 .loc 1 149 5 is_stmt 1 view .LVU438 + 1304 0012 FFF7FEFF bl USBD_CtlError + 1305 .LVL163: + 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1306 .loc 1 150 5 view .LVU439 + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1307 .loc 1 102 22 is_stmt 0 view .LVU440 + 1308 0016 0024 movs r4, #0 + 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1309 .loc 1 150 5 view .LVU441 + 1310 0018 04E0 b .L95 + 1311 .LVL164: + 1312 .L92: + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1313 .loc 1 108 5 is_stmt 1 view .LVU442 + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1314 .loc 1 108 35 is_stmt 0 view .LVU443 + 1315 001a D0F8B832 ldr r3, [r0, #696] + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1316 .loc 1 108 43 view .LVU444 + 1317 001e 9B68 ldr r3, [r3, #8] + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1318 .loc 1 108 31 view .LVU445 + 1319 0020 9847 blx r3 + 1320 .LVL165: + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1321 .loc 1 108 31 view .LVU446 + ARM GAS /tmp/cc37ZWv9.s page 53 + + + 1322 0022 0446 mov r4, r0 + 1323 .LVL166: + 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1324 .loc 1 109 5 is_stmt 1 view .LVU447 + 1325 .L95: + 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1326 .loc 1 153 3 view .LVU448 + 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1327 .loc 1 154 1 is_stmt 0 view .LVU449 + 1328 0024 2046 mov r0, r4 + 1329 0026 38BD pop {r3, r4, r5, pc} + 1330 .LVL167: + 1331 .L107: + 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1332 .loc 1 112 5 is_stmt 1 view .LVU450 + 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1333 .loc 1 112 16 is_stmt 0 view .LVU451 + 1334 0028 4D78 ldrb r5, [r1, #1] @ zero_extendqisi2 + 1335 002a 092D cmp r5, #9 + 1336 002c 1DD8 bhi .L96 + 1337 002e DFE805F0 tbb [pc, r5] + 1338 .L98: + 1339 0032 12 .byte (.L104-.L98)/2 + 1340 0033 19 .byte (.L103-.L98)/2 + 1341 0034 1C .byte (.L96-.L98)/2 + 1342 0035 16 .byte (.L102-.L98)/2 + 1343 0036 1C .byte (.L96-.L98)/2 + 1344 0037 08 .byte (.L101-.L98)/2 + 1345 0038 05 .byte (.L100-.L98)/2 + 1346 0039 1C .byte (.L96-.L98)/2 + 1347 003a 0F .byte (.L99-.L98)/2 + 1348 003b 0B .byte (.L97-.L98)/2 + 1349 .p2align 1 + 1350 .L100: + 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1351 .loc 1 115 7 is_stmt 1 view .LVU452 + 1352 003c FFF7FEFF bl USBD_GetDescriptor + 1353 .LVL168: + 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1354 .loc 1 116 7 view .LVU453 + 1355 0040 F0E7 b .L95 + 1356 .LVL169: + 1357 .L101: + 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1358 .loc 1 119 7 view .LVU454 + 1359 0042 FFF7FEFF bl USBD_SetAddress + 1360 .LVL170: + 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1361 .loc 1 120 7 view .LVU455 + 1362 0046 EDE7 b .L95 + 1363 .LVL171: + 1364 .L97: + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1365 .loc 1 123 7 view .LVU456 + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1366 .loc 1 123 13 is_stmt 0 view .LVU457 + 1367 0048 FFF7FEFF bl USBD_SetConfig + ARM GAS /tmp/cc37ZWv9.s page 54 + + + 1368 .LVL172: + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1369 .loc 1 123 13 view .LVU458 + 1370 004c 0446 mov r4, r0 + 1371 .LVL173: + 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1372 .loc 1 124 7 is_stmt 1 view .LVU459 + 1373 004e E9E7 b .L95 + 1374 .LVL174: + 1375 .L99: + 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1376 .loc 1 127 7 view .LVU460 + 1377 0050 FFF7FEFF bl USBD_GetConfig + 1378 .LVL175: + 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1379 .loc 1 128 7 view .LVU461 + 1380 0054 E6E7 b .L95 + 1381 .LVL176: + 1382 .L104: + 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1383 .loc 1 131 7 view .LVU462 + 1384 0056 FFF7FEFF bl USBD_GetStatus + 1385 .LVL177: + 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1386 .loc 1 132 7 view .LVU463 + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1387 .loc 1 102 22 is_stmt 0 view .LVU464 + 1388 005a 2C46 mov r4, r5 + 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1389 .loc 1 132 7 view .LVU465 + 1390 005c E2E7 b .L95 + 1391 .LVL178: + 1392 .L102: + 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1393 .loc 1 135 7 is_stmt 1 view .LVU466 + 1394 005e FFF7FEFF bl USBD_SetFeature + 1395 .LVL179: + 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1396 .loc 1 136 7 view .LVU467 + 1397 0062 DFE7 b .L95 + 1398 .LVL180: + 1399 .L103: + 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1400 .loc 1 139 7 view .LVU468 + 1401 0064 FFF7FEFF bl USBD_ClrFeature + 1402 .LVL181: + 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1403 .loc 1 140 7 view .LVU469 + 1404 0068 DCE7 b .L95 + 1405 .LVL182: + 1406 .L96: + 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1407 .loc 1 143 7 view .LVU470 + 1408 006a FFF7FEFF bl USBD_CtlError + 1409 .LVL183: + 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1410 .loc 1 144 7 view .LVU471 + ARM GAS /tmp/cc37ZWv9.s page 55 + + + 1411 006e D9E7 b .L95 + 1412 .cfi_endproc + 1413 .LFE145: + 1415 .section .text.USBD_StdItfReq,"ax",%progbits + 1416 .align 1 + 1417 .global USBD_StdItfReq + 1418 .syntax unified + 1419 .thumb + 1420 .thumb_func + 1421 .fpu fpv5-d16 + 1423 USBD_StdItfReq: + 1424 .LVL184: + 1425 .LFB146: + 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 1426 .loc 1 164 1 view -0 + 1427 .cfi_startproc + 1428 @ args = 0, pretend = 0, frame = 0 + 1429 @ frame_needed = 0, uses_anonymous_args = 0 + 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 1430 .loc 1 164 1 is_stmt 0 view .LVU473 + 1431 0000 70B5 push {r4, r5, r6, lr} + 1432 .LCFI12: + 1433 .cfi_def_cfa_offset 16 + 1434 .cfi_offset 4, -16 + 1435 .cfi_offset 5, -12 + 1436 .cfi_offset 6, -8 + 1437 .cfi_offset 14, -4 + 1438 0002 0546 mov r5, r0 + 1439 0004 0C46 mov r4, r1 + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1440 .loc 1 165 3 is_stmt 1 view .LVU474 + 1441 .LVL185: + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1442 .loc 1 167 3 view .LVU475 + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1443 .loc 1 167 14 is_stmt 0 view .LVU476 + 1444 0006 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 1445 0008 03F06003 and r3, r3, #96 + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1446 .loc 1 167 3 view .LVU477 + 1447 000c 202B cmp r3, #32 + 1448 000e 07D0 beq .L109 + 1449 0010 402B cmp r3, #64 + 1450 0012 05D0 beq .L109 + 1451 0014 23B1 cbz r3, .L109 + 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1452 .loc 1 200 5 is_stmt 1 view .LVU478 + 1453 0016 FFF7FEFF bl USBD_CtlError + 1454 .LVL186: + 201:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1455 .loc 1 201 5 view .LVU479 + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1456 .loc 1 165 22 is_stmt 0 view .LVU480 + 1457 001a 0026 movs r6, #0 + 1458 .LVL187: + 1459 .L113: + 204:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 56 + + + 1460 .loc 1 204 3 is_stmt 1 view .LVU481 + 205:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1461 .loc 1 205 1 is_stmt 0 view .LVU482 + 1462 001c 3046 mov r0, r6 + 1463 001e 70BD pop {r4, r5, r6, pc} + 1464 .LVL188: + 1465 .L109: + 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1466 .loc 1 172 5 is_stmt 1 view .LVU483 + 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1467 .loc 1 172 17 is_stmt 0 view .LVU484 + 1468 0020 95F89C32 ldrb r3, [r5, #668] @ zero_extendqisi2 + 1469 0024 013B subs r3, r3, #1 + 1470 0026 022B cmp r3, #2 + 1471 0028 18D8 bhi .L111 + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1472 .loc 1 178 7 is_stmt 1 view .LVU485 + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1473 .loc 1 178 11 is_stmt 0 view .LVU486 + 1474 002a 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1475 .loc 1 178 10 view .LVU487 + 1476 002c 012B cmp r3, #1 + 1477 002e 0FD8 bhi .L112 + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1478 .loc 1 180 9 is_stmt 1 view .LVU488 + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1479 .loc 1 180 39 is_stmt 0 view .LVU489 + 1480 0030 D5F8B832 ldr r3, [r5, #696] + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1481 .loc 1 180 47 view .LVU490 + 1482 0034 9B68 ldr r3, [r3, #8] + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1483 .loc 1 180 35 view .LVU491 + 1484 0036 2146 mov r1, r4 + 1485 .LVL189: + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1486 .loc 1 180 35 view .LVU492 + 1487 0038 2846 mov r0, r5 + 1488 .LVL190: + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1489 .loc 1 180 35 view .LVU493 + 1490 003a 9847 blx r3 + 1491 .LVL191: + 1492 003c 0646 mov r6, r0 + 1493 .LVL192: + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1494 .loc 1 182 9 is_stmt 1 view .LVU494 + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1495 .loc 1 182 17 is_stmt 0 view .LVU495 + 1496 003e E388 ldrh r3, [r4, #6] + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1497 .loc 1 182 12 view .LVU496 + 1498 0040 002B cmp r3, #0 + 1499 0042 EBD1 bne .L113 + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1500 .loc 1 182 34 discriminator 1 view .LVU497 + ARM GAS /tmp/cc37ZWv9.s page 57 + + + 1501 0044 0028 cmp r0, #0 + 1502 0046 E9D1 bne .L113 + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1503 .loc 1 184 11 is_stmt 1 view .LVU498 + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1504 .loc 1 184 17 is_stmt 0 view .LVU499 + 1505 0048 2846 mov r0, r5 + 1506 .LVL193: + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1507 .loc 1 184 17 view .LVU500 + 1508 004a FFF7FEFF bl USBD_CtlSendStatus + 1509 .LVL194: + 1510 004e E5E7 b .L113 + 1511 .LVL195: + 1512 .L112: + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1513 .loc 1 189 9 is_stmt 1 view .LVU501 + 1514 0050 2146 mov r1, r4 + 1515 .LVL196: + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1516 .loc 1 189 9 is_stmt 0 view .LVU502 + 1517 0052 2846 mov r0, r5 + 1518 .LVL197: + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1519 .loc 1 189 9 view .LVU503 + 1520 0054 FFF7FEFF bl USBD_CtlError + 1521 .LVL198: + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1522 .loc 1 165 22 view .LVU504 + 1523 0058 0026 movs r6, #0 + 1524 005a DFE7 b .L113 + 1525 .LVL199: + 1526 .L111: + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1527 .loc 1 194 7 is_stmt 1 view .LVU505 + 1528 005c 2146 mov r1, r4 + 1529 .LVL200: + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1530 .loc 1 194 7 is_stmt 0 view .LVU506 + 1531 005e 2846 mov r0, r5 + 1532 .LVL201: + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1533 .loc 1 194 7 view .LVU507 + 1534 0060 FFF7FEFF bl USBD_CtlError + 1535 .LVL202: + 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1536 .loc 1 195 7 is_stmt 1 view .LVU508 + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1537 .loc 1 165 22 is_stmt 0 view .LVU509 + 1538 0064 0026 movs r6, #0 + 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1539 .loc 1 195 7 view .LVU510 + 1540 0066 D9E7 b .L113 + 1541 .cfi_endproc + 1542 .LFE146: + 1544 .section .text.USBD_StdEPReq,"ax",%progbits + 1545 .align 1 + ARM GAS /tmp/cc37ZWv9.s page 58 + + + 1546 .global USBD_StdEPReq + 1547 .syntax unified + 1548 .thumb + 1549 .thumb_func + 1550 .fpu fpv5-d16 + 1552 USBD_StdEPReq: + 1553 .LVL203: + 1554 .LFB147: + 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_EndpointTypeDef *pep; + 1555 .loc 1 215 1 is_stmt 1 view -0 + 1556 .cfi_startproc + 1557 @ args = 0, pretend = 0, frame = 0 + 1558 @ frame_needed = 0, uses_anonymous_args = 0 + 215:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_EndpointTypeDef *pep; + 1559 .loc 1 215 1 is_stmt 0 view .LVU512 + 1560 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1561 .LCFI13: + 1562 .cfi_def_cfa_offset 24 + 1563 .cfi_offset 3, -24 + 1564 .cfi_offset 4, -20 + 1565 .cfi_offset 5, -16 + 1566 .cfi_offset 6, -12 + 1567 .cfi_offset 7, -8 + 1568 .cfi_offset 14, -4 + 1569 0002 0646 mov r6, r0 + 1570 0004 0D46 mov r5, r1 + 216:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t ep_addr; + 1571 .loc 1 216 3 is_stmt 1 view .LVU513 + 217:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** USBD_StatusTypeDef ret = USBD_OK; + 1572 .loc 1 217 3 view .LVU514 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1573 .loc 1 218 3 view .LVU515 + 1574 .LVL204: + 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1575 .loc 1 219 3 view .LVU516 + 219:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1576 .loc 1 219 13 is_stmt 0 view .LVU517 + 1577 0006 8B88 ldrh r3, [r1, #4] + 1578 .LVL205: + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1579 .loc 1 221 3 is_stmt 1 view .LVU518 + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1580 .loc 1 221 14 is_stmt 0 view .LVU519 + 1581 0008 0C78 ldrb r4, [r1] @ zero_extendqisi2 + 1582 000a 04F06004 and r4, r4, #96 + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1583 .loc 1 221 3 view .LVU520 + 1584 000e 202C cmp r4, #32 + 1585 0010 08D0 beq .L116 + 1586 0012 D9B2 uxtb r1, r3 + 1587 .LVL206: + 221:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1588 .loc 1 221 3 view .LVU521 + 1589 0014 402C cmp r4, #64 + 1590 0016 05D0 beq .L116 + 1591 0018 6CB1 cbz r4, .L153 + 365:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + ARM GAS /tmp/cc37ZWv9.s page 59 + + + 1592 .loc 1 365 5 is_stmt 1 view .LVU522 + 1593 001a 2946 mov r1, r5 + 1594 001c FFF7FEFF bl USBD_CtlError + 1595 .LVL207: + 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1596 .loc 1 366 5 view .LVU523 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1597 .loc 1 218 22 is_stmt 0 view .LVU524 + 1598 0020 0024 movs r4, #0 + 366:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1599 .loc 1 366 5 view .LVU525 + 1600 0022 06E0 b .L119 + 1601 .LVL208: + 1602 .L116: + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1603 .loc 1 225 5 is_stmt 1 view .LVU526 + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1604 .loc 1 225 35 is_stmt 0 view .LVU527 + 1605 0024 D6F8B832 ldr r3, [r6, #696] + 1606 .LVL209: + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1607 .loc 1 225 43 view .LVU528 + 1608 0028 9B68 ldr r3, [r3, #8] + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1609 .loc 1 225 31 view .LVU529 + 1610 002a 2946 mov r1, r5 + 1611 002c 3046 mov r0, r6 + 1612 .LVL210: + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1613 .loc 1 225 31 view .LVU530 + 1614 002e 9847 blx r3 + 1615 .LVL211: + 225:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1616 .loc 1 225 31 view .LVU531 + 1617 0030 0446 mov r4, r0 + 1618 .LVL212: + 226:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1619 .loc 1 226 5 is_stmt 1 view .LVU532 + 1620 .L119: + 369:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1621 .loc 1 369 3 view .LVU533 + 370:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1622 .loc 1 370 1 is_stmt 0 view .LVU534 + 1623 0032 2046 mov r0, r4 + 1624 0034 F8BD pop {r3, r4, r5, r6, r7, pc} + 1625 .LVL213: + 1626 .L153: + 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1627 .loc 1 229 5 is_stmt 1 view .LVU535 + 229:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1628 .loc 1 229 16 is_stmt 0 view .LVU536 + 1629 0036 6F78 ldrb r7, [r5, #1] @ zero_extendqisi2 + 1630 0038 012F cmp r7, #1 + 1631 003a 2FD0 beq .L120 + 1632 003c 032F cmp r7, #3 + 1633 003e 05D0 beq .L121 + 1634 0040 002F cmp r7, #0 + ARM GAS /tmp/cc37ZWv9.s page 60 + + + 1635 0042 57D0 beq .L154 + 359:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1636 .loc 1 359 7 is_stmt 1 view .LVU537 + 1637 0044 2946 mov r1, r5 + 1638 0046 FFF7FEFF bl USBD_CtlError + 1639 .LVL214: + 360:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1640 .loc 1 360 7 view .LVU538 + 1641 004a F2E7 b .L119 + 1642 .LVL215: + 1643 .L121: + 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1644 .loc 1 232 7 discriminator 3 view .LVU539 + 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1645 .loc 1 232 19 is_stmt 0 discriminator 3 view .LVU540 + 1646 004c 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 1647 .LVL216: + 232:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1648 .loc 1 232 19 discriminator 3 view .LVU541 + 1649 0050 022B cmp r3, #2 + 1650 0052 05D0 beq .L124 + 1651 0054 032B cmp r3, #3 + 1652 0056 12D0 beq .L125 + 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1653 .loc 1 259 9 is_stmt 1 view .LVU542 + 1654 0058 2946 mov r1, r5 + 1655 .LVL217: + 259:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1656 .loc 1 259 9 is_stmt 0 view .LVU543 + 1657 005a FFF7FEFF bl USBD_CtlError + 1658 .LVL218: + 260:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1659 .loc 1 260 9 is_stmt 1 view .LVU544 + 1660 005e E8E7 b .L119 + 1661 .LVL219: + 1662 .L124: + 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1663 .loc 1 235 9 view .LVU545 + 235:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1664 .loc 1 235 12 is_stmt 0 view .LVU546 + 1665 0060 0029 cmp r1, #0 + 1666 0062 18BF it ne + 1667 0064 8029 cmpne r1, #128 + 1668 0066 06D0 beq .L127 + 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 1669 .loc 1 237 11 is_stmt 1 view .LVU547 + 237:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 1670 .loc 1 237 17 is_stmt 0 view .LVU548 + 1671 0068 FFF7FEFF bl USBD_LL_StallEP + 1672 .LVL220: + 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1673 .loc 1 238 11 is_stmt 1 view .LVU549 + 238:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1674 .loc 1 238 17 is_stmt 0 view .LVU550 + 1675 006c 8021 movs r1, #128 + 1676 006e 3046 mov r0, r6 + 1677 0070 FFF7FEFF bl USBD_LL_StallEP + ARM GAS /tmp/cc37ZWv9.s page 61 + + + 1678 .LVL221: + 1679 0074 DDE7 b .L119 + 1680 .LVL222: + 1681 .L127: + 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1682 .loc 1 242 11 is_stmt 1 view .LVU551 + 1683 0076 2946 mov r1, r5 + 1684 .LVL223: + 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1685 .loc 1 242 11 is_stmt 0 view .LVU552 + 1686 0078 FFF7FEFF bl USBD_CtlError + 1687 .LVL224: + 242:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1688 .loc 1 242 11 view .LVU553 + 1689 007c D9E7 b .L119 + 1690 .LVL225: + 1691 .L125: + 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1692 .loc 1 247 9 is_stmt 1 view .LVU554 + 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1693 .loc 1 247 16 is_stmt 0 view .LVU555 + 1694 007e 6B88 ldrh r3, [r5, #2] + 247:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1695 .loc 1 247 12 view .LVU556 + 1696 0080 2BB9 cbnz r3, .L128 + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1697 .loc 1 249 11 is_stmt 1 view .LVU557 + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1698 .loc 1 249 14 is_stmt 0 view .LVU558 + 1699 0082 0029 cmp r1, #0 + 1700 0084 18BF it ne + 1701 0086 8029 cmpne r1, #128 + 1702 0088 01D0 beq .L128 + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1703 .loc 1 249 63 discriminator 1 view .LVU559 + 1704 008a EB88 ldrh r3, [r5, #6] + 249:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1705 .loc 1 249 56 discriminator 1 view .LVU560 + 1706 008c 1BB1 cbz r3, .L155 + 1707 .LVL226: + 1708 .L128: + 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1709 .loc 1 254 9 is_stmt 1 view .LVU561 + 254:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1710 .loc 1 254 15 is_stmt 0 view .LVU562 + 1711 008e 3046 mov r0, r6 + 1712 0090 FFF7FEFF bl USBD_CtlSendStatus + 1713 .LVL227: + 256:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1714 .loc 1 256 9 is_stmt 1 view .LVU563 + 1715 0094 CDE7 b .L119 + 1716 .LVL228: + 1717 .L155: + 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1718 .loc 1 251 13 view .LVU564 + 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1719 .loc 1 251 19 is_stmt 0 view .LVU565 + ARM GAS /tmp/cc37ZWv9.s page 62 + + + 1720 0096 FFF7FEFF bl USBD_LL_StallEP + 1721 .LVL229: + 251:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1722 .loc 1 251 19 view .LVU566 + 1723 009a F8E7 b .L128 + 1724 .LVL230: + 1725 .L120: + 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1726 .loc 1 266 7 is_stmt 1 discriminator 2 view .LVU567 + 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1727 .loc 1 266 19 is_stmt 0 discriminator 2 view .LVU568 + 1728 009c 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 1729 .LVL231: + 266:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1730 .loc 1 266 19 discriminator 2 view .LVU569 + 1731 00a0 022B cmp r3, #2 + 1732 00a2 05D0 beq .L129 + 1733 00a4 032B cmp r3, #3 + 1734 00a6 12D0 beq .L130 + 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1735 .loc 1 293 9 is_stmt 1 view .LVU570 + 1736 00a8 2946 mov r1, r5 + 1737 .LVL232: + 293:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1738 .loc 1 293 9 is_stmt 0 view .LVU571 + 1739 00aa FFF7FEFF bl USBD_CtlError + 1740 .LVL233: + 294:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1741 .loc 1 294 9 is_stmt 1 view .LVU572 + 1742 00ae C0E7 b .L119 + 1743 .LVL234: + 1744 .L129: + 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1745 .loc 1 269 9 view .LVU573 + 269:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1746 .loc 1 269 12 is_stmt 0 view .LVU574 + 1747 00b0 0029 cmp r1, #0 + 1748 00b2 18BF it ne + 1749 00b4 8029 cmpne r1, #128 + 1750 00b6 06D0 beq .L132 + 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 1751 .loc 1 271 11 is_stmt 1 view .LVU575 + 271:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (void)USBD_LL_StallEP(pdev, 0x80U); + 1752 .loc 1 271 17 is_stmt 0 view .LVU576 + 1753 00b8 FFF7FEFF bl USBD_LL_StallEP + 1754 .LVL235: + 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1755 .loc 1 272 11 is_stmt 1 view .LVU577 + 272:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1756 .loc 1 272 17 is_stmt 0 view .LVU578 + 1757 00bc 8021 movs r1, #128 + 1758 00be 3046 mov r0, r6 + 1759 00c0 FFF7FEFF bl USBD_LL_StallEP + 1760 .LVL236: + 1761 00c4 B5E7 b .L119 + 1762 .LVL237: + 1763 .L132: + ARM GAS /tmp/cc37ZWv9.s page 63 + + + 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1764 .loc 1 276 11 is_stmt 1 view .LVU579 + 1765 00c6 2946 mov r1, r5 + 1766 .LVL238: + 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1767 .loc 1 276 11 is_stmt 0 view .LVU580 + 1768 00c8 FFF7FEFF bl USBD_CtlError + 1769 .LVL239: + 276:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1770 .loc 1 276 11 view .LVU581 + 1771 00cc B1E7 b .L119 + 1772 .LVL240: + 1773 .L130: + 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1774 .loc 1 281 9 is_stmt 1 view .LVU582 + 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1775 .loc 1 281 16 is_stmt 0 view .LVU583 + 1776 00ce 6B88 ldrh r3, [r5, #2] + 281:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1777 .loc 1 281 12 view .LVU584 + 1778 00d0 002B cmp r3, #0 + 1779 00d2 AED1 bne .L119 + 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1780 .loc 1 283 11 is_stmt 1 view .LVU585 + 283:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1781 .loc 1 283 14 is_stmt 0 view .LVU586 + 1782 00d4 11F07F0F tst r1, #127 + 1783 00d8 09D1 bne .L156 + 1784 .LVL241: + 1785 .L133: + 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 1786 .loc 1 287 11 is_stmt 1 view .LVU587 + 287:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + 1787 .loc 1 287 17 is_stmt 0 view .LVU588 + 1788 00da 3046 mov r0, r6 + 1789 00dc FFF7FEFF bl USBD_CtlSendStatus + 1790 .LVL242: + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1791 .loc 1 288 11 is_stmt 1 view .LVU589 + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1792 .loc 1 288 35 is_stmt 0 view .LVU590 + 1793 00e0 D6F8B832 ldr r3, [r6, #696] + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1794 .loc 1 288 43 view .LVU591 + 1795 00e4 9B68 ldr r3, [r3, #8] + 288:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1796 .loc 1 288 31 view .LVU592 + 1797 00e6 2946 mov r1, r5 + 1798 00e8 3046 mov r0, r6 + 1799 00ea 9847 blx r3 + 1800 .LVL243: + 1801 00ec A1E7 b .L119 + 1802 .LVL244: + 1803 .L156: + 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1804 .loc 1 285 13 is_stmt 1 view .LVU593 + 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + ARM GAS /tmp/cc37ZWv9.s page 64 + + + 1805 .loc 1 285 19 is_stmt 0 view .LVU594 + 1806 00ee FFF7FEFF bl USBD_LL_ClearStallEP + 1807 .LVL245: + 285:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1808 .loc 1 285 19 view .LVU595 + 1809 00f2 F2E7 b .L133 + 1810 .LVL246: + 1811 .L154: + 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1812 .loc 1 299 7 is_stmt 1 discriminator 1 view .LVU596 + 299:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1813 .loc 1 299 19 is_stmt 0 discriminator 1 view .LVU597 + 1814 00f4 90F89C22 ldrb r2, [r0, #668] @ zero_extendqisi2 + 1815 00f8 022A cmp r2, #2 + 1816 00fa 06D0 beq .L134 + 1817 00fc 032A cmp r2, #3 + 1818 00fe 2AD0 beq .L135 + 353:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1819 .loc 1 353 9 is_stmt 1 view .LVU598 + 1820 0100 2946 mov r1, r5 + 1821 0102 FFF7FEFF bl USBD_CtlError + 1822 .LVL247: + 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1823 .loc 1 354 9 view .LVU599 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1824 .loc 1 218 22 is_stmt 0 view .LVU600 + 1825 0106 3C46 mov r4, r7 + 354:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1826 .loc 1 354 9 view .LVU601 + 1827 0108 93E7 b .L119 + 1828 .LVL248: + 1829 .L134: + 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1830 .loc 1 302 9 is_stmt 1 view .LVU602 + 302:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1831 .loc 1 302 12 is_stmt 0 view .LVU603 + 1832 010a 0029 cmp r1, #0 + 1833 010c 18BF it ne + 1834 010e 8029 cmpne r1, #128 + 1835 0110 13D1 bne .L157 + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1836 .loc 1 307 9 is_stmt 1 view .LVU604 + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1837 .loc 1 307 76 is_stmt 0 view .LVU605 + 1838 0112 13F0800F tst r3, #128 + 1839 0116 15D1 bne .L158 + 308:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1840 .loc 1 308 37 discriminator 2 view .LVU606 + 1841 0118 01F07F01 and r1, r1, #127 + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1842 .loc 1 307 76 discriminator 2 view .LVU607 + 1843 011c 01EB8101 add r1, r1, r1, lsl #2 + 1844 0120 8900 lsls r1, r1, #2 + 1845 0122 01F5A871 add r1, r1, #336 + 1846 0126 0144 add r1, r1, r0 + 1847 0128 0431 adds r1, r1, #4 + 1848 .L139: + ARM GAS /tmp/cc37ZWv9.s page 65 + + + 1849 .LVL249: + 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1850 .loc 1 310 9 is_stmt 1 discriminator 4 view .LVU608 + 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1851 .loc 1 310 21 is_stmt 0 discriminator 4 view .LVU609 + 1852 012a 0023 movs r3, #0 + 1853 .LVL250: + 310:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1854 .loc 1 310 21 discriminator 4 view .LVU610 + 1855 012c 0B60 str r3, [r1] + 1856 .LVL251: + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1857 .loc 1 312 9 is_stmt 1 discriminator 4 view .LVU611 + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1858 .loc 1 312 15 is_stmt 0 discriminator 4 view .LVU612 + 1859 012e 0222 movs r2, #2 + 1860 0130 3046 mov r0, r6 + 1861 .LVL252: + 312:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1862 .loc 1 312 15 discriminator 4 view .LVU613 + 1863 0132 FFF7FEFF bl USBD_CtlSendData + 1864 .LVL253: + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1865 .loc 1 313 9 is_stmt 1 discriminator 4 view .LVU614 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1866 .loc 1 218 22 is_stmt 0 discriminator 4 view .LVU615 + 1867 0136 3C46 mov r4, r7 + 313:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1868 .loc 1 313 9 discriminator 4 view .LVU616 + 1869 0138 7BE7 b .L119 + 1870 .LVL254: + 1871 .L157: + 304:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1872 .loc 1 304 11 is_stmt 1 view .LVU617 + 1873 013a 2946 mov r1, r5 + 1874 013c FFF7FEFF bl USBD_CtlError + 1875 .LVL255: + 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1876 .loc 1 305 11 view .LVU618 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1877 .loc 1 218 22 is_stmt 0 view .LVU619 + 1878 0140 3C46 mov r4, r7 + 305:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1879 .loc 1 305 11 view .LVU620 + 1880 0142 76E7 b .L119 + 1881 .LVL256: + 1882 .L158: + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1883 .loc 1 307 67 discriminator 1 view .LVU621 + 1884 0144 01F07F01 and r1, r1, #127 + 307:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1885 .loc 1 307 76 discriminator 1 view .LVU622 + 1886 0148 01EB8101 add r1, r1, r1, lsl #2 + 1887 014c 8900 lsls r1, r1, #2 + 1888 014e 1031 adds r1, r1, #16 + 1889 0150 0144 add r1, r1, r0 + 1890 0152 0431 adds r1, r1, #4 + ARM GAS /tmp/cc37ZWv9.s page 66 + + + 1891 0154 E9E7 b .L139 + 1892 .L135: + 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1893 .loc 1 316 9 is_stmt 1 view .LVU623 + 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1894 .loc 1 316 31 is_stmt 0 view .LVU624 + 1895 0156 5BB2 sxtb r3, r3 + 316:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1896 .loc 1 316 12 view .LVU625 + 1897 0158 002B cmp r3, #0 + 1898 015a 20DB blt .L159 + 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1899 .loc 1 326 11 is_stmt 1 view .LVU626 + 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1900 .loc 1 326 36 is_stmt 0 view .LVU627 + 1901 015c 01F00F02 and r2, r1, #15 + 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1902 .loc 1 326 43 view .LVU628 + 1903 0160 02EB8202 add r2, r2, r2, lsl #2 + 1904 0164 00EB8202 add r2, r0, r2, lsl #2 + 1905 0168 B2F86421 ldrh r2, [r2, #356] + 326:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1906 .loc 1 326 14 view .LVU629 + 1907 016c 2AB3 cbz r2, .L160 + 1908 .L141: + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1909 .loc 1 333 9 is_stmt 1 view .LVU630 + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1910 .loc 1 333 76 is_stmt 0 view .LVU631 + 1911 016e 002B cmp r3, #0 + 1912 0170 28DB blt .L161 + 334:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1913 .loc 1 334 37 discriminator 2 view .LVU632 + 1914 0172 01F07F03 and r3, r1, #127 + 1915 .LVL257: + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1916 .loc 1 333 76 discriminator 2 view .LVU633 + 1917 0176 03EB8303 add r3, r3, r3, lsl #2 + 1918 017a 9C00 lsls r4, r3, #2 + 1919 017c 04F5A874 add r4, r4, #336 + 1920 0180 3444 add r4, r4, r6 + 1921 0182 0434 adds r4, r4, #4 + 1922 .L143: + 1923 .LVL258: + 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1924 .loc 1 336 11 is_stmt 1 discriminator 4 view .LVU634 + 336:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1925 .loc 1 336 14 is_stmt 0 discriminator 4 view .LVU635 + 1926 0184 8029 cmp r1, #128 + 1927 0186 18BF it ne + 1928 0188 0029 cmpne r1, #0 + 1929 018a 24D1 bne .L144 + 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1930 .loc 1 338 13 is_stmt 1 view .LVU636 + 338:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1931 .loc 1 338 25 is_stmt 0 view .LVU637 + 1932 018c 0023 movs r3, #0 + ARM GAS /tmp/cc37ZWv9.s page 67 + + + 1933 018e 2360 str r3, [r4] + 1934 .LVL259: + 1935 .L145: + 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1936 .loc 1 349 11 is_stmt 1 view .LVU638 + 349:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1937 .loc 1 349 17 is_stmt 0 view .LVU639 + 1938 0190 0222 movs r2, #2 + 1939 0192 2146 mov r1, r4 + 1940 0194 3046 mov r0, r6 + 1941 0196 FFF7FEFF bl USBD_CtlSendData + 1942 .LVL260: + 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1943 .loc 1 350 11 is_stmt 1 view .LVU640 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1944 .loc 1 218 22 is_stmt 0 view .LVU641 + 1945 019a 3C46 mov r4, r7 + 1946 .LVL261: + 350:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 1947 .loc 1 350 11 view .LVU642 + 1948 019c 49E7 b .L119 + 1949 .LVL262: + 1950 .L159: + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1951 .loc 1 318 11 is_stmt 1 view .LVU643 + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1952 .loc 1 318 35 is_stmt 0 view .LVU644 + 1953 019e 01F00F02 and r2, r1, #15 + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1954 .loc 1 318 42 view .LVU645 + 1955 01a2 02EB8202 add r2, r2, r2, lsl #2 + 1956 01a6 00EB8202 add r2, r0, r2, lsl #2 + 1957 01aa 928C ldrh r2, [r2, #36] + 318:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1958 .loc 1 318 14 view .LVU646 + 1959 01ac 002A cmp r2, #0 + 1960 01ae DED1 bne .L141 + 320:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1961 .loc 1 320 13 is_stmt 1 view .LVU647 + 1962 01b0 2946 mov r1, r5 + 1963 01b2 FFF7FEFF bl USBD_CtlError + 1964 .LVL263: + 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1965 .loc 1 321 13 view .LVU648 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1966 .loc 1 218 22 is_stmt 0 view .LVU649 + 1967 01b6 3C46 mov r4, r7 + 321:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1968 .loc 1 321 13 view .LVU650 + 1969 01b8 3BE7 b .L119 + 1970 .LVL264: + 1971 .L160: + 328:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** break; + 1972 .loc 1 328 13 is_stmt 1 view .LVU651 + 1973 01ba 2946 mov r1, r5 + 1974 01bc FFF7FEFF bl USBD_CtlError + 1975 .LVL265: + ARM GAS /tmp/cc37ZWv9.s page 68 + + + 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1976 .loc 1 329 13 view .LVU652 + 218:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** ep_addr = LOBYTE(req->wIndex); + 1977 .loc 1 218 22 is_stmt 0 view .LVU653 + 1978 01c0 3C46 mov r4, r7 + 329:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 1979 .loc 1 329 13 view .LVU654 + 1980 01c2 36E7 b .L119 + 1981 .LVL266: + 1982 .L161: + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1983 .loc 1 333 67 discriminator 1 view .LVU655 + 1984 01c4 01F07F03 and r3, r1, #127 + 1985 .LVL267: + 333:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** &pdev->ep_out[ep_addr & 0x7FU]; + 1986 .loc 1 333 76 discriminator 1 view .LVU656 + 1987 01c8 03EB8303 add r3, r3, r3, lsl #2 + 1988 01cc 9C00 lsls r4, r3, #2 + 1989 01ce 1034 adds r4, r4, #16 + 1990 01d0 3444 add r4, r4, r6 + 1991 01d2 0434 adds r4, r4, #4 + 1992 01d4 D6E7 b .L143 + 1993 .LVL268: + 1994 .L144: + 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1995 .loc 1 340 16 is_stmt 1 view .LVU657 + 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1996 .loc 1 340 20 is_stmt 0 view .LVU658 + 1997 01d6 3046 mov r0, r6 + 1998 .LVL269: + 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 1999 .loc 1 340 20 view .LVU659 + 2000 01d8 FFF7FEFF bl USBD_LL_IsStallEP + 2001 .LVL270: + 340:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2002 .loc 1 340 19 view .LVU660 + 2003 01dc 10B1 cbz r0, .L146 + 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 2004 .loc 1 342 13 is_stmt 1 view .LVU661 + 342:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 2005 .loc 1 342 25 is_stmt 0 view .LVU662 + 2006 01de 0123 movs r3, #1 + 2007 01e0 2360 str r3, [r4] + 2008 01e2 D5E7 b .L145 + 2009 .L146: + 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 2010 .loc 1 346 13 is_stmt 1 view .LVU663 + 346:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 2011 .loc 1 346 25 is_stmt 0 view .LVU664 + 2012 01e4 0023 movs r3, #0 + 2013 01e6 2360 str r3, [r4] + 2014 01e8 D2E7 b .L145 + 2015 .cfi_endproc + 2016 .LFE147: + 2018 .section .text.USBD_GetString,"ax",%progbits + 2019 .align 1 + 2020 .global USBD_GetString + ARM GAS /tmp/cc37ZWv9.s page 69 + + + 2021 .syntax unified + 2022 .thumb + 2023 .thumb_func + 2024 .fpu fpv5-d16 + 2026 USBD_GetString: + 2027 .LVL271: + 2028 .LFB157: + 883:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t idx = 0U; + 2029 .loc 1 883 1 is_stmt 1 view -0 + 2030 .cfi_startproc + 2031 @ args = 0, pretend = 0, frame = 0 + 2032 @ frame_needed = 0, uses_anonymous_args = 0 + 884:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t *pdesc; + 2033 .loc 1 884 3 view .LVU666 + 885:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2034 .loc 1 885 3 view .LVU667 + 887:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2035 .loc 1 887 3 view .LVU668 + 887:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2036 .loc 1 887 6 is_stmt 0 view .LVU669 + 2037 0000 D0B1 cbz r0, .L167 + 883:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** uint8_t idx = 0U; + 2038 .loc 1 883 1 view .LVU670 + 2039 0002 70B5 push {r4, r5, r6, lr} + 2040 .LCFI14: + 2041 .cfi_def_cfa_offset 16 + 2042 .cfi_offset 4, -16 + 2043 .cfi_offset 5, -12 + 2044 .cfi_offset 6, -8 + 2045 .cfi_offset 14, -4 + 2046 0004 0D46 mov r5, r1 + 2047 0006 1646 mov r6, r2 + 2048 0008 0446 mov r4, r0 + 892:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; + 2049 .loc 1 892 3 is_stmt 1 view .LVU671 + 2050 .LVL272: + 893:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2051 .loc 1 893 3 view .LVU672 + 893:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2052 .loc 1 893 21 is_stmt 0 view .LVU673 + 2053 000a FFF7FEFF bl USBD_GetLen + 2054 .LVL273: + 893:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2055 .loc 1 893 46 view .LVU674 + 2056 000e 431C adds r3, r0, #1 + 893:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2057 .loc 1 893 8 view .LVU675 + 2058 0010 5B00 lsls r3, r3, #1 + 2059 0012 9BB2 uxth r3, r3 + 2060 0014 3380 strh r3, [r6] @ movhi + 895:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2061 .loc 1 895 3 is_stmt 1 view .LVU676 + 895:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2062 .loc 1 895 16 is_stmt 0 view .LVU677 + 2063 0016 2B70 strb r3, [r5] + 896:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** unicode[idx] = USB_DESC_TYPE_STRING; + 2064 .loc 1 896 3 is_stmt 1 view .LVU678 + ARM GAS /tmp/cc37ZWv9.s page 70 + + + 2065 .LVL274: + 897:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2066 .loc 1 897 3 view .LVU679 + 897:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2067 .loc 1 897 16 is_stmt 0 view .LVU680 + 2068 0018 0323 movs r3, #3 + 2069 001a 6B70 strb r3, [r5, #1] + 898:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2070 .loc 1 898 3 is_stmt 1 view .LVU681 + 2071 .LVL275: + 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2072 .loc 1 900 3 view .LVU682 + 898:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2073 .loc 1 898 6 is_stmt 0 view .LVU683 + 2074 001c 0223 movs r3, #2 + 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2075 .loc 1 900 9 view .LVU684 + 2076 001e 07E0 b .L164 + 2077 .LVL276: + 2078 .L165: + 902:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdesc++; + 2079 .loc 1 902 5 is_stmt 1 view .LVU685 + 902:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** pdesc++; + 2080 .loc 1 902 18 is_stmt 0 view .LVU686 + 2081 0020 EA54 strb r2, [r5, r3] + 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2082 .loc 1 903 5 is_stmt 1 view .LVU687 + 903:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2083 .loc 1 903 10 is_stmt 0 view .LVU688 + 2084 0022 0134 adds r4, r4, #1 + 2085 .LVL277: + 904:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2086 .loc 1 904 5 is_stmt 1 view .LVU689 + 904:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2087 .loc 1 904 8 is_stmt 0 view .LVU690 + 2088 0024 5A1C adds r2, r3, #1 + 2089 0026 D2B2 uxtb r2, r2 + 2090 .LVL278: + 906:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2091 .loc 1 906 5 is_stmt 1 view .LVU691 + 906:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** idx++; + 2092 .loc 1 906 18 is_stmt 0 view .LVU692 + 2093 0028 0021 movs r1, #0 + 2094 002a A954 strb r1, [r5, r2] + 907:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 2095 .loc 1 907 5 is_stmt 1 view .LVU693 + 907:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** } + 2096 .loc 1 907 8 is_stmt 0 view .LVU694 + 2097 002c 0233 adds r3, r3, #2 + 2098 002e DBB2 uxtb r3, r3 + 2099 .LVL279: + 2100 .L164: + 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2101 .loc 1 900 9 is_stmt 1 view .LVU695 + 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2102 .loc 1 900 10 is_stmt 0 view .LVU696 + 2103 0030 2278 ldrb r2, [r4] @ zero_extendqisi2 + ARM GAS /tmp/cc37ZWv9.s page 71 + + + 900:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** { + 2104 .loc 1 900 9 view .LVU697 + 2105 0032 002A cmp r2, #0 + 2106 0034 F4D1 bne .L165 + 909:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2107 .loc 1 909 1 view .LVU698 + 2108 0036 70BD pop {r4, r5, r6, pc} + 2109 .LVL280: + 2110 .L167: + 2111 .LCFI15: + 2112 .cfi_def_cfa_offset 0 + 2113 .cfi_restore 4 + 2114 .cfi_restore 5 + 2115 .cfi_restore 6 + 2116 .cfi_restore 14 + 909:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c **** + 2117 .loc 1 909 1 view .LVU699 + 2118 0038 7047 bx lr + 2119 .cfi_endproc + 2120 .LFE157: + 2122 .section .bss.cfgidx.0,"aw",%nobits + 2123 .set .LANCHOR0,. + 0 + 2126 cfgidx.0: + 2127 0000 00 .space 1 + 2128 .text + 2129 .Letext0: + 2130 .file 3 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2131 .file 4 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2132 .file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h" + 2133 .file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h" + ARM GAS /tmp/cc37ZWv9.s page 72 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_ctlreq.c + /tmp/cc37ZWv9.s:17 .text.USBD_GetLen:0000000000000000 $t + /tmp/cc37ZWv9.s:24 .text.USBD_GetLen:0000000000000000 USBD_GetLen + /tmp/cc37ZWv9.s:71 .text.USBD_SetFeature:0000000000000000 $t + /tmp/cc37ZWv9.s:77 .text.USBD_SetFeature:0000000000000000 USBD_SetFeature + /tmp/cc37ZWv9.s:115 .text.USBD_ParseSetupRequest:0000000000000000 $t + /tmp/cc37ZWv9.s:122 .text.USBD_ParseSetupRequest:0000000000000000 USBD_ParseSetupRequest + /tmp/cc37ZWv9.s:237 .text.USBD_CtlError:0000000000000000 $t + /tmp/cc37ZWv9.s:244 .text.USBD_CtlError:0000000000000000 USBD_CtlError + /tmp/cc37ZWv9.s:279 .text.USBD_GetDescriptor:0000000000000000 $t + /tmp/cc37ZWv9.s:285 .text.USBD_GetDescriptor:0000000000000000 USBD_GetDescriptor + /tmp/cc37ZWv9.s:322 .text.USBD_GetDescriptor:000000000000001e $d + /tmp/cc37ZWv9.s:435 .text.USBD_GetDescriptor:000000000000008e $d + /tmp/cc37ZWv9.s:441 .text.USBD_GetDescriptor:0000000000000094 $t + /tmp/cc37ZWv9.s:731 .text.USBD_SetAddress:0000000000000000 $t + /tmp/cc37ZWv9.s:737 .text.USBD_SetAddress:0000000000000000 USBD_SetAddress + /tmp/cc37ZWv9.s:830 .text.USBD_SetConfig:0000000000000000 $t + /tmp/cc37ZWv9.s:836 .text.USBD_SetConfig:0000000000000000 USBD_SetConfig + /tmp/cc37ZWv9.s:1044 .text.USBD_SetConfig:00000000000000c0 $d + /tmp/cc37ZWv9.s:1049 .text.USBD_GetConfig:0000000000000000 $t + /tmp/cc37ZWv9.s:1055 .text.USBD_GetConfig:0000000000000000 USBD_GetConfig + /tmp/cc37ZWv9.s:1132 .text.USBD_GetStatus:0000000000000000 $t + /tmp/cc37ZWv9.s:1138 .text.USBD_GetStatus:0000000000000000 USBD_GetStatus + /tmp/cc37ZWv9.s:1209 .text.USBD_ClrFeature:0000000000000000 $t + /tmp/cc37ZWv9.s:1215 .text.USBD_ClrFeature:0000000000000000 USBD_ClrFeature + /tmp/cc37ZWv9.s:1269 .text.USBD_StdDevReq:0000000000000000 $t + /tmp/cc37ZWv9.s:1276 .text.USBD_StdDevReq:0000000000000000 USBD_StdDevReq + /tmp/cc37ZWv9.s:1339 .text.USBD_StdDevReq:0000000000000032 $d + /tmp/cc37ZWv9.s:1349 .text.USBD_StdDevReq:000000000000003c $t + /tmp/cc37ZWv9.s:1416 .text.USBD_StdItfReq:0000000000000000 $t + /tmp/cc37ZWv9.s:1423 .text.USBD_StdItfReq:0000000000000000 USBD_StdItfReq + /tmp/cc37ZWv9.s:1545 .text.USBD_StdEPReq:0000000000000000 $t + /tmp/cc37ZWv9.s:1552 .text.USBD_StdEPReq:0000000000000000 USBD_StdEPReq + /tmp/cc37ZWv9.s:2019 .text.USBD_GetString:0000000000000000 $t + /tmp/cc37ZWv9.s:2026 .text.USBD_GetString:0000000000000000 USBD_GetString + /tmp/cc37ZWv9.s:2126 .bss.cfgidx.0:0000000000000000 cfgidx.0 + /tmp/cc37ZWv9.s:2127 .bss.cfgidx.0:0000000000000000 $d + /tmp/cc37ZWv9.s:329 .text.USBD_GetDescriptor:0000000000000025 $d + /tmp/cc37ZWv9.s:329 .text.USBD_GetDescriptor:0000000000000026 $t + +UNDEFINED SYMBOLS +USBD_CtlSendStatus +USBD_LL_StallEP +USBD_CtlSendData +USBD_LL_SetUSBAddress +USBD_ClrClassConfig +USBD_SetClassConfig +USBD_LL_ClearStallEP +USBD_LL_IsStallEP diff --git a/build/usbd_ctlreq.o b/build/usbd_ctlreq.o new file mode 100644 index 0000000..3fa0751 Binary files /dev/null and b/build/usbd_ctlreq.o differ diff --git a/build/usbd_desc.d b/build/usbd_desc.d new file mode 100644 index 0000000..66084fd --- /dev/null +++ b/build/usbd_desc.d @@ -0,0 +1,88 @@ +build/usbd_desc.o: USB_DEVICE/App/usbd_desc.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + USB_DEVICE/App/usbd_desc.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +USB_DEVICE/App/usbd_desc.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: diff --git a/build/usbd_desc.lst b/build/usbd_desc.lst new file mode 100644 index 0000000..27dfebc --- /dev/null +++ b/build/usbd_desc.lst @@ -0,0 +1,1138 @@ +ARM GAS /tmp/cc3RdOng.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_desc.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.USBD_FS_DeviceDescriptor,"ax",%progbits + 17 .align 1 + 18 .global USBD_FS_DeviceDescriptor + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 USBD_FS_DeviceDescriptor: + 26 .LVL0: + 27 .LFB145: + 28 .file 1 "USB_DEVICE/App/usbd_desc.c" + 1:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN Header */ + 2:USB_DEVICE/App/usbd_desc.c **** /** + 3:USB_DEVICE/App/usbd_desc.c **** ****************************************************************************** + 4:USB_DEVICE/App/usbd_desc.c **** * @file : App/usbd_desc.c + 5:USB_DEVICE/App/usbd_desc.c **** * @version : v1.0_Cube + 6:USB_DEVICE/App/usbd_desc.c **** * @brief : This file implements the USB device descriptors. + 7:USB_DEVICE/App/usbd_desc.c **** ****************************************************************************** + 8:USB_DEVICE/App/usbd_desc.c **** * @attention + 9:USB_DEVICE/App/usbd_desc.c **** * + 10:USB_DEVICE/App/usbd_desc.c **** *

© Copyright (c) 2019 STMicroelectronics. + 11:USB_DEVICE/App/usbd_desc.c **** * All rights reserved.

+ 12:USB_DEVICE/App/usbd_desc.c **** * + 13:USB_DEVICE/App/usbd_desc.c **** * This software component is licensed by ST under Ultimate Liberty license + 14:USB_DEVICE/App/usbd_desc.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 15:USB_DEVICE/App/usbd_desc.c **** * the License. You may obtain a copy of the License at: + 16:USB_DEVICE/App/usbd_desc.c **** * www.st.com/SLA0044 + 17:USB_DEVICE/App/usbd_desc.c **** * + 18:USB_DEVICE/App/usbd_desc.c **** ****************************************************************************** + 19:USB_DEVICE/App/usbd_desc.c **** */ + 20:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END Header */ + 21:USB_DEVICE/App/usbd_desc.c **** + 22:USB_DEVICE/App/usbd_desc.c **** /* Includes ------------------------------------------------------------------*/ + 23:USB_DEVICE/App/usbd_desc.c **** #include "usbd_core.h" + 24:USB_DEVICE/App/usbd_desc.c **** #include "usbd_desc.h" + 25:USB_DEVICE/App/usbd_desc.c **** #include "usbd_conf.h" + 26:USB_DEVICE/App/usbd_desc.c **** + 27:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN INCLUDE */ + 28:USB_DEVICE/App/usbd_desc.c **** + 29:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END INCLUDE */ + 30:USB_DEVICE/App/usbd_desc.c **** + ARM GAS /tmp/cc3RdOng.s page 2 + + + 31:USB_DEVICE/App/usbd_desc.c **** /* Private typedef -----------------------------------------------------------*/ + 32:USB_DEVICE/App/usbd_desc.c **** /* Private define ------------------------------------------------------------*/ + 33:USB_DEVICE/App/usbd_desc.c **** /* Private macro -------------------------------------------------------------*/ + 34:USB_DEVICE/App/usbd_desc.c **** + 35:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN PV */ + 36:USB_DEVICE/App/usbd_desc.c **** /* Private variables ---------------------------------------------------------*/ + 37:USB_DEVICE/App/usbd_desc.c **** + 38:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END PV */ + 39:USB_DEVICE/App/usbd_desc.c **** + 40:USB_DEVICE/App/usbd_desc.c **** /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + 41:USB_DEVICE/App/usbd_desc.c **** * @{ + 42:USB_DEVICE/App/usbd_desc.c **** */ + 43:USB_DEVICE/App/usbd_desc.c **** + 44:USB_DEVICE/App/usbd_desc.c **** /** @addtogroup USBD_DESC + 45:USB_DEVICE/App/usbd_desc.c **** * @{ + 46:USB_DEVICE/App/usbd_desc.c **** */ + 47:USB_DEVICE/App/usbd_desc.c **** + 48:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions + 49:USB_DEVICE/App/usbd_desc.c **** * @brief Private types. + 50:USB_DEVICE/App/usbd_desc.c **** * @{ + 51:USB_DEVICE/App/usbd_desc.c **** */ + 52:USB_DEVICE/App/usbd_desc.c **** + 53:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN PRIVATE_TYPES */ + 54:USB_DEVICE/App/usbd_desc.c **** + 55:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END PRIVATE_TYPES */ + 56:USB_DEVICE/App/usbd_desc.c **** + 57:USB_DEVICE/App/usbd_desc.c **** /** + 58:USB_DEVICE/App/usbd_desc.c **** * @} + 59:USB_DEVICE/App/usbd_desc.c **** */ + 60:USB_DEVICE/App/usbd_desc.c **** + 61:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines + 62:USB_DEVICE/App/usbd_desc.c **** * @brief Private defines. + 63:USB_DEVICE/App/usbd_desc.c **** * @{ + 64:USB_DEVICE/App/usbd_desc.c **** */ + 65:USB_DEVICE/App/usbd_desc.c **** + 66:USB_DEVICE/App/usbd_desc.c **** #define USBD_VID 1155 + 67:USB_DEVICE/App/usbd_desc.c **** #define USBD_LANGID_STRING 1033 + 68:USB_DEVICE/App/usbd_desc.c **** #define USBD_MANUFACTURER_STRING "STMicroelectronics" + 69:USB_DEVICE/App/usbd_desc.c **** #define USBD_PID_FS 57105 + 70:USB_DEVICE/App/usbd_desc.c **** #define USBD_PRODUCT_STRING_FS "STM32 DownLoad Firmware Update" + 71:USB_DEVICE/App/usbd_desc.c **** #define USBD_CONFIGURATION_STRING_FS "DFU Config" + 72:USB_DEVICE/App/usbd_desc.c **** #define USBD_INTERFACE_STRING_FS "DFU Interface" + 73:USB_DEVICE/App/usbd_desc.c **** + 74:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN PRIVATE_DEFINES */ + 75:USB_DEVICE/App/usbd_desc.c **** + 76:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END PRIVATE_DEFINES */ + 77:USB_DEVICE/App/usbd_desc.c **** + 78:USB_DEVICE/App/usbd_desc.c **** /** + 79:USB_DEVICE/App/usbd_desc.c **** * @} + 80:USB_DEVICE/App/usbd_desc.c **** */ + 81:USB_DEVICE/App/usbd_desc.c **** + 82:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN 0 */ + 83:USB_DEVICE/App/usbd_desc.c **** + 84:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END 0 */ + 85:USB_DEVICE/App/usbd_desc.c **** + 86:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros + 87:USB_DEVICE/App/usbd_desc.c **** * @brief Private macros. + ARM GAS /tmp/cc3RdOng.s page 3 + + + 88:USB_DEVICE/App/usbd_desc.c **** * @{ + 89:USB_DEVICE/App/usbd_desc.c **** */ + 90:USB_DEVICE/App/usbd_desc.c **** + 91:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN PRIVATE_MACRO */ + 92:USB_DEVICE/App/usbd_desc.c **** + 93:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END PRIVATE_MACRO */ + 94:USB_DEVICE/App/usbd_desc.c **** + 95:USB_DEVICE/App/usbd_desc.c **** /** + 96:USB_DEVICE/App/usbd_desc.c **** * @} + 97:USB_DEVICE/App/usbd_desc.c **** */ + 98:USB_DEVICE/App/usbd_desc.c **** + 99:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes + 100:USB_DEVICE/App/usbd_desc.c **** * @brief Private functions declaration. + 101:USB_DEVICE/App/usbd_desc.c **** * @{ + 102:USB_DEVICE/App/usbd_desc.c **** */ + 103:USB_DEVICE/App/usbd_desc.c **** + 104:USB_DEVICE/App/usbd_desc.c **** static void Get_SerialNum(void); + 105:USB_DEVICE/App/usbd_desc.c **** static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len); + 106:USB_DEVICE/App/usbd_desc.c **** + 107:USB_DEVICE/App/usbd_desc.c **** /** + 108:USB_DEVICE/App/usbd_desc.c **** * @} + 109:USB_DEVICE/App/usbd_desc.c **** */ + 110:USB_DEVICE/App/usbd_desc.c **** + 111:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes + 112:USB_DEVICE/App/usbd_desc.c **** * @brief Private functions declaration for FS. + 113:USB_DEVICE/App/usbd_desc.c **** * @{ + 114:USB_DEVICE/App/usbd_desc.c **** */ + 115:USB_DEVICE/App/usbd_desc.c **** + 116:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 117:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 118:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 119:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 120:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 121:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 122:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); + 123:USB_DEVICE/App/usbd_desc.c **** + 124:USB_DEVICE/App/usbd_desc.c **** /** + 125:USB_DEVICE/App/usbd_desc.c **** * @} + 126:USB_DEVICE/App/usbd_desc.c **** */ + 127:USB_DEVICE/App/usbd_desc.c **** + 128:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables + 129:USB_DEVICE/App/usbd_desc.c **** * @brief Private variables. + 130:USB_DEVICE/App/usbd_desc.c **** * @{ + 131:USB_DEVICE/App/usbd_desc.c **** */ + 132:USB_DEVICE/App/usbd_desc.c **** + 133:USB_DEVICE/App/usbd_desc.c **** USBD_DescriptorsTypeDef FS_Desc = + 134:USB_DEVICE/App/usbd_desc.c **** { + 135:USB_DEVICE/App/usbd_desc.c **** USBD_FS_DeviceDescriptor + 136:USB_DEVICE/App/usbd_desc.c **** , USBD_FS_LangIDStrDescriptor + 137:USB_DEVICE/App/usbd_desc.c **** , USBD_FS_ManufacturerStrDescriptor + 138:USB_DEVICE/App/usbd_desc.c **** , USBD_FS_ProductStrDescriptor + 139:USB_DEVICE/App/usbd_desc.c **** , USBD_FS_SerialStrDescriptor + 140:USB_DEVICE/App/usbd_desc.c **** , USBD_FS_ConfigStrDescriptor + 141:USB_DEVICE/App/usbd_desc.c **** , USBD_FS_InterfaceStrDescriptor + 142:USB_DEVICE/App/usbd_desc.c **** }; + 143:USB_DEVICE/App/usbd_desc.c **** + 144:USB_DEVICE/App/usbd_desc.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */ + ARM GAS /tmp/cc3RdOng.s page 4 + + + 145:USB_DEVICE/App/usbd_desc.c **** #pragma data_alignment=4 + 146:USB_DEVICE/App/usbd_desc.c **** #endif /* defined ( __ICCARM__ ) */ + 147:USB_DEVICE/App/usbd_desc.c **** /** USB standard device descriptor. */ + 148:USB_DEVICE/App/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = + 149:USB_DEVICE/App/usbd_desc.c **** { + 150:USB_DEVICE/App/usbd_desc.c **** 0x12, /*bLength */ + 151:USB_DEVICE/App/usbd_desc.c **** USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ + 152:USB_DEVICE/App/usbd_desc.c **** 0x00, /*bcdUSB */ + 153:USB_DEVICE/App/usbd_desc.c **** 0x02, + 154:USB_DEVICE/App/usbd_desc.c **** 0x00, /*bDeviceClass*/ + 155:USB_DEVICE/App/usbd_desc.c **** 0x00, /*bDeviceSubClass*/ + 156:USB_DEVICE/App/usbd_desc.c **** 0x00, /*bDeviceProtocol*/ + 157:USB_DEVICE/App/usbd_desc.c **** USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ + 158:USB_DEVICE/App/usbd_desc.c **** LOBYTE(USBD_VID), /*idVendor*/ + 159:USB_DEVICE/App/usbd_desc.c **** HIBYTE(USBD_VID), /*idVendor*/ + 160:USB_DEVICE/App/usbd_desc.c **** LOBYTE(USBD_PID_FS), /*idProduct*/ + 161:USB_DEVICE/App/usbd_desc.c **** HIBYTE(USBD_PID_FS), /*idProduct*/ + 162:USB_DEVICE/App/usbd_desc.c **** 0x00, /*bcdDevice rel. 2.00*/ + 163:USB_DEVICE/App/usbd_desc.c **** 0x02, + 164:USB_DEVICE/App/usbd_desc.c **** USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + 165:USB_DEVICE/App/usbd_desc.c **** USBD_IDX_PRODUCT_STR, /*Index of product string*/ + 166:USB_DEVICE/App/usbd_desc.c **** USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + 167:USB_DEVICE/App/usbd_desc.c **** USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ + 168:USB_DEVICE/App/usbd_desc.c **** }; + 169:USB_DEVICE/App/usbd_desc.c **** + 170:USB_DEVICE/App/usbd_desc.c **** /* USB_DeviceDescriptor */ + 171:USB_DEVICE/App/usbd_desc.c **** + 172:USB_DEVICE/App/usbd_desc.c **** /** + 173:USB_DEVICE/App/usbd_desc.c **** * @} + 174:USB_DEVICE/App/usbd_desc.c **** */ + 175:USB_DEVICE/App/usbd_desc.c **** + 176:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables + 177:USB_DEVICE/App/usbd_desc.c **** * @brief Private variables. + 178:USB_DEVICE/App/usbd_desc.c **** * @{ + 179:USB_DEVICE/App/usbd_desc.c **** */ + 180:USB_DEVICE/App/usbd_desc.c **** + 181:USB_DEVICE/App/usbd_desc.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */ + 182:USB_DEVICE/App/usbd_desc.c **** #pragma data_alignment=4 + 183:USB_DEVICE/App/usbd_desc.c **** #endif /* defined ( __ICCARM__ ) */ + 184:USB_DEVICE/App/usbd_desc.c **** + 185:USB_DEVICE/App/usbd_desc.c **** /** USB lang indentifier descriptor. */ + 186:USB_DEVICE/App/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = + 187:USB_DEVICE/App/usbd_desc.c **** { + 188:USB_DEVICE/App/usbd_desc.c **** USB_LEN_LANGID_STR_DESC, + 189:USB_DEVICE/App/usbd_desc.c **** USB_DESC_TYPE_STRING, + 190:USB_DEVICE/App/usbd_desc.c **** LOBYTE(USBD_LANGID_STRING), + 191:USB_DEVICE/App/usbd_desc.c **** HIBYTE(USBD_LANGID_STRING) + 192:USB_DEVICE/App/usbd_desc.c **** }; + 193:USB_DEVICE/App/usbd_desc.c **** + 194:USB_DEVICE/App/usbd_desc.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */ + 195:USB_DEVICE/App/usbd_desc.c **** #pragma data_alignment=4 + 196:USB_DEVICE/App/usbd_desc.c **** #endif /* defined ( __ICCARM__ ) */ + 197:USB_DEVICE/App/usbd_desc.c **** /* Internal string descriptor. */ + 198:USB_DEVICE/App/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; + 199:USB_DEVICE/App/usbd_desc.c **** + 200:USB_DEVICE/App/usbd_desc.c **** #if defined ( __ICCARM__ ) /*!< IAR Compiler */ + 201:USB_DEVICE/App/usbd_desc.c **** #pragma data_alignment=4 + ARM GAS /tmp/cc3RdOng.s page 5 + + + 202:USB_DEVICE/App/usbd_desc.c **** #endif + 203:USB_DEVICE/App/usbd_desc.c **** __ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = { + 204:USB_DEVICE/App/usbd_desc.c **** USB_SIZ_STRING_SERIAL, + 205:USB_DEVICE/App/usbd_desc.c **** USB_DESC_TYPE_STRING, + 206:USB_DEVICE/App/usbd_desc.c **** }; + 207:USB_DEVICE/App/usbd_desc.c **** + 208:USB_DEVICE/App/usbd_desc.c **** /** + 209:USB_DEVICE/App/usbd_desc.c **** * @} + 210:USB_DEVICE/App/usbd_desc.c **** */ + 211:USB_DEVICE/App/usbd_desc.c **** + 212:USB_DEVICE/App/usbd_desc.c **** /** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions + 213:USB_DEVICE/App/usbd_desc.c **** * @brief Private functions. + 214:USB_DEVICE/App/usbd_desc.c **** * @{ + 215:USB_DEVICE/App/usbd_desc.c **** */ + 216:USB_DEVICE/App/usbd_desc.c **** + 217:USB_DEVICE/App/usbd_desc.c **** /** + 218:USB_DEVICE/App/usbd_desc.c **** * @brief Return the device descriptor + 219:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 220:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 221:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 222:USB_DEVICE/App/usbd_desc.c **** */ + 223:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 224:USB_DEVICE/App/usbd_desc.c **** { + 29 .loc 1 224 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 225:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 34 .loc 1 225 3 view .LVU1 + 226:USB_DEVICE/App/usbd_desc.c **** *length = sizeof(USBD_FS_DeviceDesc); + 35 .loc 1 226 3 view .LVU2 + 36 .loc 1 226 11 is_stmt 0 view .LVU3 + 37 0000 1223 movs r3, #18 + 38 0002 0B80 strh r3, [r1] @ movhi + 227:USB_DEVICE/App/usbd_desc.c **** return USBD_FS_DeviceDesc; + 39 .loc 1 227 3 is_stmt 1 view .LVU4 + 228:USB_DEVICE/App/usbd_desc.c **** } + 40 .loc 1 228 1 is_stmt 0 view .LVU5 + 41 0004 0048 ldr r0, .L2 + 42 .LVL1: + 43 .loc 1 228 1 view .LVU6 + 44 0006 7047 bx lr + 45 .L3: + 46 .align 2 + 47 .L2: + 48 0008 00000000 .word .LANCHOR0 + 49 .cfi_endproc + 50 .LFE145: + 52 .section .text.USBD_FS_LangIDStrDescriptor,"ax",%progbits + 53 .align 1 + 54 .global USBD_FS_LangIDStrDescriptor + 55 .syntax unified + 56 .thumb + 57 .thumb_func + 58 .fpu fpv5-d16 + 60 USBD_FS_LangIDStrDescriptor: + ARM GAS /tmp/cc3RdOng.s page 6 + + + 61 .LVL2: + 62 .LFB146: + 229:USB_DEVICE/App/usbd_desc.c **** + 230:USB_DEVICE/App/usbd_desc.c **** /** + 231:USB_DEVICE/App/usbd_desc.c **** * @brief Return the LangID string descriptor + 232:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 233:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 234:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 235:USB_DEVICE/App/usbd_desc.c **** */ + 236:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 237:USB_DEVICE/App/usbd_desc.c **** { + 63 .loc 1 237 1 is_stmt 1 view -0 + 64 .cfi_startproc + 65 @ args = 0, pretend = 0, frame = 0 + 66 @ frame_needed = 0, uses_anonymous_args = 0 + 67 @ link register save eliminated. + 238:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 68 .loc 1 238 3 view .LVU8 + 239:USB_DEVICE/App/usbd_desc.c **** *length = sizeof(USBD_LangIDDesc); + 69 .loc 1 239 3 view .LVU9 + 70 .loc 1 239 11 is_stmt 0 view .LVU10 + 71 0000 0423 movs r3, #4 + 72 0002 0B80 strh r3, [r1] @ movhi + 240:USB_DEVICE/App/usbd_desc.c **** return USBD_LangIDDesc; + 73 .loc 1 240 3 is_stmt 1 view .LVU11 + 241:USB_DEVICE/App/usbd_desc.c **** } + 74 .loc 1 241 1 is_stmt 0 view .LVU12 + 75 0004 0048 ldr r0, .L5 + 76 .LVL3: + 77 .loc 1 241 1 view .LVU13 + 78 0006 7047 bx lr + 79 .L6: + 80 .align 2 + 81 .L5: + 82 0008 00000000 .word .LANCHOR1 + 83 .cfi_endproc + 84 .LFE146: + 86 .section .text.IntToUnicode,"ax",%progbits + 87 .align 1 + 88 .syntax unified + 89 .thumb + 90 .thumb_func + 91 .fpu fpv5-d16 + 93 IntToUnicode: + 94 .LVL4: + 95 .LFB153: + 242:USB_DEVICE/App/usbd_desc.c **** + 243:USB_DEVICE/App/usbd_desc.c **** /** + 244:USB_DEVICE/App/usbd_desc.c **** * @brief Return the product string descriptor + 245:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 246:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 247:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 248:USB_DEVICE/App/usbd_desc.c **** */ + 249:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 250:USB_DEVICE/App/usbd_desc.c **** { + 251:USB_DEVICE/App/usbd_desc.c **** if(speed == 0) + 252:USB_DEVICE/App/usbd_desc.c **** { + ARM GAS /tmp/cc3RdOng.s page 7 + + + 253:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + 254:USB_DEVICE/App/usbd_desc.c **** } + 255:USB_DEVICE/App/usbd_desc.c **** else + 256:USB_DEVICE/App/usbd_desc.c **** { + 257:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); + 258:USB_DEVICE/App/usbd_desc.c **** } + 259:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + 260:USB_DEVICE/App/usbd_desc.c **** } + 261:USB_DEVICE/App/usbd_desc.c **** + 262:USB_DEVICE/App/usbd_desc.c **** /** + 263:USB_DEVICE/App/usbd_desc.c **** * @brief Return the manufacturer string descriptor + 264:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 265:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 266:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 267:USB_DEVICE/App/usbd_desc.c **** */ + 268:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 269:USB_DEVICE/App/usbd_desc.c **** { + 270:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 271:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + 272:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + 273:USB_DEVICE/App/usbd_desc.c **** } + 274:USB_DEVICE/App/usbd_desc.c **** + 275:USB_DEVICE/App/usbd_desc.c **** /** + 276:USB_DEVICE/App/usbd_desc.c **** * @brief Return the serial number string descriptor + 277:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 278:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 279:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 280:USB_DEVICE/App/usbd_desc.c **** */ + 281:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 282:USB_DEVICE/App/usbd_desc.c **** { + 283:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 284:USB_DEVICE/App/usbd_desc.c **** *length = USB_SIZ_STRING_SERIAL; + 285:USB_DEVICE/App/usbd_desc.c **** + 286:USB_DEVICE/App/usbd_desc.c **** /* Update the serial number string descriptor with the data from the unique + 287:USB_DEVICE/App/usbd_desc.c **** * ID */ + 288:USB_DEVICE/App/usbd_desc.c **** Get_SerialNum(); + 289:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ + 290:USB_DEVICE/App/usbd_desc.c **** + 291:USB_DEVICE/App/usbd_desc.c **** /* USER CODE END USBD_FS_SerialStrDescriptor */ + 292:USB_DEVICE/App/usbd_desc.c **** return (uint8_t *) USBD_StringSerial; + 293:USB_DEVICE/App/usbd_desc.c **** } + 294:USB_DEVICE/App/usbd_desc.c **** + 295:USB_DEVICE/App/usbd_desc.c **** /** + 296:USB_DEVICE/App/usbd_desc.c **** * @brief Return the configuration string descriptor + 297:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 298:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 299:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 300:USB_DEVICE/App/usbd_desc.c **** */ + 301:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 302:USB_DEVICE/App/usbd_desc.c **** { + 303:USB_DEVICE/App/usbd_desc.c **** if(speed == USBD_SPEED_HIGH) + 304:USB_DEVICE/App/usbd_desc.c **** { + 305:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + 306:USB_DEVICE/App/usbd_desc.c **** } + 307:USB_DEVICE/App/usbd_desc.c **** else + 308:USB_DEVICE/App/usbd_desc.c **** { + 309:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + ARM GAS /tmp/cc3RdOng.s page 8 + + + 310:USB_DEVICE/App/usbd_desc.c **** } + 311:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + 312:USB_DEVICE/App/usbd_desc.c **** } + 313:USB_DEVICE/App/usbd_desc.c **** + 314:USB_DEVICE/App/usbd_desc.c **** /** + 315:USB_DEVICE/App/usbd_desc.c **** * @brief Return the interface string descriptor + 316:USB_DEVICE/App/usbd_desc.c **** * @param speed : Current device speed + 317:USB_DEVICE/App/usbd_desc.c **** * @param length : Pointer to data length variable + 318:USB_DEVICE/App/usbd_desc.c **** * @retval Pointer to descriptor buffer + 319:USB_DEVICE/App/usbd_desc.c **** */ + 320:USB_DEVICE/App/usbd_desc.c **** uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) + 321:USB_DEVICE/App/usbd_desc.c **** { + 322:USB_DEVICE/App/usbd_desc.c **** if(speed == 0) + 323:USB_DEVICE/App/usbd_desc.c **** { + 324:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + 325:USB_DEVICE/App/usbd_desc.c **** } + 326:USB_DEVICE/App/usbd_desc.c **** else + 327:USB_DEVICE/App/usbd_desc.c **** { + 328:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + 329:USB_DEVICE/App/usbd_desc.c **** } + 330:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + 331:USB_DEVICE/App/usbd_desc.c **** } + 332:USB_DEVICE/App/usbd_desc.c **** + 333:USB_DEVICE/App/usbd_desc.c **** /** + 334:USB_DEVICE/App/usbd_desc.c **** * @brief Create the serial number string descriptor + 335:USB_DEVICE/App/usbd_desc.c **** * @param None + 336:USB_DEVICE/App/usbd_desc.c **** * @retval None + 337:USB_DEVICE/App/usbd_desc.c **** */ + 338:USB_DEVICE/App/usbd_desc.c **** static void Get_SerialNum(void) + 339:USB_DEVICE/App/usbd_desc.c **** { + 340:USB_DEVICE/App/usbd_desc.c **** uint32_t deviceserial0, deviceserial1, deviceserial2; + 341:USB_DEVICE/App/usbd_desc.c **** + 342:USB_DEVICE/App/usbd_desc.c **** deviceserial0 = *(uint32_t *) DEVICE_ID1; + 343:USB_DEVICE/App/usbd_desc.c **** deviceserial1 = *(uint32_t *) DEVICE_ID2; + 344:USB_DEVICE/App/usbd_desc.c **** deviceserial2 = *(uint32_t *) DEVICE_ID3; + 345:USB_DEVICE/App/usbd_desc.c **** + 346:USB_DEVICE/App/usbd_desc.c **** deviceserial0 += deviceserial2; + 347:USB_DEVICE/App/usbd_desc.c **** + 348:USB_DEVICE/App/usbd_desc.c **** if (deviceserial0 != 0) + 349:USB_DEVICE/App/usbd_desc.c **** { + 350:USB_DEVICE/App/usbd_desc.c **** IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8); + 351:USB_DEVICE/App/usbd_desc.c **** IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); + 352:USB_DEVICE/App/usbd_desc.c **** } + 353:USB_DEVICE/App/usbd_desc.c **** } + 354:USB_DEVICE/App/usbd_desc.c **** + 355:USB_DEVICE/App/usbd_desc.c **** /** + 356:USB_DEVICE/App/usbd_desc.c **** * @brief Convert Hex 32Bits value into char + 357:USB_DEVICE/App/usbd_desc.c **** * @param value: value to convert + 358:USB_DEVICE/App/usbd_desc.c **** * @param pbuf: pointer to the buffer + 359:USB_DEVICE/App/usbd_desc.c **** * @param len: buffer length + 360:USB_DEVICE/App/usbd_desc.c **** * @retval None + 361:USB_DEVICE/App/usbd_desc.c **** */ + 362:USB_DEVICE/App/usbd_desc.c **** static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len) + 363:USB_DEVICE/App/usbd_desc.c **** { + 96 .loc 1 363 1 is_stmt 1 view -0 + 97 .cfi_startproc + 98 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/cc3RdOng.s page 9 + + + 99 @ frame_needed = 0, uses_anonymous_args = 0 + 364:USB_DEVICE/App/usbd_desc.c **** uint8_t idx = 0; + 100 .loc 1 364 3 view .LVU15 + 365:USB_DEVICE/App/usbd_desc.c **** + 366:USB_DEVICE/App/usbd_desc.c **** for (idx = 0; idx < len; idx++) + 101 .loc 1 366 3 view .LVU16 + 102 .loc 1 366 12 is_stmt 0 view .LVU17 + 103 0000 0023 movs r3, #0 + 104 .LVL5: + 105 .loc 1 366 17 is_stmt 1 view .LVU18 + 106 .loc 1 366 3 is_stmt 0 view .LVU19 + 107 0002 9342 cmp r3, r2 + 108 0004 1ED2 bcs .L15 + 363:USB_DEVICE/App/usbd_desc.c **** uint8_t idx = 0; + 109 .loc 1 363 1 view .LVU20 + 110 0006 00B5 push {lr} + 111 .LCFI0: + 112 .cfi_def_cfa_offset 4 + 113 .cfi_offset 14, -4 + 114 0008 10E0 b .L11 + 115 .L9: + 367:USB_DEVICE/App/usbd_desc.c **** { + 368:USB_DEVICE/App/usbd_desc.c **** if (((value >> 28)) < 0xA) + 369:USB_DEVICE/App/usbd_desc.c **** { + 370:USB_DEVICE/App/usbd_desc.c **** pbuf[2 * idx] = (value >> 28) + '0'; + 371:USB_DEVICE/App/usbd_desc.c **** } + 372:USB_DEVICE/App/usbd_desc.c **** else + 373:USB_DEVICE/App/usbd_desc.c **** { + 374:USB_DEVICE/App/usbd_desc.c **** pbuf[2 * idx] = (value >> 28) + 'A' - 10; + 116 .loc 1 374 7 is_stmt 1 view .LVU21 + 117 .loc 1 374 43 is_stmt 0 view .LVU22 + 118 000a 0CF1370C add ip, ip, #55 + 119 .loc 1 374 21 view .LVU23 + 120 000e 01F813C0 strb ip, [r1, r3, lsl #1] + 121 .L10: + 375:USB_DEVICE/App/usbd_desc.c **** } + 376:USB_DEVICE/App/usbd_desc.c **** + 377:USB_DEVICE/App/usbd_desc.c **** value = value << 4; + 122 .loc 1 377 5 is_stmt 1 discriminator 2 view .LVU24 + 123 .loc 1 377 11 is_stmt 0 discriminator 2 view .LVU25 + 124 0012 0001 lsls r0, r0, #4 + 125 .LVL6: + 378:USB_DEVICE/App/usbd_desc.c **** + 379:USB_DEVICE/App/usbd_desc.c **** pbuf[2 * idx + 1] = 0; + 126 .loc 1 379 5 is_stmt 1 discriminator 2 view .LVU26 + 127 .loc 1 379 12 is_stmt 0 discriminator 2 view .LVU27 + 128 0014 4FEA430C lsl ip, r3, #1 + 129 .loc 1 379 9 discriminator 2 view .LVU28 + 130 0018 0CF1010C add ip, ip, #1 + 131 .loc 1 379 23 discriminator 2 view .LVU29 + 132 001c 4FF0000E mov lr, #0 + 133 0020 01F80CE0 strb lr, [r1, ip] + 366:USB_DEVICE/App/usbd_desc.c **** { + 134 .loc 1 366 28 is_stmt 1 discriminator 2 view .LVU30 + 366:USB_DEVICE/App/usbd_desc.c **** { + 135 .loc 1 366 31 is_stmt 0 discriminator 2 view .LVU31 + 136 0024 0133 adds r3, r3, #1 + ARM GAS /tmp/cc3RdOng.s page 10 + + + 137 .LVL7: + 366:USB_DEVICE/App/usbd_desc.c **** { + 138 .loc 1 366 31 discriminator 2 view .LVU32 + 139 0026 DBB2 uxtb r3, r3 + 140 .LVL8: + 366:USB_DEVICE/App/usbd_desc.c **** { + 141 .loc 1 366 17 is_stmt 1 discriminator 2 view .LVU33 + 366:USB_DEVICE/App/usbd_desc.c **** { + 142 .loc 1 366 3 is_stmt 0 discriminator 2 view .LVU34 + 143 0028 9342 cmp r3, r2 + 144 002a 09D2 bcs .L16 + 145 .L11: + 368:USB_DEVICE/App/usbd_desc.c **** { + 146 .loc 1 368 5 is_stmt 1 view .LVU35 + 368:USB_DEVICE/App/usbd_desc.c **** { + 147 .loc 1 368 17 is_stmt 0 view .LVU36 + 148 002c 4FEA107C lsr ip, r0, #28 + 368:USB_DEVICE/App/usbd_desc.c **** { + 149 .loc 1 368 8 view .LVU37 + 150 0030 B0F1204F cmp r0, #-1610612736 + 151 0034 E9D2 bcs .L9 + 370:USB_DEVICE/App/usbd_desc.c **** } + 152 .loc 1 370 7 is_stmt 1 view .LVU38 + 370:USB_DEVICE/App/usbd_desc.c **** } + 153 .loc 1 370 37 is_stmt 0 view .LVU39 + 154 0036 0CF1300C add ip, ip, #48 + 370:USB_DEVICE/App/usbd_desc.c **** } + 155 .loc 1 370 21 view .LVU40 + 156 003a 01F813C0 strb ip, [r1, r3, lsl #1] + 157 003e E8E7 b .L10 + 158 .L16: + 380:USB_DEVICE/App/usbd_desc.c **** } + 381:USB_DEVICE/App/usbd_desc.c **** } + 159 .loc 1 381 1 view .LVU41 + 160 0040 5DF804FB ldr pc, [sp], #4 + 161 .L15: + 162 .LCFI1: + 163 .cfi_def_cfa_offset 0 + 164 .cfi_restore 14 + 165 .loc 1 381 1 view .LVU42 + 166 0044 7047 bx lr + 167 .cfi_endproc + 168 .LFE153: + 170 .section .text.Get_SerialNum,"ax",%progbits + 171 .align 1 + 172 .syntax unified + 173 .thumb + 174 .thumb_func + 175 .fpu fpv5-d16 + 177 Get_SerialNum: + 178 .LFB152: + 339:USB_DEVICE/App/usbd_desc.c **** uint32_t deviceserial0, deviceserial1, deviceserial2; + 179 .loc 1 339 1 is_stmt 1 view -0 + 180 .cfi_startproc + 181 @ args = 0, pretend = 0, frame = 0 + 182 @ frame_needed = 0, uses_anonymous_args = 0 + 183 0000 38B5 push {r3, r4, r5, lr} + ARM GAS /tmp/cc3RdOng.s page 11 + + + 184 .LCFI2: + 185 .cfi_def_cfa_offset 16 + 186 .cfi_offset 3, -16 + 187 .cfi_offset 4, -12 + 188 .cfi_offset 5, -8 + 189 .cfi_offset 14, -4 + 340:USB_DEVICE/App/usbd_desc.c **** + 190 .loc 1 340 3 view .LVU44 + 342:USB_DEVICE/App/usbd_desc.c **** deviceserial1 = *(uint32_t *) DEVICE_ID2; + 191 .loc 1 342 3 view .LVU45 + 342:USB_DEVICE/App/usbd_desc.c **** deviceserial1 = *(uint32_t *) DEVICE_ID2; + 192 .loc 1 342 17 is_stmt 0 view .LVU46 + 193 0002 0B4B ldr r3, .L21 + 194 0004 D3F80008 ldr r0, [r3, #2048] + 195 .LVL9: + 343:USB_DEVICE/App/usbd_desc.c **** deviceserial2 = *(uint32_t *) DEVICE_ID3; + 196 .loc 1 343 3 is_stmt 1 view .LVU47 + 343:USB_DEVICE/App/usbd_desc.c **** deviceserial2 = *(uint32_t *) DEVICE_ID3; + 197 .loc 1 343 17 is_stmt 0 view .LVU48 + 198 0008 D3F80448 ldr r4, [r3, #2052] + 199 .LVL10: + 344:USB_DEVICE/App/usbd_desc.c **** + 200 .loc 1 344 3 is_stmt 1 view .LVU49 + 344:USB_DEVICE/App/usbd_desc.c **** + 201 .loc 1 344 17 is_stmt 0 view .LVU50 + 202 000c D3F80838 ldr r3, [r3, #2056] + 203 .LVL11: + 346:USB_DEVICE/App/usbd_desc.c **** + 204 .loc 1 346 3 is_stmt 1 view .LVU51 + 348:USB_DEVICE/App/usbd_desc.c **** { + 205 .loc 1 348 3 view .LVU52 + 348:USB_DEVICE/App/usbd_desc.c **** { + 206 .loc 1 348 6 is_stmt 0 view .LVU53 + 207 0010 C018 adds r0, r0, r3 + 208 .LVL12: + 348:USB_DEVICE/App/usbd_desc.c **** { + 209 .loc 1 348 6 view .LVU54 + 210 0012 00D1 bne .L20 + 211 .LVL13: + 212 .L17: + 353:USB_DEVICE/App/usbd_desc.c **** + 213 .loc 1 353 1 view .LVU55 + 214 0014 38BD pop {r3, r4, r5, pc} + 215 .LVL14: + 216 .L20: + 350:USB_DEVICE/App/usbd_desc.c **** IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4); + 217 .loc 1 350 5 is_stmt 1 view .LVU56 + 218 0016 074D ldr r5, .L21+4 + 219 0018 0822 movs r2, #8 + 220 001a A91C adds r1, r5, #2 + 221 001c FFF7FEFF bl IntToUnicode + 222 .LVL15: + 351:USB_DEVICE/App/usbd_desc.c **** } + 223 .loc 1 351 5 view .LVU57 + 224 0020 0422 movs r2, #4 + 225 0022 05F11201 add r1, r5, #18 + 226 0026 2046 mov r0, r4 + ARM GAS /tmp/cc3RdOng.s page 12 + + + 227 0028 FFF7FEFF bl IntToUnicode + 228 .LVL16: + 353:USB_DEVICE/App/usbd_desc.c **** + 229 .loc 1 353 1 is_stmt 0 view .LVU58 + 230 002c F2E7 b .L17 + 231 .L22: + 232 002e 00BF .align 2 + 233 .L21: + 234 0030 00E0F11F .word 535945216 + 235 0034 00000000 .word .LANCHOR2 + 236 .cfi_endproc + 237 .LFE152: + 239 .section .text.USBD_FS_SerialStrDescriptor,"ax",%progbits + 240 .align 1 + 241 .global USBD_FS_SerialStrDescriptor + 242 .syntax unified + 243 .thumb + 244 .thumb_func + 245 .fpu fpv5-d16 + 247 USBD_FS_SerialStrDescriptor: + 248 .LVL17: + 249 .LFB149: + 282:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 250 .loc 1 282 1 is_stmt 1 view -0 + 251 .cfi_startproc + 252 @ args = 0, pretend = 0, frame = 0 + 253 @ frame_needed = 0, uses_anonymous_args = 0 + 282:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 254 .loc 1 282 1 is_stmt 0 view .LVU60 + 255 0000 08B5 push {r3, lr} + 256 .LCFI3: + 257 .cfi_def_cfa_offset 8 + 258 .cfi_offset 3, -8 + 259 .cfi_offset 14, -4 + 283:USB_DEVICE/App/usbd_desc.c **** *length = USB_SIZ_STRING_SERIAL; + 260 .loc 1 283 3 is_stmt 1 view .LVU61 + 284:USB_DEVICE/App/usbd_desc.c **** + 261 .loc 1 284 3 view .LVU62 + 284:USB_DEVICE/App/usbd_desc.c **** + 262 .loc 1 284 11 is_stmt 0 view .LVU63 + 263 0002 1A23 movs r3, #26 + 264 0004 0B80 strh r3, [r1] @ movhi + 288:USB_DEVICE/App/usbd_desc.c **** /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */ + 265 .loc 1 288 3 is_stmt 1 view .LVU64 + 266 0006 FFF7FEFF bl Get_SerialNum + 267 .LVL18: + 292:USB_DEVICE/App/usbd_desc.c **** } + 268 .loc 1 292 3 view .LVU65 + 293:USB_DEVICE/App/usbd_desc.c **** + 269 .loc 1 293 1 is_stmt 0 view .LVU66 + 270 000a 0148 ldr r0, .L25 + 271 000c 08BD pop {r3, pc} + 272 .L26: + 273 000e 00BF .align 2 + 274 .L25: + 275 0010 00000000 .word .LANCHOR2 + 276 .cfi_endproc + ARM GAS /tmp/cc3RdOng.s page 13 + + + 277 .LFE149: + 279 .section .rodata.USBD_FS_ProductStrDescriptor.str1.4,"aMS",%progbits,1 + 280 .align 2 + 281 .LC0: + 282 0000 53544D33 .ascii "STM32 DownLoad Firmware Update\000" + 282 3220446F + 282 776E4C6F + 282 61642046 + 282 69726D77 + 283 .section .text.USBD_FS_ProductStrDescriptor,"ax",%progbits + 284 .align 1 + 285 .global USBD_FS_ProductStrDescriptor + 286 .syntax unified + 287 .thumb + 288 .thumb_func + 289 .fpu fpv5-d16 + 291 USBD_FS_ProductStrDescriptor: + 292 .LVL19: + 293 .LFB147: + 250:USB_DEVICE/App/usbd_desc.c **** if(speed == 0) + 294 .loc 1 250 1 is_stmt 1 view -0 + 295 .cfi_startproc + 296 @ args = 0, pretend = 0, frame = 0 + 297 @ frame_needed = 0, uses_anonymous_args = 0 + 250:USB_DEVICE/App/usbd_desc.c **** if(speed == 0) + 298 .loc 1 250 1 is_stmt 0 view .LVU68 + 299 0000 08B5 push {r3, lr} + 300 .LCFI4: + 301 .cfi_def_cfa_offset 8 + 302 .cfi_offset 3, -8 + 303 .cfi_offset 14, -4 + 304 0002 0A46 mov r2, r1 + 251:USB_DEVICE/App/usbd_desc.c **** { + 305 .loc 1 251 3 is_stmt 1 view .LVU69 + 251:USB_DEVICE/App/usbd_desc.c **** { + 306 .loc 1 251 5 is_stmt 0 view .LVU70 + 307 0004 28B9 cbnz r0, .L28 + 253:USB_DEVICE/App/usbd_desc.c **** } + 308 .loc 1 253 5 is_stmt 1 view .LVU71 + 309 0006 0549 ldr r1, .L31 + 310 .LVL20: + 253:USB_DEVICE/App/usbd_desc.c **** } + 311 .loc 1 253 5 is_stmt 0 view .LVU72 + 312 0008 0548 ldr r0, .L31+4 + 313 .LVL21: + 253:USB_DEVICE/App/usbd_desc.c **** } + 314 .loc 1 253 5 view .LVU73 + 315 000a FFF7FEFF bl USBD_GetString + 316 .LVL22: + 317 .L29: + 259:USB_DEVICE/App/usbd_desc.c **** } + 318 .loc 1 259 3 is_stmt 1 view .LVU74 + 260:USB_DEVICE/App/usbd_desc.c **** + 319 .loc 1 260 1 is_stmt 0 view .LVU75 + 320 000e 0348 ldr r0, .L31 + 321 0010 08BD pop {r3, pc} + 322 .LVL23: + ARM GAS /tmp/cc3RdOng.s page 14 + + + 323 .L28: + 257:USB_DEVICE/App/usbd_desc.c **** } + 324 .loc 1 257 5 is_stmt 1 view .LVU76 + 325 0012 0249 ldr r1, .L31 + 326 .LVL24: + 257:USB_DEVICE/App/usbd_desc.c **** } + 327 .loc 1 257 5 is_stmt 0 view .LVU77 + 328 0014 0248 ldr r0, .L31+4 + 329 .LVL25: + 257:USB_DEVICE/App/usbd_desc.c **** } + 330 .loc 1 257 5 view .LVU78 + 331 0016 FFF7FEFF bl USBD_GetString + 332 .LVL26: + 257:USB_DEVICE/App/usbd_desc.c **** } + 333 .loc 1 257 5 view .LVU79 + 334 001a F8E7 b .L29 + 335 .L32: + 336 .align 2 + 337 .L31: + 338 001c 00000000 .word .LANCHOR3 + 339 0020 00000000 .word .LC0 + 340 .cfi_endproc + 341 .LFE147: + 343 .section .rodata.USBD_FS_ManufacturerStrDescriptor.str1.4,"aMS",%progbits,1 + 344 .align 2 + 345 .LC1: + 346 0000 53544D69 .ascii "STMicroelectronics\000" + 346 63726F65 + 346 6C656374 + 346 726F6E69 + 346 637300 + 347 .section .text.USBD_FS_ManufacturerStrDescriptor,"ax",%progbits + 348 .align 1 + 349 .global USBD_FS_ManufacturerStrDescriptor + 350 .syntax unified + 351 .thumb + 352 .thumb_func + 353 .fpu fpv5-d16 + 355 USBD_FS_ManufacturerStrDescriptor: + 356 .LVL27: + 357 .LFB148: + 269:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 358 .loc 1 269 1 is_stmt 1 view -0 + 359 .cfi_startproc + 360 @ args = 0, pretend = 0, frame = 0 + 361 @ frame_needed = 0, uses_anonymous_args = 0 + 269:USB_DEVICE/App/usbd_desc.c **** UNUSED(speed); + 362 .loc 1 269 1 is_stmt 0 view .LVU81 + 363 0000 10B5 push {r4, lr} + 364 .LCFI5: + 365 .cfi_def_cfa_offset 8 + 366 .cfi_offset 4, -8 + 367 .cfi_offset 14, -4 + 368 0002 0A46 mov r2, r1 + 270:USB_DEVICE/App/usbd_desc.c **** USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + 369 .loc 1 270 3 is_stmt 1 view .LVU82 + 271:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + ARM GAS /tmp/cc3RdOng.s page 15 + + + 370 .loc 1 271 3 view .LVU83 + 371 0004 034C ldr r4, .L35 + 372 0006 2146 mov r1, r4 + 373 .LVL28: + 271:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + 374 .loc 1 271 3 is_stmt 0 view .LVU84 + 375 0008 0348 ldr r0, .L35+4 + 376 .LVL29: + 271:USB_DEVICE/App/usbd_desc.c **** return USBD_StrDesc; + 377 .loc 1 271 3 view .LVU85 + 378 000a FFF7FEFF bl USBD_GetString + 379 .LVL30: + 272:USB_DEVICE/App/usbd_desc.c **** } + 380 .loc 1 272 3 is_stmt 1 view .LVU86 + 273:USB_DEVICE/App/usbd_desc.c **** + 381 .loc 1 273 1 is_stmt 0 view .LVU87 + 382 000e 2046 mov r0, r4 + 383 0010 10BD pop {r4, pc} + 384 .L36: + 385 0012 00BF .align 2 + 386 .L35: + 387 0014 00000000 .word .LANCHOR3 + 388 0018 00000000 .word .LC1 + 389 .cfi_endproc + 390 .LFE148: + 392 .section .rodata.USBD_FS_ConfigStrDescriptor.str1.4,"aMS",%progbits,1 + 393 .align 2 + 394 .LC2: + 395 0000 44465520 .ascii "DFU Config\000" + 395 436F6E66 + 395 696700 + 396 .section .text.USBD_FS_ConfigStrDescriptor,"ax",%progbits + 397 .align 1 + 398 .global USBD_FS_ConfigStrDescriptor + 399 .syntax unified + 400 .thumb + 401 .thumb_func + 402 .fpu fpv5-d16 + 404 USBD_FS_ConfigStrDescriptor: + 405 .LVL31: + 406 .LFB150: + 302:USB_DEVICE/App/usbd_desc.c **** if(speed == USBD_SPEED_HIGH) + 407 .loc 1 302 1 is_stmt 1 view -0 + 408 .cfi_startproc + 409 @ args = 0, pretend = 0, frame = 0 + 410 @ frame_needed = 0, uses_anonymous_args = 0 + 302:USB_DEVICE/App/usbd_desc.c **** if(speed == USBD_SPEED_HIGH) + 411 .loc 1 302 1 is_stmt 0 view .LVU89 + 412 0000 08B5 push {r3, lr} + 413 .LCFI6: + 414 .cfi_def_cfa_offset 8 + 415 .cfi_offset 3, -8 + 416 .cfi_offset 14, -4 + 417 0002 0A46 mov r2, r1 + 303:USB_DEVICE/App/usbd_desc.c **** { + 418 .loc 1 303 3 is_stmt 1 view .LVU90 + 303:USB_DEVICE/App/usbd_desc.c **** { + ARM GAS /tmp/cc3RdOng.s page 16 + + + 419 .loc 1 303 5 is_stmt 0 view .LVU91 + 420 0004 28B9 cbnz r0, .L38 + 305:USB_DEVICE/App/usbd_desc.c **** } + 421 .loc 1 305 5 is_stmt 1 view .LVU92 + 422 0006 0549 ldr r1, .L41 + 423 .LVL32: + 305:USB_DEVICE/App/usbd_desc.c **** } + 424 .loc 1 305 5 is_stmt 0 view .LVU93 + 425 0008 0548 ldr r0, .L41+4 + 426 .LVL33: + 305:USB_DEVICE/App/usbd_desc.c **** } + 427 .loc 1 305 5 view .LVU94 + 428 000a FFF7FEFF bl USBD_GetString + 429 .LVL34: + 430 .L39: + 311:USB_DEVICE/App/usbd_desc.c **** } + 431 .loc 1 311 3 is_stmt 1 view .LVU95 + 312:USB_DEVICE/App/usbd_desc.c **** + 432 .loc 1 312 1 is_stmt 0 view .LVU96 + 433 000e 0348 ldr r0, .L41 + 434 0010 08BD pop {r3, pc} + 435 .LVL35: + 436 .L38: + 309:USB_DEVICE/App/usbd_desc.c **** } + 437 .loc 1 309 5 is_stmt 1 view .LVU97 + 438 0012 0249 ldr r1, .L41 + 439 .LVL36: + 309:USB_DEVICE/App/usbd_desc.c **** } + 440 .loc 1 309 5 is_stmt 0 view .LVU98 + 441 0014 0248 ldr r0, .L41+4 + 442 .LVL37: + 309:USB_DEVICE/App/usbd_desc.c **** } + 443 .loc 1 309 5 view .LVU99 + 444 0016 FFF7FEFF bl USBD_GetString + 445 .LVL38: + 309:USB_DEVICE/App/usbd_desc.c **** } + 446 .loc 1 309 5 view .LVU100 + 447 001a F8E7 b .L39 + 448 .L42: + 449 .align 2 + 450 .L41: + 451 001c 00000000 .word .LANCHOR3 + 452 0020 00000000 .word .LC2 + 453 .cfi_endproc + 454 .LFE150: + 456 .section .rodata.USBD_FS_InterfaceStrDescriptor.str1.4,"aMS",%progbits,1 + 457 .align 2 + 458 .LC3: + 459 0000 44465520 .ascii "DFU Interface\000" + 459 496E7465 + 459 72666163 + 459 6500 + 460 .section .text.USBD_FS_InterfaceStrDescriptor,"ax",%progbits + 461 .align 1 + 462 .global USBD_FS_InterfaceStrDescriptor + 463 .syntax unified + 464 .thumb + ARM GAS /tmp/cc3RdOng.s page 17 + + + 465 .thumb_func + 466 .fpu fpv5-d16 + 468 USBD_FS_InterfaceStrDescriptor: + 469 .LVL39: + 470 .LFB151: + 321:USB_DEVICE/App/usbd_desc.c **** if(speed == 0) + 471 .loc 1 321 1 is_stmt 1 view -0 + 472 .cfi_startproc + 473 @ args = 0, pretend = 0, frame = 0 + 474 @ frame_needed = 0, uses_anonymous_args = 0 + 321:USB_DEVICE/App/usbd_desc.c **** if(speed == 0) + 475 .loc 1 321 1 is_stmt 0 view .LVU102 + 476 0000 08B5 push {r3, lr} + 477 .LCFI7: + 478 .cfi_def_cfa_offset 8 + 479 .cfi_offset 3, -8 + 480 .cfi_offset 14, -4 + 481 0002 0A46 mov r2, r1 + 322:USB_DEVICE/App/usbd_desc.c **** { + 482 .loc 1 322 3 is_stmt 1 view .LVU103 + 322:USB_DEVICE/App/usbd_desc.c **** { + 483 .loc 1 322 5 is_stmt 0 view .LVU104 + 484 0004 28B9 cbnz r0, .L44 + 324:USB_DEVICE/App/usbd_desc.c **** } + 485 .loc 1 324 5 is_stmt 1 view .LVU105 + 486 0006 0549 ldr r1, .L47 + 487 .LVL40: + 324:USB_DEVICE/App/usbd_desc.c **** } + 488 .loc 1 324 5 is_stmt 0 view .LVU106 + 489 0008 0548 ldr r0, .L47+4 + 490 .LVL41: + 324:USB_DEVICE/App/usbd_desc.c **** } + 491 .loc 1 324 5 view .LVU107 + 492 000a FFF7FEFF bl USBD_GetString + 493 .LVL42: + 494 .L45: + 330:USB_DEVICE/App/usbd_desc.c **** } + 495 .loc 1 330 3 is_stmt 1 view .LVU108 + 331:USB_DEVICE/App/usbd_desc.c **** + 496 .loc 1 331 1 is_stmt 0 view .LVU109 + 497 000e 0348 ldr r0, .L47 + 498 0010 08BD pop {r3, pc} + 499 .LVL43: + 500 .L44: + 328:USB_DEVICE/App/usbd_desc.c **** } + 501 .loc 1 328 5 is_stmt 1 view .LVU110 + 502 0012 0249 ldr r1, .L47 + 503 .LVL44: + 328:USB_DEVICE/App/usbd_desc.c **** } + 504 .loc 1 328 5 is_stmt 0 view .LVU111 + 505 0014 0248 ldr r0, .L47+4 + 506 .LVL45: + 328:USB_DEVICE/App/usbd_desc.c **** } + 507 .loc 1 328 5 view .LVU112 + 508 0016 FFF7FEFF bl USBD_GetString + 509 .LVL46: + 328:USB_DEVICE/App/usbd_desc.c **** } + ARM GAS /tmp/cc3RdOng.s page 18 + + + 510 .loc 1 328 5 view .LVU113 + 511 001a F8E7 b .L45 + 512 .L48: + 513 .align 2 + 514 .L47: + 515 001c 00000000 .word .LANCHOR3 + 516 0020 00000000 .word .LC3 + 517 .cfi_endproc + 518 .LFE151: + 520 .global USBD_StringSerial + 521 .global USBD_StrDesc + 522 .global USBD_LangIDDesc + 523 .global USBD_FS_DeviceDesc + 524 .global FS_Desc + 525 .section .bss.USBD_StrDesc,"aw",%nobits + 526 .align 2 + 527 .set .LANCHOR3,. + 0 + 530 USBD_StrDesc: + 531 0000 00000000 .space 512 + 531 00000000 + 531 00000000 + 531 00000000 + 531 00000000 + 532 .section .data.FS_Desc,"aw" + 533 .align 2 + 536 FS_Desc: + 537 0000 00000000 .word USBD_FS_DeviceDescriptor + 538 0004 00000000 .word USBD_FS_LangIDStrDescriptor + 539 0008 00000000 .word USBD_FS_ManufacturerStrDescriptor + 540 000c 00000000 .word USBD_FS_ProductStrDescriptor + 541 0010 00000000 .word USBD_FS_SerialStrDescriptor + 542 0014 00000000 .word USBD_FS_ConfigStrDescriptor + 543 0018 00000000 .word USBD_FS_InterfaceStrDescriptor + 544 .section .data.USBD_FS_DeviceDesc,"aw" + 545 .align 2 + 546 .set .LANCHOR0,. + 0 + 549 USBD_FS_DeviceDesc: + 550 0000 12010002 .ascii "\022\001\000\002\000\000\000@\203\004\021\337\000\002" + 550 00000040 + 550 830411DF + 550 0002 + 551 000e 01020301 .ascii "\001\002\003\001" + 552 .section .data.USBD_LangIDDesc,"aw" + 553 .align 2 + 554 .set .LANCHOR1,. + 0 + 557 USBD_LangIDDesc: + 558 0000 04030904 .ascii "\004\003\011\004" + 559 .section .data.USBD_StringSerial,"aw" + 560 .align 2 + 561 .set .LANCHOR2,. + 0 + 564 USBD_StringSerial: + 565 0000 1A0300 .ascii "\032\003\000" + 566 0003 00000000 .space 23 + 566 00000000 + 566 00000000 + 566 00000000 + 566 00000000 + ARM GAS /tmp/cc3RdOng.s page 19 + + + 567 .text + 568 .Letext0: + 569 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 570 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 571 .file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 572 .file 5 "USB_DEVICE/App/usbd_desc.h" + 573 .file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h" + ARM GAS /tmp/cc3RdOng.s page 20 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_desc.c + /tmp/cc3RdOng.s:17 .text.USBD_FS_DeviceDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:25 .text.USBD_FS_DeviceDescriptor:0000000000000000 USBD_FS_DeviceDescriptor + /tmp/cc3RdOng.s:48 .text.USBD_FS_DeviceDescriptor:0000000000000008 $d + /tmp/cc3RdOng.s:53 .text.USBD_FS_LangIDStrDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:60 .text.USBD_FS_LangIDStrDescriptor:0000000000000000 USBD_FS_LangIDStrDescriptor + /tmp/cc3RdOng.s:82 .text.USBD_FS_LangIDStrDescriptor:0000000000000008 $d + /tmp/cc3RdOng.s:87 .text.IntToUnicode:0000000000000000 $t + /tmp/cc3RdOng.s:93 .text.IntToUnicode:0000000000000000 IntToUnicode + /tmp/cc3RdOng.s:171 .text.Get_SerialNum:0000000000000000 $t + /tmp/cc3RdOng.s:177 .text.Get_SerialNum:0000000000000000 Get_SerialNum + /tmp/cc3RdOng.s:234 .text.Get_SerialNum:0000000000000030 $d + /tmp/cc3RdOng.s:240 .text.USBD_FS_SerialStrDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:247 .text.USBD_FS_SerialStrDescriptor:0000000000000000 USBD_FS_SerialStrDescriptor + /tmp/cc3RdOng.s:275 .text.USBD_FS_SerialStrDescriptor:0000000000000010 $d + /tmp/cc3RdOng.s:280 .rodata.USBD_FS_ProductStrDescriptor.str1.4:0000000000000000 $d + /tmp/cc3RdOng.s:284 .text.USBD_FS_ProductStrDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:291 .text.USBD_FS_ProductStrDescriptor:0000000000000000 USBD_FS_ProductStrDescriptor + /tmp/cc3RdOng.s:338 .text.USBD_FS_ProductStrDescriptor:000000000000001c $d + /tmp/cc3RdOng.s:344 .rodata.USBD_FS_ManufacturerStrDescriptor.str1.4:0000000000000000 $d + /tmp/cc3RdOng.s:348 .text.USBD_FS_ManufacturerStrDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:355 .text.USBD_FS_ManufacturerStrDescriptor:0000000000000000 USBD_FS_ManufacturerStrDescriptor + /tmp/cc3RdOng.s:387 .text.USBD_FS_ManufacturerStrDescriptor:0000000000000014 $d + /tmp/cc3RdOng.s:393 .rodata.USBD_FS_ConfigStrDescriptor.str1.4:0000000000000000 $d + /tmp/cc3RdOng.s:397 .text.USBD_FS_ConfigStrDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:404 .text.USBD_FS_ConfigStrDescriptor:0000000000000000 USBD_FS_ConfigStrDescriptor + /tmp/cc3RdOng.s:451 .text.USBD_FS_ConfigStrDescriptor:000000000000001c $d + /tmp/cc3RdOng.s:457 .rodata.USBD_FS_InterfaceStrDescriptor.str1.4:0000000000000000 $d + /tmp/cc3RdOng.s:461 .text.USBD_FS_InterfaceStrDescriptor:0000000000000000 $t + /tmp/cc3RdOng.s:468 .text.USBD_FS_InterfaceStrDescriptor:0000000000000000 USBD_FS_InterfaceStrDescriptor + /tmp/cc3RdOng.s:515 .text.USBD_FS_InterfaceStrDescriptor:000000000000001c $d + /tmp/cc3RdOng.s:564 .data.USBD_StringSerial:0000000000000000 USBD_StringSerial + /tmp/cc3RdOng.s:530 .bss.USBD_StrDesc:0000000000000000 USBD_StrDesc + /tmp/cc3RdOng.s:557 .data.USBD_LangIDDesc:0000000000000000 USBD_LangIDDesc + /tmp/cc3RdOng.s:549 .data.USBD_FS_DeviceDesc:0000000000000000 USBD_FS_DeviceDesc + /tmp/cc3RdOng.s:536 .data.FS_Desc:0000000000000000 FS_Desc + /tmp/cc3RdOng.s:526 .bss.USBD_StrDesc:0000000000000000 $d + /tmp/cc3RdOng.s:533 .data.FS_Desc:0000000000000000 $d + /tmp/cc3RdOng.s:545 .data.USBD_FS_DeviceDesc:0000000000000000 $d + /tmp/cc3RdOng.s:553 .data.USBD_LangIDDesc:0000000000000000 $d + /tmp/cc3RdOng.s:560 .data.USBD_StringSerial:0000000000000000 $d + +UNDEFINED SYMBOLS +USBD_GetString diff --git a/build/usbd_desc.o b/build/usbd_desc.o new file mode 100644 index 0000000..23f6804 Binary files /dev/null and b/build/usbd_desc.o differ diff --git a/build/usbd_dfu.d b/build/usbd_dfu.d new file mode 100644 index 0000000..587d584 --- /dev/null +++ b/build/usbd_dfu.d @@ -0,0 +1,89 @@ +build/usbd_dfu.o: \ + Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c \ + Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/build/usbd_dfu.lst b/build/usbd_dfu.lst new file mode 100644 index 0000000..139b72e --- /dev/null +++ b/build/usbd_dfu.lst @@ -0,0 +1,7229 @@ +ARM GAS /tmp/ccyvpZhC.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_dfu.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.USBD_DFU_GetCfgDesc,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 USBD_DFU_GetCfgDesc: + 25 .LVL0: + 26 .LFB148: + 27 .file 1 "Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c" + 1:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 2:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ****************************************************************************** + 3:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @file usbd_dfu.c + 4:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @author MCD Application Team + 5:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief This file provides the DFU core functions. + 6:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 7:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @verbatim + 8:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 9:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * =================================================================== + 10:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * DFU Class Driver Description + 11:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * =================================================================== + 12:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * This driver manages the DFU class V1.1 following the "Device Class Specification for + 13:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Device Firmware Upgrade Version 1.1 Aug 5, 2004". + 14:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * This driver implements the following aspects of the specification: + 15:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - Device descriptor management + 16:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - Configuration descriptor management + 17:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - Enumeration as DFU device (in DFU mode only) + 18:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - Requests management (supporting ST DFU sub-protocol) + 19:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus) + 20:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - DFU state machine implementation. + 21:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 22:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @note + 23:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage + 24:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * memory addressing, commands processing, specific memories operations (ie. Erase) ... + 25:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * As required by the DFU specification, only endpoint 0 is used in this application. + 26:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Other endpoints and functions may be added to the application (ie. DFU ...) + 27:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 28:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * These aspects may be enriched or modified for a specific user application. + 29:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 30:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * This driver doesn't implement the following aspects of the specification + 31:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * (but it is possible to manage these features with some modifications on this driver): + ARM GAS /tmp/ccyvpZhC.s page 2 + + + 32:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * - Manifestation Tolerant mode + 33:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 34:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @endverbatim + 35:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 36:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ****************************************************************************** + 37:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @attention + 38:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 39:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** *

© Copyright (c) 2015 STMicroelectronics. + 40:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * All rights reserved.

+ 41:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 42:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * This software component is licensed by ST under Ultimate Liberty license + 43:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 44:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * the License. You may obtain a copy of the License at: + 45:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * www.st.com/SLA0044 + 46:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * + 47:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ****************************************************************************** + 48:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 49:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 50:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* BSPDependencies + 51:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** - "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" + 52:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** - "stm32xxxxx_{eval}{discovery}_io.c" + 53:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** EndBSPDependencies */ + 54:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 55:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Includes ------------------------------------------------------------------*/ + 56:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #include "usbd_dfu.h" + 57:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #include "usbd_ctlreq.h" + 58:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 59:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 60:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @addtogroup STM32_USB_DEVICE_LIBRARY + 61:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 62:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 63:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 64:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 65:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU + 66:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief usbd core module + 67:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 68:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 69:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 70:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU_Private_TypesDefinitions + 71:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 72:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 73:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 74:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @} + 75:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 76:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 77:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 78:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU_Private_Defines + 79:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 80:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 81:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 82:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 83:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @} + 84:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 85:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 86:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 87:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU_Private_Macros + 88:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + ARM GAS /tmp/ccyvpZhC.s page 3 + + + 89:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 90:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 91:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 92:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @} + 93:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 94:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 95:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 96:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU_Private_FunctionPrototypes + 97:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 98:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 99:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 100:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + 101:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + 102:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 103:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev); + 104:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev); + 105:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev); + 106:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 107:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length); + 108:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length); + 109:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 110:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U) + 111:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, + 112:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t index, uint16_t *length); + 113:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif + 114:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 115:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 116:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 117:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); + 118:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_GetStatus(USBD_HandleTypeDef *pdev); + 119:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_ClearStatus(USBD_HandleTypeDef *pdev); + 120:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_GetState(USBD_HandleTypeDef *pdev); + 121:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Abort(USBD_HandleTypeDef *pdev); + 122:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Leave(USBD_HandleTypeDef *pdev); + 123:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 124:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 125:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @} + 126:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 127:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 128:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU_Private_Variables + 129:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 130:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 131:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 132:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_ClassTypeDef USBD_DFU = + 133:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 134:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_Init, + 135:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_DeInit, + 136:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_Setup, + 137:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_EP0_TxReady, + 138:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_EP0_RxReady, + 139:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** NULL, + 140:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** NULL, + 141:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_SOF, + 142:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** NULL, + 143:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** NULL, + 144:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_GetCfgDesc, + 145:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_GetCfgDesc, + ARM GAS /tmp/ccyvpZhC.s page 4 + + + 146:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_GetCfgDesc, + 147:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_GetDeviceQualifierDesc, + 148:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U) + 149:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_GetUsrStringDesc + 150:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif + 151:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** }; + 152:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 153:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* USB DFU device Configuration Descriptor */ + 154:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** __ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = + 155:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 156:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x09, /* bLength: Configuation Descriptor size */ + 157:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 158:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USB_DFU_CONFIG_DESC_SIZ, + 159:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* wTotalLength: Bytes returned */ + 160:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 161:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x01, /* bNumInterfaces: 1 interface */ + 162:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x01, /* bConfigurationValue: Configuration value + 163:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x02, /* iConfiguration: Index of string descripto + 164:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0xC0, /* bmAttributes: bus powered and Supprts Rem + 165:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x32, /* MaxPower 100 mA: this current is used for + 166:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* 09 */ + 167:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 168:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ + 169:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_IF_DESC(0U), /* This interface is mandatory for all devic + 170:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 171:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_DFU_MAX_ITF_NUM > 1U) + 172:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ + 173:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_IF_DESC(1), + 174:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif /* (USBD_DFU_MAX_ITF_NUM > 1) */ + 175:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 176:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_DFU_MAX_ITF_NUM > 2U) + 177:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ + 178:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_IF_DESC(2), + 179:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif /* (USBD_DFU_MAX_ITF_NUM > 2) */ + 180:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 181:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_DFU_MAX_ITF_NUM > 3U) + 182:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ + 183:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_IF_DESC(3), + 184:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif /* (USBD_DFU_MAX_ITF_NUM > 3) */ + 185:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 186:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_DFU_MAX_ITF_NUM > 4U) + 187:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ + 188:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_IF_DESC(4), + 189:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif /* (USBD_DFU_MAX_ITF_NUM > 4) */ + 190:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 191:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_DFU_MAX_ITF_NUM > 5U) + 192:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ + 193:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_IF_DESC(5), + 194:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif /* (USBD_DFU_MAX_ITF_NUM > 5) */ + 195:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 196:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_DFU_MAX_ITF_NUM > 6U) + 197:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" + 198:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif /* (USBD_DFU_MAX_ITF_NUM > 6) */ + 199:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 200:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /******************** DFU Functional Descriptor********************/ + 201:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x09, /* blength = 9 Bytes */ + 202:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor */ + ARM GAS /tmp/ccyvpZhC.s page 5 + + + 203:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x0B, /* bmAttribute: + 204:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** bitCanDnload = 1 (bit 0) + 205:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** bitCanUpload = 1 (bit 1) + 206:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** bitManifestationTolerant = 0 (bit 2) + 207:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** bitWillDetach = 1 (bit 3) + 208:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** Reserved (bit4-6 + 209:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** bitAcceleratedST = 0 (bit 7) + 210:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0xFF, /* DetachTimeOut= 255 ms*/ + 211:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 212:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* WARNING: In DMA mode the multiple MPS packets feature is still not supported + 213:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ==> In this case, when using DMA USBD_DFU_XFER_SIZE should be set to 64 in usbd_conf.h */ + 214:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE), /* TransferSize = 1024 Byte */ + 215:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x1A, /* bcdDFUVersion */ + 216:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x01 + 217:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /***********************************************************/ + 218:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* 9*/ + 219:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** }; + 220:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 221:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* USB Standard Device Descriptor */ + 222:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** __ALIGN_BEGIN static uint8_t USBD_DFU_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = + 223:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 224:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USB_LEN_DEV_QUALIFIER_DESC, + 225:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USB_DESC_TYPE_DEVICE_QUALIFIER, + 226:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 227:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x02, + 228:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 229:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 230:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 231:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x40, + 232:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x01, + 233:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** 0x00, + 234:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** }; + 235:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 236:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 237:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @} + 238:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 239:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 240:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** @defgroup USBD_DFU_Private_Functions + 241:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @{ + 242:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 243:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 244:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 245:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_Init + 246:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Initialize the DFU interface + 247:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 248:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param cfgidx: Configuration index + 249:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 250:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 251:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) + 252:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 253:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(cfgidx); + 254:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 255:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu; + 256:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 257:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Allocate Audio structure */ + 258:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu = USBD_malloc(sizeof(USBD_DFU_HandleTypeDef)); + 259:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + ARM GAS /tmp/ccyvpZhC.s page 6 + + + 260:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu == NULL) + 261:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 262:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** pdev->pClassData = NULL; + 263:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_EMEM; + 264:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 265:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 266:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** pdev->pClassData = (void *)hdfu; + 267:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 268:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->alt_setting = 0U; + 269:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; + 270:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 271:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 272:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 273:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->manif_state = DFU_MANIFEST_COMPLETE; + 274:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 275:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 276:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 277:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 278:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 279:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 280:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = DFU_STATE_IDLE; + 281:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; + 282:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 283:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Initialize Hardware layer */ + 284:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK) + 285:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 286:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_FAIL; + 287:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 288:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 289:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_OK; + 290:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 291:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 292:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 293:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_Init + 294:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * De-Initialize the DFU layer + 295:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 296:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param cfgidx: Configuration index + 297:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 298:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 299:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) + 300:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 301:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(cfgidx); + 302:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu; + 303:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 304:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (pdev->pClassData == NULL) + 305:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 306:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_EMEM; + 307:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 308:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 309:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 310:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 311:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 312:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 313:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 314:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 315:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = DFU_STATE_IDLE; + 316:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + ARM GAS /tmp/ccyvpZhC.s page 7 + + + 317:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* DeInit physical Interface components and Hardware Layer */ + 318:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); + 319:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_free(pdev->pClassData); + 320:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** pdev->pClassData = NULL; + 321:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 322:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_OK; + 323:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 324:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 325:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 326:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_Setup + 327:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handle the DFU specific requests + 328:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: instance + 329:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param req: usb requests + 330:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 331:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 332:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 333:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 334:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_StatusTypeDef ret = USBD_OK; + 336:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 337:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint16_t len = 0U; + 338:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint16_t status_info = 0U; + 339:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 340:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** switch (req->bmRequest & USB_REQ_TYPE_MASK) + 341:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 342:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_TYPE_CLASS: + 343:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** switch (req->bRequest) + 344:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 345:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_DNLOAD: + 346:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_Download(pdev, req); + 347:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 348:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 349:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_UPLOAD: + 350:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_Upload(pdev, req); + 351:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 352:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 353:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_GETSTATUS: + 354:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_GetStatus(pdev); + 355:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 356:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 357:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_CLRSTATUS: + 358:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_ClearStatus(pdev); + 359:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 360:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 361:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_GETSTATE: + 362:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_GetState(pdev); + 363:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 364:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 365:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_ABORT: + 366:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_Abort(pdev); + 367:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 368:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 369:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_DETACH: + 370:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_Detach(pdev, req); + 371:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 372:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 373:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** default: + ARM GAS /tmp/ccyvpZhC.s page 8 + + + 374:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 375:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 376:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 377:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 378:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 379:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 380:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_TYPE_STANDARD: + 381:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** switch (req->bRequest) + 382:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 383:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_GET_STATUS: + 384:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (pdev->dev_state == USBD_STATE_CONFIGURED) + 385:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 386:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + 387:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 388:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 389:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 390:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 391:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 392:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 393:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 394:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 395:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_GET_DESCRIPTOR: + 396:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) + 397:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 398:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** pbuf = USBD_DFU_CfgDesc + (9U * (USBD_DFU_MAX_ITF_NUM + 1U)); + 399:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** len = MIN(USB_DFU_DESC_SIZ, req->wLength); + 400:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 401:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 402:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, pbuf, len); + 403:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 404:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 405:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_GET_INTERFACE: + 406:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (pdev->dev_state == USBD_STATE_CONFIGURED) + 407:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)hdfu->alt_setting, 1U); + 409:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 410:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 411:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 412:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 413:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 414:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 415:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 416:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 417:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_SET_INTERFACE: + 418:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM) + 419:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 420:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (pdev->dev_state == USBD_STATE_CONFIGURED) + 421:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 422:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->alt_setting = (uint8_t)(req->wValue); + 423:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 424:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 425:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 426:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 427:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 428:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 429:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 430:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + ARM GAS /tmp/ccyvpZhC.s page 9 + + + 431:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 432:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked */ + 433:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 434:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 435:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 436:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 437:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 438:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case USB_REQ_CLEAR_FEATURE: + 439:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 440:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 441:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** default: + 442:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 443:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 444:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 445:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 446:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 447:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 448:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** default: + 449:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 450:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 451:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 452:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 453:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 454:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)ret; + 455:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 456:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 457:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 458:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 459:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_GetCfgDesc + 460:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * return configuration descriptor + 461:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param speed : current device speed + 462:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param length : pointer data length + 463:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval pointer to descriptor buffer + 464:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 465:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length) + 466:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 28 .loc 1 466 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 467:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** *length = (uint16_t)sizeof(USBD_DFU_CfgDesc); + 33 .loc 1 467 3 view .LVU1 + 34 .loc 1 467 11 is_stmt 0 view .LVU2 + 35 0000 1B23 movs r3, #27 + 36 0002 0380 strh r3, [r0] @ movhi + 468:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 469:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return USBD_DFU_CfgDesc; + 37 .loc 1 469 3 is_stmt 1 view .LVU3 + 470:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 38 .loc 1 470 1 is_stmt 0 view .LVU4 + 39 0004 0048 ldr r0, .L2 + 40 .LVL1: + 41 .loc 1 470 1 view .LVU5 + 42 0006 7047 bx lr + 43 .L3: + 44 .align 2 + ARM GAS /tmp/ccyvpZhC.s page 10 + + + 45 .L2: + 46 0008 00000000 .word .LANCHOR0 + 47 .cfi_endproc + 48 .LFE148: + 50 .section .text.USBD_DFU_EP0_RxReady,"ax",%progbits + 51 .align 1 + 52 .syntax unified + 53 .thumb + 54 .thumb_func + 55 .fpu fpv5-d16 + 57 USBD_DFU_EP0_RxReady: + 58 .LVL2: + 59 .LFB149: + 471:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 472:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 473:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 474:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_EP0_RxReady + 475:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * handle EP0 Rx Ready event + 476:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 477:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 478:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 479:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) + 480:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 60 .loc 1 480 1 is_stmt 1 view -0 + 61 .cfi_startproc + 62 @ args = 0, pretend = 0, frame = 0 + 63 @ frame_needed = 0, uses_anonymous_args = 0 + 64 @ link register save eliminated. + 481:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(pdev); + 65 .loc 1 481 3 view .LVU7 + 482:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 483:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_OK; + 66 .loc 1 483 3 view .LVU8 + 484:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 67 .loc 1 484 1 is_stmt 0 view .LVU9 + 68 0000 0020 movs r0, #0 + 69 .LVL3: + 70 .loc 1 484 1 view .LVU10 + 71 0002 7047 bx lr + 72 .cfi_endproc + 73 .LFE149: + 75 .section .text.USBD_DFU_SOF,"ax",%progbits + 76 .align 1 + 77 .syntax unified + 78 .thumb + 79 .thumb_func + 80 .fpu fpv5-d16 + 82 USBD_DFU_SOF: + 83 .LVL4: + 84 .LFB151: + 485:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 486:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_EP0_TxReady + 487:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * handle EP0 TRx Ready event + 488:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 489:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 490:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 491:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) + ARM GAS /tmp/ccyvpZhC.s page 11 + + + 492:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 493:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_SetupReqTypedef req; + 494:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint32_t addr; + 495:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 496:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 497:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 498:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->dev_state == DFU_STATE_DNLOAD_BUSY) + 499:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 500:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Decode the Special Command*/ + 501:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->wblock_num == 0U) + 502:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 503:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if(hdfu->wlength == 1U) + 504:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 505:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->buffer.d8[0] == DFU_CMD_GETCOMMANDS) + 506:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 507:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* nothink to do */ + 508:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 509:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 510:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else if (hdfu->wlength == 5U) + 511:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 512:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER) + 513:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 514:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr = hdfu->buffer.d8[1]; + 515:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 516:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 517:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 518:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 519:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else if (hdfu->buffer.d8[0] == DFU_CMD_ERASE) + 520:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 521:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr = hdfu->buffer.d8[1]; + 522:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 523:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 524:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 525:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 526:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (DfuInterface->Erase(hdfu->data_ptr) != USBD_OK) + 527:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 528:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_FAIL; + 529:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 530:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 531:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 532:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 533:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* .. */ + 534:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 535:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 536:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 537:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 538:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Reset the global length and block number */ + 539:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 540:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 541:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked) */ + 542:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** req.bmRequest = 0U; + 543:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** req.wLength = 1U; + 544:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, &req); + 545:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 546:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 547:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Regular Download Command */ + 548:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + ARM GAS /tmp/ccyvpZhC.s page 12 + + + 549:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 550:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->wblock_num > 1U) + 551:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 552:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Decode the required address */ + 553:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; + 554:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 555:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Preform the write operation */ + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (DfuInterface->Write(hdfu->buffer.d8, (uint8_t *)addr, hdfu->wlength) != USBD_OK) + 557:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 558:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_FAIL; + 559:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 560:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 561:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 562:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 563:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Reset the global length and block number */ + 564:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 565:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 566:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 567:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Update the state machine */ + 568:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_DNLOAD_SYNC; + 569:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 570:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 571:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 572:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 573:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 574:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 575:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress */ + 576:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 577:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Start leaving DFU mode */ + 578:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU_Leave(pdev); + 579:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 580:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 581:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 582:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* .. */ + 583:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 584:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 585:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_OK; + 586:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 587:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 588:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_SOF + 589:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * handle SOF event + 590:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 591:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 592:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 593:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev) + 594:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 85 .loc 1 594 1 is_stmt 1 view -0 + 86 .cfi_startproc + 87 @ args = 0, pretend = 0, frame = 0 + 88 @ frame_needed = 0, uses_anonymous_args = 0 + 89 @ link register save eliminated. + 595:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(pdev); + 90 .loc 1 595 3 view .LVU12 + 596:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 597:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_OK; + 91 .loc 1 597 3 view .LVU13 + 598:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + ARM GAS /tmp/ccyvpZhC.s page 13 + + + 92 .loc 1 598 1 is_stmt 0 view .LVU14 + 93 0000 0020 movs r0, #0 + 94 .LVL5: + 95 .loc 1 598 1 view .LVU15 + 96 0002 7047 bx lr + 97 .cfi_endproc + 98 .LFE151: + 100 .section .text.USBD_DFU_GetDeviceQualifierDesc,"ax",%progbits + 101 .align 1 + 102 .syntax unified + 103 .thumb + 104 .thumb_func + 105 .fpu fpv5-d16 + 107 USBD_DFU_GetDeviceQualifierDesc: + 108 .LVL6: + 109 .LFB152: + 599:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 600:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 601:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 602:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DeviceQualifierDescriptor + 603:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * return Device Qualifier descriptor + 604:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param length : pointer data length + 605:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval pointer to descriptor buffer + 606:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 607:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) + 608:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 110 .loc 1 608 1 is_stmt 1 view -0 + 111 .cfi_startproc + 112 @ args = 0, pretend = 0, frame = 0 + 113 @ frame_needed = 0, uses_anonymous_args = 0 + 114 @ link register save eliminated. + 609:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** *length = (uint16_t)sizeof(USBD_DFU_DeviceQualifierDesc); + 115 .loc 1 609 3 view .LVU17 + 116 .loc 1 609 11 is_stmt 0 view .LVU18 + 117 0000 0A23 movs r3, #10 + 118 0002 0380 strh r3, [r0] @ movhi + 610:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 611:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return USBD_DFU_DeviceQualifierDesc; + 119 .loc 1 611 3 is_stmt 1 view .LVU19 + 612:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 120 .loc 1 612 1 is_stmt 0 view .LVU20 + 121 0004 0048 ldr r0, .L7 + 122 .LVL7: + 123 .loc 1 612 1 view .LVU21 + 124 0006 7047 bx lr + 125 .L8: + 126 .align 2 + 127 .L7: + 128 0008 00000000 .word .LANCHOR1 + 129 .cfi_endproc + 130 .LFE152: + 132 .section .text.DFU_ClearStatus,"ax",%progbits + 133 .align 1 + 134 .syntax unified + 135 .thumb + 136 .thumb_func + 137 .fpu fpv5-d16 + ARM GAS /tmp/ccyvpZhC.s page 14 + + + 139 DFU_ClearStatus: + 140 .LVL8: + 141 .LFB159: + 613:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 614:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 615:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_DFU_GetUsrStringDesc + 616:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Manages the transfer of memory interfaces string descriptors. + 617:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param speed : current device speed + 618:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param index: desciptor index + 619:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param length : pointer data length + 620:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval pointer to the descriptor table or NULL if the descriptor is not supported. + 621:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 622:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #if (USBD_SUPPORT_USER_STRING_DESC == 1U) + 623:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length + 624:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 625:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_StrDesc[255]; + 626:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 627:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 628:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Check if the requested string interface is supported */ + 629:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (index <= (USBD_IDX_INTERFACE_STR + USBD_DFU_MAX_ITF_NUM)) + 630:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 631:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_GetString((uint8_t *)DfuInterface->pStrDesc, USBD_StrDesc, length); + 632:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return USBD_StrDesc; + 633:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 634:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 635:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 636:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Not supported Interface Descriptor index */ + 637:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return NULL; + 638:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 639:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 640:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif + 641:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 642:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 643:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief USBD_MSC_RegisterStorage + 644:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param fops: storage callback + 645:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 646:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 647:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, + 648:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *fops) + 649:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 650:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (fops == NULL) + 651:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 652:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_FAIL; + 653:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 654:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 655:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** pdev->pUserData = fops; + 656:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 657:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_OK; + 658:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 659:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 660:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /****************************************************************************** + 661:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DFU Class requests management + 662:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ******************************************************************************/ + 663:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 664:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_Detach + 665:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU DETACH request. + 666:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + ARM GAS /tmp/ccyvpZhC.s page 15 + + + 667:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param req: pointer to the request structure. + 668:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval None. + 669:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 670:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 671:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 672:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 673:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 674:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->dev_state == DFU_STATE_IDLE) || + 675:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + 676:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + 677:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + 678:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) + 679:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 680:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Update the state machine */ + 681:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 682:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 683:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 684:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 685:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 686:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 687:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 688:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 689:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 690:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 691:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 692:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Check the detach capability in the DFU functional descriptor */ + 693:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (((USBD_DFU_CfgDesc[12U + (9U * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK) != 0U) + 694:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 695:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Perform an Attach-Detach operation on USB bus */ + 696:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_Stop(pdev); + 697:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_Start(pdev); + 698:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 699:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 700:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 701:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Wait for the period of time specified in Detach request */ + 702:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_Delay((uint32_t)req->wValue); + 703:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 704:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 705:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 706:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 707:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_Download + 708:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU DNLOAD request. + 709:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 710:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param req: pointer to the request structure + 711:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval None + 712:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 713:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 714:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 715:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 716:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 717:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Data setup request */ + 718:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (req->wLength > 0U) + 719:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 720:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->dev_state == DFU_STATE_IDLE) || (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE)) + 721:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 722:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Update the global length and block number */ + 723:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = req->wValue; + ARM GAS /tmp/ccyvpZhC.s page 16 + + + 724:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 725:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 726:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Update the state machine */ + 727:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_DNLOAD_SYNC; + 728:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 729:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 730:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Prepare the reception of the buffer over EP0 */ + 731:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hdfu->buffer.d8, hdfu->wlength); + 732:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 733:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Unsupported state */ + 734:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 735:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 736:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked */ + 737:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 738:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 739:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 740:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* 0 Data DNLOAD request */ + 741:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 742:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 743:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* End of DNLOAD operation*/ + 744:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || (hdfu->dev_state == DFU_STATE_IDLE)) + 745:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 746:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->manif_state = DFU_MANIFEST_IN_PROGRESS; + 747:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; + 748:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 749:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 750:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 751:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 752:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 753:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 754:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 755:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked */ + 756:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 757:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 758:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 759:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 760:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 761:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 762:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_Upload + 763:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU UPLOAD request. + 764:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: instance + 765:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param req: pointer to the request structure + 766:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 767:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 768:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) + 769:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 770:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 771:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 772:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *phaddr; + 773:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint32_t addr; + 774:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 775:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Data setup request */ + 776:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (req->wLength > 0U) + 777:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 778:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->dev_state == DFU_STATE_IDLE) || (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) + 779:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 780:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Update the global length and block number */ + ARM GAS /tmp/ccyvpZhC.s page 17 + + + 781:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = req->wValue; + 782:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 783:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 784:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* DFU Get Command */ + 785:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->wblock_num == 0U) + 786:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 787:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Update the state machine */ + 788:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = (hdfu->wlength > 3U) ? DFU_STATE_IDLE : DFU_STATE_UPLOAD_IDLE; + 789:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 790:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 791:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 792:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 793:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 794:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 795:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Store the values of all supported commands */ + 796:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[0] = DFU_CMD_GETCOMMANDS; + 797:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[1] = DFU_CMD_SETADDRESSPOINTER; + 798:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[2] = DFU_CMD_ERASE; + 799:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 800:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Send the status data over EP0 */ + 801:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->buffer.d8[0])), 3U); + 802:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 803:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else if (hdfu->wblock_num > 1U) + 804:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 805:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_UPLOAD_IDLE; + 806:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 807:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 808:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 809:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 810:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 811:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 812:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; + 813:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 814:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Return the physical address where data are stored */ + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** phaddr = DfuInterface->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength); + 816:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 817:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Send the status data over EP0 */ + 818:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, phaddr, hdfu->wlength); + 819:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 820:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else /* unsupported hdfu->wblock_num */ + 821:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 822:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_ERROR_STALLEDPKT; + 823:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 824:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 825:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 826:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 827:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 828:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 829:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked */ + 830:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 831:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 832:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 833:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Unsupported state */ + 834:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 835:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 836:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 837:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + ARM GAS /tmp/ccyvpZhC.s page 18 + + + 838:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 839:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked */ + 840:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, req); + 841:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 842:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 843:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* No Data setup request */ + 844:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 845:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 846:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 847:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 848:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 849:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 850:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 851:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 852:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 853:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 854:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 855:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 856:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_GetStatus + 857:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU GETSTATUS request. + 858:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: instance + 859:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 860:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 861:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_GetStatus(USBD_HandleTypeDef *pdev) + 862:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 863:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 864:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 865:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 866:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** switch (hdfu->dev_state) + 867:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 868:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_STATE_DNLOAD_SYNC: + 869:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->wlength != 0U) + 870:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 871:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_DNLOAD_BUSY; + 872:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 873:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 874:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 875:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 876:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 877:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 878:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->wblock_num == 0U) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE)) + 879:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 880:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DfuInterface->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status); + 881:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 882:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 883:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 884:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** DfuInterface->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status); + 885:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 886:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 887:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else /* (hdfu->wlength==0)*/ + 888:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 889:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_DNLOAD_IDLE; + 890:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 891:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 892:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 893:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 894:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + ARM GAS /tmp/ccyvpZhC.s page 19 + + + 895:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 896:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 897:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 898:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** case DFU_STATE_MANIFEST_SYNC: + 899:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS) + 900:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 901:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST; + 902:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 903:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 1U; /*bwPollTimeout = 1ms*/ + 904:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 905:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 906:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 907:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 908:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 909:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 910:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && + 911:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U)) + 912:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 913:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 914:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 915:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 916:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 917:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 918:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 919:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 920:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 921:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 922:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 923:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** default: + 924:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 925:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 926:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 927:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Send the status data over EP0 */ + 928:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->dev_status[0])), 6U); + 929:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 930:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 931:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 932:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_ClearStatus + 933:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU CLRSTATUS request. + 934:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 935:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval status + 936:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 937:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_ClearStatus(USBD_HandleTypeDef *pdev) + 938:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 142 .loc 1 938 1 is_stmt 1 view -0 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 0 + 145 @ frame_needed = 0, uses_anonymous_args = 0 + 146 @ link register save eliminated. + 939:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 147 .loc 1 939 3 view .LVU23 + 148 .loc 1 939 27 is_stmt 0 view .LVU24 + 149 0000 D0F8BC32 ldr r3, [r0, #700] + 150 .LVL9: + 940:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 941:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (hdfu->dev_state == DFU_STATE_ERROR) + 151 .loc 1 941 3 is_stmt 1 view .LVU25 + ARM GAS /tmp/ccyvpZhC.s page 20 + + + 152 .loc 1 941 11 is_stmt 0 view .LVU26 + 153 0004 03F58052 add r2, r3, #4096 + 154 0008 127E ldrb r2, [r2, #24] @ zero_extendqisi2 + 155 .loc 1 941 6 view .LVU27 + 156 000a 0A2A cmp r2, #10 + 157 000c 0CD0 beq .L12 + 942:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 943:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 944:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; /*bStatus*/ + 945:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 946:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 947:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 948:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + 949:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 950:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 951:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else + 952:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 953:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /*State Error*/ + 954:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_ERROR; + 158 .loc 1 954 5 is_stmt 1 view .LVU28 + 159 .loc 1 954 21 is_stmt 0 view .LVU29 + 160 000e 03F58053 add r3, r3, #4096 + 161 .LVL10: + 162 .loc 1 954 21 view .LVU30 + 163 0012 0A21 movs r1, #10 + 164 0014 1976 strb r1, [r3, #24] + 165 .LVL11: + 955:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_UNKNOWN; /*bStatus*/ + 166 .loc 1 955 5 is_stmt 1 view .LVU31 + 167 .loc 1 955 25 is_stmt 0 view .LVU32 + 168 0016 0E22 movs r2, #14 + 169 0018 1A74 strb r2, [r3, #16] + 956:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 170 .loc 1 956 5 is_stmt 1 view .LVU33 + 171 .loc 1 956 25 is_stmt 0 view .LVU34 + 172 001a 0022 movs r2, #0 + 173 001c 5A74 strb r2, [r3, #17] + 957:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 174 .loc 1 957 5 is_stmt 1 view .LVU35 + 175 .loc 1 957 25 is_stmt 0 view .LVU36 + 176 001e 9A74 strb r2, [r3, #18] + 958:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 177 .loc 1 958 5 is_stmt 1 view .LVU37 + 178 .loc 1 958 25 is_stmt 0 view .LVU38 + 179 0020 DA74 strb r2, [r3, #19] + 959:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + 180 .loc 1 959 5 is_stmt 1 view .LVU39 + 181 .loc 1 959 25 is_stmt 0 view .LVU40 + 182 0022 1975 strb r1, [r3, #20] + 960:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 183 .loc 1 960 5 is_stmt 1 view .LVU41 + 184 .loc 1 960 25 is_stmt 0 view .LVU42 + 185 0024 5A75 strb r2, [r3, #21] + 961:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 962:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 186 .loc 1 962 1 view .LVU43 + 187 0026 7047 bx lr + ARM GAS /tmp/ccyvpZhC.s page 21 + + + 188 .LVL12: + 189 .L12: + 943:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; /*bStatus*/ + 190 .loc 1 943 5 is_stmt 1 view .LVU44 + 943:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; /*bStatus*/ + 191 .loc 1 943 21 is_stmt 0 view .LVU45 + 192 0028 03F58053 add r3, r3, #4096 + 193 .LVL13: + 943:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; /*bStatus*/ + 194 .loc 1 943 21 view .LVU46 + 195 002c 0221 movs r1, #2 + 196 002e 1976 strb r1, [r3, #24] + 197 .LVL14: + 944:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 198 .loc 1 944 5 is_stmt 1 view .LVU47 + 944:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 199 .loc 1 944 25 is_stmt 0 view .LVU48 + 200 0030 0022 movs r2, #0 + 201 0032 1A74 strb r2, [r3, #16] + 945:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 202 .loc 1 945 5 is_stmt 1 view .LVU49 + 945:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 203 .loc 1 945 25 is_stmt 0 view .LVU50 + 204 0034 5A74 strb r2, [r3, #17] + 946:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 205 .loc 1 946 5 is_stmt 1 view .LVU51 + 946:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 206 .loc 1 946 25 is_stmt 0 view .LVU52 + 207 0036 9A74 strb r2, [r3, #18] + 947:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + 208 .loc 1 947 5 is_stmt 1 view .LVU53 + 947:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + 209 .loc 1 947 25 is_stmt 0 view .LVU54 + 210 0038 DA74 strb r2, [r3, #19] + 948:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 211 .loc 1 948 5 is_stmt 1 view .LVU55 + 948:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 212 .loc 1 948 25 is_stmt 0 view .LVU56 + 213 003a 1975 strb r1, [r3, #20] + 949:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 214 .loc 1 949 5 is_stmt 1 view .LVU57 + 949:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 215 .loc 1 949 25 is_stmt 0 view .LVU58 + 216 003c 5A75 strb r2, [r3, #21] + 217 003e 7047 bx lr + 218 .cfi_endproc + 219 .LFE159: + 221 .section .text.DFU_Abort,"ax",%progbits + 222 .align 1 + 223 .syntax unified + 224 .thumb + 225 .thumb_func + 226 .fpu fpv5-d16 + 228 DFU_Abort: + 229 .LVL15: + 230 .LFB161: + 963:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + ARM GAS /tmp/ccyvpZhC.s page 22 + + + 964:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 965:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_GetState + 966:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU GETSTATE request. + 967:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 968:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval None + 969:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 970:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_GetState(USBD_HandleTypeDef *pdev) + 971:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 972:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 973:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 974:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Return the current state of the DFU interface */ + 975:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_CtlSendData(pdev, &hdfu->dev_state, 1U); + 976:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 977:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 978:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 979:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_Abort + 980:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the DFU ABORT request. + 981:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance + 982:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval None + 983:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ + 984:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Abort(USBD_HandleTypeDef *pdev) + 985:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 231 .loc 1 985 1 is_stmt 1 view -0 + 232 .cfi_startproc + 233 @ args = 0, pretend = 0, frame = 0 + 234 @ frame_needed = 0, uses_anonymous_args = 0 + 235 @ link register save eliminated. + 986:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 236 .loc 1 986 3 view .LVU60 + 237 .loc 1 986 27 is_stmt 0 view .LVU61 + 238 0000 D0F8BC32 ldr r3, [r0, #700] + 239 .LVL16: + 987:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 988:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 989:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if ((hdfu->dev_state == DFU_STATE_IDLE) || + 240 .loc 1 989 3 is_stmt 1 view .LVU62 + 241 .loc 1 989 12 is_stmt 0 view .LVU63 + 242 0004 03F58052 add r2, r3, #4096 + 243 0008 117E ldrb r1, [r2, #24] @ zero_extendqisi2 + 990:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + 244 .loc 1 990 50 view .LVU64 + 245 000a 8A1E subs r2, r1, #2 + 246 000c D2B2 uxtb r2, r2 + 989:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + 247 .loc 1 989 6 view .LVU65 + 248 000e 0529 cmp r1, #5 + 249 0010 18BF it ne + 250 0012 012A cmpne r2, #1 + 251 0014 03D9 bls .L14 + 991:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + 252 .loc 1 991 50 view .LVU66 + 253 0016 0629 cmp r1, #6 + 254 0018 01D0 beq .L14 + 992:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + 255 .loc 1 992 52 view .LVU67 + 256 001a 0929 cmp r1, #9 + 257 001c 0CD1 bne .L13 + ARM GAS /tmp/ccyvpZhC.s page 23 + + + 258 .L14: + 993:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) + 994:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 995:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 259 .loc 1 995 5 is_stmt 1 view .LVU68 + 260 .loc 1 995 21 is_stmt 0 view .LVU69 + 261 001e 03F58053 add r3, r3, #4096 + 262 .LVL17: + 263 .loc 1 995 21 view .LVU70 + 264 0022 0221 movs r1, #2 + 265 0024 1976 strb r1, [r3, #24] + 266 .LVL18: + 996:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 267 .loc 1 996 5 is_stmt 1 view .LVU71 + 268 .loc 1 996 25 is_stmt 0 view .LVU72 + 269 0026 0022 movs r2, #0 + 270 0028 1A74 strb r2, [r3, #16] + 997:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 271 .loc 1 997 5 is_stmt 1 view .LVU73 + 272 .loc 1 997 25 is_stmt 0 view .LVU74 + 273 002a 5A74 strb r2, [r3, #17] + 998:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 274 .loc 1 998 5 is_stmt 1 view .LVU75 + 275 .loc 1 998 25 is_stmt 0 view .LVU76 + 276 002c 9A74 strb r2, [r3, #18] + 999:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 277 .loc 1 999 5 is_stmt 1 view .LVU77 + 278 .loc 1 999 25 is_stmt 0 view .LVU78 + 279 002e DA74 strb r2, [r3, #19] +1000:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 280 .loc 1 1000 5 is_stmt 1 view .LVU79 + 281 .loc 1 1000 25 is_stmt 0 view .LVU80 + 282 0030 1975 strb r1, [r3, #20] +1001:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 283 .loc 1 1001 5 is_stmt 1 view .LVU81 + 284 .loc 1 1001 25 is_stmt 0 view .LVU82 + 285 0032 5A75 strb r2, [r3, #21] +1002:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 286 .loc 1 1002 5 is_stmt 1 view .LVU83 + 287 .loc 1 1002 22 is_stmt 0 view .LVU84 + 288 0034 1A60 str r2, [r3] +1003:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 289 .loc 1 1003 5 is_stmt 1 view .LVU85 + 290 .loc 1 1003 19 is_stmt 0 view .LVU86 + 291 0036 5A60 str r2, [r3, #4] + 292 .LVL19: + 293 .L13: +1004:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } +1005:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 294 .loc 1 1005 1 view .LVU87 + 295 0038 7047 bx lr + 296 .cfi_endproc + 297 .LFE161: + 299 .section .text.USBD_DFU_GetUsrStringDesc,"ax",%progbits + 300 .align 1 + 301 .syntax unified + 302 .thumb + ARM GAS /tmp/ccyvpZhC.s page 24 + + + 303 .thumb_func + 304 .fpu fpv5-d16 + 306 USBD_DFU_GetUsrStringDesc: + 307 .LVL20: + 308 .LFB153: + 624:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_StrDesc[255]; + 309 .loc 1 624 1 is_stmt 1 view -0 + 310 .cfi_startproc + 311 @ args = 0, pretend = 0, frame = 0 + 312 @ frame_needed = 0, uses_anonymous_args = 0 + 625:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 313 .loc 1 625 3 view .LVU89 + 626:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 314 .loc 1 626 3 view .LVU90 + 626:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 315 .loc 1 626 26 is_stmt 0 view .LVU91 + 316 0000 D0F8C032 ldr r3, [r0, #704] + 317 .LVL21: + 629:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 318 .loc 1 629 3 is_stmt 1 view .LVU92 + 629:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 319 .loc 1 629 6 is_stmt 0 view .LVU93 + 320 0004 0629 cmp r1, #6 + 321 0006 07D8 bhi .L18 + 624:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static uint8_t USBD_StrDesc[255]; + 322 .loc 1 624 1 view .LVU94 + 323 0008 10B5 push {r4, lr} + 324 .LCFI0: + 325 .cfi_def_cfa_offset 8 + 326 .cfi_offset 4, -8 + 327 .cfi_offset 14, -4 + 631:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return USBD_StrDesc; + 328 .loc 1 631 5 is_stmt 1 view .LVU95 + 329 000a 044C ldr r4, .L23 + 330 000c 2146 mov r1, r4 + 331 .LVL22: + 631:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return USBD_StrDesc; + 332 .loc 1 631 5 is_stmt 0 view .LVU96 + 333 000e 1868 ldr r0, [r3] + 334 .LVL23: + 631:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return USBD_StrDesc; + 335 .loc 1 631 5 view .LVU97 + 336 0010 FFF7FEFF bl USBD_GetString + 337 .LVL24: + 632:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 338 .loc 1 632 5 is_stmt 1 view .LVU98 + 632:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 339 .loc 1 632 12 is_stmt 0 view .LVU99 + 340 0014 2046 mov r0, r4 + 639:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif + 341 .loc 1 639 1 view .LVU100 + 342 0016 10BD pop {r4, pc} + 343 .LVL25: + 344 .L18: + 345 .LCFI1: + 346 .cfi_def_cfa_offset 0 + 347 .cfi_restore 4 + ARM GAS /tmp/ccyvpZhC.s page 25 + + + 348 .cfi_restore 14 + 637:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 349 .loc 1 637 12 view .LVU101 + 350 0018 0020 movs r0, #0 + 351 .LVL26: + 639:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** #endif + 352 .loc 1 639 1 view .LVU102 + 353 001a 7047 bx lr + 354 .L24: + 355 .align 2 + 356 .L23: + 357 001c 00000000 .word .LANCHOR2 + 358 .cfi_endproc + 359 .LFE153: + 361 .section .text.DFU_Leave,"ax",%progbits + 362 .align 1 + 363 .syntax unified + 364 .thumb + 365 .thumb_func + 366 .fpu fpv5-d16 + 368 DFU_Leave: + 369 .LVL27: + 370 .LFB162: +1006:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1007:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** +1008:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @brief DFU_Leave +1009:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode +1010:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * and resets device to jump to user loaded code). +1011:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @param pdev: device instance +1012:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** * @retval None +1013:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** */ +1014:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** static void DFU_Leave(USBD_HandleTypeDef *pdev) +1015:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 371 .loc 1 1015 1 is_stmt 1 view -0 + 372 .cfi_startproc + 373 @ args = 0, pretend = 0, frame = 0 + 374 @ frame_needed = 0, uses_anonymous_args = 0 + 375 .loc 1 1015 1 is_stmt 0 view .LVU104 + 376 0000 08B5 push {r3, lr} + 377 .LCFI2: + 378 .cfi_def_cfa_offset 8 + 379 .cfi_offset 3, -8 + 380 .cfi_offset 14, -4 +1016:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 381 .loc 1 1016 3 is_stmt 1 view .LVU105 + 382 .loc 1 1016 27 is_stmt 0 view .LVU106 + 383 0002 D0F8BC32 ldr r3, [r0, #700] + 384 .LVL28: +1017:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1018:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->manif_state = DFU_MANIFEST_COMPLETE; + 385 .loc 1 1018 3 is_stmt 1 view .LVU107 + 386 .loc 1 1018 21 is_stmt 0 view .LVU108 + 387 0006 03F58052 add r2, r3, #4096 + 388 000a 0021 movs r1, #0 + 389 000c 5176 strb r1, [r2, #25] +1019:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1020:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U) + ARM GAS /tmp/ccyvpZhC.s page 26 + + + 390 .loc 1 1020 3 is_stmt 1 view .LVU109 + 391 .loc 1 1020 25 is_stmt 0 view .LVU110 + 392 000e 134A ldr r2, .L30 + 393 0010 127D ldrb r2, [r2, #20] @ zero_extendqisi2 + 394 .loc 1 1020 6 view .LVU111 + 395 0012 12F0040F tst r2, #4 + 396 0016 09D0 beq .L26 +1021:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { +1022:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; + 397 .loc 1 1022 5 is_stmt 1 view .LVU112 + 398 .loc 1 1022 21 is_stmt 0 view .LVU113 + 399 0018 03F58053 add r3, r3, #4096 + 400 .LVL29: + 401 .loc 1 1022 21 view .LVU114 + 402 001c 0621 movs r1, #6 + 403 001e 1976 strb r1, [r3, #24] +1023:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1024:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 404 .loc 1 1024 5 is_stmt 1 view .LVU115 + 405 .loc 1 1024 25 is_stmt 0 view .LVU116 + 406 0020 0022 movs r2, #0 + 407 0022 5A74 strb r2, [r3, #17] +1025:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 408 .loc 1 1025 5 is_stmt 1 view .LVU117 + 409 .loc 1 1025 25 is_stmt 0 view .LVU118 + 410 0024 9A74 strb r2, [r3, #18] +1026:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 411 .loc 1 1026 5 is_stmt 1 view .LVU119 + 412 .loc 1 1026 25 is_stmt 0 view .LVU120 + 413 0026 DA74 strb r2, [r3, #19] +1027:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 414 .loc 1 1027 5 is_stmt 1 view .LVU121 + 415 .loc 1 1027 25 is_stmt 0 view .LVU122 + 416 0028 1975 strb r1, [r3, #20] +1028:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return; + 417 .loc 1 1028 5 is_stmt 1 view .LVU123 +1029:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } +1030:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** else +1031:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { +1032:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST_WAIT_RESET; +1033:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1034:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; +1035:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; +1036:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; +1037:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; +1038:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1039:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Disconnect the USB device */ +1040:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_Stop(pdev); +1041:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1042:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Generate system reset to allow jumping to the user code */ +1043:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** NVIC_SystemReset(); +1044:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** +1045:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* The next instructions will not be reached (system reset) */ +1046:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } +1047:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 418 .loc 1 1047 1 is_stmt 0 view .LVU124 + 419 002a 08BD pop {r3, pc} + ARM GAS /tmp/ccyvpZhC.s page 27 + + + 420 .LVL30: + 421 .L26: +1032:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 422 .loc 1 1032 5 is_stmt 1 view .LVU125 +1032:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 423 .loc 1 1032 21 is_stmt 0 view .LVU126 + 424 002c 03F58053 add r3, r3, #4096 + 425 .LVL31: +1032:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 426 .loc 1 1032 21 view .LVU127 + 427 0030 0821 movs r1, #8 + 428 0032 1976 strb r1, [r3, #24] +1034:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 429 .loc 1 1034 5 is_stmt 1 view .LVU128 +1034:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 430 .loc 1 1034 25 is_stmt 0 view .LVU129 + 431 0034 0022 movs r2, #0 + 432 0036 5A74 strb r2, [r3, #17] +1035:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 433 .loc 1 1035 5 is_stmt 1 view .LVU130 +1035:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 434 .loc 1 1035 25 is_stmt 0 view .LVU131 + 435 0038 9A74 strb r2, [r3, #18] +1036:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 436 .loc 1 1036 5 is_stmt 1 view .LVU132 +1036:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 437 .loc 1 1036 25 is_stmt 0 view .LVU133 + 438 003a DA74 strb r2, [r3, #19] +1037:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 439 .loc 1 1037 5 is_stmt 1 view .LVU134 +1037:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 440 .loc 1 1037 25 is_stmt 0 view .LVU135 + 441 003c 1975 strb r1, [r3, #20] +1040:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 442 .loc 1 1040 5 is_stmt 1 view .LVU136 +1040:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 443 .loc 1 1040 11 is_stmt 0 view .LVU137 + 444 003e FFF7FEFF bl USBD_Stop + 445 .LVL32: +1043:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 446 .loc 1 1043 5 is_stmt 1 view .LVU138 + 447 .LBB12: + 448 .LBI12: + 449 .file 2 "Drivers/CMSIS/Include/core_cm7.h" + 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h + 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 + 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 + 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm7.h **** /* + 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm7.h **** * + 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm7.h **** * + 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. + ARM GAS /tmp/ccyvpZhC.s page 28 + + + 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm7.h **** * + 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm7.h **** * + 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm7.h **** */ + 24:Drivers/CMSIS/Include/core_cm7.h **** + 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm7.h **** #endif + 30:Drivers/CMSIS/Include/core_cm7.h **** + 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm7.h **** + 34:Drivers/CMSIS/Include/core_cm7.h **** #include + 35:Drivers/CMSIS/Include/core_cm7.h **** + 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm7.h **** #endif + 39:Drivers/CMSIS/Include/core_cm7.h **** + 40:Drivers/CMSIS/Include/core_cm7.h **** /** + 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: + 43:Drivers/CMSIS/Include/core_cm7.h **** + 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm7.h **** + 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm7.h **** + 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm7.h **** */ + 53:Drivers/CMSIS/Include/core_cm7.h **** + 54:Drivers/CMSIS/Include/core_cm7.h **** + 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm7.h **** /** + 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 + 60:Drivers/CMSIS/Include/core_cm7.h **** @{ + 61:Drivers/CMSIS/Include/core_cm7.h **** */ + 62:Drivers/CMSIS/Include/core_cm7.h **** + 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm7.h **** + 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ + 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 + 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 + 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS + 70:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccyvpZhC.s page 29 + + + 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm7.h **** + 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun + 75:Drivers/CMSIS/Include/core_cm7.h **** */ + 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) + 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP + 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 80:Drivers/CMSIS/Include/core_cm7.h **** #else + 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 83:Drivers/CMSIS/Include/core_cm7.h **** #endif + 84:Drivers/CMSIS/Include/core_cm7.h **** #else + 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 86:Drivers/CMSIS/Include/core_cm7.h **** #endif + 87:Drivers/CMSIS/Include/core_cm7.h **** + 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP + 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 92:Drivers/CMSIS/Include/core_cm7.h **** #else + 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN + 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 95:Drivers/CMSIS/Include/core_cm7.h **** #endif + 96:Drivers/CMSIS/Include/core_cm7.h **** #else + 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 98:Drivers/CMSIS/Include/core_cm7.h **** #endif + 99:Drivers/CMSIS/Include/core_cm7.h **** + 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) + 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 104:Drivers/CMSIS/Include/core_cm7.h **** #else + 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 107:Drivers/CMSIS/Include/core_cm7.h **** #endif + 108:Drivers/CMSIS/Include/core_cm7.h **** #else + 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 110:Drivers/CMSIS/Include/core_cm7.h **** #endif + 111:Drivers/CMSIS/Include/core_cm7.h **** + 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) + 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ + 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 116:Drivers/CMSIS/Include/core_cm7.h **** #else + 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 119:Drivers/CMSIS/Include/core_cm7.h **** #endif + 120:Drivers/CMSIS/Include/core_cm7.h **** #else + 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 122:Drivers/CMSIS/Include/core_cm7.h **** #endif + 123:Drivers/CMSIS/Include/core_cm7.h **** + 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) + 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ + 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + ARM GAS /tmp/ccyvpZhC.s page 30 + + + 128:Drivers/CMSIS/Include/core_cm7.h **** #else + 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 131:Drivers/CMSIS/Include/core_cm7.h **** #endif + 132:Drivers/CMSIS/Include/core_cm7.h **** #else + 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 134:Drivers/CMSIS/Include/core_cm7.h **** #endif + 135:Drivers/CMSIS/Include/core_cm7.h **** + 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) + 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ + 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 140:Drivers/CMSIS/Include/core_cm7.h **** #else + 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 143:Drivers/CMSIS/Include/core_cm7.h **** #endif + 144:Drivers/CMSIS/Include/core_cm7.h **** #else + 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 146:Drivers/CMSIS/Include/core_cm7.h **** #endif + 147:Drivers/CMSIS/Include/core_cm7.h **** + 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) + 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) + 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 152:Drivers/CMSIS/Include/core_cm7.h **** #else + 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 155:Drivers/CMSIS/Include/core_cm7.h **** #endif + 156:Drivers/CMSIS/Include/core_cm7.h **** #else + 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 158:Drivers/CMSIS/Include/core_cm7.h **** #endif + 159:Drivers/CMSIS/Include/core_cm7.h **** + 160:Drivers/CMSIS/Include/core_cm7.h **** #endif + 161:Drivers/CMSIS/Include/core_cm7.h **** + 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 163:Drivers/CMSIS/Include/core_cm7.h **** + 164:Drivers/CMSIS/Include/core_cm7.h **** + 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 166:Drivers/CMSIS/Include/core_cm7.h **** } + 167:Drivers/CMSIS/Include/core_cm7.h **** #endif + 168:Drivers/CMSIS/Include/core_cm7.h **** + 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ + 170:Drivers/CMSIS/Include/core_cm7.h **** + 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC + 172:Drivers/CMSIS/Include/core_cm7.h **** + 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT + 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm7.h **** + 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 178:Drivers/CMSIS/Include/core_cm7.h **** #endif + 179:Drivers/CMSIS/Include/core_cm7.h **** + 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ + 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES + 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV + 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U + 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" + ARM GAS /tmp/ccyvpZhC.s page 31 + + + 185:Drivers/CMSIS/Include/core_cm7.h **** #endif + 186:Drivers/CMSIS/Include/core_cm7.h **** + 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT + 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U + 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" + 190:Drivers/CMSIS/Include/core_cm7.h **** #endif + 191:Drivers/CMSIS/Include/core_cm7.h **** + 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT + 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U + 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 195:Drivers/CMSIS/Include/core_cm7.h **** #endif + 196:Drivers/CMSIS/Include/core_cm7.h **** + 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT + 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U + 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" + 200:Drivers/CMSIS/Include/core_cm7.h **** #endif + 201:Drivers/CMSIS/Include/core_cm7.h **** + 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT + 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U + 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" + 205:Drivers/CMSIS/Include/core_cm7.h **** #endif + 206:Drivers/CMSIS/Include/core_cm7.h **** + 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT + 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U + 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" + 210:Drivers/CMSIS/Include/core_cm7.h **** #endif + 211:Drivers/CMSIS/Include/core_cm7.h **** + 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS + 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U + 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 215:Drivers/CMSIS/Include/core_cm7.h **** #endif + 216:Drivers/CMSIS/Include/core_cm7.h **** + 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig + 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U + 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 220:Drivers/CMSIS/Include/core_cm7.h **** #endif + 221:Drivers/CMSIS/Include/core_cm7.h **** #endif + 222:Drivers/CMSIS/Include/core_cm7.h **** + 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ + 224:Drivers/CMSIS/Include/core_cm7.h **** /** + 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 226:Drivers/CMSIS/Include/core_cm7.h **** + 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used + 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. + 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. + 230:Drivers/CMSIS/Include/core_cm7.h **** */ + 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 233:Drivers/CMSIS/Include/core_cm7.h **** #else + 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 235:Drivers/CMSIS/Include/core_cm7.h **** #endif + 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 238:Drivers/CMSIS/Include/core_cm7.h **** + 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ + 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + ARM GAS /tmp/ccyvpZhC.s page 32 + + + 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 243:Drivers/CMSIS/Include/core_cm7.h **** + 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ + 245:Drivers/CMSIS/Include/core_cm7.h **** + 246:Drivers/CMSIS/Include/core_cm7.h **** + 247:Drivers/CMSIS/Include/core_cm7.h **** + 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction + 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: + 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register + 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register + 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register + 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register + 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register + 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register + 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register + 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 259:Drivers/CMSIS/Include/core_cm7.h **** /** + 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 262:Drivers/CMSIS/Include/core_cm7.h **** */ + 263:Drivers/CMSIS/Include/core_cm7.h **** + 264:Drivers/CMSIS/Include/core_cm7.h **** /** + 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers + 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. + 268:Drivers/CMSIS/Include/core_cm7.h **** @{ + 269:Drivers/CMSIS/Include/core_cm7.h **** */ + 270:Drivers/CMSIS/Include/core_cm7.h **** + 271:Drivers/CMSIS/Include/core_cm7.h **** /** + 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). + 273:Drivers/CMSIS/Include/core_cm7.h **** */ + 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 275:Drivers/CMSIS/Include/core_cm7.h **** { + 276:Drivers/CMSIS/Include/core_cm7.h **** struct + 277:Drivers/CMSIS/Include/core_cm7.h **** { + 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; + 289:Drivers/CMSIS/Include/core_cm7.h **** + 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ + 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR + 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 293:Drivers/CMSIS/Include/core_cm7.h **** + 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR + 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 296:Drivers/CMSIS/Include/core_cm7.h **** + 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR + 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + ARM GAS /tmp/ccyvpZhC.s page 33 + + + 299:Drivers/CMSIS/Include/core_cm7.h **** + 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR + 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 302:Drivers/CMSIS/Include/core_cm7.h **** + 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR + 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR + 305:Drivers/CMSIS/Include/core_cm7.h **** + 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR + 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR + 308:Drivers/CMSIS/Include/core_cm7.h **** + 309:Drivers/CMSIS/Include/core_cm7.h **** + 310:Drivers/CMSIS/Include/core_cm7.h **** /** + 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 312:Drivers/CMSIS/Include/core_cm7.h **** */ + 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 314:Drivers/CMSIS/Include/core_cm7.h **** { + 315:Drivers/CMSIS/Include/core_cm7.h **** struct + 316:Drivers/CMSIS/Include/core_cm7.h **** { + 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; + 322:Drivers/CMSIS/Include/core_cm7.h **** + 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ + 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 326:Drivers/CMSIS/Include/core_cm7.h **** + 327:Drivers/CMSIS/Include/core_cm7.h **** + 328:Drivers/CMSIS/Include/core_cm7.h **** /** + 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 330:Drivers/CMSIS/Include/core_cm7.h **** */ + 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 332:Drivers/CMSIS/Include/core_cm7.h **** { + 333:Drivers/CMSIS/Include/core_cm7.h **** struct + 334:Drivers/CMSIS/Include/core_cm7.h **** { + 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ + 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; + 350:Drivers/CMSIS/Include/core_cm7.h **** + 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ + 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR + 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 354:Drivers/CMSIS/Include/core_cm7.h **** + 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR + ARM GAS /tmp/ccyvpZhC.s page 34 + + + 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 357:Drivers/CMSIS/Include/core_cm7.h **** + 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR + 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 360:Drivers/CMSIS/Include/core_cm7.h **** + 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR + 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 363:Drivers/CMSIS/Include/core_cm7.h **** + 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR + 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR + 366:Drivers/CMSIS/Include/core_cm7.h **** + 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR + 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR + 369:Drivers/CMSIS/Include/core_cm7.h **** + 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR + 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 372:Drivers/CMSIS/Include/core_cm7.h **** + 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR + 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR + 375:Drivers/CMSIS/Include/core_cm7.h **** + 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR + 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR + 378:Drivers/CMSIS/Include/core_cm7.h **** + 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 381:Drivers/CMSIS/Include/core_cm7.h **** + 382:Drivers/CMSIS/Include/core_cm7.h **** + 383:Drivers/CMSIS/Include/core_cm7.h **** /** + 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). + 385:Drivers/CMSIS/Include/core_cm7.h **** */ + 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 387:Drivers/CMSIS/Include/core_cm7.h **** { + 388:Drivers/CMSIS/Include/core_cm7.h **** struct + 389:Drivers/CMSIS/Include/core_cm7.h **** { + 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; + 397:Drivers/CMSIS/Include/core_cm7.h **** + 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ + 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT + 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT + 401:Drivers/CMSIS/Include/core_cm7.h **** + 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 404:Drivers/CMSIS/Include/core_cm7.h **** + 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 407:Drivers/CMSIS/Include/core_cm7.h **** + 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ + 409:Drivers/CMSIS/Include/core_cm7.h **** + 410:Drivers/CMSIS/Include/core_cm7.h **** + 411:Drivers/CMSIS/Include/core_cm7.h **** /** + 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + ARM GAS /tmp/ccyvpZhC.s page 35 + + + 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers + 415:Drivers/CMSIS/Include/core_cm7.h **** @{ + 416:Drivers/CMSIS/Include/core_cm7.h **** */ + 417:Drivers/CMSIS/Include/core_cm7.h **** + 418:Drivers/CMSIS/Include/core_cm7.h **** /** + 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 420:Drivers/CMSIS/Include/core_cm7.h **** */ + 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 422:Drivers/CMSIS/Include/core_cm7.h **** { + 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; + 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; + 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; + 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; + 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; + 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi + 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; + 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis + 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; + 437:Drivers/CMSIS/Include/core_cm7.h **** + 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ + 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I + 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I + 441:Drivers/CMSIS/Include/core_cm7.h **** + 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ + 443:Drivers/CMSIS/Include/core_cm7.h **** + 444:Drivers/CMSIS/Include/core_cm7.h **** + 445:Drivers/CMSIS/Include/core_cm7.h **** /** + 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers + 449:Drivers/CMSIS/Include/core_cm7.h **** @{ + 450:Drivers/CMSIS/Include/core_cm7.h **** */ + 451:Drivers/CMSIS/Include/core_cm7.h **** + 452:Drivers/CMSIS/Include/core_cm7.h **** /** + 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). + 454:Drivers/CMSIS/Include/core_cm7.h **** */ + 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 456:Drivers/CMSIS/Include/core_cm7.h **** { + 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe + 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist + 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register + 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + ARM GAS /tmp/ccyvpZhC.s page 36 + + + 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register + 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis + 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis + 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; + 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg + 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; + 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 + 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 + 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 + 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; + 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; + 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU + 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC + 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by + 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by + 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; + 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo + 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont + 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; + 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis + 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; + 508:Drivers/CMSIS/Include/core_cm7.h **** + 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ + 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 512:Drivers/CMSIS/Include/core_cm7.h **** + 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 515:Drivers/CMSIS/Include/core_cm7.h **** + 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 518:Drivers/CMSIS/Include/core_cm7.h **** + 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 521:Drivers/CMSIS/Include/core_cm7.h **** + 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 524:Drivers/CMSIS/Include/core_cm7.h **** + 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ + 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + ARM GAS /tmp/ccyvpZhC.s page 37 + + + 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 528:Drivers/CMSIS/Include/core_cm7.h **** + 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 531:Drivers/CMSIS/Include/core_cm7.h **** + 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 534:Drivers/CMSIS/Include/core_cm7.h **** + 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 537:Drivers/CMSIS/Include/core_cm7.h **** + 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 540:Drivers/CMSIS/Include/core_cm7.h **** + 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 543:Drivers/CMSIS/Include/core_cm7.h **** + 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 546:Drivers/CMSIS/Include/core_cm7.h **** + 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 549:Drivers/CMSIS/Include/core_cm7.h **** + 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB + 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB + 552:Drivers/CMSIS/Include/core_cm7.h **** + 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 555:Drivers/CMSIS/Include/core_cm7.h **** + 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ + 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB + 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 559:Drivers/CMSIS/Include/core_cm7.h **** + 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 563:Drivers/CMSIS/Include/core_cm7.h **** + 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 566:Drivers/CMSIS/Include/core_cm7.h **** + 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 569:Drivers/CMSIS/Include/core_cm7.h **** + 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB + 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB + 572:Drivers/CMSIS/Include/core_cm7.h **** + 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 575:Drivers/CMSIS/Include/core_cm7.h **** + 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 578:Drivers/CMSIS/Include/core_cm7.h **** + 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB + 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB + 581:Drivers/CMSIS/Include/core_cm7.h **** + 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ + 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + ARM GAS /tmp/ccyvpZhC.s page 38 + + + 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 585:Drivers/CMSIS/Include/core_cm7.h **** + 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 588:Drivers/CMSIS/Include/core_cm7.h **** + 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 591:Drivers/CMSIS/Include/core_cm7.h **** + 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ + 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB + 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB + 595:Drivers/CMSIS/Include/core_cm7.h **** + 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB + 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB + 598:Drivers/CMSIS/Include/core_cm7.h **** + 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB + 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB + 601:Drivers/CMSIS/Include/core_cm7.h **** + 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 604:Drivers/CMSIS/Include/core_cm7.h **** + 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB + 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB + 607:Drivers/CMSIS/Include/core_cm7.h **** + 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB + 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB + 610:Drivers/CMSIS/Include/core_cm7.h **** + 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 613:Drivers/CMSIS/Include/core_cm7.h **** + 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB + 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB + 616:Drivers/CMSIS/Include/core_cm7.h **** + 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB + 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB + 619:Drivers/CMSIS/Include/core_cm7.h **** + 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ + 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB + 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB + 623:Drivers/CMSIS/Include/core_cm7.h **** + 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB + 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB + 626:Drivers/CMSIS/Include/core_cm7.h **** + 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB + 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB + 629:Drivers/CMSIS/Include/core_cm7.h **** + 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 632:Drivers/CMSIS/Include/core_cm7.h **** + 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB + 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB + 635:Drivers/CMSIS/Include/core_cm7.h **** + 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB + 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB + 638:Drivers/CMSIS/Include/core_cm7.h **** + 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB + 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB + ARM GAS /tmp/ccyvpZhC.s page 39 + + + 641:Drivers/CMSIS/Include/core_cm7.h **** + 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB + 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB + 644:Drivers/CMSIS/Include/core_cm7.h **** + 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB + 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB + 647:Drivers/CMSIS/Include/core_cm7.h **** + 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB + 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB + 650:Drivers/CMSIS/Include/core_cm7.h **** + 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB + 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB + 653:Drivers/CMSIS/Include/core_cm7.h **** + 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB + 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB + 656:Drivers/CMSIS/Include/core_cm7.h **** + 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB + 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB + 659:Drivers/CMSIS/Include/core_cm7.h **** + 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB + 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB + 662:Drivers/CMSIS/Include/core_cm7.h **** + 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ + 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB + 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB + 666:Drivers/CMSIS/Include/core_cm7.h **** + 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB + 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB + 669:Drivers/CMSIS/Include/core_cm7.h **** + 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB + 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB + 672:Drivers/CMSIS/Include/core_cm7.h **** + 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ + 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB + 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB + 676:Drivers/CMSIS/Include/core_cm7.h **** + 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB + 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB + 679:Drivers/CMSIS/Include/core_cm7.h **** + 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB + 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB + 682:Drivers/CMSIS/Include/core_cm7.h **** + 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB + 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB + 685:Drivers/CMSIS/Include/core_cm7.h **** + 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB + 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB + 688:Drivers/CMSIS/Include/core_cm7.h **** + 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB + 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB + 691:Drivers/CMSIS/Include/core_cm7.h **** + 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ + 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB + 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB + 695:Drivers/CMSIS/Include/core_cm7.h **** + 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB + 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB + ARM GAS /tmp/ccyvpZhC.s page 40 + + + 698:Drivers/CMSIS/Include/core_cm7.h **** + 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB + 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB + 701:Drivers/CMSIS/Include/core_cm7.h **** + 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB + 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB + 704:Drivers/CMSIS/Include/core_cm7.h **** + 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB + 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB + 707:Drivers/CMSIS/Include/core_cm7.h **** + 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB + 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB + 710:Drivers/CMSIS/Include/core_cm7.h **** + 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB + 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB + 713:Drivers/CMSIS/Include/core_cm7.h **** + 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ + 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB + 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB + 717:Drivers/CMSIS/Include/core_cm7.h **** + 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB + 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB + 720:Drivers/CMSIS/Include/core_cm7.h **** + 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB + 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB + 723:Drivers/CMSIS/Include/core_cm7.h **** + 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB + 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB + 726:Drivers/CMSIS/Include/core_cm7.h **** + 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB + 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB + 729:Drivers/CMSIS/Include/core_cm7.h **** + 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB + 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB + 732:Drivers/CMSIS/Include/core_cm7.h **** + 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ + 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB + 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB + 736:Drivers/CMSIS/Include/core_cm7.h **** + 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB + 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB + 739:Drivers/CMSIS/Include/core_cm7.h **** + 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB + 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB + 742:Drivers/CMSIS/Include/core_cm7.h **** + 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ + 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB + 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB + 746:Drivers/CMSIS/Include/core_cm7.h **** + 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB + 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB + 749:Drivers/CMSIS/Include/core_cm7.h **** + 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB + 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB + 752:Drivers/CMSIS/Include/core_cm7.h **** + 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB + 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB + ARM GAS /tmp/ccyvpZhC.s page 41 + + + 755:Drivers/CMSIS/Include/core_cm7.h **** + 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB + 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB + 758:Drivers/CMSIS/Include/core_cm7.h **** + 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ + 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB + 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB + 762:Drivers/CMSIS/Include/core_cm7.h **** + 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB + 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB + 765:Drivers/CMSIS/Include/core_cm7.h **** + 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ + 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB + 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB + 769:Drivers/CMSIS/Include/core_cm7.h **** + 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB + 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB + 772:Drivers/CMSIS/Include/core_cm7.h **** + 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB + 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB + 775:Drivers/CMSIS/Include/core_cm7.h **** + 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB + 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB + 778:Drivers/CMSIS/Include/core_cm7.h **** + 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB + 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB + 781:Drivers/CMSIS/Include/core_cm7.h **** + 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ + 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB + 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB + 785:Drivers/CMSIS/Include/core_cm7.h **** + 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB + 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB + 788:Drivers/CMSIS/Include/core_cm7.h **** + 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB + 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB + 791:Drivers/CMSIS/Include/core_cm7.h **** + 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB + 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB + 794:Drivers/CMSIS/Include/core_cm7.h **** + 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB + 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB + 797:Drivers/CMSIS/Include/core_cm7.h **** + 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB + 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB + 800:Drivers/CMSIS/Include/core_cm7.h **** + 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB + 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB + 803:Drivers/CMSIS/Include/core_cm7.h **** + 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ + 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB + 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB + 807:Drivers/CMSIS/Include/core_cm7.h **** + 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB + 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB + 810:Drivers/CMSIS/Include/core_cm7.h **** + 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ + ARM GAS /tmp/ccyvpZhC.s page 42 + + + 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB + 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB + 814:Drivers/CMSIS/Include/core_cm7.h **** + 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ + 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB + 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB + 818:Drivers/CMSIS/Include/core_cm7.h **** + 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB + 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB + 821:Drivers/CMSIS/Include/core_cm7.h **** + 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ + 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB + 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB + 825:Drivers/CMSIS/Include/core_cm7.h **** + 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB + 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB + 828:Drivers/CMSIS/Include/core_cm7.h **** + 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ + 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB + 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB + 832:Drivers/CMSIS/Include/core_cm7.h **** + 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB + 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB + 835:Drivers/CMSIS/Include/core_cm7.h **** + 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ + 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB + 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB + 839:Drivers/CMSIS/Include/core_cm7.h **** + 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB + 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB + 842:Drivers/CMSIS/Include/core_cm7.h **** + 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB + 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB + 845:Drivers/CMSIS/Include/core_cm7.h **** + 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB + 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB + 848:Drivers/CMSIS/Include/core_cm7.h **** + 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ + 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB + 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB + 852:Drivers/CMSIS/Include/core_cm7.h **** + 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB + 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB + 855:Drivers/CMSIS/Include/core_cm7.h **** + 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB + 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB + 858:Drivers/CMSIS/Include/core_cm7.h **** + 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB + 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB + 861:Drivers/CMSIS/Include/core_cm7.h **** + 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ + 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB + 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB + 865:Drivers/CMSIS/Include/core_cm7.h **** + 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB + 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB + 868:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccyvpZhC.s page 43 + + + 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ + 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB + 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB + 872:Drivers/CMSIS/Include/core_cm7.h **** + 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB + 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB + 875:Drivers/CMSIS/Include/core_cm7.h **** + 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB + 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB + 878:Drivers/CMSIS/Include/core_cm7.h **** + 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ + 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB + 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB + 882:Drivers/CMSIS/Include/core_cm7.h **** + 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB + 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB + 885:Drivers/CMSIS/Include/core_cm7.h **** + 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB + 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB + 888:Drivers/CMSIS/Include/core_cm7.h **** + 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ + 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB + 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB + 892:Drivers/CMSIS/Include/core_cm7.h **** + 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB + 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB + 895:Drivers/CMSIS/Include/core_cm7.h **** + 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB + 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB + 898:Drivers/CMSIS/Include/core_cm7.h **** + 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB + 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB + 901:Drivers/CMSIS/Include/core_cm7.h **** + 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB + 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB + 904:Drivers/CMSIS/Include/core_cm7.h **** + 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB + 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB + 907:Drivers/CMSIS/Include/core_cm7.h **** + 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ + 909:Drivers/CMSIS/Include/core_cm7.h **** + 910:Drivers/CMSIS/Include/core_cm7.h **** + 911:Drivers/CMSIS/Include/core_cm7.h **** /** + 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB + 915:Drivers/CMSIS/Include/core_cm7.h **** @{ + 916:Drivers/CMSIS/Include/core_cm7.h **** */ + 917:Drivers/CMSIS/Include/core_cm7.h **** + 918:Drivers/CMSIS/Include/core_cm7.h **** /** + 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. + 920:Drivers/CMSIS/Include/core_cm7.h **** */ + 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 922:Drivers/CMSIS/Include/core_cm7.h **** { + 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist + 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + ARM GAS /tmp/ccyvpZhC.s page 44 + + + 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; + 927:Drivers/CMSIS/Include/core_cm7.h **** + 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ + 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I + 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I + 931:Drivers/CMSIS/Include/core_cm7.h **** + 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ + 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: + 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: + 935:Drivers/CMSIS/Include/core_cm7.h **** + 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: + 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: + 938:Drivers/CMSIS/Include/core_cm7.h **** + 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: + 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: + 941:Drivers/CMSIS/Include/core_cm7.h **** + 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: + 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: + 944:Drivers/CMSIS/Include/core_cm7.h **** + 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: + 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: + 947:Drivers/CMSIS/Include/core_cm7.h **** + 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ + 949:Drivers/CMSIS/Include/core_cm7.h **** + 950:Drivers/CMSIS/Include/core_cm7.h **** + 951:Drivers/CMSIS/Include/core_cm7.h **** /** + 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. + 955:Drivers/CMSIS/Include/core_cm7.h **** @{ + 956:Drivers/CMSIS/Include/core_cm7.h **** */ + 957:Drivers/CMSIS/Include/core_cm7.h **** + 958:Drivers/CMSIS/Include/core_cm7.h **** /** + 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). + 960:Drivers/CMSIS/Include/core_cm7.h **** */ + 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 962:Drivers/CMSIS/Include/core_cm7.h **** { + 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; + 968:Drivers/CMSIS/Include/core_cm7.h **** + 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ + 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 972:Drivers/CMSIS/Include/core_cm7.h **** + 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 975:Drivers/CMSIS/Include/core_cm7.h **** + 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 978:Drivers/CMSIS/Include/core_cm7.h **** + 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 981:Drivers/CMSIS/Include/core_cm7.h **** + 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ + ARM GAS /tmp/ccyvpZhC.s page 45 + + + 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 985:Drivers/CMSIS/Include/core_cm7.h **** + 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ + 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 989:Drivers/CMSIS/Include/core_cm7.h **** + 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ + 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 993:Drivers/CMSIS/Include/core_cm7.h **** + 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 996:Drivers/CMSIS/Include/core_cm7.h **** + 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 999:Drivers/CMSIS/Include/core_cm7.h **** +1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ +1001:Drivers/CMSIS/Include/core_cm7.h **** +1002:Drivers/CMSIS/Include/core_cm7.h **** +1003:Drivers/CMSIS/Include/core_cm7.h **** /** +1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) +1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) +1007:Drivers/CMSIS/Include/core_cm7.h **** @{ +1008:Drivers/CMSIS/Include/core_cm7.h **** */ +1009:Drivers/CMSIS/Include/core_cm7.h **** +1010:Drivers/CMSIS/Include/core_cm7.h **** /** +1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). +1012:Drivers/CMSIS/Include/core_cm7.h **** */ +1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1014:Drivers/CMSIS/Include/core_cm7.h **** { +1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union +1016:Drivers/CMSIS/Include/core_cm7.h **** { +1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ +1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ +1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ +1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ +1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; +1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ +1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; +1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ +1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; +1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; +1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * +1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ +1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg +1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; +1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ +1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ +1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; +1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re +1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re +1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re +1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re +1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re + ARM GAS /tmp/ccyvpZhC.s page 46 + + +1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re +1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re +1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re +1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re +1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re +1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re +1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re +1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; +1048:Drivers/CMSIS/Include/core_cm7.h **** +1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ +1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM +1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM +1052:Drivers/CMSIS/Include/core_cm7.h **** +1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ +1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM +1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM +1056:Drivers/CMSIS/Include/core_cm7.h **** +1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM +1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM +1059:Drivers/CMSIS/Include/core_cm7.h **** +1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM +1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM +1062:Drivers/CMSIS/Include/core_cm7.h **** +1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM +1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM +1065:Drivers/CMSIS/Include/core_cm7.h **** +1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM +1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM +1068:Drivers/CMSIS/Include/core_cm7.h **** +1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM +1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM +1071:Drivers/CMSIS/Include/core_cm7.h **** +1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM +1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM +1074:Drivers/CMSIS/Include/core_cm7.h **** +1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM +1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM +1077:Drivers/CMSIS/Include/core_cm7.h **** +1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM +1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM +1080:Drivers/CMSIS/Include/core_cm7.h **** +1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ +1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM +1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM +1084:Drivers/CMSIS/Include/core_cm7.h **** +1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ +1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM +1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM +1088:Drivers/CMSIS/Include/core_cm7.h **** +1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ +1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM +1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM +1092:Drivers/CMSIS/Include/core_cm7.h **** +1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ +1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM +1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM +1096:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccyvpZhC.s page 47 + + +1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM +1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM +1099:Drivers/CMSIS/Include/core_cm7.h **** +1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM +1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM +1102:Drivers/CMSIS/Include/core_cm7.h **** +1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ +1104:Drivers/CMSIS/Include/core_cm7.h **** +1105:Drivers/CMSIS/Include/core_cm7.h **** +1106:Drivers/CMSIS/Include/core_cm7.h **** /** +1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) +1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) +1110:Drivers/CMSIS/Include/core_cm7.h **** @{ +1111:Drivers/CMSIS/Include/core_cm7.h **** */ +1112:Drivers/CMSIS/Include/core_cm7.h **** +1113:Drivers/CMSIS/Include/core_cm7.h **** /** +1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). +1115:Drivers/CMSIS/Include/core_cm7.h **** */ +1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1117:Drivers/CMSIS/Include/core_cm7.h **** { +1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ +1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ +1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe +1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ +1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ +1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe +1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register +1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ +1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ +1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ +1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ +1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ +1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ +1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; +1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ +1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ +1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ +1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; +1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ +1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ +1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; +1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ +1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; +1145:Drivers/CMSIS/Include/core_cm7.h **** +1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ +1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR +1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR +1149:Drivers/CMSIS/Include/core_cm7.h **** +1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR +1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR +1152:Drivers/CMSIS/Include/core_cm7.h **** +1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR + ARM GAS /tmp/ccyvpZhC.s page 48 + + +1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR +1155:Drivers/CMSIS/Include/core_cm7.h **** +1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR +1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR +1158:Drivers/CMSIS/Include/core_cm7.h **** +1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR +1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR +1161:Drivers/CMSIS/Include/core_cm7.h **** +1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR +1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR +1164:Drivers/CMSIS/Include/core_cm7.h **** +1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR +1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR +1167:Drivers/CMSIS/Include/core_cm7.h **** +1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR +1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR +1170:Drivers/CMSIS/Include/core_cm7.h **** +1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR +1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR +1173:Drivers/CMSIS/Include/core_cm7.h **** +1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR +1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR +1176:Drivers/CMSIS/Include/core_cm7.h **** +1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR +1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR +1179:Drivers/CMSIS/Include/core_cm7.h **** +1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR +1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR +1182:Drivers/CMSIS/Include/core_cm7.h **** +1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR +1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR +1185:Drivers/CMSIS/Include/core_cm7.h **** +1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR +1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR +1188:Drivers/CMSIS/Include/core_cm7.h **** +1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR +1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR +1191:Drivers/CMSIS/Include/core_cm7.h **** +1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR +1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR +1194:Drivers/CMSIS/Include/core_cm7.h **** +1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR +1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR +1197:Drivers/CMSIS/Include/core_cm7.h **** +1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR +1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR +1200:Drivers/CMSIS/Include/core_cm7.h **** +1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ +1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI +1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI +1204:Drivers/CMSIS/Include/core_cm7.h **** +1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ +1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC +1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC +1208:Drivers/CMSIS/Include/core_cm7.h **** +1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ +1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE + ARM GAS /tmp/ccyvpZhC.s page 49 + + +1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE +1212:Drivers/CMSIS/Include/core_cm7.h **** +1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ +1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU +1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU +1216:Drivers/CMSIS/Include/core_cm7.h **** +1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ +1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL +1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL +1220:Drivers/CMSIS/Include/core_cm7.h **** +1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ +1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS +1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS +1224:Drivers/CMSIS/Include/core_cm7.h **** +1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ +1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN +1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN +1228:Drivers/CMSIS/Include/core_cm7.h **** +1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN +1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN +1231:Drivers/CMSIS/Include/core_cm7.h **** +1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN +1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN +1234:Drivers/CMSIS/Include/core_cm7.h **** +1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN +1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN +1237:Drivers/CMSIS/Include/core_cm7.h **** +1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN +1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN +1240:Drivers/CMSIS/Include/core_cm7.h **** +1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN +1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN +1243:Drivers/CMSIS/Include/core_cm7.h **** +1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN +1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN +1246:Drivers/CMSIS/Include/core_cm7.h **** +1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN +1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN +1249:Drivers/CMSIS/Include/core_cm7.h **** +1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN +1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN +1252:Drivers/CMSIS/Include/core_cm7.h **** +1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ +1254:Drivers/CMSIS/Include/core_cm7.h **** +1255:Drivers/CMSIS/Include/core_cm7.h **** +1256:Drivers/CMSIS/Include/core_cm7.h **** /** +1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) +1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) +1260:Drivers/CMSIS/Include/core_cm7.h **** @{ +1261:Drivers/CMSIS/Include/core_cm7.h **** */ +1262:Drivers/CMSIS/Include/core_cm7.h **** +1263:Drivers/CMSIS/Include/core_cm7.h **** /** +1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). +1265:Drivers/CMSIS/Include/core_cm7.h **** */ +1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1267:Drivers/CMSIS/Include/core_cm7.h **** { + ARM GAS /tmp/ccyvpZhC.s page 50 + + +1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg +1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis +1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; +1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg +1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; +1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * +1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; +1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis +1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi +1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte +1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; +1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ +1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ +1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ +1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; +1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ +1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ +1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ +1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; +1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ +1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ +1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; +1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ +1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; +1293:Drivers/CMSIS/Include/core_cm7.h **** +1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ +1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP +1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP +1297:Drivers/CMSIS/Include/core_cm7.h **** +1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ +1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP +1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP +1301:Drivers/CMSIS/Include/core_cm7.h **** +1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ +1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS +1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS +1305:Drivers/CMSIS/Include/core_cm7.h **** +1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS +1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS +1308:Drivers/CMSIS/Include/core_cm7.h **** +1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS +1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS +1311:Drivers/CMSIS/Include/core_cm7.h **** +1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS +1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS +1314:Drivers/CMSIS/Include/core_cm7.h **** +1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ +1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC +1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC +1318:Drivers/CMSIS/Include/core_cm7.h **** +1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC +1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC +1321:Drivers/CMSIS/Include/core_cm7.h **** +1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ +1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI +1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI + ARM GAS /tmp/ccyvpZhC.s page 51 + + +1325:Drivers/CMSIS/Include/core_cm7.h **** +1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ +1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF +1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF +1329:Drivers/CMSIS/Include/core_cm7.h **** +1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF +1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF +1332:Drivers/CMSIS/Include/core_cm7.h **** +1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF +1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF +1335:Drivers/CMSIS/Include/core_cm7.h **** +1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF +1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF +1338:Drivers/CMSIS/Include/core_cm7.h **** +1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF +1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF +1341:Drivers/CMSIS/Include/core_cm7.h **** +1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF +1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF +1344:Drivers/CMSIS/Include/core_cm7.h **** +1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF +1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF +1347:Drivers/CMSIS/Include/core_cm7.h **** +1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ +1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA +1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA +1351:Drivers/CMSIS/Include/core_cm7.h **** +1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA +1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA +1354:Drivers/CMSIS/Include/core_cm7.h **** +1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ +1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF +1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF +1358:Drivers/CMSIS/Include/core_cm7.h **** +1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF +1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF +1361:Drivers/CMSIS/Include/core_cm7.h **** +1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF +1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF +1364:Drivers/CMSIS/Include/core_cm7.h **** +1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF +1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF +1367:Drivers/CMSIS/Include/core_cm7.h **** +1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF +1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF +1370:Drivers/CMSIS/Include/core_cm7.h **** +1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF +1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF +1373:Drivers/CMSIS/Include/core_cm7.h **** +1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF +1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF +1376:Drivers/CMSIS/Include/core_cm7.h **** +1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ +1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA +1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA +1380:Drivers/CMSIS/Include/core_cm7.h **** +1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA + ARM GAS /tmp/ccyvpZhC.s page 52 + + +1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA +1383:Drivers/CMSIS/Include/core_cm7.h **** +1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ +1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC +1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC +1387:Drivers/CMSIS/Include/core_cm7.h **** +1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ +1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV +1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV +1391:Drivers/CMSIS/Include/core_cm7.h **** +1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV +1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV +1394:Drivers/CMSIS/Include/core_cm7.h **** +1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV +1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV +1397:Drivers/CMSIS/Include/core_cm7.h **** +1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV +1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV +1400:Drivers/CMSIS/Include/core_cm7.h **** +1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV +1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV +1403:Drivers/CMSIS/Include/core_cm7.h **** +1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV +1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV +1406:Drivers/CMSIS/Include/core_cm7.h **** +1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ +1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV +1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV +1410:Drivers/CMSIS/Include/core_cm7.h **** +1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV +1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV +1413:Drivers/CMSIS/Include/core_cm7.h **** +1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ +1415:Drivers/CMSIS/Include/core_cm7.h **** +1416:Drivers/CMSIS/Include/core_cm7.h **** +1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1418:Drivers/CMSIS/Include/core_cm7.h **** /** +1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) +1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) +1422:Drivers/CMSIS/Include/core_cm7.h **** @{ +1423:Drivers/CMSIS/Include/core_cm7.h **** */ +1424:Drivers/CMSIS/Include/core_cm7.h **** +1425:Drivers/CMSIS/Include/core_cm7.h **** /** +1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). +1427:Drivers/CMSIS/Include/core_cm7.h **** */ +1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1429:Drivers/CMSIS/Include/core_cm7.h **** { +1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ +1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ +1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ +1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register +1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re +1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address +1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and +1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address +1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and + ARM GAS /tmp/ccyvpZhC.s page 53 + + +1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address +1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and +1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; +1442:Drivers/CMSIS/Include/core_cm7.h **** +1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U +1444:Drivers/CMSIS/Include/core_cm7.h **** +1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ +1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU +1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU +1448:Drivers/CMSIS/Include/core_cm7.h **** +1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU +1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU +1451:Drivers/CMSIS/Include/core_cm7.h **** +1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU +1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU +1454:Drivers/CMSIS/Include/core_cm7.h **** +1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ +1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU +1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU +1458:Drivers/CMSIS/Include/core_cm7.h **** +1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU +1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU +1461:Drivers/CMSIS/Include/core_cm7.h **** +1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU +1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU +1464:Drivers/CMSIS/Include/core_cm7.h **** +1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ +1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU +1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU +1468:Drivers/CMSIS/Include/core_cm7.h **** +1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ +1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU +1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU +1472:Drivers/CMSIS/Include/core_cm7.h **** +1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU +1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU +1475:Drivers/CMSIS/Include/core_cm7.h **** +1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU +1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU +1478:Drivers/CMSIS/Include/core_cm7.h **** +1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ +1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU +1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU +1482:Drivers/CMSIS/Include/core_cm7.h **** +1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU +1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU +1485:Drivers/CMSIS/Include/core_cm7.h **** +1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU +1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU +1488:Drivers/CMSIS/Include/core_cm7.h **** +1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU +1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU +1491:Drivers/CMSIS/Include/core_cm7.h **** +1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU +1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU +1494:Drivers/CMSIS/Include/core_cm7.h **** +1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU + ARM GAS /tmp/ccyvpZhC.s page 54 + + +1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU +1497:Drivers/CMSIS/Include/core_cm7.h **** +1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU +1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU +1500:Drivers/CMSIS/Include/core_cm7.h **** +1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU +1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU +1503:Drivers/CMSIS/Include/core_cm7.h **** +1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU +1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU +1506:Drivers/CMSIS/Include/core_cm7.h **** +1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU +1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU +1509:Drivers/CMSIS/Include/core_cm7.h **** +1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ +1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +1512:Drivers/CMSIS/Include/core_cm7.h **** +1513:Drivers/CMSIS/Include/core_cm7.h **** +1514:Drivers/CMSIS/Include/core_cm7.h **** /** +1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) +1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) +1518:Drivers/CMSIS/Include/core_cm7.h **** @{ +1519:Drivers/CMSIS/Include/core_cm7.h **** */ +1520:Drivers/CMSIS/Include/core_cm7.h **** +1521:Drivers/CMSIS/Include/core_cm7.h **** /** +1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). +1523:Drivers/CMSIS/Include/core_cm7.h **** */ +1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1525:Drivers/CMSIS/Include/core_cm7.h **** { +1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R +1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R +1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co +1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 +1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 +1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 +1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; +1534:Drivers/CMSIS/Include/core_cm7.h **** +1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ +1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC +1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC +1538:Drivers/CMSIS/Include/core_cm7.h **** +1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC +1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC +1541:Drivers/CMSIS/Include/core_cm7.h **** +1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC +1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC +1544:Drivers/CMSIS/Include/core_cm7.h **** +1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC +1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC +1547:Drivers/CMSIS/Include/core_cm7.h **** +1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC +1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC +1550:Drivers/CMSIS/Include/core_cm7.h **** +1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC +1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC + ARM GAS /tmp/ccyvpZhC.s page 55 + + +1553:Drivers/CMSIS/Include/core_cm7.h **** +1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC +1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC +1556:Drivers/CMSIS/Include/core_cm7.h **** +1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC +1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC +1559:Drivers/CMSIS/Include/core_cm7.h **** +1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC +1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC +1562:Drivers/CMSIS/Include/core_cm7.h **** +1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ +1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA +1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA +1566:Drivers/CMSIS/Include/core_cm7.h **** +1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ +1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS +1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS +1570:Drivers/CMSIS/Include/core_cm7.h **** +1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS +1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS +1573:Drivers/CMSIS/Include/core_cm7.h **** +1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS +1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS +1576:Drivers/CMSIS/Include/core_cm7.h **** +1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS +1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS +1579:Drivers/CMSIS/Include/core_cm7.h **** +1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ +1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR +1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR +1583:Drivers/CMSIS/Include/core_cm7.h **** +1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR +1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR +1586:Drivers/CMSIS/Include/core_cm7.h **** +1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR +1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR +1589:Drivers/CMSIS/Include/core_cm7.h **** +1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR +1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR +1592:Drivers/CMSIS/Include/core_cm7.h **** +1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR +1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR +1595:Drivers/CMSIS/Include/core_cm7.h **** +1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR +1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR +1598:Drivers/CMSIS/Include/core_cm7.h **** +1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR +1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR +1601:Drivers/CMSIS/Include/core_cm7.h **** +1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR +1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR +1604:Drivers/CMSIS/Include/core_cm7.h **** +1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ +1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR +1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR +1608:Drivers/CMSIS/Include/core_cm7.h **** +1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR + ARM GAS /tmp/ccyvpZhC.s page 56 + + +1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR +1611:Drivers/CMSIS/Include/core_cm7.h **** +1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR +1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR +1614:Drivers/CMSIS/Include/core_cm7.h **** +1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR +1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR +1617:Drivers/CMSIS/Include/core_cm7.h **** +1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ +1619:Drivers/CMSIS/Include/core_cm7.h **** +1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ +1621:Drivers/CMSIS/Include/core_cm7.h **** +1622:Drivers/CMSIS/Include/core_cm7.h **** +1623:Drivers/CMSIS/Include/core_cm7.h **** /** +1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers +1627:Drivers/CMSIS/Include/core_cm7.h **** @{ +1628:Drivers/CMSIS/Include/core_cm7.h **** */ +1629:Drivers/CMSIS/Include/core_cm7.h **** +1630:Drivers/CMSIS/Include/core_cm7.h **** /** +1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). +1632:Drivers/CMSIS/Include/core_cm7.h **** */ +1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1634:Drivers/CMSIS/Include/core_cm7.h **** { +1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status +1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg +1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe +1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont +1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; +1640:Drivers/CMSIS/Include/core_cm7.h **** +1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ +1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core +1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core +1644:Drivers/CMSIS/Include/core_cm7.h **** +1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core +1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core +1647:Drivers/CMSIS/Include/core_cm7.h **** +1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core +1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core +1650:Drivers/CMSIS/Include/core_cm7.h **** +1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core +1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core +1653:Drivers/CMSIS/Include/core_cm7.h **** +1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core +1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core +1656:Drivers/CMSIS/Include/core_cm7.h **** +1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core +1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core +1659:Drivers/CMSIS/Include/core_cm7.h **** +1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core +1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core +1662:Drivers/CMSIS/Include/core_cm7.h **** +1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core +1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core +1665:Drivers/CMSIS/Include/core_cm7.h **** +1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core + ARM GAS /tmp/ccyvpZhC.s page 57 + + +1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core +1668:Drivers/CMSIS/Include/core_cm7.h **** +1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core +1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core +1671:Drivers/CMSIS/Include/core_cm7.h **** +1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core +1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core +1674:Drivers/CMSIS/Include/core_cm7.h **** +1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core +1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core +1677:Drivers/CMSIS/Include/core_cm7.h **** +1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ +1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core +1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core +1681:Drivers/CMSIS/Include/core_cm7.h **** +1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core +1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core +1684:Drivers/CMSIS/Include/core_cm7.h **** +1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ +1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core +1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core +1688:Drivers/CMSIS/Include/core_cm7.h **** +1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core +1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core +1691:Drivers/CMSIS/Include/core_cm7.h **** +1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core +1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core +1694:Drivers/CMSIS/Include/core_cm7.h **** +1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core +1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core +1697:Drivers/CMSIS/Include/core_cm7.h **** +1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core +1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core +1700:Drivers/CMSIS/Include/core_cm7.h **** +1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core +1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core +1703:Drivers/CMSIS/Include/core_cm7.h **** +1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core +1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core +1706:Drivers/CMSIS/Include/core_cm7.h **** +1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core +1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core +1709:Drivers/CMSIS/Include/core_cm7.h **** +1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core +1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core +1712:Drivers/CMSIS/Include/core_cm7.h **** +1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core +1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core +1715:Drivers/CMSIS/Include/core_cm7.h **** +1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core +1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core +1718:Drivers/CMSIS/Include/core_cm7.h **** +1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core +1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core +1721:Drivers/CMSIS/Include/core_cm7.h **** +1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core +1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core + ARM GAS /tmp/ccyvpZhC.s page 58 + + +1724:Drivers/CMSIS/Include/core_cm7.h **** +1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ +1726:Drivers/CMSIS/Include/core_cm7.h **** +1727:Drivers/CMSIS/Include/core_cm7.h **** +1728:Drivers/CMSIS/Include/core_cm7.h **** /** +1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros +1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +1732:Drivers/CMSIS/Include/core_cm7.h **** @{ +1733:Drivers/CMSIS/Include/core_cm7.h **** */ +1734:Drivers/CMSIS/Include/core_cm7.h **** +1735:Drivers/CMSIS/Include/core_cm7.h **** /** +1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. +1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. +1740:Drivers/CMSIS/Include/core_cm7.h **** */ +1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +1742:Drivers/CMSIS/Include/core_cm7.h **** +1743:Drivers/CMSIS/Include/core_cm7.h **** /** +1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. +1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. +1748:Drivers/CMSIS/Include/core_cm7.h **** */ +1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +1750:Drivers/CMSIS/Include/core_cm7.h **** +1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ +1752:Drivers/CMSIS/Include/core_cm7.h **** +1753:Drivers/CMSIS/Include/core_cm7.h **** +1754:Drivers/CMSIS/Include/core_cm7.h **** /** +1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions +1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. +1758:Drivers/CMSIS/Include/core_cm7.h **** @{ +1759:Drivers/CMSIS/Include/core_cm7.h **** */ +1760:Drivers/CMSIS/Include/core_cm7.h **** +1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ +1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas +1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address +1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas +1770:Drivers/CMSIS/Include/core_cm7.h **** +1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register +1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct +1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st +1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc +1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct +1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct +1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct +1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration +1779:Drivers/CMSIS/Include/core_cm7.h **** +1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + ARM GAS /tmp/ccyvpZhC.s page 59 + + +1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * +1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * +1783:Drivers/CMSIS/Include/core_cm7.h **** #endif +1784:Drivers/CMSIS/Include/core_cm7.h **** +1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +1787:Drivers/CMSIS/Include/core_cm7.h **** +1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ +1789:Drivers/CMSIS/Include/core_cm7.h **** +1790:Drivers/CMSIS/Include/core_cm7.h **** +1791:Drivers/CMSIS/Include/core_cm7.h **** +1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* +1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer +1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: +1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions +1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions +1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions +1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions +1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ +1800:Drivers/CMSIS/Include/core_cm7.h **** /** +1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +1802:Drivers/CMSIS/Include/core_cm7.h **** */ +1803:Drivers/CMSIS/Include/core_cm7.h **** +1804:Drivers/CMSIS/Include/core_cm7.h **** +1805:Drivers/CMSIS/Include/core_cm7.h **** +1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ +1807:Drivers/CMSIS/Include/core_cm7.h **** /** +1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions +1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. +1811:Drivers/CMSIS/Include/core_cm7.h **** @{ +1812:Drivers/CMSIS/Include/core_cm7.h **** */ +1813:Drivers/CMSIS/Include/core_cm7.h **** +1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL +1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +1817:Drivers/CMSIS/Include/core_cm7.h **** #endif +1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +1819:Drivers/CMSIS/Include/core_cm7.h **** #else +1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ +1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ +1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive +1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority +1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority +1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset +1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ +1833:Drivers/CMSIS/Include/core_cm7.h **** +1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL +1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +1837:Drivers/CMSIS/Include/core_cm7.h **** #endif + ARM GAS /tmp/ccyvpZhC.s page 60 + + +1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1839:Drivers/CMSIS/Include/core_cm7.h **** #else +1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector +1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector +1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ +1843:Drivers/CMSIS/Include/core_cm7.h **** +1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 +1845:Drivers/CMSIS/Include/core_cm7.h **** +1846:Drivers/CMSIS/Include/core_cm7.h **** +1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ +1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret +1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu +1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu +1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret +1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu +1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu +1854:Drivers/CMSIS/Include/core_cm7.h **** +1855:Drivers/CMSIS/Include/core_cm7.h **** +1856:Drivers/CMSIS/Include/core_cm7.h **** /** +1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping +1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. +1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. +1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. +1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. +1864:Drivers/CMSIS/Include/core_cm7.h **** */ +1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +1866:Drivers/CMSIS/Include/core_cm7.h **** { +1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; +1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a +1869:Drivers/CMSIS/Include/core_cm7.h **** +1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan +1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | +1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a +1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; +1876:Drivers/CMSIS/Include/core_cm7.h **** } +1877:Drivers/CMSIS/Include/core_cm7.h **** +1878:Drivers/CMSIS/Include/core_cm7.h **** +1879:Drivers/CMSIS/Include/core_cm7.h **** /** +1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping +1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. +1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +1883:Drivers/CMSIS/Include/core_cm7.h **** */ +1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +1885:Drivers/CMSIS/Include/core_cm7.h **** { +1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +1887:Drivers/CMSIS/Include/core_cm7.h **** } +1888:Drivers/CMSIS/Include/core_cm7.h **** +1889:Drivers/CMSIS/Include/core_cm7.h **** +1890:Drivers/CMSIS/Include/core_cm7.h **** /** +1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt +1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. +1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. + ARM GAS /tmp/ccyvpZhC.s page 61 + + +1895:Drivers/CMSIS/Include/core_cm7.h **** */ +1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +1897:Drivers/CMSIS/Include/core_cm7.h **** { +1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1899:Drivers/CMSIS/Include/core_cm7.h **** { +1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1901:Drivers/CMSIS/Include/core_cm7.h **** } +1902:Drivers/CMSIS/Include/core_cm7.h **** } +1903:Drivers/CMSIS/Include/core_cm7.h **** +1904:Drivers/CMSIS/Include/core_cm7.h **** +1905:Drivers/CMSIS/Include/core_cm7.h **** /** +1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status +1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. +1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. +1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1912:Drivers/CMSIS/Include/core_cm7.h **** */ +1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +1914:Drivers/CMSIS/Include/core_cm7.h **** { +1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1916:Drivers/CMSIS/Include/core_cm7.h **** { +1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1918:Drivers/CMSIS/Include/core_cm7.h **** } +1919:Drivers/CMSIS/Include/core_cm7.h **** else +1920:Drivers/CMSIS/Include/core_cm7.h **** { +1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1922:Drivers/CMSIS/Include/core_cm7.h **** } +1923:Drivers/CMSIS/Include/core_cm7.h **** } +1924:Drivers/CMSIS/Include/core_cm7.h **** +1925:Drivers/CMSIS/Include/core_cm7.h **** +1926:Drivers/CMSIS/Include/core_cm7.h **** /** +1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt +1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. +1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1931:Drivers/CMSIS/Include/core_cm7.h **** */ +1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +1933:Drivers/CMSIS/Include/core_cm7.h **** { +1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1935:Drivers/CMSIS/Include/core_cm7.h **** { +1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +1939:Drivers/CMSIS/Include/core_cm7.h **** } +1940:Drivers/CMSIS/Include/core_cm7.h **** } +1941:Drivers/CMSIS/Include/core_cm7.h **** +1942:Drivers/CMSIS/Include/core_cm7.h **** +1943:Drivers/CMSIS/Include/core_cm7.h **** /** +1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt +1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe +1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. +1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. +1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1950:Drivers/CMSIS/Include/core_cm7.h **** */ +1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) + ARM GAS /tmp/ccyvpZhC.s page 62 + + +1952:Drivers/CMSIS/Include/core_cm7.h **** { +1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1954:Drivers/CMSIS/Include/core_cm7.h **** { +1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1956:Drivers/CMSIS/Include/core_cm7.h **** } +1957:Drivers/CMSIS/Include/core_cm7.h **** else +1958:Drivers/CMSIS/Include/core_cm7.h **** { +1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1960:Drivers/CMSIS/Include/core_cm7.h **** } +1961:Drivers/CMSIS/Include/core_cm7.h **** } +1962:Drivers/CMSIS/Include/core_cm7.h **** +1963:Drivers/CMSIS/Include/core_cm7.h **** +1964:Drivers/CMSIS/Include/core_cm7.h **** /** +1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt +1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1969:Drivers/CMSIS/Include/core_cm7.h **** */ +1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +1971:Drivers/CMSIS/Include/core_cm7.h **** { +1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1973:Drivers/CMSIS/Include/core_cm7.h **** { +1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1975:Drivers/CMSIS/Include/core_cm7.h **** } +1976:Drivers/CMSIS/Include/core_cm7.h **** } +1977:Drivers/CMSIS/Include/core_cm7.h **** +1978:Drivers/CMSIS/Include/core_cm7.h **** +1979:Drivers/CMSIS/Include/core_cm7.h **** /** +1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt +1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1984:Drivers/CMSIS/Include/core_cm7.h **** */ +1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +1986:Drivers/CMSIS/Include/core_cm7.h **** { +1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1988:Drivers/CMSIS/Include/core_cm7.h **** { +1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1990:Drivers/CMSIS/Include/core_cm7.h **** } +1991:Drivers/CMSIS/Include/core_cm7.h **** } +1992:Drivers/CMSIS/Include/core_cm7.h **** +1993:Drivers/CMSIS/Include/core_cm7.h **** +1994:Drivers/CMSIS/Include/core_cm7.h **** /** +1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt +1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific +1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. +1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. +2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +2001:Drivers/CMSIS/Include/core_cm7.h **** */ +2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +2003:Drivers/CMSIS/Include/core_cm7.h **** { +2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2005:Drivers/CMSIS/Include/core_cm7.h **** { +2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +2007:Drivers/CMSIS/Include/core_cm7.h **** } +2008:Drivers/CMSIS/Include/core_cm7.h **** else + ARM GAS /tmp/ccyvpZhC.s page 63 + + +2009:Drivers/CMSIS/Include/core_cm7.h **** { +2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +2011:Drivers/CMSIS/Include/core_cm7.h **** } +2012:Drivers/CMSIS/Include/core_cm7.h **** } +2013:Drivers/CMSIS/Include/core_cm7.h **** +2014:Drivers/CMSIS/Include/core_cm7.h **** +2015:Drivers/CMSIS/Include/core_cm7.h **** /** +2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority +2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. +2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. +2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. +2023:Drivers/CMSIS/Include/core_cm7.h **** */ +2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +2025:Drivers/CMSIS/Include/core_cm7.h **** { +2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2027:Drivers/CMSIS/Include/core_cm7.h **** { +2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( +2029:Drivers/CMSIS/Include/core_cm7.h **** } +2030:Drivers/CMSIS/Include/core_cm7.h **** else +2031:Drivers/CMSIS/Include/core_cm7.h **** { +2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( +2033:Drivers/CMSIS/Include/core_cm7.h **** } +2034:Drivers/CMSIS/Include/core_cm7.h **** } +2035:Drivers/CMSIS/Include/core_cm7.h **** +2036:Drivers/CMSIS/Include/core_cm7.h **** +2037:Drivers/CMSIS/Include/core_cm7.h **** /** +2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority +2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. +2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. +2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc +2045:Drivers/CMSIS/Include/core_cm7.h **** */ +2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +2047:Drivers/CMSIS/Include/core_cm7.h **** { +2048:Drivers/CMSIS/Include/core_cm7.h **** +2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2050:Drivers/CMSIS/Include/core_cm7.h **** { +2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); +2052:Drivers/CMSIS/Include/core_cm7.h **** } +2053:Drivers/CMSIS/Include/core_cm7.h **** else +2054:Drivers/CMSIS/Include/core_cm7.h **** { +2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); +2056:Drivers/CMSIS/Include/core_cm7.h **** } +2057:Drivers/CMSIS/Include/core_cm7.h **** } +2058:Drivers/CMSIS/Include/core_cm7.h **** +2059:Drivers/CMSIS/Include/core_cm7.h **** +2060:Drivers/CMSIS/Include/core_cm7.h **** /** +2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority +2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, +2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. +2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + ARM GAS /tmp/ccyvpZhC.s page 64 + + +2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). +2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). +2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP +2070:Drivers/CMSIS/Include/core_cm7.h **** */ +2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin +2072:Drivers/CMSIS/Include/core_cm7.h **** { +2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used +2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; +2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; +2076:Drivers/CMSIS/Include/core_cm7.h **** +2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV +2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint +2079:Drivers/CMSIS/Include/core_cm7.h **** +2080:Drivers/CMSIS/Include/core_cm7.h **** return ( +2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits +2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) +2083:Drivers/CMSIS/Include/core_cm7.h **** ); +2084:Drivers/CMSIS/Include/core_cm7.h **** } +2085:Drivers/CMSIS/Include/core_cm7.h **** +2086:Drivers/CMSIS/Include/core_cm7.h **** +2087:Drivers/CMSIS/Include/core_cm7.h **** /** +2088:Drivers/CMSIS/Include/core_cm7.h **** \brief Decode Priority +2089:Drivers/CMSIS/Include/core_cm7.h **** \details Decodes an interrupt priority value with a given priority group to +2090:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value and subpriority value. +2091:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2092:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +2093:Drivers/CMSIS/Include/core_cm7.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC +2094:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2095:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). +2096:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pSubPriority Subpriority value (starting from 0). +2097:Drivers/CMSIS/Include/core_cm7.h **** */ +2098:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons +2099:Drivers/CMSIS/Include/core_cm7.h **** { +2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used +2101:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; +2102:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; +2103:Drivers/CMSIS/Include/core_cm7.h **** +2104:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV +2105:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint +2106:Drivers/CMSIS/Include/core_cm7.h **** +2107:Drivers/CMSIS/Include/core_cm7.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 +2108:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 +2109:Drivers/CMSIS/Include/core_cm7.h **** } +2110:Drivers/CMSIS/Include/core_cm7.h **** +2111:Drivers/CMSIS/Include/core_cm7.h **** +2112:Drivers/CMSIS/Include/core_cm7.h **** /** +2113:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Vector +2114:Drivers/CMSIS/Include/core_cm7.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. +2115:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2116:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2117:Drivers/CMSIS/Include/core_cm7.h **** VTOR must been relocated to SRAM before. +2118:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number +2119:Drivers/CMSIS/Include/core_cm7.h **** \param [in] vector Address of interrupt handler function +2120:Drivers/CMSIS/Include/core_cm7.h **** */ +2121:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +2122:Drivers/CMSIS/Include/core_cm7.h **** { + ARM GAS /tmp/ccyvpZhC.s page 65 + + +2123:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +2124:Drivers/CMSIS/Include/core_cm7.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +2125:Drivers/CMSIS/Include/core_cm7.h **** } +2126:Drivers/CMSIS/Include/core_cm7.h **** +2127:Drivers/CMSIS/Include/core_cm7.h **** +2128:Drivers/CMSIS/Include/core_cm7.h **** /** +2129:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Vector +2130:Drivers/CMSIS/Include/core_cm7.h **** \details Reads an interrupt vector from interrupt vector table. +2131:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2132:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2133:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2134:Drivers/CMSIS/Include/core_cm7.h **** \return Address of interrupt handler function +2135:Drivers/CMSIS/Include/core_cm7.h **** */ +2136:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +2137:Drivers/CMSIS/Include/core_cm7.h **** { +2138:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +2139:Drivers/CMSIS/Include/core_cm7.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +2140:Drivers/CMSIS/Include/core_cm7.h **** } +2141:Drivers/CMSIS/Include/core_cm7.h **** +2142:Drivers/CMSIS/Include/core_cm7.h **** +2143:Drivers/CMSIS/Include/core_cm7.h **** /** +2144:Drivers/CMSIS/Include/core_cm7.h **** \brief System Reset +2145:Drivers/CMSIS/Include/core_cm7.h **** \details Initiates a system reset request to reset the MCU. +2146:Drivers/CMSIS/Include/core_cm7.h **** */ +2147:Drivers/CMSIS/Include/core_cm7.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) + 450 .loc 2 2147 34 view .LVU139 + 451 .LBB13: +2148:Drivers/CMSIS/Include/core_cm7.h **** { +2149:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure all outstanding memor + 452 .loc 2 2149 3 view .LVU140 + 453 .LBB14: + 454 .LBI14: + 455 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccyvpZhC.s page 66 + + + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + ARM GAS /tmp/ccyvpZhC.s page 67 + + + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + ARM GAS /tmp/ccyvpZhC.s page 68 + + + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + ARM GAS /tmp/ccyvpZhC.s page 69 + + + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccyvpZhC.s page 70 + + + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccyvpZhC.s page 71 + + + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + ARM GAS /tmp/ccyvpZhC.s page 72 + + + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccyvpZhC.s page 73 + + + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + ARM GAS /tmp/ccyvpZhC.s page 74 + + + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccyvpZhC.s page 75 + + + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + ARM GAS /tmp/ccyvpZhC.s page 76 + + + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + ARM GAS /tmp/ccyvpZhC.s page 77 + + + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccyvpZhC.s page 78 + + + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccyvpZhC.s page 79 + + + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + ARM GAS /tmp/ccyvpZhC.s page 80 + + + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 456 .loc 3 877 27 view .LVU141 + 457 .LBB15: + ARM GAS /tmp/ccyvpZhC.s page 81 + + + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 458 .loc 3 879 3 view .LVU142 + 459 .syntax unified + 460 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 461 0042 BFF34F8F dsb 0xF + 462 @ 0 "" 2 + 463 .thumb + 464 .syntax unified + 465 .LBE15: + 466 .LBE14: +2150:Drivers/CMSIS/Include/core_cm7.h **** buffered write are completed +2151:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 467 .loc 2 2151 3 view .LVU143 +2152:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 468 .loc 2 2152 32 is_stmt 0 view .LVU144 + 469 0046 0649 ldr r1, .L30+4 + 470 0048 CA68 ldr r2, [r1, #12] + 471 .loc 2 2152 40 view .LVU145 + 472 004a 02F4E062 and r2, r2, #1792 +2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 473 .loc 2 2151 17 view .LVU146 + 474 004e 054B ldr r3, .L30+8 + 475 0050 1343 orrs r3, r3, r2 +2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 476 .loc 2 2151 15 view .LVU147 + 477 0052 CB60 str r3, [r1, #12] +2153:Drivers/CMSIS/Include/core_cm7.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange +2154:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure completion of memory + 478 .loc 2 2154 3 is_stmt 1 view .LVU148 + 479 .LBB16: + 480 .LBI16: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 481 .loc 3 877 27 view .LVU149 + 482 .LBB17: + 483 .loc 3 879 3 view .LVU150 + 484 .syntax unified + 485 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 486 0054 BFF34F8F dsb 0xF + 487 @ 0 "" 2 + 488 .thumb + 489 .syntax unified + 490 .L27: + 491 .LBE17: + 492 .LBE16: +2155:Drivers/CMSIS/Include/core_cm7.h **** +2156:Drivers/CMSIS/Include/core_cm7.h **** for(;;) /* wait until reset */ + 493 .loc 2 2156 3 view .LVU151 +2157:Drivers/CMSIS/Include/core_cm7.h **** { +2158:Drivers/CMSIS/Include/core_cm7.h **** __NOP(); + 494 .loc 2 2158 5 view .LVU152 + 495 .syntax unified + 496 @ 2158 "Drivers/CMSIS/Include/core_cm7.h" 1 + 497 0058 00BF nop + 498 @ 0 "" 2 +2156:Drivers/CMSIS/Include/core_cm7.h **** { + 499 .loc 2 2156 8 view .LVU153 + ARM GAS /tmp/ccyvpZhC.s page 82 + + + 500 .thumb + 501 .syntax unified + 502 005a FDE7 b .L27 + 503 .L31: + 504 .align 2 + 505 .L30: + 506 005c 00000000 .word .LANCHOR0 + 507 0060 00ED00E0 .word -536810240 + 508 0064 0400FA05 .word 100270084 + 509 .LBE13: + 510 .LBE12: + 511 .cfi_endproc + 512 .LFE162: + 514 .section .text.USBD_DFU_EP0_TxReady,"ax",%progbits + 515 .align 1 + 516 .syntax unified + 517 .thumb + 518 .thumb_func + 519 .fpu fpv5-d16 + 521 USBD_DFU_EP0_TxReady: + 522 .LVL33: + 523 .LFB150: + 492:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_SetupReqTypedef req; + 524 .loc 1 492 1 view -0 + 525 .cfi_startproc + 526 @ args = 0, pretend = 0, frame = 8 + 527 @ frame_needed = 0, uses_anonymous_args = 0 + 492:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_SetupReqTypedef req; + 528 .loc 1 492 1 is_stmt 0 view .LVU155 + 529 0000 30B5 push {r4, r5, lr} + 530 .LCFI3: + 531 .cfi_def_cfa_offset 12 + 532 .cfi_offset 4, -12 + 533 .cfi_offset 5, -8 + 534 .cfi_offset 14, -4 + 535 0002 83B0 sub sp, sp, #12 + 536 .LCFI4: + 537 .cfi_def_cfa_offset 24 + 493:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint32_t addr; + 538 .loc 1 493 3 is_stmt 1 view .LVU156 + 494:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 539 .loc 1 494 3 view .LVU157 + 495:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 540 .loc 1 495 3 view .LVU158 + 495:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 541 .loc 1 495 27 is_stmt 0 view .LVU159 + 542 0004 D0F8BC42 ldr r4, [r0, #700] + 543 .LVL34: + 496:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 544 .loc 1 496 3 is_stmt 1 view .LVU160 + 496:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 545 .loc 1 496 26 is_stmt 0 view .LVU161 + 546 0008 D0F8C022 ldr r2, [r0, #704] + 547 .LVL35: + 498:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 548 .loc 1 498 3 is_stmt 1 view .LVU162 + 498:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + ARM GAS /tmp/ccyvpZhC.s page 83 + + + 549 .loc 1 498 11 is_stmt 0 view .LVU163 + 550 000c 04F58053 add r3, r4, #4096 + 551 0010 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 498:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 552 .loc 1 498 6 view .LVU164 + 553 0012 042B cmp r3, #4 + 554 0014 04D0 beq .L43 + 575:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 555 .loc 1 575 8 is_stmt 1 view .LVU165 + 575:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 556 .loc 1 575 11 is_stmt 0 view .LVU166 + 557 0016 072B cmp r3, #7 + 558 0018 5ED0 beq .L44 + 585:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 559 .loc 1 585 10 view .LVU167 + 560 001a 0020 movs r0, #0 + 561 .LVL36: + 562 .L38: + 586:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /** + 563 .loc 1 586 1 view .LVU168 + 564 001c 03B0 add sp, sp, #12 + 565 .LCFI5: + 566 .cfi_remember_state + 567 .cfi_def_cfa_offset 12 + 568 @ sp needed + 569 001e 30BD pop {r4, r5, pc} + 570 .LVL37: + 571 .L43: + 572 .LCFI6: + 573 .cfi_restore_state + 501:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 574 .loc 1 501 5 is_stmt 1 view .LVU169 + 501:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 575 .loc 1 501 13 is_stmt 0 view .LVU170 + 576 0020 04F58053 add r3, r4, #4096 + 577 0024 1968 ldr r1, [r3] + 501:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 578 .loc 1 501 8 view .LVU171 + 579 0026 0029 cmp r1, #0 + 580 0028 3DD1 bne .L34 + 503:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 581 .loc 1 503 7 is_stmt 1 view .LVU172 + 503:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 582 .loc 1 503 14 is_stmt 0 view .LVU173 + 583 002a 5B68 ldr r3, [r3, #4] + 503:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 584 .loc 1 503 9 view .LVU174 + 585 002c 012B cmp r3, #1 + 586 002e 47D0 beq .L35 + 510:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 587 .loc 1 510 12 is_stmt 1 view .LVU175 + 510:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 588 .loc 1 510 15 is_stmt 0 view .LVU176 + 589 0030 052B cmp r3, #5 + 590 0032 2AD1 bne .L36 + 512:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 591 .loc 1 512 9 is_stmt 1 view .LVU177 + ARM GAS /tmp/ccyvpZhC.s page 84 + + + 512:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 592 .loc 1 512 28 is_stmt 0 view .LVU178 + 593 0034 2378 ldrb r3, [r4] @ zero_extendqisi2 + 512:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 594 .loc 1 512 12 view .LVU179 + 595 0036 212B cmp r3, #33 + 596 0038 16D0 beq .L45 + 519:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 597 .loc 1 519 14 is_stmt 1 view .LVU180 + 519:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 598 .loc 1 519 17 is_stmt 0 view .LVU181 + 599 003a 412B cmp r3, #65 + 600 003c 40D1 bne .L35 + 521:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 601 .loc 1 521 11 is_stmt 1 view .LVU182 + 521:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 602 .loc 1 521 43 is_stmt 0 view .LVU183 + 603 003e 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 604 .LVL38: + 521:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 605 .loc 1 521 26 view .LVU184 + 606 0040 04F58053 add r3, r4, #4096 + 607 0044 9860 str r0, [r3, #8] + 522:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 608 .loc 1 522 11 is_stmt 1 view .LVU185 + 522:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 609 .loc 1 522 54 is_stmt 0 view .LVU186 + 610 0046 A178 ldrb r1, [r4, #2] @ zero_extendqisi2 + 522:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 611 .loc 1 522 26 view .LVU187 + 612 0048 00EB0120 add r0, r0, r1, lsl #8 + 613 004c 9860 str r0, [r3, #8] + 523:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 614 .loc 1 523 11 is_stmt 1 view .LVU188 + 523:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 615 .loc 1 523 54 is_stmt 0 view .LVU189 + 616 004e E178 ldrb r1, [r4, #3] @ zero_extendqisi2 + 523:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 617 .loc 1 523 26 view .LVU190 + 618 0050 00EB0140 add r0, r0, r1, lsl #16 + 619 0054 9860 str r0, [r3, #8] + 524:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 620 .loc 1 524 11 is_stmt 1 view .LVU191 + 524:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 621 .loc 1 524 54 is_stmt 0 view .LVU192 + 622 0056 2179 ldrb r1, [r4, #4] @ zero_extendqisi2 + 524:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 623 .loc 1 524 26 view .LVU193 + 624 0058 00EB0160 add r0, r0, r1, lsl #24 + 625 005c 9860 str r0, [r3, #8] + 526:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 626 .loc 1 526 11 is_stmt 1 view .LVU194 + 526:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 627 .loc 1 526 27 is_stmt 0 view .LVU195 + 628 005e D368 ldr r3, [r2, #12] + 526:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 629 .loc 1 526 15 view .LVU196 + ARM GAS /tmp/ccyvpZhC.s page 85 + + + 630 0060 9847 blx r3 + 631 .LVL39: + 526:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 632 .loc 1 526 14 view .LVU197 + 633 0062 68B3 cbz r0, .L35 + 528:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 634 .loc 1 528 20 view .LVU198 + 635 0064 0320 movs r0, #3 + 636 0066 D9E7 b .L38 + 637 .LVL40: + 638 .L45: + 514:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 639 .loc 1 514 11 is_stmt 1 view .LVU199 + 514:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 640 .loc 1 514 43 is_stmt 0 view .LVU200 + 641 0068 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 + 514:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 642 .loc 1 514 26 view .LVU201 + 643 006a 04F58052 add r2, r4, #4096 + 644 .LVL41: + 514:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + 645 .loc 1 514 26 view .LVU202 + 646 006e 9360 str r3, [r2, #8] + 647 .LVL42: + 515:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 648 .loc 1 515 11 is_stmt 1 view .LVU203 + 515:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 649 .loc 1 515 54 is_stmt 0 view .LVU204 + 650 0070 A178 ldrb r1, [r4, #2] @ zero_extendqisi2 + 515:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + 651 .loc 1 515 26 view .LVU205 + 652 0072 03EB0123 add r3, r3, r1, lsl #8 + 653 0076 9360 str r3, [r2, #8] + 516:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 654 .loc 1 516 11 is_stmt 1 view .LVU206 + 516:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 655 .loc 1 516 54 is_stmt 0 view .LVU207 + 656 0078 E178 ldrb r1, [r4, #3] @ zero_extendqisi2 + 516:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + 657 .loc 1 516 26 view .LVU208 + 658 007a 03EB0143 add r3, r3, r1, lsl #16 + 659 007e 9360 str r3, [r2, #8] + 517:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 660 .loc 1 517 11 is_stmt 1 view .LVU209 + 517:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 661 .loc 1 517 54 is_stmt 0 view .LVU210 + 662 0080 2179 ldrb r1, [r4, #4] @ zero_extendqisi2 + 517:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 663 .loc 1 517 26 view .LVU211 + 664 0082 03EB0163 add r3, r3, r1, lsl #24 + 665 0086 9360 str r3, [r2, #8] + 666 0088 1AE0 b .L35 + 667 .LVL43: + 668 .L36: + 539:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 669 .loc 1 539 9 is_stmt 1 view .LVU212 + 539:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + ARM GAS /tmp/ccyvpZhC.s page 86 + + + 670 .loc 1 539 23 is_stmt 0 view .LVU213 + 671 008a 04F58053 add r3, r4, #4096 + 672 008e 0022 movs r2, #0 + 673 .LVL44: + 539:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 674 .loc 1 539 23 view .LVU214 + 675 0090 5A60 str r2, [r3, #4] + 676 .LVL45: + 540:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked) */ + 677 .loc 1 540 9 is_stmt 1 view .LVU215 + 540:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** /* Call the error management function (command will be nacked) */ + 678 .loc 1 540 26 is_stmt 0 view .LVU216 + 679 0092 1A60 str r2, [r3] + 542:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** req.wLength = 1U; + 680 .loc 1 542 9 is_stmt 1 view .LVU217 + 542:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** req.wLength = 1U; + 681 .loc 1 542 23 is_stmt 0 view .LVU218 + 682 0094 8DF80020 strb r2, [sp] + 543:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, &req); + 683 .loc 1 543 9 is_stmt 1 view .LVU219 + 543:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_CtlError(pdev, &req); + 684 .loc 1 543 21 is_stmt 0 view .LVU220 + 685 0098 0123 movs r3, #1 + 686 009a ADF80630 strh r3, [sp, #6] @ movhi + 544:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 687 .loc 1 544 9 is_stmt 1 view .LVU221 + 688 009e 6946 mov r1, sp + 689 00a0 FFF7FEFF bl USBD_CtlError + 690 .LVL46: + 544:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 691 .loc 1 544 9 is_stmt 0 view .LVU222 + 692 00a4 0CE0 b .L35 + 693 .LVL47: + 694 .L34: + 550:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 695 .loc 1 550 7 is_stmt 1 view .LVU223 + 550:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 696 .loc 1 550 10 is_stmt 0 view .LVU224 + 697 00a6 0129 cmp r1, #1 + 698 00a8 0AD9 bls .L35 + 553:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 699 .loc 1 553 9 is_stmt 1 view .LVU225 + 553:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 700 .loc 1 553 35 is_stmt 0 view .LVU226 + 701 00aa 0239 subs r1, r1, #2 + 553:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 702 .loc 1 553 69 view .LVU227 + 703 00ac 04F58053 add r3, r4, #4096 + 704 00b0 9868 ldr r0, [r3, #8] + 705 .LVL48: + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 706 .loc 1 556 9 is_stmt 1 view .LVU228 + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 707 .loc 1 556 25 is_stmt 0 view .LVU229 + 708 00b2 1569 ldr r5, [r2, #16] + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 709 .loc 1 556 13 view .LVU230 + ARM GAS /tmp/ccyvpZhC.s page 87 + + + 710 00b4 5A68 ldr r2, [r3, #4] + 711 .LVL49: + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 712 .loc 1 556 13 view .LVU231 + 713 00b6 00EB0131 add r1, r0, r1, lsl #12 + 714 .LVL50: + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 715 .loc 1 556 13 view .LVU232 + 716 00ba 2046 mov r0, r4 + 717 00bc A847 blx r5 + 718 .LVL51: + 556:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 719 .loc 1 556 12 view .LVU233 + 720 00be 78B9 cbnz r0, .L40 + 721 .L35: + 564:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 722 .loc 1 564 5 is_stmt 1 view .LVU234 + 564:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 723 .loc 1 564 19 is_stmt 0 view .LVU235 + 724 00c0 04F58054 add r4, r4, #4096 + 725 .LVL52: + 564:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 726 .loc 1 564 19 view .LVU236 + 727 00c4 0020 movs r0, #0 + 728 00c6 6060 str r0, [r4, #4] + 565:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 729 .loc 1 565 5 is_stmt 1 view .LVU237 + 565:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 730 .loc 1 565 22 is_stmt 0 view .LVU238 + 731 00c8 2060 str r0, [r4] + 568:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 732 .loc 1 568 5 is_stmt 1 view .LVU239 + 568:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 733 .loc 1 568 21 is_stmt 0 view .LVU240 + 734 00ca 0323 movs r3, #3 + 735 00cc 2376 strb r3, [r4, #24] + 570:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 736 .loc 1 570 5 is_stmt 1 view .LVU241 + 570:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 737 .loc 1 570 25 is_stmt 0 view .LVU242 + 738 00ce 6074 strb r0, [r4, #17] + 571:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 739 .loc 1 571 5 is_stmt 1 view .LVU243 + 571:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 740 .loc 1 571 25 is_stmt 0 view .LVU244 + 741 00d0 A074 strb r0, [r4, #18] + 572:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 742 .loc 1 572 5 is_stmt 1 view .LVU245 + 572:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 743 .loc 1 572 25 is_stmt 0 view .LVU246 + 744 00d2 E074 strb r0, [r4, #19] + 573:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 745 .loc 1 573 5 is_stmt 1 view .LVU247 + 573:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 746 .loc 1 573 25 is_stmt 0 view .LVU248 + 747 00d4 2375 strb r3, [r4, #20] + 748 00d6 A1E7 b .L38 + ARM GAS /tmp/ccyvpZhC.s page 88 + + + 749 .LVL53: + 750 .L44: + 578:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 751 .loc 1 578 5 is_stmt 1 view .LVU249 + 752 00d8 FFF7FEFF bl DFU_Leave + 753 .LVL54: + 585:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 754 .loc 1 585 10 is_stmt 0 view .LVU250 + 755 00dc 0020 movs r0, #0 + 756 00de 9DE7 b .L38 + 757 .L40: + 558:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 758 .loc 1 558 18 view .LVU251 + 759 00e0 0320 movs r0, #3 + 760 00e2 9BE7 b .L38 + 761 .cfi_endproc + 762 .LFE150: + 764 .section .text.DFU_Upload,"ax",%progbits + 765 .align 1 + 766 .syntax unified + 767 .thumb + 768 .thumb_func + 769 .fpu fpv5-d16 + 771 DFU_Upload: + 772 .LVL55: + 773 .LFB157: + 769:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 774 .loc 1 769 1 is_stmt 1 view -0 + 775 .cfi_startproc + 776 @ args = 0, pretend = 0, frame = 0 + 777 @ frame_needed = 0, uses_anonymous_args = 0 + 769:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 778 .loc 1 769 1 is_stmt 0 view .LVU253 + 779 0000 70B5 push {r4, r5, r6, lr} + 780 .LCFI7: + 781 .cfi_def_cfa_offset 16 + 782 .cfi_offset 4, -16 + 783 .cfi_offset 5, -12 + 784 .cfi_offset 6, -8 + 785 .cfi_offset 14, -4 + 770:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 786 .loc 1 770 3 is_stmt 1 view .LVU254 + 770:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 787 .loc 1 770 27 is_stmt 0 view .LVU255 + 788 0002 D0F8BC32 ldr r3, [r0, #700] + 789 .LVL56: + 771:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *phaddr; + 790 .loc 1 771 3 is_stmt 1 view .LVU256 + 771:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *phaddr; + 791 .loc 1 771 26 is_stmt 0 view .LVU257 + 792 0006 D0F8C052 ldr r5, [r0, #704] + 793 .LVL57: + 772:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint32_t addr; + 794 .loc 1 772 3 is_stmt 1 view .LVU258 + 773:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 795 .loc 1 773 3 view .LVU259 + 776:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + ARM GAS /tmp/ccyvpZhC.s page 89 + + + 796 .loc 1 776 3 view .LVU260 + 776:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 797 .loc 1 776 10 is_stmt 0 view .LVU261 + 798 000a CA88 ldrh r2, [r1, #6] + 776:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 799 .loc 1 776 6 view .LVU262 + 800 000c 002A cmp r2, #0 + 801 000e 58D0 beq .L47 + 802 0010 0446 mov r4, r0 + 778:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 803 .loc 1 778 5 is_stmt 1 view .LVU263 + 778:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 804 .loc 1 778 14 is_stmt 0 view .LVU264 + 805 0012 03F58052 add r2, r3, #4096 + 806 0016 127E ldrb r2, [r2, #24] @ zero_extendqisi2 + 778:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 807 .loc 1 778 8 view .LVU265 + 808 0018 092A cmp r2, #9 + 809 001a 18BF it ne + 810 001c 022A cmpne r2, #2 + 811 001e 48D1 bne .L48 + 781:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 812 .loc 1 781 7 is_stmt 1 view .LVU266 + 781:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 813 .loc 1 781 29 is_stmt 0 view .LVU267 + 814 0020 4888 ldrh r0, [r1, #2] + 815 .LVL58: + 781:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 816 .loc 1 781 24 view .LVU268 + 817 0022 03F5805C add ip, r3, #4096 + 818 0026 CCF80000 str r0, [ip] + 782:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 819 .loc 1 782 7 is_stmt 1 view .LVU269 + 782:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 820 .loc 1 782 26 is_stmt 0 view .LVU270 + 821 002a CA88 ldrh r2, [r1, #6] + 782:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 822 .loc 1 782 21 view .LVU271 + 823 002c CCF80420 str r2, [ip, #4] + 785:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 824 .loc 1 785 7 is_stmt 1 view .LVU272 + 785:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 825 .loc 1 785 10 is_stmt 0 view .LVU273 + 826 0030 B8B9 cbnz r0, .L49 + 788:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 827 .loc 1 788 9 is_stmt 1 view .LVU274 + 788:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 828 .loc 1 788 25 is_stmt 0 view .LVU275 + 829 0032 032A cmp r2, #3 + 830 0034 13D9 bls .L53 + 831 0036 0220 movs r0, #2 + 832 .L50: + 788:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 833 .loc 1 788 25 discriminator 4 view .LVU276 + 834 0038 03F58052 add r2, r3, #4096 + 835 003c 1076 strb r0, [r2, #24] + 790:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + ARM GAS /tmp/ccyvpZhC.s page 90 + + + 836 .loc 1 790 9 is_stmt 1 discriminator 4 view .LVU277 + 790:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 837 .loc 1 790 29 is_stmt 0 discriminator 4 view .LVU278 + 838 003e 0021 movs r1, #0 + 839 .LVL59: + 790:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 840 .loc 1 790 29 discriminator 4 view .LVU279 + 841 0040 5174 strb r1, [r2, #17] + 791:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 842 .loc 1 791 9 is_stmt 1 discriminator 4 view .LVU280 + 791:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 843 .loc 1 791 29 is_stmt 0 discriminator 4 view .LVU281 + 844 0042 9174 strb r1, [r2, #18] + 792:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 845 .loc 1 792 9 is_stmt 1 discriminator 4 view .LVU282 + 792:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 846 .loc 1 792 29 is_stmt 0 discriminator 4 view .LVU283 + 847 0044 D174 strb r1, [r2, #19] + 793:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 848 .loc 1 793 9 is_stmt 1 discriminator 4 view .LVU284 + 793:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 849 .loc 1 793 29 is_stmt 0 discriminator 4 view .LVU285 + 850 0046 1075 strb r0, [r2, #20] + 796:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[1] = DFU_CMD_SETADDRESSPOINTER; + 851 .loc 1 796 9 is_stmt 1 discriminator 4 view .LVU286 + 796:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[1] = DFU_CMD_SETADDRESSPOINTER; + 852 .loc 1 796 28 is_stmt 0 discriminator 4 view .LVU287 + 853 0048 1970 strb r1, [r3] + 797:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[2] = DFU_CMD_ERASE; + 854 .loc 1 797 9 is_stmt 1 discriminator 4 view .LVU288 + 797:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->buffer.d8[2] = DFU_CMD_ERASE; + 855 .loc 1 797 28 is_stmt 0 discriminator 4 view .LVU289 + 856 004a 2122 movs r2, #33 + 857 004c 5A70 strb r2, [r3, #1] + 798:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 858 .loc 1 798 9 is_stmt 1 discriminator 4 view .LVU290 + 798:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 859 .loc 1 798 28 is_stmt 0 discriminator 4 view .LVU291 + 860 004e 4122 movs r2, #65 + 861 0050 9A70 strb r2, [r3, #2] + 801:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 862 .loc 1 801 9 is_stmt 1 discriminator 4 view .LVU292 + 801:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 863 .loc 1 801 15 is_stmt 0 discriminator 4 view .LVU293 + 864 0052 0322 movs r2, #3 + 865 0054 1946 mov r1, r3 + 866 0056 2046 mov r0, r4 + 867 0058 FFF7FEFF bl USBD_CtlSendData + 868 .LVL60: + 801:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 869 .loc 1 801 15 discriminator 4 view .LVU294 + 870 005c 3AE0 b .L46 + 871 .LVL61: + 872 .L53: + 788:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 873 .loc 1 788 25 view .LVU295 + 874 005e 0920 movs r0, #9 + ARM GAS /tmp/ccyvpZhC.s page 91 + + + 875 0060 EAE7 b .L50 + 876 .L49: + 803:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 877 .loc 1 803 12 is_stmt 1 view .LVU296 + 803:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 878 .loc 1 803 15 is_stmt 0 view .LVU297 + 879 0062 0128 cmp r0, #1 + 880 0064 18D9 bls .L52 + 805:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 881 .loc 1 805 9 is_stmt 1 view .LVU298 + 805:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 882 .loc 1 805 25 is_stmt 0 view .LVU299 + 883 0066 03F58056 add r6, r3, #4096 + 884 006a 4FF0090C mov ip, #9 + 885 006e 86F818C0 strb ip, [r6, #24] + 807:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 886 .loc 1 807 9 is_stmt 1 view .LVU300 + 807:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 887 .loc 1 807 29 is_stmt 0 view .LVU301 + 888 0072 0021 movs r1, #0 + 889 .LVL62: + 807:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 890 .loc 1 807 29 view .LVU302 + 891 0074 7174 strb r1, [r6, #17] + 808:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 892 .loc 1 808 9 is_stmt 1 view .LVU303 + 808:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 893 .loc 1 808 29 is_stmt 0 view .LVU304 + 894 0076 B174 strb r1, [r6, #18] + 809:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 895 .loc 1 809 9 is_stmt 1 view .LVU305 + 809:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 896 .loc 1 809 29 is_stmt 0 view .LVU306 + 897 0078 F174 strb r1, [r6, #19] + 810:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 898 .loc 1 810 9 is_stmt 1 view .LVU307 + 810:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 899 .loc 1 810 29 is_stmt 0 view .LVU308 + 900 007a 86F814C0 strb ip, [r6, #20] + 812:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 901 .loc 1 812 9 is_stmt 1 view .LVU309 + 812:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 902 .loc 1 812 35 is_stmt 0 view .LVU310 + 903 007e 0238 subs r0, r0, #2 + 904 .LVL63: + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 905 .loc 1 815 9 is_stmt 1 view .LVU311 + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 906 .loc 1 815 30 is_stmt 0 view .LVU312 + 907 0080 6D69 ldr r5, [r5, #20] + 908 .LVL64: + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 909 .loc 1 815 18 view .LVU313 + 910 0082 1946 mov r1, r3 + 911 0084 B368 ldr r3, [r6, #8] + 912 .LVL65: + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + ARM GAS /tmp/ccyvpZhC.s page 92 + + + 913 .loc 1 815 18 view .LVU314 + 914 0086 03EB0030 add r0, r3, r0, lsl #12 + 915 .LVL66: + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 916 .loc 1 815 18 view .LVU315 + 917 008a A847 blx r5 + 918 .LVL67: + 815:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 919 .loc 1 815 18 view .LVU316 + 920 008c 0146 mov r1, r0 + 921 .LVL68: + 818:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 922 .loc 1 818 9 is_stmt 1 view .LVU317 + 818:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 923 .loc 1 818 15 is_stmt 0 view .LVU318 + 924 008e 7268 ldr r2, [r6, #4] + 925 0090 2046 mov r0, r4 + 926 .LVL69: + 818:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 927 .loc 1 818 15 view .LVU319 + 928 0092 FFF7FEFF bl USBD_CtlSendData + 929 .LVL70: + 818:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 930 .loc 1 818 15 view .LVU320 + 931 0096 1DE0 b .L46 + 932 .LVL71: + 933 .L52: + 822:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 934 .loc 1 822 9 is_stmt 1 view .LVU321 + 822:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 935 .loc 1 822 25 is_stmt 0 view .LVU322 + 936 0098 03F58053 add r3, r3, #4096 + 937 .LVL72: + 822:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 938 .loc 1 822 25 view .LVU323 + 939 009c 0F20 movs r0, #15 + 940 009e 1876 strb r0, [r3, #24] + 824:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 941 .loc 1 824 9 is_stmt 1 view .LVU324 + 824:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 942 .loc 1 824 29 is_stmt 0 view .LVU325 + 943 00a0 0022 movs r2, #0 + 944 00a2 5A74 strb r2, [r3, #17] + 825:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 945 .loc 1 825 9 is_stmt 1 view .LVU326 + 825:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 946 .loc 1 825 29 is_stmt 0 view .LVU327 + 947 00a4 9A74 strb r2, [r3, #18] + 826:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 948 .loc 1 826 9 is_stmt 1 view .LVU328 + 826:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 949 .loc 1 826 29 is_stmt 0 view .LVU329 + 950 00a6 DA74 strb r2, [r3, #19] + 827:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 951 .loc 1 827 9 is_stmt 1 view .LVU330 + 827:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 952 .loc 1 827 29 is_stmt 0 view .LVU331 + ARM GAS /tmp/ccyvpZhC.s page 93 + + + 953 00a8 1875 strb r0, [r3, #20] + 830:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 954 .loc 1 830 9 is_stmt 1 view .LVU332 + 955 00aa 2046 mov r0, r4 + 956 00ac FFF7FEFF bl USBD_CtlError + 957 .LVL73: + 830:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 958 .loc 1 830 9 is_stmt 0 view .LVU333 + 959 00b0 10E0 b .L46 + 960 .LVL74: + 961 .L48: + 836:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 962 .loc 1 836 7 is_stmt 1 view .LVU334 + 836:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 963 .loc 1 836 21 is_stmt 0 view .LVU335 + 964 00b2 03F58053 add r3, r3, #4096 + 965 .LVL75: + 836:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 966 .loc 1 836 21 view .LVU336 + 967 00b6 0022 movs r2, #0 + 968 00b8 5A60 str r2, [r3, #4] + 969 .LVL76: + 837:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 970 .loc 1 837 7 is_stmt 1 view .LVU337 + 837:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 971 .loc 1 837 24 is_stmt 0 view .LVU338 + 972 00ba 1A60 str r2, [r3] + 840:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 973 .loc 1 840 7 is_stmt 1 view .LVU339 + 974 00bc FFF7FEFF bl USBD_CtlError + 975 .LVL77: + 840:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 976 .loc 1 840 7 is_stmt 0 view .LVU340 + 977 00c0 08E0 b .L46 + 978 .LVL78: + 979 .L47: + 846:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 980 .loc 1 846 5 is_stmt 1 view .LVU341 + 846:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 981 .loc 1 846 21 is_stmt 0 view .LVU342 + 982 00c2 03F58053 add r3, r3, #4096 + 983 .LVL79: + 846:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 984 .loc 1 846 21 view .LVU343 + 985 00c6 0221 movs r1, #2 + 986 .LVL80: + 846:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 987 .loc 1 846 21 view .LVU344 + 988 00c8 1976 strb r1, [r3, #24] + 989 .LVL81: + 848:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 990 .loc 1 848 5 is_stmt 1 view .LVU345 + 848:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 991 .loc 1 848 25 is_stmt 0 view .LVU346 + 992 00ca 0022 movs r2, #0 + 993 00cc 5A74 strb r2, [r3, #17] + 849:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + ARM GAS /tmp/ccyvpZhC.s page 94 + + + 994 .loc 1 849 5 is_stmt 1 view .LVU347 + 849:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 995 .loc 1 849 25 is_stmt 0 view .LVU348 + 996 00ce 9A74 strb r2, [r3, #18] + 850:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 997 .loc 1 850 5 is_stmt 1 view .LVU349 + 850:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 998 .loc 1 850 25 is_stmt 0 view .LVU350 + 999 00d0 DA74 strb r2, [r3, #19] + 851:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1000 .loc 1 851 5 is_stmt 1 view .LVU351 + 851:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1001 .loc 1 851 25 is_stmt 0 view .LVU352 + 1002 00d2 1975 strb r1, [r3, #20] + 1003 .LVL82: + 1004 .L46: + 853:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1005 .loc 1 853 1 view .LVU353 + 1006 00d4 70BD pop {r4, r5, r6, pc} + 1007 .cfi_endproc + 1008 .LFE157: + 1010 .section .text.DFU_GetStatus,"ax",%progbits + 1011 .align 1 + 1012 .syntax unified + 1013 .thumb + 1014 .thumb_func + 1015 .fpu fpv5-d16 + 1017 DFU_GetStatus: + 1018 .LVL83: + 1019 .LFB158: + 862:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1020 .loc 1 862 1 is_stmt 1 view -0 + 1021 .cfi_startproc + 1022 @ args = 0, pretend = 0, frame = 0 + 1023 @ frame_needed = 0, uses_anonymous_args = 0 + 862:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1024 .loc 1 862 1 is_stmt 0 view .LVU355 + 1025 0000 70B5 push {r4, r5, r6, lr} + 1026 .LCFI8: + 1027 .cfi_def_cfa_offset 16 + 1028 .cfi_offset 4, -16 + 1029 .cfi_offset 5, -12 + 1030 .cfi_offset 6, -8 + 1031 .cfi_offset 14, -4 + 1032 0002 0446 mov r4, r0 + 863:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 1033 .loc 1 863 3 is_stmt 1 view .LVU356 + 863:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + 1034 .loc 1 863 27 is_stmt 0 view .LVU357 + 1035 0004 D0F8BC52 ldr r5, [r0, #700] + 1036 .LVL84: + 864:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1037 .loc 1 864 3 is_stmt 1 view .LVU358 + 864:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1038 .loc 1 864 26 is_stmt 0 view .LVU359 + 1039 0008 D0F8C022 ldr r2, [r0, #704] + 1040 .LVL85: + ARM GAS /tmp/ccyvpZhC.s page 95 + + + 866:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1041 .loc 1 866 3 is_stmt 1 view .LVU360 + 866:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1042 .loc 1 866 15 is_stmt 0 view .LVU361 + 1043 000c 05F58053 add r3, r5, #4096 + 1044 0010 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 866:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1045 .loc 1 866 3 view .LVU362 + 1046 0012 032B cmp r3, #3 + 1047 0014 09D0 beq .L56 + 1048 0016 062B cmp r3, #6 + 1049 0018 36D0 beq .L57 + 1050 .LVL86: + 1051 .L58: + 928:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1052 .loc 1 928 3 is_stmt 1 view .LVU363 + 928:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1053 .loc 1 928 9 is_stmt 0 view .LVU364 + 1054 001a 0622 movs r2, #6 + 1055 001c 41F21001 movw r1, #4112 + 1056 0020 2944 add r1, r1, r5 + 1057 0022 2046 mov r0, r4 + 1058 0024 FFF7FEFF bl USBD_CtlSendData + 1059 .LVL87: + 929:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1060 .loc 1 929 1 view .LVU365 + 1061 0028 70BD pop {r4, r5, r6, pc} + 1062 .LVL88: + 1063 .L56: + 869:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1064 .loc 1 869 5 is_stmt 1 view .LVU366 + 869:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1065 .loc 1 869 13 is_stmt 0 view .LVU367 + 1066 002a 05F58053 add r3, r5, #4096 + 1067 002e 5B68 ldr r3, [r3, #4] + 869:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1068 .loc 1 869 8 view .LVU368 + 1069 0030 03B3 cbz r3, .L59 + 871:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1070 .loc 1 871 7 is_stmt 1 view .LVU369 + 871:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1071 .loc 1 871 23 is_stmt 0 view .LVU370 + 1072 0032 05F58053 add r3, r5, #4096 + 1073 0036 0420 movs r0, #4 + 1074 .LVL89: + 871:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1075 .loc 1 871 23 view .LVU371 + 1076 0038 1876 strb r0, [r3, #24] + 873:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1077 .loc 1 873 7 is_stmt 1 view .LVU372 + 873:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1078 .loc 1 873 27 is_stmt 0 view .LVU373 + 1079 003a 0021 movs r1, #0 + 1080 003c 5974 strb r1, [r3, #17] + 874:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1081 .loc 1 874 7 is_stmt 1 view .LVU374 + 874:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + ARM GAS /tmp/ccyvpZhC.s page 96 + + + 1082 .loc 1 874 27 is_stmt 0 view .LVU375 + 1083 003e 9974 strb r1, [r3, #18] + 875:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1084 .loc 1 875 7 is_stmt 1 view .LVU376 + 875:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1085 .loc 1 875 27 is_stmt 0 view .LVU377 + 1086 0040 D974 strb r1, [r3, #19] + 876:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1087 .loc 1 876 7 is_stmt 1 view .LVU378 + 876:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1088 .loc 1 876 27 is_stmt 0 view .LVU379 + 1089 0042 1875 strb r0, [r3, #20] + 878:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1090 .loc 1 878 7 is_stmt 1 view .LVU380 + 878:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1091 .loc 1 878 16 is_stmt 0 view .LVU381 + 1092 0044 1B68 ldr r3, [r3] + 878:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1093 .loc 1 878 10 view .LVU382 + 1094 0046 13B9 cbnz r3, .L60 + 878:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1095 .loc 1 878 55 discriminator 1 view .LVU383 + 1096 0048 2B78 ldrb r3, [r5] @ zero_extendqisi2 + 878:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1097 .loc 1 878 36 discriminator 1 view .LVU384 + 1098 004a 412B cmp r3, #65 + 1099 004c 09D0 beq .L63 + 1100 .L60: + 884:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1101 .loc 1 884 9 is_stmt 1 view .LVU385 + 884:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1102 .loc 1 884 21 is_stmt 0 view .LVU386 + 1103 004e 9669 ldr r6, [r2, #24] + 884:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1104 .loc 1 884 9 view .LVU387 + 1105 0050 05F58053 add r3, r5, #4096 + 1106 0054 41F21002 movw r2, #4112 + 1107 .LVL90: + 884:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1108 .loc 1 884 9 view .LVU388 + 1109 0058 2A44 add r2, r2, r5 + 1110 005a 0121 movs r1, #1 + 1111 005c 9868 ldr r0, [r3, #8] + 1112 005e B047 blx r6 + 1113 .LVL91: + 1114 0060 DBE7 b .L58 + 1115 .LVL92: + 1116 .L63: + 880:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1117 .loc 1 880 9 is_stmt 1 view .LVU389 + 880:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1118 .loc 1 880 21 is_stmt 0 view .LVU390 + 1119 0062 9669 ldr r6, [r2, #24] + 880:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1120 .loc 1 880 9 view .LVU391 + 1121 0064 05F58053 add r3, r5, #4096 + 1122 0068 41F21002 movw r2, #4112 + ARM GAS /tmp/ccyvpZhC.s page 97 + + + 1123 .LVL93: + 880:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1124 .loc 1 880 9 view .LVU392 + 1125 006c 2A44 add r2, r2, r5 + 1126 006e 9868 ldr r0, [r3, #8] + 1127 0070 B047 blx r6 + 1128 .LVL94: + 1129 0072 D2E7 b .L58 + 1130 .LVL95: + 1131 .L59: + 889:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1132 .loc 1 889 7 is_stmt 1 view .LVU393 + 889:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1133 .loc 1 889 23 is_stmt 0 view .LVU394 + 1134 0074 05F58053 add r3, r5, #4096 + 1135 0078 0521 movs r1, #5 + 1136 007a 1976 strb r1, [r3, #24] + 891:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1137 .loc 1 891 7 is_stmt 1 view .LVU395 + 891:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1138 .loc 1 891 27 is_stmt 0 view .LVU396 + 1139 007c 0022 movs r2, #0 + 1140 .LVL96: + 891:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1141 .loc 1 891 27 view .LVU397 + 1142 007e 5A74 strb r2, [r3, #17] + 892:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1143 .loc 1 892 7 is_stmt 1 view .LVU398 + 892:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1144 .loc 1 892 27 is_stmt 0 view .LVU399 + 1145 0080 9A74 strb r2, [r3, #18] + 893:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1146 .loc 1 893 7 is_stmt 1 view .LVU400 + 893:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1147 .loc 1 893 27 is_stmt 0 view .LVU401 + 1148 0082 DA74 strb r2, [r3, #19] + 894:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1149 .loc 1 894 7 is_stmt 1 view .LVU402 + 894:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1150 .loc 1 894 27 is_stmt 0 view .LVU403 + 1151 0084 1975 strb r1, [r3, #20] + 1152 0086 C8E7 b .L58 + 1153 .LVL97: + 1154 .L57: + 899:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1155 .loc 1 899 5 is_stmt 1 view .LVU404 + 899:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1156 .loc 1 899 13 is_stmt 0 view .LVU405 + 1157 0088 05F58053 add r3, r5, #4096 + 1158 008c 5B7E ldrb r3, [r3, #25] @ zero_extendqisi2 + 899:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1159 .loc 1 899 8 view .LVU406 + 1160 008e 012B cmp r3, #1 + 1161 0090 10D0 beq .L64 + 910:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U)) + 1162 .loc 1 910 7 is_stmt 1 view .LVU407 + 910:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U)) + ARM GAS /tmp/ccyvpZhC.s page 98 + + + 1163 .loc 1 910 10 is_stmt 0 view .LVU408 + 1164 0092 002B cmp r3, #0 + 1165 0094 C1D1 bne .L58 + 911:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1166 .loc 1 911 30 discriminator 1 view .LVU409 + 1167 0096 0D4B ldr r3, .L65 + 1168 0098 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 910:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U)) + 1169 .loc 1 910 56 discriminator 1 view .LVU410 + 1170 009a 13F0040F tst r3, #4 + 1171 009e BCD0 beq .L58 + 913:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1172 .loc 1 913 9 is_stmt 1 view .LVU411 + 913:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1173 .loc 1 913 25 is_stmt 0 view .LVU412 + 1174 00a0 05F58053 add r3, r5, #4096 + 1175 00a4 0221 movs r1, #2 + 1176 00a6 1976 strb r1, [r3, #24] + 915:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1177 .loc 1 915 9 is_stmt 1 view .LVU413 + 915:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1178 .loc 1 915 29 is_stmt 0 view .LVU414 + 1179 00a8 0022 movs r2, #0 + 1180 .LVL98: + 915:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1181 .loc 1 915 29 view .LVU415 + 1182 00aa 5A74 strb r2, [r3, #17] + 916:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1183 .loc 1 916 9 is_stmt 1 view .LVU416 + 916:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1184 .loc 1 916 29 is_stmt 0 view .LVU417 + 1185 00ac 9A74 strb r2, [r3, #18] + 917:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1186 .loc 1 917 9 is_stmt 1 view .LVU418 + 917:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1187 .loc 1 917 29 is_stmt 0 view .LVU419 + 1188 00ae DA74 strb r2, [r3, #19] + 918:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1189 .loc 1 918 9 is_stmt 1 view .LVU420 + 918:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1190 .loc 1 918 29 is_stmt 0 view .LVU421 + 1191 00b0 1975 strb r1, [r3, #20] + 1192 00b2 B2E7 b .L58 + 1193 .LVL99: + 1194 .L64: + 901:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1195 .loc 1 901 7 is_stmt 1 view .LVU422 + 901:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1196 .loc 1 901 23 is_stmt 0 view .LVU423 + 1197 00b4 05F58053 add r3, r5, #4096 + 1198 00b8 0722 movs r2, #7 + 1199 .LVL100: + 901:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1200 .loc 1 901 23 view .LVU424 + 1201 00ba 1A76 strb r2, [r3, #24] + 1202 .LVL101: + 903:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + ARM GAS /tmp/ccyvpZhC.s page 99 + + + 1203 .loc 1 903 7 is_stmt 1 view .LVU425 + 903:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1204 .loc 1 903 27 is_stmt 0 view .LVU426 + 1205 00bc 0121 movs r1, #1 + 1206 00be 5974 strb r1, [r3, #17] + 904:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1207 .loc 1 904 7 is_stmt 1 view .LVU427 + 904:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1208 .loc 1 904 27 is_stmt 0 view .LVU428 + 1209 00c0 0021 movs r1, #0 + 1210 00c2 9974 strb r1, [r3, #18] + 905:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1211 .loc 1 905 7 is_stmt 1 view .LVU429 + 905:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1212 .loc 1 905 27 is_stmt 0 view .LVU430 + 1213 00c4 D974 strb r1, [r3, #19] + 906:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1214 .loc 1 906 7 is_stmt 1 view .LVU431 + 906:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1215 .loc 1 906 27 is_stmt 0 view .LVU432 + 1216 00c6 1A75 strb r2, [r3, #20] + 1217 00c8 A7E7 b .L58 + 1218 .L66: + 1219 00ca 00BF .align 2 + 1220 .L65: + 1221 00cc 00000000 .word .LANCHOR0 + 1222 .cfi_endproc + 1223 .LFE158: + 1225 .section .text.DFU_GetState,"ax",%progbits + 1226 .align 1 + 1227 .syntax unified + 1228 .thumb + 1229 .thumb_func + 1230 .fpu fpv5-d16 + 1232 DFU_GetState: + 1233 .LVL102: + 1234 .LFB160: + 971:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1235 .loc 1 971 1 is_stmt 1 view -0 + 1236 .cfi_startproc + 1237 @ args = 0, pretend = 0, frame = 0 + 1238 @ frame_needed = 0, uses_anonymous_args = 0 + 971:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1239 .loc 1 971 1 is_stmt 0 view .LVU434 + 1240 0000 08B5 push {r3, lr} + 1241 .LCFI9: + 1242 .cfi_def_cfa_offset 8 + 1243 .cfi_offset 3, -8 + 1244 .cfi_offset 14, -4 + 972:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1245 .loc 1 972 3 is_stmt 1 view .LVU435 + 972:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1246 .loc 1 972 27 is_stmt 0 view .LVU436 + 1247 0002 D0F8BC32 ldr r3, [r0, #700] + 1248 .LVL103: + 975:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1249 .loc 1 975 3 is_stmt 1 view .LVU437 + ARM GAS /tmp/ccyvpZhC.s page 100 + + + 975:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1250 .loc 1 975 9 is_stmt 0 view .LVU438 + 1251 0006 0122 movs r2, #1 + 1252 0008 41F21801 movw r1, #4120 + 1253 000c 1944 add r1, r1, r3 + 1254 000e FFF7FEFF bl USBD_CtlSendData + 1255 .LVL104: + 976:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1256 .loc 1 976 1 view .LVU439 + 1257 0012 08BD pop {r3, pc} + 1258 .cfi_endproc + 1259 .LFE160: + 1261 .section .text.DFU_Download,"ax",%progbits + 1262 .align 1 + 1263 .syntax unified + 1264 .thumb + 1265 .thumb_func + 1266 .fpu fpv5-d16 + 1268 DFU_Download: + 1269 .LVL105: + 1270 .LFB156: + 714:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1271 .loc 1 714 1 is_stmt 1 view -0 + 1272 .cfi_startproc + 1273 @ args = 0, pretend = 0, frame = 0 + 1274 @ frame_needed = 0, uses_anonymous_args = 0 + 714:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1275 .loc 1 714 1 is_stmt 0 view .LVU441 + 1276 0000 08B5 push {r3, lr} + 1277 .LCFI10: + 1278 .cfi_def_cfa_offset 8 + 1279 .cfi_offset 3, -8 + 1280 .cfi_offset 14, -4 + 715:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1281 .loc 1 715 3 is_stmt 1 view .LVU442 + 715:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1282 .loc 1 715 27 is_stmt 0 view .LVU443 + 1283 0002 D0F8BC32 ldr r3, [r0, #700] + 1284 .LVL106: + 718:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1285 .loc 1 718 3 is_stmt 1 view .LVU444 + 718:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1286 .loc 1 718 10 is_stmt 0 view .LVU445 + 1287 0006 CA88 ldrh r2, [r1, #6] + 718:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1288 .loc 1 718 6 view .LVU446 + 1289 0008 D2B1 cbz r2, .L70 + 720:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1290 .loc 1 720 5 is_stmt 1 view .LVU447 + 720:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1291 .loc 1 720 14 is_stmt 0 view .LVU448 + 1292 000a 03F58052 add r2, r3, #4096 + 1293 000e 127E ldrb r2, [r2, #24] @ zero_extendqisi2 + 720:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1294 .loc 1 720 8 view .LVU449 + 1295 0010 052A cmp r2, #5 + 1296 0012 18BF it ne + ARM GAS /tmp/ccyvpZhC.s page 101 + + + 1297 0014 022A cmpne r2, #2 + 1298 0016 10D1 bne .L71 + 723:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 1299 .loc 1 723 7 is_stmt 1 view .LVU450 + 723:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 1300 .loc 1 723 29 is_stmt 0 view .LVU451 + 1301 0018 4A88 ldrh r2, [r1, #2] + 723:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = req->wLength; + 1302 .loc 1 723 24 view .LVU452 + 1303 001a 03F5805C add ip, r3, #4096 + 1304 001e CCF80020 str r2, [ip] + 724:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1305 .loc 1 724 7 is_stmt 1 view .LVU453 + 724:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1306 .loc 1 724 26 is_stmt 0 view .LVU454 + 1307 0022 CA88 ldrh r2, [r1, #6] + 724:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1308 .loc 1 724 21 view .LVU455 + 1309 0024 CCF80420 str r2, [ip, #4] + 727:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1310 .loc 1 727 7 is_stmt 1 view .LVU456 + 727:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1311 .loc 1 727 23 is_stmt 0 view .LVU457 + 1312 0028 0321 movs r1, #3 + 1313 .LVL107: + 727:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1314 .loc 1 727 23 view .LVU458 + 1315 002a 8CF81810 strb r1, [ip, #24] + 728:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1316 .loc 1 728 7 is_stmt 1 view .LVU459 + 728:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1317 .loc 1 728 27 is_stmt 0 view .LVU460 + 1318 002e 8CF81410 strb r1, [ip, #20] + 731:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1319 .loc 1 731 7 is_stmt 1 view .LVU461 + 731:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1320 .loc 1 731 13 is_stmt 0 view .LVU462 + 1321 0032 1946 mov r1, r3 + 1322 0034 FFF7FEFF bl USBD_CtlPrepareRx + 1323 .LVL108: + 731:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1324 .loc 1 731 13 view .LVU463 + 1325 0038 14E0 b .L69 + 1326 .LVL109: + 1327 .L71: + 737:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1328 .loc 1 737 7 is_stmt 1 view .LVU464 + 1329 003a FFF7FEFF bl USBD_CtlError + 1330 .LVL110: + 737:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1331 .loc 1 737 7 is_stmt 0 view .LVU465 + 1332 003e 11E0 b .L69 + 1333 .LVL111: + 1334 .L70: + 744:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1335 .loc 1 744 5 is_stmt 1 view .LVU466 + 744:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + ARM GAS /tmp/ccyvpZhC.s page 102 + + + 1336 .loc 1 744 14 is_stmt 0 view .LVU467 + 1337 0040 03F58052 add r2, r3, #4096 + 1338 0044 127E ldrb r2, [r2, #24] @ zero_extendqisi2 + 744:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1339 .loc 1 744 8 view .LVU468 + 1340 0046 022A cmp r2, #2 + 1341 0048 18BF it ne + 1342 004a 052A cmpne r2, #5 + 1343 004c 0BD1 bne .L73 + 746:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; + 1344 .loc 1 746 7 is_stmt 1 view .LVU469 + 746:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; + 1345 .loc 1 746 25 is_stmt 0 view .LVU470 + 1346 004e 03F58053 add r3, r3, #4096 + 1347 .LVL112: + 746:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; + 1348 .loc 1 746 25 view .LVU471 + 1349 0052 0122 movs r2, #1 + 1350 0054 5A76 strb r2, [r3, #25] + 1351 .LVL113: + 747:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1352 .loc 1 747 7 is_stmt 1 view .LVU472 + 747:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1353 .loc 1 747 23 is_stmt 0 view .LVU473 + 1354 0056 0621 movs r1, #6 + 1355 .LVL114: + 747:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1356 .loc 1 747 23 view .LVU474 + 1357 0058 1976 strb r1, [r3, #24] + 748:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1358 .loc 1 748 7 is_stmt 1 view .LVU475 + 748:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1359 .loc 1 748 27 is_stmt 0 view .LVU476 + 1360 005a 0022 movs r2, #0 + 1361 005c 5A74 strb r2, [r3, #17] + 749:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1362 .loc 1 749 7 is_stmt 1 view .LVU477 + 749:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1363 .loc 1 749 27 is_stmt 0 view .LVU478 + 1364 005e 9A74 strb r2, [r3, #18] + 750:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1365 .loc 1 750 7 is_stmt 1 view .LVU479 + 750:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1366 .loc 1 750 27 is_stmt 0 view .LVU480 + 1367 0060 DA74 strb r2, [r3, #19] + 751:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1368 .loc 1 751 7 is_stmt 1 view .LVU481 + 751:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1369 .loc 1 751 27 is_stmt 0 view .LVU482 + 1370 0062 1975 strb r1, [r3, #20] + 1371 .LVL115: + 1372 .L69: + 759:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1373 .loc 1 759 1 view .LVU483 + 1374 0064 08BD pop {r3, pc} + 1375 .LVL116: + 1376 .L73: + ARM GAS /tmp/ccyvpZhC.s page 103 + + + 756:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1377 .loc 1 756 7 is_stmt 1 view .LVU484 + 1378 0066 FFF7FEFF bl USBD_CtlError + 1379 .LVL117: + 759:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1380 .loc 1 759 1 is_stmt 0 view .LVU485 + 1381 006a FBE7 b .L69 + 1382 .cfi_endproc + 1383 .LFE156: + 1385 .section .text.DFU_Detach,"ax",%progbits + 1386 .align 1 + 1387 .syntax unified + 1388 .thumb + 1389 .thumb_func + 1390 .fpu fpv5-d16 + 1392 DFU_Detach: + 1393 .LVL118: + 1394 .LFB155: + 671:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1395 .loc 1 671 1 is_stmt 1 view -0 + 1396 .cfi_startproc + 1397 @ args = 0, pretend = 0, frame = 0 + 1398 @ frame_needed = 0, uses_anonymous_args = 0 + 671:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1399 .loc 1 671 1 is_stmt 0 view .LVU487 + 1400 0000 10B5 push {r4, lr} + 1401 .LCFI11: + 1402 .cfi_def_cfa_offset 8 + 1403 .cfi_offset 4, -8 + 1404 .cfi_offset 14, -4 + 1405 0002 0446 mov r4, r0 + 672:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1406 .loc 1 672 3 is_stmt 1 view .LVU488 + 672:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1407 .loc 1 672 27 is_stmt 0 view .LVU489 + 1408 0004 D0F8BC32 ldr r3, [r0, #700] + 1409 .LVL119: + 674:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + 1410 .loc 1 674 3 is_stmt 1 view .LVU490 + 674:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + 1411 .loc 1 674 12 is_stmt 0 view .LVU491 + 1412 0008 03F58052 add r2, r3, #4096 + 1413 000c 107E ldrb r0, [r2, #24] @ zero_extendqisi2 + 1414 .LVL120: + 675:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + 1415 .loc 1 675 50 view .LVU492 + 1416 000e 821E subs r2, r0, #2 + 1417 0010 D2B2 uxtb r2, r2 + 674:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + 1418 .loc 1 674 6 view .LVU493 + 1419 0012 0528 cmp r0, #5 + 1420 0014 18BF it ne + 1421 0016 012A cmpne r2, #1 + 1422 0018 03D9 bls .L76 + 676:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + 1423 .loc 1 676 50 view .LVU494 + 1424 001a 0628 cmp r0, #6 + ARM GAS /tmp/ccyvpZhC.s page 104 + + + 1425 001c 01D0 beq .L76 + 677:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) + 1426 .loc 1 677 52 view .LVU495 + 1427 001e 0928 cmp r0, #9 + 1428 0020 0CD1 bne .L77 + 1429 .L76: + 681:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 1430 .loc 1 681 5 is_stmt 1 view .LVU496 + 681:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 1431 .loc 1 681 21 is_stmt 0 view .LVU497 + 1432 0022 03F58053 add r3, r3, #4096 + 1433 .LVL121: + 681:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 1434 .loc 1 681 21 view .LVU498 + 1435 0026 0220 movs r0, #2 + 1436 0028 1876 strb r0, [r3, #24] + 1437 .LVL122: + 682:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1438 .loc 1 682 5 is_stmt 1 view .LVU499 + 682:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1439 .loc 1 682 25 is_stmt 0 view .LVU500 + 1440 002a 0022 movs r2, #0 + 1441 002c 1A74 strb r2, [r3, #16] + 683:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1442 .loc 1 683 5 is_stmt 1 view .LVU501 + 683:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1443 .loc 1 683 25 is_stmt 0 view .LVU502 + 1444 002e 5A74 strb r2, [r3, #17] + 684:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 1445 .loc 1 684 5 is_stmt 1 view .LVU503 + 684:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + 1446 .loc 1 684 25 is_stmt 0 view .LVU504 + 1447 0030 9A74 strb r2, [r3, #18] + 685:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1448 .loc 1 685 5 is_stmt 1 view .LVU505 + 685:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = hdfu->dev_state; + 1449 .loc 1 685 25 is_stmt 0 view .LVU506 + 1450 0032 DA74 strb r2, [r3, #19] + 686:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 1451 .loc 1 686 5 is_stmt 1 view .LVU507 + 686:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; /*iString*/ + 1452 .loc 1 686 25 is_stmt 0 view .LVU508 + 1453 0034 1875 strb r0, [r3, #20] + 687:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 1454 .loc 1 687 5 is_stmt 1 view .LVU509 + 687:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 1455 .loc 1 687 25 is_stmt 0 view .LVU510 + 1456 0036 5A75 strb r2, [r3, #21] + 688:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1457 .loc 1 688 5 is_stmt 1 view .LVU511 + 688:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1458 .loc 1 688 22 is_stmt 0 view .LVU512 + 1459 0038 1A60 str r2, [r3] + 689:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1460 .loc 1 689 5 is_stmt 1 view .LVU513 + 689:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1461 .loc 1 689 19 is_stmt 0 view .LVU514 + ARM GAS /tmp/ccyvpZhC.s page 105 + + + 1462 003a 5A60 str r2, [r3, #4] + 1463 .LVL123: + 1464 .L77: + 693:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1465 .loc 1 693 3 is_stmt 1 view .LVU515 + 693:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1466 .loc 1 693 25 is_stmt 0 view .LVU516 + 1467 003c 074B ldr r3, .L81 + 1468 003e 5B7D ldrb r3, [r3, #21] @ zero_extendqisi2 + 693:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1469 .loc 1 693 6 view .LVU517 + 1470 0040 13F0100F tst r3, #16 + 1471 0044 06D0 beq .L78 + 696:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_Start(pdev); + 1472 .loc 1 696 5 is_stmt 1 view .LVU518 + 696:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** (void)USBD_Start(pdev); + 1473 .loc 1 696 11 is_stmt 0 view .LVU519 + 1474 0046 2046 mov r0, r4 + 1475 0048 FFF7FEFF bl USBD_Stop + 1476 .LVL124: + 697:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1477 .loc 1 697 5 is_stmt 1 view .LVU520 + 697:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1478 .loc 1 697 11 is_stmt 0 view .LVU521 + 1479 004c 2046 mov r0, r4 + 1480 004e FFF7FEFF bl USBD_Start + 1481 .LVL125: + 1482 .L75: + 704:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1483 .loc 1 704 1 view .LVU522 + 1484 0052 10BD pop {r4, pc} + 1485 .LVL126: + 1486 .L78: + 702:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1487 .loc 1 702 5 is_stmt 1 view .LVU523 + 1488 0054 4888 ldrh r0, [r1, #2] + 1489 0056 FFF7FEFF bl HAL_Delay + 1490 .LVL127: + 704:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1491 .loc 1 704 1 is_stmt 0 view .LVU524 + 1492 005a FAE7 b .L75 + 1493 .L82: + 1494 .align 2 + 1495 .L81: + 1496 005c 00000000 .word .LANCHOR0 + 1497 .cfi_endproc + 1498 .LFE155: + 1500 .section .text.USBD_DFU_Setup,"ax",%progbits + 1501 .align 1 + 1502 .syntax unified + 1503 .thumb + 1504 .thumb_func + 1505 .fpu fpv5-d16 + 1507 USBD_DFU_Setup: + 1508 .LVL128: + 1509 .LFB147: + 333:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + ARM GAS /tmp/ccyvpZhC.s page 106 + + + 1510 .loc 1 333 1 is_stmt 1 view -0 + 1511 .cfi_startproc + 1512 @ args = 0, pretend = 0, frame = 8 + 1513 @ frame_needed = 0, uses_anonymous_args = 0 + 333:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + 1514 .loc 1 333 1 is_stmt 0 view .LVU526 + 1515 0000 30B5 push {r4, r5, lr} + 1516 .LCFI12: + 1517 .cfi_def_cfa_offset 12 + 1518 .cfi_offset 4, -12 + 1519 .cfi_offset 5, -8 + 1520 .cfi_offset 14, -4 + 1521 0002 83B0 sub sp, sp, #12 + 1522 .LCFI13: + 1523 .cfi_def_cfa_offset 24 + 334:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_StatusTypeDef ret = USBD_OK; + 1524 .loc 1 334 3 is_stmt 1 view .LVU527 + 334:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_StatusTypeDef ret = USBD_OK; + 1525 .loc 1 334 27 is_stmt 0 view .LVU528 + 1526 0004 D0F8BC22 ldr r2, [r0, #700] + 1527 .LVL129: + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1528 .loc 1 335 3 is_stmt 1 view .LVU529 + 336:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint16_t len = 0U; + 1529 .loc 1 336 3 view .LVU530 + 337:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint16_t status_info = 0U; + 1530 .loc 1 337 3 view .LVU531 + 338:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1531 .loc 1 338 3 view .LVU532 + 338:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1532 .loc 1 338 12 is_stmt 0 view .LVU533 + 1533 0008 0023 movs r3, #0 + 1534 000a ADF80630 strh r3, [sp, #6] @ movhi + 340:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1535 .loc 1 340 3 is_stmt 1 view .LVU534 + 340:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1536 .loc 1 340 14 is_stmt 0 view .LVU535 + 1537 000e 0C78 ldrb r4, [r1] @ zero_extendqisi2 + 340:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1538 .loc 1 340 3 view .LVU536 + 1539 0010 14F06004 ands r4, r4, #96 + 1540 0014 29D0 beq .L84 + 1541 0016 202C cmp r4, #32 + 1542 0018 75D1 bne .L85 + 343:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1543 .loc 1 343 5 is_stmt 1 view .LVU537 + 343:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1544 .loc 1 343 16 is_stmt 0 view .LVU538 + 1545 001a 4C78 ldrb r4, [r1, #1] @ zero_extendqisi2 + 1546 001c 062C cmp r4, #6 + 1547 001e 20D8 bhi .L86 + 1548 0020 DFE804F0 tbb [pc, r4] + 1549 .L88: + 1550 0024 1C .byte (.L94-.L88)/2 + 1551 0025 04 .byte (.L93-.L88)/2 + 1552 0026 08 .byte (.L92-.L88)/2 + 1553 0027 0C .byte (.L91-.L88)/2 + ARM GAS /tmp/ccyvpZhC.s page 107 + + + 1554 0028 10 .byte (.L90-.L88)/2 + 1555 0029 14 .byte (.L89-.L88)/2 + 1556 002a 18 .byte (.L87-.L88)/2 + 1557 002b 00 .p2align 1 + 1558 .L93: + 346:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1559 .loc 1 346 7 is_stmt 1 view .LVU539 + 1560 002c FFF7FEFF bl DFU_Download + 1561 .LVL130: + 347:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1562 .loc 1 347 7 view .LVU540 + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1563 .loc 1 335 22 is_stmt 0 view .LVU541 + 1564 0030 0024 movs r4, #0 + 347:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1565 .loc 1 347 7 view .LVU542 + 1566 0032 6BE0 b .L95 + 1567 .LVL131: + 1568 .L92: + 350:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1569 .loc 1 350 7 is_stmt 1 view .LVU543 + 1570 0034 FFF7FEFF bl DFU_Upload + 1571 .LVL132: + 351:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1572 .loc 1 351 7 view .LVU544 + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1573 .loc 1 335 22 is_stmt 0 view .LVU545 + 1574 0038 0024 movs r4, #0 + 351:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1575 .loc 1 351 7 view .LVU546 + 1576 003a 67E0 b .L95 + 1577 .LVL133: + 1578 .L91: + 354:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1579 .loc 1 354 7 is_stmt 1 view .LVU547 + 1580 003c FFF7FEFF bl DFU_GetStatus + 1581 .LVL134: + 355:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1582 .loc 1 355 7 view .LVU548 + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1583 .loc 1 335 22 is_stmt 0 view .LVU549 + 1584 0040 0024 movs r4, #0 + 355:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1585 .loc 1 355 7 view .LVU550 + 1586 0042 63E0 b .L95 + 1587 .LVL135: + 1588 .L90: + 358:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1589 .loc 1 358 7 is_stmt 1 view .LVU551 + 1590 0044 FFF7FEFF bl DFU_ClearStatus + 1591 .LVL136: + 359:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1592 .loc 1 359 7 view .LVU552 + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1593 .loc 1 335 22 is_stmt 0 view .LVU553 + 1594 0048 0024 movs r4, #0 + 359:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + ARM GAS /tmp/ccyvpZhC.s page 108 + + + 1595 .loc 1 359 7 view .LVU554 + 1596 004a 5FE0 b .L95 + 1597 .LVL137: + 1598 .L89: + 362:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1599 .loc 1 362 7 is_stmt 1 view .LVU555 + 1600 004c FFF7FEFF bl DFU_GetState + 1601 .LVL138: + 363:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1602 .loc 1 363 7 view .LVU556 + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1603 .loc 1 335 22 is_stmt 0 view .LVU557 + 1604 0050 0024 movs r4, #0 + 363:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1605 .loc 1 363 7 view .LVU558 + 1606 0052 5BE0 b .L95 + 1607 .LVL139: + 1608 .L87: + 366:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1609 .loc 1 366 7 is_stmt 1 view .LVU559 + 1610 0054 FFF7FEFF bl DFU_Abort + 1611 .LVL140: + 367:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1612 .loc 1 367 7 view .LVU560 + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1613 .loc 1 335 22 is_stmt 0 view .LVU561 + 1614 0058 0024 movs r4, #0 + 367:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1615 .loc 1 367 7 view .LVU562 + 1616 005a 57E0 b .L95 + 1617 .LVL141: + 1618 .L94: + 370:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1619 .loc 1 370 7 is_stmt 1 view .LVU563 + 1620 005c FFF7FEFF bl DFU_Detach + 1621 .LVL142: + 371:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1622 .loc 1 371 7 view .LVU564 + 1623 0060 54E0 b .L95 + 1624 .LVL143: + 1625 .L86: + 374:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1626 .loc 1 374 7 view .LVU565 + 1627 0062 FFF7FEFF bl USBD_CtlError + 1628 .LVL144: + 375:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1629 .loc 1 375 7 view .LVU566 + 376:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1630 .loc 1 376 7 view .LVU567 + 375:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1631 .loc 1 375 11 is_stmt 0 view .LVU568 + 1632 0066 0324 movs r4, #3 + 376:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1633 .loc 1 376 7 view .LVU569 + 1634 0068 50E0 b .L95 + 1635 .LVL145: + 1636 .L84: + ARM GAS /tmp/ccyvpZhC.s page 109 + + + 381:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1637 .loc 1 381 5 is_stmt 1 view .LVU570 + 381:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1638 .loc 1 381 16 is_stmt 0 view .LVU571 + 1639 006a 4D78 ldrb r5, [r1, #1] @ zero_extendqisi2 + 1640 006c 0B2D cmp r5, #11 + 1641 006e 46D8 bhi .L96 + 1642 0070 DFE805F0 tbb [pc, r5] + 1643 .L98: + 1644 0074 06 .byte (.L101-.L98)/2 + 1645 0075 4C .byte (.L95-.L98)/2 + 1646 0076 45 .byte (.L96-.L98)/2 + 1647 0077 45 .byte (.L96-.L98)/2 + 1648 0078 45 .byte (.L96-.L98)/2 + 1649 0079 45 .byte (.L96-.L98)/2 + 1650 007a 15 .byte (.L100-.L98)/2 + 1651 007b 45 .byte (.L96-.L98)/2 + 1652 007c 45 .byte (.L96-.L98)/2 + 1653 007d 45 .byte (.L96-.L98)/2 + 1654 007e 24 .byte (.L99-.L98)/2 + 1655 007f 33 .byte (.L97-.L98)/2 + 1656 .p2align 1 + 1657 .L101: + 384:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1658 .loc 1 384 7 is_stmt 1 view .LVU572 + 384:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1659 .loc 1 384 15 is_stmt 0 view .LVU573 + 1660 0080 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 384:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1661 .loc 1 384 10 view .LVU574 + 1662 0084 032B cmp r3, #3 + 1663 0086 03D0 beq .L109 + 390:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1664 .loc 1 390 9 is_stmt 1 view .LVU575 + 1665 0088 FFF7FEFF bl USBD_CtlError + 1666 .LVL146: + 391:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1667 .loc 1 391 9 view .LVU576 + 391:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1668 .loc 1 391 13 is_stmt 0 view .LVU577 + 1669 008c 0324 movs r4, #3 + 1670 008e 3DE0 b .L95 + 1671 .LVL147: + 1672 .L109: + 386:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1673 .loc 1 386 9 is_stmt 1 view .LVU578 + 386:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1674 .loc 1 386 15 is_stmt 0 view .LVU579 + 1675 0090 0222 movs r2, #2 + 1676 .LVL148: + 386:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1677 .loc 1 386 15 view .LVU580 + 1678 0092 0DF10601 add r1, sp, #6 + 1679 .LVL149: + 386:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1680 .loc 1 386 15 view .LVU581 + 1681 0096 FFF7FEFF bl USBD_CtlSendData + ARM GAS /tmp/ccyvpZhC.s page 110 + + + 1682 .LVL150: + 335:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint8_t *pbuf = NULL; + 1683 .loc 1 335 22 view .LVU582 + 1684 009a 2C46 mov r4, r5 + 1685 009c 36E0 b .L95 + 1686 .LVL151: + 1687 .L100: + 396:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1688 .loc 1 396 7 is_stmt 1 view .LVU583 + 396:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1689 .loc 1 396 15 is_stmt 0 view .LVU584 + 1690 009e 4B88 ldrh r3, [r1, #2] + 396:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1691 .loc 1 396 30 view .LVU585 + 1692 00a0 1B0A lsrs r3, r3, #8 + 396:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1693 .loc 1 396 10 view .LVU586 + 1694 00a2 212B cmp r3, #33 + 1695 00a4 04D0 beq .L110 + 337:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint16_t status_info = 0U; + 1696 .loc 1 337 12 view .LVU587 + 1697 00a6 0022 movs r2, #0 + 1698 .LVL152: + 336:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** uint16_t len = 0U; + 1699 .loc 1 336 12 view .LVU588 + 1700 00a8 1146 mov r1, r2 + 1701 .LVL153: + 1702 .L103: + 402:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1703 .loc 1 402 7 is_stmt 1 view .LVU589 + 402:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1704 .loc 1 402 13 is_stmt 0 view .LVU590 + 1705 00aa FFF7FEFF bl USBD_CtlSendData + 1706 .LVL154: + 403:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1707 .loc 1 403 7 is_stmt 1 view .LVU591 + 1708 00ae 2DE0 b .L95 + 1709 .LVL155: + 1710 .L110: + 398:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** len = MIN(USB_DFU_DESC_SIZ, req->wLength); + 1711 .loc 1 398 9 view .LVU592 + 399:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1712 .loc 1 399 9 view .LVU593 + 399:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1713 .loc 1 399 15 is_stmt 0 view .LVU594 + 1714 00b0 CA88 ldrh r2, [r1, #6] + 1715 .LVL156: + 399:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1716 .loc 1 399 13 view .LVU595 + 1717 00b2 092A cmp r2, #9 + 1718 00b4 28BF it cs + 1719 00b6 0922 movcs r2, #9 + 1720 .LVL157: + 398:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** len = MIN(USB_DFU_DESC_SIZ, req->wLength); + 1721 .loc 1 398 14 view .LVU596 + 1722 00b8 1649 ldr r1, .L112 + 1723 .LVL158: + ARM GAS /tmp/ccyvpZhC.s page 111 + + + 398:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** len = MIN(USB_DFU_DESC_SIZ, req->wLength); + 1724 .loc 1 398 14 view .LVU597 + 1725 00ba F6E7 b .L103 + 1726 .LVL159: + 1727 .L99: + 406:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1728 .loc 1 406 7 is_stmt 1 view .LVU598 + 406:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1729 .loc 1 406 15 is_stmt 0 view .LVU599 + 1730 00bc 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 406:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1731 .loc 1 406 10 view .LVU600 + 1732 00c0 032B cmp r3, #3 + 1733 00c2 03D0 beq .L111 + 412:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1734 .loc 1 412 9 is_stmt 1 view .LVU601 + 1735 00c4 FFF7FEFF bl USBD_CtlError + 1736 .LVL160: + 413:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1737 .loc 1 413 9 view .LVU602 + 413:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1738 .loc 1 413 13 is_stmt 0 view .LVU603 + 1739 00c8 0324 movs r4, #3 + 1740 00ca 1FE0 b .L95 + 1741 .LVL161: + 1742 .L111: + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1743 .loc 1 408 9 is_stmt 1 view .LVU604 + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1744 .loc 1 408 53 is_stmt 0 view .LVU605 + 1745 00cc 02F58053 add r3, r2, #4096 + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1746 .loc 1 408 15 view .LVU606 + 1747 00d0 0122 movs r2, #1 + 1748 .LVL162: + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1749 .loc 1 408 15 view .LVU607 + 1750 00d2 D968 ldr r1, [r3, #12] + 1751 .LVL163: + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1752 .loc 1 408 15 view .LVU608 + 1753 00d4 FFF7FEFF bl USBD_CtlSendData + 1754 .LVL164: + 408:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1755 .loc 1 408 15 view .LVU609 + 1756 00d8 18E0 b .L95 + 1757 .LVL165: + 1758 .L97: + 418:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1759 .loc 1 418 7 is_stmt 1 view .LVU610 + 418:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1760 .loc 1 418 11 is_stmt 0 view .LVU611 + 1761 00da 8C78 ldrb r4, [r1, #2] @ zero_extendqisi2 + 418:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1762 .loc 1 418 10 view .LVU612 + 1763 00dc 5CB9 cbnz r4, .L105 + 420:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + ARM GAS /tmp/ccyvpZhC.s page 112 + + + 1764 .loc 1 420 9 is_stmt 1 view .LVU613 + 420:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1765 .loc 1 420 17 is_stmt 0 view .LVU614 + 1766 00de 90F89C32 ldrb r3, [r0, #668] @ zero_extendqisi2 + 420:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1767 .loc 1 420 12 view .LVU615 + 1768 00e2 032B cmp r3, #3 + 1769 00e4 03D1 bne .L106 + 422:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1770 .loc 1 422 11 is_stmt 1 view .LVU616 + 422:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1771 .loc 1 422 29 is_stmt 0 view .LVU617 + 1772 00e6 02F58052 add r2, r2, #4096 + 1773 .LVL166: + 422:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1774 .loc 1 422 29 view .LVU618 + 1775 00ea D460 str r4, [r2, #12] + 1776 .LVL167: + 422:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1777 .loc 1 422 29 view .LVU619 + 1778 00ec 0EE0 b .L95 + 1779 .LVL168: + 1780 .L106: + 426:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1781 .loc 1 426 11 is_stmt 1 view .LVU620 + 1782 00ee FFF7FEFF bl USBD_CtlError + 1783 .LVL169: + 427:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1784 .loc 1 427 11 view .LVU621 + 427:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1785 .loc 1 427 15 is_stmt 0 view .LVU622 + 1786 00f2 0324 movs r4, #3 + 1787 00f4 0AE0 b .L95 + 1788 .LVL170: + 1789 .L105: + 433:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1790 .loc 1 433 9 is_stmt 1 view .LVU623 + 1791 00f6 FFF7FEFF bl USBD_CtlError + 1792 .LVL171: + 434:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1793 .loc 1 434 9 view .LVU624 + 434:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1794 .loc 1 434 13 is_stmt 0 view .LVU625 + 1795 00fa 0324 movs r4, #3 + 1796 00fc 06E0 b .L95 + 1797 .LVL172: + 1798 .L96: + 442:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1799 .loc 1 442 7 is_stmt 1 view .LVU626 + 1800 00fe FFF7FEFF bl USBD_CtlError + 1801 .LVL173: + 443:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1802 .loc 1 443 7 view .LVU627 + 444:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1803 .loc 1 444 7 view .LVU628 + 443:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1804 .loc 1 443 11 is_stmt 0 view .LVU629 + ARM GAS /tmp/ccyvpZhC.s page 113 + + + 1805 0102 0324 movs r4, #3 + 444:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1806 .loc 1 444 7 view .LVU630 + 1807 0104 02E0 b .L95 + 1808 .LVL174: + 1809 .L85: + 449:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** ret = USBD_FAIL; + 1810 .loc 1 449 5 is_stmt 1 view .LVU631 + 1811 0106 FFF7FEFF bl USBD_CtlError + 1812 .LVL175: + 450:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1813 .loc 1 450 5 view .LVU632 + 451:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1814 .loc 1 451 5 view .LVU633 + 450:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** break; + 1815 .loc 1 450 9 is_stmt 0 view .LVU634 + 1816 010a 0324 movs r4, #3 + 1817 .LVL176: + 1818 .L95: + 454:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1819 .loc 1 454 3 is_stmt 1 view .LVU635 + 455:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1820 .loc 1 455 1 is_stmt 0 view .LVU636 + 1821 010c 2046 mov r0, r4 + 1822 010e 03B0 add sp, sp, #12 + 1823 .LCFI14: + 1824 .cfi_def_cfa_offset 12 + 1825 @ sp needed + 1826 0110 30BD pop {r4, r5, pc} + 1827 .LVL177: + 1828 .L113: + 455:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1829 .loc 1 455 1 view .LVU637 + 1830 0112 00BF .align 2 + 1831 .L112: + 1832 0114 12000000 .word .LANCHOR0+18 + 1833 .cfi_endproc + 1834 .LFE147: + 1836 .section .text.USBD_DFU_DeInit,"ax",%progbits + 1837 .align 1 + 1838 .syntax unified + 1839 .thumb + 1840 .thumb_func + 1841 .fpu fpv5-d16 + 1843 USBD_DFU_DeInit: + 1844 .LVL178: + 1845 .LFB146: + 300:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(cfgidx); + 1846 .loc 1 300 1 is_stmt 1 view -0 + 1847 .cfi_startproc + 1848 @ args = 0, pretend = 0, frame = 0 + 1849 @ frame_needed = 0, uses_anonymous_args = 0 + 300:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(cfgidx); + 1850 .loc 1 300 1 is_stmt 0 view .LVU639 + 1851 0000 38B5 push {r3, r4, r5, lr} + 1852 .LCFI15: + 1853 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccyvpZhC.s page 114 + + + 1854 .cfi_offset 3, -16 + 1855 .cfi_offset 4, -12 + 1856 .cfi_offset 5, -8 + 1857 .cfi_offset 14, -4 + 301:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_DFU_HandleTypeDef *hdfu; + 1858 .loc 1 301 3 is_stmt 1 view .LVU640 + 302:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1859 .loc 1 302 3 view .LVU641 + 304:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1860 .loc 1 304 3 view .LVU642 + 304:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1861 .loc 1 304 11 is_stmt 0 view .LVU643 + 1862 0002 D0F8BC32 ldr r3, [r0, #700] + 304:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1863 .loc 1 304 6 view .LVU644 + 1864 0006 ABB1 cbz r3, .L116 + 1865 0008 0546 mov r5, r0 + 309:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 1866 .loc 1 309 3 is_stmt 1 view .LVU645 + 1867 .LVL179: + 310:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1868 .loc 1 310 3 view .LVU646 + 310:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1869 .loc 1 310 20 is_stmt 0 view .LVU647 + 1870 000a 03F58053 add r3, r3, #4096 + 1871 .LVL180: + 310:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1872 .loc 1 310 20 view .LVU648 + 1873 000e 0024 movs r4, #0 + 1874 0010 1C60 str r4, [r3] + 1875 .LVL181: + 311:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1876 .loc 1 311 3 is_stmt 1 view .LVU649 + 311:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1877 .loc 1 311 17 is_stmt 0 view .LVU650 + 1878 0012 5C60 str r4, [r3, #4] + 313:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 1879 .loc 1 313 3 is_stmt 1 view .LVU651 + 313:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[0] = DFU_ERROR_NONE; + 1880 .loc 1 313 19 is_stmt 0 view .LVU652 + 1881 0014 0222 movs r2, #2 + 1882 0016 1A76 strb r2, [r3, #24] + 314:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = DFU_STATE_IDLE; + 1883 .loc 1 314 3 is_stmt 1 view .LVU653 + 314:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = DFU_STATE_IDLE; + 1884 .loc 1 314 23 is_stmt 0 view .LVU654 + 1885 0018 1C74 strb r4, [r3, #16] + 315:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1886 .loc 1 315 3 is_stmt 1 view .LVU655 + 315:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1887 .loc 1 315 23 is_stmt 0 view .LVU656 + 1888 001a 1A75 strb r2, [r3, #20] + 318:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_free(pdev->pClassData); + 1889 .loc 1 318 3 is_stmt 1 view .LVU657 + 318:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_free(pdev->pClassData); + 1890 .loc 1 318 33 is_stmt 0 view .LVU658 + 1891 001c D0F8C032 ldr r3, [r0, #704] + ARM GAS /tmp/ccyvpZhC.s page 115 + + + 1892 .LVL182: + 318:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_free(pdev->pClassData); + 1893 .loc 1 318 45 view .LVU659 + 1894 0020 9B68 ldr r3, [r3, #8] + 318:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** USBD_free(pdev->pClassData); + 1895 .loc 1 318 4 view .LVU660 + 1896 0022 9847 blx r3 + 1897 .LVL183: + 319:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** pdev->pClassData = NULL; + 1898 .loc 1 319 3 is_stmt 1 view .LVU661 + 1899 0024 D5F8BC02 ldr r0, [r5, #700] + 1900 0028 FFF7FEFF bl free + 1901 .LVL184: + 320:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1902 .loc 1 320 3 view .LVU662 + 320:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1903 .loc 1 320 20 is_stmt 0 view .LVU663 + 1904 002c C5F8BC42 str r4, [r5, #700] + 322:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1905 .loc 1 322 3 is_stmt 1 view .LVU664 + 322:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1906 .loc 1 322 10 is_stmt 0 view .LVU665 + 1907 0030 2046 mov r0, r4 + 1908 .LVL185: + 1909 .L115: + 323:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1910 .loc 1 323 1 view .LVU666 + 1911 0032 38BD pop {r3, r4, r5, pc} + 1912 .LVL186: + 1913 .L116: + 306:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1914 .loc 1 306 12 view .LVU667 + 1915 0034 0220 movs r0, #2 + 1916 .LVL187: + 306:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 1917 .loc 1 306 12 view .LVU668 + 1918 0036 FCE7 b .L115 + 1919 .cfi_endproc + 1920 .LFE146: + 1922 .section .text.USBD_DFU_Init,"ax",%progbits + 1923 .align 1 + 1924 .syntax unified + 1925 .thumb + 1926 .thumb_func + 1927 .fpu fpv5-d16 + 1929 USBD_DFU_Init: + 1930 .LVL188: + 1931 .LFB145: + 252:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(cfgidx); + 1932 .loc 1 252 1 is_stmt 1 view -0 + 1933 .cfi_startproc + 1934 @ args = 0, pretend = 0, frame = 0 + 1935 @ frame_needed = 0, uses_anonymous_args = 0 + 252:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** UNUSED(cfgidx); + 1936 .loc 1 252 1 is_stmt 0 view .LVU670 + 1937 0000 10B5 push {r4, lr} + 1938 .LCFI16: + ARM GAS /tmp/ccyvpZhC.s page 116 + + + 1939 .cfi_def_cfa_offset 8 + 1940 .cfi_offset 4, -8 + 1941 .cfi_offset 14, -4 + 1942 0002 0446 mov r4, r0 + 253:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1943 .loc 1 253 3 is_stmt 1 view .LVU671 + 255:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1944 .loc 1 255 3 view .LVU672 + 258:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1945 .loc 1 258 3 view .LVU673 + 258:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1946 .loc 1 258 10 is_stmt 0 view .LVU674 + 1947 0004 41F21C00 movw r0, #4124 + 1948 .LVL189: + 258:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1949 .loc 1 258 10 view .LVU675 + 1950 0008 FFF7FEFF bl malloc + 1951 .LVL190: + 260:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1952 .loc 1 260 3 is_stmt 1 view .LVU676 + 260:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1953 .loc 1 260 6 is_stmt 0 view .LVU677 + 1954 000c C8B1 cbz r0, .L123 + 266:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1955 .loc 1 266 3 is_stmt 1 view .LVU678 + 266:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1956 .loc 1 266 20 is_stmt 0 view .LVU679 + 1957 000e C4F8BC02 str r0, [r4, #700] + 268:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; + 1958 .loc 1 268 3 is_stmt 1 view .LVU680 + 268:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; + 1959 .loc 1 268 21 is_stmt 0 view .LVU681 + 1960 0012 00F58053 add r3, r0, #4096 + 1961 0016 0022 movs r2, #0 + 1962 0018 DA60 str r2, [r3, #12] + 269:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 1963 .loc 1 269 3 is_stmt 1 view .LVU682 + 269:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wblock_num = 0U; + 1964 .loc 1 269 18 is_stmt 0 view .LVU683 + 1965 001a 4FF01041 mov r1, #-1879048192 + 1966 001e 9960 str r1, [r3, #8] + 270:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1967 .loc 1 270 3 is_stmt 1 view .LVU684 + 270:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->wlength = 0U; + 1968 .loc 1 270 20 is_stmt 0 view .LVU685 + 1969 0020 1A60 str r2, [r3] + 271:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1970 .loc 1 271 3 is_stmt 1 view .LVU686 + 271:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1971 .loc 1 271 17 is_stmt 0 view .LVU687 + 1972 0022 5A60 str r2, [r3, #4] + 273:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 1973 .loc 1 273 3 is_stmt 1 view .LVU688 + 273:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_state = DFU_STATE_IDLE; + 1974 .loc 1 273 21 is_stmt 0 view .LVU689 + 1975 0024 5A76 strb r2, [r3, #25] + 274:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + ARM GAS /tmp/ccyvpZhC.s page 117 + + + 1976 .loc 1 274 3 is_stmt 1 view .LVU690 + 274:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1977 .loc 1 274 19 is_stmt 0 view .LVU691 + 1978 0026 0221 movs r1, #2 + 1979 0028 1976 strb r1, [r3, #24] + 276:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1980 .loc 1 276 3 is_stmt 1 view .LVU692 + 276:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[1] = 0U; + 1981 .loc 1 276 23 is_stmt 0 view .LVU693 + 1982 002a 1A74 strb r2, [r3, #16] + 277:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1983 .loc 1 277 3 is_stmt 1 view .LVU694 + 277:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[2] = 0U; + 1984 .loc 1 277 23 is_stmt 0 view .LVU695 + 1985 002c 5A74 strb r2, [r3, #17] + 278:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1986 .loc 1 278 3 is_stmt 1 view .LVU696 + 278:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[3] = 0U; + 1987 .loc 1 278 23 is_stmt 0 view .LVU697 + 1988 002e 9A74 strb r2, [r3, #18] + 279:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = DFU_STATE_IDLE; + 1989 .loc 1 279 3 is_stmt 1 view .LVU698 + 279:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[4] = DFU_STATE_IDLE; + 1990 .loc 1 279 23 is_stmt 0 view .LVU699 + 1991 0030 DA74 strb r2, [r3, #19] + 280:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; + 1992 .loc 1 280 3 is_stmt 1 view .LVU700 + 280:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** hdfu->dev_status[5] = 0U; + 1993 .loc 1 280 23 is_stmt 0 view .LVU701 + 1994 0032 1975 strb r1, [r3, #20] + 281:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1995 .loc 1 281 3 is_stmt 1 view .LVU702 + 281:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 1996 .loc 1 281 23 is_stmt 0 view .LVU703 + 1997 0034 5A75 strb r2, [r3, #21] + 284:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1998 .loc 1 284 3 is_stmt 1 view .LVU704 + 284:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 1999 .loc 1 284 37 is_stmt 0 view .LVU705 + 2000 0036 D4F8C032 ldr r3, [r4, #704] + 284:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 2001 .loc 1 284 49 view .LVU706 + 2002 003a 5B68 ldr r3, [r3, #4] + 284:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 2003 .loc 1 284 8 view .LVU707 + 2004 003c 9847 blx r3 + 2005 .LVL191: + 284:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 2006 .loc 1 284 6 view .LVU708 + 2007 003e 28B9 cbnz r0, .L124 + 2008 .L120: + 290:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 2009 .loc 1 290 1 view .LVU709 + 2010 0040 10BD pop {r4, pc} + 2011 .LVL192: + 2012 .L123: + 262:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_EMEM; + ARM GAS /tmp/ccyvpZhC.s page 118 + + + 2013 .loc 1 262 5 is_stmt 1 view .LVU710 + 262:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** return (uint8_t)USBD_EMEM; + 2014 .loc 1 262 22 is_stmt 0 view .LVU711 + 2015 0042 0023 movs r3, #0 + 2016 0044 C4F8BC32 str r3, [r4, #700] + 263:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2017 .loc 1 263 5 is_stmt 1 view .LVU712 + 263:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2018 .loc 1 263 12 is_stmt 0 view .LVU713 + 2019 0048 0220 movs r0, #2 + 2020 .LVL193: + 263:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2021 .loc 1 263 12 view .LVU714 + 2022 004a F9E7 b .L120 + 2023 .L124: + 286:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2024 .loc 1 286 12 view .LVU715 + 2025 004c 0320 movs r0, #3 + 2026 004e F7E7 b .L120 + 2027 .cfi_endproc + 2028 .LFE145: + 2030 .section .text.USBD_DFU_RegisterMedia,"ax",%progbits + 2031 .align 1 + 2032 .global USBD_DFU_RegisterMedia + 2033 .syntax unified + 2034 .thumb + 2035 .thumb_func + 2036 .fpu fpv5-d16 + 2038 USBD_DFU_RegisterMedia: + 2039 .LVL194: + 2040 .LFB154: + 649:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** if (fops == NULL) + 2041 .loc 1 649 1 is_stmt 1 view -0 + 2042 .cfi_startproc + 2043 @ args = 0, pretend = 0, frame = 0 + 2044 @ frame_needed = 0, uses_anonymous_args = 0 + 2045 @ link register save eliminated. + 650:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 2046 .loc 1 650 3 view .LVU717 + 650:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** { + 2047 .loc 1 650 6 is_stmt 0 view .LVU718 + 2048 0000 19B1 cbz r1, .L127 + 655:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 2049 .loc 1 655 3 is_stmt 1 view .LVU719 + 655:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 2050 .loc 1 655 19 is_stmt 0 view .LVU720 + 2051 0002 C0F8C012 str r1, [r0, #704] + 657:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2052 .loc 1 657 3 is_stmt 1 view .LVU721 + 657:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2053 .loc 1 657 10 is_stmt 0 view .LVU722 + 2054 0006 0020 movs r0, #0 + 2055 .LVL195: + 657:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2056 .loc 1 657 10 view .LVU723 + 2057 0008 7047 bx lr + 2058 .LVL196: + ARM GAS /tmp/ccyvpZhC.s page 119 + + + 2059 .L127: + 652:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** } + 2060 .loc 1 652 12 view .LVU724 + 2061 000a 0320 movs r0, #3 + 2062 .LVL197: + 658:Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c **** + 2063 .loc 1 658 1 view .LVU725 + 2064 000c 7047 bx lr + 2065 .cfi_endproc + 2066 .LFE154: + 2068 .global USBD_DFU + 2069 .section .bss.USBD_StrDesc.0,"aw",%nobits + 2070 .align 2 + 2071 .set .LANCHOR2,. + 0 + 2074 USBD_StrDesc.0: + 2075 0000 00000000 .space 255 + 2075 00000000 + 2075 00000000 + 2075 00000000 + 2075 00000000 + 2076 .section .data.USBD_DFU,"aw" + 2077 .align 2 + 2080 USBD_DFU: + 2081 0000 00000000 .word USBD_DFU_Init + 2082 0004 00000000 .word USBD_DFU_DeInit + 2083 0008 00000000 .word USBD_DFU_Setup + 2084 000c 00000000 .word USBD_DFU_EP0_TxReady + 2085 0010 00000000 .word USBD_DFU_EP0_RxReady + 2086 0014 00000000 .word 0 + 2087 0018 00000000 .word 0 + 2088 001c 00000000 .word USBD_DFU_SOF + 2089 0020 00000000 .word 0 + 2090 0024 00000000 .word 0 + 2091 0028 00000000 .word USBD_DFU_GetCfgDesc + 2092 002c 00000000 .word USBD_DFU_GetCfgDesc + 2093 0030 00000000 .word USBD_DFU_GetCfgDesc + 2094 0034 00000000 .word USBD_DFU_GetDeviceQualifierDesc + 2095 0038 00000000 .word USBD_DFU_GetUsrStringDesc + 2096 .section .data.USBD_DFU_CfgDesc,"aw" + 2097 .align 2 + 2098 .set .LANCHOR0,. + 0 + 2101 USBD_DFU_CfgDesc: + 2102 0000 09021B00 .ascii "\011\002\033\000\001\001\002\3002\011\004\000\000\000" + 2102 010102C0 + 2102 32090400 + 2102 0000 + 2103 000e FE010206 .ascii "\376\001\002\006\011!\013\377\000\000\020\032\001" + 2103 09210BFF + 2103 0000101A + 2103 01 + 2104 .section .data.USBD_DFU_DeviceQualifierDesc,"aw" + 2105 .align 2 + 2106 .set .LANCHOR1,. + 0 + 2109 USBD_DFU_DeviceQualifierDesc: + 2110 0000 0A060002 .ascii "\012\006\000\002\000\000\000@\001\000" + 2110 00000040 + 2110 0100 + ARM GAS /tmp/ccyvpZhC.s page 120 + + + 2111 .text + 2112 .Letext0: + 2113 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h" + 2114 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h" + 2115 .file 6 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 2116 .file 7 "Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h" + 2117 .file 8 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h" + 2118 .file 9 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h" + 2119 .file 10 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h" + 2120 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" + 2121 .file 12 "/usr/arm-none-eabi/include/stdlib.h" + ARM GAS /tmp/ccyvpZhC.s page 121 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_dfu.c + /tmp/ccyvpZhC.s:17 .text.USBD_DFU_GetCfgDesc:0000000000000000 $t + /tmp/ccyvpZhC.s:24 .text.USBD_DFU_GetCfgDesc:0000000000000000 USBD_DFU_GetCfgDesc + /tmp/ccyvpZhC.s:46 .text.USBD_DFU_GetCfgDesc:0000000000000008 $d + /tmp/ccyvpZhC.s:51 .text.USBD_DFU_EP0_RxReady:0000000000000000 $t + /tmp/ccyvpZhC.s:57 .text.USBD_DFU_EP0_RxReady:0000000000000000 USBD_DFU_EP0_RxReady + /tmp/ccyvpZhC.s:76 .text.USBD_DFU_SOF:0000000000000000 $t + /tmp/ccyvpZhC.s:82 .text.USBD_DFU_SOF:0000000000000000 USBD_DFU_SOF + /tmp/ccyvpZhC.s:101 .text.USBD_DFU_GetDeviceQualifierDesc:0000000000000000 $t + /tmp/ccyvpZhC.s:107 .text.USBD_DFU_GetDeviceQualifierDesc:0000000000000000 USBD_DFU_GetDeviceQualifierDesc + /tmp/ccyvpZhC.s:128 .text.USBD_DFU_GetDeviceQualifierDesc:0000000000000008 $d + /tmp/ccyvpZhC.s:133 .text.DFU_ClearStatus:0000000000000000 $t + /tmp/ccyvpZhC.s:139 .text.DFU_ClearStatus:0000000000000000 DFU_ClearStatus + /tmp/ccyvpZhC.s:222 .text.DFU_Abort:0000000000000000 $t + /tmp/ccyvpZhC.s:228 .text.DFU_Abort:0000000000000000 DFU_Abort + /tmp/ccyvpZhC.s:300 .text.USBD_DFU_GetUsrStringDesc:0000000000000000 $t + /tmp/ccyvpZhC.s:306 .text.USBD_DFU_GetUsrStringDesc:0000000000000000 USBD_DFU_GetUsrStringDesc + /tmp/ccyvpZhC.s:357 .text.USBD_DFU_GetUsrStringDesc:000000000000001c $d + /tmp/ccyvpZhC.s:362 .text.DFU_Leave:0000000000000000 $t + /tmp/ccyvpZhC.s:368 .text.DFU_Leave:0000000000000000 DFU_Leave + /tmp/ccyvpZhC.s:506 .text.DFU_Leave:000000000000005c $d + /tmp/ccyvpZhC.s:515 .text.USBD_DFU_EP0_TxReady:0000000000000000 $t + /tmp/ccyvpZhC.s:521 .text.USBD_DFU_EP0_TxReady:0000000000000000 USBD_DFU_EP0_TxReady + /tmp/ccyvpZhC.s:765 .text.DFU_Upload:0000000000000000 $t + /tmp/ccyvpZhC.s:771 .text.DFU_Upload:0000000000000000 DFU_Upload + /tmp/ccyvpZhC.s:1011 .text.DFU_GetStatus:0000000000000000 $t + /tmp/ccyvpZhC.s:1017 .text.DFU_GetStatus:0000000000000000 DFU_GetStatus + /tmp/ccyvpZhC.s:1221 .text.DFU_GetStatus:00000000000000cc $d + /tmp/ccyvpZhC.s:1226 .text.DFU_GetState:0000000000000000 $t + /tmp/ccyvpZhC.s:1232 .text.DFU_GetState:0000000000000000 DFU_GetState + /tmp/ccyvpZhC.s:1262 .text.DFU_Download:0000000000000000 $t + /tmp/ccyvpZhC.s:1268 .text.DFU_Download:0000000000000000 DFU_Download + /tmp/ccyvpZhC.s:1386 .text.DFU_Detach:0000000000000000 $t + /tmp/ccyvpZhC.s:1392 .text.DFU_Detach:0000000000000000 DFU_Detach + /tmp/ccyvpZhC.s:1496 .text.DFU_Detach:000000000000005c $d + /tmp/ccyvpZhC.s:1501 .text.USBD_DFU_Setup:0000000000000000 $t + /tmp/ccyvpZhC.s:1507 .text.USBD_DFU_Setup:0000000000000000 USBD_DFU_Setup + /tmp/ccyvpZhC.s:1550 .text.USBD_DFU_Setup:0000000000000024 $d + /tmp/ccyvpZhC.s:1644 .text.USBD_DFU_Setup:0000000000000074 $d + /tmp/ccyvpZhC.s:1656 .text.USBD_DFU_Setup:0000000000000080 $t + /tmp/ccyvpZhC.s:1832 .text.USBD_DFU_Setup:0000000000000114 $d + /tmp/ccyvpZhC.s:1837 .text.USBD_DFU_DeInit:0000000000000000 $t + /tmp/ccyvpZhC.s:1843 .text.USBD_DFU_DeInit:0000000000000000 USBD_DFU_DeInit + /tmp/ccyvpZhC.s:1923 .text.USBD_DFU_Init:0000000000000000 $t + /tmp/ccyvpZhC.s:1929 .text.USBD_DFU_Init:0000000000000000 USBD_DFU_Init + /tmp/ccyvpZhC.s:2031 .text.USBD_DFU_RegisterMedia:0000000000000000 $t + /tmp/ccyvpZhC.s:2038 .text.USBD_DFU_RegisterMedia:0000000000000000 USBD_DFU_RegisterMedia + /tmp/ccyvpZhC.s:2080 .data.USBD_DFU:0000000000000000 USBD_DFU + /tmp/ccyvpZhC.s:2070 .bss.USBD_StrDesc.0:0000000000000000 $d + /tmp/ccyvpZhC.s:2074 .bss.USBD_StrDesc.0:0000000000000000 USBD_StrDesc.0 + /tmp/ccyvpZhC.s:2077 .data.USBD_DFU:0000000000000000 $d + /tmp/ccyvpZhC.s:2097 .data.USBD_DFU_CfgDesc:0000000000000000 $d + /tmp/ccyvpZhC.s:2101 .data.USBD_DFU_CfgDesc:0000000000000000 USBD_DFU_CfgDesc + /tmp/ccyvpZhC.s:2105 .data.USBD_DFU_DeviceQualifierDesc:0000000000000000 $d + /tmp/ccyvpZhC.s:2109 .data.USBD_DFU_DeviceQualifierDesc:0000000000000000 USBD_DFU_DeviceQualifierDesc + /tmp/ccyvpZhC.s:1557 .text.USBD_DFU_Setup:000000000000002b $d + ARM GAS /tmp/ccyvpZhC.s page 122 + + + /tmp/ccyvpZhC.s:1557 .text.USBD_DFU_Setup:000000000000002c $t + +UNDEFINED SYMBOLS +USBD_GetString +USBD_Stop +USBD_CtlError +USBD_CtlSendData +USBD_CtlPrepareRx +USBD_Start +HAL_Delay +free +malloc diff --git a/build/usbd_dfu.o b/build/usbd_dfu.o new file mode 100644 index 0000000..6659793 Binary files /dev/null and b/build/usbd_dfu.o differ diff --git a/build/usbd_dfu_if.d b/build/usbd_dfu_if.d new file mode 100644 index 0000000..9381ddb --- /dev/null +++ b/build/usbd_dfu_if.d @@ -0,0 +1,91 @@ +build/usbd_dfu_if.o: USB_DEVICE/App/usbd_dfu_if.c \ + USB_DEVICE/App/usbd_dfu_if.h \ + Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h \ + Core/Inc/w25_qspi.h Core/Inc/pin_config.h +USB_DEVICE/App/usbd_dfu_if.h: +Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: +Core/Inc/w25_qspi.h: +Core/Inc/pin_config.h: diff --git a/build/usbd_dfu_if.lst b/build/usbd_dfu_if.lst new file mode 100644 index 0000000..faf4f10 --- /dev/null +++ b/build/usbd_dfu_if.lst @@ -0,0 +1,900 @@ +ARM GAS /tmp/cc6jjrOm.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_dfu_if.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.MEM_If_DeInit_FS,"ax",%progbits + 17 .align 1 + 18 .arch armv7e-m + 19 .syntax unified + 20 .thumb + 21 .thumb_func + 22 .fpu fpv5-d16 + 24 MEM_If_DeInit_FS: + 25 .LFB146: + 26 .file 1 "USB_DEVICE/App/usbd_dfu_if.c" + 1:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN Header */ + 2:USB_DEVICE/App/usbd_dfu_if.c **** /** + 3:USB_DEVICE/App/usbd_dfu_if.c **** ****************************************************************************** + 4:USB_DEVICE/App/usbd_dfu_if.c **** * @file : usbd_dfu_if.c + 5:USB_DEVICE/App/usbd_dfu_if.c **** * @brief : Usb device for Download Firmware Update. + 6:USB_DEVICE/App/usbd_dfu_if.c **** ****************************************************************************** + 7:USB_DEVICE/App/usbd_dfu_if.c **** * @attention + 8:USB_DEVICE/App/usbd_dfu_if.c **** * + 9:USB_DEVICE/App/usbd_dfu_if.c **** *

© Copyright (c) 2019 STMicroelectronics. + 10:USB_DEVICE/App/usbd_dfu_if.c **** * All rights reserved.

+ 11:USB_DEVICE/App/usbd_dfu_if.c **** * + 12:USB_DEVICE/App/usbd_dfu_if.c **** * This software component is licensed by ST under Ultimate Liberty license + 13:USB_DEVICE/App/usbd_dfu_if.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 14:USB_DEVICE/App/usbd_dfu_if.c **** * the License. You may obtain a copy of the License at: + 15:USB_DEVICE/App/usbd_dfu_if.c **** * www.st.com/SLA0044 + 16:USB_DEVICE/App/usbd_dfu_if.c **** * + 17:USB_DEVICE/App/usbd_dfu_if.c **** ****************************************************************************** + 18:USB_DEVICE/App/usbd_dfu_if.c **** */ + 19:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END Header */ + 20:USB_DEVICE/App/usbd_dfu_if.c **** + 21:USB_DEVICE/App/usbd_dfu_if.c **** /* Includes ------------------------------------------------------------------*/ + 22:USB_DEVICE/App/usbd_dfu_if.c **** #include "usbd_dfu_if.h" + 23:USB_DEVICE/App/usbd_dfu_if.c **** + 24:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN INCLUDE */ + 25:USB_DEVICE/App/usbd_dfu_if.c **** + 26:USB_DEVICE/App/usbd_dfu_if.c **** #include "w25_qspi.h" + 27:USB_DEVICE/App/usbd_dfu_if.c **** #include "printf.h" + 28:USB_DEVICE/App/usbd_dfu_if.c **** #include "pin_config.h" + 29:USB_DEVICE/App/usbd_dfu_if.c **** + 30:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END INCLUDE */ + 31:USB_DEVICE/App/usbd_dfu_if.c **** + 32:USB_DEVICE/App/usbd_dfu_if.c **** /* Private typedef -----------------------------------------------------------*/ + ARM GAS /tmp/cc6jjrOm.s page 2 + + + 33:USB_DEVICE/App/usbd_dfu_if.c **** /* Private define ------------------------------------------------------------*/ + 34:USB_DEVICE/App/usbd_dfu_if.c **** /* Private macro -------------------------------------------------------------*/ + 35:USB_DEVICE/App/usbd_dfu_if.c **** + 36:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN PV */ + 37:USB_DEVICE/App/usbd_dfu_if.c **** /* Private variables ---------------------------------------------------------*/ + 38:USB_DEVICE/App/usbd_dfu_if.c **** + 39:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END PV */ + 40:USB_DEVICE/App/usbd_dfu_if.c **** + 41:USB_DEVICE/App/usbd_dfu_if.c **** /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + 42:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Usb device. + 43:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 44:USB_DEVICE/App/usbd_dfu_if.c **** */ + 45:USB_DEVICE/App/usbd_dfu_if.c **** + 46:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU + 47:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Usb DFU device module. + 48:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 49:USB_DEVICE/App/usbd_dfu_if.c **** */ + 50:USB_DEVICE/App/usbd_dfu_if.c **** + 51:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU_Private_TypesDefinitions + 52:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Private types. + 53:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 54:USB_DEVICE/App/usbd_dfu_if.c **** */ + 55:USB_DEVICE/App/usbd_dfu_if.c **** + 56:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN PRIVATE_TYPES */ + 57:USB_DEVICE/App/usbd_dfu_if.c **** + 58:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END PRIVATE_TYPES */ + 59:USB_DEVICE/App/usbd_dfu_if.c **** + 60:USB_DEVICE/App/usbd_dfu_if.c **** /** + 61:USB_DEVICE/App/usbd_dfu_if.c **** * @} + 62:USB_DEVICE/App/usbd_dfu_if.c **** */ + 63:USB_DEVICE/App/usbd_dfu_if.c **** + 64:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU_Private_Defines + 65:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Private defines. + 66:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 67:USB_DEVICE/App/usbd_dfu_if.c **** */ + 68:USB_DEVICE/App/usbd_dfu_if.c **** + 69:USB_DEVICE/App/usbd_dfu_if.c **** #define FLASH_DESC_STR "@QSPI Flash/0x90000000/4096*4Kg" + 70:USB_DEVICE/App/usbd_dfu_if.c **** + 71:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN PRIVATE_DEFINES */ + 72:USB_DEVICE/App/usbd_dfu_if.c **** + 73:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END PRIVATE_DEFINES */ + 74:USB_DEVICE/App/usbd_dfu_if.c **** + 75:USB_DEVICE/App/usbd_dfu_if.c **** /** + 76:USB_DEVICE/App/usbd_dfu_if.c **** * @} + 77:USB_DEVICE/App/usbd_dfu_if.c **** */ + 78:USB_DEVICE/App/usbd_dfu_if.c **** + 79:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU_Private_Macros + 80:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Private macros. + 81:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 82:USB_DEVICE/App/usbd_dfu_if.c **** */ + 83:USB_DEVICE/App/usbd_dfu_if.c **** + 84:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN PRIVATE_MACRO */ + 85:USB_DEVICE/App/usbd_dfu_if.c **** + 86:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END PRIVATE_MACRO */ + 87:USB_DEVICE/App/usbd_dfu_if.c **** + 88:USB_DEVICE/App/usbd_dfu_if.c **** /** + 89:USB_DEVICE/App/usbd_dfu_if.c **** * @} + ARM GAS /tmp/cc6jjrOm.s page 3 + + + 90:USB_DEVICE/App/usbd_dfu_if.c **** */ + 91:USB_DEVICE/App/usbd_dfu_if.c **** + 92:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU_Private_Variables + 93:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Private variables. + 94:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 95:USB_DEVICE/App/usbd_dfu_if.c **** */ + 96:USB_DEVICE/App/usbd_dfu_if.c **** + 97:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN PRIVATE_VARIABLES */ + 98:USB_DEVICE/App/usbd_dfu_if.c **** + 99:USB_DEVICE/App/usbd_dfu_if.c **** extern QSPI_HandleTypeDef hqspi; + 100:USB_DEVICE/App/usbd_dfu_if.c **** w25_qspi_t w25_flash; + 101:USB_DEVICE/App/usbd_dfu_if.c **** + 102:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END PRIVATE_VARIABLES */ + 103:USB_DEVICE/App/usbd_dfu_if.c **** + 104:USB_DEVICE/App/usbd_dfu_if.c **** /** + 105:USB_DEVICE/App/usbd_dfu_if.c **** * @} + 106:USB_DEVICE/App/usbd_dfu_if.c **** */ + 107:USB_DEVICE/App/usbd_dfu_if.c **** + 108:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU_Exported_Variables + 109:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Public variables. + 110:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 111:USB_DEVICE/App/usbd_dfu_if.c **** */ + 112:USB_DEVICE/App/usbd_dfu_if.c **** + 113:USB_DEVICE/App/usbd_dfu_if.c **** extern USBD_HandleTypeDef hUsbDeviceFS; + 114:USB_DEVICE/App/usbd_dfu_if.c **** + 115:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN EXPORTED_VARIABLES */ + 116:USB_DEVICE/App/usbd_dfu_if.c **** + 117:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END EXPORTED_VARIABLES */ + 118:USB_DEVICE/App/usbd_dfu_if.c **** + 119:USB_DEVICE/App/usbd_dfu_if.c **** /** + 120:USB_DEVICE/App/usbd_dfu_if.c **** * @} + 121:USB_DEVICE/App/usbd_dfu_if.c **** */ + 122:USB_DEVICE/App/usbd_dfu_if.c **** + 123:USB_DEVICE/App/usbd_dfu_if.c **** /** @defgroup USBD_DFU_Private_FunctionPrototypes + 124:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Private functions declaration. + 125:USB_DEVICE/App/usbd_dfu_if.c **** * @{ + 126:USB_DEVICE/App/usbd_dfu_if.c **** */ + 127:USB_DEVICE/App/usbd_dfu_if.c **** + 128:USB_DEVICE/App/usbd_dfu_if.c **** static uint16_t MEM_If_Init_FS(void); + 129:USB_DEVICE/App/usbd_dfu_if.c **** static uint16_t MEM_If_Erase_FS(uint32_t Add); + 130:USB_DEVICE/App/usbd_dfu_if.c **** static uint16_t MEM_If_Write_FS(uint8_t *src, uint8_t *dest, uint32_t Len); + 131:USB_DEVICE/App/usbd_dfu_if.c **** static uint8_t *MEM_If_Read_FS(uint8_t *src, uint8_t *dest, uint32_t Len); + 132:USB_DEVICE/App/usbd_dfu_if.c **** static uint16_t MEM_If_DeInit_FS(void); + 133:USB_DEVICE/App/usbd_dfu_if.c **** static uint16_t MEM_If_GetStatus_FS(uint32_t Add, uint8_t Cmd, uint8_t *buffer); + 134:USB_DEVICE/App/usbd_dfu_if.c **** + 135:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ + 136:USB_DEVICE/App/usbd_dfu_if.c **** + 137:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ + 138:USB_DEVICE/App/usbd_dfu_if.c **** + 139:USB_DEVICE/App/usbd_dfu_if.c **** /** + 140:USB_DEVICE/App/usbd_dfu_if.c **** * @} + 141:USB_DEVICE/App/usbd_dfu_if.c **** */ + 142:USB_DEVICE/App/usbd_dfu_if.c **** + 143:USB_DEVICE/App/usbd_dfu_if.c **** #if defined ( __ICCARM__ ) /* IAR Compiler */ + 144:USB_DEVICE/App/usbd_dfu_if.c **** #pragma data_alignment=4 + 145:USB_DEVICE/App/usbd_dfu_if.c **** #endif + 146:USB_DEVICE/App/usbd_dfu_if.c **** __ALIGN_BEGIN USBD_DFU_MediaTypeDef USBD_DFU_fops_FS __ALIGN_END = + ARM GAS /tmp/cc6jjrOm.s page 4 + + + 147:USB_DEVICE/App/usbd_dfu_if.c **** { + 148:USB_DEVICE/App/usbd_dfu_if.c **** (uint8_t*)FLASH_DESC_STR, + 149:USB_DEVICE/App/usbd_dfu_if.c **** MEM_If_Init_FS, + 150:USB_DEVICE/App/usbd_dfu_if.c **** MEM_If_DeInit_FS, + 151:USB_DEVICE/App/usbd_dfu_if.c **** MEM_If_Erase_FS, + 152:USB_DEVICE/App/usbd_dfu_if.c **** MEM_If_Write_FS, + 153:USB_DEVICE/App/usbd_dfu_if.c **** MEM_If_Read_FS, + 154:USB_DEVICE/App/usbd_dfu_if.c **** MEM_If_GetStatus_FS + 155:USB_DEVICE/App/usbd_dfu_if.c **** }; + 156:USB_DEVICE/App/usbd_dfu_if.c **** + 157:USB_DEVICE/App/usbd_dfu_if.c **** /* Private functions ---------------------------------------------------------*/ + 158:USB_DEVICE/App/usbd_dfu_if.c **** /** + 159:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Memory initialization routine. + 160:USB_DEVICE/App/usbd_dfu_if.c **** * @retval USBD_OK if operation is successful, MAL_FAIL else. + 161:USB_DEVICE/App/usbd_dfu_if.c **** */ + 162:USB_DEVICE/App/usbd_dfu_if.c **** uint16_t MEM_If_Init_FS(void) + 163:USB_DEVICE/App/usbd_dfu_if.c **** { + 164:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 0 */ + 165:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.interface = &hqspi; + 166:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.mode = W25_MODE_QUAD; + 167:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.address_size = W25_ADDRESS_24BITS; + 168:USB_DEVICE/App/usbd_dfu_if.c **** + 169:USB_DEVICE/App/usbd_dfu_if.c **** #if(USE_QPI_MODE == 1) + 170:USB_DEVICE/App/usbd_dfu_if.c **** W25_QPI_Mode(&w25_flash, 0); + 171:USB_DEVICE/App/usbd_dfu_if.c **** #endif // USE_QPI_MODE + 172:USB_DEVICE/App/usbd_dfu_if.c **** + 173:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Init(&w25_flash); + 174:USB_DEVICE/App/usbd_dfu_if.c **** printf("MEM_If_Init_FS: Mfg: 0x%x\r\n", w25_flash.manufacturer); + 175:USB_DEVICE/App/usbd_dfu_if.c **** return (USBD_OK); + 176:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 0 */ + 177:USB_DEVICE/App/usbd_dfu_if.c **** } + 178:USB_DEVICE/App/usbd_dfu_if.c **** + 179:USB_DEVICE/App/usbd_dfu_if.c **** /** + 180:USB_DEVICE/App/usbd_dfu_if.c **** * @brief De-Initializes Memory + 181:USB_DEVICE/App/usbd_dfu_if.c **** * @retval USBD_OK if operation is successful, MAL_FAIL else + 182:USB_DEVICE/App/usbd_dfu_if.c **** */ + 183:USB_DEVICE/App/usbd_dfu_if.c **** uint16_t MEM_If_DeInit_FS(void) + 184:USB_DEVICE/App/usbd_dfu_if.c **** { + 27 .loc 1 184 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 185:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 1 */ + 186:USB_DEVICE/App/usbd_dfu_if.c **** return (USBD_OK); + 32 .loc 1 186 3 view .LVU1 + 187:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 1 */ + 188:USB_DEVICE/App/usbd_dfu_if.c **** } + 33 .loc 1 188 1 is_stmt 0 view .LVU2 + 34 0000 0020 movs r0, #0 + 35 0002 7047 bx lr + 36 .cfi_endproc + 37 .LFE146: + 39 .section .text.MEM_If_GetStatus_FS,"ax",%progbits + 40 .align 1 + 41 .syntax unified + 42 .thumb + ARM GAS /tmp/cc6jjrOm.s page 5 + + + 43 .thumb_func + 44 .fpu fpv5-d16 + 46 MEM_If_GetStatus_FS: + 47 .LVL0: + 48 .LFB150: + 189:USB_DEVICE/App/usbd_dfu_if.c **** + 190:USB_DEVICE/App/usbd_dfu_if.c **** /** + 191:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Erase sector. + 192:USB_DEVICE/App/usbd_dfu_if.c **** * @param Add: Address of sector to be erased. + 193:USB_DEVICE/App/usbd_dfu_if.c **** * @retval 0 if operation is successful, MAL_FAIL else. + 194:USB_DEVICE/App/usbd_dfu_if.c **** */ + 195:USB_DEVICE/App/usbd_dfu_if.c **** uint16_t MEM_If_Erase_FS(uint32_t Add) + 196:USB_DEVICE/App/usbd_dfu_if.c **** { + 197:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 2 */ + 198:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Erase_FS: Add: 0x%08x\r\n", Add); + 199:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Erase_Sector(&w25_flash, Add - 0x90000000); + 200:USB_DEVICE/App/usbd_dfu_if.c **** //HAL_Delay(100); + 201:USB_DEVICE/App/usbd_dfu_if.c **** return (USBD_OK); + 202:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 2 */ + 203:USB_DEVICE/App/usbd_dfu_if.c **** } + 204:USB_DEVICE/App/usbd_dfu_if.c **** + 205:USB_DEVICE/App/usbd_dfu_if.c **** /** + 206:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Memory write routine. + 207:USB_DEVICE/App/usbd_dfu_if.c **** * @param src: Pointer to the source buffer. Address to be written to. + 208:USB_DEVICE/App/usbd_dfu_if.c **** * @param dest: Pointer to the destination buffer. + 209:USB_DEVICE/App/usbd_dfu_if.c **** * @param Len: Number of data to be written (in bytes). + 210:USB_DEVICE/App/usbd_dfu_if.c **** * @retval USBD_OK if operation is successful, MAL_FAIL else. + 211:USB_DEVICE/App/usbd_dfu_if.c **** */ + 212:USB_DEVICE/App/usbd_dfu_if.c **** uint16_t MEM_If_Write_FS(uint8_t *src, uint8_t *dest, uint32_t Len) + 213:USB_DEVICE/App/usbd_dfu_if.c **** { + 214:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 3 */ + 215:USB_DEVICE/App/usbd_dfu_if.c **** HAL_GPIO_TogglePin(LED_PORT, LED_PIN); + 216:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08x 1St: 0x%02x\r\n", (uint32_t)dest, (u + 217:USB_DEVICE/App/usbd_dfu_if.c **** uint8_t page_count = Len / 256; + 218:USB_DEVICE/App/usbd_dfu_if.c **** if(Len & 0xFFU) page_count++; + 219:USB_DEVICE/App/usbd_dfu_if.c **** for(uint8_t i = 0; i < page_count; i++) { + 220:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 221:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Pge: 0x%08x\r\n", page_addr); + 222:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Program_Page(&w25_flash, page_addr, &src[256 * i]); + 223:USB_DEVICE/App/usbd_dfu_if.c **** } + 224:USB_DEVICE/App/usbd_dfu_if.c **** //HAL_Delay(10); + 225:USB_DEVICE/App/usbd_dfu_if.c **** return (USBD_OK); + 226:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 3 */ + 227:USB_DEVICE/App/usbd_dfu_if.c **** } + 228:USB_DEVICE/App/usbd_dfu_if.c **** + 229:USB_DEVICE/App/usbd_dfu_if.c **** /** + 230:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Memory read routine. + 231:USB_DEVICE/App/usbd_dfu_if.c **** * @param src: Pointer to the source buffer. Address to be written to. + 232:USB_DEVICE/App/usbd_dfu_if.c **** * @param dest: Pointer to the destination buffer. + 233:USB_DEVICE/App/usbd_dfu_if.c **** * @param Len: Number of data to be read (in bytes). + 234:USB_DEVICE/App/usbd_dfu_if.c **** * @retval Pointer to the physical address where data should be read. + 235:USB_DEVICE/App/usbd_dfu_if.c **** */ + 236:USB_DEVICE/App/usbd_dfu_if.c **** uint8_t *MEM_If_Read_FS(uint8_t *src, uint8_t *dest, uint32_t Len) + 237:USB_DEVICE/App/usbd_dfu_if.c **** { + 238:USB_DEVICE/App/usbd_dfu_if.c **** /* Return a valid address to avoid HardFault */ + 239:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 4 */ + 240:USB_DEVICE/App/usbd_dfu_if.c **** HAL_GPIO_TogglePin(LED_PORT, LED_PIN); + ARM GAS /tmp/cc6jjrOm.s page 6 + + + 241:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Read_FS: Add: 0x%08x\r\n", (uint32_t)src); + 242:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Read(&w25_flash, (uint32_t)src - 0x90000000, dest, Len); + 243:USB_DEVICE/App/usbd_dfu_if.c **** //HAL_Delay(100); + 244:USB_DEVICE/App/usbd_dfu_if.c **** return (uint8_t*)(USBD_OK); + 245:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 4 */ + 246:USB_DEVICE/App/usbd_dfu_if.c **** } + 247:USB_DEVICE/App/usbd_dfu_if.c **** + 248:USB_DEVICE/App/usbd_dfu_if.c **** /** + 249:USB_DEVICE/App/usbd_dfu_if.c **** * @brief Get status routine + 250:USB_DEVICE/App/usbd_dfu_if.c **** * @param Add: Address to be read from + 251:USB_DEVICE/App/usbd_dfu_if.c **** * @param Cmd: Number of data to be read (in bytes) + 252:USB_DEVICE/App/usbd_dfu_if.c **** * @param buffer: used for returning the time necessary for a program or an erase operation + 253:USB_DEVICE/App/usbd_dfu_if.c **** * @retval USBD_OK if operation is successful + 254:USB_DEVICE/App/usbd_dfu_if.c **** */ + 255:USB_DEVICE/App/usbd_dfu_if.c **** uint16_t MEM_If_GetStatus_FS(uint32_t Add, uint8_t Cmd, uint8_t *buffer) + 256:USB_DEVICE/App/usbd_dfu_if.c **** { + 49 .loc 1 256 1 is_stmt 1 view -0 + 50 .cfi_startproc + 51 @ args = 0, pretend = 0, frame = 0 + 52 @ frame_needed = 0, uses_anonymous_args = 0 + 53 @ link register save eliminated. + 257:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 5 */ + 258:USB_DEVICE/App/usbd_dfu_if.c **** switch (Cmd) + 54 .loc 1 258 3 view .LVU4 + 55 0000 41B1 cbz r1, .L3 + 56 0002 0129 cmp r1, #1 + 57 0004 04D1 bne .L4 + 259:USB_DEVICE/App/usbd_dfu_if.c **** { + 260:USB_DEVICE/App/usbd_dfu_if.c **** case DFU_MEDIA_PROGRAM: + 261:USB_DEVICE/App/usbd_dfu_if.c **** buffer[2] = 0; + 58 .loc 1 261 9 view .LVU5 + 59 .loc 1 261 19 is_stmt 0 view .LVU6 + 60 0006 0023 movs r3, #0 + 61 0008 9370 strb r3, [r2, #2] + 262:USB_DEVICE/App/usbd_dfu_if.c **** buffer[1] = 0x0A; + 62 .loc 1 262 9 is_stmt 1 view .LVU7 + 63 .loc 1 262 19 is_stmt 0 view .LVU8 + 64 000a 0A21 movs r1, #10 + 65 .LVL1: + 66 .loc 1 262 19 view .LVU9 + 67 000c 5170 strb r1, [r2, #1] + 263:USB_DEVICE/App/usbd_dfu_if.c **** buffer[0] = 0; + 68 .loc 1 263 9 is_stmt 1 view .LVU10 + 69 .loc 1 263 19 is_stmt 0 view .LVU11 + 70 000e 1370 strb r3, [r2] + 264:USB_DEVICE/App/usbd_dfu_if.c **** break; + 71 .loc 1 264 5 is_stmt 1 view .LVU12 + 72 .L4: + 265:USB_DEVICE/App/usbd_dfu_if.c **** + 266:USB_DEVICE/App/usbd_dfu_if.c **** case DFU_MEDIA_ERASE: + 267:USB_DEVICE/App/usbd_dfu_if.c **** buffer[2] = 0; + 268:USB_DEVICE/App/usbd_dfu_if.c **** buffer[1] = 0x64; + 269:USB_DEVICE/App/usbd_dfu_if.c **** buffer[0] = 0; + 270:USB_DEVICE/App/usbd_dfu_if.c **** default: + 271:USB_DEVICE/App/usbd_dfu_if.c **** + 272:USB_DEVICE/App/usbd_dfu_if.c **** break; + 273:USB_DEVICE/App/usbd_dfu_if.c **** } + ARM GAS /tmp/cc6jjrOm.s page 7 + + + 274:USB_DEVICE/App/usbd_dfu_if.c **** return (USBD_OK); + 73 .loc 1 274 3 view .LVU13 + 275:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 5 */ + 276:USB_DEVICE/App/usbd_dfu_if.c **** } + 74 .loc 1 276 1 is_stmt 0 view .LVU14 + 75 0010 0020 movs r0, #0 + 76 .LVL2: + 77 .loc 1 276 1 view .LVU15 + 78 0012 7047 bx lr + 79 .LVL3: + 80 .L3: + 267:USB_DEVICE/App/usbd_dfu_if.c **** buffer[1] = 0x64; + 81 .loc 1 267 9 is_stmt 1 view .LVU16 + 267:USB_DEVICE/App/usbd_dfu_if.c **** buffer[1] = 0x64; + 82 .loc 1 267 19 is_stmt 0 view .LVU17 + 83 0014 0023 movs r3, #0 + 84 0016 9370 strb r3, [r2, #2] + 268:USB_DEVICE/App/usbd_dfu_if.c **** buffer[0] = 0; + 85 .loc 1 268 9 is_stmt 1 view .LVU18 + 268:USB_DEVICE/App/usbd_dfu_if.c **** buffer[0] = 0; + 86 .loc 1 268 19 is_stmt 0 view .LVU19 + 87 0018 6421 movs r1, #100 + 88 .LVL4: + 268:USB_DEVICE/App/usbd_dfu_if.c **** buffer[0] = 0; + 89 .loc 1 268 19 view .LVU20 + 90 001a 5170 strb r1, [r2, #1] + 269:USB_DEVICE/App/usbd_dfu_if.c **** default: + 91 .loc 1 269 9 is_stmt 1 view .LVU21 + 269:USB_DEVICE/App/usbd_dfu_if.c **** default: + 92 .loc 1 269 19 is_stmt 0 view .LVU22 + 93 001c 1370 strb r3, [r2] + 94 001e F7E7 b .L4 + 95 .cfi_endproc + 96 .LFE150: + 98 .section .rodata.MEM_If_Read_FS.str1.4,"aMS",%progbits,1 + 99 .align 2 + 100 .LC0: + 101 0000 4D656D5F .ascii "Mem_If_Read_FS: Add: 0x%08x\015\012\000" + 101 49665F52 + 101 6561645F + 101 46533A20 + 101 4164643A + 102 .section .text.MEM_If_Read_FS,"ax",%progbits + 103 .align 1 + 104 .syntax unified + 105 .thumb + 106 .thumb_func + 107 .fpu fpv5-d16 + 109 MEM_If_Read_FS: + 110 .LVL5: + 111 .LFB149: + 237:USB_DEVICE/App/usbd_dfu_if.c **** /* Return a valid address to avoid HardFault */ + 112 .loc 1 237 1 is_stmt 1 view -0 + 113 .cfi_startproc + 114 @ args = 0, pretend = 0, frame = 0 + 115 @ frame_needed = 0, uses_anonymous_args = 0 + 237:USB_DEVICE/App/usbd_dfu_if.c **** /* Return a valid address to avoid HardFault */ + ARM GAS /tmp/cc6jjrOm.s page 8 + + + 116 .loc 1 237 1 is_stmt 0 view .LVU24 + 117 0000 70B5 push {r4, r5, r6, lr} + 118 .LCFI0: + 119 .cfi_def_cfa_offset 16 + 120 .cfi_offset 4, -16 + 121 .cfi_offset 5, -12 + 122 .cfi_offset 6, -8 + 123 .cfi_offset 14, -4 + 124 0002 0446 mov r4, r0 + 125 0004 0D46 mov r5, r1 + 126 0006 1646 mov r6, r2 + 240:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Read_FS: Add: 0x%08x\r\n", (uint32_t)src); + 127 .loc 1 240 3 is_stmt 1 view .LVU25 + 128 0008 0221 movs r1, #2 + 129 .LVL6: + 240:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Read_FS: Add: 0x%08x\r\n", (uint32_t)src); + 130 .loc 1 240 3 is_stmt 0 view .LVU26 + 131 000a 0848 ldr r0, .L7 + 132 .LVL7: + 240:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Read_FS: Add: 0x%08x\r\n", (uint32_t)src); + 133 .loc 1 240 3 view .LVU27 + 134 000c FFF7FEFF bl HAL_GPIO_TogglePin + 135 .LVL8: + 241:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Read(&w25_flash, (uint32_t)src - 0x90000000, dest, Len); + 136 .loc 1 241 3 is_stmt 1 view .LVU28 + 137 0010 2146 mov r1, r4 + 138 0012 0748 ldr r0, .L7+4 + 139 0014 FFF7FEFF bl printf_ + 140 .LVL9: + 242:USB_DEVICE/App/usbd_dfu_if.c **** //HAL_Delay(100); + 141 .loc 1 242 3 view .LVU29 + 142 0018 3346 mov r3, r6 + 143 001a 2A46 mov r2, r5 + 144 001c 04F1E041 add r1, r4, #1879048192 + 145 0020 0448 ldr r0, .L7+8 + 146 0022 FFF7FEFF bl W25_QSPI_Read + 147 .LVL10: + 244:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 4 */ + 148 .loc 1 244 3 view .LVU30 + 246:USB_DEVICE/App/usbd_dfu_if.c **** + 149 .loc 1 246 1 is_stmt 0 view .LVU31 + 150 0026 0020 movs r0, #0 + 151 0028 70BD pop {r4, r5, r6, pc} + 152 .LVL11: + 153 .L8: + 246:USB_DEVICE/App/usbd_dfu_if.c **** + 154 .loc 1 246 1 view .LVU32 + 155 002a 00BF .align 2 + 156 .L7: + 157 002c 00000258 .word 1476526080 + 158 0030 00000000 .word .LC0 + 159 0034 00000000 .word .LANCHOR0 + 160 .cfi_endproc + 161 .LFE149: + 163 .section .rodata.MEM_If_Write_FS.str1.4,"aMS",%progbits,1 + 164 .align 2 + 165 .LC1: + ARM GAS /tmp/cc6jjrOm.s page 9 + + + 166 0000 4D656D5F .ascii "Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08" + 166 49665F57 + 166 72697465 + 166 5F46533A + 166 20416464 + 167 0033 78203153 .ascii "x 1St: 0x%02x\015\012\000" + 167 743A2030 + 167 78253032 + 167 780D0A00 + 168 0043 00 .align 2 + 169 .LC2: + 170 0044 4D656D5F .ascii "Mem_If_Write_FS: Pge: 0x%08x\015\012\000" + 170 49665F57 + 170 72697465 + 170 5F46533A + 170 20506765 + 171 .section .text.MEM_If_Write_FS,"ax",%progbits + 172 .align 1 + 173 .syntax unified + 174 .thumb + 175 .thumb_func + 176 .fpu fpv5-d16 + 178 MEM_If_Write_FS: + 179 .LVL12: + 180 .LFB148: + 213:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 3 */ + 181 .loc 1 213 1 is_stmt 1 view -0 + 182 .cfi_startproc + 183 @ args = 0, pretend = 0, frame = 0 + 184 @ frame_needed = 0, uses_anonymous_args = 0 + 213:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 3 */ + 185 .loc 1 213 1 is_stmt 0 view .LVU34 + 186 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 187 .LCFI1: + 188 .cfi_def_cfa_offset 28 + 189 .cfi_offset 4, -28 + 190 .cfi_offset 5, -24 + 191 .cfi_offset 6, -20 + 192 .cfi_offset 7, -16 + 193 .cfi_offset 8, -12 + 194 .cfi_offset 9, -8 + 195 .cfi_offset 14, -4 + 196 0004 83B0 sub sp, sp, #12 + 197 .LCFI2: + 198 .cfi_def_cfa_offset 40 + 199 0006 0746 mov r7, r0 + 200 0008 8946 mov r9, r1 + 201 000a 1446 mov r4, r2 + 215:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08x 1St: 0x%02x\r\n", (uint32_t)dest, (u + 202 .loc 1 215 3 is_stmt 1 view .LVU35 + 203 000c 0221 movs r1, #2 + 204 .LVL13: + 215:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08x 1St: 0x%02x\r\n", (uint32_t)dest, (u + 205 .loc 1 215 3 is_stmt 0 view .LVU36 + 206 000e 1648 ldr r0, .L14 + 207 .LVL14: + 215:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Add: 0x%08x Src: 0x%08x Len: 0x%08x 1St: 0x%02x\r\n", (uint32_t)dest, (u + ARM GAS /tmp/cc6jjrOm.s page 10 + + + 208 .loc 1 215 3 view .LVU37 + 209 0010 FFF7FEFF bl HAL_GPIO_TogglePin + 210 .LVL15: + 216:USB_DEVICE/App/usbd_dfu_if.c **** uint8_t page_count = Len / 256; + 211 .loc 1 216 3 is_stmt 1 view .LVU38 + 216:USB_DEVICE/App/usbd_dfu_if.c **** uint8_t page_count = Len / 256; + 212 .loc 1 216 121 is_stmt 0 view .LVU39 + 213 0014 3B78 ldrb r3, [r7] @ zero_extendqisi2 + 216:USB_DEVICE/App/usbd_dfu_if.c **** uint8_t page_count = Len / 256; + 214 .loc 1 216 3 view .LVU40 + 215 0016 0093 str r3, [sp] + 216 0018 2346 mov r3, r4 + 217 001a 3A46 mov r2, r7 + 218 001c 4946 mov r1, r9 + 219 001e 1348 ldr r0, .L14+4 + 220 0020 FFF7FEFF bl printf_ + 221 .LVL16: + 217:USB_DEVICE/App/usbd_dfu_if.c **** if(Len & 0xFFU) page_count++; + 222 .loc 1 217 3 is_stmt 1 view .LVU41 + 217:USB_DEVICE/App/usbd_dfu_if.c **** if(Len & 0xFFU) page_count++; + 223 .loc 1 217 11 is_stmt 0 view .LVU42 + 224 0024 C4F30728 ubfx r8, r4, #8, #8 + 225 .LVL17: + 218:USB_DEVICE/App/usbd_dfu_if.c **** for(uint8_t i = 0; i < page_count; i++) { + 226 .loc 1 218 3 is_stmt 1 view .LVU43 + 218:USB_DEVICE/App/usbd_dfu_if.c **** for(uint8_t i = 0; i < page_count; i++) { + 227 .loc 1 218 5 is_stmt 0 view .LVU44 + 228 0028 14F0FF0F tst r4, #255 + 229 002c 03D0 beq .L10 + 218:USB_DEVICE/App/usbd_dfu_if.c **** for(uint8_t i = 0; i < page_count; i++) { + 230 .loc 1 218 19 is_stmt 1 discriminator 1 view .LVU45 + 218:USB_DEVICE/App/usbd_dfu_if.c **** for(uint8_t i = 0; i < page_count; i++) { + 231 .loc 1 218 29 is_stmt 0 discriminator 1 view .LVU46 + 232 002e 08F10108 add r8, r8, #1 + 233 .LVL18: + 218:USB_DEVICE/App/usbd_dfu_if.c **** for(uint8_t i = 0; i < page_count; i++) { + 234 .loc 1 218 29 discriminator 1 view .LVU47 + 235 0032 5FFA88F8 uxtb r8, r8 + 236 .LVL19: + 237 .L10: + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 238 .loc 1 219 3 is_stmt 1 view .LVU48 + 239 .LBB2: + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 240 .loc 1 219 7 view .LVU49 + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 241 .loc 1 219 15 is_stmt 0 view .LVU50 + 242 0036 0024 movs r4, #0 + 243 .LVL20: + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 244 .loc 1 219 3 view .LVU51 + 245 0038 0FE0 b .L11 + 246 .LVL21: + 247 .L12: + 248 .LBB3: + 220:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Pge: 0x%08x\r\n", page_addr); + 249 .loc 1 220 7 is_stmt 1 discriminator 3 view .LVU52 + ARM GAS /tmp/cc6jjrOm.s page 11 + + + 220:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Pge: 0x%08x\r\n", page_addr); + 250 .loc 1 220 62 is_stmt 0 discriminator 3 view .LVU53 + 251 003a 2602 lsls r6, r4, #8 + 220:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Pge: 0x%08x\r\n", page_addr); + 252 .loc 1 220 56 discriminator 3 view .LVU54 + 253 003c 09EB0425 add r5, r9, r4, lsl #8 + 220:USB_DEVICE/App/usbd_dfu_if.c **** printf("Mem_If_Write_FS: Pge: 0x%08x\r\n", page_addr); + 254 .loc 1 220 16 discriminator 3 view .LVU55 + 255 0040 05F1E045 add r5, r5, #1879048192 + 256 .LVL22: + 221:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Program_Page(&w25_flash, page_addr, &src[256 * i]); + 257 .loc 1 221 7 is_stmt 1 discriminator 3 view .LVU56 + 258 0044 2946 mov r1, r5 + 259 0046 0A48 ldr r0, .L14+8 + 260 0048 FFF7FEFF bl printf_ + 261 .LVL23: + 222:USB_DEVICE/App/usbd_dfu_if.c **** } + 262 .loc 1 222 7 discriminator 3 view .LVU57 + 263 004c BA19 adds r2, r7, r6 + 264 004e 2946 mov r1, r5 + 265 0050 0848 ldr r0, .L14+12 + 266 0052 FFF7FEFF bl W25_QSPI_Program_Page + 267 .LVL24: + 268 .LBE3: + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 269 .loc 1 219 38 discriminator 3 view .LVU58 + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 270 .loc 1 219 39 is_stmt 0 discriminator 3 view .LVU59 + 271 0056 0134 adds r4, r4, #1 + 272 .LVL25: + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 273 .loc 1 219 39 discriminator 3 view .LVU60 + 274 0058 E4B2 uxtb r4, r4 + 275 .LVL26: + 276 .L11: + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 277 .loc 1 219 22 is_stmt 1 discriminator 1 view .LVU61 + 219:USB_DEVICE/App/usbd_dfu_if.c **** uint32_t page_addr = (uint32_t)dest - 0x90000000 + 256 * i; + 278 .loc 1 219 3 is_stmt 0 discriminator 1 view .LVU62 + 279 005a A045 cmp r8, r4 + 280 005c EDD8 bhi .L12 + 281 .LBE2: + 225:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 3 */ + 282 .loc 1 225 3 is_stmt 1 view .LVU63 + 227:USB_DEVICE/App/usbd_dfu_if.c **** + 283 .loc 1 227 1 is_stmt 0 view .LVU64 + 284 005e 0020 movs r0, #0 + 285 0060 03B0 add sp, sp, #12 + 286 .LCFI3: + 287 .cfi_def_cfa_offset 28 + 288 @ sp needed + 289 0062 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 290 .LVL27: + 291 .L15: + 227:USB_DEVICE/App/usbd_dfu_if.c **** + 292 .loc 1 227 1 view .LVU65 + 293 0066 00BF .align 2 + ARM GAS /tmp/cc6jjrOm.s page 12 + + + 294 .L14: + 295 0068 00000258 .word 1476526080 + 296 006c 00000000 .word .LC1 + 297 0070 44000000 .word .LC2 + 298 0074 00000000 .word .LANCHOR0 + 299 .cfi_endproc + 300 .LFE148: + 302 .section .rodata.MEM_If_Erase_FS.str1.4,"aMS",%progbits,1 + 303 .align 2 + 304 .LC3: + 305 0000 4D656D5F .ascii "Mem_If_Erase_FS: Add: 0x%08x\015\012\000" + 305 49665F45 + 305 72617365 + 305 5F46533A + 305 20416464 + 306 .section .text.MEM_If_Erase_FS,"ax",%progbits + 307 .align 1 + 308 .syntax unified + 309 .thumb + 310 .thumb_func + 311 .fpu fpv5-d16 + 313 MEM_If_Erase_FS: + 314 .LVL28: + 315 .LFB147: + 196:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 2 */ + 316 .loc 1 196 1 is_stmt 1 view -0 + 317 .cfi_startproc + 318 @ args = 0, pretend = 0, frame = 0 + 319 @ frame_needed = 0, uses_anonymous_args = 0 + 196:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 2 */ + 320 .loc 1 196 1 is_stmt 0 view .LVU67 + 321 0000 10B5 push {r4, lr} + 322 .LCFI4: + 323 .cfi_def_cfa_offset 8 + 324 .cfi_offset 4, -8 + 325 .cfi_offset 14, -4 + 326 0002 0446 mov r4, r0 + 198:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Erase_Sector(&w25_flash, Add - 0x90000000); + 327 .loc 1 198 3 is_stmt 1 view .LVU68 + 328 0004 0146 mov r1, r0 + 329 0006 0548 ldr r0, .L18 + 330 .LVL29: + 198:USB_DEVICE/App/usbd_dfu_if.c **** W25_QSPI_Erase_Sector(&w25_flash, Add - 0x90000000); + 331 .loc 1 198 3 is_stmt 0 view .LVU69 + 332 0008 FFF7FEFF bl printf_ + 333 .LVL30: + 199:USB_DEVICE/App/usbd_dfu_if.c **** //HAL_Delay(100); + 334 .loc 1 199 3 is_stmt 1 view .LVU70 + 335 000c 04F1E041 add r1, r4, #1879048192 + 336 0010 0348 ldr r0, .L18+4 + 337 0012 FFF7FEFF bl W25_QSPI_Erase_Sector + 338 .LVL31: + 201:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 2 */ + 339 .loc 1 201 3 view .LVU71 + 203:USB_DEVICE/App/usbd_dfu_if.c **** + 340 .loc 1 203 1 is_stmt 0 view .LVU72 + 341 0016 0020 movs r0, #0 + ARM GAS /tmp/cc6jjrOm.s page 13 + + + 342 0018 10BD pop {r4, pc} + 343 .LVL32: + 344 .L19: + 203:USB_DEVICE/App/usbd_dfu_if.c **** + 345 .loc 1 203 1 view .LVU73 + 346 001a 00BF .align 2 + 347 .L18: + 348 001c 00000000 .word .LC3 + 349 0020 00000000 .word .LANCHOR0 + 350 .cfi_endproc + 351 .LFE147: + 353 .section .rodata.MEM_If_Init_FS.str1.4,"aMS",%progbits,1 + 354 .align 2 + 355 .LC4: + 356 0000 4D454D5F .ascii "MEM_If_Init_FS: Mfg: 0x%x\015\012\000" + 356 49665F49 + 356 6E69745F + 356 46533A20 + 356 4D66673A + 357 .section .text.MEM_If_Init_FS,"ax",%progbits + 358 .align 1 + 359 .syntax unified + 360 .thumb + 361 .thumb_func + 362 .fpu fpv5-d16 + 364 MEM_If_Init_FS: + 365 .LFB145: + 163:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE BEGIN 0 */ + 366 .loc 1 163 1 is_stmt 1 view -0 + 367 .cfi_startproc + 368 @ args = 0, pretend = 0, frame = 0 + 369 @ frame_needed = 0, uses_anonymous_args = 0 + 370 0000 38B5 push {r3, r4, r5, lr} + 371 .LCFI5: + 372 .cfi_def_cfa_offset 16 + 373 .cfi_offset 3, -16 + 374 .cfi_offset 4, -12 + 375 .cfi_offset 5, -8 + 376 .cfi_offset 14, -4 + 165:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.mode = W25_MODE_QUAD; + 377 .loc 1 165 5 view .LVU75 + 165:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.mode = W25_MODE_QUAD; + 378 .loc 1 165 25 is_stmt 0 view .LVU76 + 379 0002 0A4C ldr r4, .L22 + 380 0004 0A4B ldr r3, .L22+4 + 381 0006 2360 str r3, [r4] + 166:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.address_size = W25_ADDRESS_24BITS; + 382 .loc 1 166 5 is_stmt 1 view .LVU77 + 166:USB_DEVICE/App/usbd_dfu_if.c **** w25_flash.address_size = W25_ADDRESS_24BITS; + 383 .loc 1 166 20 is_stmt 0 view .LVU78 + 384 0008 0223 movs r3, #2 + 385 000a 2371 strb r3, [r4, #4] + 167:USB_DEVICE/App/usbd_dfu_if.c **** + 386 .loc 1 167 5 is_stmt 1 view .LVU79 + 167:USB_DEVICE/App/usbd_dfu_if.c **** + 387 .loc 1 167 28 is_stmt 0 view .LVU80 + 388 000c 0025 movs r5, #0 + ARM GAS /tmp/cc6jjrOm.s page 14 + + + 389 000e 6571 strb r5, [r4, #5] + 170:USB_DEVICE/App/usbd_dfu_if.c **** #endif // USE_QPI_MODE + 390 .loc 1 170 5 is_stmt 1 view .LVU81 + 391 0010 2946 mov r1, r5 + 392 0012 2046 mov r0, r4 + 393 0014 FFF7FEFF bl W25_QPI_Mode + 394 .LVL33: + 173:USB_DEVICE/App/usbd_dfu_if.c **** printf("MEM_If_Init_FS: Mfg: 0x%x\r\n", w25_flash.manufacturer); + 395 .loc 1 173 5 view .LVU82 + 396 0018 2046 mov r0, r4 + 397 001a FFF7FEFF bl W25_QSPI_Init + 398 .LVL34: + 174:USB_DEVICE/App/usbd_dfu_if.c **** return (USBD_OK); + 399 .loc 1 174 5 view .LVU83 + 400 001e 217B ldrb r1, [r4, #12] @ zero_extendqisi2 + 401 0020 0448 ldr r0, .L22+8 + 402 0022 FFF7FEFF bl printf_ + 403 .LVL35: + 175:USB_DEVICE/App/usbd_dfu_if.c **** /* USER CODE END 0 */ + 404 .loc 1 175 3 view .LVU84 + 177:USB_DEVICE/App/usbd_dfu_if.c **** + 405 .loc 1 177 1 is_stmt 0 view .LVU85 + 406 0026 2846 mov r0, r5 + 407 0028 38BD pop {r3, r4, r5, pc} + 408 .L23: + 409 002a 00BF .align 2 + 410 .L22: + 411 002c 00000000 .word .LANCHOR0 + 412 0030 00000000 .word hqspi + 413 0034 00000000 .word .LC4 + 414 .cfi_endproc + 415 .LFE145: + 417 .global USBD_DFU_fops_FS + 418 .section .rodata.str1.4,"aMS",%progbits,1 + 419 .align 2 + 420 .LC5: + 421 0000 40515350 .ascii "@QSPI Flash/0x90000000/4096*4Kg\000" + 421 4920466C + 421 6173682F + 421 30783930 + 421 30303030 + 422 .global w25_flash + 423 .section .bss.w25_flash,"aw",%nobits + 424 .align 2 + 425 .set .LANCHOR0,. + 0 + 428 w25_flash: + 429 0000 00000000 .space 16 + 429 00000000 + 429 00000000 + 429 00000000 + 430 .section .data.USBD_DFU_fops_FS,"aw" + 431 .align 2 + 434 USBD_DFU_fops_FS: + 435 0000 00000000 .word .LC5 + 436 0004 00000000 .word MEM_If_Init_FS + 437 0008 00000000 .word MEM_If_DeInit_FS + 438 000c 00000000 .word MEM_If_Erase_FS + ARM GAS /tmp/cc6jjrOm.s page 15 + + + 439 0010 00000000 .word MEM_If_Write_FS + 440 0014 00000000 .word MEM_If_Read_FS + 441 0018 00000000 .word MEM_If_GetStatus_FS + 442 .text + 443 .Letext0: + 444 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 445 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 446 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 447 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 448 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 449 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" + 450 .file 8 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 451 .file 9 "Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h" + 452 .file 10 "Core/Inc/w25_qspi.h" + 453 .file 11 "USB_DEVICE/App/usbd_dfu_if.h" + 454 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" + 455 .file 13 "Core/Inc/printf.h" + ARM GAS /tmp/cc6jjrOm.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_dfu_if.c + /tmp/cc6jjrOm.s:17 .text.MEM_If_DeInit_FS:0000000000000000 $t + /tmp/cc6jjrOm.s:24 .text.MEM_If_DeInit_FS:0000000000000000 MEM_If_DeInit_FS + /tmp/cc6jjrOm.s:40 .text.MEM_If_GetStatus_FS:0000000000000000 $t + /tmp/cc6jjrOm.s:46 .text.MEM_If_GetStatus_FS:0000000000000000 MEM_If_GetStatus_FS + /tmp/cc6jjrOm.s:99 .rodata.MEM_If_Read_FS.str1.4:0000000000000000 $d + /tmp/cc6jjrOm.s:103 .text.MEM_If_Read_FS:0000000000000000 $t + /tmp/cc6jjrOm.s:109 .text.MEM_If_Read_FS:0000000000000000 MEM_If_Read_FS + /tmp/cc6jjrOm.s:157 .text.MEM_If_Read_FS:000000000000002c $d + /tmp/cc6jjrOm.s:164 .rodata.MEM_If_Write_FS.str1.4:0000000000000000 $d + /tmp/cc6jjrOm.s:172 .text.MEM_If_Write_FS:0000000000000000 $t + /tmp/cc6jjrOm.s:178 .text.MEM_If_Write_FS:0000000000000000 MEM_If_Write_FS + /tmp/cc6jjrOm.s:295 .text.MEM_If_Write_FS:0000000000000068 $d + /tmp/cc6jjrOm.s:303 .rodata.MEM_If_Erase_FS.str1.4:0000000000000000 $d + /tmp/cc6jjrOm.s:307 .text.MEM_If_Erase_FS:0000000000000000 $t + /tmp/cc6jjrOm.s:313 .text.MEM_If_Erase_FS:0000000000000000 MEM_If_Erase_FS + /tmp/cc6jjrOm.s:348 .text.MEM_If_Erase_FS:000000000000001c $d + /tmp/cc6jjrOm.s:354 .rodata.MEM_If_Init_FS.str1.4:0000000000000000 $d + /tmp/cc6jjrOm.s:358 .text.MEM_If_Init_FS:0000000000000000 $t + /tmp/cc6jjrOm.s:364 .text.MEM_If_Init_FS:0000000000000000 MEM_If_Init_FS + /tmp/cc6jjrOm.s:411 .text.MEM_If_Init_FS:000000000000002c $d + /tmp/cc6jjrOm.s:434 .data.USBD_DFU_fops_FS:0000000000000000 USBD_DFU_fops_FS + /tmp/cc6jjrOm.s:419 .rodata.str1.4:0000000000000000 $d + /tmp/cc6jjrOm.s:428 .bss.w25_flash:0000000000000000 w25_flash + /tmp/cc6jjrOm.s:424 .bss.w25_flash:0000000000000000 $d + /tmp/cc6jjrOm.s:431 .data.USBD_DFU_fops_FS:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_TogglePin +printf_ +W25_QSPI_Read +W25_QSPI_Program_Page +W25_QSPI_Erase_Sector +W25_QPI_Mode +W25_QSPI_Init +hqspi diff --git a/build/usbd_dfu_if.o b/build/usbd_dfu_if.o new file mode 100644 index 0000000..82ffb26 Binary files /dev/null and b/build/usbd_dfu_if.o differ diff --git a/build/usbd_ioreq.d b/build/usbd_ioreq.d new file mode 100644 index 0000000..6ebbc07 --- /dev/null +++ b/build/usbd_ioreq.d @@ -0,0 +1,85 @@ +build/usbd_ioreq.o: \ + Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h \ + USB_DEVICE/Target/usbd_conf.h Core/Inc/main.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/pin_config.h Core/Inc/flash_config.h Core/Inc/printf.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h \ + Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h: +USB_DEVICE/Target/usbd_conf.h: +Core/Inc/main.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/pin_config.h: +Core/Inc/flash_config.h: +Core/Inc/printf.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h: +Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h: diff --git a/build/usbd_ioreq.lst b/build/usbd_ioreq.lst new file mode 100644 index 0000000..ad108c3 --- /dev/null +++ b/build/usbd_ioreq.lst @@ -0,0 +1,544 @@ +ARM GAS /tmp/cclxsWls.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "usbd_ioreq.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text.USBD_CtlSendData,"ax",%progbits + 17 .align 1 + 18 .global USBD_CtlSendData + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 USBD_CtlSendData: + 26 .LVL0: + 27 .LFB145: + 28 .file 1 "Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c" + 1:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 2:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** ****************************************************************************** + 3:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @file usbd_ioreq.c + 4:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @author MCD Application Team + 5:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief This file provides the IO requests APIs for control endpoints. + 6:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** ****************************************************************************** + 7:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @attention + 8:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * + 9:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** *

© Copyright (c) 2015 STMicroelectronics. + 10:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * All rights reserved.

+ 11:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * + 12:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * This software component is licensed by ST under Ultimate Liberty license + 13:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * SLA0044, the "License"; You may not use this file except in compliance with + 14:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * the License. You may obtain a copy of the License at: + 15:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * www.st.com/SLA0044 + 16:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * + 17:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** ****************************************************************************** + 18:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 19:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 20:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Includes ------------------------------------------------------------------*/ + 21:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** #include "usbd_ioreq.h" + 22:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 23:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @addtogroup STM32_USB_DEVICE_LIBRARY + 24:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 25:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 26:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 27:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 28:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ + 29:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief control I/O requests module + 30:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + ARM GAS /tmp/cclxsWls.s page 2 + + + 31:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 32:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 33:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_TypesDefinitions + 34:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 35:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 36:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 37:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @} + 38:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 39:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 40:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 41:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Defines + 42:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 43:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 44:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 45:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 46:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @} + 47:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 48:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 49:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 50:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Macros + 51:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 52:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 53:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 54:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @} + 55:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 56:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 57:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 58:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Variables + 59:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 60:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 61:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 62:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 63:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @} + 64:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 65:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 66:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 67:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_FunctionPrototypes + 68:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 69:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 70:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 71:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @} + 72:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 73:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 74:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 75:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** @defgroup USBD_IOREQ_Private_Functions + 76:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @{ + 77:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 78:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 79:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 80:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_CtlSendData + 81:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * send data on the ctl pipe + 82:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 83:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param buff: pointer to data buffer + 84:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param len: length of data to be sent + 85:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval status + 86:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 87:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + ARM GAS /tmp/cclxsWls.s page 3 + + + 88:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** uint8_t *pbuf, uint32_t len) + 89:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 29 .loc 1 89 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 89 1 is_stmt 0 view .LVU1 + 34 0000 08B5 push {r3, lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 3, -8 + 38 .cfi_offset 14, -4 + 39 0002 1346 mov r3, r2 + 90:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Set EP0 State */ + 91:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep0_state = USBD_EP0_DATA_IN; + 40 .loc 1 91 3 is_stmt 1 view .LVU2 + 41 .loc 1 91 19 is_stmt 0 view .LVU3 + 42 0004 0222 movs r2, #2 + 43 .LVL1: + 44 .loc 1 91 19 view .LVU4 + 45 0006 C0F89422 str r2, [r0, #660] + 92:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep_in[0].total_length = len; + 46 .loc 1 92 3 is_stmt 1 view .LVU5 + 47 .loc 1 92 31 is_stmt 0 view .LVU6 + 48 000a 8361 str r3, [r0, #24] + 93:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep_in[0].rem_length = len; + 49 .loc 1 93 3 is_stmt 1 view .LVU7 + 50 .loc 1 93 29 is_stmt 0 view .LVU8 + 51 000c C361 str r3, [r0, #28] + 94:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 95:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Start the transfer */ + 96:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + 52 .loc 1 96 3 is_stmt 1 view .LVU9 + 53 .loc 1 96 9 is_stmt 0 view .LVU10 + 54 000e 0A46 mov r2, r1 + 55 0010 0021 movs r1, #0 + 56 .LVL2: + 57 .loc 1 96 9 view .LVU11 + 58 0012 FFF7FEFF bl USBD_LL_Transmit + 59 .LVL3: + 97:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 98:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_OK; + 60 .loc 1 98 3 is_stmt 1 view .LVU12 + 99:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 61 .loc 1 99 1 is_stmt 0 view .LVU13 + 62 0016 0020 movs r0, #0 + 63 0018 08BD pop {r3, pc} + 64 .cfi_endproc + 65 .LFE145: + 67 .section .text.USBD_CtlContinueSendData,"ax",%progbits + 68 .align 1 + 69 .global USBD_CtlContinueSendData + 70 .syntax unified + 71 .thumb + 72 .thumb_func + 73 .fpu fpv5-d16 + 75 USBD_CtlContinueSendData: + ARM GAS /tmp/cclxsWls.s page 4 + + + 76 .LVL4: + 77 .LFB146: + 100:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 101:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 102:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_CtlContinueSendData + 103:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * continue sending data on the ctl pipe + 104:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 105:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param buff: pointer to data buffer + 106:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param len: length of data to be sent + 107:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval status + 108:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 109:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + 110:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** uint8_t *pbuf, uint32_t len) + 111:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 78 .loc 1 111 1 is_stmt 1 view -0 + 79 .cfi_startproc + 80 @ args = 0, pretend = 0, frame = 0 + 81 @ frame_needed = 0, uses_anonymous_args = 0 + 82 .loc 1 111 1 is_stmt 0 view .LVU15 + 83 0000 08B5 push {r3, lr} + 84 .LCFI1: + 85 .cfi_def_cfa_offset 8 + 86 .cfi_offset 3, -8 + 87 .cfi_offset 14, -4 + 88 0002 1346 mov r3, r2 + 112:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Start the next transfer */ + 113:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + 89 .loc 1 113 3 is_stmt 1 view .LVU16 + 90 .loc 1 113 9 is_stmt 0 view .LVU17 + 91 0004 0A46 mov r2, r1 + 92 .LVL5: + 93 .loc 1 113 9 view .LVU18 + 94 0006 0021 movs r1, #0 + 95 .LVL6: + 96 .loc 1 113 9 view .LVU19 + 97 0008 FFF7FEFF bl USBD_LL_Transmit + 98 .LVL7: + 114:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 115:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_OK; + 99 .loc 1 115 3 is_stmt 1 view .LVU20 + 116:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 100 .loc 1 116 1 is_stmt 0 view .LVU21 + 101 000c 0020 movs r0, #0 + 102 000e 08BD pop {r3, pc} + 103 .cfi_endproc + 104 .LFE146: + 106 .section .text.USBD_CtlPrepareRx,"ax",%progbits + 107 .align 1 + 108 .global USBD_CtlPrepareRx + 109 .syntax unified + 110 .thumb + 111 .thumb_func + 112 .fpu fpv5-d16 + 114 USBD_CtlPrepareRx: + 115 .LVL8: + 116 .LFB147: + 117:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + ARM GAS /tmp/cclxsWls.s page 5 + + + 118:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 119:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_CtlPrepareRx + 120:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * receive data on the ctl pipe + 121:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 122:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param buff: pointer to data buffer + 123:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param len: length of data to be received + 124:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval status + 125:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 126:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + 127:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** uint8_t *pbuf, uint32_t len) + 128:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 117 .loc 1 128 1 is_stmt 1 view -0 + 118 .cfi_startproc + 119 @ args = 0, pretend = 0, frame = 0 + 120 @ frame_needed = 0, uses_anonymous_args = 0 + 121 .loc 1 128 1 is_stmt 0 view .LVU23 + 122 0000 08B5 push {r3, lr} + 123 .LCFI2: + 124 .cfi_def_cfa_offset 8 + 125 .cfi_offset 3, -8 + 126 .cfi_offset 14, -4 + 127 0002 1346 mov r3, r2 + 129:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Set EP0 State */ + 130:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep0_state = USBD_EP0_DATA_OUT; + 128 .loc 1 130 3 is_stmt 1 view .LVU24 + 129 .loc 1 130 19 is_stmt 0 view .LVU25 + 130 0004 0322 movs r2, #3 + 131 .LVL9: + 132 .loc 1 130 19 view .LVU26 + 133 0006 C0F89422 str r2, [r0, #660] + 131:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep_out[0].total_length = len; + 134 .loc 1 131 3 is_stmt 1 view .LVU27 + 135 .loc 1 131 32 is_stmt 0 view .LVU28 + 136 000a C0F85831 str r3, [r0, #344] + 132:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep_out[0].rem_length = len; + 137 .loc 1 132 3 is_stmt 1 view .LVU29 + 138 .loc 1 132 30 is_stmt 0 view .LVU30 + 139 000e C0F85C31 str r3, [r0, #348] + 133:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 134:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Start the transfer */ + 135:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + 140 .loc 1 135 3 is_stmt 1 view .LVU31 + 141 .loc 1 135 9 is_stmt 0 view .LVU32 + 142 0012 0A46 mov r2, r1 + 143 0014 0021 movs r1, #0 + 144 .LVL10: + 145 .loc 1 135 9 view .LVU33 + 146 0016 FFF7FEFF bl USBD_LL_PrepareReceive + 147 .LVL11: + 136:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 137:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_OK; + 148 .loc 1 137 3 is_stmt 1 view .LVU34 + 138:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 149 .loc 1 138 1 is_stmt 0 view .LVU35 + 150 001a 0020 movs r0, #0 + 151 001c 08BD pop {r3, pc} + 152 .cfi_endproc + ARM GAS /tmp/cclxsWls.s page 6 + + + 153 .LFE147: + 155 .section .text.USBD_CtlContinueRx,"ax",%progbits + 156 .align 1 + 157 .global USBD_CtlContinueRx + 158 .syntax unified + 159 .thumb + 160 .thumb_func + 161 .fpu fpv5-d16 + 163 USBD_CtlContinueRx: + 164 .LVL12: + 165 .LFB148: + 139:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 140:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 141:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_CtlContinueRx + 142:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * continue receive data on the ctl pipe + 143:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 144:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param buff: pointer to data buffer + 145:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param len: length of data to be received + 146:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval status + 147:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 148:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + 149:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** uint8_t *pbuf, uint32_t len) + 150:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 166 .loc 1 150 1 is_stmt 1 view -0 + 167 .cfi_startproc + 168 @ args = 0, pretend = 0, frame = 0 + 169 @ frame_needed = 0, uses_anonymous_args = 0 + 170 .loc 1 150 1 is_stmt 0 view .LVU37 + 171 0000 08B5 push {r3, lr} + 172 .LCFI3: + 173 .cfi_def_cfa_offset 8 + 174 .cfi_offset 3, -8 + 175 .cfi_offset 14, -4 + 176 0002 1346 mov r3, r2 + 151:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + 177 .loc 1 151 3 is_stmt 1 view .LVU38 + 178 .loc 1 151 9 is_stmt 0 view .LVU39 + 179 0004 0A46 mov r2, r1 + 180 .LVL13: + 181 .loc 1 151 9 view .LVU40 + 182 0006 0021 movs r1, #0 + 183 .LVL14: + 184 .loc 1 151 9 view .LVU41 + 185 0008 FFF7FEFF bl USBD_LL_PrepareReceive + 186 .LVL15: + 152:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 153:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_OK; + 187 .loc 1 153 3 is_stmt 1 view .LVU42 + 154:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 188 .loc 1 154 1 is_stmt 0 view .LVU43 + 189 000c 0020 movs r0, #0 + 190 000e 08BD pop {r3, pc} + 191 .cfi_endproc + 192 .LFE148: + 194 .section .text.USBD_CtlSendStatus,"ax",%progbits + 195 .align 1 + 196 .global USBD_CtlSendStatus + ARM GAS /tmp/cclxsWls.s page 7 + + + 197 .syntax unified + 198 .thumb + 199 .thumb_func + 200 .fpu fpv5-d16 + 202 USBD_CtlSendStatus: + 203 .LVL16: + 204 .LFB149: + 155:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 156:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 157:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_CtlSendStatus + 158:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * send zero lzngth packet on the ctl pipe + 159:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 160:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval status + 161:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 162:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) + 163:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 205 .loc 1 163 1 is_stmt 1 view -0 + 206 .cfi_startproc + 207 @ args = 0, pretend = 0, frame = 0 + 208 @ frame_needed = 0, uses_anonymous_args = 0 + 209 .loc 1 163 1 is_stmt 0 view .LVU45 + 210 0000 08B5 push {r3, lr} + 211 .LCFI4: + 212 .cfi_def_cfa_offset 8 + 213 .cfi_offset 3, -8 + 214 .cfi_offset 14, -4 + 164:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Set EP0 State */ + 165:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep0_state = USBD_EP0_STATUS_IN; + 215 .loc 1 165 3 is_stmt 1 view .LVU46 + 216 .loc 1 165 19 is_stmt 0 view .LVU47 + 217 0002 0423 movs r3, #4 + 218 0004 C0F89432 str r3, [r0, #660] + 166:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 167:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Start the transfer */ + 168:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); + 219 .loc 1 168 3 is_stmt 1 view .LVU48 + 220 .loc 1 168 9 is_stmt 0 view .LVU49 + 221 0008 0023 movs r3, #0 + 222 000a 1A46 mov r2, r3 + 223 000c 1946 mov r1, r3 + 224 000e FFF7FEFF bl USBD_LL_Transmit + 225 .LVL17: + 169:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 170:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_OK; + 226 .loc 1 170 3 is_stmt 1 view .LVU50 + 171:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 227 .loc 1 171 1 is_stmt 0 view .LVU51 + 228 0012 0020 movs r0, #0 + 229 0014 08BD pop {r3, pc} + 230 .cfi_endproc + 231 .LFE149: + 233 .section .text.USBD_CtlReceiveStatus,"ax",%progbits + 234 .align 1 + 235 .global USBD_CtlReceiveStatus + 236 .syntax unified + 237 .thumb + 238 .thumb_func + ARM GAS /tmp/cclxsWls.s page 8 + + + 239 .fpu fpv5-d16 + 241 USBD_CtlReceiveStatus: + 242 .LVL18: + 243 .LFB150: + 172:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 173:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 174:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_CtlReceiveStatus + 175:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * receive zero lzngth packet on the ctl pipe + 176:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 177:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval status + 178:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 179:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) + 180:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 244 .loc 1 180 1 is_stmt 1 view -0 + 245 .cfi_startproc + 246 @ args = 0, pretend = 0, frame = 0 + 247 @ frame_needed = 0, uses_anonymous_args = 0 + 248 .loc 1 180 1 is_stmt 0 view .LVU53 + 249 0000 08B5 push {r3, lr} + 250 .LCFI5: + 251 .cfi_def_cfa_offset 8 + 252 .cfi_offset 3, -8 + 253 .cfi_offset 14, -4 + 181:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Set EP0 State */ + 182:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** pdev->ep0_state = USBD_EP0_STATUS_OUT; + 254 .loc 1 182 3 is_stmt 1 view .LVU54 + 255 .loc 1 182 19 is_stmt 0 view .LVU55 + 256 0002 0523 movs r3, #5 + 257 0004 C0F89432 str r3, [r0, #660] + 183:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 184:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /* Start the transfer */ + 185:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + 258 .loc 1 185 3 is_stmt 1 view .LVU56 + 259 .loc 1 185 9 is_stmt 0 view .LVU57 + 260 0008 0023 movs r3, #0 + 261 000a 1A46 mov r2, r3 + 262 000c 1946 mov r1, r3 + 263 000e FFF7FEFF bl USBD_LL_PrepareReceive + 264 .LVL19: + 186:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 187:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_OK; + 265 .loc 1 187 3 is_stmt 1 view .LVU58 + 188:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 266 .loc 1 188 1 is_stmt 0 view .LVU59 + 267 0012 0020 movs r0, #0 + 268 0014 08BD pop {r3, pc} + 269 .cfi_endproc + 270 .LFE150: + 272 .section .text.USBD_GetRxCount,"ax",%progbits + 273 .align 1 + 274 .global USBD_GetRxCount + 275 .syntax unified + 276 .thumb + 277 .thumb_func + 278 .fpu fpv5-d16 + 280 USBD_GetRxCount: + 281 .LVL20: + ARM GAS /tmp/cclxsWls.s page 9 + + + 282 .LFB151: + 189:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** + 190:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** /** + 191:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @brief USBD_GetRxCount + 192:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * returns the received data length + 193:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param pdev: device instance + 194:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @param ep_addr: endpoint address + 195:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** * @retval Rx Data blength + 196:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** */ + 197:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr) + 198:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** { + 283 .loc 1 198 1 is_stmt 1 view -0 + 284 .cfi_startproc + 285 @ args = 0, pretend = 0, frame = 0 + 286 @ frame_needed = 0, uses_anonymous_args = 0 + 287 .loc 1 198 1 is_stmt 0 view .LVU61 + 288 0000 08B5 push {r3, lr} + 289 .LCFI6: + 290 .cfi_def_cfa_offset 8 + 291 .cfi_offset 3, -8 + 292 .cfi_offset 14, -4 + 199:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** return USBD_LL_GetRxDataSize(pdev, ep_addr); + 293 .loc 1 199 3 is_stmt 1 view .LVU62 + 294 .loc 1 199 10 is_stmt 0 view .LVU63 + 295 0002 FFF7FEFF bl USBD_LL_GetRxDataSize + 296 .LVL21: + 200:Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c **** } + 297 .loc 1 200 1 view .LVU64 + 298 0006 08BD pop {r3, pc} + 299 .cfi_endproc + 300 .LFE151: + 302 .text + 303 .Letext0: + 304 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 305 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 306 .file 4 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h" + 307 .file 5 "Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h" + ARM GAS /tmp/cclxsWls.s page 10 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 usbd_ioreq.c + /tmp/cclxsWls.s:17 .text.USBD_CtlSendData:0000000000000000 $t + /tmp/cclxsWls.s:25 .text.USBD_CtlSendData:0000000000000000 USBD_CtlSendData + /tmp/cclxsWls.s:68 .text.USBD_CtlContinueSendData:0000000000000000 $t + /tmp/cclxsWls.s:75 .text.USBD_CtlContinueSendData:0000000000000000 USBD_CtlContinueSendData + /tmp/cclxsWls.s:107 .text.USBD_CtlPrepareRx:0000000000000000 $t + /tmp/cclxsWls.s:114 .text.USBD_CtlPrepareRx:0000000000000000 USBD_CtlPrepareRx + /tmp/cclxsWls.s:156 .text.USBD_CtlContinueRx:0000000000000000 $t + /tmp/cclxsWls.s:163 .text.USBD_CtlContinueRx:0000000000000000 USBD_CtlContinueRx + /tmp/cclxsWls.s:195 .text.USBD_CtlSendStatus:0000000000000000 $t + /tmp/cclxsWls.s:202 .text.USBD_CtlSendStatus:0000000000000000 USBD_CtlSendStatus + /tmp/cclxsWls.s:234 .text.USBD_CtlReceiveStatus:0000000000000000 $t + /tmp/cclxsWls.s:241 .text.USBD_CtlReceiveStatus:0000000000000000 USBD_CtlReceiveStatus + /tmp/cclxsWls.s:273 .text.USBD_GetRxCount:0000000000000000 $t + /tmp/cclxsWls.s:280 .text.USBD_GetRxCount:0000000000000000 USBD_GetRxCount + +UNDEFINED SYMBOLS +USBD_LL_Transmit +USBD_LL_PrepareReceive +USBD_LL_GetRxDataSize diff --git a/build/usbd_ioreq.o b/build/usbd_ioreq.o new file mode 100644 index 0000000..5969991 Binary files /dev/null and b/build/usbd_ioreq.o differ diff --git a/build/w25_qspi.d b/build/w25_qspi.d new file mode 100644 index 0000000..18dc55d --- /dev/null +++ b/build/w25_qspi.d @@ -0,0 +1,69 @@ +build/w25_qspi.o: Core/Src/w25_qspi.c \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + Core/Inc/stm32h7xx_hal_conf.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h \ + Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h \ + Core/Inc/w25_qspi.h +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +Core/Inc/stm32h7xx_hal_conf.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h: +Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h: +Core/Inc/w25_qspi.h: diff --git a/build/w25_qspi.lst b/build/w25_qspi.lst new file mode 100644 index 0000000..1d034de --- /dev/null +++ b/build/w25_qspi.lst @@ -0,0 +1,1676 @@ +ARM GAS /tmp/cc77UdtT.s page 1 + + + 1 .cpu cortex-m7 + 2 .eabi_attribute 28, 1 + 3 .eabi_attribute 20, 1 + 4 .eabi_attribute 21, 1 + 5 .eabi_attribute 23, 3 + 6 .eabi_attribute 24, 1 + 7 .eabi_attribute 25, 1 + 8 .eabi_attribute 26, 1 + 9 .eabi_attribute 30, 1 + 10 .eabi_attribute 34, 1 + 11 .eabi_attribute 18, 4 + 12 .file "w25_qspi.c" + 13 .text + 14 .Ltext0: + 15 .cfi_sections .debug_frame + 16 .section .text._W25_GetDefaultCommand,"ax",%progbits + 17 .align 1 + 18 .global _W25_GetDefaultCommand + 19 .arch armv7e-m + 20 .syntax unified + 21 .thumb + 22 .thumb_func + 23 .fpu fpv5-d16 + 25 _W25_GetDefaultCommand: + 26 .LVL0: + 27 .LFB151: + 28 .file 1 "Core/Src/w25_qspi.c" + 1:Core/Src/w25_qspi.c **** // + 2:Core/Src/w25_qspi.c **** // Created by imi415 on 2019/12/19. + 3:Core/Src/w25_qspi.c **** // + 4:Core/Src/w25_qspi.c **** + 5:Core/Src/w25_qspi.c **** #include + 6:Core/Src/w25_qspi.c **** + 7:Core/Src/w25_qspi.c **** #include "stm32h7xx_hal.h" + 8:Core/Src/w25_qspi.c **** #include "w25_qspi.h" + 9:Core/Src/w25_qspi.c **** + 10:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash); + 11:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_Write_Volatile_Enable(w25_qspi_t *flash); + 12:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_Wait_Ready(w25_qspi_t *flash); + 13:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_GetDefaultCommand(w25_qspi_t *flash, QSPI_CommandTypeDef *sCommand); + 14:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_QSPI_Identify(w25_qspi_t *flash); + 15:Core/Src/w25_qspi.c **** + 16:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_Init(w25_qspi_t *flash) { + 17:Core/Src/w25_qspi.c **** return _W25_QSPI_Identify(flash); + 18:Core/Src/w25_qspi.c **** } + 19:Core/Src/w25_qspi.c **** + 20:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_Erase_Sector(w25_qspi_t *flash, uint32_t address) { + 21:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 22:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 23:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_SECTOR_ERASE; + 24:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 25:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 26:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 27:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 28:Core/Src/w25_qspi.c **** sCommand.Address = address; + 29:Core/Src/w25_qspi.c **** + 30:Core/Src/w25_qspi.c **** _W25_Write_Enable(flash); + ARM GAS /tmp/cc77UdtT.s page 2 + + + 31:Core/Src/w25_qspi.c **** HAL_QSPI_Command(flash->interface, &sCommand, 1000); + 32:Core/Src/w25_qspi.c **** _W25_Wait_Ready(flash); + 33:Core/Src/w25_qspi.c **** + 34:Core/Src/w25_qspi.c **** return HAL_OK; + 35:Core/Src/w25_qspi.c **** } + 36:Core/Src/w25_qspi.c **** + 37:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_Program_Page(w25_qspi_t *flash, uint32_t address, uint8_t *data) { + 38:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 39:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 40:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_PAGE_PROGRAM; + 41:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 42:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 43:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 44:Core/Src/w25_qspi.c **** sCommand.NbData = 256; + 45:Core/Src/w25_qspi.c **** sCommand.Address = address; + 46:Core/Src/w25_qspi.c **** + 47:Core/Src/w25_qspi.c **** _W25_Write_Enable(flash); + 48:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + 49:Core/Src/w25_qspi.c **** return HAL_ERROR; + 50:Core/Src/w25_qspi.c **** } + 51:Core/Src/w25_qspi.c **** if(HAL_QSPI_Transmit(flash->interface, data, 1000) != HAL_OK) { + 52:Core/Src/w25_qspi.c **** return HAL_ERROR; + 53:Core/Src/w25_qspi.c **** } + 54:Core/Src/w25_qspi.c **** _W25_Wait_Ready(flash); + 55:Core/Src/w25_qspi.c **** + 56:Core/Src/w25_qspi.c **** return HAL_OK; + 57:Core/Src/w25_qspi.c **** } + 58:Core/Src/w25_qspi.c **** + 59:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_Read(w25_qspi_t *flash, uint32_t address, uint8_t *data, uint32_t length + 60:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 61:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 62:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ; + 63:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 64:Core/Src/w25_qspi.c **** sCommand.Address = address; + 65:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 66:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 67:Core/Src/w25_qspi.c **** sCommand.NbData = length; + 68:Core/Src/w25_qspi.c **** + 69:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + 70:Core/Src/w25_qspi.c **** return HAL_ERROR; + 71:Core/Src/w25_qspi.c **** } + 72:Core/Src/w25_qspi.c **** if(HAL_QSPI_Receive(flash->interface, data, 1000) != HAL_OK) { + 73:Core/Src/w25_qspi.c **** return HAL_ERROR; + 74:Core/Src/w25_qspi.c **** } + 75:Core/Src/w25_qspi.c **** return HAL_OK; + 76:Core/Src/w25_qspi.c **** } + 77:Core/Src/w25_qspi.c **** + 78:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_QuadEnable(w25_qspi_t *flash, uint8_t permanent) { + 79:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 80:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 81:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_STATUS_2; + 82:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 83:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 84:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 85:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 86:Core/Src/w25_qspi.c **** + 87:Core/Src/w25_qspi.c **** uint8_t status_2; + ARM GAS /tmp/cc77UdtT.s page 3 + + + 88:Core/Src/w25_qspi.c **** + 89:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + 90:Core/Src/w25_qspi.c **** return HAL_ERROR; + 91:Core/Src/w25_qspi.c **** } + 92:Core/Src/w25_qspi.c **** if(HAL_QSPI_Receive(flash->interface, &status_2, 1000) != HAL_OK) { + 93:Core/Src/w25_qspi.c **** return HAL_ERROR; + 94:Core/Src/w25_qspi.c **** } + 95:Core/Src/w25_qspi.c **** + 96:Core/Src/w25_qspi.c **** if(permanent) { + 97:Core/Src/w25_qspi.c **** _W25_Write_Enable(flash); + 98:Core/Src/w25_qspi.c **** } + 99:Core/Src/w25_qspi.c **** else _W25_Write_Volatile_Enable(flash); + 100:Core/Src/w25_qspi.c **** + 101:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_WRITE_STATUS_2; + 102:Core/Src/w25_qspi.c **** status_2 |= 0x02; // BIT 1 QE + 103:Core/Src/w25_qspi.c **** + 104:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + 105:Core/Src/w25_qspi.c **** return HAL_ERROR; + 106:Core/Src/w25_qspi.c **** } + 107:Core/Src/w25_qspi.c **** if(HAL_QSPI_Transmit(flash->interface, &status_2, 1000) != HAL_OK) { + 108:Core/Src/w25_qspi.c **** return HAL_ERROR; + 109:Core/Src/w25_qspi.c **** } + 110:Core/Src/w25_qspi.c **** + 111:Core/Src/w25_qspi.c **** return HAL_OK; + 112:Core/Src/w25_qspi.c **** + 113:Core/Src/w25_qspi.c **** } + 114:Core/Src/w25_qspi.c **** + 115:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QPI_Mode(w25_qspi_t *flash, uint8_t enable) { + 116:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 117:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 118:Core/Src/w25_qspi.c **** if(enable) { + 119:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_ENABLE; + 120:Core/Src/w25_qspi.c **** } + 121:Core/Src/w25_qspi.c **** else { + 122:Core/Src/w25_qspi.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + 123:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_DISABLE; + 124:Core/Src/w25_qspi.c **** } + 125:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 126:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 127:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 128:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 129:Core/Src/w25_qspi.c **** + 130:Core/Src/w25_qspi.c **** return HAL_QSPI_Command(flash->interface, &sCommand, 1000); + 131:Core/Src/w25_qspi.c **** } + 132:Core/Src/w25_qspi.c **** + 133:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QPI_ReadParams(w25_qspi_t *flash, w25_qpi_dummy_t dummy_clocks, w25_qpi_wrap_ + 134:Core/Src/w25_qspi.c **** uint8_t rd_params = (dummy_clocks & 0x03) << 4 | (wrap_length & 0x03); // BIT 5-4: DUMMY, BIT 1 + 135:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 136:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 137:Core/Src/w25_qspi.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + 138:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_READ_PARAMS; + 139:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 140:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_4_LINES; + 141:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 142:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 143:Core/Src/w25_qspi.c **** + 144:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + ARM GAS /tmp/cc77UdtT.s page 4 + + + 145:Core/Src/w25_qspi.c **** return HAL_ERROR; + 146:Core/Src/w25_qspi.c **** } + 147:Core/Src/w25_qspi.c **** + 148:Core/Src/w25_qspi.c **** return HAL_QSPI_Transmit(flash->interface, &rd_params, 1000); + 149:Core/Src/w25_qspi.c **** } + 150:Core/Src/w25_qspi.c **** + 151:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_Write_Enable(w25_qspi_t *flash) { + 152:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 153:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 154:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_WRITE_ENABLE; + 155:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 156:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 157:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 158:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 159:Core/Src/w25_qspi.c **** + 160:Core/Src/w25_qspi.c **** HAL_QSPI_Command(flash->interface, &sCommand, 1000); + 161:Core/Src/w25_qspi.c **** + 162:Core/Src/w25_qspi.c **** return HAL_OK; + 163:Core/Src/w25_qspi.c **** } + 164:Core/Src/w25_qspi.c **** + 165:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_Write_Volatile_Enable(w25_qspi_t *flash) { + 166:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 167:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 168:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_WRITE_VOLATILE_ENABLE; + 169:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 170:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 171:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 172:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 173:Core/Src/w25_qspi.c **** + 174:Core/Src/w25_qspi.c **** HAL_QSPI_Command(flash->interface, &sCommand, 1000); + 175:Core/Src/w25_qspi.c **** + 176:Core/Src/w25_qspi.c **** return HAL_OK; + 177:Core/Src/w25_qspi.c **** } + 178:Core/Src/w25_qspi.c **** + 179:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_Wait_Ready(w25_qspi_t *flash) { + 180:Core/Src/w25_qspi.c **** QSPI_AutoPollingTypeDef sConfig; + 181:Core/Src/w25_qspi.c **** sConfig.Match = 0x00; + 182:Core/Src/w25_qspi.c **** sConfig.Mask = 0x01; + 183:Core/Src/w25_qspi.c **** sConfig.MatchMode = QSPI_MATCH_MODE_AND; + 184:Core/Src/w25_qspi.c **** sConfig.StatusBytesSize = 1; + 185:Core/Src/w25_qspi.c **** sConfig.Interval = 0x10; + 186:Core/Src/w25_qspi.c **** sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + 187:Core/Src/w25_qspi.c **** + 188:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 189:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 190:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 191:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 192:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_STATUS_1; + 193:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 194:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 195:Core/Src/w25_qspi.c **** + 196:Core/Src/w25_qspi.c **** if(HAL_QSPI_AutoPolling_IT(flash->interface, &sCommand, &sConfig) != HAL_OK) { + 197:Core/Src/w25_qspi.c **** return HAL_ERROR; + 198:Core/Src/w25_qspi.c **** } + 199:Core/Src/w25_qspi.c **** return HAL_OK; + 200:Core/Src/w25_qspi.c **** } + 201:Core/Src/w25_qspi.c **** + ARM GAS /tmp/cc77UdtT.s page 5 + + + 202:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_GetDefaultCommand(w25_qspi_t *flash, QSPI_CommandTypeDef *sCommand) { + 29 .loc 1 202 92 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 203:Core/Src/w25_qspi.c **** sCommand->InstructionMode = QSPI_INSTRUCTION_1_LINE; + 34 .loc 1 203 5 view .LVU1 + 35 .loc 1 203 31 is_stmt 0 view .LVU2 + 36 0000 4FF48073 mov r3, #256 + 37 0004 8B61 str r3, [r1, #24] + 204:Core/Src/w25_qspi.c **** sCommand->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + 38 .loc 1 204 5 is_stmt 1 view .LVU3 + 39 .loc 1 204 33 is_stmt 0 view .LVU4 + 40 0006 0023 movs r3, #0 + 41 0008 0B62 str r3, [r1, #32] + 205:Core/Src/w25_qspi.c **** sCommand->DdrMode = QSPI_DDR_MODE_DISABLE; + 42 .loc 1 205 5 is_stmt 1 view .LVU5 + 43 .loc 1 205 23 is_stmt 0 view .LVU6 + 44 000a CB62 str r3, [r1, #44] + 206:Core/Src/w25_qspi.c **** sCommand->DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + 45 .loc 1 206 5 is_stmt 1 view .LVU7 + 46 .loc 1 206 32 is_stmt 0 view .LVU8 + 47 000c 0B63 str r3, [r1, #48] + 207:Core/Src/w25_qspi.c **** sCommand->SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + 48 .loc 1 207 5 is_stmt 1 view .LVU9 + 49 .loc 1 207 24 is_stmt 0 view .LVU10 + 50 000e 4B63 str r3, [r1, #52] + 208:Core/Src/w25_qspi.c **** + 209:Core/Src/w25_qspi.c **** if(flash->address_size == W25_ADDRESS_32BITS) sCommand->AddressSize = QSPI_ADDRESS_32_BITS; + 51 .loc 1 209 5 is_stmt 1 view .LVU11 + 52 .loc 1 209 13 is_stmt 0 view .LVU12 + 53 0010 4379 ldrb r3, [r0, #5] @ zero_extendqisi2 + 54 .loc 1 209 7 view .LVU13 + 55 0012 012B cmp r3, #1 + 56 0014 04D0 beq .L4 + 210:Core/Src/w25_qspi.c **** else sCommand->AddressSize = QSPI_ADDRESS_24_BITS; + 57 .loc 1 210 10 is_stmt 1 view .LVU14 + 58 .loc 1 210 32 is_stmt 0 view .LVU15 + 59 0016 4FF40053 mov r3, #8192 + 60 001a CB60 str r3, [r1, #12] + 61 .L3: + 211:Core/Src/w25_qspi.c **** + 212:Core/Src/w25_qspi.c **** return HAL_OK; + 62 .loc 1 212 5 is_stmt 1 view .LVU16 + 213:Core/Src/w25_qspi.c **** } + 63 .loc 1 213 1 is_stmt 0 view .LVU17 + 64 001c 0020 movs r0, #0 + 65 .LVL1: + 66 .loc 1 213 1 view .LVU18 + 67 001e 7047 bx lr + 68 .LVL2: + 69 .L4: + 209:Core/Src/w25_qspi.c **** else sCommand->AddressSize = QSPI_ADDRESS_24_BITS; + 70 .loc 1 209 51 is_stmt 1 discriminator 1 view .LVU19 + 209:Core/Src/w25_qspi.c **** else sCommand->AddressSize = QSPI_ADDRESS_24_BITS; + 71 .loc 1 209 73 is_stmt 0 discriminator 1 view .LVU20 + ARM GAS /tmp/cc77UdtT.s page 6 + + + 72 0020 4FF44053 mov r3, #12288 + 73 0024 CB60 str r3, [r1, #12] + 74 0026 F9E7 b .L3 + 75 .cfi_endproc + 76 .LFE151: + 78 .section .text.W25_QSPI_Read,"ax",%progbits + 79 .align 1 + 80 .global W25_QSPI_Read + 81 .syntax unified + 82 .thumb + 83 .thumb_func + 84 .fpu fpv5-d16 + 86 W25_QSPI_Read: + 87 .LVL3: + 88 .LFB144: + 59:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 89 .loc 1 59 102 is_stmt 1 view -0 + 90 .cfi_startproc + 91 @ args = 0, pretend = 0, frame = 56 + 92 @ frame_needed = 0, uses_anonymous_args = 0 + 59:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 93 .loc 1 59 102 is_stmt 0 view .LVU22 + 94 0000 F0B5 push {r4, r5, r6, r7, lr} + 95 .LCFI0: + 96 .cfi_def_cfa_offset 20 + 97 .cfi_offset 4, -20 + 98 .cfi_offset 5, -16 + 99 .cfi_offset 6, -12 + 100 .cfi_offset 7, -8 + 101 .cfi_offset 14, -4 + 102 0002 8FB0 sub sp, sp, #60 + 103 .LCFI1: + 104 .cfi_def_cfa_offset 80 + 105 0004 0446 mov r4, r0 + 106 0006 0E46 mov r6, r1 + 107 0008 1746 mov r7, r2 + 108 000a 1D46 mov r5, r3 + 60:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 109 .loc 1 60 5 is_stmt 1 view .LVU23 + 61:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ; + 110 .loc 1 61 5 view .LVU24 + 111 000c 6946 mov r1, sp + 112 .LVL4: + 61:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ; + 113 .loc 1 61 5 is_stmt 0 view .LVU25 + 114 000e FFF7FEFF bl _W25_GetDefaultCommand + 115 .LVL5: + 62:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 116 .loc 1 62 5 is_stmt 1 view .LVU26 + 62:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 117 .loc 1 62 26 is_stmt 0 view .LVU27 + 118 0012 0323 movs r3, #3 + 119 0014 0093 str r3, [sp] + 63:Core/Src/w25_qspi.c **** sCommand.Address = address; + 120 .loc 1 63 5 is_stmt 1 view .LVU28 + 63:Core/Src/w25_qspi.c **** sCommand.Address = address; + 121 .loc 1 63 26 is_stmt 0 view .LVU29 + ARM GAS /tmp/cc77UdtT.s page 7 + + + 122 0016 4FF48063 mov r3, #1024 + 123 001a 0793 str r3, [sp, #28] + 64:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 124 .loc 1 64 5 is_stmt 1 view .LVU30 + 64:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 125 .loc 1 64 22 is_stmt 0 view .LVU31 + 126 001c 0196 str r6, [sp, #4] + 65:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 127 .loc 1 65 5 is_stmt 1 view .LVU32 + 65:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 128 .loc 1 65 23 is_stmt 0 view .LVU33 + 129 001e 4FF08073 mov r3, #16777216 + 130 0022 0993 str r3, [sp, #36] + 66:Core/Src/w25_qspi.c **** sCommand.NbData = length; + 131 .loc 1 66 5 is_stmt 1 view .LVU34 + 66:Core/Src/w25_qspi.c **** sCommand.NbData = length; + 132 .loc 1 66 26 is_stmt 0 view .LVU35 + 133 0024 0023 movs r3, #0 + 134 0026 0593 str r3, [sp, #20] + 67:Core/Src/w25_qspi.c **** + 135 .loc 1 67 5 is_stmt 1 view .LVU36 + 67:Core/Src/w25_qspi.c **** + 136 .loc 1 67 21 is_stmt 0 view .LVU37 + 137 0028 0A95 str r5, [sp, #40] + 69:Core/Src/w25_qspi.c **** return HAL_ERROR; + 138 .loc 1 69 5 is_stmt 1 view .LVU38 + 69:Core/Src/w25_qspi.c **** return HAL_ERROR; + 139 .loc 1 69 8 is_stmt 0 view .LVU39 + 140 002a 4FF47A72 mov r2, #1000 + 141 002e 6946 mov r1, sp + 142 0030 2068 ldr r0, [r4] + 143 0032 FFF7FEFF bl HAL_QSPI_Command + 144 .LVL6: + 69:Core/Src/w25_qspi.c **** return HAL_ERROR; + 145 .loc 1 69 7 view .LVU40 + 146 0036 10B1 cbz r0, .L10 + 70:Core/Src/w25_qspi.c **** } + 147 .loc 1 70 16 view .LVU41 + 148 0038 0120 movs r0, #1 + 149 .L6: + 76:Core/Src/w25_qspi.c **** + 150 .loc 1 76 1 view .LVU42 + 151 003a 0FB0 add sp, sp, #60 + 152 .LCFI2: + 153 .cfi_remember_state + 154 .cfi_def_cfa_offset 20 + 155 @ sp needed + 156 003c F0BD pop {r4, r5, r6, r7, pc} + 157 .LVL7: + 158 .L10: + 159 .LCFI3: + 160 .cfi_restore_state + 72:Core/Src/w25_qspi.c **** return HAL_ERROR; + 161 .loc 1 72 5 is_stmt 1 view .LVU43 + 72:Core/Src/w25_qspi.c **** return HAL_ERROR; + 162 .loc 1 72 8 is_stmt 0 view .LVU44 + 163 003e 4FF47A72 mov r2, #1000 + ARM GAS /tmp/cc77UdtT.s page 8 + + + 164 0042 3946 mov r1, r7 + 165 0044 2068 ldr r0, [r4] + 166 0046 FFF7FEFF bl HAL_QSPI_Receive + 167 .LVL8: + 72:Core/Src/w25_qspi.c **** return HAL_ERROR; + 168 .loc 1 72 7 view .LVU45 + 169 004a 0028 cmp r0, #0 + 170 004c F5D0 beq .L6 + 73:Core/Src/w25_qspi.c **** } + 171 .loc 1 73 16 view .LVU46 + 172 004e 0120 movs r0, #1 + 173 0050 F3E7 b .L6 + 174 .cfi_endproc + 175 .LFE144: + 177 .section .text.W25_QPI_Mode,"ax",%progbits + 178 .align 1 + 179 .global W25_QPI_Mode + 180 .syntax unified + 181 .thumb + 182 .thumb_func + 183 .fpu fpv5-d16 + 185 W25_QPI_Mode: + 186 .LVL9: + 187 .LFB146: + 115:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 188 .loc 1 115 67 is_stmt 1 view -0 + 189 .cfi_startproc + 190 @ args = 0, pretend = 0, frame = 56 + 191 @ frame_needed = 0, uses_anonymous_args = 0 + 115:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 192 .loc 1 115 67 is_stmt 0 view .LVU48 + 193 0000 30B5 push {r4, r5, lr} + 194 .LCFI4: + 195 .cfi_def_cfa_offset 12 + 196 .cfi_offset 4, -12 + 197 .cfi_offset 5, -8 + 198 .cfi_offset 14, -4 + 199 0002 8FB0 sub sp, sp, #60 + 200 .LCFI5: + 201 .cfi_def_cfa_offset 72 + 202 0004 0446 mov r4, r0 + 203 0006 0D46 mov r5, r1 + 116:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 204 .loc 1 116 5 is_stmt 1 view .LVU49 + 117:Core/Src/w25_qspi.c **** if(enable) { + 205 .loc 1 117 5 view .LVU50 + 206 0008 6946 mov r1, sp + 207 .LVL10: + 117:Core/Src/w25_qspi.c **** if(enable) { + 208 .loc 1 117 5 is_stmt 0 view .LVU51 + 209 000a FFF7FEFF bl _W25_GetDefaultCommand + 210 .LVL11: + 118:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_ENABLE; + 211 .loc 1 118 5 is_stmt 1 view .LVU52 + 118:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_ENABLE; + 212 .loc 1 118 7 is_stmt 0 view .LVU53 + 213 000e 75B1 cbz r5, .L12 + ARM GAS /tmp/cc77UdtT.s page 9 + + + 119:Core/Src/w25_qspi.c **** } + 214 .loc 1 119 9 is_stmt 1 view .LVU54 + 119:Core/Src/w25_qspi.c **** } + 215 .loc 1 119 30 is_stmt 0 view .LVU55 + 216 0010 3823 movs r3, #56 + 217 0012 0093 str r3, [sp] + 218 .L13: + 125:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 219 .loc 1 125 5 is_stmt 1 view .LVU56 + 125:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 220 .loc 1 125 26 is_stmt 0 view .LVU57 + 221 0014 0023 movs r3, #0 + 222 0016 0793 str r3, [sp, #28] + 126:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 223 .loc 1 126 5 is_stmt 1 view .LVU58 + 126:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 224 .loc 1 126 23 is_stmt 0 view .LVU59 + 225 0018 0993 str r3, [sp, #36] + 127:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 226 .loc 1 127 5 is_stmt 1 view .LVU60 + 127:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 227 .loc 1 127 21 is_stmt 0 view .LVU61 + 228 001a 0A93 str r3, [sp, #40] + 128:Core/Src/w25_qspi.c **** + 229 .loc 1 128 5 is_stmt 1 view .LVU62 + 128:Core/Src/w25_qspi.c **** + 230 .loc 1 128 26 is_stmt 0 view .LVU63 + 231 001c 0593 str r3, [sp, #20] + 130:Core/Src/w25_qspi.c **** } + 232 .loc 1 130 5 is_stmt 1 view .LVU64 + 130:Core/Src/w25_qspi.c **** } + 233 .loc 1 130 12 is_stmt 0 view .LVU65 + 234 001e 4FF47A72 mov r2, #1000 + 235 0022 6946 mov r1, sp + 236 0024 2068 ldr r0, [r4] + 237 0026 FFF7FEFF bl HAL_QSPI_Command + 238 .LVL12: + 131:Core/Src/w25_qspi.c **** + 239 .loc 1 131 1 view .LVU66 + 240 002a 0FB0 add sp, sp, #60 + 241 .LCFI6: + 242 .cfi_remember_state + 243 .cfi_def_cfa_offset 12 + 244 @ sp needed + 245 002c 30BD pop {r4, r5, pc} + 246 .LVL13: + 247 .L12: + 248 .LCFI7: + 249 .cfi_restore_state + 122:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_DISABLE; + 250 .loc 1 122 9 is_stmt 1 view .LVU67 + 122:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_DISABLE; + 251 .loc 1 122 34 is_stmt 0 view .LVU68 + 252 002e 4FF44073 mov r3, #768 + 253 0032 0693 str r3, [sp, #24] + 123:Core/Src/w25_qspi.c **** } + 254 .loc 1 123 9 is_stmt 1 view .LVU69 + ARM GAS /tmp/cc77UdtT.s page 10 + + + 123:Core/Src/w25_qspi.c **** } + 255 .loc 1 123 30 is_stmt 0 view .LVU70 + 256 0034 FF23 movs r3, #255 + 257 0036 0093 str r3, [sp] + 258 0038 ECE7 b .L13 + 259 .cfi_endproc + 260 .LFE146: + 262 .section .text.W25_QPI_ReadParams,"ax",%progbits + 263 .align 1 + 264 .global W25_QPI_ReadParams + 265 .syntax unified + 266 .thumb + 267 .thumb_func + 268 .fpu fpv5-d16 + 270 W25_QPI_ReadParams: + 271 .LVL14: + 272 .LFB147: + 133:Core/Src/w25_qspi.c **** uint8_t rd_params = (dummy_clocks & 0x03) << 4 | (wrap_length & 0x03); // BIT 5-4: DUMMY, BIT 1 + 273 .loc 1 133 115 is_stmt 1 view -0 + 274 .cfi_startproc + 275 @ args = 0, pretend = 0, frame = 64 + 276 @ frame_needed = 0, uses_anonymous_args = 0 + 133:Core/Src/w25_qspi.c **** uint8_t rd_params = (dummy_clocks & 0x03) << 4 | (wrap_length & 0x03); // BIT 5-4: DUMMY, BIT 1 + 277 .loc 1 133 115 is_stmt 0 view .LVU72 + 278 0000 10B5 push {r4, lr} + 279 .LCFI8: + 280 .cfi_def_cfa_offset 8 + 281 .cfi_offset 4, -8 + 282 .cfi_offset 14, -4 + 283 0002 90B0 sub sp, sp, #64 + 284 .LCFI9: + 285 .cfi_def_cfa_offset 72 + 286 0004 0446 mov r4, r0 + 134:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 287 .loc 1 134 5 is_stmt 1 view .LVU73 + 134:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 288 .loc 1 134 47 is_stmt 0 view .LVU74 + 289 0006 0901 lsls r1, r1, #4 + 290 .LVL15: + 134:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 291 .loc 1 134 47 view .LVU75 + 292 0008 01F03001 and r1, r1, #48 + 134:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 293 .loc 1 134 67 view .LVU76 + 294 000c 02F00302 and r2, r2, #3 + 295 .LVL16: + 134:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 296 .loc 1 134 52 view .LVU77 + 297 0010 1143 orrs r1, r1, r2 + 134:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 298 .loc 1 134 13 view .LVU78 + 299 0012 8DF83F10 strb r1, [sp, #63] + 135:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 300 .loc 1 135 5 is_stmt 1 view .LVU79 + 136:Core/Src/w25_qspi.c **** sCommand.InstructionMode = QSPI_INSTRUCTION_4_LINES; + 301 .loc 1 136 5 view .LVU80 + 302 0016 01A9 add r1, sp, #4 + ARM GAS /tmp/cc77UdtT.s page 11 + + + 303 0018 FFF7FEFF bl _W25_GetDefaultCommand + 304 .LVL17: + 137:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_READ_PARAMS; + 305 .loc 1 137 5 view .LVU81 + 137:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_QPI_READ_PARAMS; + 306 .loc 1 137 30 is_stmt 0 view .LVU82 + 307 001c 4FF44073 mov r3, #768 + 308 0020 0793 str r3, [sp, #28] + 138:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 309 .loc 1 138 5 is_stmt 1 view .LVU83 + 138:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 310 .loc 1 138 26 is_stmt 0 view .LVU84 + 311 0022 C023 movs r3, #192 + 312 0024 0193 str r3, [sp, #4] + 139:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_4_LINES; + 313 .loc 1 139 5 is_stmt 1 view .LVU85 + 139:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_4_LINES; + 314 .loc 1 139 26 is_stmt 0 view .LVU86 + 315 0026 0023 movs r3, #0 + 316 0028 0893 str r3, [sp, #32] + 140:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 317 .loc 1 140 5 is_stmt 1 view .LVU87 + 140:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 318 .loc 1 140 23 is_stmt 0 view .LVU88 + 319 002a 4FF04072 mov r2, #50331648 + 320 002e 0A92 str r2, [sp, #40] + 141:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 321 .loc 1 141 5 is_stmt 1 view .LVU89 + 141:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 322 .loc 1 141 21 is_stmt 0 view .LVU90 + 323 0030 0122 movs r2, #1 + 324 0032 0B92 str r2, [sp, #44] + 142:Core/Src/w25_qspi.c **** + 325 .loc 1 142 5 is_stmt 1 view .LVU91 + 142:Core/Src/w25_qspi.c **** + 326 .loc 1 142 26 is_stmt 0 view .LVU92 + 327 0034 0693 str r3, [sp, #24] + 144:Core/Src/w25_qspi.c **** return HAL_ERROR; + 328 .loc 1 144 5 is_stmt 1 view .LVU93 + 144:Core/Src/w25_qspi.c **** return HAL_ERROR; + 329 .loc 1 144 8 is_stmt 0 view .LVU94 + 330 0036 4FF47A72 mov r2, #1000 + 331 003a 01A9 add r1, sp, #4 + 332 003c 2068 ldr r0, [r4] + 333 003e FFF7FEFF bl HAL_QSPI_Command + 334 .LVL18: + 144:Core/Src/w25_qspi.c **** return HAL_ERROR; + 335 .loc 1 144 7 view .LVU95 + 336 0042 10B1 cbz r0, .L19 + 145:Core/Src/w25_qspi.c **** } + 337 .loc 1 145 16 view .LVU96 + 338 0044 0120 movs r0, #1 + 339 .L16: + 149:Core/Src/w25_qspi.c **** + 340 .loc 1 149 1 view .LVU97 + 341 0046 10B0 add sp, sp, #64 + 342 .LCFI10: + ARM GAS /tmp/cc77UdtT.s page 12 + + + 343 .cfi_remember_state + 344 .cfi_def_cfa_offset 8 + 345 @ sp needed + 346 0048 10BD pop {r4, pc} + 347 .LVL19: + 348 .L19: + 349 .LCFI11: + 350 .cfi_restore_state + 148:Core/Src/w25_qspi.c **** } + 351 .loc 1 148 5 is_stmt 1 view .LVU98 + 148:Core/Src/w25_qspi.c **** } + 352 .loc 1 148 12 is_stmt 0 view .LVU99 + 353 004a 4FF47A72 mov r2, #1000 + 354 004e 0DF13F01 add r1, sp, #63 + 355 0052 2068 ldr r0, [r4] + 356 0054 FFF7FEFF bl HAL_QSPI_Transmit + 357 .LVL20: + 358 0058 F5E7 b .L16 + 359 .cfi_endproc + 360 .LFE147: + 362 .section .text._W25_Write_Enable,"ax",%progbits + 363 .align 1 + 364 .global _W25_Write_Enable + 365 .syntax unified + 366 .thumb + 367 .thumb_func + 368 .fpu fpv5-d16 + 370 _W25_Write_Enable: + 371 .LVL21: + 372 .LFB148: + 151:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 373 .loc 1 151 56 is_stmt 1 view -0 + 374 .cfi_startproc + 375 @ args = 0, pretend = 0, frame = 56 + 376 @ frame_needed = 0, uses_anonymous_args = 0 + 151:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 377 .loc 1 151 56 is_stmt 0 view .LVU101 + 378 0000 30B5 push {r4, r5, lr} + 379 .LCFI12: + 380 .cfi_def_cfa_offset 12 + 381 .cfi_offset 4, -12 + 382 .cfi_offset 5, -8 + 383 .cfi_offset 14, -4 + 384 0002 8FB0 sub sp, sp, #60 + 385 .LCFI13: + 386 .cfi_def_cfa_offset 72 + 387 0004 0546 mov r5, r0 + 152:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 388 .loc 1 152 5 is_stmt 1 view .LVU102 + 153:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_WRITE_ENABLE; + 389 .loc 1 153 5 view .LVU103 + 390 0006 6946 mov r1, sp + 391 0008 FFF7FEFF bl _W25_GetDefaultCommand + 392 .LVL22: + 154:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 393 .loc 1 154 5 view .LVU104 + 154:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + ARM GAS /tmp/cc77UdtT.s page 13 + + + 394 .loc 1 154 26 is_stmt 0 view .LVU105 + 395 000c 0623 movs r3, #6 + 396 000e 0093 str r3, [sp] + 155:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 397 .loc 1 155 5 is_stmt 1 view .LVU106 + 155:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 398 .loc 1 155 26 is_stmt 0 view .LVU107 + 399 0010 0024 movs r4, #0 + 400 0012 0794 str r4, [sp, #28] + 156:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 401 .loc 1 156 5 is_stmt 1 view .LVU108 + 156:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 402 .loc 1 156 23 is_stmt 0 view .LVU109 + 403 0014 0994 str r4, [sp, #36] + 157:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 404 .loc 1 157 5 is_stmt 1 view .LVU110 + 157:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 405 .loc 1 157 21 is_stmt 0 view .LVU111 + 406 0016 0A94 str r4, [sp, #40] + 158:Core/Src/w25_qspi.c **** + 407 .loc 1 158 5 is_stmt 1 view .LVU112 + 158:Core/Src/w25_qspi.c **** + 408 .loc 1 158 26 is_stmt 0 view .LVU113 + 409 0018 0594 str r4, [sp, #20] + 160:Core/Src/w25_qspi.c **** + 410 .loc 1 160 5 is_stmt 1 view .LVU114 + 411 001a 4FF47A72 mov r2, #1000 + 412 001e 6946 mov r1, sp + 413 0020 2868 ldr r0, [r5] + 414 0022 FFF7FEFF bl HAL_QSPI_Command + 415 .LVL23: + 162:Core/Src/w25_qspi.c **** } + 416 .loc 1 162 5 view .LVU115 + 163:Core/Src/w25_qspi.c **** + 417 .loc 1 163 1 is_stmt 0 view .LVU116 + 418 0026 2046 mov r0, r4 + 419 0028 0FB0 add sp, sp, #60 + 420 .LCFI14: + 421 .cfi_def_cfa_offset 12 + 422 @ sp needed + 423 002a 30BD pop {r4, r5, pc} + 163:Core/Src/w25_qspi.c **** + 424 .loc 1 163 1 view .LVU117 + 425 .cfi_endproc + 426 .LFE148: + 428 .section .text._W25_Write_Volatile_Enable,"ax",%progbits + 429 .align 1 + 430 .global _W25_Write_Volatile_Enable + 431 .syntax unified + 432 .thumb + 433 .thumb_func + 434 .fpu fpv5-d16 + 436 _W25_Write_Volatile_Enable: + 437 .LVL24: + 438 .LFB149: + 165:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 439 .loc 1 165 65 is_stmt 1 view -0 + ARM GAS /tmp/cc77UdtT.s page 14 + + + 440 .cfi_startproc + 441 @ args = 0, pretend = 0, frame = 56 + 442 @ frame_needed = 0, uses_anonymous_args = 0 + 165:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 443 .loc 1 165 65 is_stmt 0 view .LVU119 + 444 0000 30B5 push {r4, r5, lr} + 445 .LCFI15: + 446 .cfi_def_cfa_offset 12 + 447 .cfi_offset 4, -12 + 448 .cfi_offset 5, -8 + 449 .cfi_offset 14, -4 + 450 0002 8FB0 sub sp, sp, #60 + 451 .LCFI16: + 452 .cfi_def_cfa_offset 72 + 453 0004 0546 mov r5, r0 + 166:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 454 .loc 1 166 5 is_stmt 1 view .LVU120 + 167:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_WRITE_VOLATILE_ENABLE; + 455 .loc 1 167 5 view .LVU121 + 456 0006 6946 mov r1, sp + 457 0008 FFF7FEFF bl _W25_GetDefaultCommand + 458 .LVL25: + 168:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 459 .loc 1 168 5 view .LVU122 + 168:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 460 .loc 1 168 26 is_stmt 0 view .LVU123 + 461 000c 5023 movs r3, #80 + 462 000e 0093 str r3, [sp] + 169:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 463 .loc 1 169 5 is_stmt 1 view .LVU124 + 169:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 464 .loc 1 169 26 is_stmt 0 view .LVU125 + 465 0010 0024 movs r4, #0 + 466 0012 0794 str r4, [sp, #28] + 170:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 467 .loc 1 170 5 is_stmt 1 view .LVU126 + 170:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 468 .loc 1 170 23 is_stmt 0 view .LVU127 + 469 0014 0994 str r4, [sp, #36] + 171:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 470 .loc 1 171 5 is_stmt 1 view .LVU128 + 171:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 471 .loc 1 171 21 is_stmt 0 view .LVU129 + 472 0016 0A94 str r4, [sp, #40] + 172:Core/Src/w25_qspi.c **** + 473 .loc 1 172 5 is_stmt 1 view .LVU130 + 172:Core/Src/w25_qspi.c **** + 474 .loc 1 172 26 is_stmt 0 view .LVU131 + 475 0018 0594 str r4, [sp, #20] + 174:Core/Src/w25_qspi.c **** + 476 .loc 1 174 5 is_stmt 1 view .LVU132 + 477 001a 4FF47A72 mov r2, #1000 + 478 001e 6946 mov r1, sp + 479 0020 2868 ldr r0, [r5] + 480 0022 FFF7FEFF bl HAL_QSPI_Command + 481 .LVL26: + 176:Core/Src/w25_qspi.c **** } + ARM GAS /tmp/cc77UdtT.s page 15 + + + 482 .loc 1 176 5 view .LVU133 + 177:Core/Src/w25_qspi.c **** + 483 .loc 1 177 1 is_stmt 0 view .LVU134 + 484 0026 2046 mov r0, r4 + 485 0028 0FB0 add sp, sp, #60 + 486 .LCFI17: + 487 .cfi_def_cfa_offset 12 + 488 @ sp needed + 489 002a 30BD pop {r4, r5, pc} + 177:Core/Src/w25_qspi.c **** + 490 .loc 1 177 1 view .LVU135 + 491 .cfi_endproc + 492 .LFE149: + 494 .section .text.W25_QSPI_QuadEnable,"ax",%progbits + 495 .align 1 + 496 .global W25_QSPI_QuadEnable + 497 .syntax unified + 498 .thumb + 499 .thumb_func + 500 .fpu fpv5-d16 + 502 W25_QSPI_QuadEnable: + 503 .LVL27: + 504 .LFB145: + 78:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 505 .loc 1 78 77 is_stmt 1 view -0 + 506 .cfi_startproc + 507 @ args = 0, pretend = 0, frame = 64 + 508 @ frame_needed = 0, uses_anonymous_args = 0 + 78:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 509 .loc 1 78 77 is_stmt 0 view .LVU137 + 510 0000 30B5 push {r4, r5, lr} + 511 .LCFI18: + 512 .cfi_def_cfa_offset 12 + 513 .cfi_offset 4, -12 + 514 .cfi_offset 5, -8 + 515 .cfi_offset 14, -4 + 516 0002 91B0 sub sp, sp, #68 + 517 .LCFI19: + 518 .cfi_def_cfa_offset 80 + 519 0004 0446 mov r4, r0 + 520 0006 0D46 mov r5, r1 + 79:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 521 .loc 1 79 5 is_stmt 1 view .LVU138 + 80:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_STATUS_2; + 522 .loc 1 80 5 view .LVU139 + 523 0008 02A9 add r1, sp, #8 + 524 .LVL28: + 80:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_STATUS_2; + 525 .loc 1 80 5 is_stmt 0 view .LVU140 + 526 000a FFF7FEFF bl _W25_GetDefaultCommand + 527 .LVL29: + 81:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 528 .loc 1 81 5 is_stmt 1 view .LVU141 + 81:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 529 .loc 1 81 26 is_stmt 0 view .LVU142 + 530 000e 3523 movs r3, #53 + 531 0010 0293 str r3, [sp, #8] + ARM GAS /tmp/cc77UdtT.s page 16 + + + 82:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 532 .loc 1 82 5 is_stmt 1 view .LVU143 + 82:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 533 .loc 1 82 26 is_stmt 0 view .LVU144 + 534 0012 0023 movs r3, #0 + 535 0014 0993 str r3, [sp, #36] + 83:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 536 .loc 1 83 5 is_stmt 1 view .LVU145 + 83:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 537 .loc 1 83 23 is_stmt 0 view .LVU146 + 538 0016 4FF08072 mov r2, #16777216 + 539 001a 0B92 str r2, [sp, #44] + 84:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 540 .loc 1 84 5 is_stmt 1 view .LVU147 + 84:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 541 .loc 1 84 21 is_stmt 0 view .LVU148 + 542 001c 0122 movs r2, #1 + 543 001e 0C92 str r2, [sp, #48] + 85:Core/Src/w25_qspi.c **** + 544 .loc 1 85 5 is_stmt 1 view .LVU149 + 85:Core/Src/w25_qspi.c **** + 545 .loc 1 85 26 is_stmt 0 view .LVU150 + 546 0020 0793 str r3, [sp, #28] + 87:Core/Src/w25_qspi.c **** + 547 .loc 1 87 5 is_stmt 1 view .LVU151 + 89:Core/Src/w25_qspi.c **** return HAL_ERROR; + 548 .loc 1 89 5 view .LVU152 + 89:Core/Src/w25_qspi.c **** return HAL_ERROR; + 549 .loc 1 89 8 is_stmt 0 view .LVU153 + 550 0022 4FF47A72 mov r2, #1000 + 551 0026 02A9 add r1, sp, #8 + 552 0028 2068 ldr r0, [r4] + 553 002a FFF7FEFF bl HAL_QSPI_Command + 554 .LVL30: + 89:Core/Src/w25_qspi.c **** return HAL_ERROR; + 555 .loc 1 89 7 view .LVU154 + 556 002e 10B1 cbz r0, .L33 + 90:Core/Src/w25_qspi.c **** } + 557 .loc 1 90 16 view .LVU155 + 558 0030 0120 movs r0, #1 + 559 .L25: + 113:Core/Src/w25_qspi.c **** + 560 .loc 1 113 1 view .LVU156 + 561 0032 11B0 add sp, sp, #68 + 562 .LCFI20: + 563 .cfi_remember_state + 564 .cfi_def_cfa_offset 12 + 565 @ sp needed + 566 0034 30BD pop {r4, r5, pc} + 567 .LVL31: + 568 .L33: + 569 .LCFI21: + 570 .cfi_restore_state + 92:Core/Src/w25_qspi.c **** return HAL_ERROR; + 571 .loc 1 92 5 is_stmt 1 view .LVU157 + 92:Core/Src/w25_qspi.c **** return HAL_ERROR; + 572 .loc 1 92 8 is_stmt 0 view .LVU158 + ARM GAS /tmp/cc77UdtT.s page 17 + + + 573 0036 4FF47A72 mov r2, #1000 + 574 003a 0DF10701 add r1, sp, #7 + 575 003e 2068 ldr r0, [r4] + 576 0040 FFF7FEFF bl HAL_QSPI_Receive + 577 .LVL32: + 92:Core/Src/w25_qspi.c **** return HAL_ERROR; + 578 .loc 1 92 7 view .LVU159 + 579 0044 18BB cbnz r0, .L29 + 96:Core/Src/w25_qspi.c **** _W25_Write_Enable(flash); + 580 .loc 1 96 5 is_stmt 1 view .LVU160 + 96:Core/Src/w25_qspi.c **** _W25_Write_Enable(flash); + 581 .loc 1 96 7 is_stmt 0 view .LVU161 + 582 0046 9DB1 cbz r5, .L26 + 97:Core/Src/w25_qspi.c **** } + 583 .loc 1 97 9 is_stmt 1 view .LVU162 + 584 0048 2046 mov r0, r4 + 585 004a FFF7FEFF bl _W25_Write_Enable + 586 .LVL33: + 587 .L27: + 101:Core/Src/w25_qspi.c **** status_2 |= 0x02; // BIT 1 QE + 588 .loc 1 101 5 view .LVU163 + 101:Core/Src/w25_qspi.c **** status_2 |= 0x02; // BIT 1 QE + 589 .loc 1 101 26 is_stmt 0 view .LVU164 + 590 004e 3123 movs r3, #49 + 591 0050 0293 str r3, [sp, #8] + 102:Core/Src/w25_qspi.c **** + 592 .loc 1 102 5 is_stmt 1 view .LVU165 + 102:Core/Src/w25_qspi.c **** + 593 .loc 1 102 14 is_stmt 0 view .LVU166 + 594 0052 9DF80730 ldrb r3, [sp, #7] @ zero_extendqisi2 + 595 0056 43F00203 orr r3, r3, #2 + 596 005a 8DF80730 strb r3, [sp, #7] + 104:Core/Src/w25_qspi.c **** return HAL_ERROR; + 597 .loc 1 104 5 is_stmt 1 view .LVU167 + 104:Core/Src/w25_qspi.c **** return HAL_ERROR; + 598 .loc 1 104 8 is_stmt 0 view .LVU168 + 599 005e 4FF47A72 mov r2, #1000 + 600 0062 02A9 add r1, sp, #8 + 601 0064 2068 ldr r0, [r4] + 602 0066 FFF7FEFF bl HAL_QSPI_Command + 603 .LVL34: + 104:Core/Src/w25_qspi.c **** return HAL_ERROR; + 604 .loc 1 104 7 view .LVU169 + 605 006a 28B1 cbz r0, .L34 + 105:Core/Src/w25_qspi.c **** } + 606 .loc 1 105 16 view .LVU170 + 607 006c 0120 movs r0, #1 + 608 006e E0E7 b .L25 + 609 .L26: + 99:Core/Src/w25_qspi.c **** + 610 .loc 1 99 10 is_stmt 1 view .LVU171 + 611 0070 2046 mov r0, r4 + 612 0072 FFF7FEFF bl _W25_Write_Volatile_Enable + 613 .LVL35: + 614 0076 EAE7 b .L27 + 615 .L34: + 107:Core/Src/w25_qspi.c **** return HAL_ERROR; + ARM GAS /tmp/cc77UdtT.s page 18 + + + 616 .loc 1 107 5 view .LVU172 + 107:Core/Src/w25_qspi.c **** return HAL_ERROR; + 617 .loc 1 107 8 is_stmt 0 view .LVU173 + 618 0078 4FF47A72 mov r2, #1000 + 619 007c 0DF10701 add r1, sp, #7 + 620 0080 2068 ldr r0, [r4] + 621 0082 FFF7FEFF bl HAL_QSPI_Transmit + 622 .LVL36: + 107:Core/Src/w25_qspi.c **** return HAL_ERROR; + 623 .loc 1 107 7 view .LVU174 + 624 0086 0028 cmp r0, #0 + 625 0088 D3D0 beq .L25 + 108:Core/Src/w25_qspi.c **** } + 626 .loc 1 108 16 view .LVU175 + 627 008a 0120 movs r0, #1 + 628 008c D1E7 b .L25 + 629 .L29: + 93:Core/Src/w25_qspi.c **** } + 630 .loc 1 93 16 view .LVU176 + 631 008e 0120 movs r0, #1 + 632 0090 CFE7 b .L25 + 633 .cfi_endproc + 634 .LFE145: + 636 .section .text._W25_Wait_Ready,"ax",%progbits + 637 .align 1 + 638 .global _W25_Wait_Ready + 639 .syntax unified + 640 .thumb + 641 .thumb_func + 642 .fpu fpv5-d16 + 644 _W25_Wait_Ready: + 645 .LVL37: + 646 .LFB150: + 179:Core/Src/w25_qspi.c **** QSPI_AutoPollingTypeDef sConfig; + 647 .loc 1 179 54 is_stmt 1 view -0 + 648 .cfi_startproc + 649 @ args = 0, pretend = 0, frame = 80 + 650 @ frame_needed = 0, uses_anonymous_args = 0 + 179:Core/Src/w25_qspi.c **** QSPI_AutoPollingTypeDef sConfig; + 651 .loc 1 179 54 is_stmt 0 view .LVU178 + 652 0000 70B5 push {r4, r5, r6, lr} + 653 .LCFI22: + 654 .cfi_def_cfa_offset 16 + 655 .cfi_offset 4, -16 + 656 .cfi_offset 5, -12 + 657 .cfi_offset 6, -8 + 658 .cfi_offset 14, -4 + 659 0002 94B0 sub sp, sp, #80 + 660 .LCFI23: + 661 .cfi_def_cfa_offset 96 + 662 0004 0546 mov r5, r0 + 180:Core/Src/w25_qspi.c **** sConfig.Match = 0x00; + 663 .loc 1 180 5 is_stmt 1 view .LVU179 + 181:Core/Src/w25_qspi.c **** sConfig.Mask = 0x01; + 664 .loc 1 181 5 view .LVU180 + 181:Core/Src/w25_qspi.c **** sConfig.Mask = 0x01; + 665 .loc 1 181 19 is_stmt 0 view .LVU181 + ARM GAS /tmp/cc77UdtT.s page 19 + + + 666 0006 0024 movs r4, #0 + 667 0008 0E94 str r4, [sp, #56] + 182:Core/Src/w25_qspi.c **** sConfig.MatchMode = QSPI_MATCH_MODE_AND; + 668 .loc 1 182 5 is_stmt 1 view .LVU182 + 182:Core/Src/w25_qspi.c **** sConfig.MatchMode = QSPI_MATCH_MODE_AND; + 669 .loc 1 182 18 is_stmt 0 view .LVU183 + 670 000a 0126 movs r6, #1 + 671 000c 0F96 str r6, [sp, #60] + 183:Core/Src/w25_qspi.c **** sConfig.StatusBytesSize = 1; + 672 .loc 1 183 5 is_stmt 1 view .LVU184 + 183:Core/Src/w25_qspi.c **** sConfig.StatusBytesSize = 1; + 673 .loc 1 183 23 is_stmt 0 view .LVU185 + 674 000e 1294 str r4, [sp, #72] + 184:Core/Src/w25_qspi.c **** sConfig.Interval = 0x10; + 675 .loc 1 184 5 is_stmt 1 view .LVU186 + 184:Core/Src/w25_qspi.c **** sConfig.Interval = 0x10; + 676 .loc 1 184 29 is_stmt 0 view .LVU187 + 677 0010 1196 str r6, [sp, #68] + 185:Core/Src/w25_qspi.c **** sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + 678 .loc 1 185 5 is_stmt 1 view .LVU188 + 185:Core/Src/w25_qspi.c **** sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + 679 .loc 1 185 22 is_stmt 0 view .LVU189 + 680 0012 1023 movs r3, #16 + 681 0014 1093 str r3, [sp, #64] + 186:Core/Src/w25_qspi.c **** + 682 .loc 1 186 5 is_stmt 1 view .LVU190 + 186:Core/Src/w25_qspi.c **** + 683 .loc 1 186 27 is_stmt 0 view .LVU191 + 684 0016 4FF48003 mov r3, #4194304 + 685 001a 1393 str r3, [sp, #76] + 188:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 686 .loc 1 188 5 is_stmt 1 view .LVU192 + 189:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 687 .loc 1 189 5 view .LVU193 + 688 001c 6946 mov r1, sp + 689 001e FFF7FEFF bl _W25_GetDefaultCommand + 690 .LVL38: + 190:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 691 .loc 1 190 5 view .LVU194 + 190:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 692 .loc 1 190 23 is_stmt 0 view .LVU195 + 693 0022 4FF08073 mov r3, #16777216 + 694 0026 0993 str r3, [sp, #36] + 191:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_STATUS_1; + 695 .loc 1 191 5 is_stmt 1 view .LVU196 + 191:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_STATUS_1; + 696 .loc 1 191 26 is_stmt 0 view .LVU197 + 697 0028 0594 str r4, [sp, #20] + 192:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 698 .loc 1 192 5 is_stmt 1 view .LVU198 + 192:Core/Src/w25_qspi.c **** sCommand.NbData = 1; + 699 .loc 1 192 26 is_stmt 0 view .LVU199 + 700 002a 0523 movs r3, #5 + 701 002c 0093 str r3, [sp] + 193:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 702 .loc 1 193 5 is_stmt 1 view .LVU200 + 193:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + ARM GAS /tmp/cc77UdtT.s page 20 + + + 703 .loc 1 193 21 is_stmt 0 view .LVU201 + 704 002e 0A96 str r6, [sp, #40] + 194:Core/Src/w25_qspi.c **** + 705 .loc 1 194 5 is_stmt 1 view .LVU202 + 194:Core/Src/w25_qspi.c **** + 706 .loc 1 194 26 is_stmt 0 view .LVU203 + 707 0030 0794 str r4, [sp, #28] + 196:Core/Src/w25_qspi.c **** return HAL_ERROR; + 708 .loc 1 196 5 is_stmt 1 view .LVU204 + 196:Core/Src/w25_qspi.c **** return HAL_ERROR; + 709 .loc 1 196 8 is_stmt 0 view .LVU205 + 710 0032 0EAA add r2, sp, #56 + 711 0034 6946 mov r1, sp + 712 0036 2868 ldr r0, [r5] + 713 0038 FFF7FEFF bl HAL_QSPI_AutoPolling_IT + 714 .LVL39: + 196:Core/Src/w25_qspi.c **** return HAL_ERROR; + 715 .loc 1 196 7 view .LVU206 + 716 003c 08B9 cbnz r0, .L39 + 717 .L36: + 200:Core/Src/w25_qspi.c **** + 718 .loc 1 200 1 view .LVU207 + 719 003e 14B0 add sp, sp, #80 + 720 .LCFI24: + 721 .cfi_remember_state + 722 .cfi_def_cfa_offset 16 + 723 @ sp needed + 724 0040 70BD pop {r4, r5, r6, pc} + 725 .LVL40: + 726 .L39: + 727 .LCFI25: + 728 .cfi_restore_state + 197:Core/Src/w25_qspi.c **** } + 729 .loc 1 197 16 view .LVU208 + 730 0042 3046 mov r0, r6 + 731 0044 FBE7 b .L36 + 732 .cfi_endproc + 733 .LFE150: + 735 .section .text.W25_QSPI_Erase_Sector,"ax",%progbits + 736 .align 1 + 737 .global W25_QSPI_Erase_Sector + 738 .syntax unified + 739 .thumb + 740 .thumb_func + 741 .fpu fpv5-d16 + 743 W25_QSPI_Erase_Sector: + 744 .LVL41: + 745 .LFB142: + 20:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 746 .loc 1 20 78 is_stmt 1 view -0 + 747 .cfi_startproc + 748 @ args = 0, pretend = 0, frame = 56 + 749 @ frame_needed = 0, uses_anonymous_args = 0 + 20:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 750 .loc 1 20 78 is_stmt 0 view .LVU210 + 751 0000 70B5 push {r4, r5, r6, lr} + 752 .LCFI26: + ARM GAS /tmp/cc77UdtT.s page 21 + + + 753 .cfi_def_cfa_offset 16 + 754 .cfi_offset 4, -16 + 755 .cfi_offset 5, -12 + 756 .cfi_offset 6, -8 + 757 .cfi_offset 14, -4 + 758 0002 8EB0 sub sp, sp, #56 + 759 .LCFI27: + 760 .cfi_def_cfa_offset 72 + 761 0004 0446 mov r4, r0 + 762 0006 0E46 mov r6, r1 + 21:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 763 .loc 1 21 5 is_stmt 1 view .LVU211 + 22:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_SECTOR_ERASE; + 764 .loc 1 22 5 view .LVU212 + 765 0008 6946 mov r1, sp + 766 .LVL42: + 22:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_SECTOR_ERASE; + 767 .loc 1 22 5 is_stmt 0 view .LVU213 + 768 000a FFF7FEFF bl _W25_GetDefaultCommand + 769 .LVL43: + 23:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 770 .loc 1 23 5 is_stmt 1 view .LVU214 + 23:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 771 .loc 1 23 26 is_stmt 0 view .LVU215 + 772 000e 2023 movs r3, #32 + 773 0010 0093 str r3, [sp] + 24:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 774 .loc 1 24 5 is_stmt 1 view .LVU216 + 24:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_NONE; + 775 .loc 1 24 26 is_stmt 0 view .LVU217 + 776 0012 4FF48063 mov r3, #1024 + 777 0016 0793 str r3, [sp, #28] + 25:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 778 .loc 1 25 5 is_stmt 1 view .LVU218 + 25:Core/Src/w25_qspi.c **** sCommand.NbData = 0; + 779 .loc 1 25 23 is_stmt 0 view .LVU219 + 780 0018 0025 movs r5, #0 + 781 001a 0995 str r5, [sp, #36] + 26:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 782 .loc 1 26 5 is_stmt 1 view .LVU220 + 26:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 783 .loc 1 26 21 is_stmt 0 view .LVU221 + 784 001c 0A95 str r5, [sp, #40] + 27:Core/Src/w25_qspi.c **** sCommand.Address = address; + 785 .loc 1 27 5 is_stmt 1 view .LVU222 + 27:Core/Src/w25_qspi.c **** sCommand.Address = address; + 786 .loc 1 27 26 is_stmt 0 view .LVU223 + 787 001e 0595 str r5, [sp, #20] + 28:Core/Src/w25_qspi.c **** + 788 .loc 1 28 5 is_stmt 1 view .LVU224 + 28:Core/Src/w25_qspi.c **** + 789 .loc 1 28 22 is_stmt 0 view .LVU225 + 790 0020 0196 str r6, [sp, #4] + 30:Core/Src/w25_qspi.c **** HAL_QSPI_Command(flash->interface, &sCommand, 1000); + 791 .loc 1 30 5 is_stmt 1 view .LVU226 + 792 0022 2046 mov r0, r4 + 793 0024 FFF7FEFF bl _W25_Write_Enable + ARM GAS /tmp/cc77UdtT.s page 22 + + + 794 .LVL44: + 31:Core/Src/w25_qspi.c **** _W25_Wait_Ready(flash); + 795 .loc 1 31 5 view .LVU227 + 796 0028 4FF47A72 mov r2, #1000 + 797 002c 6946 mov r1, sp + 798 002e 2068 ldr r0, [r4] + 799 0030 FFF7FEFF bl HAL_QSPI_Command + 800 .LVL45: + 32:Core/Src/w25_qspi.c **** + 801 .loc 1 32 5 view .LVU228 + 802 0034 2046 mov r0, r4 + 803 0036 FFF7FEFF bl _W25_Wait_Ready + 804 .LVL46: + 34:Core/Src/w25_qspi.c **** } + 805 .loc 1 34 5 view .LVU229 + 35:Core/Src/w25_qspi.c **** + 806 .loc 1 35 1 is_stmt 0 view .LVU230 + 807 003a 2846 mov r0, r5 + 808 003c 0EB0 add sp, sp, #56 + 809 .LCFI28: + 810 .cfi_def_cfa_offset 16 + 811 @ sp needed + 812 003e 70BD pop {r4, r5, r6, pc} + 35:Core/Src/w25_qspi.c **** + 813 .loc 1 35 1 view .LVU231 + 814 .cfi_endproc + 815 .LFE142: + 817 .section .text.W25_QSPI_Program_Page,"ax",%progbits + 818 .align 1 + 819 .global W25_QSPI_Program_Page + 820 .syntax unified + 821 .thumb + 822 .thumb_func + 823 .fpu fpv5-d16 + 825 W25_QSPI_Program_Page: + 826 .LVL47: + 827 .LFB143: + 37:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 828 .loc 1 37 93 is_stmt 1 view -0 + 829 .cfi_startproc + 830 @ args = 0, pretend = 0, frame = 56 + 831 @ frame_needed = 0, uses_anonymous_args = 0 + 37:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 832 .loc 1 37 93 is_stmt 0 view .LVU233 + 833 0000 70B5 push {r4, r5, r6, lr} + 834 .LCFI29: + 835 .cfi_def_cfa_offset 16 + 836 .cfi_offset 4, -16 + 837 .cfi_offset 5, -12 + 838 .cfi_offset 6, -8 + 839 .cfi_offset 14, -4 + 840 0002 8EB0 sub sp, sp, #56 + 841 .LCFI30: + 842 .cfi_def_cfa_offset 72 + 843 0004 0446 mov r4, r0 + 844 0006 0D46 mov r5, r1 + 845 0008 1646 mov r6, r2 + ARM GAS /tmp/cc77UdtT.s page 23 + + + 38:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 846 .loc 1 38 5 is_stmt 1 view .LVU234 + 39:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_PAGE_PROGRAM; + 847 .loc 1 39 5 view .LVU235 + 848 000a 6946 mov r1, sp + 849 .LVL48: + 39:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_PAGE_PROGRAM; + 850 .loc 1 39 5 is_stmt 0 view .LVU236 + 851 000c FFF7FEFF bl _W25_GetDefaultCommand + 852 .LVL49: + 40:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 853 .loc 1 40 5 is_stmt 1 view .LVU237 + 40:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_1_LINE; + 854 .loc 1 40 26 is_stmt 0 view .LVU238 + 855 0010 0223 movs r3, #2 + 856 0012 0093 str r3, [sp] + 41:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 857 .loc 1 41 5 is_stmt 1 view .LVU239 + 41:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 858 .loc 1 41 26 is_stmt 0 view .LVU240 + 859 0014 4FF48063 mov r3, #1024 + 860 0018 0793 str r3, [sp, #28] + 42:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 861 .loc 1 42 5 is_stmt 1 view .LVU241 + 42:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 862 .loc 1 42 23 is_stmt 0 view .LVU242 + 863 001a 4FF08073 mov r3, #16777216 + 864 001e 0993 str r3, [sp, #36] + 43:Core/Src/w25_qspi.c **** sCommand.NbData = 256; + 865 .loc 1 43 5 is_stmt 1 view .LVU243 + 43:Core/Src/w25_qspi.c **** sCommand.NbData = 256; + 866 .loc 1 43 26 is_stmt 0 view .LVU244 + 867 0020 0023 movs r3, #0 + 868 0022 0593 str r3, [sp, #20] + 44:Core/Src/w25_qspi.c **** sCommand.Address = address; + 869 .loc 1 44 5 is_stmt 1 view .LVU245 + 44:Core/Src/w25_qspi.c **** sCommand.Address = address; + 870 .loc 1 44 21 is_stmt 0 view .LVU246 + 871 0024 4FF48073 mov r3, #256 + 872 0028 0A93 str r3, [sp, #40] + 45:Core/Src/w25_qspi.c **** + 873 .loc 1 45 5 is_stmt 1 view .LVU247 + 45:Core/Src/w25_qspi.c **** + 874 .loc 1 45 22 is_stmt 0 view .LVU248 + 875 002a 0195 str r5, [sp, #4] + 47:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + 876 .loc 1 47 5 is_stmt 1 view .LVU249 + 877 002c 2046 mov r0, r4 + 878 002e FFF7FEFF bl _W25_Write_Enable + 879 .LVL50: + 48:Core/Src/w25_qspi.c **** return HAL_ERROR; + 880 .loc 1 48 5 view .LVU250 + 48:Core/Src/w25_qspi.c **** return HAL_ERROR; + 881 .loc 1 48 8 is_stmt 0 view .LVU251 + 882 0032 4FF47A72 mov r2, #1000 + 883 0036 6946 mov r1, sp + 884 0038 2068 ldr r0, [r4] + ARM GAS /tmp/cc77UdtT.s page 24 + + + 885 003a FFF7FEFF bl HAL_QSPI_Command + 886 .LVL51: + 48:Core/Src/w25_qspi.c **** return HAL_ERROR; + 887 .loc 1 48 7 view .LVU252 + 888 003e 18B1 cbz r0, .L47 + 49:Core/Src/w25_qspi.c **** } + 889 .loc 1 49 16 view .LVU253 + 890 0040 0125 movs r5, #1 + 891 .LVL52: + 892 .L43: + 57:Core/Src/w25_qspi.c **** + 893 .loc 1 57 1 view .LVU254 + 894 0042 2846 mov r0, r5 + 895 0044 0EB0 add sp, sp, #56 + 896 .LCFI31: + 897 .cfi_remember_state + 898 .cfi_def_cfa_offset 16 + 899 @ sp needed + 900 0046 70BD pop {r4, r5, r6, pc} + 901 .LVL53: + 902 .L47: + 903 .LCFI32: + 904 .cfi_restore_state + 51:Core/Src/w25_qspi.c **** return HAL_ERROR; + 905 .loc 1 51 5 is_stmt 1 view .LVU255 + 51:Core/Src/w25_qspi.c **** return HAL_ERROR; + 906 .loc 1 51 8 is_stmt 0 view .LVU256 + 907 0048 4FF47A72 mov r2, #1000 + 908 004c 3146 mov r1, r6 + 909 004e 2068 ldr r0, [r4] + 910 0050 FFF7FEFF bl HAL_QSPI_Transmit + 911 .LVL54: + 51:Core/Src/w25_qspi.c **** return HAL_ERROR; + 912 .loc 1 51 7 view .LVU257 + 913 0054 0546 mov r5, r0 + 914 .LVL55: + 51:Core/Src/w25_qspi.c **** return HAL_ERROR; + 915 .loc 1 51 7 view .LVU258 + 916 0056 08B1 cbz r0, .L48 + 52:Core/Src/w25_qspi.c **** } + 917 .loc 1 52 16 view .LVU259 + 918 0058 0125 movs r5, #1 + 919 005a F2E7 b .L43 + 920 .L48: + 54:Core/Src/w25_qspi.c **** + 921 .loc 1 54 5 is_stmt 1 view .LVU260 + 922 005c 2046 mov r0, r4 + 923 005e FFF7FEFF bl _W25_Wait_Ready + 924 .LVL56: + 56:Core/Src/w25_qspi.c **** } + 925 .loc 1 56 5 view .LVU261 + 56:Core/Src/w25_qspi.c **** } + 926 .loc 1 56 12 is_stmt 0 view .LVU262 + 927 0062 EEE7 b .L43 + 928 .cfi_endproc + 929 .LFE143: + 931 .section .text._W25_QSPI_Identify,"ax",%progbits + ARM GAS /tmp/cc77UdtT.s page 25 + + + 932 .align 1 + 933 .global _W25_QSPI_Identify + 934 .syntax unified + 935 .thumb + 936 .thumb_func + 937 .fpu fpv5-d16 + 939 _W25_QSPI_Identify: + 940 .LVL57: + 941 .LFB152: + 214:Core/Src/w25_qspi.c **** + 215:Core/Src/w25_qspi.c **** HAL_StatusTypeDef _W25_QSPI_Identify(w25_qspi_t *flash) { + 942 .loc 1 215 57 is_stmt 1 view -0 + 943 .cfi_startproc + 944 @ args = 0, pretend = 0, frame = 64 + 945 @ frame_needed = 0, uses_anonymous_args = 0 + 946 .loc 1 215 57 is_stmt 0 view .LVU264 + 947 0000 10B5 push {r4, lr} + 948 .LCFI33: + 949 .cfi_def_cfa_offset 8 + 950 .cfi_offset 4, -8 + 951 .cfi_offset 14, -4 + 952 0002 90B0 sub sp, sp, #64 + 953 .LCFI34: + 954 .cfi_def_cfa_offset 72 + 955 0004 0446 mov r4, r0 + 216:Core/Src/w25_qspi.c **** QSPI_CommandTypeDef sCommand; + 956 .loc 1 216 5 is_stmt 1 view .LVU265 + 217:Core/Src/w25_qspi.c **** uint8_t jedec_id[3]; + 957 .loc 1 217 5 view .LVU266 + 218:Core/Src/w25_qspi.c **** _W25_GetDefaultCommand(flash, &sCommand); + 958 .loc 1 218 5 view .LVU267 + 959 0006 02A9 add r1, sp, #8 + 960 0008 FFF7FEFF bl _W25_GetDefaultCommand + 961 .LVL58: + 219:Core/Src/w25_qspi.c **** sCommand.AddressMode = QSPI_ADDRESS_NONE; + 962 .loc 1 219 5 view .LVU268 + 963 .loc 1 219 26 is_stmt 0 view .LVU269 + 964 000c 0023 movs r3, #0 + 965 000e 0993 str r3, [sp, #36] + 220:Core/Src/w25_qspi.c **** sCommand.DataMode = QSPI_DATA_1_LINE; + 966 .loc 1 220 5 is_stmt 1 view .LVU270 + 967 .loc 1 220 23 is_stmt 0 view .LVU271 + 968 0010 4FF08072 mov r2, #16777216 + 969 0014 0B92 str r2, [sp, #44] + 221:Core/Src/w25_qspi.c **** sCommand.DummyCycles = 0; + 970 .loc 1 221 5 is_stmt 1 view .LVU272 + 971 .loc 1 221 26 is_stmt 0 view .LVU273 + 972 0016 0793 str r3, [sp, #28] + 222:Core/Src/w25_qspi.c **** sCommand.Instruction = W25_CMD_READ_JEDEC_ID; + 973 .loc 1 222 5 is_stmt 1 view .LVU274 + 974 .loc 1 222 26 is_stmt 0 view .LVU275 + 975 0018 9F23 movs r3, #159 + 976 001a 0293 str r3, [sp, #8] + 223:Core/Src/w25_qspi.c **** sCommand.NbData = 3; + 977 .loc 1 223 5 is_stmt 1 view .LVU276 + 978 .loc 1 223 21 is_stmt 0 view .LVU277 + 979 001c 0323 movs r3, #3 + ARM GAS /tmp/cc77UdtT.s page 26 + + + 980 001e 0C93 str r3, [sp, #48] + 224:Core/Src/w25_qspi.c **** + 225:Core/Src/w25_qspi.c **** if(HAL_QSPI_Command(flash->interface, &sCommand, 1000) != HAL_OK) { + 981 .loc 1 225 5 is_stmt 1 view .LVU278 + 982 .loc 1 225 8 is_stmt 0 view .LVU279 + 983 0020 4FF47A72 mov r2, #1000 + 984 0024 02A9 add r1, sp, #8 + 985 0026 2068 ldr r0, [r4] + 986 0028 FFF7FEFF bl HAL_QSPI_Command + 987 .LVL59: + 988 .loc 1 225 7 view .LVU280 + 989 002c 10B1 cbz r0, .L54 + 226:Core/Src/w25_qspi.c **** return HAL_ERROR; + 990 .loc 1 226 16 view .LVU281 + 991 002e 0120 movs r0, #1 + 992 .L50: + 227:Core/Src/w25_qspi.c **** } + 228:Core/Src/w25_qspi.c **** if(HAL_QSPI_Receive(flash->interface, jedec_id, 1000) != HAL_OK) { + 229:Core/Src/w25_qspi.c **** return HAL_ERROR; + 230:Core/Src/w25_qspi.c **** } + 231:Core/Src/w25_qspi.c **** + 232:Core/Src/w25_qspi.c **** flash->manufacturer = jedec_id[0]; + 233:Core/Src/w25_qspi.c **** flash->memory_type = jedec_id[1]; + 234:Core/Src/w25_qspi.c **** flash->capacity = 1U << jedec_id[2]; + 235:Core/Src/w25_qspi.c **** + 236:Core/Src/w25_qspi.c **** return HAL_OK; + 237:Core/Src/w25_qspi.c **** }... + 993 .loc 1 237 1 view .LVU282 + 994 0030 10B0 add sp, sp, #64 + 995 .LCFI35: + 996 .cfi_remember_state + 997 .cfi_def_cfa_offset 8 + 998 @ sp needed + 999 0032 10BD pop {r4, pc} + 1000 .LVL60: + 1001 .L54: + 1002 .LCFI36: + 1003 .cfi_restore_state + 228:Core/Src/w25_qspi.c **** if(HAL_QSPI_Receive(flash->interface, jedec_id, 1000) != HAL_OK) { + 1004 .loc 1 228 5 is_stmt 1 view .LVU283 + 228:Core/Src/w25_qspi.c **** if(HAL_QSPI_Receive(flash->interface, jedec_id, 1000) != HAL_OK) { + 1005 .loc 1 228 8 is_stmt 0 view .LVU284 + 1006 0034 4FF47A72 mov r2, #1000 + 1007 0038 01A9 add r1, sp, #4 + 1008 003a 2068 ldr r0, [r4] + 1009 003c FFF7FEFF bl HAL_QSPI_Receive + 1010 .LVL61: + 228:Core/Src/w25_qspi.c **** if(HAL_QSPI_Receive(flash->interface, jedec_id, 1000) != HAL_OK) { + 1011 .loc 1 228 7 view .LVU285 + 1012 0040 58B9 cbnz r0, .L52 + 232:Core/Src/w25_qspi.c **** flash->manufacturer = jedec_id[0]; + 1013 .loc 1 232 5 is_stmt 1 view .LVU286 + 232:Core/Src/w25_qspi.c **** flash->manufacturer = jedec_id[0]; + 1014 .loc 1 232 35 is_stmt 0 view .LVU287 + 1015 0042 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 232:Core/Src/w25_qspi.c **** flash->manufacturer = jedec_id[0]; + 1016 .loc 1 232 25 view .LVU288 + ARM GAS /tmp/cc77UdtT.s page 27 + + + 1017 0046 2373 strb r3, [r4, #12] + 233:Core/Src/w25_qspi.c **** flash->memory_type = jedec_id[1]; + 1018 .loc 1 233 5 is_stmt 1 view .LVU289 + 233:Core/Src/w25_qspi.c **** flash->memory_type = jedec_id[1]; + 1019 .loc 1 233 34 is_stmt 0 view .LVU290 + 1020 0048 9DF80530 ldrb r3, [sp, #5] @ zero_extendqisi2 + 233:Core/Src/w25_qspi.c **** flash->memory_type = jedec_id[1]; + 1021 .loc 1 233 24 view .LVU291 + 1022 004c 6373 strb r3, [r4, #13] + 234:Core/Src/w25_qspi.c **** flash->capacity = 1U << jedec_id[2]; + 1023 .loc 1 234 5 is_stmt 1 view .LVU292 + 234:Core/Src/w25_qspi.c **** flash->capacity = 1U << jedec_id[2]; + 1024 .loc 1 234 37 is_stmt 0 view .LVU293 + 1025 004e 9DF80620 ldrb r2, [sp, #6] @ zero_extendqisi2 + 234:Core/Src/w25_qspi.c **** flash->capacity = 1U << jedec_id[2]; + 1026 .loc 1 234 26 view .LVU294 + 1027 0052 0123 movs r3, #1 + 1028 0054 9340 lsls r3, r3, r2 + 234:Core/Src/w25_qspi.c **** flash->capacity = 1U << jedec_id[2]; + 1029 .loc 1 234 21 view .LVU295 + 1030 0056 A360 str r3, [r4, #8] + 236:Core/Src/w25_qspi.c **** return HAL_OK; + 1031 .loc 1 236 5 is_stmt 1 view .LVU296 + 236:Core/Src/w25_qspi.c **** return HAL_OK; + 1032 .loc 1 236 12 is_stmt 0 view .LVU297 + 1033 0058 EAE7 b .L50 + 1034 .L52: + 229:Core/Src/w25_qspi.c **** return HAL_ERROR; + 1035 .loc 1 229 16 view .LVU298 + 1036 005a 0120 movs r0, #1 + 1037 005c E8E7 b .L50 + 1038 .cfi_endproc + 1039 .LFE152: + 1041 .section .text.W25_QSPI_Init,"ax",%progbits + 1042 .align 1 + 1043 .global W25_QSPI_Init + 1044 .syntax unified + 1045 .thumb + 1046 .thumb_func + 1047 .fpu fpv5-d16 + 1049 W25_QSPI_Init: + 1050 .LVL62: + 1051 .LFB141: + 16:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_Init(w25_qspi_t *flash) { + 1052 .loc 1 16 52 is_stmt 1 view -0 + 1053 .cfi_startproc + 1054 @ args = 0, pretend = 0, frame = 0 + 1055 @ frame_needed = 0, uses_anonymous_args = 0 + 16:Core/Src/w25_qspi.c **** HAL_StatusTypeDef W25_QSPI_Init(w25_qspi_t *flash) { + 1056 .loc 1 16 52 is_stmt 0 view .LVU300 + 1057 0000 08B5 push {r3, lr} + 1058 .LCFI37: + 1059 .cfi_def_cfa_offset 8 + 1060 .cfi_offset 3, -8 + 1061 .cfi_offset 14, -4 + 17:Core/Src/w25_qspi.c **** return _W25_QSPI_Identify(flash); + 1062 .loc 1 17 5 is_stmt 1 view .LVU301 + ARM GAS /tmp/cc77UdtT.s page 28 + + + 17:Core/Src/w25_qspi.c **** return _W25_QSPI_Identify(flash); + 1063 .loc 1 17 12 is_stmt 0 view .LVU302 + 1064 0002 FFF7FEFF bl _W25_QSPI_Identify + 1065 .LVL63: + 18:Core/Src/w25_qspi.c **** } + 1066 .loc 1 18 1 view .LVU303 + 1067 0006 08BD pop {r3, pc} + 1068 .cfi_endproc + 1069 .LFE141: + 1071 .text + 1072 .Letext0: + 1073 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h" + 1074 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h" + 1075 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h" + 1076 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" + 1077 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h" + 1078 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h" + 1079 .file 8 "Core/Inc/w25_qspi.h" + ARM GAS /tmp/cc77UdtT.s page 29 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 w25_qspi.c + /tmp/cc77UdtT.s:17 .text._W25_GetDefaultCommand:0000000000000000 $t + /tmp/cc77UdtT.s:25 .text._W25_GetDefaultCommand:0000000000000000 _W25_GetDefaultCommand + /tmp/cc77UdtT.s:79 .text.W25_QSPI_Read:0000000000000000 $t + /tmp/cc77UdtT.s:86 .text.W25_QSPI_Read:0000000000000000 W25_QSPI_Read + /tmp/cc77UdtT.s:178 .text.W25_QPI_Mode:0000000000000000 $t + /tmp/cc77UdtT.s:185 .text.W25_QPI_Mode:0000000000000000 W25_QPI_Mode + /tmp/cc77UdtT.s:263 .text.W25_QPI_ReadParams:0000000000000000 $t + /tmp/cc77UdtT.s:270 .text.W25_QPI_ReadParams:0000000000000000 W25_QPI_ReadParams + /tmp/cc77UdtT.s:363 .text._W25_Write_Enable:0000000000000000 $t + /tmp/cc77UdtT.s:370 .text._W25_Write_Enable:0000000000000000 _W25_Write_Enable + /tmp/cc77UdtT.s:429 .text._W25_Write_Volatile_Enable:0000000000000000 $t + /tmp/cc77UdtT.s:436 .text._W25_Write_Volatile_Enable:0000000000000000 _W25_Write_Volatile_Enable + /tmp/cc77UdtT.s:495 .text.W25_QSPI_QuadEnable:0000000000000000 $t + /tmp/cc77UdtT.s:502 .text.W25_QSPI_QuadEnable:0000000000000000 W25_QSPI_QuadEnable + /tmp/cc77UdtT.s:637 .text._W25_Wait_Ready:0000000000000000 $t + /tmp/cc77UdtT.s:644 .text._W25_Wait_Ready:0000000000000000 _W25_Wait_Ready + /tmp/cc77UdtT.s:736 .text.W25_QSPI_Erase_Sector:0000000000000000 $t + /tmp/cc77UdtT.s:743 .text.W25_QSPI_Erase_Sector:0000000000000000 W25_QSPI_Erase_Sector + /tmp/cc77UdtT.s:818 .text.W25_QSPI_Program_Page:0000000000000000 $t + /tmp/cc77UdtT.s:825 .text.W25_QSPI_Program_Page:0000000000000000 W25_QSPI_Program_Page + /tmp/cc77UdtT.s:932 .text._W25_QSPI_Identify:0000000000000000 $t + /tmp/cc77UdtT.s:939 .text._W25_QSPI_Identify:0000000000000000 _W25_QSPI_Identify + /tmp/cc77UdtT.s:1042 .text.W25_QSPI_Init:0000000000000000 $t + /tmp/cc77UdtT.s:1049 .text.W25_QSPI_Init:0000000000000000 W25_QSPI_Init + +UNDEFINED SYMBOLS +HAL_QSPI_Command +HAL_QSPI_Receive +HAL_QSPI_Transmit +HAL_QSPI_AutoPolling_IT diff --git a/build/w25_qspi.o b/build/w25_qspi.o new file mode 100644 index 0000000..c111975 Binary files /dev/null and b/build/w25_qspi.o differ diff --git a/startup/startup_stm32h750xx.s b/startup_stm32h750xx.s similarity index 97% rename from startup/startup_stm32h750xx.s rename to startup_stm32h750xx.s index eee67da..fae2960 100644 --- a/startup/startup_stm32h750xx.s +++ b/startup_stm32h750xx.s @@ -61,6 +61,9 @@ defined in linker script */ Reset_Handler: ldr sp, =_estack /* set stack pointer */ +/* Call the clock system intitialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit @@ -89,8 +92,6 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/